2 * Copyright (c) 2015 Stanislav Galabov.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef __RT305X_PCIREG_H__
29 #define __RT305X_PCIREG_H__
31 #define RT305X_PCI_NIRQS 1
32 #define RT305X_PCI_BASESLOT 0
34 #define RT305X_PCI_PCICFG 0x0000
35 #define RT305X_PCI_PCIINT 0x0008
36 #define RT305X_PCI_PCIENA 0x000C
37 #define RT305X_PCI_CFGADDR 0x0020
38 #define RT305X_PCI_CFGDATA 0x0024
39 #define RT305X_PCI_MEMBASE 0x0028
40 #define RT305X_PCI_IOBASE 0x002C
41 #define RT305X_PCI_PHY0_CFG 0x0090
43 #define RT305X_PCI_PCIE0_BAR0SETUP 0x2010
44 #define RT305X_PCI_PCIE0_BAR1SETUP 0x2014
45 #define RT305X_PCI_PCIE0_IMBASEBAR0 0x2018
46 #define RT305X_PCI_PCIE0_ID 0x2030
47 #define RT305X_PCI_PCIE0_CLASS 0x2034
48 #define RT305X_PCI_PCIE0_SUBID 0x2038
49 #define RT305X_PCI_PCIE0_STATUS 0x2050
50 #define RT305X_PCI_PCIE0_DLECR 0x2060
51 #define RT305X_PCI_PCIE0_ECRC 0x2064
53 #define RT305X_PCIE0_IRQ 20
54 #define RT305X_PCIE1_IRQ 21
55 #define RT305X_PCIE2_IRQ 22
57 #define RT305X_PCI_INTR_PIN 2
59 #define PCI_MIN_IO_ALLOC 4
60 #define PCI_MIN_MEM_ALLOC 16
61 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
63 #define RT_WRITE32(sc, off, val) \
64 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
65 #define RT_WRITE16(sc, off, val) \
66 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
67 #define RT_WRITE8(sc, off, val) \
68 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (off), (val))
69 #define RT_READ32(sc, off) \
70 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (off))
71 #define RT_READ16(sc, off) \
72 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (off))
73 #define RT_READ8(sc, off) \
74 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (off))
76 #endif /* __RT305X_PCIREG_H__ */