2 * Copyright (c) 2007 Bruce M. Simpson.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/systm.h>
37 #include <sys/imgact.h>
44 #include <sys/ucontext.h>
47 #include <sys/ptrace.h>
48 #include <sys/reboot.h>
49 #include <sys/signalvar.h>
50 #include <sys/sysent.h>
51 #include <sys/sysproto.h>
53 #include <sys/timetc.h>
56 #include <vm/vm_object.h>
57 #include <vm/vm_page.h>
59 #include <machine/cache.h>
60 #include <machine/clock.h>
61 #include <machine/cpu.h>
62 #include <machine/cpuinfo.h>
63 #include <machine/cpufunc.h>
64 #include <machine/cpuregs.h>
65 #include <machine/hwfunc.h>
66 #include <machine/intr_machdep.h>
67 #include <machine/locore.h>
68 #include <machine/md_var.h>
69 #include <machine/pte.h>
70 #include <machine/sigframe.h>
71 #include <machine/trap.h>
72 #include <machine/vmparam.h>
76 #include <machine/smp.h>
80 #include <dev/cfe/cfe_api.h>
87 #error KDB must be enabled in order for DDB to work!
92 extern void cfe_env_init(void);
98 extern char MipsTLBMiss[], MipsTLBMissEnd[];
103 /* Nothing special */
107 sb_intr_init(int cpuid)
112 * Disable all sources to the interrupt mapper and setup the mapping
113 * between an interrupt source and the mips hard interrupt number.
115 for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) {
116 intrnum = sb_route_intsrc(intsrc);
117 sb_disable_intsrc(cpuid, intsrc);
118 sb_write_intmap(cpuid, intsrc, intrnum);
121 * Set up the mailbox interrupt mapping.
123 * The mailbox interrupt is "special" in that it is not shared
124 * with any other interrupt source.
126 if (intsrc == INTSRC_MAILBOX3) {
127 intrnum = platform_ipi_intrnum();
128 sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
129 sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
138 int i, j, cfe_mem_idx, tmp;
145 TUNABLE_INT_FETCH("boothowto", &boothowto);
147 if (boothowto & RB_VERBOSE)
155 TUNABLE_INT_FETCH("hw.physmem", &tmp);
156 maxmem = (uint64_t)tmp * 1024;
160 * If we used vm_paddr_t consistently in pmap, etc., we could
161 * use 64-bit page numbers on !n64 systems, too, like i386
164 #if !defined(__mips_n64)
165 if (maxmem == 0 || maxmem > 0xffffffff)
171 * Query DRAM memory map from CFE.
175 for (i = 0; i < 10; i += 2) {
177 uint64_t addr, len, type;
179 result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type);
181 phys_avail[i] = phys_avail[i + 1] = 0;
185 KASSERT(type == CFE_MI_AVAILABLE,
186 ("CFE DRAM region is not available?"));
189 printf("cfe_enummem: 0x%016jx/%ju.\n", addr, len);
192 if (addr >= maxmem) {
193 printf("Ignoring %ju bytes of memory at 0x%jx "
194 "that is above maxmem %dMB\n",
196 (int)(maxmem / (1024 * 1024)));
200 if (addr + len > maxmem) {
201 printf("Ignoring %ju bytes of memory "
202 "that is above maxmem %dMB\n",
203 (addr + len) - maxmem,
204 (int)(maxmem / (1024 * 1024)));
209 phys_avail[i] = addr;
210 if (i == 0 && addr == 0) {
212 * If this is the first physical memory segment probed
213 * from CFE, omit the region at the start of physical
214 * memory where the kernel has been loaded.
216 phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
218 phys_avail[i + 1] = addr + len;
222 realmem = btoc(physmem);
225 for (j = 0; j < i; j++)
226 dump_avail[j] = phys_avail[j];
231 init_param2(physmem);
235 * Sibyte has a L1 data cache coherent with DMA. This includes
236 * on-chip network interfaces as well as PCI/HyperTransport bus
239 cpuinfo.cache_coherent_dma = TRUE;
243 * The kernel is running in 32-bit mode but the CFE is running in
244 * 64-bit mode. So the SR_KX bit in the status register is turned
245 * on by the CFE every time we call into it - for e.g. CFE_CONSOLE.
247 * This means that if get a TLB miss for any address above 0xc0000000
248 * and the SR_KX bit is set then we will end up in the XTLB exception
251 * For now work around this by copying the TLB exception handling
252 * code to the XTLB exception vector.
255 bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
256 MipsTLBMissEnd - MipsTLBMiss);
258 mips_icache_sync_all();
259 mips_dcache_wbinv_all();
268 if (boothowto & RB_KDB)
269 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
279 * XXX flush data caches
285 kseg0_map_coherent(void)
288 const int CFG_K0_COHERENT = 5;
290 config = mips_rd_config();
291 config &= ~MIPS_CONFIG_K0_MASK;
292 config |= CFG_K0_COHERENT;
293 mips_wr_config(config);
298 platform_ipi_send(int cpuid)
300 KASSERT(cpuid == 0 || cpuid == 1,
301 ("platform_ipi_send: invalid cpuid %d", cpuid));
303 sb_set_mailbox(cpuid, 1ULL);
307 platform_ipi_clear(void)
311 cpuid = PCPU_GET(cpuid);
312 sb_clear_mailbox(cpuid, 1ULL);
316 platform_ipi_intrnum(void)
323 platform_smp_topo(void)
326 return (smp_topo_none());
330 platform_init_ap(int cpuid)
332 int ipi_int_mask, clock_int_mask;
334 KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
337 * Make sure that kseg0 is mapped cacheable-coherent
339 kseg0_map_coherent();
344 * Unmask the clock and ipi interrupts.
346 clock_int_mask = hard_int_mask(5);
347 ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
348 set_intr_mask(ipi_int_mask | clock_int_mask);
352 platform_start_ap(int cpuid)
357 if ((error = cfe_cpu_start(cpuid, mpentry, 0, 0, 0))) {
358 printf("cfe_cpu_start error: %d\n", error);
370 sb_get_timecount(struct timecounter *tc)
373 return ((u_int)sb_zbbus_cycle_count());
377 sb_timecounter_init(void)
379 static struct timecounter sb_timecounter = {
384 "sibyte_zbbus_counter",
389 * The ZBbus cycle counter runs at half the cpu frequency.
391 sb_timecounter.tc_frequency = sb_cpu_speed() / 2;
392 platform_timecounter = &sb_timecounter;
396 platform_start(__register_t a0, __register_t a1, __register_t a2,
400 * Make sure that kseg0 is mapped cacheable-coherent
402 kseg0_map_coherent();
404 /* clear the BSS and SBSS segments */
405 memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata);
406 mips_postboot_fixup();
409 sb_timecounter_init();
411 /* Initialize pcpu stuff */
416 * Initialize CFE firmware trampolines before
417 * we initialize the low-level console.
419 * CFE passes the following values in registers:
420 * a0: firmware handle
421 * a2: firmware entry point
422 * a3: entry point seal
424 if (a3 == CFE_EPTSEAL)
431 mips_timer_init_params(sb_cpu_speed(), 0);