3 CXGB = ${.CURDIR}/../../dev/cxgb
4 .PATH: ${CXGB} ${CXGB}/common ${CXGB}/sys
7 SRCS= cxgb_mc5.c cxgb_vsc8211.c cxgb_ael1002.c cxgb_mv88e1xxx.c
8 SRCS+= cxgb_xgmac.c cxgb_vsc7323.c cxgb_t3_hw.c cxgb_main.c
9 SRCS+= cxgb_sge.c cxgb_lro.c cxgb_offload.c cxgb_l2t.c
10 SRCS+= device_if.h bus_if.h pci_if.h opt_zero.h
13 CFLAGS+= -DCONFIG_CHELSIO_T3_CORE -g -DCONFIG_DEFINED -DDEFAULT_JUMBO -I${CXGB}
14 #CFLAGS+= -DINVARIANT_SUPPORT -DINVARIANTS
16 .if ${MACHINE_ARCH} != "ia64"
17 # ld is broken on ia64
18 t3fw-4.5.0.bin: ${CXGB}/t3fw-4.5.0.bin.gz.uu
19 uudecode -p < ${CXGB}/t3fw-4.5.0.bin.gz.uu \
20 | gzip -dc > ${.TARGET}
22 FIRMWS= t3fw-4.5.0.bin:t3fw450
23 CLEANFILES+= t3fw-4.5.0.bin
25 t3b_protocol_sram-1.1.0.bin: ${CXGB}/t3b_protocol_sram-1.1.0.bin.gz.uu
26 uudecode -p < ${CXGB}/t3b_protocol_sram-1.1.0.bin.gz.uu \
27 | gzip -dc > ${.TARGET}
29 FIRMWS+= t3b_protocol_sram-1.1.0.bin:t3bps110
30 CLEANFILES+= t3b_protocol_sram-1.1.0.bin
32 t3b_tp_eeprom-1.1.0.bin: ${CXGB}/t3b_tp_eeprom-1.1.0.bin.gz.uu
33 uudecode -p < ${CXGB}/t3b_tp_eeprom-1.1.0.bin.gz.uu \
34 | gzip -dc > ${.TARGET}
36 FIRMWS+= t3b_tp_eeprom-1.1.0.bin:t3btpe110
37 CLEANFILES+= t3b_tp_eeprom-1.1.0.bin
43 .include <bsd.kmod.mk>