2 * Copyright (c) 2014-2016, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
63 #include <netinet/in.h>
64 #include <netinet/in_pcb.h>
65 #include <netinet/tcp_lro.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/if_ether.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
78 #include <dev/led/led.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pci_private.h>
83 #include <net/iflib.h>
87 #if defined(__i386__) || defined(__amd64__)
88 #include <sys/memdesc.h>
89 #include <machine/bus.h>
90 #include <machine/md_var.h>
91 #include <machine/specialreg.h>
92 #include <x86/include/busdma_impl.h>
93 #include <x86/iommu/busdma_dmar.h>
98 * enable accounting of every mbuf as it comes in to and goes out of iflib's software descriptor references
100 #define MEMORY_LOGGING 0
102 * Enable mbuf vectors for compressing long mbuf chains
107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
108 * we prefetch needs to be determined by the time spent in m_free vis a vis
109 * the cost of a prefetch. This will of course vary based on the workload:
110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
111 * is quite expensive, thus suggesting very little prefetch.
112 * - small packet forwarding which is just returning a single mbuf to
113 * UMA will typically be very fast vis a vis the cost of a memory
120 * - private structures
121 * - iflib private utility functions
123 * - vlan registry and other exported functions
124 * - iflib public core functions
128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 typedef struct iflib_txq *iflib_txq_t;
133 typedef struct iflib_rxq *iflib_rxq_t;
135 typedef struct iflib_fl *iflib_fl_t;
137 typedef struct iflib_filter_info {
138 driver_filter_t *ifi_filter;
139 void *ifi_filter_arg;
140 struct grouptask *ifi_task;
141 } *iflib_filter_info_t;
146 * Pointer to hardware driver's softc
153 if_shared_ctx_t ifc_sctx;
154 struct if_softc_ctx ifc_softc_ctx;
158 uint16_t ifc_nhwtxqs;
159 uint16_t ifc_nhwrxqs;
161 iflib_txq_t ifc_txqs;
162 iflib_rxq_t ifc_rxqs;
163 uint32_t ifc_if_flags;
165 uint32_t ifc_max_fl_buf_size;
170 int ifc_pause_frames;
171 int ifc_watchdog_events;
172 struct cdev *ifc_led_dev;
173 struct resource *ifc_msix_mem;
175 struct if_irq ifc_legacy_irq;
176 struct grouptask ifc_admin_task;
177 struct grouptask ifc_vflr_task;
178 struct iflib_filter_info ifc_filter_info;
179 struct ifmedia ifc_media;
181 struct sysctl_oid *ifc_sysctl_node;
182 uint16_t ifc_sysctl_ntxqs;
183 uint16_t ifc_sysctl_nrxqs;
184 uint16_t ifc_sysctl_qs_eq_override;
186 uint16_t ifc_sysctl_ntxds[8];
187 uint16_t ifc_sysctl_nrxds[8];
188 struct if_txrx ifc_txrx;
189 #define isc_txd_encap ifc_txrx.ift_txd_encap
190 #define isc_txd_flush ifc_txrx.ift_txd_flush
191 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
192 #define isc_rxd_available ifc_txrx.ift_rxd_available
193 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
194 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
195 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
196 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
198 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
199 eventhandler_tag ifc_vlan_attach_event;
200 eventhandler_tag ifc_vlan_detach_event;
201 uint8_t ifc_mac[ETHER_ADDR_LEN];
202 char ifc_mtx_name[16];
207 iflib_get_softc(if_ctx_t ctx)
210 return (ctx->ifc_softc);
214 iflib_get_dev(if_ctx_t ctx)
217 return (ctx->ifc_dev);
221 iflib_get_ifp(if_ctx_t ctx)
224 return (ctx->ifc_ifp);
228 iflib_get_media(if_ctx_t ctx)
231 return (&ctx->ifc_media);
235 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
238 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
242 iflib_get_softc_ctx(if_ctx_t ctx)
245 return (&ctx->ifc_softc_ctx);
249 iflib_get_sctx(if_ctx_t ctx)
252 return (ctx->ifc_sctx);
255 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
257 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
258 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
260 #define RX_SW_DESC_MAP_CREATED (1 << 0)
261 #define TX_SW_DESC_MAP_CREATED (1 << 1)
262 #define RX_SW_DESC_INUSE (1 << 3)
263 #define TX_SW_DESC_MAPPED (1 << 4)
265 typedef struct iflib_sw_rx_desc {
266 bus_dmamap_t ifsd_map; /* bus_dma map for packet */
267 struct mbuf *ifsd_m; /* rx: uninitialized mbuf */
268 caddr_t ifsd_cl; /* direct cluster pointer for rx */
272 typedef struct iflib_sw_tx_desc_val {
273 bus_dmamap_t ifsd_map; /* bus_dma map for packet */
274 struct mbuf *ifsd_m; /* pkthdr mbuf */
278 typedef struct iflib_sw_tx_desc_array {
279 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
280 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 } iflib_txsd_array_t;
285 /* magic number that should be high enough for any hardware */
286 #define IFLIB_MAX_TX_SEGS 128
287 #define IFLIB_MAX_RX_SEGS 32
288 #define IFLIB_RX_COPY_THRESH 128
289 #define IFLIB_MAX_RX_REFRESH 32
290 #define IFLIB_QUEUE_IDLE 0
291 #define IFLIB_QUEUE_HUNG 1
292 #define IFLIB_QUEUE_WORKING 2
294 /* this should really scale with ring size - 32 is a fairly arbitrary value for this */
295 #define TX_BATCH_SIZE 16
297 #define IFLIB_RESTART_BUDGET 8
299 #define IFC_LEGACY 0x01
300 #define IFC_QFLUSH 0x02
301 #define IFC_MULTISEG 0x04
302 #define IFC_DMAR 0x08
303 #define IFC_SC_ALLOCATED 0x10
305 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
306 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
307 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
311 uint16_t ift_cidx_processed;
314 uint8_t ift_db_pending;
315 uint8_t ift_db_pending_queued;
316 uint8_t ift_npending;
317 uint8_t ift_br_offset;
319 uint64_t ift_processed;
320 uint64_t ift_cleaned;
322 uint64_t ift_enqueued;
323 uint64_t ift_dequeued;
325 uint64_t ift_no_tx_dma_setup;
326 uint64_t ift_no_desc_avail;
327 uint64_t ift_mbuf_defrag_failed;
328 uint64_t ift_mbuf_defrag;
329 uint64_t ift_map_failed;
330 uint64_t ift_txd_encap_efbig;
331 uint64_t ift_pullups;
334 struct mtx ift_db_mtx;
336 /* constant values */
338 struct ifmp_ring **ift_br;
339 struct grouptask ift_task;
342 struct callout ift_timer;
343 struct callout ift_db_check;
345 iflib_txsd_array_t ift_sds;
350 int ift_watchdog_time;
351 struct iflib_filter_info ift_filter_info;
352 bus_dma_tag_t ift_desc_tag;
353 bus_dma_tag_t ift_tso_desc_tag;
354 iflib_dma_info_t ift_ifdi;
355 #define MTX_NAME_LEN 16
356 char ift_mtx_name[MTX_NAME_LEN];
357 char ift_db_mtx_name[MTX_NAME_LEN];
358 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
359 } __aligned(CACHE_LINE_SIZE);
364 uint16_t ifl_credits;
367 uint64_t ifl_m_enqueued;
368 uint64_t ifl_m_dequeued;
369 uint64_t ifl_cl_enqueued;
370 uint64_t ifl_cl_dequeued;
376 uint16_t ifl_buf_size;
379 iflib_rxsd_t ifl_sds;
382 bus_dma_tag_t ifl_desc_tag;
383 iflib_dma_info_t ifl_ifdi;
384 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
385 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
386 } __aligned(CACHE_LINE_SIZE);
389 get_inuse(int size, int cidx, int pidx, int gen)
395 else if (pidx < cidx)
396 used = size - cidx + pidx;
397 else if (gen == 0 && pidx == cidx)
399 else if (gen == 1 && pidx == cidx)
407 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
409 #define IDXDIFF(head, tail, wrap) \
410 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
413 /* If there is a separate completion queue -
414 * these are the cq cidx and pidx. Otherwise
418 uint16_t ifr_cq_cidx;
419 uint16_t ifr_cq_pidx;
421 uint8_t ifr_fl_offset;
427 uint8_t ifr_lro_enabled;
429 struct lro_ctrl ifr_lc;
430 struct grouptask ifr_task;
431 struct iflib_filter_info ifr_filter_info;
432 iflib_dma_info_t ifr_ifdi;
433 /* dynamically allocate if any drivers need a value substantially larger than this */
434 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
435 } __aligned(CACHE_LINE_SIZE);
438 * Only allow a single packet to take up most 1/nth of the tx ring
440 #define MAX_SINGLE_PACKET_FRACTION 12
441 #define IF_BAD_DMA (bus_addr_t)-1
443 static int enable_msix = 1;
445 #define mtx_held(m) (((m)->mtx_lock & ~MTX_FLAGMASK) != (uintptr_t)0)
449 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
451 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
453 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
454 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
455 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
458 #define TXDB_LOCK_INIT(txq) mtx_init(&(txq)->ift_db_mtx, (txq)->ift_db_mtx_name, NULL, MTX_DEF)
459 #define TXDB_TRYLOCK(txq) mtx_trylock(&(txq)->ift_db_mtx)
460 #define TXDB_LOCK(txq) mtx_lock(&(txq)->ift_db_mtx)
461 #define TXDB_UNLOCK(txq) mtx_unlock(&(txq)->ift_db_mtx)
462 #define TXDB_LOCK_DESTROY(txq) mtx_destroy(&(txq)->ift_db_mtx)
464 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
465 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
468 /* Our boot-time initialization hook */
469 static int iflib_module_event_handler(module_t, int, void *);
471 static moduledata_t iflib_moduledata = {
473 iflib_module_event_handler,
477 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
478 MODULE_VERSION(iflib, 1);
480 MODULE_DEPEND(iflib, pci, 1, 1, 1);
481 MODULE_DEPEND(iflib, ether, 1, 1, 1);
483 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
485 #ifndef IFLIB_DEBUG_COUNTERS
487 #define IFLIB_DEBUG_COUNTERS 1
489 #define IFLIB_DEBUG_COUNTERS 0
490 #endif /* !INVARIANTS */
493 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
494 "iflib driver parameters");
497 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
499 static int iflib_min_tx_latency = 0;
501 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
502 &iflib_min_tx_latency, 0, "minimize transmit latency at the possibel expense of throughput");
505 #if IFLIB_DEBUG_COUNTERS
507 static int iflib_tx_seen;
508 static int iflib_tx_sent;
509 static int iflib_tx_encap;
510 static int iflib_rx_allocs;
511 static int iflib_fl_refills;
512 static int iflib_fl_refills_large;
513 static int iflib_tx_frees;
515 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
516 &iflib_tx_seen, 0, "# tx mbufs seen");
517 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
518 &iflib_tx_sent, 0, "# tx mbufs sent");
519 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
520 &iflib_tx_encap, 0, "# tx mbufs encapped");
521 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
522 &iflib_tx_frees, 0, "# tx frees");
523 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
524 &iflib_rx_allocs, 0, "# rx allocations");
525 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
526 &iflib_fl_refills, 0, "# refills");
527 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
528 &iflib_fl_refills_large, 0, "# large refills");
531 static int iflib_txq_drain_flushing;
532 static int iflib_txq_drain_oactive;
533 static int iflib_txq_drain_notready;
534 static int iflib_txq_drain_encapfail;
536 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
537 &iflib_txq_drain_flushing, 0, "# drain flushes");
538 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
539 &iflib_txq_drain_oactive, 0, "# drain oactives");
540 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
541 &iflib_txq_drain_notready, 0, "# drain notready");
542 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
543 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
546 static int iflib_encap_load_mbuf_fail;
547 static int iflib_encap_txq_avail_fail;
548 static int iflib_encap_txd_encap_fail;
550 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
551 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
552 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
553 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
554 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
555 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
557 static int iflib_task_fn_rxs;
558 static int iflib_rx_intr_enables;
559 static int iflib_fast_intrs;
560 static int iflib_intr_link;
561 static int iflib_intr_msix;
562 static int iflib_rx_unavail;
563 static int iflib_rx_ctx_inactive;
564 static int iflib_rx_zero_len;
565 static int iflib_rx_if_input;
566 static int iflib_rx_mbuf_null;
567 static int iflib_rxd_flush;
569 static int iflib_verbose_debug;
571 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
572 &iflib_intr_link, 0, "# intr link calls");
573 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
574 &iflib_intr_msix, 0, "# intr msix calls");
575 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
576 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
577 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
578 &iflib_rx_intr_enables, 0, "# rx intr enables");
579 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
580 &iflib_fast_intrs, 0, "# fast_intr calls");
581 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
582 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
583 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
584 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
585 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
586 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
587 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
588 &iflib_rx_if_input, 0, "# times rxeof called if_input");
589 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
590 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
591 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
592 &iflib_rxd_flush, 0, "# times rxd_flush called");
593 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
594 &iflib_verbose_debug, 0, "enable verbose debugging");
596 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
599 #define DBG_COUNTER_INC(name)
605 #define IFLIB_DEBUG 0
607 static void iflib_tx_structures_free(if_ctx_t ctx);
608 static void iflib_rx_structures_free(if_ctx_t ctx);
609 static int iflib_queues_alloc(if_ctx_t ctx);
610 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
611 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget);
612 static int iflib_qset_structures_setup(if_ctx_t ctx);
613 static int iflib_msix_init(if_ctx_t ctx);
614 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
615 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
616 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
617 static int iflib_register(if_ctx_t);
618 static void iflib_init_locked(if_ctx_t ctx);
619 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
620 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
624 #include <sys/selinfo.h>
625 #include <net/netmap.h>
626 #include <dev/netmap/netmap_kern.h>
628 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
631 * device-specific sysctl variables:
633 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
634 * During regular operations the CRC is stripped, but on some
635 * hardware reception of frames not multiple of 64 is slower,
636 * so using crcstrip=0 helps in benchmarks.
638 * iflib_rx_miss, iflib_rx_miss_bufs:
639 * count packets that might be missed due to lost interrupts.
641 SYSCTL_DECL(_dev_netmap);
643 * The xl driver by default strips CRCs and we do not override it.
646 int iflib_crcstrip = 1;
647 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
648 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
650 int iflib_rx_miss, iflib_rx_miss_bufs;
651 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
652 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
653 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
654 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
657 * Register/unregister. We are already under netmap lock.
658 * Only called on the first register or the last unregister.
661 iflib_netmap_register(struct netmap_adapter *na, int onoff)
663 struct ifnet *ifp = na->ifp;
664 if_ctx_t ctx = ifp->if_softc;
667 IFDI_INTR_DISABLE(ctx);
669 /* Tell the stack that the interface is no longer active */
670 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
673 IFDI_CRCSTRIP_SET(ctx, onoff);
675 /* enable or disable flags and callbacks in na and ifp */
677 nm_set_native_flags(na);
679 nm_clear_native_flags(na);
682 IFDI_CRCSTRIP_SET(ctx, onoff); // XXX why twice ?
684 return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1);
688 * Reconcile kernel and user view of the transmit ring.
690 * All information is in the kring.
691 * Userspace wants to send packets up to the one before kring->rhead,
692 * kernel knows kring->nr_hwcur is the first unsent packet.
694 * Here we push packets out (as many as possible), and possibly
695 * reclaim buffers from previously completed transmission.
697 * The caller (netmap) guarantees that there is only one instance
698 * running at any time. Any interference with other driver
699 * methods should be handled by the individual drivers.
702 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
704 struct netmap_adapter *na = kring->na;
705 struct ifnet *ifp = na->ifp;
706 struct netmap_ring *ring = kring->ring;
707 u_int nm_i; /* index into the netmap ring */
708 u_int nic_i; /* index into the NIC ring */
710 u_int const lim = kring->nkr_num_slots - 1;
711 u_int const head = kring->rhead;
712 struct if_pkt_info pi;
715 * interrupts on every tx packet are expensive so request
716 * them every half ring, or where NS_REPORT is set
718 u_int report_frequency = kring->nkr_num_slots >> 1;
719 /* device-specific */
720 if_ctx_t ctx = ifp->if_softc;
721 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
723 pi.ipi_segs = txq->ift_segs;
724 pi.ipi_qsidx = kring->ring_id;
727 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
728 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
732 * First part: process new packets to send.
733 * nm_i is the current index in the netmap ring,
734 * nic_i is the corresponding index in the NIC ring.
736 * If we have packets to send (nm_i != head)
737 * iterate over the netmap ring, fetch length and update
738 * the corresponding slot in the NIC ring. Some drivers also
739 * need to update the buffer's physical address in the NIC slot
740 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
742 * The netmap_reload_map() calls is especially expensive,
743 * even when (as in this case) the tag is 0, so do only
744 * when the buffer has actually changed.
746 * If possible do not set the report/intr bit on all slots,
747 * but only a few times per ring or when NS_REPORT is set.
749 * Finally, on 10G and faster drivers, it might be useful
750 * to prefetch the next slot and txr entry.
753 nm_i = kring->nr_hwcur;
754 if (nm_i != head) { /* we have new packets to send */
755 nic_i = netmap_idx_k2n(kring, nm_i);
757 __builtin_prefetch(&ring->slot[nm_i]);
758 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
759 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
761 for (n = 0; nm_i != head; n++) {
762 struct netmap_slot *slot = &ring->slot[nm_i];
763 u_int len = slot->len;
765 void *addr = PNMB(na, slot, &paddr);
766 int flags = (slot->flags & NS_REPORT ||
767 nic_i == 0 || nic_i == report_frequency) ?
770 /* device-specific */
772 pi.ipi_flags = flags;
774 /* Fill the slot in the NIC ring. */
775 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
777 /* prefetch for next round */
778 __builtin_prefetch(&ring->slot[nm_i + 1]);
779 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
780 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
782 NM_CHECK_ADDR_LEN(na, addr, len);
784 if (slot->flags & NS_BUF_CHANGED) {
785 /* buffer has changed, reload map */
786 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
788 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
790 /* make sure changes to the buffer are synced */
791 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
792 BUS_DMASYNC_PREWRITE);
794 nm_i = nm_next(nm_i, lim);
795 nic_i = nm_next(nic_i, lim);
797 kring->nr_hwcur = head;
799 /* synchronize the NIC ring */
800 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
803 /* (re)start the tx unit up to slot nic_i (excluded) */
804 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
808 * Second part: reclaim buffers for completed transmissions.
810 if (iflib_tx_credits_update(ctx, txq)) {
811 /* some tx completed, increment avail */
812 nic_i = txq->ift_cidx_processed;
813 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
819 * Reconcile kernel and user view of the receive ring.
820 * Same as for the txsync, this routine must be efficient.
821 * The caller guarantees a single invocations, but races against
822 * the rest of the driver should be handled here.
824 * On call, kring->rhead is the first packet that userspace wants
825 * to keep, and kring->rcur is the wakeup point.
826 * The kernel has previously reported packets up to kring->rtail.
828 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
829 * of whether or not we received an interrupt.
832 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
834 struct netmap_adapter *na = kring->na;
835 struct ifnet *ifp = na->ifp;
836 struct netmap_ring *ring = kring->ring;
837 u_int nm_i; /* index into the netmap ring */
838 u_int nic_i; /* index into the NIC ring */
840 u_int const lim = kring->nkr_num_slots - 1;
841 u_int const head = kring->rhead;
842 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
843 struct if_rxd_info ri;
844 /* device-specific */
845 if_ctx_t ctx = ifp->if_softc;
846 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
847 iflib_fl_t fl = rxq->ifr_fl;
849 return netmap_ring_reinit(kring);
851 bzero(&ri, sizeof(ri));
852 ri.iri_qsidx = kring->ring_id;
853 ri.iri_ifp = ctx->ifc_ifp;
854 /* XXX check sync modes */
855 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++)
856 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
857 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
860 * First part: import newly received packets.
862 * nm_i is the index of the next free slot in the netmap ring,
863 * nic_i is the index of the next received packet in the NIC ring,
864 * and they may differ in case if_init() has been called while
865 * in netmap mode. For the receive ring we have
867 * nic_i = rxr->next_check;
868 * nm_i = kring->nr_hwtail (previous)
870 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
872 * rxr->next_check is set to 0 on a ring reinit
874 if (netmap_no_pendintr || force_update) {
875 int crclen = iflib_crcstrip ? 0 : 4;
877 uint16_t slot_flags = kring->nkr_slot_flags;
879 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) {
880 nic_i = fl->ifl_cidx;
881 nm_i = netmap_idx_n2k(kring, nic_i);
882 avail = ctx->isc_rxd_available(ctx->ifc_softc, kring->ring_id, nic_i, INT_MAX);
883 for (n = 0; avail > 0; n++, avail--) {
884 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
886 ring->slot[nm_i].len = 0;
888 ring->slot[nm_i].len = ri.iri_len - crclen;
889 ring->slot[nm_i].flags = slot_flags;
890 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
891 fl->ifl_sds[nic_i].ifsd_map, BUS_DMASYNC_POSTREAD);
892 nm_i = nm_next(nm_i, lim);
893 nic_i = nm_next(nic_i, lim);
895 if (n) { /* update the state variables */
896 if (netmap_no_pendintr && !force_update) {
899 iflib_rx_miss_bufs += n;
901 fl->ifl_cidx = nic_i;
902 kring->nr_hwtail = nm_i;
904 kring->nr_kflags &= ~NKR_PENDINTR;
908 * Second part: skip past packets that userspace has released.
909 * (kring->nr_hwcur to head excluded),
910 * and make the buffers available for reception.
911 * As usual nm_i is the index in the netmap ring,
912 * nic_i is the index in the NIC ring, and
913 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
915 /* XXX not sure how this will work with multiple free lists */
916 nm_i = kring->nr_hwcur;
918 nic_i = netmap_idx_k2n(kring, nm_i);
919 for (n = 0; nm_i != head; n++) {
920 struct netmap_slot *slot = &ring->slot[nm_i];
923 void *addr = PNMB(na, slot, &paddr);
925 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
929 if (slot->flags & NS_BUF_CHANGED) {
930 /* buffer has changed, reload map */
931 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map, addr);
932 slot->flags &= ~NS_BUF_CHANGED;
935 * XXX we should be batching this operation - TODO
937 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i, &paddr, &vaddr, 1, fl->ifl_buf_size);
938 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map,
939 BUS_DMASYNC_PREREAD);
940 nm_i = nm_next(nm_i, lim);
941 nic_i = nm_next(nic_i, lim);
943 kring->nr_hwcur = head;
945 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
948 * IMPORTANT: we must leave one free slot in the ring,
949 * so move nic_i back by one unit
951 nic_i = nm_prev(nic_i, lim);
952 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
958 return netmap_ring_reinit(kring);
962 iflib_netmap_attach(if_ctx_t ctx)
964 struct netmap_adapter na;
965 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
967 bzero(&na, sizeof(na));
969 na.ifp = ctx->ifc_ifp;
970 na.na_flags = NAF_BDG_MAYSLEEP;
971 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
972 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
974 na.num_tx_desc = scctx->isc_ntxd[0];
975 na.num_rx_desc = scctx->isc_nrxd[0];
976 na.nm_txsync = iflib_netmap_txsync;
977 na.nm_rxsync = iflib_netmap_rxsync;
978 na.nm_register = iflib_netmap_register;
979 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
980 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
981 return (netmap_attach(&na));
985 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
987 struct netmap_adapter *na = NA(ctx->ifc_ifp);
988 struct netmap_slot *slot;
990 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
994 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
997 * In netmap mode, set the map for the packet buffer.
998 * NOTE: Some drivers (not this one) also need to set
999 * the physical buffer address in the NIC ring.
1000 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1001 * netmap slot index, si
1003 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1004 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1008 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1010 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1011 struct netmap_slot *slot;
1015 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1018 sd = rxq->ifr_fl[0].ifl_sds;
1019 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0];
1020 for (int i = 0; i < nrxd; i++, sd++) {
1021 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i);
1026 vaddr = addr = PNMB(na, slot + sj, &paddr);
1027 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, sd->ifsd_map, addr);
1028 /* Update descriptor and the cached value */
1029 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, i, &paddr, &vaddr, 1, rxq->ifr_fl[0].ifl_buf_size);
1031 /* preserve queue */
1032 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) {
1033 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1034 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1035 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t);
1037 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1);
1040 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1043 #define iflib_netmap_txq_init(ctx, txq)
1044 #define iflib_netmap_rxq_init(ctx, rxq)
1045 #define iflib_netmap_detach(ifp)
1047 #define iflib_netmap_attach(ctx) (0)
1048 #define netmap_rx_irq(ifp, qid, budget) (0)
1052 #if defined(__i386__) || defined(__amd64__)
1053 static __inline void
1056 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1063 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1067 *(bus_addr_t *) arg = segs[0].ds_addr;
1071 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1074 if_shared_ctx_t sctx = ctx->ifc_sctx;
1075 device_t dev = ctx->ifc_dev;
1077 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1079 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1080 sctx->isc_q_align, 0, /* alignment, bounds */
1081 BUS_SPACE_MAXADDR, /* lowaddr */
1082 BUS_SPACE_MAXADDR, /* highaddr */
1083 NULL, NULL, /* filter, filterarg */
1086 size, /* maxsegsize */
1087 BUS_DMA_ALLOCNOW, /* flags */
1088 NULL, /* lockfunc */
1093 "%s: bus_dma_tag_create failed: %d\n",
1098 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1099 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1102 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1103 __func__, (uintmax_t)size, err);
1107 dma->idi_paddr = IF_BAD_DMA;
1108 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1109 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1110 if (err || dma->idi_paddr == IF_BAD_DMA) {
1112 "%s: bus_dmamap_load failed: %d\n",
1117 dma->idi_size = size;
1121 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1123 bus_dma_tag_destroy(dma->idi_tag);
1125 dma->idi_tag = NULL;
1131 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1134 iflib_dma_info_t *dmaiter;
1137 for (i = 0; i < count; i++, dmaiter++) {
1138 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1142 iflib_dma_free_multi(dmalist, i);
1147 iflib_dma_free(iflib_dma_info_t dma)
1149 if (dma->idi_tag == NULL)
1151 if (dma->idi_paddr != IF_BAD_DMA) {
1152 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1153 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1154 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1155 dma->idi_paddr = IF_BAD_DMA;
1157 if (dma->idi_vaddr != NULL) {
1158 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1159 dma->idi_vaddr = NULL;
1161 bus_dma_tag_destroy(dma->idi_tag);
1162 dma->idi_tag = NULL;
1166 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1169 iflib_dma_info_t *dmaiter = dmalist;
1171 for (i = 0; i < count; i++, dmaiter++)
1172 iflib_dma_free(*dmaiter);
1176 iflib_fast_intr(void *arg)
1178 iflib_filter_info_t info = arg;
1179 struct grouptask *gtask = info->ifi_task;
1181 DBG_COUNTER_INC(fast_intrs);
1182 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1183 return (FILTER_HANDLED);
1185 GROUPTASK_ENQUEUE(gtask);
1186 return (FILTER_HANDLED);
1190 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1191 driver_filter_t filter, driver_intr_t handler, void *arg,
1195 struct resource *res;
1197 device_t dev = ctx->ifc_dev;
1201 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid,
1202 RF_SHAREABLE | RF_ACTIVE);
1205 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1209 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1210 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1211 filter, handler, arg, &tag);
1214 "failed to setup interrupt for rid %d, name %s: %d\n",
1215 rid, name ? name : "unknown", rc);
1218 bus_describe_intr(dev, res, tag, "%s", name);
1225 /*********************************************************************
1227 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1228 * the information needed to transmit a packet on the wire. This is
1229 * called only once at attach, setup is done every reset.
1231 **********************************************************************/
1234 iflib_txsd_alloc(iflib_txq_t txq)
1236 if_ctx_t ctx = txq->ift_ctx;
1237 if_shared_ctx_t sctx = ctx->ifc_sctx;
1238 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1239 device_t dev = ctx->ifc_dev;
1240 int err, nsegments, ntsosegments;
1242 nsegments = scctx->isc_tx_nsegments;
1243 ntsosegments = scctx->isc_tx_tso_segments_max;
1244 MPASS(scctx->isc_ntxd[0] > 0);
1245 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1246 MPASS(nsegments > 0);
1247 MPASS(ntsosegments > 0);
1249 * Setup DMA descriptor areas.
1251 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1252 1, 0, /* alignment, bounds */
1253 BUS_SPACE_MAXADDR, /* lowaddr */
1254 BUS_SPACE_MAXADDR, /* highaddr */
1255 NULL, NULL, /* filter, filterarg */
1256 sctx->isc_tx_maxsize, /* maxsize */
1257 nsegments, /* nsegments */
1258 sctx->isc_tx_maxsegsize, /* maxsegsize */
1260 NULL, /* lockfunc */
1261 NULL, /* lockfuncarg */
1262 &txq->ift_desc_tag))) {
1263 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1264 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1265 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1268 #ifdef IFLIB_DIAGNOSTICS
1269 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n",
1270 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize);
1273 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1274 1, 0, /* alignment, bounds */
1275 BUS_SPACE_MAXADDR, /* lowaddr */
1276 BUS_SPACE_MAXADDR, /* highaddr */
1277 NULL, NULL, /* filter, filterarg */
1278 scctx->isc_tx_tso_size_max, /* maxsize */
1279 ntsosegments, /* nsegments */
1280 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1282 NULL, /* lockfunc */
1283 NULL, /* lockfuncarg */
1284 &txq->ift_tso_desc_tag))) {
1285 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1289 #ifdef IFLIB_DIAGNOSTICS
1290 device_printf(dev,"TSO maxsize: %d ntsosegments: %d maxsegsize: %d\n",
1291 scctx->isc_tx_tso_size_max, ntsosegments,
1292 scctx->isc_tx_tso_segsize_max);
1294 if (!(txq->ift_sds.ifsd_flags =
1295 (uint8_t *) malloc(sizeof(uint8_t) *
1296 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1297 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1301 if (!(txq->ift_sds.ifsd_m =
1302 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1303 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1304 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1309 /* Create the descriptor buffer dma maps */
1310 #if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__)))
1311 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1314 if (!(txq->ift_sds.ifsd_map =
1315 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1316 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1321 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1322 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1324 device_printf(dev, "Unable to create TX DMA map\n");
1331 /* We free all, it handles case where we are in the middle */
1332 iflib_tx_structures_free(ctx);
1337 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1342 if (txq->ift_sds.ifsd_map != NULL)
1343 map = txq->ift_sds.ifsd_map[i];
1345 bus_dmamap_unload(txq->ift_desc_tag, map);
1346 bus_dmamap_destroy(txq->ift_desc_tag, map);
1347 txq->ift_sds.ifsd_map[i] = NULL;
1352 iflib_txq_destroy(iflib_txq_t txq)
1354 if_ctx_t ctx = txq->ift_ctx;
1356 for (int i = 0; i < txq->ift_size; i++)
1357 iflib_txsd_destroy(ctx, txq, i);
1358 if (txq->ift_sds.ifsd_map != NULL) {
1359 free(txq->ift_sds.ifsd_map, M_IFLIB);
1360 txq->ift_sds.ifsd_map = NULL;
1362 if (txq->ift_sds.ifsd_m != NULL) {
1363 free(txq->ift_sds.ifsd_m, M_IFLIB);
1364 txq->ift_sds.ifsd_m = NULL;
1366 if (txq->ift_sds.ifsd_flags != NULL) {
1367 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1368 txq->ift_sds.ifsd_flags = NULL;
1370 if (txq->ift_desc_tag != NULL) {
1371 bus_dma_tag_destroy(txq->ift_desc_tag);
1372 txq->ift_desc_tag = NULL;
1374 if (txq->ift_tso_desc_tag != NULL) {
1375 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1376 txq->ift_tso_desc_tag = NULL;
1381 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1385 mp = &txq->ift_sds.ifsd_m[i];
1389 if (txq->ift_sds.ifsd_map != NULL) {
1390 bus_dmamap_sync(txq->ift_desc_tag,
1391 txq->ift_sds.ifsd_map[i],
1392 BUS_DMASYNC_POSTWRITE);
1393 bus_dmamap_unload(txq->ift_desc_tag,
1394 txq->ift_sds.ifsd_map[i]);
1397 DBG_COUNTER_INC(tx_frees);
1402 iflib_txq_setup(iflib_txq_t txq)
1404 if_ctx_t ctx = txq->ift_ctx;
1405 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1406 iflib_dma_info_t di;
1409 /* Set number of descriptors available */
1410 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1413 txq->ift_cidx_processed = txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1414 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1416 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1417 bzero((void *)di->idi_vaddr, di->idi_size);
1419 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1420 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1421 bus_dmamap_sync(di->idi_tag, di->idi_map,
1422 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1426 /*********************************************************************
1428 * Allocate memory for rx_buffer structures. Since we use one
1429 * rx_buffer per received packet, the maximum number of rx_buffer's
1430 * that we'll need is equal to the number of receive descriptors
1431 * that we've allocated.
1433 **********************************************************************/
1435 iflib_rxsd_alloc(iflib_rxq_t rxq)
1437 if_ctx_t ctx = rxq->ifr_ctx;
1438 if_shared_ctx_t sctx = ctx->ifc_sctx;
1439 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1440 device_t dev = ctx->ifc_dev;
1445 MPASS(scctx->isc_nrxd[0] > 0);
1446 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1449 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1450 fl->ifl_sds = malloc(sizeof(struct iflib_sw_rx_desc) *
1451 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB,
1453 if (fl->ifl_sds == NULL) {
1454 device_printf(dev, "Unable to allocate rx sw desc memory\n");
1457 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1458 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1459 1, 0, /* alignment, bounds */
1460 BUS_SPACE_MAXADDR, /* lowaddr */
1461 BUS_SPACE_MAXADDR, /* highaddr */
1462 NULL, NULL, /* filter, filterarg */
1463 sctx->isc_rx_maxsize, /* maxsize */
1464 sctx->isc_rx_nsegments, /* nsegments */
1465 sctx->isc_rx_maxsegsize, /* maxsegsize */
1467 NULL, /* lockfunc */
1471 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1477 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++, rxsd++) {
1478 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &rxsd->ifsd_map);
1480 device_printf(dev, "%s: bus_dmamap_create failed: %d\n",
1489 iflib_rx_structures_free(ctx);
1495 * Internal service routines
1498 struct rxq_refill_cb_arg {
1500 bus_dma_segment_t seg;
1505 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1507 struct rxq_refill_cb_arg *cb_arg = arg;
1509 cb_arg->error = error;
1510 cb_arg->seg = segs[0];
1511 cb_arg->nseg = nseg;
1516 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1518 #define IS_DMAR(ctx) (0)
1522 * rxq_refill - refill an rxq free-buffer list
1523 * @ctx: the iflib context
1524 * @rxq: the free-list to refill
1525 * @n: the number of new buffers to allocate
1527 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1528 * The caller must assure that @n does not exceed the queue's capacity.
1531 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1534 int pidx = fl->ifl_pidx;
1535 iflib_rxsd_t rxsd = &fl->ifl_sds[pidx];
1543 MPASS(fl->ifl_credits + n <= fl->ifl_size);
1545 if (pidx < fl->ifl_cidx)
1546 MPASS(pidx + n <= fl->ifl_cidx);
1547 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size))
1548 MPASS(fl->ifl_gen == 0);
1549 if (pidx > fl->ifl_cidx)
1550 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1552 DBG_COUNTER_INC(fl_refills);
1554 DBG_COUNTER_INC(fl_refills_large);
1558 * We allocate an uninitialized mbuf + cluster, mbuf is
1559 * initialized after rx.
1561 * If the cluster is still set then we know a minimum sized packet was received
1563 if ((cl = rxsd->ifsd_cl) == NULL) {
1564 if ((cl = rxsd->ifsd_cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1567 fl->ifl_cl_enqueued++;
1570 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1574 fl->ifl_m_enqueued++;
1577 DBG_COUNTER_INC(rx_allocs);
1579 if ((rxsd->ifsd_flags & RX_SW_DESC_MAP_CREATED) == 0) {
1582 if ((err = bus_dmamap_create(fl->ifl_ifdi->idi_tag, 0, &rxsd->ifsd_map))) {
1583 log(LOG_WARNING, "bus_dmamap_create failed %d\n", err);
1584 uma_zfree(fl->ifl_zone, cl);
1588 rxsd->ifsd_flags |= RX_SW_DESC_MAP_CREATED;
1591 #if defined(__i386__) || defined(__amd64__)
1592 if (!IS_DMAR(ctx)) {
1593 bus_addr = pmap_kextract((vm_offset_t)cl);
1597 struct rxq_refill_cb_arg cb_arg;
1602 err = bus_dmamap_load(fl->ifl_desc_tag, rxsd->ifsd_map,
1603 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1605 if (err != 0 || cb_arg.error) {
1609 if (fl->ifl_zone == zone_pack)
1610 uma_zfree(fl->ifl_zone, cl);
1615 bus_addr = cb_arg.seg.ds_addr;
1617 rxsd->ifsd_flags |= RX_SW_DESC_INUSE;
1619 MPASS(rxsd->ifsd_m == NULL);
1622 fl->ifl_bus_addrs[i] = bus_addr;
1623 fl->ifl_vm_addrs[i] = cl;
1627 MPASS(fl->ifl_credits <= fl->ifl_size);
1628 if (++fl->ifl_pidx == fl->ifl_size) {
1633 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1634 ctx->isc_rxd_refill(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx,
1635 fl->ifl_bus_addrs, fl->ifl_vm_addrs, i, fl->ifl_buf_size);
1637 pidx = fl->ifl_pidx;
1641 DBG_COUNTER_INC(rxd_flush);
1642 if (fl->ifl_pidx == 0)
1643 pidx = fl->ifl_size - 1;
1645 pidx = fl->ifl_pidx - 1;
1646 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1649 static __inline void
1650 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1652 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1653 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1655 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1658 MPASS(fl->ifl_credits <= fl->ifl_size);
1659 MPASS(reclaimable == delta);
1661 if (reclaimable > 0)
1662 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1666 iflib_fl_bufs_free(iflib_fl_t fl)
1668 iflib_dma_info_t idi = fl->ifl_ifdi;
1671 for (i = 0; i < fl->ifl_size; i++) {
1672 iflib_rxsd_t d = &fl->ifl_sds[i];
1674 if (d->ifsd_flags & RX_SW_DESC_INUSE) {
1675 bus_dmamap_unload(fl->ifl_desc_tag, d->ifsd_map);
1676 bus_dmamap_destroy(fl->ifl_desc_tag, d->ifsd_map);
1677 if (d->ifsd_m != NULL) {
1678 m_init(d->ifsd_m, M_NOWAIT, MT_DATA, 0);
1679 uma_zfree(zone_mbuf, d->ifsd_m);
1681 if (d->ifsd_cl != NULL)
1682 uma_zfree(fl->ifl_zone, d->ifsd_cl);
1685 MPASS(d->ifsd_cl == NULL);
1686 MPASS(d->ifsd_m == NULL);
1689 fl->ifl_m_dequeued++;
1690 fl->ifl_cl_dequeued++;
1696 * Reset free list values
1698 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;;
1699 bzero(idi->idi_vaddr, idi->idi_size);
1702 /*********************************************************************
1704 * Initialize a receive ring and its buffers.
1706 **********************************************************************/
1708 iflib_fl_setup(iflib_fl_t fl)
1710 iflib_rxq_t rxq = fl->ifl_rxq;
1711 if_ctx_t ctx = rxq->ifr_ctx;
1712 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
1715 ** Free current RX buffer structs and their mbufs
1717 iflib_fl_bufs_free(fl);
1718 /* Now replenish the mbufs */
1719 MPASS(fl->ifl_credits == 0);
1721 * XXX don't set the max_frame_size to larger
1722 * than the hardware can handle
1724 if (sctx->isc_max_frame_size <= 2048)
1725 fl->ifl_buf_size = MCLBYTES;
1726 else if (sctx->isc_max_frame_size <= 4096)
1727 fl->ifl_buf_size = MJUMPAGESIZE;
1728 else if (sctx->isc_max_frame_size <= 9216)
1729 fl->ifl_buf_size = MJUM9BYTES;
1731 fl->ifl_buf_size = MJUM16BYTES;
1732 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
1733 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
1734 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
1735 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
1738 /* avoid pre-allocating zillions of clusters to an idle card
1739 * potentially speeding up attach
1741 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
1742 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
1743 if (min(128, fl->ifl_size) != fl->ifl_credits)
1749 MPASS(fl->ifl_ifdi != NULL);
1750 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1751 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1755 /*********************************************************************
1757 * Free receive ring data structures
1759 **********************************************************************/
1761 iflib_rx_sds_free(iflib_rxq_t rxq)
1766 if (rxq->ifr_fl != NULL) {
1767 for (i = 0; i < rxq->ifr_nfl; i++) {
1768 fl = &rxq->ifr_fl[i];
1769 if (fl->ifl_desc_tag != NULL) {
1770 bus_dma_tag_destroy(fl->ifl_desc_tag);
1771 fl->ifl_desc_tag = NULL;
1774 if (rxq->ifr_fl->ifl_sds != NULL)
1775 free(rxq->ifr_fl->ifl_sds, M_IFLIB);
1777 free(rxq->ifr_fl, M_IFLIB);
1779 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
1784 * MI independent logic
1788 iflib_timer(void *arg)
1790 iflib_txq_t txq = arg;
1791 if_ctx_t ctx = txq->ift_ctx;
1792 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1794 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
1797 ** Check on the state of the TX queue(s), this
1798 ** can be done without the lock because its RO
1799 ** and the HUNG state will be static if set.
1801 IFDI_TIMER(ctx, txq->ift_id);
1802 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
1803 (ctx->ifc_pause_frames == 0))
1806 if (TXQ_AVAIL(txq) <= 2*scctx->isc_tx_nsegments ||
1807 ifmp_ring_is_stalled(txq->ift_br[0]))
1808 GROUPTASK_ENQUEUE(&txq->ift_task);
1810 ctx->ifc_pause_frames = 0;
1811 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
1812 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
1816 if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING);
1817 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
1818 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
1820 IFDI_WATCHDOG_RESET(ctx);
1821 ctx->ifc_watchdog_events++;
1822 ctx->ifc_pause_frames = 0;
1824 iflib_init_locked(ctx);
1829 iflib_init_locked(if_ctx_t ctx)
1831 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
1832 if_t ifp = ctx->ifc_ifp;
1839 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
1840 IFDI_INTR_DISABLE(ctx);
1842 /* Set hardware offload abilities */
1843 if_clearhwassist(ifp);
1844 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
1845 if_sethwassistbits(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP, 0);
1846 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
1847 if_sethwassistbits(ifp, (CSUM_TCP_IPV6 | CSUM_UDP_IPV6), 0);
1848 if (if_getcapenable(ifp) & IFCAP_TSO4)
1849 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
1850 if (if_getcapenable(ifp) & IFCAP_TSO6)
1851 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
1853 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
1855 callout_stop(&txq->ift_timer);
1856 callout_stop(&txq->ift_db_check);
1857 CALLOUT_UNLOCK(txq);
1858 iflib_netmap_txq_init(ctx, txq);
1860 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
1861 iflib_netmap_rxq_init(ctx, rxq);
1864 i = if_getdrvflags(ifp);
1867 MPASS(if_getdrvflags(ifp) == i);
1868 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
1869 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
1870 if (iflib_fl_setup(fl)) {
1871 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
1877 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1878 IFDI_INTR_ENABLE(ctx);
1879 txq = ctx->ifc_txqs;
1880 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
1881 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
1882 txq->ift_timer.c_cpu);
1886 iflib_media_change(if_t ifp)
1888 if_ctx_t ctx = if_getsoftc(ifp);
1892 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
1893 iflib_init_locked(ctx);
1899 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
1901 if_ctx_t ctx = if_getsoftc(ifp);
1904 IFDI_UPDATE_ADMIN_STATUS(ctx);
1905 IFDI_MEDIA_STATUS(ctx, ifmr);
1910 iflib_stop(if_ctx_t ctx)
1912 iflib_txq_t txq = ctx->ifc_txqs;
1913 iflib_rxq_t rxq = ctx->ifc_rxqs;
1914 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1915 iflib_dma_info_t di;
1919 /* Tell the stack that the interface is no longer active */
1920 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
1922 IFDI_INTR_DISABLE(ctx);
1923 msleep(ctx, &ctx->ifc_mtx, PUSER, "iflib_init", hz);
1925 /* Wait for current tx queue users to exit to disarm watchdog timer. */
1926 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
1927 /* make sure all transmitters have completed before proceeding XXX */
1929 /* clean any enqueued buffers */
1930 iflib_txq_check_drain(txq, 0);
1931 /* Free any existing tx buffers. */
1932 for (j = 0; j < txq->ift_size; j++) {
1933 iflib_txsd_free(ctx, txq, j);
1935 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
1936 txq->ift_in_use = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
1937 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
1938 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
1939 txq->ift_pullups = 0;
1940 ifmp_ring_reset_stats(txq->ift_br[0]);
1941 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
1942 bzero((void *)di->idi_vaddr, di->idi_size);
1944 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
1945 /* make sure all transmitters have completed before proceeding XXX */
1947 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
1948 bzero((void *)di->idi_vaddr, di->idi_size);
1949 /* also resets the free lists pidx/cidx */
1950 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
1951 iflib_fl_bufs_free(fl);
1957 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int *cltype, int unload)
1962 iflib_dma_info_t di;
1964 flid = irf->irf_flid;
1965 cidx = irf->irf_idx;
1966 fl = &rxq->ifr_fl[flid];
1969 fl->ifl_m_dequeued++;
1971 fl->ifl_cl_dequeued++;
1973 sd = &fl->ifl_sds[cidx];
1975 bus_dmamap_sync(di->idi_tag, di->idi_map,
1976 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1978 /* not valid assert if bxe really does SGE from non-contiguous elements */
1979 MPASS(fl->ifl_cidx == cidx);
1981 bus_dmamap_unload(fl->ifl_desc_tag, sd->ifsd_map);
1983 if (__predict_false(++fl->ifl_cidx == fl->ifl_size)) {
1989 *cltype = fl->ifl_cltype;
1993 static struct mbuf *
1994 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri)
1996 int i, padlen , flags, cltype;
1997 struct mbuf *m, *mh, *mt;
2004 sd = rxd_frag_to_sd(rxq, &ri->iri_frags[i], &cltype, TRUE);
2006 MPASS(sd->ifsd_cl != NULL);
2007 MPASS(sd->ifsd_m != NULL);
2009 /* Don't include zero-length frags */
2010 if (ri->iri_frags[i].irf_len == 0) {
2011 /* XXX we can save the cluster here, but not the mbuf */
2012 m_init(sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2020 flags = M_PKTHDR|M_EXT;
2022 padlen = ri->iri_pad;
2027 /* assuming padding is only on the first fragment */
2034 /* Can these two be made one ? */
2035 m_init(m, M_NOWAIT, MT_DATA, flags);
2036 m_cljset(m, cl, cltype);
2038 * These must follow m_init and m_cljset
2040 m->m_data += padlen;
2041 ri->iri_len -= padlen;
2042 m->m_len = ri->iri_frags[i].irf_len;
2043 } while (++i < ri->iri_nfrags);
2049 * Process one software descriptor
2051 static struct mbuf *
2052 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2057 /* should I merge this back in now that the two paths are basically duplicated? */
2058 if (ri->iri_nfrags == 1 &&
2059 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2060 sd = rxd_frag_to_sd(rxq, &ri->iri_frags[0], NULL, FALSE);
2063 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2064 memcpy(m->m_data, sd->ifsd_cl, ri->iri_len);
2065 m->m_len = ri->iri_frags[0].irf_len;
2067 m = assemble_segments(rxq, ri);
2069 m->m_pkthdr.len = ri->iri_len;
2070 m->m_pkthdr.rcvif = ri->iri_ifp;
2071 m->m_flags |= ri->iri_flags;
2072 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2073 m->m_pkthdr.flowid = ri->iri_flowid;
2074 M_HASHTYPE_SET(m, ri->iri_rsstype);
2075 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2076 m->m_pkthdr.csum_data = ri->iri_csum_data;
2081 iflib_rxeof(iflib_rxq_t rxq, int budget)
2083 if_ctx_t ctx = rxq->ifr_ctx;
2084 if_shared_ctx_t sctx = ctx->ifc_sctx;
2085 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2088 struct if_rxd_info ri;
2089 int err, budget_left, rx_bytes, rx_pkts;
2094 * XXX early demux data packets so that if_input processing only handles
2095 * acks in interrupt context
2097 struct mbuf *m, *mh, *mt;
2099 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &budget)) {
2105 rx_pkts = rx_bytes = 0;
2106 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2107 cidxp = &rxq->ifr_cq_cidx;
2109 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2110 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2111 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2112 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2113 DBG_COUNTER_INC(rx_unavail);
2117 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2118 if (__predict_false(!CTX_ACTIVE(ctx))) {
2119 DBG_COUNTER_INC(rx_ctx_inactive);
2123 * Reset client set fields to their default values
2125 bzero(&ri, sizeof(ri));
2126 ri.iri_qsidx = rxq->ifr_id;
2127 ri.iri_cidx = *cidxp;
2128 ri.iri_ifp = ctx->ifc_ifp;
2129 ri.iri_frags = rxq->ifr_frags;
2130 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2132 /* in lieu of handling correctly - make sure it isn't being unhandled */
2134 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2135 *cidxp = ri.iri_cidx;
2136 /* Update our consumer index */
2137 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2138 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2139 rxq->ifr_cq_gen = 0;
2141 /* was this only a completion queue message? */
2142 if (__predict_false(ri.iri_nfrags == 0))
2145 MPASS(ri.iri_nfrags != 0);
2146 MPASS(ri.iri_len != 0);
2148 /* will advance the cidx on the corresponding free lists */
2149 m = iflib_rxd_pkt_get(rxq, &ri);
2150 if (avail == 0 && budget_left)
2151 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2153 if (__predict_false(m == NULL)) {
2154 DBG_COUNTER_INC(rx_mbuf_null);
2157 /* imm_pkt: -- cxgb */
2165 /* make sure that we can refill faster than drain */
2166 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2167 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2170 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2171 while (mh != NULL) {
2174 m->m_nextpkt = NULL;
2175 rx_bytes += m->m_pkthdr.len;
2177 #if defined(INET6) || defined(INET)
2178 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2181 DBG_COUNTER_INC(rx_if_input);
2182 ifp->if_input(ifp, m);
2185 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2186 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2189 * Flush any outstanding LRO work
2191 #if defined(INET6) || defined(INET)
2192 tcp_lro_flush_all(&rxq->ifr_lc);
2196 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2199 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2200 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2201 #define TXQ_MAX_DB_DEFERRED(size) (size >> 5)
2202 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2204 static __inline void
2205 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring)
2209 if (ring || txq->ift_db_pending >=
2210 TXQ_MAX_DB_DEFERRED(txq->ift_size)) {
2212 /* the lock will only ever be contended in the !min_latency case */
2213 if (!TXDB_TRYLOCK(txq))
2215 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2216 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2217 txq->ift_db_pending = txq->ift_npending = 0;
2223 iflib_txd_deferred_db_check(void * arg)
2225 iflib_txq_t txq = arg;
2227 /* simple non-zero boolean so use bitwise OR */
2228 if ((txq->ift_db_pending | txq->ift_npending) &&
2229 txq->ift_db_pending >= txq->ift_db_pending_queued)
2230 iflib_txd_db_check(txq->ift_ctx, txq, TRUE);
2231 txq->ift_db_pending_queued = 0;
2232 if (ifmp_ring_is_stalled(txq->ift_br[0]))
2233 iflib_txq_check_drain(txq, 4);
2238 print_pkt(if_pkt_info_t pi)
2240 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2241 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2242 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2243 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2244 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2245 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2249 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2250 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2253 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2255 struct ether_vlan_header *eh;
2260 * Determine where frame payload starts.
2261 * Jump over vlan headers if already present,
2262 * helpful for QinQ too.
2264 if (__predict_false(m->m_len < sizeof(*eh))) {
2266 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2269 eh = mtod(m, struct ether_vlan_header *);
2270 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2271 pi->ipi_etype = ntohs(eh->evl_proto);
2272 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2274 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2275 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2278 switch (pi->ipi_etype) {
2282 struct ip *ip = NULL;
2283 struct tcphdr *th = NULL;
2286 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2287 if (__predict_false(m->m_len < minthlen)) {
2289 * if this code bloat is causing too much of a hit
2290 * move it to a separate function and mark it noinline
2292 if (m->m_len == pi->ipi_ehdrlen) {
2295 if (n->m_len >= sizeof(*ip)) {
2296 ip = (struct ip *)n->m_data;
2297 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2298 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2301 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2303 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2307 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2309 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2310 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2311 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2314 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2315 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2316 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2318 pi->ipi_ip_hlen = ip->ip_hl << 2;
2319 pi->ipi_ipproto = ip->ip_p;
2320 pi->ipi_flags |= IPI_TX_IPV4;
2322 if (pi->ipi_csum_flags & CSUM_IP)
2325 if (pi->ipi_ipproto == IPPROTO_TCP) {
2326 if (__predict_false(th == NULL)) {
2328 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2330 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2332 pi->ipi_tcp_hflags = th->th_flags;
2333 pi->ipi_tcp_hlen = th->th_off << 2;
2334 pi->ipi_tcp_seq = th->th_seq;
2337 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2339 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2340 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2341 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2347 case ETHERTYPE_IPV6:
2349 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2351 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2353 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2354 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2357 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2359 /* XXX-BZ this will go badly in case of ext hdrs. */
2360 pi->ipi_ipproto = ip6->ip6_nxt;
2361 pi->ipi_flags |= IPI_TX_IPV6;
2363 if (pi->ipi_ipproto == IPPROTO_TCP) {
2364 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2365 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2368 pi->ipi_tcp_hflags = th->th_flags;
2369 pi->ipi_tcp_hlen = th->th_off << 2;
2373 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2376 * The corresponding flag is set by the stack in the IPv4
2377 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2378 * So, set it here because the rest of the flow requires it.
2380 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2381 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2382 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2388 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2389 pi->ipi_ip_hlen = 0;
2397 static __noinline struct mbuf *
2398 collapse_pkthdr(struct mbuf *m0)
2400 struct mbuf *m, *m_next, *tmp;
2404 while (m_next != NULL && m_next->m_len == 0) {
2408 m_next = m_next->m_next;
2412 if ((m_next->m_flags & M_EXT) == 0) {
2413 m = m_defrag(m, M_NOWAIT);
2415 tmp = m_next->m_next;
2416 memcpy(m_next, m, MPKTHSIZE);
2424 * If dodgy hardware rejects the scatter gather chain we've handed it
2425 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2428 static __noinline struct mbuf *
2429 iflib_remove_mbuf(iflib_txq_t txq)
2432 struct mbuf *m, *mh, **ifsd_m;
2434 pidx = txq->ift_pidx;
2435 ifsd_m = txq->ift_sds.ifsd_m;
2436 ntxd = txq->ift_size;
2437 mh = m = ifsd_m[pidx];
2438 ifsd_m[pidx] = NULL;
2440 txq->ift_dequeued++;
2445 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2447 txq->ift_dequeued++;
2456 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2457 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2458 int max_segs, int flags)
2461 if_shared_ctx_t sctx;
2462 if_softc_ctx_t scctx;
2463 int i, next, pidx, mask, err, maxsegsz, ntxd, count;
2464 struct mbuf *m, *tmp, **ifsd_m, **mp;
2469 * Please don't ever do this
2471 if (__predict_false(m->m_len == 0))
2472 *m0 = m = collapse_pkthdr(m);
2475 sctx = ctx->ifc_sctx;
2476 scctx = &ctx->ifc_softc_ctx;
2477 ifsd_m = txq->ift_sds.ifsd_m;
2478 ntxd = txq->ift_size;
2479 pidx = txq->ift_pidx;
2481 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2483 err = bus_dmamap_load_mbuf_sg(tag, map,
2484 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2487 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
2490 mask = (txq->ift_size-1);
2496 if (__predict_false((*mp)->m_len == 0)) {
2500 next = (pidx + i) & (ntxd-1);
2501 } while (m != NULL);
2503 int buflen, sgsize, max_sgsize;
2508 maxsegsz = sctx->isc_tx_maxsize;
2511 if (__predict_false(m->m_len <= 0)) {
2519 vaddr = (vm_offset_t)m->m_data;
2521 * see if we can't be smarter about physically
2522 * contiguous mappings
2524 next = (pidx + count) & (ntxd-1);
2525 MPASS(ifsd_m[next] == NULL);
2527 txq->ift_enqueued++;
2530 while (buflen > 0) {
2531 max_sgsize = MIN(buflen, maxsegsz);
2532 curaddr = pmap_kextract(vaddr);
2533 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
2534 sgsize = MIN(sgsize, max_sgsize);
2535 segs[i].ds_addr = curaddr;
2536 segs[i].ds_len = sgsize;
2546 } while (m != NULL);
2551 *m0 = iflib_remove_mbuf(txq);
2556 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
2559 if_shared_ctx_t sctx;
2560 if_softc_ctx_t scctx;
2561 bus_dma_segment_t *segs;
2562 struct mbuf *m_head;
2564 struct if_pkt_info pi;
2566 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
2567 bus_dma_tag_t desc_tag;
2569 segs = txq->ift_segs;
2571 sctx = ctx->ifc_sctx;
2572 scctx = &ctx->ifc_softc_ctx;
2573 segs = txq->ift_segs;
2574 ntxd = txq->ift_size;
2579 * If we're doing TSO the next descriptor to clean may be quite far ahead
2581 cidx = txq->ift_cidx;
2582 pidx = txq->ift_pidx;
2583 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
2585 /* prefetch the next cache line of mbuf pointers and flags */
2586 prefetch(&txq->ift_sds.ifsd_m[next]);
2587 if (txq->ift_sds.ifsd_map != NULL) {
2588 prefetch(&txq->ift_sds.ifsd_map[next]);
2589 map = txq->ift_sds.ifsd_map[pidx];
2590 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
2591 prefetch(&txq->ift_sds.ifsd_flags[next]);
2595 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2596 desc_tag = txq->ift_tso_desc_tag;
2597 max_segs = scctx->isc_tx_tso_segments_max;
2599 desc_tag = txq->ift_desc_tag;
2600 max_segs = scctx->isc_tx_nsegments;
2603 bzero(&pi, sizeof(pi));
2604 pi.ipi_len = m_head->m_pkthdr.len;
2605 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
2606 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
2607 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
2609 pi.ipi_qsidx = txq->ift_id;
2611 /* deliberate bitwise OR to make one condition */
2612 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
2613 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
2619 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
2621 if (__predict_false(err)) {
2624 /* try collapse once and defrag once */
2626 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
2628 m_head = m_defrag(*m_headp, M_NOWAIT);
2630 if (__predict_false(m_head == NULL))
2632 txq->ift_mbuf_defrag++;
2637 txq->ift_no_tx_dma_setup++;
2640 txq->ift_no_tx_dma_setup++;
2642 DBG_COUNTER_INC(tx_frees);
2646 txq->ift_map_failed++;
2647 DBG_COUNTER_INC(encap_load_mbuf_fail);
2652 * XXX assumes a 1 to 1 relationship between segments and
2653 * descriptors - this does not hold true on all drivers, e.g.
2656 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
2657 txq->ift_no_desc_avail++;
2659 bus_dmamap_unload(desc_tag, map);
2660 DBG_COUNTER_INC(encap_txq_avail_fail);
2661 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
2662 GROUPTASK_ENQUEUE(&txq->ift_task);
2666 pi.ipi_nsegs = nsegs;
2668 MPASS(pidx >= 0 && pidx < txq->ift_size);
2672 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
2673 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2674 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2676 DBG_COUNTER_INC(tx_encap);
2677 MPASS(pi.ipi_new_pidx >= 0 &&
2678 pi.ipi_new_pidx < txq->ift_size);
2680 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
2681 if (pi.ipi_new_pidx < pi.ipi_pidx) {
2682 ndesc += txq->ift_size;
2685 MPASS(pi.ipi_new_pidx != pidx);
2687 txq->ift_in_use += ndesc;
2689 * We update the last software descriptor again here because there may
2690 * be a sentinel and/or there may be more mbufs than segments
2692 txq->ift_pidx = pi.ipi_new_pidx;
2693 txq->ift_npending += pi.ipi_ndescs;
2694 } else if (__predict_false(err == EFBIG && remap < 2)) {
2695 *m_headp = m_head = iflib_remove_mbuf(txq);
2697 txq->ift_txd_encap_efbig++;
2700 DBG_COUNTER_INC(encap_txd_encap_fail);
2704 txq->ift_mbuf_defrag_failed++;
2705 txq->ift_map_failed++;
2707 DBG_COUNTER_INC(tx_frees);
2712 /* forward compatibility for cxgb */
2713 #define FIRST_QSET(ctx) 0
2715 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2716 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2717 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2718 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2719 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2720 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2724 /* if there are more than TXQ_MIN_OCCUPANCY packets pending we consider deferring
2727 * ORing with 2 assures that min occupancy is never less than 2 without any conditional logic
2729 #define TXQ_MIN_OCCUPANCY(size) ((size >> 6)| 0x2)
2732 iflib_txq_min_occupancy(iflib_txq_t txq)
2737 return (get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx,
2738 txq->ift_gen) < TXQ_MIN_OCCUPANCY(txq->ift_size) +
2743 iflib_tx_desc_free(iflib_txq_t txq, int n)
2746 uint32_t qsize, cidx, mask, gen;
2747 struct mbuf *m, **ifsd_m;
2748 uint8_t *ifsd_flags;
2749 bus_dmamap_t *ifsd_map;
2751 cidx = txq->ift_cidx;
2753 qsize = txq->ift_size;
2755 hasmap = txq->ift_sds.ifsd_map != NULL;
2756 ifsd_flags = txq->ift_sds.ifsd_flags;
2757 ifsd_m = txq->ift_sds.ifsd_m;
2758 ifsd_map = txq->ift_sds.ifsd_map;
2761 prefetch(ifsd_m[(cidx + 3) & mask]);
2762 prefetch(ifsd_m[(cidx + 4) & mask]);
2764 if (ifsd_m[cidx] != NULL) {
2765 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
2766 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
2767 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
2769 * does it matter if it's not the TSO tag? If so we'll
2770 * have to add the type to flags
2772 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
2773 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
2775 if ((m = ifsd_m[cidx]) != NULL) {
2776 /* XXX we don't support any drivers that batch packets yet */
2777 MPASS(m->m_nextpkt == NULL);
2780 ifsd_m[cidx] = NULL;
2782 txq->ift_dequeued++;
2784 DBG_COUNTER_INC(tx_frees);
2787 if (__predict_false(++cidx == qsize)) {
2792 txq->ift_cidx = cidx;
2797 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
2800 if_ctx_t ctx = txq->ift_ctx;
2802 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
2803 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
2806 * Need a rate-limiting check so that this isn't called every time
2808 iflib_tx_credits_update(ctx, txq);
2809 reclaim = DESC_RECLAIMABLE(txq);
2811 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
2813 if (iflib_verbose_debug) {
2814 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
2815 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
2822 iflib_tx_desc_free(txq, reclaim);
2823 txq->ift_cleaned += reclaim;
2824 txq->ift_in_use -= reclaim;
2826 if (txq->ift_active == FALSE)
2827 txq->ift_active = TRUE;
2832 static struct mbuf **
2833 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset)
2836 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (r->size-1)]));
2840 iflib_txq_check_drain(iflib_txq_t txq, int budget)
2843 ifmp_ring_check_drainage(txq->ift_br[0], budget);
2847 iflib_txq_can_drain(struct ifmp_ring *r)
2849 iflib_txq_t txq = r->cookie;
2850 if_ctx_t ctx = txq->ift_ctx;
2852 return ((TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx)) ||
2853 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, false));
2857 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
2859 iflib_txq_t txq = r->cookie;
2860 if_ctx_t ctx = txq->ift_ctx;
2861 if_t ifp = ctx->ifc_ifp;
2862 struct mbuf **mp, *m;
2863 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail, err, in_use_prev, desc_used;
2865 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
2866 !LINK_ACTIVE(ctx))) {
2867 DBG_COUNTER_INC(txq_drain_notready);
2871 avail = IDXDIFF(pidx, cidx, r->size);
2872 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
2873 DBG_COUNTER_INC(txq_drain_flushing);
2874 for (i = 0; i < avail; i++) {
2875 m_free(r->items[(cidx + i) & (r->size-1)]);
2876 r->items[(cidx + i) & (r->size-1)] = NULL;
2880 iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
2881 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
2882 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
2884 callout_stop(&txq->ift_timer);
2885 callout_stop(&txq->ift_db_check);
2886 CALLOUT_UNLOCK(txq);
2887 DBG_COUNTER_INC(txq_drain_oactive);
2890 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
2891 count = MIN(avail, TX_BATCH_SIZE);
2893 for (desc_used = i = 0; i < count && TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2; i++) {
2894 mp = _ring_peek_one(r, cidx, i);
2895 in_use_prev = txq->ift_in_use;
2896 err = iflib_encap(txq, mp);
2898 * What other errors should we bail out for?
2900 if (err == ENOBUFS) {
2901 DBG_COUNTER_INC(txq_drain_encapfail);
2910 DBG_COUNTER_INC(tx_sent);
2911 bytes_sent += m->m_pkthdr.len;
2912 if (m->m_flags & M_MCAST)
2915 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
2916 desc_used += (txq->ift_in_use - in_use_prev);
2917 iflib_txd_db_check(ctx, txq, FALSE);
2918 ETHER_BPF_MTAP(ifp, m);
2919 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
2922 if (desc_used > TXQ_MAX_DB_CONSUMED(txq->ift_size))
2926 if ((iflib_min_tx_latency || iflib_txq_min_occupancy(txq)) && txq->ift_db_pending)
2927 iflib_txd_db_check(ctx, txq, TRUE);
2928 else if ((txq->ift_db_pending || TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)) &&
2929 (callout_pending(&txq->ift_db_check) == 0)) {
2930 txq->ift_db_pending_queued = txq->ift_db_pending;
2931 callout_reset_on(&txq->ift_db_check, 1, iflib_txd_deferred_db_check,
2932 txq, txq->ift_db_check.c_cpu);
2934 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
2935 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
2937 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
2943 _task_fn_tx(void *context)
2945 iflib_txq_t txq = context;
2946 if_ctx_t ctx = txq->ift_ctx;
2948 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2950 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE);
2954 _task_fn_rx(void *context)
2956 iflib_rxq_t rxq = context;
2957 if_ctx_t ctx = rxq->ifr_ctx;
2961 DBG_COUNTER_INC(task_fn_rxs);
2962 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
2965 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) {
2966 if (ctx->ifc_flags & IFC_LEGACY)
2967 IFDI_INTR_ENABLE(ctx);
2969 DBG_COUNTER_INC(rx_intr_enables);
2970 rc = IFDI_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
2971 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
2974 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
2977 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2981 _task_fn_admin(void *context)
2983 if_ctx_t ctx = context;
2984 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2988 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2992 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
2994 callout_stop(&txq->ift_timer);
2995 CALLOUT_UNLOCK(txq);
2997 IFDI_UPDATE_ADMIN_STATUS(ctx);
2998 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2999 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3000 IFDI_LINK_INTR_ENABLE(ctx);
3003 if (LINK_ACTIVE(ctx) == 0)
3005 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3006 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3011 _task_fn_iov(void *context)
3013 if_ctx_t ctx = context;
3015 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3019 IFDI_VFLR_HANDLE(ctx);
3024 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3027 if_int_delay_info_t info;
3030 info = (if_int_delay_info_t)arg1;
3031 ctx = info->iidi_ctx;
3032 info->iidi_req = req;
3033 info->iidi_oidp = oidp;
3035 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3040 /*********************************************************************
3044 **********************************************************************/
3047 iflib_if_init_locked(if_ctx_t ctx)
3050 iflib_init_locked(ctx);
3055 iflib_if_init(void *arg)
3060 iflib_if_init_locked(ctx);
3065 iflib_if_transmit(if_t ifp, struct mbuf *m)
3067 if_ctx_t ctx = if_getsoftc(ifp);
3072 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3073 DBG_COUNTER_INC(tx_frees);
3078 MPASS(m->m_nextpkt == NULL);
3080 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3081 qidx = QIDX(ctx, m);
3083 * XXX calculate buf_ring based on flowid (divvy up bits?)
3085 txq = &ctx->ifc_txqs[qidx];
3087 #ifdef DRIVER_BACKPRESSURE
3088 if (txq->ift_closed) {
3090 next = m->m_nextpkt;
3091 m->m_nextpkt = NULL;
3104 next = next->m_nextpkt;
3105 } while (next != NULL);
3107 if (count > nitems(marr))
3108 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3109 /* XXX check nextpkt */
3111 /* XXX simplify for now */
3112 DBG_COUNTER_INC(tx_frees);
3115 for (next = m, i = 0; next != NULL; i++) {
3117 next = next->m_nextpkt;
3118 mp[i]->m_nextpkt = NULL;
3121 DBG_COUNTER_INC(tx_seen);
3122 err = ifmp_ring_enqueue(txq->ift_br[0], (void **)&m, 1, TX_BATCH_SIZE);
3125 GROUPTASK_ENQUEUE(&txq->ift_task);
3126 /* support forthcoming later */
3127 #ifdef DRIVER_BACKPRESSURE
3128 txq->ift_closed = TRUE;
3130 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE);
3132 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) {
3133 GROUPTASK_ENQUEUE(&txq->ift_task);
3140 iflib_if_qflush(if_t ifp)
3142 if_ctx_t ctx = if_getsoftc(ifp);
3143 iflib_txq_t txq = ctx->ifc_txqs;
3147 ctx->ifc_flags |= IFC_QFLUSH;
3149 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3150 while (!(ifmp_ring_is_idle(txq->ift_br[0]) || ifmp_ring_is_stalled(txq->ift_br[0])))
3151 iflib_txq_check_drain(txq, 0);
3153 ctx->ifc_flags &= ~IFC_QFLUSH;
3160 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3161 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \
3162 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3164 #define IFCAP_REINIT IFCAP_FLAGS
3167 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3169 if_ctx_t ctx = if_getsoftc(ifp);
3170 struct ifreq *ifr = (struct ifreq *)data;
3171 #if defined(INET) || defined(INET6)
3172 struct ifaddr *ifa = (struct ifaddr *)data;
3174 bool avoid_reset = FALSE;
3175 int err = 0, reinit = 0, bits;
3180 if (ifa->ifa_addr->sa_family == AF_INET)
3184 if (ifa->ifa_addr->sa_family == AF_INET6)
3188 ** Calling init results in link renegotiation,
3189 ** so we avoid doing it when possible.
3192 if_setflagbits(ifp, IFF_UP,0);
3193 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3196 if (!(if_getflags(ifp) & IFF_NOARP))
3197 arp_ifinit(ifp, ifa);
3200 err = ether_ioctl(ifp, command, data);
3204 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3208 bits = if_getdrvflags(ifp);
3209 /* stop the driver and free any clusters before proceeding */
3212 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3213 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3214 ctx->ifc_flags |= IFC_MULTISEG;
3216 ctx->ifc_flags &= ~IFC_MULTISEG;
3217 err = if_setmtu(ifp, ifr->ifr_mtu);
3219 iflib_init_locked(ctx);
3220 if_setdrvflags(ifp, bits);
3225 if (if_getflags(ifp) & IFF_UP) {
3226 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3227 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3228 (IFF_PROMISC | IFF_ALLMULTI)) {
3229 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3233 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3236 ctx->ifc_if_flags = if_getflags(ifp);
3243 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3245 IFDI_INTR_DISABLE(ctx);
3246 IFDI_MULTI_SET(ctx);
3247 IFDI_INTR_ENABLE(ctx);
3253 IFDI_MEDIA_SET(ctx);
3257 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3261 struct ifi2creq i2c;
3263 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3266 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3270 if (i2c.len > sizeof(i2c.data)) {
3275 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3276 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3283 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3286 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3288 setmask |= (mask & IFCAP_FLAGS);
3290 if ((mask & IFCAP_WOL) &&
3291 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3292 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3295 * want to ensure that traffic has stopped before we change any of the flags
3299 bits = if_getdrvflags(ifp);
3300 if (setmask & IFCAP_REINIT)
3302 if_togglecapenable(ifp, setmask);
3303 if (setmask & IFCAP_REINIT)
3304 iflib_init_locked(ctx);
3305 if_setdrvflags(ifp, bits);
3310 case SIOCGPRIVATE_0:
3314 err = IFDI_PRIV_IOCTL(ctx, command, data);
3318 err = ether_ioctl(ifp, command, data);
3327 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3329 if_ctx_t ctx = if_getsoftc(ifp);
3331 return (IFDI_GET_COUNTER(ctx, cnt));
3334 /*********************************************************************
3336 * OTHER FUNCTIONS EXPORTED TO THE STACK
3338 **********************************************************************/
3341 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
3343 if_ctx_t ctx = if_getsoftc(ifp);
3345 if ((void *)ctx != arg)
3348 if ((vtag == 0) || (vtag > 4095))
3352 IFDI_VLAN_REGISTER(ctx, vtag);
3353 /* Re-init to load the changes */
3354 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3355 iflib_init_locked(ctx);
3360 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
3362 if_ctx_t ctx = if_getsoftc(ifp);
3364 if ((void *)ctx != arg)
3367 if ((vtag == 0) || (vtag > 4095))
3371 IFDI_VLAN_UNREGISTER(ctx, vtag);
3372 /* Re-init to load the changes */
3373 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3374 iflib_init_locked(ctx);
3379 iflib_led_func(void *arg, int onoff)
3384 IFDI_LED_FUNC(ctx, onoff);
3388 /*********************************************************************
3390 * BUS FUNCTION DEFINITIONS
3392 **********************************************************************/
3395 iflib_device_probe(device_t dev)
3397 pci_vendor_info_t *ent;
3399 uint16_t pci_vendor_id, pci_device_id;
3400 uint16_t pci_subvendor_id, pci_subdevice_id;
3401 uint16_t pci_rev_id;
3402 if_shared_ctx_t sctx;
3404 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3407 pci_vendor_id = pci_get_vendor(dev);
3408 pci_device_id = pci_get_device(dev);
3409 pci_subvendor_id = pci_get_subvendor(dev);
3410 pci_subdevice_id = pci_get_subdevice(dev);
3411 pci_rev_id = pci_get_revid(dev);
3412 if (sctx->isc_parse_devinfo != NULL)
3413 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
3415 ent = sctx->isc_vendor_info;
3416 while (ent->pvi_vendor_id != 0) {
3417 if (pci_vendor_id != ent->pvi_vendor_id) {
3421 if ((pci_device_id == ent->pvi_device_id) &&
3422 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
3423 (ent->pvi_subvendor_id == 0)) &&
3424 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
3425 (ent->pvi_subdevice_id == 0)) &&
3426 ((pci_rev_id == ent->pvi_rev_id) ||
3427 (ent->pvi_rev_id == 0))) {
3429 device_set_desc_copy(dev, ent->pvi_name);
3430 /* this needs to be changed to zero if the bus probing code
3431 * ever stops re-probing on best match because the sctx
3432 * may have its values over written by register calls
3433 * in subsequent probes
3435 return (BUS_PROBE_DEFAULT);
3443 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
3445 int err, rid, msix, msix_bar;
3448 if_softc_ctx_t scctx;
3454 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
3457 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
3458 device_set_softc(dev, ctx);
3459 ctx->ifc_flags |= IFC_SC_ALLOCATED;
3462 ctx->ifc_sctx = sctx;
3464 ctx->ifc_txrx = *sctx->isc_txrx;
3465 ctx->ifc_softc = sc;
3467 if ((err = iflib_register(ctx)) != 0) {
3468 device_printf(dev, "iflib_register failed %d\n", err);
3471 iflib_add_device_sysctl_pre(ctx);
3473 scctx = &ctx->ifc_softc_ctx;
3475 * XXX sanity check that ntxd & nrxd are a power of 2
3477 if (ctx->ifc_sysctl_ntxqs != 0)
3478 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
3479 if (ctx->ifc_sysctl_nrxqs != 0)
3480 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
3482 for (i = 0; i < sctx->isc_ntxqs; i++) {
3483 if (ctx->ifc_sysctl_ntxds[i] != 0)
3484 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
3486 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
3489 for (i = 0; i < sctx->isc_nrxqs; i++) {
3490 if (ctx->ifc_sysctl_nrxds[i] != 0)
3491 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
3493 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
3496 for (i = 0; i < sctx->isc_nrxqs; i++) {
3497 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
3498 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
3499 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
3500 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
3502 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
3503 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
3504 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
3505 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
3509 for (i = 0; i < sctx->isc_ntxqs; i++) {
3510 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
3511 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
3512 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
3513 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
3515 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
3516 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
3517 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
3518 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
3522 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
3523 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
3526 if (scctx->isc_ntxqsets_max)
3527 scctx->isc_ntxqsets = min(scctx->isc_ntxqsets, scctx->isc_ntxqsets_max);
3528 if (scctx->isc_nrxqsets_max)
3529 scctx->isc_nrxqsets = min(scctx->isc_nrxqsets, scctx->isc_nrxqsets_max);
3532 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
3533 ctx->ifc_flags |= IFC_DMAR;
3536 msix_bar = scctx->isc_msix_bar;
3540 if(sctx->isc_flags & IFLIB_HAS_TXCQ)
3545 if(sctx->isc_flags & IFLIB_HAS_RXCQ)
3550 /* XXX change for per-queue sizes */
3551 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
3552 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
3553 for (i = 0; i < sctx->isc_nrxqs; i++) {
3554 if (!powerof2(scctx->isc_nrxd[i])) {
3555 /* round down instead? */
3556 device_printf(dev, "# rx descriptors must be a power of 2\n");
3561 for (i = 0; i < sctx->isc_ntxqs; i++) {
3562 if (!powerof2(scctx->isc_ntxd[i])) {
3564 "# tx descriptors must be a power of 2");
3570 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
3571 MAX_SINGLE_PACKET_FRACTION)
3572 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
3573 MAX_SINGLE_PACKET_FRACTION);
3574 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
3575 MAX_SINGLE_PACKET_FRACTION)
3576 scctx->isc_tx_tso_segments_max = max(1,
3577 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
3580 * Protect the stack against modern hardware
3582 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
3583 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
3585 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
3586 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
3587 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
3588 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
3589 if (scctx->isc_rss_table_size == 0)
3590 scctx->isc_rss_table_size = 64;
3591 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
3593 ** Now setup MSI or MSI/X, should
3594 ** return us the number of supported
3595 ** vectors. (Will be 1 for MSI)
3597 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
3598 msix = scctx->isc_vectors;
3599 } else if (scctx->isc_msix_bar != 0)
3600 msix = iflib_msix_init(ctx);
3602 scctx->isc_vectors = 1;
3603 scctx->isc_ntxqsets = 1;
3604 scctx->isc_nrxqsets = 1;
3605 scctx->isc_intr = IFLIB_INTR_LEGACY;
3608 /* Get memory for the station queues */
3609 if ((err = iflib_queues_alloc(ctx))) {
3610 device_printf(dev, "Unable to allocate queue memory\n");
3614 if ((err = iflib_qset_structures_setup(ctx))) {
3615 device_printf(dev, "qset structure setup failed %d\n", err);
3619 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
3620 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
3621 goto fail_intr_free;
3625 if (scctx->isc_intr == IFLIB_INTR_MSI) {
3629 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
3630 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
3631 goto fail_intr_free;
3634 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
3635 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
3636 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
3639 if ((err = iflib_netmap_attach(ctx))) {
3640 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
3645 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
3646 iflib_add_device_sysctl_post(ctx);
3649 ether_ifdetach(ctx->ifc_ifp);
3651 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
3652 pci_release_msi(ctx->ifc_dev);
3654 /* XXX free queues */
3661 iflib_device_attach(device_t dev)
3664 if_shared_ctx_t sctx;
3666 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3669 pci_enable_busmaster(dev);
3671 return (iflib_device_register(dev, NULL, sctx, &ctx));
3675 iflib_device_deregister(if_ctx_t ctx)
3677 if_t ifp = ctx->ifc_ifp;
3680 device_t dev = ctx->ifc_dev;
3682 struct taskqgroup *tqg;
3684 /* Make sure VLANS are not using driver */
3685 if (if_vlantrunkinuse(ifp)) {
3686 device_printf(dev,"Vlan in use, detach first\n");
3691 ctx->ifc_in_detach = 1;
3695 /* Unregister VLAN events */
3696 if (ctx->ifc_vlan_attach_event != NULL)
3697 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
3698 if (ctx->ifc_vlan_detach_event != NULL)
3699 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
3701 iflib_netmap_detach(ifp);
3702 ether_ifdetach(ifp);
3703 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
3704 CTX_LOCK_DESTROY(ctx);
3705 if (ctx->ifc_led_dev != NULL)
3706 led_destroy(ctx->ifc_led_dev);
3707 /* XXX drain any dependent tasks */
3708 tqg = qgroup_softirq;
3709 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
3710 callout_drain(&txq->ift_timer);
3711 callout_drain(&txq->ift_db_check);
3712 if (txq->ift_task.gt_uniq != NULL)
3713 taskqgroup_detach(tqg, &txq->ift_task);
3715 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
3716 if (rxq->ifr_task.gt_uniq != NULL)
3717 taskqgroup_detach(tqg, &rxq->ifr_task);
3719 tqg = qgroup_if_config_tqg;
3720 if (ctx->ifc_admin_task.gt_uniq != NULL)
3721 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
3722 if (ctx->ifc_vflr_task.gt_uniq != NULL)
3723 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
3726 device_set_softc(ctx->ifc_dev, NULL);
3727 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
3728 pci_release_msi(dev);
3730 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
3731 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
3733 if (ctx->ifc_msix_mem != NULL) {
3734 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
3735 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
3736 ctx->ifc_msix_mem = NULL;
3739 bus_generic_detach(dev);
3742 iflib_tx_structures_free(ctx);
3743 iflib_rx_structures_free(ctx);
3744 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
3745 free(ctx->ifc_softc, M_IFLIB);
3752 iflib_device_detach(device_t dev)
3754 if_ctx_t ctx = device_get_softc(dev);
3756 return (iflib_device_deregister(ctx));
3760 iflib_device_suspend(device_t dev)
3762 if_ctx_t ctx = device_get_softc(dev);
3768 return bus_generic_suspend(dev);
3771 iflib_device_shutdown(device_t dev)
3773 if_ctx_t ctx = device_get_softc(dev);
3779 return bus_generic_suspend(dev);
3784 iflib_device_resume(device_t dev)
3786 if_ctx_t ctx = device_get_softc(dev);
3787 iflib_txq_t txq = ctx->ifc_txqs;
3791 iflib_init_locked(ctx);
3793 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
3794 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3796 return (bus_generic_resume(dev));
3800 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
3803 if_ctx_t ctx = device_get_softc(dev);
3806 error = IFDI_IOV_INIT(ctx, num_vfs, params);
3813 iflib_device_iov_uninit(device_t dev)
3815 if_ctx_t ctx = device_get_softc(dev);
3818 IFDI_IOV_UNINIT(ctx);
3823 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
3826 if_ctx_t ctx = device_get_softc(dev);
3829 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
3835 /*********************************************************************
3837 * MODULE FUNCTION DEFINITIONS
3839 **********************************************************************/
3842 * - Start a fast taskqueue thread for each core
3843 * - Start a taskqueue for control operations
3846 iflib_module_init(void)
3852 iflib_module_event_handler(module_t mod, int what, void *arg)
3858 if ((err = iflib_module_init()) != 0)
3864 return (EOPNOTSUPP);
3870 /*********************************************************************
3872 * PUBLIC FUNCTION DEFINITIONS
3873 * ordered as in iflib.h
3875 **********************************************************************/
3879 _iflib_assert(if_shared_ctx_t sctx)
3881 MPASS(sctx->isc_tx_maxsize);
3882 MPASS(sctx->isc_tx_maxsegsize);
3884 MPASS(sctx->isc_rx_maxsize);
3885 MPASS(sctx->isc_rx_nsegments);
3886 MPASS(sctx->isc_rx_maxsegsize);
3889 MPASS(sctx->isc_txrx->ift_txd_encap);
3890 MPASS(sctx->isc_txrx->ift_txd_flush);
3891 MPASS(sctx->isc_txrx->ift_txd_credits_update);
3892 MPASS(sctx->isc_txrx->ift_rxd_available);
3893 MPASS(sctx->isc_txrx->ift_rxd_pkt_get);
3894 MPASS(sctx->isc_txrx->ift_rxd_refill);
3895 MPASS(sctx->isc_txrx->ift_rxd_flush);
3897 MPASS(sctx->isc_nrxd_min[0]);
3898 MPASS(sctx->isc_nrxd_max[0]);
3899 MPASS(sctx->isc_nrxd_default[0]);
3900 MPASS(sctx->isc_ntxd_min[0]);
3901 MPASS(sctx->isc_ntxd_max[0]);
3902 MPASS(sctx->isc_ntxd_default[0]);
3906 iflib_register(if_ctx_t ctx)
3908 if_shared_ctx_t sctx = ctx->ifc_sctx;
3909 driver_t *driver = sctx->isc_driver;
3910 device_t dev = ctx->ifc_dev;
3913 _iflib_assert(sctx);
3915 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
3917 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
3919 device_printf(dev, "can not allocate ifnet structure\n");
3924 * Initialize our context's device specific methods
3926 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
3927 kobj_class_compile((kobj_class_t) driver);
3930 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3931 if_setsoftc(ifp, ctx);
3932 if_setdev(ifp, dev);
3933 if_setinitfn(ifp, iflib_if_init);
3934 if_setioctlfn(ifp, iflib_if_ioctl);
3935 if_settransmitfn(ifp, iflib_if_transmit);
3936 if_setqflushfn(ifp, iflib_if_qflush);
3937 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3939 if_setcapabilities(ifp, 0);
3940 if_setcapenable(ifp, 0);
3942 ctx->ifc_vlan_attach_event =
3943 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
3944 EVENTHANDLER_PRI_FIRST);
3945 ctx->ifc_vlan_detach_event =
3946 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
3947 EVENTHANDLER_PRI_FIRST);
3949 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
3950 iflib_media_change, iflib_media_status);
3957 iflib_queues_alloc(if_ctx_t ctx)
3959 if_shared_ctx_t sctx = ctx->ifc_sctx;
3960 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
3961 device_t dev = ctx->ifc_dev;
3962 int nrxqsets = scctx->isc_nrxqsets;
3963 int ntxqsets = scctx->isc_ntxqsets;
3966 iflib_fl_t fl = NULL;
3967 int i, j, cpu, err, txconf, rxconf;
3968 iflib_dma_info_t ifdip;
3969 uint32_t *rxqsizes = scctx->isc_rxqsizes;
3970 uint32_t *txqsizes = scctx->isc_txqsizes;
3971 uint8_t nrxqs = sctx->isc_nrxqs;
3972 uint8_t ntxqs = sctx->isc_ntxqs;
3973 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
3976 struct ifmp_ring **brscp;
3977 int nbuf_rings = 1; /* XXX determine dynamically */
3979 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
3980 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
3986 /* Allocate the TX ring struct memory */
3988 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
3989 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
3990 device_printf(dev, "Unable to allocate TX ring memory\n");
3995 /* Now allocate the RX */
3997 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
3998 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
3999 device_printf(dev, "Unable to allocate RX ring memory\n");
4003 if (!(brscp = malloc(sizeof(void *) * nbuf_rings * nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4004 device_printf(dev, "Unable to buf_ring_sc * memory\n");
4009 ctx->ifc_txqs = txq;
4010 ctx->ifc_rxqs = rxq;
4013 * XXX handle allocation failure
4015 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4016 /* Set up some basics */
4018 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4019 device_printf(dev, "failed to allocate iflib_dma_info\n");
4023 txq->ift_ifdi = ifdip;
4024 for (j = 0; j < ntxqs; j++, ifdip++) {
4025 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4026 device_printf(dev, "Unable to allocate Descriptor memory\n");
4030 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4034 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4035 txq->ift_br_offset = 1;
4037 txq->ift_br_offset = 0;
4040 txq->ift_timer.c_cpu = cpu;
4041 txq->ift_db_check.c_cpu = cpu;
4042 txq->ift_nbr = nbuf_rings;
4044 if (iflib_txsd_alloc(txq)) {
4045 device_printf(dev, "Critical Failure setting up TX buffers\n");
4050 /* Initialize the TX lock */
4051 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4052 device_get_nameunit(dev), txq->ift_id);
4053 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4054 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4055 callout_init_mtx(&txq->ift_db_check, &txq->ift_mtx, 0);
4057 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4058 device_get_nameunit(dev), txq->ift_id);
4059 TXDB_LOCK_INIT(txq);
4061 txq->ift_br = brscp + i*nbuf_rings;
4062 for (j = 0; j < nbuf_rings; j++) {
4063 err = ifmp_ring_alloc(&txq->ift_br[j], 2048, txq, iflib_txq_drain,
4064 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4066 /* XXX free any allocated rings */
4067 device_printf(dev, "Unable to allocate buf_ring\n");
4073 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4074 /* Set up some basics */
4076 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4077 device_printf(dev, "failed to allocate iflib_dma_info\n");
4082 rxq->ifr_ifdi = ifdip;
4083 for (j = 0; j < nrxqs; j++, ifdip++) {
4084 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4085 device_printf(dev, "Unable to allocate Descriptor memory\n");
4089 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4093 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4094 rxq->ifr_fl_offset = 1;
4096 rxq->ifr_fl_offset = 0;
4098 rxq->ifr_nfl = nfree_lists;
4100 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4101 device_printf(dev, "Unable to allocate free list memory\n");
4106 for (j = 0; j < nfree_lists; j++) {
4107 rxq->ifr_fl[j].ifl_rxq = rxq;
4108 rxq->ifr_fl[j].ifl_id = j;
4109 rxq->ifr_fl[j].ifl_ifdi =
4110 &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4112 /* Allocate receive buffers for the ring*/
4113 if (iflib_rxsd_alloc(rxq)) {
4115 "Critical Failure setting up receive buffers\n");
4122 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4123 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4124 for (i = 0; i < ntxqsets; i++) {
4125 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4127 for (j = 0; j < ntxqs; j++, di++) {
4128 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4129 paddrs[i*ntxqs + j] = di->idi_paddr;
4132 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4133 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4134 iflib_tx_structures_free(ctx);
4135 free(vaddrs, M_IFLIB);
4136 free(paddrs, M_IFLIB);
4139 free(vaddrs, M_IFLIB);
4140 free(paddrs, M_IFLIB);
4143 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4144 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4145 for (i = 0; i < nrxqsets; i++) {
4146 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4148 for (j = 0; j < nrxqs; j++, di++) {
4149 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4150 paddrs[i*nrxqs + j] = di->idi_paddr;
4153 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4154 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4155 iflib_tx_structures_free(ctx);
4156 free(vaddrs, M_IFLIB);
4157 free(paddrs, M_IFLIB);
4160 free(vaddrs, M_IFLIB);
4161 free(paddrs, M_IFLIB);
4165 /* XXX handle allocation failure changes */
4168 if (ctx->ifc_rxqs != NULL)
4169 free(ctx->ifc_rxqs, M_IFLIB);
4170 ctx->ifc_rxqs = NULL;
4171 if (ctx->ifc_txqs != NULL)
4172 free(ctx->ifc_txqs, M_IFLIB);
4173 ctx->ifc_txqs = NULL;
4176 free(brscp, M_IFLIB);
4186 iflib_tx_structures_setup(if_ctx_t ctx)
4188 iflib_txq_t txq = ctx->ifc_txqs;
4191 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4192 iflib_txq_setup(txq);
4198 iflib_tx_structures_free(if_ctx_t ctx)
4200 iflib_txq_t txq = ctx->ifc_txqs;
4203 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4204 iflib_txq_destroy(txq);
4205 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4206 iflib_dma_free(&txq->ift_ifdi[j]);
4208 free(ctx->ifc_txqs, M_IFLIB);
4209 ctx->ifc_txqs = NULL;
4210 IFDI_QUEUES_FREE(ctx);
4213 /*********************************************************************
4215 * Initialize all receive rings.
4217 **********************************************************************/
4219 iflib_rx_structures_setup(if_ctx_t ctx)
4221 iflib_rxq_t rxq = ctx->ifc_rxqs;
4223 #if defined(INET6) || defined(INET)
4227 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4228 #if defined(INET6) || defined(INET)
4229 tcp_lro_free(&rxq->ifr_lc);
4230 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4231 TCP_LRO_ENTRIES, min(1024,
4232 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4233 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4236 rxq->ifr_lro_enabled = TRUE;
4238 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4241 #if defined(INET6) || defined(INET)
4244 * Free RX software descriptors allocated so far, we will only handle
4245 * the rings that completed, the failing case will have
4246 * cleaned up for itself. 'q' failed, so its the terminus.
4248 rxq = ctx->ifc_rxqs;
4249 for (i = 0; i < q; ++i, rxq++) {
4250 iflib_rx_sds_free(rxq);
4251 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4257 /*********************************************************************
4259 * Free all receive rings.
4261 **********************************************************************/
4263 iflib_rx_structures_free(if_ctx_t ctx)
4265 iflib_rxq_t rxq = ctx->ifc_rxqs;
4267 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4268 iflib_rx_sds_free(rxq);
4273 iflib_qset_structures_setup(if_ctx_t ctx)
4277 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4280 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4281 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4282 iflib_tx_structures_free(ctx);
4283 iflib_rx_structures_free(ctx);
4289 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4290 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4293 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4297 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4301 CPU_COPY(&ctx->ifc_cpus, cpus);
4302 /* clear up to the qid'th bit */
4303 for (i = 0; i < qid; i++) {
4304 cpuid = CPU_FFS(cpus);
4305 CPU_CLR(cpuid, cpus);
4310 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
4311 iflib_intr_type_t type, driver_filter_t *filter,
4312 void *filter_arg, int qid, char *name)
4314 struct grouptask *gtask;
4315 struct taskqgroup *tqg;
4316 iflib_filter_info_t info;
4322 info = &ctx->ifc_filter_info;
4325 /* XXX merge tx/rx for netmap? */
4327 q = &ctx->ifc_txqs[qid];
4328 info = &ctx->ifc_txqs[qid].ift_filter_info;
4329 gtask = &ctx->ifc_txqs[qid].ift_task;
4330 tqg = qgroup_softirq;
4331 tqrid = irq->ii_rid;
4335 q = &ctx->ifc_rxqs[qid];
4336 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4337 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4338 tqg = qgroup_softirq;
4339 tqrid = irq->ii_rid;
4342 case IFLIB_INTR_ADMIN:
4344 info = &ctx->ifc_filter_info;
4345 gtask = &ctx->ifc_admin_task;
4346 tqg = qgroup_if_config_tqg;
4348 fn = _task_fn_admin;
4351 panic("unknown net intr type");
4353 GROUPTASK_INIT(gtask, 0, fn, q);
4355 info->ifi_filter = filter;
4356 info->ifi_filter_arg = filter_arg;
4357 info->ifi_task = gtask;
4359 /* XXX query cpu that rid belongs to */
4361 err = _iflib_irq_alloc(ctx, irq, rid, iflib_fast_intr, NULL, info, name);
4365 find_nth(ctx, &cpus, qid);
4366 taskqgroup_attach_cpu(tqg, gtask, q, CPU_FFS(&cpus), irq->ii_rid, name);
4368 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4375 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name)
4377 struct grouptask *gtask;
4378 struct taskqgroup *tqg;
4384 q = &ctx->ifc_txqs[qid];
4385 gtask = &ctx->ifc_txqs[qid].ift_task;
4386 tqg = qgroup_softirq;
4390 q = &ctx->ifc_rxqs[qid];
4391 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4392 tqg = qgroup_softirq;
4395 case IFLIB_INTR_ADMIN:
4397 gtask = &ctx->ifc_admin_task;
4398 tqg = qgroup_if_config_tqg;
4400 fn = _task_fn_admin;
4402 case IFLIB_INTR_IOV:
4404 gtask = &ctx->ifc_vflr_task;
4405 tqg = qgroup_if_config_tqg;
4410 panic("unknown net intr type");
4412 GROUPTASK_INIT(gtask, 0, fn, q);
4413 taskqgroup_attach(tqg, gtask, q, rid, name);
4417 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
4420 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
4423 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
4427 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
4429 iflib_txq_t txq = ctx->ifc_txqs;
4430 iflib_rxq_t rxq = ctx->ifc_rxqs;
4431 if_irq_t irq = &ctx->ifc_legacy_irq;
4432 iflib_filter_info_t info;
4433 struct grouptask *gtask;
4434 struct taskqgroup *tqg;
4440 q = &ctx->ifc_rxqs[0];
4441 info = &rxq[0].ifr_filter_info;
4442 gtask = &rxq[0].ifr_task;
4443 tqg = qgroup_softirq;
4444 tqrid = irq->ii_rid = *rid;
4447 ctx->ifc_flags |= IFC_LEGACY;
4448 info->ifi_filter = filter;
4449 info->ifi_filter_arg = filter_arg;
4450 info->ifi_task = gtask;
4452 /* We allocate a single interrupt resource */
4453 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr, NULL, info, name)) != 0)
4455 GROUPTASK_INIT(gtask, 0, fn, q);
4456 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4458 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
4459 taskqgroup_attach(qgroup_softirq, &txq->ift_task, txq, tqrid, "tx");
4460 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4461 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin/link");
4467 iflib_led_create(if_ctx_t ctx)
4470 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
4471 device_get_nameunit(ctx->ifc_dev));
4475 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
4478 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
4482 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
4485 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
4489 iflib_admin_intr_deferred(if_ctx_t ctx)
4492 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
4496 iflib_iov_intr_deferred(if_ctx_t ctx)
4499 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
4503 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
4506 taskqgroup_attach_cpu(qgroup_softirq, gt, uniq, cpu, -1, name);
4510 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
4514 GROUPTASK_INIT(gtask, 0, fn, ctx);
4515 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
4519 iflib_config_gtask_deinit(struct grouptask *gtask)
4522 taskqgroup_detach(qgroup_if_config_tqg, gtask);
4526 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
4528 if_t ifp = ctx->ifc_ifp;
4529 iflib_txq_t txq = ctx->ifc_txqs;
4532 if_setbaudrate(ifp, baudrate);
4534 /* If link down, disable watchdog */
4535 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
4536 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
4537 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
4539 ctx->ifc_link_state = link_state;
4540 if_link_state_change(ifp, link_state);
4544 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
4548 if (ctx->isc_txd_credits_update == NULL)
4551 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, true)) == 0)
4554 txq->ift_processed += credits;
4555 txq->ift_cidx_processed += credits;
4557 if (txq->ift_cidx_processed >= txq->ift_size)
4558 txq->ift_cidx_processed -= txq->ift_size;
4563 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget)
4566 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
4571 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
4572 const char *description, if_int_delay_info_t info,
4573 int offset, int value)
4575 info->iidi_ctx = ctx;
4576 info->iidi_offset = offset;
4577 info->iidi_value = value;
4578 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
4579 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
4580 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4581 info, 0, iflib_sysctl_int_delay, "I", description);
4585 iflib_ctx_lock_get(if_ctx_t ctx)
4588 return (&ctx->ifc_mtx);
4592 iflib_msix_init(if_ctx_t ctx)
4594 device_t dev = ctx->ifc_dev;
4595 if_shared_ctx_t sctx = ctx->ifc_sctx;
4596 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4597 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
4598 int iflib_num_tx_queues, iflib_num_rx_queues;
4599 int err, admincnt, bar;
4601 iflib_num_tx_queues = scctx->isc_ntxqsets;
4602 iflib_num_rx_queues = scctx->isc_nrxqsets;
4604 bar = ctx->ifc_softc_ctx.isc_msix_bar;
4605 admincnt = sctx->isc_admin_intrcnt;
4606 /* Override by tuneable */
4607 if (enable_msix == 0)
4611 ** When used in a virtualized environment
4612 ** PCI BUSMASTER capability may not be set
4613 ** so explicity set it here and rewrite
4614 ** the ENABLE in the MSIX control register
4615 ** at this point to cause the host to
4616 ** successfully initialize us.
4619 uint16_t pci_cmd_word;
4623 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
4624 pci_cmd_word |= PCIM_CMD_BUSMASTEREN;
4625 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2);
4626 pci_find_cap(dev, PCIY_MSIX, &rid);
4627 rid += PCIR_MSIX_CTRL;
4628 msix_ctrl = pci_read_config(dev, rid, 2);
4629 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
4630 pci_write_config(dev, rid, msix_ctrl, 2);
4634 * bar == -1 => "trust me I know what I'm doing"
4635 * Some drivers are for hardware that is so shoddily
4636 * documented that no one knows which bars are which
4637 * so the developer has to map all bars. This hack
4638 * allows shoddy garbage to use msix in this framework.
4641 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
4642 SYS_RES_MEMORY, &bar, RF_ACTIVE);
4643 if (ctx->ifc_msix_mem == NULL) {
4644 /* May not be enabled */
4645 device_printf(dev, "Unable to map MSIX table \n");
4649 /* First try MSI/X */
4650 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
4651 device_printf(dev, "System has MSIX disabled \n");
4652 bus_release_resource(dev, SYS_RES_MEMORY,
4653 bar, ctx->ifc_msix_mem);
4654 ctx->ifc_msix_mem = NULL;
4658 /* use only 1 qset in debug mode */
4659 queuemsgs = min(msgs - admincnt, 1);
4661 queuemsgs = msgs - admincnt;
4663 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
4665 queues = imin(queuemsgs, rss_getnumbuckets());
4669 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
4670 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
4671 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
4673 device_printf(dev, "Unable to fetch CPU list\n");
4674 /* Figure out a reasonable auto config value */
4675 queues = min(queuemsgs, mp_ncpus);
4678 /* If we're doing RSS, clamp at the number of RSS buckets */
4679 if (queues > rss_getnumbuckets())
4680 queues = rss_getnumbuckets();
4682 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
4683 rx_queues = iflib_num_rx_queues;
4687 * We want this to be all logical CPUs by default
4689 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
4690 tx_queues = iflib_num_tx_queues;
4692 tx_queues = mp_ncpus;
4694 if (ctx->ifc_sysctl_qs_eq_override == 0) {
4696 if (tx_queues != rx_queues)
4697 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
4698 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
4700 tx_queues = min(rx_queues, tx_queues);
4701 rx_queues = min(rx_queues, tx_queues);
4704 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
4706 vectors = rx_queues + admincnt;
4707 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
4709 "Using MSIX interrupts with %d vectors\n", vectors);
4710 scctx->isc_vectors = vectors;
4711 scctx->isc_nrxqsets = rx_queues;
4712 scctx->isc_ntxqsets = tx_queues;
4713 scctx->isc_intr = IFLIB_INTR_MSIX;
4717 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
4720 vectors = pci_msi_count(dev);
4721 scctx->isc_nrxqsets = 1;
4722 scctx->isc_ntxqsets = 1;
4723 scctx->isc_vectors = vectors;
4724 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
4725 device_printf(dev,"Using an MSI interrupt\n");
4726 scctx->isc_intr = IFLIB_INTR_MSI;
4728 device_printf(dev,"Using a Legacy interrupt\n");
4729 scctx->isc_intr = IFLIB_INTR_LEGACY;
4735 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
4738 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
4741 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
4743 char *ring_state = "UNKNOWN";
4746 rc = sysctl_wire_old_buffer(req, 0);
4750 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
4755 ring_state = ring_states[state[3]];
4757 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
4758 state[0], state[1], state[2], ring_state);
4759 rc = sbuf_finish(sb);
4764 enum iflib_ndesc_handler {
4770 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
4772 if_ctx_t ctx = (void *)arg1;
4773 enum iflib_ndesc_handler type = arg2;
4774 char buf[256] = {0};
4779 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
4783 case IFLIB_NTXD_HANDLER:
4784 ndesc = ctx->ifc_sysctl_ntxds;
4786 nqs = ctx->ifc_sctx->isc_ntxqs;
4788 case IFLIB_NRXD_HANDLER:
4789 ndesc = ctx->ifc_sysctl_nrxds;
4791 nqs = ctx->ifc_sctx->isc_nrxqs;
4797 for (i=0; i<8; i++) {
4802 sprintf(strchr(buf, 0), "%d", ndesc[i]);
4805 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
4806 if (rc || req->newptr == NULL)
4809 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
4810 i++, p = strsep(&next, " ,")) {
4811 ndesc[i] = strtoul(p, NULL, 10);
4817 #define NAME_BUFLEN 32
4819 iflib_add_device_sysctl_pre(if_ctx_t ctx)
4821 device_t dev = iflib_get_dev(ctx);
4822 struct sysctl_oid_list *child, *oid_list;
4823 struct sysctl_ctx_list *ctx_list;
4824 struct sysctl_oid *node;
4826 ctx_list = device_get_sysctl_ctx(dev);
4827 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
4828 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
4829 CTLFLAG_RD, NULL, "IFLIB fields");
4830 oid_list = SYSCTL_CHILDREN(node);
4832 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
4833 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
4836 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
4837 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
4838 "# of txqs to use, 0 => use default #");
4839 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
4840 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
4841 "# of rxqs to use, 0 => use default #");
4842 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
4843 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
4844 "permit #txq != #rxq");
4846 /* XXX change for per-queue sizes */
4847 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
4848 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
4849 mp_ndesc_handler, "A",
4850 "list of # of tx descriptors to use, 0 = use default #");
4851 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
4852 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
4853 mp_ndesc_handler, "A",
4854 "list of # of rx descriptors to use, 0 = use default #");
4858 iflib_add_device_sysctl_post(if_ctx_t ctx)
4860 if_shared_ctx_t sctx = ctx->ifc_sctx;
4861 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4862 device_t dev = iflib_get_dev(ctx);
4863 struct sysctl_oid_list *child;
4864 struct sysctl_ctx_list *ctx_list;
4869 char namebuf[NAME_BUFLEN];
4871 struct sysctl_oid *queue_node, *fl_node, *node;
4872 struct sysctl_oid_list *queue_list, *fl_list;
4873 ctx_list = device_get_sysctl_ctx(dev);
4875 node = ctx->ifc_sysctl_node;
4876 child = SYSCTL_CHILDREN(node);
4878 if (scctx->isc_ntxqsets > 100)
4880 else if (scctx->isc_ntxqsets > 10)
4884 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
4885 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
4886 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
4887 CTLFLAG_RD, NULL, "Queue Name");
4888 queue_list = SYSCTL_CHILDREN(queue_node);
4890 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
4892 &txq->ift_dequeued, "total mbufs freed");
4893 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
4895 &txq->ift_enqueued, "total mbufs enqueued");
4897 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
4899 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
4900 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
4902 &txq->ift_pullups, "# of times m_pullup was called");
4903 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
4905 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
4906 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
4908 &txq->ift_no_desc_avail, "# of times no descriptors were available");
4909 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
4911 &txq->ift_map_failed, "# of times dma map failed");
4912 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
4914 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
4915 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
4917 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
4918 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
4920 &txq->ift_pidx, 1, "Producer Index");
4921 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
4923 &txq->ift_cidx, 1, "Consumer Index");
4924 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
4926 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
4927 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
4929 &txq->ift_in_use, 1, "descriptors in use");
4930 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
4932 &txq->ift_processed, "descriptors procesed for clean");
4933 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
4935 &txq->ift_cleaned, "total cleaned");
4936 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
4937 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br[0]->state),
4938 0, mp_ring_state_handler, "A", "soft ring state");
4939 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
4940 CTLFLAG_RD, &txq->ift_br[0]->enqueues,
4941 "# of enqueues to the mp_ring for this queue");
4942 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
4943 CTLFLAG_RD, &txq->ift_br[0]->drops,
4944 "# of drops in the mp_ring for this queue");
4945 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
4946 CTLFLAG_RD, &txq->ift_br[0]->starts,
4947 "# of normal consumer starts in the mp_ring for this queue");
4948 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
4949 CTLFLAG_RD, &txq->ift_br[0]->stalls,
4950 "# of consumer stalls in the mp_ring for this queue");
4951 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
4952 CTLFLAG_RD, &txq->ift_br[0]->restarts,
4953 "# of consumer restarts in the mp_ring for this queue");
4954 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
4955 CTLFLAG_RD, &txq->ift_br[0]->abdications,
4956 "# of consumer abdications in the mp_ring for this queue");
4960 if (scctx->isc_nrxqsets > 100)
4962 else if (scctx->isc_nrxqsets > 10)
4966 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
4967 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
4968 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
4969 CTLFLAG_RD, NULL, "Queue Name");
4970 queue_list = SYSCTL_CHILDREN(queue_node);
4971 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4972 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
4974 &rxq->ifr_cq_pidx, 1, "Producer Index");
4975 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
4977 &rxq->ifr_cq_cidx, 1, "Consumer Index");
4979 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
4980 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
4981 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
4982 CTLFLAG_RD, NULL, "freelist Name");
4983 fl_list = SYSCTL_CHILDREN(fl_node);
4984 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
4986 &fl->ifl_pidx, 1, "Producer Index");
4987 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
4989 &fl->ifl_cidx, 1, "Consumer Index");
4990 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
4992 &fl->ifl_credits, 1, "credits available");
4994 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
4996 &fl->ifl_m_enqueued, "mbufs allocated");
4997 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
4999 &fl->ifl_m_dequeued, "mbufs freed");
5000 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5002 &fl->ifl_cl_enqueued, "clusters allocated");
5003 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5005 &fl->ifl_cl_dequeued, "clusters freed");