2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/sockio.h>
41 #include <sys/kernel.h>
43 #include <sys/mutex.h>
44 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
64 #include <netinet/in.h>
65 #include <netinet/in_pcb.h>
66 #include <netinet/tcp_lro.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/if_ether.h>
69 #include <netinet/ip.h>
70 #include <netinet/ip6.h>
71 #include <netinet/tcp.h>
72 #include <netinet/ip_var.h>
73 #include <netinet/netdump/netdump.h>
74 #include <netinet6/ip6_var.h>
76 #include <machine/bus.h>
77 #include <machine/in_cksum.h>
82 #include <dev/led/led.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85 #include <dev/pci/pci_private.h>
87 #include <net/iflib.h>
91 #if defined(__i386__) || defined(__amd64__)
92 #include <sys/memdesc.h>
93 #include <machine/bus.h>
94 #include <machine/md_var.h>
95 #include <machine/specialreg.h>
96 #include <x86/include/busdma_impl.h>
97 #include <x86/iommu/busdma_dmar.h>
100 #include <sys/bitstring.h>
102 * enable accounting of every mbuf as it comes in to and goes out of
103 * iflib's software descriptor references
105 #define MEMORY_LOGGING 0
107 * Enable mbuf vectors for compressing long mbuf chains
112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
113 * we prefetch needs to be determined by the time spent in m_free vis a vis
114 * the cost of a prefetch. This will of course vary based on the workload:
115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
116 * is quite expensive, thus suggesting very little prefetch.
117 * - small packet forwarding which is just returning a single mbuf to
118 * UMA will typically be very fast vis a vis the cost of a memory
125 * - private structures
126 * - iflib private utility functions
128 * - vlan registry and other exported functions
129 * - iflib public core functions
133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 uint16_t ifc_nhwtxqs;
171 iflib_txq_t ifc_txqs;
172 iflib_rxq_t ifc_rxqs;
173 uint32_t ifc_if_flags;
175 uint32_t ifc_max_fl_buf_size;
180 int ifc_watchdog_events;
181 struct cdev *ifc_led_dev;
182 struct resource *ifc_msix_mem;
184 struct if_irq ifc_legacy_irq;
185 struct grouptask ifc_admin_task;
186 struct grouptask ifc_vflr_task;
187 struct iflib_filter_info ifc_filter_info;
188 struct ifmedia ifc_media;
190 struct sysctl_oid *ifc_sysctl_node;
191 uint16_t ifc_sysctl_ntxqs;
192 uint16_t ifc_sysctl_nrxqs;
193 uint16_t ifc_sysctl_qs_eq_override;
194 uint16_t ifc_sysctl_rx_budget;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 uint8_t ifc_mac[ETHER_ADDR_LEN];
212 char ifc_mtx_name[16];
217 iflib_get_softc(if_ctx_t ctx)
220 return (ctx->ifc_softc);
224 iflib_get_dev(if_ctx_t ctx)
227 return (ctx->ifc_dev);
231 iflib_get_ifp(if_ctx_t ctx)
234 return (ctx->ifc_ifp);
238 iflib_get_media(if_ctx_t ctx)
241 return (&ctx->ifc_media);
245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
252 iflib_get_softc_ctx(if_ctx_t ctx)
255 return (&ctx->ifc_softc_ctx);
259 iflib_get_sctx(if_ctx_t ctx)
262 return (ctx->ifc_sctx);
265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
272 #define RX_SW_DESC_MAP_CREATED (1 << 0)
273 #define TX_SW_DESC_MAP_CREATED (1 << 1)
274 #define RX_SW_DESC_INUSE (1 << 3)
275 #define TX_SW_DESC_MAPPED (1 << 4)
277 #define M_TOOBIG M_PROTO1
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 struct mbuf **ifsd_m; /* pkthdr mbufs */
293 /* magic number that should be high enough for any hardware */
294 #define IFLIB_MAX_TX_SEGS 128
295 /* bnxt supports 64 with hardware LRO enabled */
296 #define IFLIB_MAX_RX_SEGS 64
297 #define IFLIB_RX_COPY_THRESH 128
298 #define IFLIB_MAX_RX_REFRESH 32
299 /* The minimum descriptors per second before we start coalescing */
300 #define IFLIB_MIN_DESC_SEC 16384
301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
302 #define IFLIB_QUEUE_IDLE 0
303 #define IFLIB_QUEUE_HUNG 1
304 #define IFLIB_QUEUE_WORKING 2
305 /* maximum number of txqs that can share an rx interrupt */
306 #define IFLIB_MAX_TX_SHARED_INTR 4
308 /* this should really scale with ring size - this is a fairly arbitrary value */
309 #define TX_BATCH_SIZE 32
311 #define IFLIB_RESTART_BUDGET 8
313 #define IFC_LEGACY 0x001
314 #define IFC_QFLUSH 0x002
315 #define IFC_MULTISEG 0x004
316 #define IFC_DMAR 0x008
317 #define IFC_SC_ALLOCATED 0x010
318 #define IFC_INIT_DONE 0x020
319 #define IFC_PREFETCH 0x040
320 #define IFC_DO_RESET 0x080
321 #define IFC_DO_WATCHDOG 0x100
322 #define IFC_CHECK_HUNG 0x200
325 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
326 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
327 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
331 qidx_t ift_cidx_processed;
334 uint8_t ift_br_offset;
335 uint16_t ift_npending;
336 uint16_t ift_db_pending;
337 uint16_t ift_rs_pending;
339 uint8_t ift_txd_size[8];
340 uint64_t ift_processed;
341 uint64_t ift_cleaned;
342 uint64_t ift_cleaned_prev;
344 uint64_t ift_enqueued;
345 uint64_t ift_dequeued;
347 uint64_t ift_no_tx_dma_setup;
348 uint64_t ift_no_desc_avail;
349 uint64_t ift_mbuf_defrag_failed;
350 uint64_t ift_mbuf_defrag;
351 uint64_t ift_map_failed;
352 uint64_t ift_txd_encap_efbig;
353 uint64_t ift_pullups;
356 struct mtx ift_db_mtx;
358 /* constant values */
360 struct ifmp_ring *ift_br;
361 struct grouptask ift_task;
364 struct callout ift_timer;
366 if_txsd_vec_t ift_sds;
369 uint8_t ift_update_freq;
370 struct iflib_filter_info ift_filter_info;
371 bus_dma_tag_t ift_desc_tag;
372 bus_dma_tag_t ift_tso_desc_tag;
373 iflib_dma_info_t ift_ifdi;
374 #define MTX_NAME_LEN 16
375 char ift_mtx_name[MTX_NAME_LEN];
376 char ift_db_mtx_name[MTX_NAME_LEN];
377 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
378 #ifdef IFLIB_DIAGNOSTICS
379 uint64_t ift_cpu_exec_count[256];
381 } __aligned(CACHE_LINE_SIZE);
388 uint8_t ifl_rxd_size;
390 uint64_t ifl_m_enqueued;
391 uint64_t ifl_m_dequeued;
392 uint64_t ifl_cl_enqueued;
393 uint64_t ifl_cl_dequeued;
397 bitstr_t *ifl_rx_bitmap;
401 uint16_t ifl_buf_size;
404 iflib_rxsd_array_t ifl_sds;
407 bus_dma_tag_t ifl_desc_tag;
408 iflib_dma_info_t ifl_ifdi;
409 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
410 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
411 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
412 } __aligned(CACHE_LINE_SIZE);
415 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
421 else if (pidx < cidx)
422 used = size - cidx + pidx;
423 else if (gen == 0 && pidx == cidx)
425 else if (gen == 1 && pidx == cidx)
433 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
435 #define IDXDIFF(head, tail, wrap) \
436 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
439 /* If there is a separate completion queue -
440 * these are the cq cidx and pidx. Otherwise
447 uint8_t ifr_fl_offset;
453 uint8_t ifr_lro_enabled;
456 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
457 struct lro_ctrl ifr_lc;
458 struct grouptask ifr_task;
459 struct iflib_filter_info ifr_filter_info;
460 iflib_dma_info_t ifr_ifdi;
462 /* dynamically allocate if any drivers need a value substantially larger than this */
463 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
464 #ifdef IFLIB_DIAGNOSTICS
465 uint64_t ifr_cpu_exec_count[256];
467 } __aligned(CACHE_LINE_SIZE);
469 typedef struct if_rxsd {
471 struct mbuf **ifsd_m;
476 /* multiple of word size */
478 #define PKT_INFO_SIZE 6
479 #define RXD_INFO_SIZE 5
480 #define PKT_TYPE uint64_t
482 #define PKT_INFO_SIZE 11
483 #define RXD_INFO_SIZE 8
484 #define PKT_TYPE uint32_t
486 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
487 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
489 typedef struct if_pkt_info_pad {
490 PKT_TYPE pkt_val[PKT_INFO_SIZE];
491 } *if_pkt_info_pad_t;
492 typedef struct if_rxd_info_pad {
493 PKT_TYPE rxd_val[RXD_INFO_SIZE];
494 } *if_rxd_info_pad_t;
496 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
497 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
501 pkt_info_zero(if_pkt_info_t pi)
503 if_pkt_info_pad_t pi_pad;
505 pi_pad = (if_pkt_info_pad_t)pi;
506 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
507 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
509 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
510 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
515 rxd_info_zero(if_rxd_info_t ri)
517 if_rxd_info_pad_t ri_pad;
520 ri_pad = (if_rxd_info_pad_t)ri;
521 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
522 ri_pad->rxd_val[i] = 0;
523 ri_pad->rxd_val[i+1] = 0;
524 ri_pad->rxd_val[i+2] = 0;
525 ri_pad->rxd_val[i+3] = 0;
528 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
533 * Only allow a single packet to take up most 1/nth of the tx ring
535 #define MAX_SINGLE_PACKET_FRACTION 12
536 #define IF_BAD_DMA (bus_addr_t)-1
538 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
540 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
541 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
542 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
543 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
546 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
547 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
548 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
549 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
553 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
554 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
557 /* Our boot-time initialization hook */
558 static int iflib_module_event_handler(module_t, int, void *);
560 static moduledata_t iflib_moduledata = {
562 iflib_module_event_handler,
566 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
567 MODULE_VERSION(iflib, 1);
569 MODULE_DEPEND(iflib, pci, 1, 1, 1);
570 MODULE_DEPEND(iflib, ether, 1, 1, 1);
572 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
573 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
575 #ifndef IFLIB_DEBUG_COUNTERS
577 #define IFLIB_DEBUG_COUNTERS 1
579 #define IFLIB_DEBUG_COUNTERS 0
580 #endif /* !INVARIANTS */
583 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
584 "iflib driver parameters");
587 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
589 static int iflib_min_tx_latency = 0;
590 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
591 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
592 static int iflib_no_tx_batch = 0;
593 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
594 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
597 #if IFLIB_DEBUG_COUNTERS
599 static int iflib_tx_seen;
600 static int iflib_tx_sent;
601 static int iflib_tx_encap;
602 static int iflib_rx_allocs;
603 static int iflib_fl_refills;
604 static int iflib_fl_refills_large;
605 static int iflib_tx_frees;
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
608 &iflib_tx_seen, 0, "# tx mbufs seen");
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
610 &iflib_tx_sent, 0, "# tx mbufs sent");
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
612 &iflib_tx_encap, 0, "# tx mbufs encapped");
613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
614 &iflib_tx_frees, 0, "# tx frees");
615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
616 &iflib_rx_allocs, 0, "# rx allocations");
617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
618 &iflib_fl_refills, 0, "# refills");
619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
620 &iflib_fl_refills_large, 0, "# large refills");
623 static int iflib_txq_drain_flushing;
624 static int iflib_txq_drain_oactive;
625 static int iflib_txq_drain_notready;
626 static int iflib_txq_drain_encapfail;
628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
629 &iflib_txq_drain_flushing, 0, "# drain flushes");
630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
631 &iflib_txq_drain_oactive, 0, "# drain oactives");
632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
633 &iflib_txq_drain_notready, 0, "# drain notready");
634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
635 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
638 static int iflib_encap_load_mbuf_fail;
639 static int iflib_encap_pad_mbuf_fail;
640 static int iflib_encap_txq_avail_fail;
641 static int iflib_encap_txd_encap_fail;
643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
652 static int iflib_task_fn_rxs;
653 static int iflib_rx_intr_enables;
654 static int iflib_fast_intrs;
655 static int iflib_intr_link;
656 static int iflib_intr_msix;
657 static int iflib_rx_unavail;
658 static int iflib_rx_ctx_inactive;
659 static int iflib_rx_zero_len;
660 static int iflib_rx_if_input;
661 static int iflib_rx_mbuf_null;
662 static int iflib_rxd_flush;
664 static int iflib_verbose_debug;
666 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
667 &iflib_intr_link, 0, "# intr link calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
669 &iflib_intr_msix, 0, "# intr msix calls");
670 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
671 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
673 &iflib_rx_intr_enables, 0, "# rx intr enables");
674 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
675 &iflib_fast_intrs, 0, "# fast_intr calls");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
677 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
678 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
679 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
680 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
681 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
683 &iflib_rx_if_input, 0, "# times rxeof called if_input");
684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
685 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
686 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
687 &iflib_rxd_flush, 0, "# times rxd_flush called");
688 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
689 &iflib_verbose_debug, 0, "enable verbose debugging");
691 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
693 iflib_debug_reset(void)
695 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
696 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
697 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
698 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
699 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
700 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
701 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
702 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
703 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
704 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
708 #define DBG_COUNTER_INC(name)
709 static void iflib_debug_reset(void) {}
714 #define IFLIB_DEBUG 0
716 static void iflib_tx_structures_free(if_ctx_t ctx);
717 static void iflib_rx_structures_free(if_ctx_t ctx);
718 static int iflib_queues_alloc(if_ctx_t ctx);
719 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
720 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
721 static int iflib_qset_structures_setup(if_ctx_t ctx);
722 static int iflib_msix_init(if_ctx_t ctx);
723 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
724 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
725 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
726 static int iflib_register(if_ctx_t);
727 static void iflib_init_locked(if_ctx_t ctx);
728 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
729 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
730 static void iflib_ifmp_purge(iflib_txq_t txq);
731 static void _iflib_pre_assert(if_softc_ctx_t scctx);
732 static void iflib_stop(if_ctx_t ctx);
733 static void iflib_if_init_locked(if_ctx_t ctx);
734 #ifndef __NO_STRICT_ALIGNMENT
735 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
738 NETDUMP_DEFINE(iflib);
741 #include <sys/selinfo.h>
742 #include <net/netmap.h>
743 #include <dev/netmap/netmap_kern.h>
745 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
747 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
750 * device-specific sysctl variables:
752 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
753 * During regular operations the CRC is stripped, but on some
754 * hardware reception of frames not multiple of 64 is slower,
755 * so using crcstrip=0 helps in benchmarks.
757 * iflib_rx_miss, iflib_rx_miss_bufs:
758 * count packets that might be missed due to lost interrupts.
760 SYSCTL_DECL(_dev_netmap);
762 * The xl driver by default strips CRCs and we do not override it.
765 int iflib_crcstrip = 1;
766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
767 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
769 int iflib_rx_miss, iflib_rx_miss_bufs;
770 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
771 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
772 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
773 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
776 * Register/unregister. We are already under netmap lock.
777 * Only called on the first register or the last unregister.
780 iflib_netmap_register(struct netmap_adapter *na, int onoff)
782 struct ifnet *ifp = na->ifp;
783 if_ctx_t ctx = ifp->if_softc;
787 IFDI_INTR_DISABLE(ctx);
789 /* Tell the stack that the interface is no longer active */
790 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
795 /* enable or disable flags and callbacks in na and ifp */
797 nm_set_native_flags(na);
799 nm_clear_native_flags(na);
802 iflib_init_locked(ctx);
803 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
804 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
806 nm_clear_native_flags(na);
812 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
814 struct netmap_adapter *na = kring->na;
815 u_int const lim = kring->nkr_num_slots - 1;
816 u_int head = kring->rhead;
817 struct netmap_ring *ring = kring->ring;
819 struct if_rxd_update iru;
820 if_ctx_t ctx = rxq->ifr_ctx;
821 iflib_fl_t fl = &rxq->ifr_fl[0];
822 uint32_t refill_pidx, nic_i;
824 if (nm_i == head && __predict_true(!init))
826 iru_init(&iru, rxq, 0 /* flid */);
827 map = fl->ifl_sds.ifsd_map;
828 refill_pidx = netmap_idx_k2n(kring, nm_i);
830 * IMPORTANT: we must leave one free slot in the ring,
831 * so move head back by one unit
833 head = nm_prev(head, lim);
835 while (nm_i != head) {
836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
837 struct netmap_slot *slot = &ring->slot[nm_i];
838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
839 uint32_t nic_i_dma = refill_pidx;
840 nic_i = netmap_idx_k2n(kring, nm_i);
842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
845 return netmap_ring_reinit(kring);
847 fl->ifl_vm_addrs[tmp_pidx] = addr;
848 if (__predict_false(init) && map) {
849 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
850 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
851 /* buffer has changed, reload map */
852 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
854 slot->flags &= ~NS_BUF_CHANGED;
856 nm_i = nm_next(nm_i, lim);
857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
861 iru.iru_pidx = refill_pidx;
862 iru.iru_count = tmp_pidx+1;
863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
869 for (int n = 0; n < iru.iru_count; n++) {
870 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
871 BUS_DMASYNC_PREREAD);
872 /* XXX - change this to not use the netmap func*/
873 nic_i_dma = nm_next(nic_i_dma, lim);
877 kring->nr_hwcur = head;
880 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
882 if (__predict_true(nic_i != UINT_MAX))
883 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
888 * Reconcile kernel and user view of the transmit ring.
890 * All information is in the kring.
891 * Userspace wants to send packets up to the one before kring->rhead,
892 * kernel knows kring->nr_hwcur is the first unsent packet.
894 * Here we push packets out (as many as possible), and possibly
895 * reclaim buffers from previously completed transmission.
897 * The caller (netmap) guarantees that there is only one instance
898 * running at any time. Any interference with other driver
899 * methods should be handled by the individual drivers.
902 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
904 struct netmap_adapter *na = kring->na;
905 struct ifnet *ifp = na->ifp;
906 struct netmap_ring *ring = kring->ring;
907 u_int nm_i; /* index into the netmap ring */
908 u_int nic_i; /* index into the NIC ring */
910 u_int const lim = kring->nkr_num_slots - 1;
911 u_int const head = kring->rhead;
912 struct if_pkt_info pi;
915 * interrupts on every tx packet are expensive so request
916 * them every half ring, or where NS_REPORT is set
918 u_int report_frequency = kring->nkr_num_slots >> 1;
919 /* device-specific */
920 if_ctx_t ctx = ifp->if_softc;
921 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
923 if (txq->ift_sds.ifsd_map)
924 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
925 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
929 * First part: process new packets to send.
930 * nm_i is the current index in the netmap ring,
931 * nic_i is the corresponding index in the NIC ring.
933 * If we have packets to send (nm_i != head)
934 * iterate over the netmap ring, fetch length and update
935 * the corresponding slot in the NIC ring. Some drivers also
936 * need to update the buffer's physical address in the NIC slot
937 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
939 * The netmap_reload_map() calls is especially expensive,
940 * even when (as in this case) the tag is 0, so do only
941 * when the buffer has actually changed.
943 * If possible do not set the report/intr bit on all slots,
944 * but only a few times per ring or when NS_REPORT is set.
946 * Finally, on 10G and faster drivers, it might be useful
947 * to prefetch the next slot and txr entry.
950 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
952 pi.ipi_segs = txq->ift_segs;
953 pi.ipi_qsidx = kring->ring_id;
954 if (nm_i != head) { /* we have new packets to send */
955 nic_i = netmap_idx_k2n(kring, nm_i);
957 __builtin_prefetch(&ring->slot[nm_i]);
958 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
959 if (txq->ift_sds.ifsd_map)
960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
962 for (n = 0; nm_i != head; n++) {
963 struct netmap_slot *slot = &ring->slot[nm_i];
964 u_int len = slot->len;
966 void *addr = PNMB(na, slot, &paddr);
967 int flags = (slot->flags & NS_REPORT ||
968 nic_i == 0 || nic_i == report_frequency) ?
971 /* device-specific */
973 pi.ipi_segs[0].ds_addr = paddr;
974 pi.ipi_segs[0].ds_len = len;
978 pi.ipi_flags = flags;
980 /* Fill the slot in the NIC ring. */
981 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
983 /* prefetch for next round */
984 __builtin_prefetch(&ring->slot[nm_i + 1]);
985 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
986 if (txq->ift_sds.ifsd_map) {
987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
989 NM_CHECK_ADDR_LEN(na, addr, len);
991 if (slot->flags & NS_BUF_CHANGED) {
992 /* buffer has changed, reload map */
993 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
995 /* make sure changes to the buffer are synced */
996 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
997 BUS_DMASYNC_PREWRITE);
999 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1000 nm_i = nm_next(nm_i, lim);
1001 nic_i = nm_next(nic_i, lim);
1003 kring->nr_hwcur = head;
1005 /* synchronize the NIC ring */
1006 if (txq->ift_sds.ifsd_map)
1007 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1008 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1010 /* (re)start the tx unit up to slot nic_i (excluded) */
1011 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1015 * Second part: reclaim buffers for completed transmissions.
1017 if (iflib_tx_credits_update(ctx, txq)) {
1018 /* some tx completed, increment avail */
1019 nic_i = txq->ift_cidx_processed;
1020 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1026 * Reconcile kernel and user view of the receive ring.
1027 * Same as for the txsync, this routine must be efficient.
1028 * The caller guarantees a single invocations, but races against
1029 * the rest of the driver should be handled here.
1031 * On call, kring->rhead is the first packet that userspace wants
1032 * to keep, and kring->rcur is the wakeup point.
1033 * The kernel has previously reported packets up to kring->rtail.
1035 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1036 * of whether or not we received an interrupt.
1039 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1041 struct netmap_adapter *na = kring->na;
1042 struct netmap_ring *ring = kring->ring;
1043 uint32_t nm_i; /* index into the netmap ring */
1044 uint32_t nic_i; /* index into the NIC ring */
1046 u_int const lim = kring->nkr_num_slots - 1;
1047 u_int const head = netmap_idx_n2k(kring, kring->rhead);
1048 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1049 struct if_rxd_info ri;
1051 struct ifnet *ifp = na->ifp;
1052 if_ctx_t ctx = ifp->if_softc;
1053 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1054 iflib_fl_t fl = rxq->ifr_fl;
1056 return netmap_ring_reinit(kring);
1058 /* XXX check sync modes */
1059 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1060 if (fl->ifl_sds.ifsd_map == NULL)
1062 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1063 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1066 * First part: import newly received packets.
1068 * nm_i is the index of the next free slot in the netmap ring,
1069 * nic_i is the index of the next received packet in the NIC ring,
1070 * and they may differ in case if_init() has been called while
1071 * in netmap mode. For the receive ring we have
1073 * nic_i = rxr->next_check;
1074 * nm_i = kring->nr_hwtail (previous)
1076 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1078 * rxr->next_check is set to 0 on a ring reinit
1080 if (netmap_no_pendintr || force_update) {
1081 int crclen = iflib_crcstrip ? 0 : 4;
1084 for (i = 0; i < rxq->ifr_nfl; i++) {
1085 fl = &rxq->ifr_fl[i];
1086 nic_i = fl->ifl_cidx;
1087 nm_i = netmap_idx_n2k(kring, nic_i);
1088 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1089 for (n = 0; avail > 0; n++, avail--) {
1091 ri.iri_frags = rxq->ifr_frags;
1092 ri.iri_qsidx = kring->ring_id;
1093 ri.iri_ifp = ctx->ifc_ifp;
1094 ri.iri_cidx = nic_i;
1096 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1097 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1098 ring->slot[nm_i].flags = 0;
1099 if (fl->ifl_sds.ifsd_map)
1100 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1101 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1102 nm_i = nm_next(nm_i, lim);
1103 nic_i = nm_next(nic_i, lim);
1105 if (n) { /* update the state variables */
1106 if (netmap_no_pendintr && !force_update) {
1109 iflib_rx_miss_bufs += n;
1111 fl->ifl_cidx = nic_i;
1112 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i);
1114 kring->nr_kflags &= ~NKR_PENDINTR;
1118 * Second part: skip past packets that userspace has released.
1119 * (kring->nr_hwcur to head excluded),
1120 * and make the buffers available for reception.
1121 * As usual nm_i is the index in the netmap ring,
1122 * nic_i is the index in the NIC ring, and
1123 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1125 /* XXX not sure how this will work with multiple free lists */
1126 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
1128 return (netmap_fl_refill(rxq, kring, nm_i, false));
1132 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1134 struct ifnet *ifp = na->ifp;
1135 if_ctx_t ctx = ifp->if_softc;
1139 IFDI_INTR_ENABLE(ctx);
1141 IFDI_INTR_DISABLE(ctx);
1148 iflib_netmap_attach(if_ctx_t ctx)
1150 struct netmap_adapter na;
1151 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1153 bzero(&na, sizeof(na));
1155 na.ifp = ctx->ifc_ifp;
1156 na.na_flags = NAF_BDG_MAYSLEEP;
1157 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1158 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1160 na.num_tx_desc = scctx->isc_ntxd[0];
1161 na.num_rx_desc = scctx->isc_nrxd[0];
1162 na.nm_txsync = iflib_netmap_txsync;
1163 na.nm_rxsync = iflib_netmap_rxsync;
1164 na.nm_register = iflib_netmap_register;
1165 na.nm_intr = iflib_netmap_intr;
1166 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1167 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1168 return (netmap_attach(&na));
1172 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1174 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1175 struct netmap_slot *slot;
1177 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1180 if (txq->ift_sds.ifsd_map == NULL)
1183 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1186 * In netmap mode, set the map for the packet buffer.
1187 * NOTE: Some drivers (not this one) also need to set
1188 * the physical buffer address in the NIC ring.
1189 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1190 * netmap slot index, si
1192 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1193 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1198 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1200 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1201 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1202 struct netmap_slot *slot;
1205 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1208 nm_i = netmap_idx_n2k(kring, 0);
1209 netmap_fl_refill(rxq, kring, nm_i, true);
1212 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1215 #define iflib_netmap_txq_init(ctx, txq)
1216 #define iflib_netmap_rxq_init(ctx, rxq)
1217 #define iflib_netmap_detach(ifp)
1219 #define iflib_netmap_attach(ctx) (0)
1220 #define netmap_rx_irq(ifp, qid, budget) (0)
1221 #define netmap_tx_irq(ifp, qid) do {} while (0)
1225 #if defined(__i386__) || defined(__amd64__)
1226 static __inline void
1229 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1231 static __inline void
1232 prefetch2cachelines(void *x)
1234 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1235 #if (CACHE_LINE_SIZE < 128)
1236 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1241 #define prefetch2cachelines(x)
1245 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1249 fl = &rxq->ifr_fl[flid];
1250 iru->iru_paddrs = fl->ifl_bus_addrs;
1251 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1252 iru->iru_idxs = fl->ifl_rxd_idxs;
1253 iru->iru_qsidx = rxq->ifr_id;
1254 iru->iru_buf_size = fl->ifl_buf_size;
1255 iru->iru_flidx = fl->ifl_id;
1259 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1263 *(bus_addr_t *) arg = segs[0].ds_addr;
1267 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1270 if_shared_ctx_t sctx = ctx->ifc_sctx;
1271 device_t dev = ctx->ifc_dev;
1273 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1275 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1276 sctx->isc_q_align, 0, /* alignment, bounds */
1277 BUS_SPACE_MAXADDR, /* lowaddr */
1278 BUS_SPACE_MAXADDR, /* highaddr */
1279 NULL, NULL, /* filter, filterarg */
1282 size, /* maxsegsize */
1283 BUS_DMA_ALLOCNOW, /* flags */
1284 NULL, /* lockfunc */
1289 "%s: bus_dma_tag_create failed: %d\n",
1294 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1295 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1298 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1299 __func__, (uintmax_t)size, err);
1303 dma->idi_paddr = IF_BAD_DMA;
1304 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1305 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1306 if (err || dma->idi_paddr == IF_BAD_DMA) {
1308 "%s: bus_dmamap_load failed: %d\n",
1313 dma->idi_size = size;
1317 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1319 bus_dma_tag_destroy(dma->idi_tag);
1321 dma->idi_tag = NULL;
1327 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1330 iflib_dma_info_t *dmaiter;
1333 for (i = 0; i < count; i++, dmaiter++) {
1334 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1338 iflib_dma_free_multi(dmalist, i);
1343 iflib_dma_free(iflib_dma_info_t dma)
1345 if (dma->idi_tag == NULL)
1347 if (dma->idi_paddr != IF_BAD_DMA) {
1348 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1350 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1351 dma->idi_paddr = IF_BAD_DMA;
1353 if (dma->idi_vaddr != NULL) {
1354 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1355 dma->idi_vaddr = NULL;
1357 bus_dma_tag_destroy(dma->idi_tag);
1358 dma->idi_tag = NULL;
1362 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1365 iflib_dma_info_t *dmaiter = dmalist;
1367 for (i = 0; i < count; i++, dmaiter++)
1368 iflib_dma_free(*dmaiter);
1371 #ifdef EARLY_AP_STARTUP
1372 static const int iflib_started = 1;
1375 * We used to abuse the smp_started flag to decide if the queues have been
1376 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1377 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1378 * is set. Run a SYSINIT() strictly after that to just set a usable
1382 static int iflib_started;
1385 iflib_record_started(void *arg)
1390 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1391 iflib_record_started, NULL);
1395 iflib_fast_intr(void *arg)
1397 iflib_filter_info_t info = arg;
1398 struct grouptask *gtask = info->ifi_task;
1400 return (FILTER_HANDLED);
1402 DBG_COUNTER_INC(fast_intrs);
1403 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1404 return (FILTER_HANDLED);
1406 GROUPTASK_ENQUEUE(gtask);
1407 return (FILTER_HANDLED);
1411 iflib_fast_intr_rxtx(void *arg)
1413 iflib_filter_info_t info = arg;
1414 struct grouptask *gtask = info->ifi_task;
1415 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1416 if_ctx_t ctx = NULL;;
1420 return (FILTER_HANDLED);
1422 DBG_COUNTER_INC(fast_intrs);
1423 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1424 return (FILTER_HANDLED);
1426 MPASS(rxq->ifr_ntxqirq);
1427 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1428 qidx_t txqid = rxq->ifr_txqid[i];
1432 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1433 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1436 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1438 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1439 cidx = rxq->ifr_cq_cidx;
1441 cidx = rxq->ifr_fl[0].ifl_cidx;
1442 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1443 GROUPTASK_ENQUEUE(gtask);
1445 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1446 return (FILTER_HANDLED);
1451 iflib_fast_intr_ctx(void *arg)
1453 iflib_filter_info_t info = arg;
1454 struct grouptask *gtask = info->ifi_task;
1457 return (FILTER_HANDLED);
1459 DBG_COUNTER_INC(fast_intrs);
1460 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1461 return (FILTER_HANDLED);
1463 GROUPTASK_ENQUEUE(gtask);
1464 return (FILTER_HANDLED);
1468 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1469 driver_filter_t filter, driver_intr_t handler, void *arg,
1473 struct resource *res;
1475 device_t dev = ctx->ifc_dev;
1478 if (ctx->ifc_flags & IFC_LEGACY)
1479 flags |= RF_SHAREABLE;
1482 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1485 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1489 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1490 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1491 filter, handler, arg, &tag);
1494 "failed to setup interrupt for rid %d, name %s: %d\n",
1495 rid, name ? name : "unknown", rc);
1498 bus_describe_intr(dev, res, tag, "%s", name);
1505 /*********************************************************************
1507 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1508 * the information needed to transmit a packet on the wire. This is
1509 * called only once at attach, setup is done every reset.
1511 **********************************************************************/
1514 iflib_txsd_alloc(iflib_txq_t txq)
1516 if_ctx_t ctx = txq->ift_ctx;
1517 if_shared_ctx_t sctx = ctx->ifc_sctx;
1518 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1519 device_t dev = ctx->ifc_dev;
1520 int err, nsegments, ntsosegments;
1522 nsegments = scctx->isc_tx_nsegments;
1523 ntsosegments = scctx->isc_tx_tso_segments_max;
1524 MPASS(scctx->isc_ntxd[0] > 0);
1525 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1526 MPASS(nsegments > 0);
1527 MPASS(ntsosegments > 0);
1529 * Setup DMA descriptor areas.
1531 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1532 1, 0, /* alignment, bounds */
1533 BUS_SPACE_MAXADDR, /* lowaddr */
1534 BUS_SPACE_MAXADDR, /* highaddr */
1535 NULL, NULL, /* filter, filterarg */
1536 sctx->isc_tx_maxsize, /* maxsize */
1537 nsegments, /* nsegments */
1538 sctx->isc_tx_maxsegsize, /* maxsegsize */
1540 NULL, /* lockfunc */
1541 NULL, /* lockfuncarg */
1542 &txq->ift_desc_tag))) {
1543 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1544 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1545 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1548 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1549 1, 0, /* alignment, bounds */
1550 BUS_SPACE_MAXADDR, /* lowaddr */
1551 BUS_SPACE_MAXADDR, /* highaddr */
1552 NULL, NULL, /* filter, filterarg */
1553 scctx->isc_tx_tso_size_max, /* maxsize */
1554 ntsosegments, /* nsegments */
1555 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1557 NULL, /* lockfunc */
1558 NULL, /* lockfuncarg */
1559 &txq->ift_tso_desc_tag))) {
1560 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1564 if (!(txq->ift_sds.ifsd_flags =
1565 (uint8_t *) malloc(sizeof(uint8_t) *
1566 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1567 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1571 if (!(txq->ift_sds.ifsd_m =
1572 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1573 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1574 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1579 /* Create the descriptor buffer dma maps */
1580 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1581 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1584 if (!(txq->ift_sds.ifsd_map =
1585 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1586 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1591 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1592 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1594 device_printf(dev, "Unable to create TX DMA map\n");
1601 /* We free all, it handles case where we are in the middle */
1602 iflib_tx_structures_free(ctx);
1607 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1612 if (txq->ift_sds.ifsd_map != NULL)
1613 map = txq->ift_sds.ifsd_map[i];
1615 bus_dmamap_unload(txq->ift_desc_tag, map);
1616 bus_dmamap_destroy(txq->ift_desc_tag, map);
1617 txq->ift_sds.ifsd_map[i] = NULL;
1622 iflib_txq_destroy(iflib_txq_t txq)
1624 if_ctx_t ctx = txq->ift_ctx;
1626 for (int i = 0; i < txq->ift_size; i++)
1627 iflib_txsd_destroy(ctx, txq, i);
1628 if (txq->ift_sds.ifsd_map != NULL) {
1629 free(txq->ift_sds.ifsd_map, M_IFLIB);
1630 txq->ift_sds.ifsd_map = NULL;
1632 if (txq->ift_sds.ifsd_m != NULL) {
1633 free(txq->ift_sds.ifsd_m, M_IFLIB);
1634 txq->ift_sds.ifsd_m = NULL;
1636 if (txq->ift_sds.ifsd_flags != NULL) {
1637 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1638 txq->ift_sds.ifsd_flags = NULL;
1640 if (txq->ift_desc_tag != NULL) {
1641 bus_dma_tag_destroy(txq->ift_desc_tag);
1642 txq->ift_desc_tag = NULL;
1644 if (txq->ift_tso_desc_tag != NULL) {
1645 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1646 txq->ift_tso_desc_tag = NULL;
1651 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1655 mp = &txq->ift_sds.ifsd_m[i];
1659 if (txq->ift_sds.ifsd_map != NULL) {
1660 bus_dmamap_sync(txq->ift_desc_tag,
1661 txq->ift_sds.ifsd_map[i],
1662 BUS_DMASYNC_POSTWRITE);
1663 bus_dmamap_unload(txq->ift_desc_tag,
1664 txq->ift_sds.ifsd_map[i]);
1667 DBG_COUNTER_INC(tx_frees);
1672 iflib_txq_setup(iflib_txq_t txq)
1674 if_ctx_t ctx = txq->ift_ctx;
1675 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1676 iflib_dma_info_t di;
1679 /* Set number of descriptors available */
1680 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1681 /* XXX make configurable */
1682 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1685 txq->ift_cidx_processed = 0;
1686 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1687 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1689 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1690 bzero((void *)di->idi_vaddr, di->idi_size);
1692 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1693 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1694 bus_dmamap_sync(di->idi_tag, di->idi_map,
1695 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1699 /*********************************************************************
1701 * Allocate memory for rx_buffer structures. Since we use one
1702 * rx_buffer per received packet, the maximum number of rx_buffer's
1703 * that we'll need is equal to the number of receive descriptors
1704 * that we've allocated.
1706 **********************************************************************/
1708 iflib_rxsd_alloc(iflib_rxq_t rxq)
1710 if_ctx_t ctx = rxq->ifr_ctx;
1711 if_shared_ctx_t sctx = ctx->ifc_sctx;
1712 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1713 device_t dev = ctx->ifc_dev;
1717 MPASS(scctx->isc_nrxd[0] > 0);
1718 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1721 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1722 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1723 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1724 1, 0, /* alignment, bounds */
1725 BUS_SPACE_MAXADDR, /* lowaddr */
1726 BUS_SPACE_MAXADDR, /* highaddr */
1727 NULL, NULL, /* filter, filterarg */
1728 sctx->isc_rx_maxsize, /* maxsize */
1729 sctx->isc_rx_nsegments, /* nsegments */
1730 sctx->isc_rx_maxsegsize, /* maxsegsize */
1732 NULL, /* lockfunc */
1736 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1740 if (!(fl->ifl_sds.ifsd_flags =
1741 (uint8_t *) malloc(sizeof(uint8_t) *
1742 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1743 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1747 if (!(fl->ifl_sds.ifsd_m =
1748 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1749 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1750 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1754 if (!(fl->ifl_sds.ifsd_cl =
1755 (caddr_t *) malloc(sizeof(caddr_t) *
1756 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1757 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1762 /* Create the descriptor buffer dma maps */
1763 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1764 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1767 if (!(fl->ifl_sds.ifsd_map =
1768 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1769 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1774 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1775 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1777 device_printf(dev, "Unable to create RX buffer DMA map\n");
1786 iflib_rx_structures_free(ctx);
1792 * Internal service routines
1795 struct rxq_refill_cb_arg {
1797 bus_dma_segment_t seg;
1802 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1804 struct rxq_refill_cb_arg *cb_arg = arg;
1806 cb_arg->error = error;
1807 cb_arg->seg = segs[0];
1808 cb_arg->nseg = nseg;
1813 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1815 #define IS_DMAR(ctx) (0)
1819 * rxq_refill - refill an rxq free-buffer list
1820 * @ctx: the iflib context
1821 * @rxq: the free-list to refill
1822 * @n: the number of new buffers to allocate
1824 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1825 * The caller must assure that @n does not exceed the queue's capacity.
1828 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1831 int idx, frag_idx = fl->ifl_fragidx;
1832 int pidx = fl->ifl_pidx;
1836 struct if_rxd_update iru;
1837 bus_dmamap_t *sd_map;
1843 sd_m = fl->ifl_sds.ifsd_m;
1844 sd_map = fl->ifl_sds.ifsd_map;
1845 sd_cl = fl->ifl_sds.ifsd_cl;
1846 sd_flags = fl->ifl_sds.ifsd_flags;
1848 credits = fl->ifl_credits;
1852 MPASS(credits + n <= fl->ifl_size);
1854 if (pidx < fl->ifl_cidx)
1855 MPASS(pidx + n <= fl->ifl_cidx);
1856 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1857 MPASS(fl->ifl_gen == 0);
1858 if (pidx > fl->ifl_cidx)
1859 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1861 DBG_COUNTER_INC(fl_refills);
1863 DBG_COUNTER_INC(fl_refills_large);
1864 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1867 * We allocate an uninitialized mbuf + cluster, mbuf is
1868 * initialized after rx.
1870 * If the cluster is still set then we know a minimum sized packet was received
1872 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1873 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1874 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1875 if ((cl = sd_cl[frag_idx]) == NULL) {
1876 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1879 fl->ifl_cl_enqueued++;
1882 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1886 fl->ifl_m_enqueued++;
1889 DBG_COUNTER_INC(rx_allocs);
1890 #if defined(__i386__) || defined(__amd64__)
1891 if (!IS_DMAR(ctx)) {
1892 bus_addr = pmap_kextract((vm_offset_t)cl);
1896 struct rxq_refill_cb_arg cb_arg;
1899 MPASS(sd_map != NULL);
1900 MPASS(sd_map[frag_idx] != NULL);
1901 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1902 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1903 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1904 BUS_DMASYNC_PREREAD);
1906 if (err != 0 || cb_arg.error) {
1910 if (fl->ifl_zone == zone_pack)
1911 uma_zfree(fl->ifl_zone, cl);
1916 bus_addr = cb_arg.seg.ds_addr;
1918 bit_set(fl->ifl_rx_bitmap, frag_idx);
1919 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1921 MPASS(sd_m[frag_idx] == NULL);
1922 sd_cl[frag_idx] = cl;
1924 fl->ifl_rxd_idxs[i] = frag_idx;
1925 fl->ifl_bus_addrs[i] = bus_addr;
1926 fl->ifl_vm_addrs[i] = cl;
1929 MPASS(credits <= fl->ifl_size);
1930 if (++idx == fl->ifl_size) {
1934 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1935 iru.iru_pidx = pidx;
1937 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1941 fl->ifl_credits = credits;
1947 iru.iru_pidx = pidx;
1949 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1951 fl->ifl_credits = credits;
1953 DBG_COUNTER_INC(rxd_flush);
1954 if (fl->ifl_pidx == 0)
1955 pidx = fl->ifl_size - 1;
1957 pidx = fl->ifl_pidx - 1;
1960 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1962 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1963 fl->ifl_fragidx = frag_idx;
1966 static __inline void
1967 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1969 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1970 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1972 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1975 MPASS(fl->ifl_credits <= fl->ifl_size);
1976 MPASS(reclaimable == delta);
1978 if (reclaimable > 0)
1979 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1983 iflib_fl_bufs_free(iflib_fl_t fl)
1985 iflib_dma_info_t idi = fl->ifl_ifdi;
1988 for (i = 0; i < fl->ifl_size; i++) {
1989 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1990 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1991 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1993 if (*sd_flags & RX_SW_DESC_INUSE) {
1994 if (fl->ifl_sds.ifsd_map != NULL) {
1995 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1996 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1997 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
1998 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2000 if (*sd_m != NULL) {
2001 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2002 uma_zfree(zone_mbuf, *sd_m);
2005 uma_zfree(fl->ifl_zone, *sd_cl);
2008 MPASS(*sd_cl == NULL);
2009 MPASS(*sd_m == NULL);
2012 fl->ifl_m_dequeued++;
2013 fl->ifl_cl_dequeued++;
2019 for (i = 0; i < fl->ifl_size; i++) {
2020 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2021 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2022 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2026 * Reset free list values
2028 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2029 bzero(idi->idi_vaddr, idi->idi_size);
2032 /*********************************************************************
2034 * Initialize a receive ring and its buffers.
2036 **********************************************************************/
2038 iflib_fl_setup(iflib_fl_t fl)
2040 iflib_rxq_t rxq = fl->ifl_rxq;
2041 if_ctx_t ctx = rxq->ifr_ctx;
2042 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2044 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2046 ** Free current RX buffer structs and their mbufs
2048 iflib_fl_bufs_free(fl);
2049 /* Now replenish the mbufs */
2050 MPASS(fl->ifl_credits == 0);
2052 * XXX don't set the max_frame_size to larger
2053 * than the hardware can handle
2055 if (sctx->isc_max_frame_size <= 2048)
2056 fl->ifl_buf_size = MCLBYTES;
2057 #ifndef CONTIGMALLOC_WORKS
2059 fl->ifl_buf_size = MJUMPAGESIZE;
2061 else if (sctx->isc_max_frame_size <= 4096)
2062 fl->ifl_buf_size = MJUMPAGESIZE;
2063 else if (sctx->isc_max_frame_size <= 9216)
2064 fl->ifl_buf_size = MJUM9BYTES;
2066 fl->ifl_buf_size = MJUM16BYTES;
2068 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2069 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2070 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2071 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2074 /* avoid pre-allocating zillions of clusters to an idle card
2075 * potentially speeding up attach
2077 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2078 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2079 if (min(128, fl->ifl_size) != fl->ifl_credits)
2085 MPASS(fl->ifl_ifdi != NULL);
2086 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2091 /*********************************************************************
2093 * Free receive ring data structures
2095 **********************************************************************/
2097 iflib_rx_sds_free(iflib_rxq_t rxq)
2102 if (rxq->ifr_fl != NULL) {
2103 for (i = 0; i < rxq->ifr_nfl; i++) {
2104 fl = &rxq->ifr_fl[i];
2105 if (fl->ifl_desc_tag != NULL) {
2106 bus_dma_tag_destroy(fl->ifl_desc_tag);
2107 fl->ifl_desc_tag = NULL;
2109 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2110 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2111 /* XXX destroy maps first */
2112 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2113 fl->ifl_sds.ifsd_m = NULL;
2114 fl->ifl_sds.ifsd_cl = NULL;
2115 fl->ifl_sds.ifsd_map = NULL;
2117 free(rxq->ifr_fl, M_IFLIB);
2119 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2124 * MI independent logic
2128 iflib_timer(void *arg)
2130 iflib_txq_t txq = arg;
2131 if_ctx_t ctx = txq->ift_ctx;
2132 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2134 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2137 ** Check on the state of the TX queue(s), this
2138 ** can be done without the lock because its RO
2139 ** and the HUNG state will be static if set.
2141 IFDI_TIMER(ctx, txq->ift_id);
2142 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2143 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2144 (sctx->isc_pause_frames == 0)))
2147 if (ifmp_ring_is_stalled(txq->ift_br))
2148 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2149 txq->ift_cleaned_prev = txq->ift_cleaned;
2150 /* handle any laggards */
2151 if (txq->ift_db_pending)
2152 GROUPTASK_ENQUEUE(&txq->ift_task);
2154 sctx->isc_pause_frames = 0;
2155 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2156 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2159 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2160 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2162 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2163 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2164 iflib_admin_intr_deferred(ctx);
2169 iflib_init_locked(if_ctx_t ctx)
2171 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2172 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2173 if_t ifp = ctx->ifc_ifp;
2177 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2180 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2181 IFDI_INTR_DISABLE(ctx);
2183 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2184 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2185 /* Set hardware offload abilities */
2186 if_clearhwassist(ifp);
2187 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2188 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2189 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2190 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2191 if (if_getcapenable(ifp) & IFCAP_TSO4)
2192 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2193 if (if_getcapenable(ifp) & IFCAP_TSO6)
2194 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2196 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2198 callout_stop(&txq->ift_timer);
2199 CALLOUT_UNLOCK(txq);
2200 iflib_netmap_txq_init(ctx, txq);
2203 i = if_getdrvflags(ifp);
2206 MPASS(if_getdrvflags(ifp) == i);
2207 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2208 /* XXX this should really be done on a per-queue basis */
2209 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2210 MPASS(rxq->ifr_id == i);
2211 iflib_netmap_rxq_init(ctx, rxq);
2214 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2215 if (iflib_fl_setup(fl)) {
2216 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2222 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2223 IFDI_INTR_ENABLE(ctx);
2224 txq = ctx->ifc_txqs;
2225 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2226 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2227 txq->ift_timer.c_cpu);
2231 iflib_media_change(if_t ifp)
2233 if_ctx_t ctx = if_getsoftc(ifp);
2237 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2238 iflib_init_locked(ctx);
2244 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2246 if_ctx_t ctx = if_getsoftc(ifp);
2249 IFDI_UPDATE_ADMIN_STATUS(ctx);
2250 IFDI_MEDIA_STATUS(ctx, ifmr);
2255 iflib_stop(if_ctx_t ctx)
2257 iflib_txq_t txq = ctx->ifc_txqs;
2258 iflib_rxq_t rxq = ctx->ifc_rxqs;
2259 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2260 iflib_dma_info_t di;
2264 /* Tell the stack that the interface is no longer active */
2265 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2267 IFDI_INTR_DISABLE(ctx);
2272 iflib_debug_reset();
2273 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2274 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2275 /* make sure all transmitters have completed before proceeding XXX */
2278 callout_stop(&txq->ift_timer);
2279 CALLOUT_UNLOCK(txq);
2281 /* clean any enqueued buffers */
2282 iflib_ifmp_purge(txq);
2283 /* Free any existing tx buffers. */
2284 for (j = 0; j < txq->ift_size; j++) {
2285 iflib_txsd_free(ctx, txq, j);
2287 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2288 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2289 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2290 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2291 txq->ift_pullups = 0;
2292 ifmp_ring_reset_stats(txq->ift_br);
2293 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2294 bzero((void *)di->idi_vaddr, di->idi_size);
2296 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2297 /* make sure all transmitters have completed before proceeding XXX */
2299 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++)
2300 bzero((void *)di->idi_vaddr, di->idi_size);
2301 /* also resets the free lists pidx/cidx */
2302 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2303 iflib_fl_bufs_free(fl);
2307 static inline caddr_t
2308 calc_next_rxd(iflib_fl_t fl, int cidx)
2312 caddr_t start, end, cur, next;
2314 nrxd = fl->ifl_size;
2315 size = fl->ifl_rxd_size;
2316 start = fl->ifl_ifdi->idi_vaddr;
2318 if (__predict_false(size == 0))
2320 cur = start + size*cidx;
2321 end = start + size*nrxd;
2322 next = CACHE_PTR_NEXT(cur);
2323 return (next < end ? next : start);
2327 prefetch_pkts(iflib_fl_t fl, int cidx)
2330 int nrxd = fl->ifl_size;
2334 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2335 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2336 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2337 next_rxd = calc_next_rxd(fl, cidx);
2339 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2340 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2341 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2342 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2343 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2344 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2345 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2346 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2350 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2355 iflib_dma_info_t di;
2359 flid = irf->irf_flid;
2360 cidx = irf->irf_idx;
2361 fl = &rxq->ifr_fl[flid];
2363 sd->ifsd_cidx = cidx;
2364 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2365 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2368 fl->ifl_m_dequeued++;
2370 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2371 prefetch_pkts(fl, cidx);
2372 if (fl->ifl_sds.ifsd_map != NULL) {
2373 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2374 prefetch(&fl->ifl_sds.ifsd_map[next]);
2375 map = fl->ifl_sds.ifsd_map[cidx];
2377 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2378 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2379 bus_dmamap_sync(di->idi_tag, di->idi_map,
2380 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2382 /* not valid assert if bxe really does SGE from non-contiguous elements */
2383 MPASS(fl->ifl_cidx == cidx);
2385 bus_dmamap_unload(fl->ifl_desc_tag, map);
2387 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2388 if (__predict_false(fl->ifl_cidx == 0))
2391 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2393 bit_clear(fl->ifl_rx_bitmap, cidx);
2396 static struct mbuf *
2397 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2399 int i, padlen , flags;
2400 struct mbuf *m, *mh, *mt;
2406 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2408 MPASS(*sd->ifsd_cl != NULL);
2409 MPASS(*sd->ifsd_m != NULL);
2411 /* Don't include zero-length frags */
2412 if (ri->iri_frags[i].irf_len == 0) {
2413 /* XXX we can save the cluster here, but not the mbuf */
2414 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2415 m_free(*sd->ifsd_m);
2422 flags = M_PKTHDR|M_EXT;
2424 padlen = ri->iri_pad;
2429 /* assuming padding is only on the first fragment */
2433 *sd->ifsd_cl = NULL;
2435 /* Can these two be made one ? */
2436 m_init(m, M_NOWAIT, MT_DATA, flags);
2437 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2439 * These must follow m_init and m_cljset
2441 m->m_data += padlen;
2442 ri->iri_len -= padlen;
2443 m->m_len = ri->iri_frags[i].irf_len;
2444 } while (++i < ri->iri_nfrags);
2450 * Process one software descriptor
2452 static struct mbuf *
2453 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2458 /* should I merge this back in now that the two paths are basically duplicated? */
2459 if (ri->iri_nfrags == 1 &&
2460 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2461 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2464 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2465 #ifndef __NO_STRICT_ALIGNMENT
2469 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2470 m->m_len = ri->iri_frags[0].irf_len;
2472 m = assemble_segments(rxq, ri, &sd);
2474 m->m_pkthdr.len = ri->iri_len;
2475 m->m_pkthdr.rcvif = ri->iri_ifp;
2476 m->m_flags |= ri->iri_flags;
2477 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2478 m->m_pkthdr.flowid = ri->iri_flowid;
2479 M_HASHTYPE_SET(m, ri->iri_rsstype);
2480 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2481 m->m_pkthdr.csum_data = ri->iri_csum_data;
2485 #if defined(INET6) || defined(INET)
2487 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2489 CURVNET_SET(lc->ifp->if_vnet);
2491 *v6 = VNET(ip6_forwarding);
2494 *v4 = VNET(ipforwarding);
2500 * Returns true if it's possible this packet could be LROed.
2501 * if it returns false, it is guaranteed that tcp_lro_rx()
2502 * would not return zero.
2505 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2507 struct ether_header *eh;
2510 eh = mtod(m, struct ether_header *);
2511 eh_type = ntohs(eh->ether_type);
2514 case ETHERTYPE_IPV6:
2515 return !v6_forwarding;
2519 return !v4_forwarding;
2527 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2533 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2535 if_ctx_t ctx = rxq->ifr_ctx;
2536 if_shared_ctx_t sctx = ctx->ifc_sctx;
2537 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2540 struct if_rxd_info ri;
2541 int err, budget_left, rx_bytes, rx_pkts;
2545 bool lro_possible = false;
2546 bool v4_forwarding, v6_forwarding;
2549 * XXX early demux data packets so that if_input processing only handles
2550 * acks in interrupt context
2552 struct mbuf *m, *mh, *mt, *mf;
2557 rx_pkts = rx_bytes = 0;
2558 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2559 cidxp = &rxq->ifr_cq_cidx;
2561 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2562 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2563 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2564 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2565 DBG_COUNTER_INC(rx_unavail);
2569 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2570 if (__predict_false(!CTX_ACTIVE(ctx))) {
2571 DBG_COUNTER_INC(rx_ctx_inactive);
2575 * Reset client set fields to their default values
2578 ri.iri_qsidx = rxq->ifr_id;
2579 ri.iri_cidx = *cidxp;
2581 ri.iri_frags = rxq->ifr_frags;
2582 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2586 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2587 *cidxp = ri.iri_cidx;
2588 /* Update our consumer index */
2589 /* XXX NB: shurd - check if this is still safe */
2590 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2591 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2592 rxq->ifr_cq_gen = 0;
2594 /* was this only a completion queue message? */
2595 if (__predict_false(ri.iri_nfrags == 0))
2598 MPASS(ri.iri_nfrags != 0);
2599 MPASS(ri.iri_len != 0);
2601 /* will advance the cidx on the corresponding free lists */
2602 m = iflib_rxd_pkt_get(rxq, &ri);
2603 if (avail == 0 && budget_left)
2604 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2606 if (__predict_false(m == NULL)) {
2607 DBG_COUNTER_INC(rx_mbuf_null);
2610 /* imm_pkt: -- cxgb */
2618 /* make sure that we can refill faster than drain */
2619 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2620 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2622 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2624 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2626 while (mh != NULL) {
2629 m->m_nextpkt = NULL;
2630 #ifndef __NO_STRICT_ALIGNMENT
2631 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2634 rx_bytes += m->m_pkthdr.len;
2636 #if defined(INET6) || defined(INET)
2638 if (!lro_possible) {
2639 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2640 if (lro_possible && mf != NULL) {
2641 ifp->if_input(ifp, mf);
2642 DBG_COUNTER_INC(rx_if_input);
2646 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2647 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2648 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2654 ifp->if_input(ifp, m);
2655 DBG_COUNTER_INC(rx_if_input);
2666 ifp->if_input(ifp, mf);
2667 DBG_COUNTER_INC(rx_if_input);
2670 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2671 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2674 * Flush any outstanding LRO work
2676 #if defined(INET6) || defined(INET)
2677 tcp_lro_flush_all(&rxq->ifr_lc);
2681 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2684 ctx->ifc_flags |= IFC_DO_RESET;
2685 iflib_admin_intr_deferred(ctx);
2690 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2691 static inline qidx_t
2692 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2694 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2695 qidx_t minthresh = txq->ift_size / 8;
2696 if (in_use > 4*minthresh)
2697 return (notify_count);
2698 if (in_use > 2*minthresh)
2699 return (notify_count >> 1);
2700 if (in_use > minthresh)
2701 return (notify_count >> 3);
2705 static inline qidx_t
2706 txq_max_rs_deferred(iflib_txq_t txq)
2708 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2709 qidx_t minthresh = txq->ift_size / 8;
2710 if (txq->ift_in_use > 4*minthresh)
2711 return (notify_count);
2712 if (txq->ift_in_use > 2*minthresh)
2713 return (notify_count >> 1);
2714 if (txq->ift_in_use > minthresh)
2715 return (notify_count >> 2);
2719 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2720 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2722 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2723 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2724 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2726 /* forward compatibility for cxgb */
2727 #define FIRST_QSET(ctx) 0
2728 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2729 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2730 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2731 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2733 /* XXX we should be setting this to something other than zero */
2734 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2735 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2738 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2744 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2745 if (ring || txq->ift_db_pending >= max) {
2746 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2747 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2748 txq->ift_db_pending = txq->ift_npending = 0;
2756 print_pkt(if_pkt_info_t pi)
2758 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2759 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2760 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2761 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2762 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2763 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2767 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2768 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2771 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2773 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2774 struct ether_vlan_header *eh;
2778 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2779 M_WRITABLE(m) == 0) {
2780 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2789 * Determine where frame payload starts.
2790 * Jump over vlan headers if already present,
2791 * helpful for QinQ too.
2793 if (__predict_false(m->m_len < sizeof(*eh))) {
2795 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2798 eh = mtod(m, struct ether_vlan_header *);
2799 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2800 pi->ipi_etype = ntohs(eh->evl_proto);
2801 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2803 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2804 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2807 switch (pi->ipi_etype) {
2811 struct ip *ip = NULL;
2812 struct tcphdr *th = NULL;
2815 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2816 if (__predict_false(m->m_len < minthlen)) {
2818 * if this code bloat is causing too much of a hit
2819 * move it to a separate function and mark it noinline
2821 if (m->m_len == pi->ipi_ehdrlen) {
2824 if (n->m_len >= sizeof(*ip)) {
2825 ip = (struct ip *)n->m_data;
2826 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2827 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2830 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2832 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2836 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2838 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2839 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2840 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2843 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2844 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2845 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2847 pi->ipi_ip_hlen = ip->ip_hl << 2;
2848 pi->ipi_ipproto = ip->ip_p;
2849 pi->ipi_flags |= IPI_TX_IPV4;
2851 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2855 if (pi->ipi_ipproto == IPPROTO_TCP) {
2856 if (__predict_false(th == NULL)) {
2858 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2860 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2862 pi->ipi_tcp_hflags = th->th_flags;
2863 pi->ipi_tcp_hlen = th->th_off << 2;
2864 pi->ipi_tcp_seq = th->th_seq;
2866 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2868 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2869 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2870 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2871 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2873 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2880 case ETHERTYPE_IPV6:
2882 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2884 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2886 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2887 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2890 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2892 /* XXX-BZ this will go badly in case of ext hdrs. */
2893 pi->ipi_ipproto = ip6->ip6_nxt;
2894 pi->ipi_flags |= IPI_TX_IPV6;
2897 if (pi->ipi_ipproto == IPPROTO_TCP) {
2898 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2899 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2902 pi->ipi_tcp_hflags = th->th_flags;
2903 pi->ipi_tcp_hlen = th->th_off << 2;
2906 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2909 * The corresponding flag is set by the stack in the IPv4
2910 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2911 * So, set it here because the rest of the flow requires it.
2913 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2914 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2915 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2921 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2922 pi->ipi_ip_hlen = 0;
2930 static __noinline struct mbuf *
2931 collapse_pkthdr(struct mbuf *m0)
2933 struct mbuf *m, *m_next, *tmp;
2937 while (m_next != NULL && m_next->m_len == 0) {
2941 m_next = m_next->m_next;
2945 if ((m_next->m_flags & M_EXT) == 0) {
2946 m = m_defrag(m, M_NOWAIT);
2948 tmp = m_next->m_next;
2949 memcpy(m_next, m, MPKTHSIZE);
2957 * If dodgy hardware rejects the scatter gather chain we've handed it
2958 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2961 static __noinline struct mbuf *
2962 iflib_remove_mbuf(iflib_txq_t txq)
2965 struct mbuf *m, *mh, **ifsd_m;
2967 pidx = txq->ift_pidx;
2968 ifsd_m = txq->ift_sds.ifsd_m;
2969 ntxd = txq->ift_size;
2970 mh = m = ifsd_m[pidx];
2971 ifsd_m[pidx] = NULL;
2973 txq->ift_dequeued++;
2978 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2980 txq->ift_dequeued++;
2989 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2990 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2991 int max_segs, int flags)
2994 if_shared_ctx_t sctx;
2995 if_softc_ctx_t scctx;
2996 int i, next, pidx, err, ntxd, count;
2997 struct mbuf *m, *tmp, **ifsd_m;
3002 * Please don't ever do this
3004 if (__predict_false(m->m_len == 0))
3005 *m0 = m = collapse_pkthdr(m);
3008 sctx = ctx->ifc_sctx;
3009 scctx = &ctx->ifc_softc_ctx;
3010 ifsd_m = txq->ift_sds.ifsd_m;
3011 ntxd = txq->ift_size;
3012 pidx = txq->ift_pidx;
3014 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3016 err = bus_dmamap_load_mbuf_sg(tag, map,
3017 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3020 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3024 if (__predict_false(m->m_len <= 0)) {
3033 } while (m != NULL);
3034 if (count > *nsegs) {
3036 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3042 next = (pidx + count) & (ntxd-1);
3043 MPASS(ifsd_m[next] == NULL);
3048 } while (m != NULL);
3050 int buflen, sgsize, maxsegsz, max_sgsize;
3056 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3057 maxsegsz = scctx->isc_tx_tso_segsize_max;
3059 maxsegsz = sctx->isc_tx_maxsegsize;
3062 if (__predict_false(m->m_len <= 0)) {
3070 vaddr = (vm_offset_t)m->m_data;
3072 * see if we can't be smarter about physically
3073 * contiguous mappings
3075 next = (pidx + count) & (ntxd-1);
3076 MPASS(ifsd_m[next] == NULL);
3078 txq->ift_enqueued++;
3081 while (buflen > 0) {
3084 max_sgsize = MIN(buflen, maxsegsz);
3085 curaddr = pmap_kextract(vaddr);
3086 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3087 sgsize = MIN(sgsize, max_sgsize);
3088 segs[i].ds_addr = curaddr;
3089 segs[i].ds_len = sgsize;
3097 } while (m != NULL);
3102 *m0 = iflib_remove_mbuf(txq);
3106 static inline caddr_t
3107 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3111 caddr_t start, end, cur, next;
3113 ntxd = txq->ift_size;
3114 size = txq->ift_txd_size[qid];
3115 start = txq->ift_ifdi[qid].idi_vaddr;
3117 if (__predict_false(size == 0))
3119 cur = start + size*cidx;
3120 end = start + size*ntxd;
3121 next = CACHE_PTR_NEXT(cur);
3122 return (next < end ? next : start);
3126 * Pad an mbuf to ensure a minimum ethernet frame size.
3127 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3129 static __noinline int
3130 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3133 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3134 * and ARP message is the smallest common payload I can think of
3136 static char pad[18]; /* just zeros */
3138 struct mbuf *new_head;
3140 if (!M_WRITABLE(*m_head)) {
3141 new_head = m_dup(*m_head, M_NOWAIT);
3142 if (new_head == NULL) {
3144 device_printf(dev, "cannot pad short frame, m_dup() failed");
3145 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3152 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3153 n > 0; n -= sizeof(pad))
3154 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3159 device_printf(dev, "cannot pad short frame\n");
3160 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3168 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3171 if_shared_ctx_t sctx;
3172 if_softc_ctx_t scctx;
3173 bus_dma_segment_t *segs;
3174 struct mbuf *m_head;
3177 struct if_pkt_info pi;
3179 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3180 bus_dma_tag_t desc_tag;
3182 segs = txq->ift_segs;
3184 sctx = ctx->ifc_sctx;
3185 scctx = &ctx->ifc_softc_ctx;
3186 segs = txq->ift_segs;
3187 ntxd = txq->ift_size;
3192 * If we're doing TSO the next descriptor to clean may be quite far ahead
3194 cidx = txq->ift_cidx;
3195 pidx = txq->ift_pidx;
3196 if (ctx->ifc_flags & IFC_PREFETCH) {
3197 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3198 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3199 next_txd = calc_next_txd(txq, cidx, 0);
3203 /* prefetch the next cache line of mbuf pointers and flags */
3204 prefetch(&txq->ift_sds.ifsd_m[next]);
3205 if (txq->ift_sds.ifsd_map != NULL) {
3206 prefetch(&txq->ift_sds.ifsd_map[next]);
3207 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3208 prefetch(&txq->ift_sds.ifsd_flags[next]);
3210 } else if (txq->ift_sds.ifsd_map != NULL)
3211 map = txq->ift_sds.ifsd_map[pidx];
3213 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3214 desc_tag = txq->ift_tso_desc_tag;
3215 max_segs = scctx->isc_tx_tso_segments_max;
3217 desc_tag = txq->ift_desc_tag;
3218 max_segs = scctx->isc_tx_nsegments;
3220 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3221 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3222 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3229 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3231 pi.ipi_qsidx = txq->ift_id;
3232 pi.ipi_len = m_head->m_pkthdr.len;
3233 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3234 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3236 /* deliberate bitwise OR to make one condition */
3237 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3238 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3244 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3246 if (__predict_false(err)) {
3249 /* try collapse once and defrag once */
3251 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3252 /* try defrag if collapsing fails */
3257 m_head = m_defrag(*m_headp, M_NOWAIT);
3259 if (__predict_false(m_head == NULL))
3261 txq->ift_mbuf_defrag++;
3266 txq->ift_no_tx_dma_setup++;
3269 txq->ift_no_tx_dma_setup++;
3271 DBG_COUNTER_INC(tx_frees);
3275 txq->ift_map_failed++;
3276 DBG_COUNTER_INC(encap_load_mbuf_fail);
3281 * XXX assumes a 1 to 1 relationship between segments and
3282 * descriptors - this does not hold true on all drivers, e.g.
3285 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3286 txq->ift_no_desc_avail++;
3288 bus_dmamap_unload(desc_tag, map);
3289 DBG_COUNTER_INC(encap_txq_avail_fail);
3290 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3291 GROUPTASK_ENQUEUE(&txq->ift_task);
3295 * On Intel cards we can greatly reduce the number of TX interrupts
3296 * we see by only setting report status on every Nth descriptor.
3297 * However, this also means that the driver will need to keep track
3298 * of the descriptors that RS was set on to check them for the DD bit.
3300 txq->ift_rs_pending += nsegs + 1;
3301 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3302 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3303 pi.ipi_flags |= IPI_TX_INTR;
3304 txq->ift_rs_pending = 0;
3308 pi.ipi_nsegs = nsegs;
3310 MPASS(pidx >= 0 && pidx < txq->ift_size);
3315 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3316 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3318 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3320 DBG_COUNTER_INC(tx_encap);
3321 MPASS(pi.ipi_new_pidx < txq->ift_size);
3323 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3324 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3325 ndesc += txq->ift_size;
3329 * drivers can need as many as
3332 MPASS(ndesc <= pi.ipi_nsegs + 2);
3333 MPASS(pi.ipi_new_pidx != pidx);
3335 txq->ift_in_use += ndesc;
3338 * We update the last software descriptor again here because there may
3339 * be a sentinel and/or there may be more mbufs than segments
3341 txq->ift_pidx = pi.ipi_new_pidx;
3342 txq->ift_npending += pi.ipi_ndescs;
3344 *m_headp = m_head = iflib_remove_mbuf(txq);
3346 txq->ift_txd_encap_efbig++;
3352 DBG_COUNTER_INC(encap_txd_encap_fail);
3358 txq->ift_mbuf_defrag_failed++;
3359 txq->ift_map_failed++;
3361 DBG_COUNTER_INC(tx_frees);
3367 iflib_tx_desc_free(iflib_txq_t txq, int n)
3370 uint32_t qsize, cidx, mask, gen;
3371 struct mbuf *m, **ifsd_m;
3372 uint8_t *ifsd_flags;
3373 bus_dmamap_t *ifsd_map;
3376 cidx = txq->ift_cidx;
3378 qsize = txq->ift_size;
3380 hasmap = txq->ift_sds.ifsd_map != NULL;
3381 ifsd_flags = txq->ift_sds.ifsd_flags;
3382 ifsd_m = txq->ift_sds.ifsd_m;
3383 ifsd_map = txq->ift_sds.ifsd_map;
3384 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3388 prefetch(ifsd_m[(cidx + 3) & mask]);
3389 prefetch(ifsd_m[(cidx + 4) & mask]);
3391 if (ifsd_m[cidx] != NULL) {
3392 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3393 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3394 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3396 * does it matter if it's not the TSO tag? If so we'll
3397 * have to add the type to flags
3399 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3400 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3402 if ((m = ifsd_m[cidx]) != NULL) {
3403 /* XXX we don't support any drivers that batch packets yet */
3404 MPASS(m->m_nextpkt == NULL);
3405 /* if the number of clusters exceeds the number of segments
3406 * there won't be space on the ring to save a pointer to each
3407 * cluster so we simply free the list here
3409 if (m->m_flags & M_TOOBIG) {
3414 ifsd_m[cidx] = NULL;
3416 txq->ift_dequeued++;
3418 DBG_COUNTER_INC(tx_frees);
3421 if (__predict_false(++cidx == qsize)) {
3426 txq->ift_cidx = cidx;
3431 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3434 if_ctx_t ctx = txq->ift_ctx;
3436 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3437 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3440 * Need a rate-limiting check so that this isn't called every time
3442 iflib_tx_credits_update(ctx, txq);
3443 reclaim = DESC_RECLAIMABLE(txq);
3445 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3447 if (iflib_verbose_debug) {
3448 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3449 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3456 iflib_tx_desc_free(txq, reclaim);
3457 txq->ift_cleaned += reclaim;
3458 txq->ift_in_use -= reclaim;
3463 static struct mbuf **
3464 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3467 struct mbuf **items;
3470 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3471 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3473 prefetch(items[(cidx + offset) & (size-1)]);
3474 if (remaining > 1) {
3475 prefetch2cachelines(&items[next]);
3476 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3477 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3478 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3480 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3484 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3487 ifmp_ring_check_drainage(txq->ift_br, budget);
3491 iflib_txq_can_drain(struct ifmp_ring *r)
3493 iflib_txq_t txq = r->cookie;
3494 if_ctx_t ctx = txq->ift_ctx;
3496 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3497 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3501 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3503 iflib_txq_t txq = r->cookie;
3504 if_ctx_t ctx = txq->ift_ctx;
3505 struct ifnet *ifp = ctx->ifc_ifp;
3506 struct mbuf **mp, *m;
3507 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3508 int reclaimed, err, in_use_prev, desc_used;
3509 bool do_prefetch, ring, rang;
3511 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3512 !LINK_ACTIVE(ctx))) {
3513 DBG_COUNTER_INC(txq_drain_notready);
3516 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3517 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3518 avail = IDXDIFF(pidx, cidx, r->size);
3519 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3520 DBG_COUNTER_INC(txq_drain_flushing);
3521 for (i = 0; i < avail; i++) {
3522 m_free(r->items[(cidx + i) & (r->size-1)]);
3523 r->items[(cidx + i) & (r->size-1)] = NULL;
3528 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3529 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3531 callout_stop(&txq->ift_timer);
3532 CALLOUT_UNLOCK(txq);
3533 DBG_COUNTER_INC(txq_drain_oactive);
3537 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3538 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3539 count = MIN(avail, TX_BATCH_SIZE);
3541 if (iflib_verbose_debug)
3542 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3543 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3545 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3546 avail = TXQ_AVAIL(txq);
3548 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3549 int rem = do_prefetch ? count - i : 0;
3551 mp = _ring_peek_one(r, cidx, i, rem);
3552 MPASS(mp != NULL && *mp != NULL);
3553 if (__predict_false(*mp == (struct mbuf *)txq)) {
3558 in_use_prev = txq->ift_in_use;
3559 err = iflib_encap(txq, mp);
3560 if (__predict_false(err)) {
3561 DBG_COUNTER_INC(txq_drain_encapfail);
3562 /* no room - bail out */
3566 DBG_COUNTER_INC(txq_drain_encapfail);
3567 /* we can't send this packet - skip it */
3573 DBG_COUNTER_INC(tx_sent);
3574 bytes_sent += m->m_pkthdr.len;
3575 mcast_sent += !!(m->m_flags & M_MCAST);
3576 avail = TXQ_AVAIL(txq);
3578 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3579 desc_used += (txq->ift_in_use - in_use_prev);
3580 ETHER_BPF_MTAP(ifp, m);
3581 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3583 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3586 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3587 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3588 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3589 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3590 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3592 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3594 if (iflib_verbose_debug)
3595 printf("consumed=%d\n", consumed);
3601 iflib_txq_drain_always(struct ifmp_ring *r)
3607 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3615 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3617 callout_stop(&txq->ift_timer);
3618 CALLOUT_UNLOCK(txq);
3620 avail = IDXDIFF(pidx, cidx, r->size);
3621 for (i = 0; i < avail; i++) {
3622 mp = _ring_peek_one(r, cidx, i, avail - i);
3623 if (__predict_false(*mp == (struct mbuf *)txq))
3627 MPASS(ifmp_ring_is_stalled(r) == 0);
3632 iflib_ifmp_purge(iflib_txq_t txq)
3634 struct ifmp_ring *r;
3637 r->drain = iflib_txq_drain_free;
3638 r->can_drain = iflib_txq_drain_always;
3640 ifmp_ring_check_drainage(r, r->size);
3642 r->drain = iflib_txq_drain;
3643 r->can_drain = iflib_txq_can_drain;
3647 _task_fn_tx(void *context)
3649 iflib_txq_t txq = context;
3650 if_ctx_t ctx = txq->ift_ctx;
3651 struct ifnet *ifp = ctx->ifc_ifp;
3653 #ifdef IFLIB_DIAGNOSTICS
3654 txq->ift_cpu_exec_count[curcpu]++;
3656 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3658 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3659 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3660 netmap_tx_irq(ifp, txq->ift_id);
3661 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3664 if (txq->ift_db_pending)
3665 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3666 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3667 if (ctx->ifc_flags & IFC_LEGACY)
3668 IFDI_INTR_ENABLE(ctx);
3673 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3674 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3679 _task_fn_rx(void *context)
3681 iflib_rxq_t rxq = context;
3682 if_ctx_t ctx = rxq->ifr_ctx;
3686 #ifdef IFLIB_DIAGNOSTICS
3687 rxq->ifr_cpu_exec_count[curcpu]++;
3689 DBG_COUNTER_INC(task_fn_rxs);
3690 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3694 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3696 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3701 budget = ctx->ifc_sysctl_rx_budget;
3703 budget = 16; /* XXX */
3704 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3705 if (ctx->ifc_flags & IFC_LEGACY)
3706 IFDI_INTR_ENABLE(ctx);
3711 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3712 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3713 DBG_COUNTER_INC(rx_intr_enables);
3716 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3719 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3723 _task_fn_admin(void *context)
3725 if_ctx_t ctx = context;
3726 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3729 bool oactive, running, do_reset, do_watchdog;
3732 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3733 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3734 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3735 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3736 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3739 if (!running & !oactive)
3743 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3745 callout_stop(&txq->ift_timer);
3746 CALLOUT_UNLOCK(txq);
3749 ctx->ifc_watchdog_events++;
3750 IFDI_WATCHDOG_RESET(ctx);
3752 IFDI_UPDATE_ADMIN_STATUS(ctx);
3753 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3754 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3755 IFDI_LINK_INTR_ENABLE(ctx);
3757 iflib_if_init_locked(ctx);
3760 if (LINK_ACTIVE(ctx) == 0)
3762 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3763 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3768 _task_fn_iov(void *context)
3770 if_ctx_t ctx = context;
3772 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3776 IFDI_VFLR_HANDLE(ctx);
3781 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3784 if_int_delay_info_t info;
3787 info = (if_int_delay_info_t)arg1;
3788 ctx = info->iidi_ctx;
3789 info->iidi_req = req;
3790 info->iidi_oidp = oidp;
3792 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3797 /*********************************************************************
3801 **********************************************************************/
3804 iflib_if_init_locked(if_ctx_t ctx)
3807 iflib_init_locked(ctx);
3812 iflib_if_init(void *arg)
3817 iflib_if_init_locked(ctx);
3822 iflib_if_transmit(if_t ifp, struct mbuf *m)
3824 if_ctx_t ctx = if_getsoftc(ifp);
3829 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3830 DBG_COUNTER_INC(tx_frees);
3835 MPASS(m->m_nextpkt == NULL);
3837 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3838 qidx = QIDX(ctx, m);
3840 * XXX calculate buf_ring based on flowid (divvy up bits?)
3842 txq = &ctx->ifc_txqs[qidx];
3844 #ifdef DRIVER_BACKPRESSURE
3845 if (txq->ift_closed) {
3847 next = m->m_nextpkt;
3848 m->m_nextpkt = NULL;
3861 next = next->m_nextpkt;
3862 } while (next != NULL);
3864 if (count > nitems(marr))
3865 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3866 /* XXX check nextpkt */
3868 /* XXX simplify for now */
3869 DBG_COUNTER_INC(tx_frees);
3872 for (next = m, i = 0; next != NULL; i++) {
3874 next = next->m_nextpkt;
3875 mp[i]->m_nextpkt = NULL;
3878 DBG_COUNTER_INC(tx_seen);
3879 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3881 GROUPTASK_ENQUEUE(&txq->ift_task);
3883 /* support forthcoming later */
3884 #ifdef DRIVER_BACKPRESSURE
3885 txq->ift_closed = TRUE;
3887 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3895 iflib_if_qflush(if_t ifp)
3897 if_ctx_t ctx = if_getsoftc(ifp);
3898 iflib_txq_t txq = ctx->ifc_txqs;
3902 ctx->ifc_flags |= IFC_QFLUSH;
3904 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3905 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3906 iflib_txq_check_drain(txq, 0);
3908 ctx->ifc_flags &= ~IFC_QFLUSH;
3915 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3916 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3917 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3920 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3922 if_ctx_t ctx = if_getsoftc(ifp);
3923 struct ifreq *ifr = (struct ifreq *)data;
3924 #if defined(INET) || defined(INET6)
3925 struct ifaddr *ifa = (struct ifaddr *)data;
3927 bool avoid_reset = FALSE;
3928 int err = 0, reinit = 0, bits;
3933 if (ifa->ifa_addr->sa_family == AF_INET)
3937 if (ifa->ifa_addr->sa_family == AF_INET6)
3941 ** Calling init results in link renegotiation,
3942 ** so we avoid doing it when possible.
3945 if_setflagbits(ifp, IFF_UP,0);
3946 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3949 if (!(if_getflags(ifp) & IFF_NOARP))
3950 arp_ifinit(ifp, ifa);
3953 err = ether_ioctl(ifp, command, data);
3957 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3961 bits = if_getdrvflags(ifp);
3962 /* stop the driver and free any clusters before proceeding */
3965 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3967 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3968 ctx->ifc_flags |= IFC_MULTISEG;
3970 ctx->ifc_flags &= ~IFC_MULTISEG;
3972 err = if_setmtu(ifp, ifr->ifr_mtu);
3974 iflib_init_locked(ctx);
3976 if_setdrvflags(ifp, bits);
3982 if (if_getflags(ifp) & IFF_UP) {
3983 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3984 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3985 (IFF_PROMISC | IFF_ALLMULTI)) {
3986 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3990 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3993 ctx->ifc_if_flags = if_getflags(ifp);
3998 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4000 IFDI_INTR_DISABLE(ctx);
4001 IFDI_MULTI_SET(ctx);
4002 IFDI_INTR_ENABLE(ctx);
4008 IFDI_MEDIA_SET(ctx);
4013 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4017 struct ifi2creq i2c;
4019 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4022 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4026 if (i2c.len > sizeof(i2c.data)) {
4031 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4032 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4040 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4043 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4045 setmask |= (mask & IFCAP_FLAGS);
4047 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4048 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4049 if ((mask & IFCAP_WOL) &&
4050 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4051 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4054 * want to ensure that traffic has stopped before we change any of the flags
4058 bits = if_getdrvflags(ifp);
4059 if (bits & IFF_DRV_RUNNING)
4062 if_togglecapenable(ifp, setmask);
4064 if (bits & IFF_DRV_RUNNING)
4065 iflib_init_locked(ctx);
4067 if_setdrvflags(ifp, bits);
4073 case SIOCGPRIVATE_0:
4077 err = IFDI_PRIV_IOCTL(ctx, command, data);
4081 err = ether_ioctl(ifp, command, data);
4090 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4092 if_ctx_t ctx = if_getsoftc(ifp);
4094 return (IFDI_GET_COUNTER(ctx, cnt));
4097 /*********************************************************************
4099 * OTHER FUNCTIONS EXPORTED TO THE STACK
4101 **********************************************************************/
4104 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4106 if_ctx_t ctx = if_getsoftc(ifp);
4108 if ((void *)ctx != arg)
4111 if ((vtag == 0) || (vtag > 4095))
4115 IFDI_VLAN_REGISTER(ctx, vtag);
4116 /* Re-init to load the changes */
4117 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4118 iflib_if_init_locked(ctx);
4123 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4125 if_ctx_t ctx = if_getsoftc(ifp);
4127 if ((void *)ctx != arg)
4130 if ((vtag == 0) || (vtag > 4095))
4134 IFDI_VLAN_UNREGISTER(ctx, vtag);
4135 /* Re-init to load the changes */
4136 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4137 iflib_if_init_locked(ctx);
4142 iflib_led_func(void *arg, int onoff)
4147 IFDI_LED_FUNC(ctx, onoff);
4151 /*********************************************************************
4153 * BUS FUNCTION DEFINITIONS
4155 **********************************************************************/
4158 iflib_device_probe(device_t dev)
4160 pci_vendor_info_t *ent;
4162 uint16_t pci_vendor_id, pci_device_id;
4163 uint16_t pci_subvendor_id, pci_subdevice_id;
4164 uint16_t pci_rev_id;
4165 if_shared_ctx_t sctx;
4167 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4170 pci_vendor_id = pci_get_vendor(dev);
4171 pci_device_id = pci_get_device(dev);
4172 pci_subvendor_id = pci_get_subvendor(dev);
4173 pci_subdevice_id = pci_get_subdevice(dev);
4174 pci_rev_id = pci_get_revid(dev);
4175 if (sctx->isc_parse_devinfo != NULL)
4176 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4178 ent = sctx->isc_vendor_info;
4179 while (ent->pvi_vendor_id != 0) {
4180 if (pci_vendor_id != ent->pvi_vendor_id) {
4184 if ((pci_device_id == ent->pvi_device_id) &&
4185 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4186 (ent->pvi_subvendor_id == 0)) &&
4187 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4188 (ent->pvi_subdevice_id == 0)) &&
4189 ((pci_rev_id == ent->pvi_rev_id) ||
4190 (ent->pvi_rev_id == 0))) {
4192 device_set_desc_copy(dev, ent->pvi_name);
4193 /* this needs to be changed to zero if the bus probing code
4194 * ever stops re-probing on best match because the sctx
4195 * may have its values over written by register calls
4196 * in subsequent probes
4198 return (BUS_PROBE_DEFAULT);
4206 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4211 if_softc_ctx_t scctx;
4217 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4220 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4221 device_set_softc(dev, ctx);
4222 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4225 ctx->ifc_sctx = sctx;
4227 ctx->ifc_softc = sc;
4229 if ((err = iflib_register(ctx)) != 0) {
4230 device_printf(dev, "iflib_register failed %d\n", err);
4233 iflib_add_device_sysctl_pre(ctx);
4235 scctx = &ctx->ifc_softc_ctx;
4237 ctx->ifc_nhwtxqs = sctx->isc_ntxqs;
4240 * XXX sanity check that ntxd & nrxd are a power of 2
4242 if (ctx->ifc_sysctl_ntxqs != 0)
4243 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4244 if (ctx->ifc_sysctl_nrxqs != 0)
4245 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4247 for (i = 0; i < sctx->isc_ntxqs; i++) {
4248 if (ctx->ifc_sysctl_ntxds[i] != 0)
4249 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4251 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4254 for (i = 0; i < sctx->isc_nrxqs; i++) {
4255 if (ctx->ifc_sysctl_nrxds[i] != 0)
4256 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4258 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4261 for (i = 0; i < sctx->isc_nrxqs; i++) {
4262 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4263 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4264 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4265 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4267 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4268 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4269 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4270 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4274 for (i = 0; i < sctx->isc_ntxqs; i++) {
4275 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4276 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4277 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4278 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4280 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4281 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4282 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4283 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4288 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4290 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4293 _iflib_pre_assert(scctx);
4294 ctx->ifc_txrx = *scctx->isc_txrx;
4297 MPASS(scctx->isc_capenable);
4298 if (scctx->isc_capenable & IFCAP_TXCSUM)
4299 MPASS(scctx->isc_tx_csum_flags);
4302 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4303 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4305 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4306 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4307 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4308 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4311 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4312 ctx->ifc_flags |= IFC_DMAR;
4313 #elif !(defined(__i386__) || defined(__amd64__))
4314 /* set unconditionally for !x86 */
4315 ctx->ifc_flags |= IFC_DMAR;
4318 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4319 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4321 /* XXX change for per-queue sizes */
4322 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4323 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4324 for (i = 0; i < sctx->isc_nrxqs; i++) {
4325 if (!powerof2(scctx->isc_nrxd[i])) {
4326 /* round down instead? */
4327 device_printf(dev, "# rx descriptors must be a power of 2\n");
4332 for (i = 0; i < sctx->isc_ntxqs; i++) {
4333 if (!powerof2(scctx->isc_ntxd[i])) {
4335 "# tx descriptors must be a power of 2");
4341 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4342 MAX_SINGLE_PACKET_FRACTION)
4343 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4344 MAX_SINGLE_PACKET_FRACTION);
4345 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4346 MAX_SINGLE_PACKET_FRACTION)
4347 scctx->isc_tx_tso_segments_max = max(1,
4348 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4351 * Protect the stack against modern hardware
4353 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4354 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4356 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4357 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4358 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4359 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4360 if (scctx->isc_rss_table_size == 0)
4361 scctx->isc_rss_table_size = 64;
4362 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4364 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4365 /* XXX format name */
4366 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4368 /* Set up cpu set. If it fails, use the set of all CPUs. */
4369 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4370 device_printf(dev, "Unable to fetch CPU list\n");
4371 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4373 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4376 ** Now setup MSI or MSI/X, should
4377 ** return us the number of supported
4378 ** vectors. (Will be 1 for MSI)
4380 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4381 msix = scctx->isc_vectors;
4382 } else if (scctx->isc_msix_bar != 0)
4384 * The simple fact that isc_msix_bar is not 0 does not mean we
4385 * we have a good value there that is known to work.
4387 msix = iflib_msix_init(ctx);
4389 scctx->isc_vectors = 1;
4390 scctx->isc_ntxqsets = 1;
4391 scctx->isc_nrxqsets = 1;
4392 scctx->isc_intr = IFLIB_INTR_LEGACY;
4395 /* Get memory for the station queues */
4396 if ((err = iflib_queues_alloc(ctx))) {
4397 device_printf(dev, "Unable to allocate queue memory\n");
4401 if ((err = iflib_qset_structures_setup(ctx))) {
4402 device_printf(dev, "qset structure setup failed %d\n", err);
4407 * Group taskqueues aren't properly set up until SMP is started,
4408 * so we disable interrupts until we can handle them post
4411 * XXX: disabling interrupts doesn't actually work, at least for
4412 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4413 * we do null handling and depend on this not causing too large an
4416 IFDI_INTR_DISABLE(ctx);
4417 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4418 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4419 goto fail_intr_free;
4423 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4427 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4428 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4429 goto fail_intr_free;
4432 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4433 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4434 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4437 if ((err = iflib_netmap_attach(ctx))) {
4438 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4443 NETDUMP_SET(ctx->ifc_ifp, iflib);
4445 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4446 iflib_add_device_sysctl_post(ctx);
4447 ctx->ifc_flags |= IFC_INIT_DONE;
4451 ether_ifdetach(ctx->ifc_ifp);
4453 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4454 pci_release_msi(ctx->ifc_dev);
4456 iflib_tx_structures_free(ctx);
4457 iflib_rx_structures_free(ctx);
4465 iflib_device_attach(device_t dev)
4468 if_shared_ctx_t sctx;
4470 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4473 pci_enable_busmaster(dev);
4475 return (iflib_device_register(dev, NULL, sctx, &ctx));
4479 iflib_device_deregister(if_ctx_t ctx)
4481 if_t ifp = ctx->ifc_ifp;
4484 device_t dev = ctx->ifc_dev;
4486 struct taskqgroup *tqg;
4489 /* Make sure VLANS are not using driver */
4490 if (if_vlantrunkinuse(ifp)) {
4491 device_printf(dev,"Vlan in use, detach first\n");
4496 ctx->ifc_in_detach = 1;
4500 /* Unregister VLAN events */
4501 if (ctx->ifc_vlan_attach_event != NULL)
4502 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4503 if (ctx->ifc_vlan_detach_event != NULL)
4504 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4506 iflib_netmap_detach(ifp);
4507 ether_ifdetach(ifp);
4508 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4509 CTX_LOCK_DESTROY(ctx);
4510 if (ctx->ifc_led_dev != NULL)
4511 led_destroy(ctx->ifc_led_dev);
4512 /* XXX drain any dependent tasks */
4513 tqg = qgroup_if_io_tqg;
4514 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4515 callout_drain(&txq->ift_timer);
4516 if (txq->ift_task.gt_uniq != NULL)
4517 taskqgroup_detach(tqg, &txq->ift_task);
4519 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4520 if (rxq->ifr_task.gt_uniq != NULL)
4521 taskqgroup_detach(tqg, &rxq->ifr_task);
4523 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4524 free(fl->ifl_rx_bitmap, M_IFLIB);
4527 tqg = qgroup_if_config_tqg;
4528 if (ctx->ifc_admin_task.gt_uniq != NULL)
4529 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4530 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4531 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4534 device_set_softc(ctx->ifc_dev, NULL);
4535 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4536 pci_release_msi(dev);
4538 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4539 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4541 if (ctx->ifc_msix_mem != NULL) {
4542 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4543 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4544 ctx->ifc_msix_mem = NULL;
4547 bus_generic_detach(dev);
4550 iflib_tx_structures_free(ctx);
4551 iflib_rx_structures_free(ctx);
4552 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4553 free(ctx->ifc_softc, M_IFLIB);
4560 iflib_device_detach(device_t dev)
4562 if_ctx_t ctx = device_get_softc(dev);
4564 return (iflib_device_deregister(ctx));
4568 iflib_device_suspend(device_t dev)
4570 if_ctx_t ctx = device_get_softc(dev);
4576 return bus_generic_suspend(dev);
4579 iflib_device_shutdown(device_t dev)
4581 if_ctx_t ctx = device_get_softc(dev);
4587 return bus_generic_suspend(dev);
4592 iflib_device_resume(device_t dev)
4594 if_ctx_t ctx = device_get_softc(dev);
4595 iflib_txq_t txq = ctx->ifc_txqs;
4599 iflib_init_locked(ctx);
4601 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4602 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4604 return (bus_generic_resume(dev));
4608 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4611 if_ctx_t ctx = device_get_softc(dev);
4614 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4621 iflib_device_iov_uninit(device_t dev)
4623 if_ctx_t ctx = device_get_softc(dev);
4626 IFDI_IOV_UNINIT(ctx);
4631 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4634 if_ctx_t ctx = device_get_softc(dev);
4637 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4643 /*********************************************************************
4645 * MODULE FUNCTION DEFINITIONS
4647 **********************************************************************/
4650 * - Start a fast taskqueue thread for each core
4651 * - Start a taskqueue for control operations
4654 iflib_module_init(void)
4660 iflib_module_event_handler(module_t mod, int what, void *arg)
4666 if ((err = iflib_module_init()) != 0)
4672 return (EOPNOTSUPP);
4678 /*********************************************************************
4680 * PUBLIC FUNCTION DEFINITIONS
4681 * ordered as in iflib.h
4683 **********************************************************************/
4687 _iflib_assert(if_shared_ctx_t sctx)
4689 MPASS(sctx->isc_tx_maxsize);
4690 MPASS(sctx->isc_tx_maxsegsize);
4692 MPASS(sctx->isc_rx_maxsize);
4693 MPASS(sctx->isc_rx_nsegments);
4694 MPASS(sctx->isc_rx_maxsegsize);
4696 MPASS(sctx->isc_nrxd_min[0]);
4697 MPASS(sctx->isc_nrxd_max[0]);
4698 MPASS(sctx->isc_nrxd_default[0]);
4699 MPASS(sctx->isc_ntxd_min[0]);
4700 MPASS(sctx->isc_ntxd_max[0]);
4701 MPASS(sctx->isc_ntxd_default[0]);
4705 _iflib_pre_assert(if_softc_ctx_t scctx)
4708 MPASS(scctx->isc_txrx->ift_txd_encap);
4709 MPASS(scctx->isc_txrx->ift_txd_flush);
4710 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4711 MPASS(scctx->isc_txrx->ift_rxd_available);
4712 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4713 MPASS(scctx->isc_txrx->ift_rxd_refill);
4714 MPASS(scctx->isc_txrx->ift_rxd_flush);
4718 iflib_register(if_ctx_t ctx)
4720 if_shared_ctx_t sctx = ctx->ifc_sctx;
4721 driver_t *driver = sctx->isc_driver;
4722 device_t dev = ctx->ifc_dev;
4725 _iflib_assert(sctx);
4728 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4729 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4731 device_printf(dev, "can not allocate ifnet structure\n");
4736 * Initialize our context's device specific methods
4738 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4739 kobj_class_compile((kobj_class_t) driver);
4742 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4743 if_setsoftc(ifp, ctx);
4744 if_setdev(ifp, dev);
4745 if_setinitfn(ifp, iflib_if_init);
4746 if_setioctlfn(ifp, iflib_if_ioctl);
4747 if_settransmitfn(ifp, iflib_if_transmit);
4748 if_setqflushfn(ifp, iflib_if_qflush);
4749 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4751 ctx->ifc_vlan_attach_event =
4752 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4753 EVENTHANDLER_PRI_FIRST);
4754 ctx->ifc_vlan_detach_event =
4755 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4756 EVENTHANDLER_PRI_FIRST);
4758 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4759 iflib_media_change, iflib_media_status);
4766 iflib_queues_alloc(if_ctx_t ctx)
4768 if_shared_ctx_t sctx = ctx->ifc_sctx;
4769 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4770 device_t dev = ctx->ifc_dev;
4771 int nrxqsets = scctx->isc_nrxqsets;
4772 int ntxqsets = scctx->isc_ntxqsets;
4775 iflib_fl_t fl = NULL;
4776 int i, j, cpu, err, txconf, rxconf;
4777 iflib_dma_info_t ifdip;
4778 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4779 uint32_t *txqsizes = scctx->isc_txqsizes;
4780 uint8_t nrxqs = sctx->isc_nrxqs;
4781 uint8_t ntxqs = sctx->isc_ntxqs;
4782 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4786 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4787 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4789 /* Allocate the TX ring struct memory */
4790 if (!(ctx->ifc_txqs =
4791 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4792 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4793 device_printf(dev, "Unable to allocate TX ring memory\n");
4798 /* Now allocate the RX */
4799 if (!(ctx->ifc_rxqs =
4800 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4801 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4802 device_printf(dev, "Unable to allocate RX ring memory\n");
4807 txq = ctx->ifc_txqs;
4808 rxq = ctx->ifc_rxqs;
4811 * XXX handle allocation failure
4813 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4814 /* Set up some basics */
4816 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4817 device_printf(dev, "failed to allocate iflib_dma_info\n");
4821 txq->ift_ifdi = ifdip;
4822 for (j = 0; j < ntxqs; j++, ifdip++) {
4823 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4824 device_printf(dev, "Unable to allocate Descriptor memory\n");
4828 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4829 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4833 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4834 txq->ift_br_offset = 1;
4836 txq->ift_br_offset = 0;
4839 txq->ift_timer.c_cpu = cpu;
4841 if (iflib_txsd_alloc(txq)) {
4842 device_printf(dev, "Critical Failure setting up TX buffers\n");
4847 /* Initialize the TX lock */
4848 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4849 device_get_nameunit(dev), txq->ift_id);
4850 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4851 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4853 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4854 device_get_nameunit(dev), txq->ift_id);
4856 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4857 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4859 /* XXX free any allocated rings */
4860 device_printf(dev, "Unable to allocate buf_ring\n");
4865 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4866 /* Set up some basics */
4868 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4869 device_printf(dev, "failed to allocate iflib_dma_info\n");
4874 rxq->ifr_ifdi = ifdip;
4875 /* XXX this needs to be changed if #rx queues != #tx queues */
4876 rxq->ifr_ntxqirq = 1;
4877 rxq->ifr_txqid[0] = i;
4878 for (j = 0; j < nrxqs; j++, ifdip++) {
4879 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4880 device_printf(dev, "Unable to allocate Descriptor memory\n");
4884 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4888 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4889 rxq->ifr_fl_offset = 1;
4891 rxq->ifr_fl_offset = 0;
4893 rxq->ifr_nfl = nfree_lists;
4895 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4896 device_printf(dev, "Unable to allocate free list memory\n");
4901 for (j = 0; j < nfree_lists; j++) {
4902 fl[j].ifl_rxq = rxq;
4904 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4905 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4907 /* Allocate receive buffers for the ring*/
4908 if (iflib_rxsd_alloc(rxq)) {
4910 "Critical Failure setting up receive buffers\n");
4915 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4916 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4920 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4921 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4922 for (i = 0; i < ntxqsets; i++) {
4923 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4925 for (j = 0; j < ntxqs; j++, di++) {
4926 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4927 paddrs[i*ntxqs + j] = di->idi_paddr;
4930 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4931 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4932 iflib_tx_structures_free(ctx);
4933 free(vaddrs, M_IFLIB);
4934 free(paddrs, M_IFLIB);
4937 free(vaddrs, M_IFLIB);
4938 free(paddrs, M_IFLIB);
4941 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4942 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4943 for (i = 0; i < nrxqsets; i++) {
4944 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4946 for (j = 0; j < nrxqs; j++, di++) {
4947 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4948 paddrs[i*nrxqs + j] = di->idi_paddr;
4951 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4952 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4953 iflib_tx_structures_free(ctx);
4954 free(vaddrs, M_IFLIB);
4955 free(paddrs, M_IFLIB);
4958 free(vaddrs, M_IFLIB);
4959 free(paddrs, M_IFLIB);
4963 /* XXX handle allocation failure changes */
4967 if (ctx->ifc_rxqs != NULL)
4968 free(ctx->ifc_rxqs, M_IFLIB);
4969 ctx->ifc_rxqs = NULL;
4970 if (ctx->ifc_txqs != NULL)
4971 free(ctx->ifc_txqs, M_IFLIB);
4972 ctx->ifc_txqs = NULL;
4978 iflib_tx_structures_setup(if_ctx_t ctx)
4980 iflib_txq_t txq = ctx->ifc_txqs;
4983 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4984 iflib_txq_setup(txq);
4990 iflib_tx_structures_free(if_ctx_t ctx)
4992 iflib_txq_t txq = ctx->ifc_txqs;
4995 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4996 iflib_txq_destroy(txq);
4997 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4998 iflib_dma_free(&txq->ift_ifdi[j]);
5000 free(ctx->ifc_txqs, M_IFLIB);
5001 ctx->ifc_txqs = NULL;
5002 IFDI_QUEUES_FREE(ctx);
5005 /*********************************************************************
5007 * Initialize all receive rings.
5009 **********************************************************************/
5011 iflib_rx_structures_setup(if_ctx_t ctx)
5013 iflib_rxq_t rxq = ctx->ifc_rxqs;
5015 #if defined(INET6) || defined(INET)
5019 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5020 #if defined(INET6) || defined(INET)
5021 tcp_lro_free(&rxq->ifr_lc);
5022 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5023 TCP_LRO_ENTRIES, min(1024,
5024 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5025 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5028 rxq->ifr_lro_enabled = TRUE;
5030 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5033 #if defined(INET6) || defined(INET)
5036 * Free RX software descriptors allocated so far, we will only handle
5037 * the rings that completed, the failing case will have
5038 * cleaned up for itself. 'q' failed, so its the terminus.
5040 rxq = ctx->ifc_rxqs;
5041 for (i = 0; i < q; ++i, rxq++) {
5042 iflib_rx_sds_free(rxq);
5043 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5049 /*********************************************************************
5051 * Free all receive rings.
5053 **********************************************************************/
5055 iflib_rx_structures_free(if_ctx_t ctx)
5057 iflib_rxq_t rxq = ctx->ifc_rxqs;
5059 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5060 iflib_rx_sds_free(rxq);
5065 iflib_qset_structures_setup(if_ctx_t ctx)
5070 * It is expected that the caller takes care of freeing queues if this
5073 if ((err = iflib_tx_structures_setup(ctx)) != 0)
5076 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5077 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5083 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5084 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
5087 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5092 find_nth(if_ctx_t ctx, int qid)
5095 int i, cpuid, eqid, count;
5097 CPU_COPY(&ctx->ifc_cpus, &cpus);
5098 count = CPU_COUNT(&cpus);
5100 /* clear up to the qid'th bit */
5101 for (i = 0; i < eqid; i++) {
5102 cpuid = CPU_FFS(&cpus);
5104 CPU_CLR(cpuid-1, &cpus);
5106 cpuid = CPU_FFS(&cpus);
5112 extern struct cpu_group *cpu_top; /* CPU topology */
5115 find_child_with_core(int cpu, struct cpu_group *grp)
5119 if (grp->cg_children == 0)
5122 MPASS(grp->cg_child);
5123 for (i = 0; i < grp->cg_children; i++) {
5124 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5132 * Find the nth "close" core to the specified core
5133 * "close" is defined as the deepest level that shares
5134 * at least an L2 cache. With threads, this will be
5135 * threads on the same core. If the sahred cache is L3
5136 * or higher, simply returns the same core.
5139 find_close_core(int cpu, int core_offset)
5141 struct cpu_group *grp;
5150 while ((i = find_child_with_core(cpu, grp)) != -1) {
5151 /* If the child only has one cpu, don't descend */
5152 if (grp->cg_child[i].cg_count <= 1)
5154 grp = &grp->cg_child[i];
5157 /* If they don't share at least an L2 cache, use the same CPU */
5158 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5162 CPU_COPY(&grp->cg_mask, &cs);
5164 /* Add the selected CPU offset to core offset. */
5165 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5166 if (fcpu - 1 == cpu)
5168 CPU_CLR(fcpu - 1, &cs);
5174 CPU_COPY(&grp->cg_mask, &cs);
5175 for (i = core_offset % grp->cg_count; i > 0; i--) {
5176 MPASS(CPU_FFS(&cs));
5177 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5179 MPASS(CPU_FFS(&cs));
5180 return CPU_FFS(&cs) - 1;
5184 find_close_core(int cpu, int core_offset __unused)
5191 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5195 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5196 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5197 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5199 case IFLIB_INTR_RXTX:
5200 /* RX queues get the specified core */
5201 return qid / CPU_COUNT(&ctx->ifc_cpus);
5207 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5208 #define find_close_core(cpuid, tid) CPU_FIRST()
5209 #define find_nth(ctx, gid) CPU_FIRST()
5212 /* Just to avoid copy/paste */
5214 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5215 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name)
5220 cpuid = find_nth(ctx, qid);
5221 tid = get_core_offset(ctx, type, qid);
5223 cpuid = find_close_core(cpuid, tid);
5224 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5226 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5230 if (cpuid > ctx->ifc_cpuid_highest)
5231 ctx->ifc_cpuid_highest = cpuid;
5237 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5238 iflib_intr_type_t type, driver_filter_t *filter,
5239 void *filter_arg, int qid, char *name)
5241 struct grouptask *gtask;
5242 struct taskqgroup *tqg;
5243 iflib_filter_info_t info;
5246 driver_filter_t *intr_fast;
5249 info = &ctx->ifc_filter_info;
5253 /* XXX merge tx/rx for netmap? */
5255 q = &ctx->ifc_txqs[qid];
5256 info = &ctx->ifc_txqs[qid].ift_filter_info;
5257 gtask = &ctx->ifc_txqs[qid].ift_task;
5258 tqg = qgroup_if_io_tqg;
5260 intr_fast = iflib_fast_intr;
5261 GROUPTASK_INIT(gtask, 0, fn, q);
5264 q = &ctx->ifc_rxqs[qid];
5265 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5266 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5267 tqg = qgroup_if_io_tqg;
5269 intr_fast = iflib_fast_intr;
5270 GROUPTASK_INIT(gtask, 0, fn, q);
5272 case IFLIB_INTR_RXTX:
5273 q = &ctx->ifc_rxqs[qid];
5274 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5275 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5276 tqg = qgroup_if_io_tqg;
5278 intr_fast = iflib_fast_intr_rxtx;
5279 GROUPTASK_INIT(gtask, 0, fn, q);
5281 case IFLIB_INTR_ADMIN:
5284 info = &ctx->ifc_filter_info;
5285 gtask = &ctx->ifc_admin_task;
5286 tqg = qgroup_if_config_tqg;
5287 fn = _task_fn_admin;
5288 intr_fast = iflib_fast_intr_ctx;
5291 panic("unknown net intr type");
5294 info->ifi_filter = filter;
5295 info->ifi_filter_arg = filter_arg;
5296 info->ifi_task = gtask;
5299 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5301 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5304 if (type == IFLIB_INTR_ADMIN)
5308 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5312 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5319 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name)
5321 struct grouptask *gtask;
5322 struct taskqgroup *tqg;
5330 q = &ctx->ifc_txqs[qid];
5331 gtask = &ctx->ifc_txqs[qid].ift_task;
5332 tqg = qgroup_if_io_tqg;
5335 irq_num = rman_get_start(irq->ii_res);
5338 q = &ctx->ifc_rxqs[qid];
5339 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5340 tqg = qgroup_if_io_tqg;
5343 irq_num = rman_get_start(irq->ii_res);
5345 case IFLIB_INTR_IOV:
5347 gtask = &ctx->ifc_vflr_task;
5348 tqg = qgroup_if_config_tqg;
5352 panic("unknown net intr type");
5354 GROUPTASK_INIT(gtask, 0, fn, q);
5355 if (irq_num != -1) {
5356 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5358 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5361 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5366 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5369 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5372 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5376 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5378 iflib_txq_t txq = ctx->ifc_txqs;
5379 iflib_rxq_t rxq = ctx->ifc_rxqs;
5380 if_irq_t irq = &ctx->ifc_legacy_irq;
5381 iflib_filter_info_t info;
5382 struct grouptask *gtask;
5383 struct taskqgroup *tqg;
5389 q = &ctx->ifc_rxqs[0];
5390 info = &rxq[0].ifr_filter_info;
5391 gtask = &rxq[0].ifr_task;
5392 tqg = qgroup_if_io_tqg;
5393 tqrid = irq->ii_rid = *rid;
5396 ctx->ifc_flags |= IFC_LEGACY;
5397 info->ifi_filter = filter;
5398 info->ifi_filter_arg = filter_arg;
5399 info->ifi_task = gtask;
5400 info->ifi_ctx = ctx;
5402 /* We allocate a single interrupt resource */
5403 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5405 GROUPTASK_INIT(gtask, 0, fn, q);
5406 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5408 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5409 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5414 iflib_led_create(if_ctx_t ctx)
5417 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5418 device_get_nameunit(ctx->ifc_dev));
5422 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5425 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5429 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5432 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5436 iflib_admin_intr_deferred(if_ctx_t ctx)
5439 struct grouptask *gtask;
5441 gtask = &ctx->ifc_admin_task;
5442 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5445 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5449 iflib_iov_intr_deferred(if_ctx_t ctx)
5452 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5456 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5459 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5463 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5467 GROUPTASK_INIT(gtask, 0, fn, ctx);
5468 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5472 iflib_config_gtask_deinit(struct grouptask *gtask)
5475 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5479 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5481 if_t ifp = ctx->ifc_ifp;
5482 iflib_txq_t txq = ctx->ifc_txqs;
5484 if_setbaudrate(ifp, baudrate);
5485 if (baudrate >= IF_Gbps(10)) {
5487 ctx->ifc_flags |= IFC_PREFETCH;
5490 /* If link down, disable watchdog */
5491 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5492 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5493 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5495 ctx->ifc_link_state = link_state;
5496 if_link_state_change(ifp, link_state);
5500 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5504 int credits_pre = txq->ift_cidx_processed;
5507 if (ctx->isc_txd_credits_update == NULL)
5510 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5513 txq->ift_processed += credits;
5514 txq->ift_cidx_processed += credits;
5516 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5517 if (txq->ift_cidx_processed >= txq->ift_size)
5518 txq->ift_cidx_processed -= txq->ift_size;
5523 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5526 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5531 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5532 const char *description, if_int_delay_info_t info,
5533 int offset, int value)
5535 info->iidi_ctx = ctx;
5536 info->iidi_offset = offset;
5537 info->iidi_value = value;
5538 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5539 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5540 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5541 info, 0, iflib_sysctl_int_delay, "I", description);
5545 iflib_ctx_lock_get(if_ctx_t ctx)
5548 return (&ctx->ifc_ctx_sx);
5552 iflib_msix_init(if_ctx_t ctx)
5554 device_t dev = ctx->ifc_dev;
5555 if_shared_ctx_t sctx = ctx->ifc_sctx;
5556 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5557 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5558 int iflib_num_tx_queues, iflib_num_rx_queues;
5559 int err, admincnt, bar;
5561 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5562 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5564 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5566 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5567 admincnt = sctx->isc_admin_intrcnt;
5568 /* Override by global tuneable */
5571 size_t len = sizeof(i);
5572 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0);
5578 device_printf(dev, "unable to read hw.pci.enable_msix.");
5581 /* Override by tuneable */
5582 if (scctx->isc_disable_msix)
5586 ** When used in a virtualized environment
5587 ** PCI BUSMASTER capability may not be set
5588 ** so explicity set it here and rewrite
5589 ** the ENABLE in the MSIX control register
5590 ** at this point to cause the host to
5591 ** successfully initialize us.
5596 pci_enable_busmaster(dev);
5598 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5599 rid += PCIR_MSIX_CTRL;
5600 msix_ctrl = pci_read_config(dev, rid, 2);
5601 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5602 pci_write_config(dev, rid, msix_ctrl, 2);
5604 device_printf(dev, "PCIY_MSIX capability not found; "
5605 "or rid %d == 0.\n", rid);
5611 * bar == -1 => "trust me I know what I'm doing"
5612 * Some drivers are for hardware that is so shoddily
5613 * documented that no one knows which bars are which
5614 * so the developer has to map all bars. This hack
5615 * allows shoddy garbage to use msix in this framework.
5618 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5619 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5620 if (ctx->ifc_msix_mem == NULL) {
5621 /* May not be enabled */
5622 device_printf(dev, "Unable to map MSIX table \n");
5626 /* First try MSI/X */
5627 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5628 device_printf(dev, "System has MSIX disabled \n");
5629 bus_release_resource(dev, SYS_RES_MEMORY,
5630 bar, ctx->ifc_msix_mem);
5631 ctx->ifc_msix_mem = NULL;
5635 /* use only 1 qset in debug mode */
5636 queuemsgs = min(msgs - admincnt, 1);
5638 queuemsgs = msgs - admincnt;
5641 queues = imin(queuemsgs, rss_getnumbuckets());
5645 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5646 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5647 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5649 /* If we're doing RSS, clamp at the number of RSS buckets */
5650 if (queues > rss_getnumbuckets())
5651 queues = rss_getnumbuckets();
5653 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5654 rx_queues = iflib_num_rx_queues;
5658 if (rx_queues > scctx->isc_nrxqsets)
5659 rx_queues = scctx->isc_nrxqsets;
5662 * We want this to be all logical CPUs by default
5664 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5665 tx_queues = iflib_num_tx_queues;
5667 tx_queues = mp_ncpus;
5669 if (tx_queues > scctx->isc_ntxqsets)
5670 tx_queues = scctx->isc_ntxqsets;
5672 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5674 if (tx_queues != rx_queues)
5675 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5676 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5678 tx_queues = min(rx_queues, tx_queues);
5679 rx_queues = min(rx_queues, tx_queues);
5682 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5684 vectors = rx_queues + admincnt;
5685 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5687 "Using MSIX interrupts with %d vectors\n", vectors);
5688 scctx->isc_vectors = vectors;
5689 scctx->isc_nrxqsets = rx_queues;
5690 scctx->isc_ntxqsets = tx_queues;
5691 scctx->isc_intr = IFLIB_INTR_MSIX;
5695 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5698 vectors = pci_msi_count(dev);
5699 scctx->isc_nrxqsets = 1;
5700 scctx->isc_ntxqsets = 1;
5701 scctx->isc_vectors = vectors;
5702 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5703 device_printf(dev,"Using an MSI interrupt\n");
5704 scctx->isc_intr = IFLIB_INTR_MSI;
5706 device_printf(dev,"Using a Legacy interrupt\n");
5707 scctx->isc_intr = IFLIB_INTR_LEGACY;
5713 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5716 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5719 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5721 char *ring_state = "UNKNOWN";
5724 rc = sysctl_wire_old_buffer(req, 0);
5728 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5733 ring_state = ring_states[state[3]];
5735 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5736 state[0], state[1], state[2], ring_state);
5737 rc = sbuf_finish(sb);
5742 enum iflib_ndesc_handler {
5748 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5750 if_ctx_t ctx = (void *)arg1;
5751 enum iflib_ndesc_handler type = arg2;
5752 char buf[256] = {0};
5757 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5761 case IFLIB_NTXD_HANDLER:
5762 ndesc = ctx->ifc_sysctl_ntxds;
5764 nqs = ctx->ifc_sctx->isc_ntxqs;
5766 case IFLIB_NRXD_HANDLER:
5767 ndesc = ctx->ifc_sysctl_nrxds;
5769 nqs = ctx->ifc_sctx->isc_nrxqs;
5772 panic("unhandled type");
5777 for (i=0; i<8; i++) {
5782 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5785 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5786 if (rc || req->newptr == NULL)
5789 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5790 i++, p = strsep(&next, " ,")) {
5791 ndesc[i] = strtoul(p, NULL, 10);
5797 #define NAME_BUFLEN 32
5799 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5801 device_t dev = iflib_get_dev(ctx);
5802 struct sysctl_oid_list *child, *oid_list;
5803 struct sysctl_ctx_list *ctx_list;
5804 struct sysctl_oid *node;
5806 ctx_list = device_get_sysctl_ctx(dev);
5807 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5808 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5809 CTLFLAG_RD, NULL, "IFLIB fields");
5810 oid_list = SYSCTL_CHILDREN(node);
5812 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5813 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5816 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5817 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5818 "# of txqs to use, 0 => use default #");
5819 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5820 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5821 "# of rxqs to use, 0 => use default #");
5822 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5823 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5824 "permit #txq != #rxq");
5825 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5826 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5827 "disable MSIX (default 0)");
5828 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
5829 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
5830 "set the rx budget");
5832 /* XXX change for per-queue sizes */
5833 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5834 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5835 mp_ndesc_handler, "A",
5836 "list of # of tx descriptors to use, 0 = use default #");
5837 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5838 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5839 mp_ndesc_handler, "A",
5840 "list of # of rx descriptors to use, 0 = use default #");
5844 iflib_add_device_sysctl_post(if_ctx_t ctx)
5846 if_shared_ctx_t sctx = ctx->ifc_sctx;
5847 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5848 device_t dev = iflib_get_dev(ctx);
5849 struct sysctl_oid_list *child;
5850 struct sysctl_ctx_list *ctx_list;
5855 char namebuf[NAME_BUFLEN];
5857 struct sysctl_oid *queue_node, *fl_node, *node;
5858 struct sysctl_oid_list *queue_list, *fl_list;
5859 ctx_list = device_get_sysctl_ctx(dev);
5861 node = ctx->ifc_sysctl_node;
5862 child = SYSCTL_CHILDREN(node);
5864 if (scctx->isc_ntxqsets > 100)
5866 else if (scctx->isc_ntxqsets > 10)
5870 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5871 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5872 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5873 CTLFLAG_RD, NULL, "Queue Name");
5874 queue_list = SYSCTL_CHILDREN(queue_node);
5876 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5878 &txq->ift_dequeued, "total mbufs freed");
5879 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5881 &txq->ift_enqueued, "total mbufs enqueued");
5883 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5885 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5886 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5888 &txq->ift_pullups, "# of times m_pullup was called");
5889 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5891 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5892 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5894 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5895 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5897 &txq->ift_map_failed, "# of times dma map failed");
5898 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5900 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5901 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5903 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5904 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5906 &txq->ift_pidx, 1, "Producer Index");
5907 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5909 &txq->ift_cidx, 1, "Consumer Index");
5910 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5912 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5913 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5915 &txq->ift_in_use, 1, "descriptors in use");
5916 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5918 &txq->ift_processed, "descriptors procesed for clean");
5919 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5921 &txq->ift_cleaned, "total cleaned");
5922 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5923 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5924 0, mp_ring_state_handler, "A", "soft ring state");
5925 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5926 CTLFLAG_RD, &txq->ift_br->enqueues,
5927 "# of enqueues to the mp_ring for this queue");
5928 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5929 CTLFLAG_RD, &txq->ift_br->drops,
5930 "# of drops in the mp_ring for this queue");
5931 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5932 CTLFLAG_RD, &txq->ift_br->starts,
5933 "# of normal consumer starts in the mp_ring for this queue");
5934 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5935 CTLFLAG_RD, &txq->ift_br->stalls,
5936 "# of consumer stalls in the mp_ring for this queue");
5937 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5938 CTLFLAG_RD, &txq->ift_br->restarts,
5939 "# of consumer restarts in the mp_ring for this queue");
5940 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5941 CTLFLAG_RD, &txq->ift_br->abdications,
5942 "# of consumer abdications in the mp_ring for this queue");
5945 if (scctx->isc_nrxqsets > 100)
5947 else if (scctx->isc_nrxqsets > 10)
5951 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5952 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5953 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5954 CTLFLAG_RD, NULL, "Queue Name");
5955 queue_list = SYSCTL_CHILDREN(queue_node);
5956 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5957 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5959 &rxq->ifr_cq_pidx, 1, "Producer Index");
5960 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5962 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5965 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5966 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5967 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5968 CTLFLAG_RD, NULL, "freelist Name");
5969 fl_list = SYSCTL_CHILDREN(fl_node);
5970 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5972 &fl->ifl_pidx, 1, "Producer Index");
5973 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5975 &fl->ifl_cidx, 1, "Consumer Index");
5976 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5978 &fl->ifl_credits, 1, "credits available");
5980 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5982 &fl->ifl_m_enqueued, "mbufs allocated");
5983 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5985 &fl->ifl_m_dequeued, "mbufs freed");
5986 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5988 &fl->ifl_cl_enqueued, "clusters allocated");
5989 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5991 &fl->ifl_cl_dequeued, "clusters freed");
5999 #ifndef __NO_STRICT_ALIGNMENT
6000 static struct mbuf *
6001 iflib_fixup_rx(struct mbuf *m)
6005 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6006 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6007 m->m_data += ETHER_HDR_LEN;
6010 MGETHDR(n, M_NOWAIT, MT_DATA);
6015 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6016 m->m_data += ETHER_HDR_LEN;
6017 m->m_len -= ETHER_HDR_LEN;
6018 n->m_len = ETHER_HDR_LEN;
6019 M_MOVE_PKTHDR(n, m);
6028 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6032 ctx = if_getsoftc(ifp);
6034 *nrxr = NRXQSETS(ctx);
6035 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6036 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6041 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6044 if_softc_ctx_t scctx;
6049 ctx = if_getsoftc(ifp);
6050 scctx = &ctx->ifc_softc_ctx;
6054 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6055 rxq = &ctx->ifc_rxqs[i];
6056 for (j = 0; j < rxq->ifr_nfl; j++) {
6058 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6061 iflib_no_tx_batch = 1;
6069 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6075 ctx = if_getsoftc(ifp);
6076 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6080 txq = &ctx->ifc_txqs[0];
6081 error = iflib_encap(txq, &m);
6083 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6088 iflib_netdump_poll(struct ifnet *ifp, int count)
6091 if_softc_ctx_t scctx;
6095 ctx = if_getsoftc(ifp);
6096 scctx = &ctx->ifc_softc_ctx;
6098 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6102 txq = &ctx->ifc_txqs[0];
6103 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6105 for (i = 0; i < scctx->isc_nrxqsets; i++)
6106 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6109 #endif /* NETDUMP */