2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/sockio.h>
41 #include <sys/kernel.h>
43 #include <sys/mutex.h>
44 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
57 #include <net/if_var.h>
58 #include <net/if_types.h>
59 #include <net/if_media.h>
61 #include <net/ethernet.h>
62 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet6/ip6_var.h>
76 #include <machine/bus.h>
77 #include <machine/in_cksum.h>
82 #include <dev/led/led.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85 #include <dev/pci/pci_private.h>
87 #include <net/iflib.h>
91 #if defined(__i386__) || defined(__amd64__)
92 #include <sys/memdesc.h>
93 #include <machine/bus.h>
94 #include <machine/md_var.h>
95 #include <machine/specialreg.h>
96 #include <x86/include/busdma_impl.h>
97 #include <x86/iommu/busdma_dmar.h>
100 #include <sys/bitstring.h>
102 * enable accounting of every mbuf as it comes in to and goes out of
103 * iflib's software descriptor references
105 #define MEMORY_LOGGING 0
107 * Enable mbuf vectors for compressing long mbuf chains
112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
113 * we prefetch needs to be determined by the time spent in m_free vis a vis
114 * the cost of a prefetch. This will of course vary based on the workload:
115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
116 * is quite expensive, thus suggesting very little prefetch.
117 * - small packet forwarding which is just returning a single mbuf to
118 * UMA will typically be very fast vis a vis the cost of a memory
125 * - private structures
126 * - iflib private utility functions
128 * - vlan registry and other exported functions
129 * - iflib public core functions
133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 uint16_t ifc_nhwtxqs;
171 iflib_txq_t ifc_txqs;
172 iflib_rxq_t ifc_rxqs;
173 uint32_t ifc_if_flags;
175 uint32_t ifc_max_fl_buf_size;
180 int ifc_watchdog_events;
181 struct cdev *ifc_led_dev;
182 struct resource *ifc_msix_mem;
184 struct if_irq ifc_legacy_irq;
185 struct grouptask ifc_admin_task;
186 struct grouptask ifc_vflr_task;
187 struct iflib_filter_info ifc_filter_info;
188 struct ifmedia ifc_media;
190 struct sysctl_oid *ifc_sysctl_node;
191 uint16_t ifc_sysctl_ntxqs;
192 uint16_t ifc_sysctl_nrxqs;
193 uint16_t ifc_sysctl_qs_eq_override;
194 uint16_t ifc_sysctl_rx_budget;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 uint8_t ifc_mac[ETHER_ADDR_LEN];
212 char ifc_mtx_name[16];
217 iflib_get_softc(if_ctx_t ctx)
220 return (ctx->ifc_softc);
224 iflib_get_dev(if_ctx_t ctx)
227 return (ctx->ifc_dev);
231 iflib_get_ifp(if_ctx_t ctx)
234 return (ctx->ifc_ifp);
238 iflib_get_media(if_ctx_t ctx)
241 return (&ctx->ifc_media);
245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
252 iflib_get_softc_ctx(if_ctx_t ctx)
255 return (&ctx->ifc_softc_ctx);
259 iflib_get_sctx(if_ctx_t ctx)
262 return (ctx->ifc_sctx);
265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
272 #define RX_SW_DESC_MAP_CREATED (1 << 0)
273 #define TX_SW_DESC_MAP_CREATED (1 << 1)
274 #define RX_SW_DESC_INUSE (1 << 3)
275 #define TX_SW_DESC_MAPPED (1 << 4)
277 #define M_TOOBIG M_PROTO1
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 struct mbuf **ifsd_m; /* pkthdr mbufs */
293 /* magic number that should be high enough for any hardware */
294 #define IFLIB_MAX_TX_SEGS 128
295 /* bnxt supports 64 with hardware LRO enabled */
296 #define IFLIB_MAX_RX_SEGS 64
297 #define IFLIB_RX_COPY_THRESH 128
298 #define IFLIB_MAX_RX_REFRESH 32
299 /* The minimum descriptors per second before we start coalescing */
300 #define IFLIB_MIN_DESC_SEC 16384
301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
302 #define IFLIB_QUEUE_IDLE 0
303 #define IFLIB_QUEUE_HUNG 1
304 #define IFLIB_QUEUE_WORKING 2
305 /* maximum number of txqs that can share an rx interrupt */
306 #define IFLIB_MAX_TX_SHARED_INTR 4
308 /* this should really scale with ring size - this is a fairly arbitrary value */
309 #define TX_BATCH_SIZE 32
311 #define IFLIB_RESTART_BUDGET 8
313 #define IFC_LEGACY 0x001
314 #define IFC_QFLUSH 0x002
315 #define IFC_MULTISEG 0x004
316 #define IFC_DMAR 0x008
317 #define IFC_SC_ALLOCATED 0x010
318 #define IFC_INIT_DONE 0x020
319 #define IFC_PREFETCH 0x040
320 #define IFC_DO_RESET 0x080
321 #define IFC_DO_WATCHDOG 0x100
322 #define IFC_CHECK_HUNG 0x200
325 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
326 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
327 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
331 qidx_t ift_cidx_processed;
334 uint8_t ift_br_offset;
335 uint16_t ift_npending;
336 uint16_t ift_db_pending;
337 uint16_t ift_rs_pending;
339 uint8_t ift_txd_size[8];
340 uint64_t ift_processed;
341 uint64_t ift_cleaned;
342 uint64_t ift_cleaned_prev;
344 uint64_t ift_enqueued;
345 uint64_t ift_dequeued;
347 uint64_t ift_no_tx_dma_setup;
348 uint64_t ift_no_desc_avail;
349 uint64_t ift_mbuf_defrag_failed;
350 uint64_t ift_mbuf_defrag;
351 uint64_t ift_map_failed;
352 uint64_t ift_txd_encap_efbig;
353 uint64_t ift_pullups;
356 struct mtx ift_db_mtx;
358 /* constant values */
360 struct ifmp_ring *ift_br;
361 struct grouptask ift_task;
364 struct callout ift_timer;
366 if_txsd_vec_t ift_sds;
369 uint8_t ift_update_freq;
370 struct iflib_filter_info ift_filter_info;
371 bus_dma_tag_t ift_desc_tag;
372 bus_dma_tag_t ift_tso_desc_tag;
373 iflib_dma_info_t ift_ifdi;
374 #define MTX_NAME_LEN 16
375 char ift_mtx_name[MTX_NAME_LEN];
376 char ift_db_mtx_name[MTX_NAME_LEN];
377 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
378 #ifdef IFLIB_DIAGNOSTICS
379 uint64_t ift_cpu_exec_count[256];
381 } __aligned(CACHE_LINE_SIZE);
388 uint8_t ifl_rxd_size;
390 uint64_t ifl_m_enqueued;
391 uint64_t ifl_m_dequeued;
392 uint64_t ifl_cl_enqueued;
393 uint64_t ifl_cl_dequeued;
397 bitstr_t *ifl_rx_bitmap;
401 uint16_t ifl_buf_size;
404 iflib_rxsd_array_t ifl_sds;
407 bus_dma_tag_t ifl_desc_tag;
408 iflib_dma_info_t ifl_ifdi;
409 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
410 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
411 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
412 } __aligned(CACHE_LINE_SIZE);
415 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
421 else if (pidx < cidx)
422 used = size - cidx + pidx;
423 else if (gen == 0 && pidx == cidx)
425 else if (gen == 1 && pidx == cidx)
433 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
435 #define IDXDIFF(head, tail, wrap) \
436 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
439 /* If there is a separate completion queue -
440 * these are the cq cidx and pidx. Otherwise
447 uint8_t ifr_fl_offset;
453 uint8_t ifr_lro_enabled;
456 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
457 struct lro_ctrl ifr_lc;
458 struct grouptask ifr_task;
459 struct iflib_filter_info ifr_filter_info;
460 iflib_dma_info_t ifr_ifdi;
462 /* dynamically allocate if any drivers need a value substantially larger than this */
463 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
464 #ifdef IFLIB_DIAGNOSTICS
465 uint64_t ifr_cpu_exec_count[256];
467 } __aligned(CACHE_LINE_SIZE);
469 typedef struct if_rxsd {
471 struct mbuf **ifsd_m;
476 /* multiple of word size */
478 #define PKT_INFO_SIZE 6
479 #define RXD_INFO_SIZE 5
480 #define PKT_TYPE uint64_t
482 #define PKT_INFO_SIZE 11
483 #define RXD_INFO_SIZE 8
484 #define PKT_TYPE uint32_t
486 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
487 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
489 typedef struct if_pkt_info_pad {
490 PKT_TYPE pkt_val[PKT_INFO_SIZE];
491 } *if_pkt_info_pad_t;
492 typedef struct if_rxd_info_pad {
493 PKT_TYPE rxd_val[RXD_INFO_SIZE];
494 } *if_rxd_info_pad_t;
496 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
497 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
501 pkt_info_zero(if_pkt_info_t pi)
503 if_pkt_info_pad_t pi_pad;
505 pi_pad = (if_pkt_info_pad_t)pi;
506 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
507 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
509 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
510 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
515 rxd_info_zero(if_rxd_info_t ri)
517 if_rxd_info_pad_t ri_pad;
520 ri_pad = (if_rxd_info_pad_t)ri;
521 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
522 ri_pad->rxd_val[i] = 0;
523 ri_pad->rxd_val[i+1] = 0;
524 ri_pad->rxd_val[i+2] = 0;
525 ri_pad->rxd_val[i+3] = 0;
528 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
533 * Only allow a single packet to take up most 1/nth of the tx ring
535 #define MAX_SINGLE_PACKET_FRACTION 12
536 #define IF_BAD_DMA (bus_addr_t)-1
538 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
540 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
541 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
542 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
543 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
546 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
547 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
548 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
549 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
553 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
554 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
557 /* Our boot-time initialization hook */
558 static int iflib_module_event_handler(module_t, int, void *);
560 static moduledata_t iflib_moduledata = {
562 iflib_module_event_handler,
566 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
567 MODULE_VERSION(iflib, 1);
569 MODULE_DEPEND(iflib, pci, 1, 1, 1);
570 MODULE_DEPEND(iflib, ether, 1, 1, 1);
572 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
573 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
575 #ifndef IFLIB_DEBUG_COUNTERS
577 #define IFLIB_DEBUG_COUNTERS 1
579 #define IFLIB_DEBUG_COUNTERS 0
580 #endif /* !INVARIANTS */
583 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
584 "iflib driver parameters");
587 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
589 static int iflib_min_tx_latency = 0;
590 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
591 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
592 static int iflib_no_tx_batch = 0;
593 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
594 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
597 #if IFLIB_DEBUG_COUNTERS
599 static int iflib_tx_seen;
600 static int iflib_tx_sent;
601 static int iflib_tx_encap;
602 static int iflib_rx_allocs;
603 static int iflib_fl_refills;
604 static int iflib_fl_refills_large;
605 static int iflib_tx_frees;
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
608 &iflib_tx_seen, 0, "# tx mbufs seen");
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
610 &iflib_tx_sent, 0, "# tx mbufs sent");
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
612 &iflib_tx_encap, 0, "# tx mbufs encapped");
613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
614 &iflib_tx_frees, 0, "# tx frees");
615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
616 &iflib_rx_allocs, 0, "# rx allocations");
617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
618 &iflib_fl_refills, 0, "# refills");
619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
620 &iflib_fl_refills_large, 0, "# large refills");
623 static int iflib_txq_drain_flushing;
624 static int iflib_txq_drain_oactive;
625 static int iflib_txq_drain_notready;
626 static int iflib_txq_drain_encapfail;
628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
629 &iflib_txq_drain_flushing, 0, "# drain flushes");
630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
631 &iflib_txq_drain_oactive, 0, "# drain oactives");
632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
633 &iflib_txq_drain_notready, 0, "# drain notready");
634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
635 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
638 static int iflib_encap_load_mbuf_fail;
639 static int iflib_encap_pad_mbuf_fail;
640 static int iflib_encap_txq_avail_fail;
641 static int iflib_encap_txd_encap_fail;
643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
652 static int iflib_task_fn_rxs;
653 static int iflib_rx_intr_enables;
654 static int iflib_fast_intrs;
655 static int iflib_intr_link;
656 static int iflib_intr_msix;
657 static int iflib_rx_unavail;
658 static int iflib_rx_ctx_inactive;
659 static int iflib_rx_zero_len;
660 static int iflib_rx_if_input;
661 static int iflib_rx_mbuf_null;
662 static int iflib_rxd_flush;
664 static int iflib_verbose_debug;
666 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
667 &iflib_intr_link, 0, "# intr link calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
669 &iflib_intr_msix, 0, "# intr msix calls");
670 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
671 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
673 &iflib_rx_intr_enables, 0, "# rx intr enables");
674 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
675 &iflib_fast_intrs, 0, "# fast_intr calls");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
677 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
678 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
679 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
680 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
681 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
683 &iflib_rx_if_input, 0, "# times rxeof called if_input");
684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
685 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
686 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
687 &iflib_rxd_flush, 0, "# times rxd_flush called");
688 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
689 &iflib_verbose_debug, 0, "enable verbose debugging");
691 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
693 iflib_debug_reset(void)
695 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
696 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
697 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
698 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
699 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
700 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
701 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
702 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
703 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
704 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
708 #define DBG_COUNTER_INC(name)
709 static void iflib_debug_reset(void) {}
714 #define IFLIB_DEBUG 0
716 static void iflib_tx_structures_free(if_ctx_t ctx);
717 static void iflib_rx_structures_free(if_ctx_t ctx);
718 static int iflib_queues_alloc(if_ctx_t ctx);
719 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
720 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
721 static int iflib_qset_structures_setup(if_ctx_t ctx);
722 static int iflib_msix_init(if_ctx_t ctx);
723 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
724 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
725 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
726 static int iflib_register(if_ctx_t);
727 static void iflib_init_locked(if_ctx_t ctx);
728 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
729 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
730 static void iflib_ifmp_purge(iflib_txq_t txq);
731 static void _iflib_pre_assert(if_softc_ctx_t scctx);
732 static void iflib_stop(if_ctx_t ctx);
733 static void iflib_if_init_locked(if_ctx_t ctx);
734 #ifndef __NO_STRICT_ALIGNMENT
735 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
739 #include <sys/selinfo.h>
740 #include <net/netmap.h>
741 #include <dev/netmap/netmap_kern.h>
743 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
745 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
748 * device-specific sysctl variables:
750 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
751 * During regular operations the CRC is stripped, but on some
752 * hardware reception of frames not multiple of 64 is slower,
753 * so using crcstrip=0 helps in benchmarks.
755 * iflib_rx_miss, iflib_rx_miss_bufs:
756 * count packets that might be missed due to lost interrupts.
758 SYSCTL_DECL(_dev_netmap);
760 * The xl driver by default strips CRCs and we do not override it.
763 int iflib_crcstrip = 1;
764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
765 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
767 int iflib_rx_miss, iflib_rx_miss_bufs;
768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
769 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
770 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
771 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
774 * Register/unregister. We are already under netmap lock.
775 * Only called on the first register or the last unregister.
778 iflib_netmap_register(struct netmap_adapter *na, int onoff)
780 struct ifnet *ifp = na->ifp;
781 if_ctx_t ctx = ifp->if_softc;
785 IFDI_INTR_DISABLE(ctx);
787 /* Tell the stack that the interface is no longer active */
788 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
791 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
793 /* enable or disable flags and callbacks in na and ifp */
795 nm_set_native_flags(na);
797 nm_clear_native_flags(na);
800 iflib_init_locked(ctx);
801 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
802 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
804 nm_clear_native_flags(na);
810 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
812 struct netmap_adapter *na = kring->na;
813 u_int const lim = kring->nkr_num_slots - 1;
814 u_int head = kring->rhead;
815 struct netmap_ring *ring = kring->ring;
817 struct if_rxd_update iru;
818 if_ctx_t ctx = rxq->ifr_ctx;
819 iflib_fl_t fl = &rxq->ifr_fl[0];
820 uint32_t refill_pidx, nic_i;
822 if (nm_i == head && __predict_true(!init))
824 iru_init(&iru, rxq, 0 /* flid */);
825 map = fl->ifl_sds.ifsd_map;
826 refill_pidx = netmap_idx_k2n(kring, nm_i);
828 * IMPORTANT: we must leave one free slot in the ring,
829 * so move head back by one unit
831 head = nm_prev(head, lim);
832 while (nm_i != head) {
833 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
834 struct netmap_slot *slot = &ring->slot[nm_i];
835 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
836 uint32_t nic_i_dma = refill_pidx;
837 nic_i = netmap_idx_k2n(kring, nm_i);
839 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
841 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
842 return netmap_ring_reinit(kring);
844 fl->ifl_vm_addrs[tmp_pidx] = addr;
845 if (__predict_false(init) && map) {
846 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
847 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
848 /* buffer has changed, reload map */
849 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
851 slot->flags &= ~NS_BUF_CHANGED;
853 nm_i = nm_next(nm_i, lim);
854 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
855 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
858 iru.iru_pidx = refill_pidx;
859 iru.iru_count = tmp_pidx+1;
860 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
866 for (int n = 0; n < iru.iru_count; n++) {
867 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
868 BUS_DMASYNC_PREREAD);
869 /* XXX - change this to not use the netmap func*/
870 nic_i_dma = nm_next(nic_i_dma, lim);
874 kring->nr_hwcur = head;
877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
879 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
884 * Reconcile kernel and user view of the transmit ring.
886 * All information is in the kring.
887 * Userspace wants to send packets up to the one before kring->rhead,
888 * kernel knows kring->nr_hwcur is the first unsent packet.
890 * Here we push packets out (as many as possible), and possibly
891 * reclaim buffers from previously completed transmission.
893 * The caller (netmap) guarantees that there is only one instance
894 * running at any time. Any interference with other driver
895 * methods should be handled by the individual drivers.
898 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
900 struct netmap_adapter *na = kring->na;
901 struct ifnet *ifp = na->ifp;
902 struct netmap_ring *ring = kring->ring;
903 u_int nm_i; /* index into the netmap ring */
904 u_int nic_i; /* index into the NIC ring */
906 u_int const lim = kring->nkr_num_slots - 1;
907 u_int const head = kring->rhead;
908 struct if_pkt_info pi;
911 * interrupts on every tx packet are expensive so request
912 * them every half ring, or where NS_REPORT is set
914 u_int report_frequency = kring->nkr_num_slots >> 1;
915 /* device-specific */
916 if_ctx_t ctx = ifp->if_softc;
917 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
919 if (txq->ift_sds.ifsd_map)
920 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
925 * First part: process new packets to send.
926 * nm_i is the current index in the netmap ring,
927 * nic_i is the corresponding index in the NIC ring.
929 * If we have packets to send (nm_i != head)
930 * iterate over the netmap ring, fetch length and update
931 * the corresponding slot in the NIC ring. Some drivers also
932 * need to update the buffer's physical address in the NIC slot
933 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
935 * The netmap_reload_map() calls is especially expensive,
936 * even when (as in this case) the tag is 0, so do only
937 * when the buffer has actually changed.
939 * If possible do not set the report/intr bit on all slots,
940 * but only a few times per ring or when NS_REPORT is set.
942 * Finally, on 10G and faster drivers, it might be useful
943 * to prefetch the next slot and txr entry.
946 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
948 pi.ipi_segs = txq->ift_segs;
949 pi.ipi_qsidx = kring->ring_id;
950 if (nm_i != head) { /* we have new packets to send */
951 nic_i = netmap_idx_k2n(kring, nm_i);
953 __builtin_prefetch(&ring->slot[nm_i]);
954 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
955 if (txq->ift_sds.ifsd_map)
956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
958 for (n = 0; nm_i != head; n++) {
959 struct netmap_slot *slot = &ring->slot[nm_i];
960 u_int len = slot->len;
962 void *addr = PNMB(na, slot, &paddr);
963 int flags = (slot->flags & NS_REPORT ||
964 nic_i == 0 || nic_i == report_frequency) ?
967 /* device-specific */
969 pi.ipi_segs[0].ds_addr = paddr;
970 pi.ipi_segs[0].ds_len = len;
974 pi.ipi_flags = flags;
976 /* Fill the slot in the NIC ring. */
977 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
979 /* prefetch for next round */
980 __builtin_prefetch(&ring->slot[nm_i + 1]);
981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
982 if (txq->ift_sds.ifsd_map) {
983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
985 NM_CHECK_ADDR_LEN(na, addr, len);
987 if (slot->flags & NS_BUF_CHANGED) {
988 /* buffer has changed, reload map */
989 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
991 /* make sure changes to the buffer are synced */
992 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
993 BUS_DMASYNC_PREWRITE);
995 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
996 nm_i = nm_next(nm_i, lim);
997 nic_i = nm_next(nic_i, lim);
999 kring->nr_hwcur = head;
1001 /* synchronize the NIC ring */
1002 if (txq->ift_sds.ifsd_map)
1003 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1006 /* (re)start the tx unit up to slot nic_i (excluded) */
1007 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1011 * Second part: reclaim buffers for completed transmissions.
1013 if (iflib_tx_credits_update(ctx, txq)) {
1014 /* some tx completed, increment avail */
1015 nic_i = txq->ift_cidx_processed;
1016 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1022 * Reconcile kernel and user view of the receive ring.
1023 * Same as for the txsync, this routine must be efficient.
1024 * The caller guarantees a single invocations, but races against
1025 * the rest of the driver should be handled here.
1027 * On call, kring->rhead is the first packet that userspace wants
1028 * to keep, and kring->rcur is the wakeup point.
1029 * The kernel has previously reported packets up to kring->rtail.
1031 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1032 * of whether or not we received an interrupt.
1035 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1037 struct netmap_adapter *na = kring->na;
1038 struct netmap_ring *ring = kring->ring;
1039 uint32_t nm_i; /* index into the netmap ring */
1040 uint32_t nic_i; /* index into the NIC ring */
1042 u_int const lim = kring->nkr_num_slots - 1;
1043 u_int const head = netmap_idx_n2k(kring, kring->rhead);
1044 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1045 struct if_rxd_info ri;
1047 struct ifnet *ifp = na->ifp;
1048 if_ctx_t ctx = ifp->if_softc;
1049 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1050 iflib_fl_t fl = rxq->ifr_fl;
1052 return netmap_ring_reinit(kring);
1054 /* XXX check sync modes */
1055 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1056 if (fl->ifl_sds.ifsd_map == NULL)
1058 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1059 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1062 * First part: import newly received packets.
1064 * nm_i is the index of the next free slot in the netmap ring,
1065 * nic_i is the index of the next received packet in the NIC ring,
1066 * and they may differ in case if_init() has been called while
1067 * in netmap mode. For the receive ring we have
1069 * nic_i = rxr->next_check;
1070 * nm_i = kring->nr_hwtail (previous)
1072 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1074 * rxr->next_check is set to 0 on a ring reinit
1076 if (netmap_no_pendintr || force_update) {
1077 int crclen = iflib_crcstrip ? 0 : 4;
1080 for (i = 0; i < rxq->ifr_nfl; i++) {
1081 fl = &rxq->ifr_fl[i];
1082 nic_i = fl->ifl_cidx;
1083 nm_i = netmap_idx_n2k(kring, nic_i);
1084 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1085 for (n = 0; avail > 0; n++, avail--) {
1087 ri.iri_frags = rxq->ifr_frags;
1088 ri.iri_qsidx = kring->ring_id;
1089 ri.iri_ifp = ctx->ifc_ifp;
1090 ri.iri_cidx = nic_i;
1092 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1093 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1094 ring->slot[nm_i].flags = 0;
1095 if (fl->ifl_sds.ifsd_map)
1096 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1097 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1098 nm_i = nm_next(nm_i, lim);
1099 nic_i = nm_next(nic_i, lim);
1101 if (n) { /* update the state variables */
1102 if (netmap_no_pendintr && !force_update) {
1105 iflib_rx_miss_bufs += n;
1107 fl->ifl_cidx = nic_i;
1108 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i);
1110 kring->nr_kflags &= ~NKR_PENDINTR;
1114 * Second part: skip past packets that userspace has released.
1115 * (kring->nr_hwcur to head excluded),
1116 * and make the buffers available for reception.
1117 * As usual nm_i is the index in the netmap ring,
1118 * nic_i is the index in the NIC ring, and
1119 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1121 /* XXX not sure how this will work with multiple free lists */
1122 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
1124 return (netmap_fl_refill(rxq, kring, nm_i, false));
1128 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1130 struct ifnet *ifp = na->ifp;
1131 if_ctx_t ctx = ifp->if_softc;
1135 IFDI_INTR_ENABLE(ctx);
1137 IFDI_INTR_DISABLE(ctx);
1144 iflib_netmap_attach(if_ctx_t ctx)
1146 struct netmap_adapter na;
1147 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1149 bzero(&na, sizeof(na));
1151 na.ifp = ctx->ifc_ifp;
1152 na.na_flags = NAF_BDG_MAYSLEEP;
1153 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1154 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1156 na.num_tx_desc = scctx->isc_ntxd[0];
1157 na.num_rx_desc = scctx->isc_nrxd[0];
1158 na.nm_txsync = iflib_netmap_txsync;
1159 na.nm_rxsync = iflib_netmap_rxsync;
1160 na.nm_register = iflib_netmap_register;
1161 na.nm_intr = iflib_netmap_intr;
1162 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1163 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1164 return (netmap_attach(&na));
1168 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1170 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1171 struct netmap_slot *slot;
1173 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1176 if (txq->ift_sds.ifsd_map == NULL)
1179 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1182 * In netmap mode, set the map for the packet buffer.
1183 * NOTE: Some drivers (not this one) also need to set
1184 * the physical buffer address in the NIC ring.
1185 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1186 * netmap slot index, si
1188 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1189 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1194 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1196 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1197 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1198 struct netmap_slot *slot;
1201 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1204 nm_i = netmap_idx_n2k(kring, 0);
1205 netmap_fl_refill(rxq, kring, nm_i, true);
1208 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1211 #define iflib_netmap_txq_init(ctx, txq)
1212 #define iflib_netmap_rxq_init(ctx, rxq)
1213 #define iflib_netmap_detach(ifp)
1215 #define iflib_netmap_attach(ctx) (0)
1216 #define netmap_rx_irq(ifp, qid, budget) (0)
1217 #define netmap_tx_irq(ifp, qid) do {} while (0)
1221 #if defined(__i386__) || defined(__amd64__)
1222 static __inline void
1225 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1227 static __inline void
1228 prefetch2cachelines(void *x)
1230 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1231 #if (CACHE_LINE_SIZE < 128)
1232 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1237 #define prefetch2cachelines(x)
1241 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1245 fl = &rxq->ifr_fl[flid];
1246 iru->iru_paddrs = fl->ifl_bus_addrs;
1247 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1248 iru->iru_idxs = fl->ifl_rxd_idxs;
1249 iru->iru_qsidx = rxq->ifr_id;
1250 iru->iru_buf_size = fl->ifl_buf_size;
1251 iru->iru_flidx = fl->ifl_id;
1255 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1259 *(bus_addr_t *) arg = segs[0].ds_addr;
1263 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1266 if_shared_ctx_t sctx = ctx->ifc_sctx;
1267 device_t dev = ctx->ifc_dev;
1269 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1271 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1272 sctx->isc_q_align, 0, /* alignment, bounds */
1273 BUS_SPACE_MAXADDR, /* lowaddr */
1274 BUS_SPACE_MAXADDR, /* highaddr */
1275 NULL, NULL, /* filter, filterarg */
1278 size, /* maxsegsize */
1279 BUS_DMA_ALLOCNOW, /* flags */
1280 NULL, /* lockfunc */
1285 "%s: bus_dma_tag_create failed: %d\n",
1290 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1291 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1294 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1295 __func__, (uintmax_t)size, err);
1299 dma->idi_paddr = IF_BAD_DMA;
1300 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1301 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1302 if (err || dma->idi_paddr == IF_BAD_DMA) {
1304 "%s: bus_dmamap_load failed: %d\n",
1309 dma->idi_size = size;
1313 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1315 bus_dma_tag_destroy(dma->idi_tag);
1317 dma->idi_tag = NULL;
1323 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1326 iflib_dma_info_t *dmaiter;
1329 for (i = 0; i < count; i++, dmaiter++) {
1330 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1334 iflib_dma_free_multi(dmalist, i);
1339 iflib_dma_free(iflib_dma_info_t dma)
1341 if (dma->idi_tag == NULL)
1343 if (dma->idi_paddr != IF_BAD_DMA) {
1344 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1345 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1346 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1347 dma->idi_paddr = IF_BAD_DMA;
1349 if (dma->idi_vaddr != NULL) {
1350 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1351 dma->idi_vaddr = NULL;
1353 bus_dma_tag_destroy(dma->idi_tag);
1354 dma->idi_tag = NULL;
1358 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1361 iflib_dma_info_t *dmaiter = dmalist;
1363 for (i = 0; i < count; i++, dmaiter++)
1364 iflib_dma_free(*dmaiter);
1367 #ifdef EARLY_AP_STARTUP
1368 static const int iflib_started = 1;
1371 * We used to abuse the smp_started flag to decide if the queues have been
1372 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1373 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1374 * is set. Run a SYSINIT() strictly after that to just set a usable
1378 static int iflib_started;
1381 iflib_record_started(void *arg)
1386 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1387 iflib_record_started, NULL);
1391 iflib_fast_intr(void *arg)
1393 iflib_filter_info_t info = arg;
1394 struct grouptask *gtask = info->ifi_task;
1396 return (FILTER_HANDLED);
1398 DBG_COUNTER_INC(fast_intrs);
1399 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1400 return (FILTER_HANDLED);
1402 GROUPTASK_ENQUEUE(gtask);
1403 return (FILTER_HANDLED);
1407 iflib_fast_intr_rxtx(void *arg)
1409 iflib_filter_info_t info = arg;
1410 struct grouptask *gtask = info->ifi_task;
1411 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1416 return (FILTER_HANDLED);
1418 DBG_COUNTER_INC(fast_intrs);
1419 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1420 return (FILTER_HANDLED);
1422 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1423 qidx_t txqid = rxq->ifr_txqid[i];
1427 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1428 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1431 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1433 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1434 cidx = rxq->ifr_cq_cidx;
1436 cidx = rxq->ifr_fl[0].ifl_cidx;
1437 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1438 GROUPTASK_ENQUEUE(gtask);
1440 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1441 return (FILTER_HANDLED);
1446 iflib_fast_intr_ctx(void *arg)
1448 iflib_filter_info_t info = arg;
1449 struct grouptask *gtask = info->ifi_task;
1452 return (FILTER_HANDLED);
1454 DBG_COUNTER_INC(fast_intrs);
1455 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1456 return (FILTER_HANDLED);
1458 GROUPTASK_ENQUEUE(gtask);
1459 return (FILTER_HANDLED);
1463 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1464 driver_filter_t filter, driver_intr_t handler, void *arg,
1468 struct resource *res;
1470 device_t dev = ctx->ifc_dev;
1473 if (ctx->ifc_flags & IFC_LEGACY)
1474 flags |= RF_SHAREABLE;
1477 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1480 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1484 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1485 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1486 filter, handler, arg, &tag);
1489 "failed to setup interrupt for rid %d, name %s: %d\n",
1490 rid, name ? name : "unknown", rc);
1493 bus_describe_intr(dev, res, tag, "%s", name);
1500 /*********************************************************************
1502 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1503 * the information needed to transmit a packet on the wire. This is
1504 * called only once at attach, setup is done every reset.
1506 **********************************************************************/
1509 iflib_txsd_alloc(iflib_txq_t txq)
1511 if_ctx_t ctx = txq->ift_ctx;
1512 if_shared_ctx_t sctx = ctx->ifc_sctx;
1513 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1514 device_t dev = ctx->ifc_dev;
1515 int err, nsegments, ntsosegments;
1517 nsegments = scctx->isc_tx_nsegments;
1518 ntsosegments = scctx->isc_tx_tso_segments_max;
1519 MPASS(scctx->isc_ntxd[0] > 0);
1520 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1521 MPASS(nsegments > 0);
1522 MPASS(ntsosegments > 0);
1524 * Setup DMA descriptor areas.
1526 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1527 1, 0, /* alignment, bounds */
1528 BUS_SPACE_MAXADDR, /* lowaddr */
1529 BUS_SPACE_MAXADDR, /* highaddr */
1530 NULL, NULL, /* filter, filterarg */
1531 sctx->isc_tx_maxsize, /* maxsize */
1532 nsegments, /* nsegments */
1533 sctx->isc_tx_maxsegsize, /* maxsegsize */
1535 NULL, /* lockfunc */
1536 NULL, /* lockfuncarg */
1537 &txq->ift_desc_tag))) {
1538 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1539 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1540 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1543 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1544 1, 0, /* alignment, bounds */
1545 BUS_SPACE_MAXADDR, /* lowaddr */
1546 BUS_SPACE_MAXADDR, /* highaddr */
1547 NULL, NULL, /* filter, filterarg */
1548 scctx->isc_tx_tso_size_max, /* maxsize */
1549 ntsosegments, /* nsegments */
1550 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1552 NULL, /* lockfunc */
1553 NULL, /* lockfuncarg */
1554 &txq->ift_tso_desc_tag))) {
1555 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1559 if (!(txq->ift_sds.ifsd_flags =
1560 (uint8_t *) malloc(sizeof(uint8_t) *
1561 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1562 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1566 if (!(txq->ift_sds.ifsd_m =
1567 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1568 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1569 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1574 /* Create the descriptor buffer dma maps */
1575 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1576 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1579 if (!(txq->ift_sds.ifsd_map =
1580 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1581 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1586 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1587 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1589 device_printf(dev, "Unable to create TX DMA map\n");
1596 /* We free all, it handles case where we are in the middle */
1597 iflib_tx_structures_free(ctx);
1602 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1607 if (txq->ift_sds.ifsd_map != NULL)
1608 map = txq->ift_sds.ifsd_map[i];
1610 bus_dmamap_unload(txq->ift_desc_tag, map);
1611 bus_dmamap_destroy(txq->ift_desc_tag, map);
1612 txq->ift_sds.ifsd_map[i] = NULL;
1617 iflib_txq_destroy(iflib_txq_t txq)
1619 if_ctx_t ctx = txq->ift_ctx;
1621 for (int i = 0; i < txq->ift_size; i++)
1622 iflib_txsd_destroy(ctx, txq, i);
1623 if (txq->ift_sds.ifsd_map != NULL) {
1624 free(txq->ift_sds.ifsd_map, M_IFLIB);
1625 txq->ift_sds.ifsd_map = NULL;
1627 if (txq->ift_sds.ifsd_m != NULL) {
1628 free(txq->ift_sds.ifsd_m, M_IFLIB);
1629 txq->ift_sds.ifsd_m = NULL;
1631 if (txq->ift_sds.ifsd_flags != NULL) {
1632 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1633 txq->ift_sds.ifsd_flags = NULL;
1635 if (txq->ift_desc_tag != NULL) {
1636 bus_dma_tag_destroy(txq->ift_desc_tag);
1637 txq->ift_desc_tag = NULL;
1639 if (txq->ift_tso_desc_tag != NULL) {
1640 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1641 txq->ift_tso_desc_tag = NULL;
1646 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1650 mp = &txq->ift_sds.ifsd_m[i];
1654 if (txq->ift_sds.ifsd_map != NULL) {
1655 bus_dmamap_sync(txq->ift_desc_tag,
1656 txq->ift_sds.ifsd_map[i],
1657 BUS_DMASYNC_POSTWRITE);
1658 bus_dmamap_unload(txq->ift_desc_tag,
1659 txq->ift_sds.ifsd_map[i]);
1662 DBG_COUNTER_INC(tx_frees);
1667 iflib_txq_setup(iflib_txq_t txq)
1669 if_ctx_t ctx = txq->ift_ctx;
1670 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1671 iflib_dma_info_t di;
1674 /* Set number of descriptors available */
1675 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1676 /* XXX make configurable */
1677 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1680 txq->ift_cidx_processed = 0;
1681 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1682 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1684 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1685 bzero((void *)di->idi_vaddr, di->idi_size);
1687 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1688 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1689 bus_dmamap_sync(di->idi_tag, di->idi_map,
1690 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1694 /*********************************************************************
1696 * Allocate memory for rx_buffer structures. Since we use one
1697 * rx_buffer per received packet, the maximum number of rx_buffer's
1698 * that we'll need is equal to the number of receive descriptors
1699 * that we've allocated.
1701 **********************************************************************/
1703 iflib_rxsd_alloc(iflib_rxq_t rxq)
1705 if_ctx_t ctx = rxq->ifr_ctx;
1706 if_shared_ctx_t sctx = ctx->ifc_sctx;
1707 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1708 device_t dev = ctx->ifc_dev;
1712 MPASS(scctx->isc_nrxd[0] > 0);
1713 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1716 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1717 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1718 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1719 1, 0, /* alignment, bounds */
1720 BUS_SPACE_MAXADDR, /* lowaddr */
1721 BUS_SPACE_MAXADDR, /* highaddr */
1722 NULL, NULL, /* filter, filterarg */
1723 sctx->isc_rx_maxsize, /* maxsize */
1724 sctx->isc_rx_nsegments, /* nsegments */
1725 sctx->isc_rx_maxsegsize, /* maxsegsize */
1727 NULL, /* lockfunc */
1731 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1735 if (!(fl->ifl_sds.ifsd_flags =
1736 (uint8_t *) malloc(sizeof(uint8_t) *
1737 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1738 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1742 if (!(fl->ifl_sds.ifsd_m =
1743 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1744 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1745 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1749 if (!(fl->ifl_sds.ifsd_cl =
1750 (caddr_t *) malloc(sizeof(caddr_t) *
1751 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1752 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1757 /* Create the descriptor buffer dma maps */
1758 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1759 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1762 if (!(fl->ifl_sds.ifsd_map =
1763 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1764 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1769 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1770 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1772 device_printf(dev, "Unable to create RX buffer DMA map\n");
1781 iflib_rx_structures_free(ctx);
1787 * Internal service routines
1790 struct rxq_refill_cb_arg {
1792 bus_dma_segment_t seg;
1797 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1799 struct rxq_refill_cb_arg *cb_arg = arg;
1801 cb_arg->error = error;
1802 cb_arg->seg = segs[0];
1803 cb_arg->nseg = nseg;
1808 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1810 #define IS_DMAR(ctx) (0)
1814 * rxq_refill - refill an rxq free-buffer list
1815 * @ctx: the iflib context
1816 * @rxq: the free-list to refill
1817 * @n: the number of new buffers to allocate
1819 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1820 * The caller must assure that @n does not exceed the queue's capacity.
1823 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1826 int idx, frag_idx = fl->ifl_fragidx;
1827 int pidx = fl->ifl_pidx;
1831 struct if_rxd_update iru;
1832 bus_dmamap_t *sd_map;
1838 sd_m = fl->ifl_sds.ifsd_m;
1839 sd_map = fl->ifl_sds.ifsd_map;
1840 sd_cl = fl->ifl_sds.ifsd_cl;
1841 sd_flags = fl->ifl_sds.ifsd_flags;
1843 credits = fl->ifl_credits;
1847 MPASS(credits + n <= fl->ifl_size);
1849 if (pidx < fl->ifl_cidx)
1850 MPASS(pidx + n <= fl->ifl_cidx);
1851 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1852 MPASS(fl->ifl_gen == 0);
1853 if (pidx > fl->ifl_cidx)
1854 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1856 DBG_COUNTER_INC(fl_refills);
1858 DBG_COUNTER_INC(fl_refills_large);
1859 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1862 * We allocate an uninitialized mbuf + cluster, mbuf is
1863 * initialized after rx.
1865 * If the cluster is still set then we know a minimum sized packet was received
1867 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1868 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1869 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1870 if ((cl = sd_cl[frag_idx]) == NULL) {
1871 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1874 fl->ifl_cl_enqueued++;
1877 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1881 fl->ifl_m_enqueued++;
1884 DBG_COUNTER_INC(rx_allocs);
1885 #if defined(__i386__) || defined(__amd64__)
1886 if (!IS_DMAR(ctx)) {
1887 bus_addr = pmap_kextract((vm_offset_t)cl);
1891 struct rxq_refill_cb_arg cb_arg;
1896 MPASS(sd_map != NULL);
1897 MPASS(sd_map[frag_idx] != NULL);
1898 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1899 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1900 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1901 BUS_DMASYNC_PREREAD);
1903 if (err != 0 || cb_arg.error) {
1907 if (fl->ifl_zone == zone_pack)
1908 uma_zfree(fl->ifl_zone, cl);
1913 bus_addr = cb_arg.seg.ds_addr;
1915 bit_set(fl->ifl_rx_bitmap, frag_idx);
1916 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1918 MPASS(sd_m[frag_idx] == NULL);
1919 sd_cl[frag_idx] = cl;
1921 fl->ifl_rxd_idxs[i] = frag_idx;
1922 fl->ifl_bus_addrs[i] = bus_addr;
1923 fl->ifl_vm_addrs[i] = cl;
1926 MPASS(credits <= fl->ifl_size);
1927 if (++idx == fl->ifl_size) {
1931 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1932 iru.iru_pidx = pidx;
1934 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1938 fl->ifl_credits = credits;
1944 iru.iru_pidx = pidx;
1946 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1948 fl->ifl_credits = credits;
1950 DBG_COUNTER_INC(rxd_flush);
1951 if (fl->ifl_pidx == 0)
1952 pidx = fl->ifl_size - 1;
1954 pidx = fl->ifl_pidx - 1;
1957 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1959 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1960 fl->ifl_fragidx = frag_idx;
1963 static __inline void
1964 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1966 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1967 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1969 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1972 MPASS(fl->ifl_credits <= fl->ifl_size);
1973 MPASS(reclaimable == delta);
1975 if (reclaimable > 0)
1976 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1980 iflib_fl_bufs_free(iflib_fl_t fl)
1982 iflib_dma_info_t idi = fl->ifl_ifdi;
1985 for (i = 0; i < fl->ifl_size; i++) {
1986 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1987 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1988 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1990 if (*sd_flags & RX_SW_DESC_INUSE) {
1991 if (fl->ifl_sds.ifsd_map != NULL) {
1992 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1993 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1994 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
1995 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1997 if (*sd_m != NULL) {
1998 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1999 uma_zfree(zone_mbuf, *sd_m);
2002 uma_zfree(fl->ifl_zone, *sd_cl);
2005 MPASS(*sd_cl == NULL);
2006 MPASS(*sd_m == NULL);
2009 fl->ifl_m_dequeued++;
2010 fl->ifl_cl_dequeued++;
2016 for (i = 0; i < fl->ifl_size; i++) {
2017 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2018 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2019 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2023 * Reset free list values
2025 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2026 bzero(idi->idi_vaddr, idi->idi_size);
2029 /*********************************************************************
2031 * Initialize a receive ring and its buffers.
2033 **********************************************************************/
2035 iflib_fl_setup(iflib_fl_t fl)
2037 iflib_rxq_t rxq = fl->ifl_rxq;
2038 if_ctx_t ctx = rxq->ifr_ctx;
2039 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2041 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2043 ** Free current RX buffer structs and their mbufs
2045 iflib_fl_bufs_free(fl);
2046 /* Now replenish the mbufs */
2047 MPASS(fl->ifl_credits == 0);
2049 * XXX don't set the max_frame_size to larger
2050 * than the hardware can handle
2052 if (sctx->isc_max_frame_size <= 2048)
2053 fl->ifl_buf_size = MCLBYTES;
2054 #ifndef CONTIGMALLOC_WORKS
2056 fl->ifl_buf_size = MJUMPAGESIZE;
2058 else if (sctx->isc_max_frame_size <= 4096)
2059 fl->ifl_buf_size = MJUMPAGESIZE;
2060 else if (sctx->isc_max_frame_size <= 9216)
2061 fl->ifl_buf_size = MJUM9BYTES;
2063 fl->ifl_buf_size = MJUM16BYTES;
2065 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2066 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2067 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2068 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2071 /* avoid pre-allocating zillions of clusters to an idle card
2072 * potentially speeding up attach
2074 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2075 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2076 if (min(128, fl->ifl_size) != fl->ifl_credits)
2082 MPASS(fl->ifl_ifdi != NULL);
2083 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2088 /*********************************************************************
2090 * Free receive ring data structures
2092 **********************************************************************/
2094 iflib_rx_sds_free(iflib_rxq_t rxq)
2099 if (rxq->ifr_fl != NULL) {
2100 for (i = 0; i < rxq->ifr_nfl; i++) {
2101 fl = &rxq->ifr_fl[i];
2102 if (fl->ifl_desc_tag != NULL) {
2103 bus_dma_tag_destroy(fl->ifl_desc_tag);
2104 fl->ifl_desc_tag = NULL;
2106 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2107 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2108 /* XXX destroy maps first */
2109 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2110 fl->ifl_sds.ifsd_m = NULL;
2111 fl->ifl_sds.ifsd_cl = NULL;
2112 fl->ifl_sds.ifsd_map = NULL;
2114 free(rxq->ifr_fl, M_IFLIB);
2116 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2121 * MI independent logic
2125 iflib_timer(void *arg)
2127 iflib_txq_t txq = arg;
2128 if_ctx_t ctx = txq->ift_ctx;
2129 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2131 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2134 ** Check on the state of the TX queue(s), this
2135 ** can be done without the lock because its RO
2136 ** and the HUNG state will be static if set.
2138 IFDI_TIMER(ctx, txq->ift_id);
2139 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2140 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2141 (sctx->isc_pause_frames == 0)))
2144 if (ifmp_ring_is_stalled(txq->ift_br))
2145 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2146 txq->ift_cleaned_prev = txq->ift_cleaned;
2147 /* handle any laggards */
2148 if (txq->ift_db_pending)
2149 GROUPTASK_ENQUEUE(&txq->ift_task);
2151 sctx->isc_pause_frames = 0;
2152 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2153 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2156 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2157 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2159 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2160 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2161 iflib_admin_intr_deferred(ctx);
2166 iflib_init_locked(if_ctx_t ctx)
2168 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2169 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2170 if_t ifp = ctx->ifc_ifp;
2174 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2177 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2178 IFDI_INTR_DISABLE(ctx);
2180 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2181 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2182 /* Set hardware offload abilities */
2183 if_clearhwassist(ifp);
2184 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2185 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2186 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2187 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2188 if (if_getcapenable(ifp) & IFCAP_TSO4)
2189 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2190 if (if_getcapenable(ifp) & IFCAP_TSO6)
2191 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2193 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2195 callout_stop(&txq->ift_timer);
2196 CALLOUT_UNLOCK(txq);
2197 iflib_netmap_txq_init(ctx, txq);
2200 i = if_getdrvflags(ifp);
2203 MPASS(if_getdrvflags(ifp) == i);
2204 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2205 /* XXX this should really be done on a per-queue basis */
2206 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2207 MPASS(rxq->ifr_id == i);
2208 iflib_netmap_rxq_init(ctx, rxq);
2211 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2212 if (iflib_fl_setup(fl)) {
2213 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2219 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2220 IFDI_INTR_ENABLE(ctx);
2221 txq = ctx->ifc_txqs;
2222 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2223 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2224 txq->ift_timer.c_cpu);
2228 iflib_media_change(if_t ifp)
2230 if_ctx_t ctx = if_getsoftc(ifp);
2234 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2235 iflib_init_locked(ctx);
2241 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2243 if_ctx_t ctx = if_getsoftc(ifp);
2246 IFDI_UPDATE_ADMIN_STATUS(ctx);
2247 IFDI_MEDIA_STATUS(ctx, ifmr);
2252 iflib_stop(if_ctx_t ctx)
2254 iflib_txq_t txq = ctx->ifc_txqs;
2255 iflib_rxq_t rxq = ctx->ifc_rxqs;
2256 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2257 iflib_dma_info_t di;
2261 /* Tell the stack that the interface is no longer active */
2262 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2264 IFDI_INTR_DISABLE(ctx);
2269 iflib_debug_reset();
2270 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2271 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2272 /* make sure all transmitters have completed before proceeding XXX */
2275 callout_stop(&txq->ift_timer);
2276 CALLOUT_UNLOCK(txq);
2278 /* clean any enqueued buffers */
2279 iflib_ifmp_purge(txq);
2280 /* Free any existing tx buffers. */
2281 for (j = 0; j < txq->ift_size; j++) {
2282 iflib_txsd_free(ctx, txq, j);
2284 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2285 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2286 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2287 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2288 txq->ift_pullups = 0;
2289 ifmp_ring_reset_stats(txq->ift_br);
2290 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2291 bzero((void *)di->idi_vaddr, di->idi_size);
2293 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2294 /* make sure all transmitters have completed before proceeding XXX */
2296 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++)
2297 bzero((void *)di->idi_vaddr, di->idi_size);
2298 /* also resets the free lists pidx/cidx */
2299 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2300 iflib_fl_bufs_free(fl);
2304 static inline caddr_t
2305 calc_next_rxd(iflib_fl_t fl, int cidx)
2309 caddr_t start, end, cur, next;
2311 nrxd = fl->ifl_size;
2312 size = fl->ifl_rxd_size;
2313 start = fl->ifl_ifdi->idi_vaddr;
2315 if (__predict_false(size == 0))
2317 cur = start + size*cidx;
2318 end = start + size*nrxd;
2319 next = CACHE_PTR_NEXT(cur);
2320 return (next < end ? next : start);
2324 prefetch_pkts(iflib_fl_t fl, int cidx)
2327 int nrxd = fl->ifl_size;
2331 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2332 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2333 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2334 next_rxd = calc_next_rxd(fl, cidx);
2336 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2337 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2338 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2339 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2340 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2341 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2342 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2343 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2347 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2352 iflib_dma_info_t di;
2356 flid = irf->irf_flid;
2357 cidx = irf->irf_idx;
2358 fl = &rxq->ifr_fl[flid];
2360 sd->ifsd_cidx = cidx;
2361 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2362 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2365 fl->ifl_m_dequeued++;
2367 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2368 prefetch_pkts(fl, cidx);
2369 if (fl->ifl_sds.ifsd_map != NULL) {
2370 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2371 prefetch(&fl->ifl_sds.ifsd_map[next]);
2372 map = fl->ifl_sds.ifsd_map[cidx];
2374 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2375 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2376 bus_dmamap_sync(di->idi_tag, di->idi_map,
2377 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2379 /* not valid assert if bxe really does SGE from non-contiguous elements */
2380 MPASS(fl->ifl_cidx == cidx);
2382 bus_dmamap_unload(fl->ifl_desc_tag, map);
2384 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2385 if (__predict_false(fl->ifl_cidx == 0))
2388 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2390 bit_clear(fl->ifl_rx_bitmap, cidx);
2393 static struct mbuf *
2394 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2396 int i, padlen , flags;
2397 struct mbuf *m, *mh, *mt;
2403 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2405 MPASS(*sd->ifsd_cl != NULL);
2406 MPASS(*sd->ifsd_m != NULL);
2408 /* Don't include zero-length frags */
2409 if (ri->iri_frags[i].irf_len == 0) {
2410 /* XXX we can save the cluster here, but not the mbuf */
2411 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2412 m_free(*sd->ifsd_m);
2419 flags = M_PKTHDR|M_EXT;
2421 padlen = ri->iri_pad;
2426 /* assuming padding is only on the first fragment */
2430 *sd->ifsd_cl = NULL;
2432 /* Can these two be made one ? */
2433 m_init(m, M_NOWAIT, MT_DATA, flags);
2434 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2436 * These must follow m_init and m_cljset
2438 m->m_data += padlen;
2439 ri->iri_len -= padlen;
2440 m->m_len = ri->iri_frags[i].irf_len;
2441 } while (++i < ri->iri_nfrags);
2447 * Process one software descriptor
2449 static struct mbuf *
2450 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2455 /* should I merge this back in now that the two paths are basically duplicated? */
2456 if (ri->iri_nfrags == 1 &&
2457 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2458 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2461 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2462 #ifndef __NO_STRICT_ALIGNMENT
2466 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2467 m->m_len = ri->iri_frags[0].irf_len;
2469 m = assemble_segments(rxq, ri, &sd);
2471 m->m_pkthdr.len = ri->iri_len;
2472 m->m_pkthdr.rcvif = ri->iri_ifp;
2473 m->m_flags |= ri->iri_flags;
2474 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2475 m->m_pkthdr.flowid = ri->iri_flowid;
2476 M_HASHTYPE_SET(m, ri->iri_rsstype);
2477 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2478 m->m_pkthdr.csum_data = ri->iri_csum_data;
2482 #if defined(INET6) || defined(INET)
2484 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2486 CURVNET_SET(lc->ifp->if_vnet);
2488 *v6 = VNET(ip6_forwarding);
2491 *v4 = VNET(ipforwarding);
2497 * Returns true if it's possible this packet could be LROed.
2498 * if it returns false, it is guaranteed that tcp_lro_rx()
2499 * would not return zero.
2502 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2504 struct ether_header *eh;
2507 eh = mtod(m, struct ether_header *);
2508 eh_type = ntohs(eh->ether_type);
2511 case ETHERTYPE_IPV6:
2512 return !v6_forwarding;
2516 return !v4_forwarding;
2524 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2530 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2532 if_ctx_t ctx = rxq->ifr_ctx;
2533 if_shared_ctx_t sctx = ctx->ifc_sctx;
2534 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2537 struct if_rxd_info ri;
2538 int err, budget_left, rx_bytes, rx_pkts;
2542 bool lro_possible = false;
2543 bool v4_forwarding, v6_forwarding;
2546 * XXX early demux data packets so that if_input processing only handles
2547 * acks in interrupt context
2549 struct mbuf *m, *mh, *mt, *mf;
2554 rx_pkts = rx_bytes = 0;
2555 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2556 cidxp = &rxq->ifr_cq_cidx;
2558 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2559 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2560 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2561 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2562 DBG_COUNTER_INC(rx_unavail);
2566 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2567 if (__predict_false(!CTX_ACTIVE(ctx))) {
2568 DBG_COUNTER_INC(rx_ctx_inactive);
2572 * Reset client set fields to their default values
2575 ri.iri_qsidx = rxq->ifr_id;
2576 ri.iri_cidx = *cidxp;
2578 ri.iri_frags = rxq->ifr_frags;
2579 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2583 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2584 *cidxp = ri.iri_cidx;
2585 /* Update our consumer index */
2586 /* XXX NB: shurd - check if this is still safe */
2587 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2588 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2589 rxq->ifr_cq_gen = 0;
2591 /* was this only a completion queue message? */
2592 if (__predict_false(ri.iri_nfrags == 0))
2595 MPASS(ri.iri_nfrags != 0);
2596 MPASS(ri.iri_len != 0);
2598 /* will advance the cidx on the corresponding free lists */
2599 m = iflib_rxd_pkt_get(rxq, &ri);
2600 if (avail == 0 && budget_left)
2601 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2603 if (__predict_false(m == NULL)) {
2604 DBG_COUNTER_INC(rx_mbuf_null);
2607 /* imm_pkt: -- cxgb */
2615 /* make sure that we can refill faster than drain */
2616 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2617 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2619 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2621 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2623 while (mh != NULL) {
2626 m->m_nextpkt = NULL;
2627 #ifndef __NO_STRICT_ALIGNMENT
2628 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2631 rx_bytes += m->m_pkthdr.len;
2633 #if defined(INET6) || defined(INET)
2635 if (!lro_possible) {
2636 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2637 if (lro_possible && mf != NULL) {
2638 ifp->if_input(ifp, mf);
2639 DBG_COUNTER_INC(rx_if_input);
2643 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2644 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2645 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2651 ifp->if_input(ifp, m);
2652 DBG_COUNTER_INC(rx_if_input);
2663 ifp->if_input(ifp, mf);
2664 DBG_COUNTER_INC(rx_if_input);
2667 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2668 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2671 * Flush any outstanding LRO work
2673 #if defined(INET6) || defined(INET)
2674 tcp_lro_flush_all(&rxq->ifr_lc);
2678 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2681 ctx->ifc_flags |= IFC_DO_RESET;
2682 iflib_admin_intr_deferred(ctx);
2687 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2688 static inline qidx_t
2689 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2691 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2692 qidx_t minthresh = txq->ift_size / 8;
2693 if (in_use > 4*minthresh)
2694 return (notify_count);
2695 if (in_use > 2*minthresh)
2696 return (notify_count >> 1);
2697 if (in_use > minthresh)
2698 return (notify_count >> 3);
2702 static inline qidx_t
2703 txq_max_rs_deferred(iflib_txq_t txq)
2705 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2706 qidx_t minthresh = txq->ift_size / 8;
2707 if (txq->ift_in_use > 4*minthresh)
2708 return (notify_count);
2709 if (txq->ift_in_use > 2*minthresh)
2710 return (notify_count >> 1);
2711 if (txq->ift_in_use > minthresh)
2712 return (notify_count >> 2);
2716 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2717 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2719 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2720 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2721 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2723 /* forward compatibility for cxgb */
2724 #define FIRST_QSET(ctx) 0
2725 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2726 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2727 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2728 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2730 /* XXX we should be setting this to something other than zero */
2731 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2732 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2735 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2741 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2742 if (ring || txq->ift_db_pending >= max) {
2743 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2744 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2745 txq->ift_db_pending = txq->ift_npending = 0;
2753 print_pkt(if_pkt_info_t pi)
2755 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2756 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2757 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2758 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2759 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2760 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2764 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2765 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2768 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2770 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2771 struct ether_vlan_header *eh;
2775 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2776 M_WRITABLE(m) == 0) {
2777 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2786 * Determine where frame payload starts.
2787 * Jump over vlan headers if already present,
2788 * helpful for QinQ too.
2790 if (__predict_false(m->m_len < sizeof(*eh))) {
2792 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2795 eh = mtod(m, struct ether_vlan_header *);
2796 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2797 pi->ipi_etype = ntohs(eh->evl_proto);
2798 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2800 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2801 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2804 switch (pi->ipi_etype) {
2808 struct ip *ip = NULL;
2809 struct tcphdr *th = NULL;
2812 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2813 if (__predict_false(m->m_len < minthlen)) {
2815 * if this code bloat is causing too much of a hit
2816 * move it to a separate function and mark it noinline
2818 if (m->m_len == pi->ipi_ehdrlen) {
2821 if (n->m_len >= sizeof(*ip)) {
2822 ip = (struct ip *)n->m_data;
2823 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2824 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2827 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2829 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2833 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2835 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2836 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2837 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2840 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2841 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2842 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2844 pi->ipi_ip_hlen = ip->ip_hl << 2;
2845 pi->ipi_ipproto = ip->ip_p;
2846 pi->ipi_flags |= IPI_TX_IPV4;
2848 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2852 if (pi->ipi_ipproto == IPPROTO_TCP) {
2853 if (__predict_false(th == NULL)) {
2855 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2857 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2859 pi->ipi_tcp_hflags = th->th_flags;
2860 pi->ipi_tcp_hlen = th->th_off << 2;
2861 pi->ipi_tcp_seq = th->th_seq;
2863 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2865 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2866 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2867 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2868 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2870 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2877 case ETHERTYPE_IPV6:
2879 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2881 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2883 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2884 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2887 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2889 /* XXX-BZ this will go badly in case of ext hdrs. */
2890 pi->ipi_ipproto = ip6->ip6_nxt;
2891 pi->ipi_flags |= IPI_TX_IPV6;
2894 if (pi->ipi_ipproto == IPPROTO_TCP) {
2895 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2896 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2899 pi->ipi_tcp_hflags = th->th_flags;
2900 pi->ipi_tcp_hlen = th->th_off << 2;
2903 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2906 * The corresponding flag is set by the stack in the IPv4
2907 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2908 * So, set it here because the rest of the flow requires it.
2910 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2911 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2912 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2918 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2919 pi->ipi_ip_hlen = 0;
2927 static __noinline struct mbuf *
2928 collapse_pkthdr(struct mbuf *m0)
2930 struct mbuf *m, *m_next, *tmp;
2934 while (m_next != NULL && m_next->m_len == 0) {
2938 m_next = m_next->m_next;
2942 if ((m_next->m_flags & M_EXT) == 0) {
2943 m = m_defrag(m, M_NOWAIT);
2945 tmp = m_next->m_next;
2946 memcpy(m_next, m, MPKTHSIZE);
2954 * If dodgy hardware rejects the scatter gather chain we've handed it
2955 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2958 static __noinline struct mbuf *
2959 iflib_remove_mbuf(iflib_txq_t txq)
2962 struct mbuf *m, *mh, **ifsd_m;
2964 pidx = txq->ift_pidx;
2965 ifsd_m = txq->ift_sds.ifsd_m;
2966 ntxd = txq->ift_size;
2967 mh = m = ifsd_m[pidx];
2968 ifsd_m[pidx] = NULL;
2970 txq->ift_dequeued++;
2975 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2977 txq->ift_dequeued++;
2986 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2987 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2988 int max_segs, int flags)
2991 if_shared_ctx_t sctx;
2992 if_softc_ctx_t scctx;
2993 int i, next, pidx, err, ntxd, count;
2994 struct mbuf *m, *tmp, **ifsd_m;
2999 * Please don't ever do this
3001 if (__predict_false(m->m_len == 0))
3002 *m0 = m = collapse_pkthdr(m);
3005 sctx = ctx->ifc_sctx;
3006 scctx = &ctx->ifc_softc_ctx;
3007 ifsd_m = txq->ift_sds.ifsd_m;
3008 ntxd = txq->ift_size;
3009 pidx = txq->ift_pidx;
3011 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3013 err = bus_dmamap_load_mbuf_sg(tag, map,
3014 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3017 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3021 if (__predict_false(m->m_len <= 0)) {
3030 } while (m != NULL);
3031 if (count > *nsegs) {
3033 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3039 next = (pidx + count) & (ntxd-1);
3040 MPASS(ifsd_m[next] == NULL);
3045 } while (m != NULL);
3047 int buflen, sgsize, maxsegsz, max_sgsize;
3053 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3054 maxsegsz = scctx->isc_tx_tso_segsize_max;
3056 maxsegsz = sctx->isc_tx_maxsegsize;
3059 if (__predict_false(m->m_len <= 0)) {
3067 vaddr = (vm_offset_t)m->m_data;
3069 * see if we can't be smarter about physically
3070 * contiguous mappings
3072 next = (pidx + count) & (ntxd-1);
3073 MPASS(ifsd_m[next] == NULL);
3075 txq->ift_enqueued++;
3078 while (buflen > 0) {
3081 max_sgsize = MIN(buflen, maxsegsz);
3082 curaddr = pmap_kextract(vaddr);
3083 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3084 sgsize = MIN(sgsize, max_sgsize);
3085 segs[i].ds_addr = curaddr;
3086 segs[i].ds_len = sgsize;
3094 } while (m != NULL);
3099 *m0 = iflib_remove_mbuf(txq);
3103 static inline caddr_t
3104 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3108 caddr_t start, end, cur, next;
3110 ntxd = txq->ift_size;
3111 size = txq->ift_txd_size[qid];
3112 start = txq->ift_ifdi[qid].idi_vaddr;
3114 if (__predict_false(size == 0))
3116 cur = start + size*cidx;
3117 end = start + size*ntxd;
3118 next = CACHE_PTR_NEXT(cur);
3119 return (next < end ? next : start);
3123 * Pad an mbuf to ensure a minimum ethernet frame size.
3124 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3126 static __noinline int
3127 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3130 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3131 * and ARP message is the smallest common payload I can think of
3133 static char pad[18]; /* just zeros */
3135 struct mbuf *new_head;
3137 if (!M_WRITABLE(*m_head)) {
3138 new_head = m_dup(*m_head, M_NOWAIT);
3139 if (new_head == NULL) {
3141 device_printf(dev, "cannot pad short frame, m_dup() failed");
3142 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3149 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3150 n > 0; n -= sizeof(pad))
3151 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3156 device_printf(dev, "cannot pad short frame\n");
3157 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3165 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3168 if_shared_ctx_t sctx;
3169 if_softc_ctx_t scctx;
3170 bus_dma_segment_t *segs;
3171 struct mbuf *m_head;
3174 struct if_pkt_info pi;
3176 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3177 bus_dma_tag_t desc_tag;
3179 segs = txq->ift_segs;
3181 sctx = ctx->ifc_sctx;
3182 scctx = &ctx->ifc_softc_ctx;
3183 segs = txq->ift_segs;
3184 ntxd = txq->ift_size;
3189 * If we're doing TSO the next descriptor to clean may be quite far ahead
3191 cidx = txq->ift_cidx;
3192 pidx = txq->ift_pidx;
3193 if (ctx->ifc_flags & IFC_PREFETCH) {
3194 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3195 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3196 next_txd = calc_next_txd(txq, cidx, 0);
3200 /* prefetch the next cache line of mbuf pointers and flags */
3201 prefetch(&txq->ift_sds.ifsd_m[next]);
3202 if (txq->ift_sds.ifsd_map != NULL) {
3203 prefetch(&txq->ift_sds.ifsd_map[next]);
3204 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3205 prefetch(&txq->ift_sds.ifsd_flags[next]);
3207 } else if (txq->ift_sds.ifsd_map != NULL)
3208 map = txq->ift_sds.ifsd_map[pidx];
3210 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3211 desc_tag = txq->ift_tso_desc_tag;
3212 max_segs = scctx->isc_tx_tso_segments_max;
3214 desc_tag = txq->ift_desc_tag;
3215 max_segs = scctx->isc_tx_nsegments;
3217 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3218 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3219 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3226 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3228 pi.ipi_qsidx = txq->ift_id;
3229 pi.ipi_len = m_head->m_pkthdr.len;
3230 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3231 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3233 /* deliberate bitwise OR to make one condition */
3234 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3235 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3241 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3243 if (__predict_false(err)) {
3246 /* try collapse once and defrag once */
3248 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3249 /* try defrag if collapsing fails */
3254 m_head = m_defrag(*m_headp, M_NOWAIT);
3256 if (__predict_false(m_head == NULL))
3258 txq->ift_mbuf_defrag++;
3263 txq->ift_no_tx_dma_setup++;
3266 txq->ift_no_tx_dma_setup++;
3268 DBG_COUNTER_INC(tx_frees);
3272 txq->ift_map_failed++;
3273 DBG_COUNTER_INC(encap_load_mbuf_fail);
3278 * XXX assumes a 1 to 1 relationship between segments and
3279 * descriptors - this does not hold true on all drivers, e.g.
3282 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3283 txq->ift_no_desc_avail++;
3285 bus_dmamap_unload(desc_tag, map);
3286 DBG_COUNTER_INC(encap_txq_avail_fail);
3287 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3288 GROUPTASK_ENQUEUE(&txq->ift_task);
3292 * On Intel cards we can greatly reduce the number of TX interrupts
3293 * we see by only setting report status on every Nth descriptor.
3294 * However, this also means that the driver will need to keep track
3295 * of the descriptors that RS was set on to check them for the DD bit.
3297 txq->ift_rs_pending += nsegs + 1;
3298 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3299 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3300 pi.ipi_flags |= IPI_TX_INTR;
3301 txq->ift_rs_pending = 0;
3305 pi.ipi_nsegs = nsegs;
3307 MPASS(pidx >= 0 && pidx < txq->ift_size);
3312 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3313 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3315 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3317 DBG_COUNTER_INC(tx_encap);
3318 MPASS(pi.ipi_new_pidx < txq->ift_size);
3320 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3321 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3322 ndesc += txq->ift_size;
3326 * drivers can need as many as
3329 MPASS(ndesc <= pi.ipi_nsegs + 2);
3330 MPASS(pi.ipi_new_pidx != pidx);
3332 txq->ift_in_use += ndesc;
3335 * We update the last software descriptor again here because there may
3336 * be a sentinel and/or there may be more mbufs than segments
3338 txq->ift_pidx = pi.ipi_new_pidx;
3339 txq->ift_npending += pi.ipi_ndescs;
3341 *m_headp = m_head = iflib_remove_mbuf(txq);
3343 txq->ift_txd_encap_efbig++;
3349 DBG_COUNTER_INC(encap_txd_encap_fail);
3355 txq->ift_mbuf_defrag_failed++;
3356 txq->ift_map_failed++;
3358 DBG_COUNTER_INC(tx_frees);
3364 iflib_tx_desc_free(iflib_txq_t txq, int n)
3367 uint32_t qsize, cidx, mask, gen;
3368 struct mbuf *m, **ifsd_m;
3369 uint8_t *ifsd_flags;
3370 bus_dmamap_t *ifsd_map;
3373 cidx = txq->ift_cidx;
3375 qsize = txq->ift_size;
3377 hasmap = txq->ift_sds.ifsd_map != NULL;
3378 ifsd_flags = txq->ift_sds.ifsd_flags;
3379 ifsd_m = txq->ift_sds.ifsd_m;
3380 ifsd_map = txq->ift_sds.ifsd_map;
3381 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3385 prefetch(ifsd_m[(cidx + 3) & mask]);
3386 prefetch(ifsd_m[(cidx + 4) & mask]);
3388 if (ifsd_m[cidx] != NULL) {
3389 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3390 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3391 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3393 * does it matter if it's not the TSO tag? If so we'll
3394 * have to add the type to flags
3396 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3397 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3399 if ((m = ifsd_m[cidx]) != NULL) {
3400 /* XXX we don't support any drivers that batch packets yet */
3401 MPASS(m->m_nextpkt == NULL);
3402 /* if the number of clusters exceeds the number of segments
3403 * there won't be space on the ring to save a pointer to each
3404 * cluster so we simply free the list here
3406 if (m->m_flags & M_TOOBIG) {
3411 ifsd_m[cidx] = NULL;
3413 txq->ift_dequeued++;
3415 DBG_COUNTER_INC(tx_frees);
3418 if (__predict_false(++cidx == qsize)) {
3423 txq->ift_cidx = cidx;
3428 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3431 if_ctx_t ctx = txq->ift_ctx;
3433 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3434 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3437 * Need a rate-limiting check so that this isn't called every time
3439 iflib_tx_credits_update(ctx, txq);
3440 reclaim = DESC_RECLAIMABLE(txq);
3442 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3444 if (iflib_verbose_debug) {
3445 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3446 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3453 iflib_tx_desc_free(txq, reclaim);
3454 txq->ift_cleaned += reclaim;
3455 txq->ift_in_use -= reclaim;
3460 static struct mbuf **
3461 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3464 struct mbuf **items;
3467 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3468 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3470 prefetch(items[(cidx + offset) & (size-1)]);
3471 if (remaining > 1) {
3472 prefetch2cachelines(&items[next]);
3473 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3474 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3475 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3477 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3481 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3484 ifmp_ring_check_drainage(txq->ift_br, budget);
3488 iflib_txq_can_drain(struct ifmp_ring *r)
3490 iflib_txq_t txq = r->cookie;
3491 if_ctx_t ctx = txq->ift_ctx;
3493 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3494 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3498 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3500 iflib_txq_t txq = r->cookie;
3501 if_ctx_t ctx = txq->ift_ctx;
3502 struct ifnet *ifp = ctx->ifc_ifp;
3503 struct mbuf **mp, *m;
3504 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3505 int reclaimed, err, in_use_prev, desc_used;
3506 bool do_prefetch, ring, rang;
3508 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3509 !LINK_ACTIVE(ctx))) {
3510 DBG_COUNTER_INC(txq_drain_notready);
3513 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3514 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3515 avail = IDXDIFF(pidx, cidx, r->size);
3516 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3517 DBG_COUNTER_INC(txq_drain_flushing);
3518 for (i = 0; i < avail; i++) {
3519 m_free(r->items[(cidx + i) & (r->size-1)]);
3520 r->items[(cidx + i) & (r->size-1)] = NULL;
3525 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3526 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3528 callout_stop(&txq->ift_timer);
3529 CALLOUT_UNLOCK(txq);
3530 DBG_COUNTER_INC(txq_drain_oactive);
3534 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3535 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3536 count = MIN(avail, TX_BATCH_SIZE);
3538 if (iflib_verbose_debug)
3539 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3540 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3542 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3543 avail = TXQ_AVAIL(txq);
3544 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3545 int pidx_prev, rem = do_prefetch ? count - i : 0;
3547 mp = _ring_peek_one(r, cidx, i, rem);
3548 MPASS(mp != NULL && *mp != NULL);
3549 if (__predict_false(*mp == (struct mbuf *)txq)) {
3554 in_use_prev = txq->ift_in_use;
3555 pidx_prev = txq->ift_pidx;
3556 err = iflib_encap(txq, mp);
3557 if (__predict_false(err)) {
3558 DBG_COUNTER_INC(txq_drain_encapfail);
3559 /* no room - bail out */
3563 DBG_COUNTER_INC(txq_drain_encapfail);
3564 /* we can't send this packet - skip it */
3570 DBG_COUNTER_INC(tx_sent);
3571 bytes_sent += m->m_pkthdr.len;
3572 mcast_sent += !!(m->m_flags & M_MCAST);
3573 avail = TXQ_AVAIL(txq);
3575 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3576 desc_used += (txq->ift_in_use - in_use_prev);
3577 ETHER_BPF_MTAP(ifp, m);
3578 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3580 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3583 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3584 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3585 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3586 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3587 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3589 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3591 if (iflib_verbose_debug)
3592 printf("consumed=%d\n", consumed);
3598 iflib_txq_drain_always(struct ifmp_ring *r)
3604 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3612 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3614 callout_stop(&txq->ift_timer);
3615 CALLOUT_UNLOCK(txq);
3617 avail = IDXDIFF(pidx, cidx, r->size);
3618 for (i = 0; i < avail; i++) {
3619 mp = _ring_peek_one(r, cidx, i, avail - i);
3620 if (__predict_false(*mp == (struct mbuf *)txq))
3624 MPASS(ifmp_ring_is_stalled(r) == 0);
3629 iflib_ifmp_purge(iflib_txq_t txq)
3631 struct ifmp_ring *r;
3634 r->drain = iflib_txq_drain_free;
3635 r->can_drain = iflib_txq_drain_always;
3637 ifmp_ring_check_drainage(r, r->size);
3639 r->drain = iflib_txq_drain;
3640 r->can_drain = iflib_txq_can_drain;
3644 _task_fn_tx(void *context)
3646 iflib_txq_t txq = context;
3647 if_ctx_t ctx = txq->ift_ctx;
3648 struct ifnet *ifp = ctx->ifc_ifp;
3651 #ifdef IFLIB_DIAGNOSTICS
3652 txq->ift_cpu_exec_count[curcpu]++;
3654 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3656 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3657 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3658 netmap_tx_irq(ifp, txq->ift_id);
3659 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3662 if (txq->ift_db_pending)
3663 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3664 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3665 if (ctx->ifc_flags & IFC_LEGACY)
3666 IFDI_INTR_ENABLE(ctx);
3668 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3669 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3674 _task_fn_rx(void *context)
3676 iflib_rxq_t rxq = context;
3677 if_ctx_t ctx = rxq->ifr_ctx;
3682 #ifdef IFLIB_DIAGNOSTICS
3683 rxq->ifr_cpu_exec_count[curcpu]++;
3685 DBG_COUNTER_INC(task_fn_rxs);
3686 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3690 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3692 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3697 budget = ctx->ifc_sysctl_rx_budget;
3699 budget = 16; /* XXX */
3700 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3701 if (ctx->ifc_flags & IFC_LEGACY)
3702 IFDI_INTR_ENABLE(ctx);
3704 DBG_COUNTER_INC(rx_intr_enables);
3705 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3706 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3709 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3712 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3716 _task_fn_admin(void *context)
3718 if_ctx_t ctx = context;
3719 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3722 bool oactive, running, do_reset, do_watchdog;
3725 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3726 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3727 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3728 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3729 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3732 if (!running & !oactive)
3736 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3738 callout_stop(&txq->ift_timer);
3739 CALLOUT_UNLOCK(txq);
3742 ctx->ifc_watchdog_events++;
3743 IFDI_WATCHDOG_RESET(ctx);
3745 IFDI_UPDATE_ADMIN_STATUS(ctx);
3746 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3747 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3748 IFDI_LINK_INTR_ENABLE(ctx);
3750 iflib_if_init_locked(ctx);
3753 if (LINK_ACTIVE(ctx) == 0)
3755 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3756 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3761 _task_fn_iov(void *context)
3763 if_ctx_t ctx = context;
3765 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3769 IFDI_VFLR_HANDLE(ctx);
3774 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3777 if_int_delay_info_t info;
3780 info = (if_int_delay_info_t)arg1;
3781 ctx = info->iidi_ctx;
3782 info->iidi_req = req;
3783 info->iidi_oidp = oidp;
3785 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3790 /*********************************************************************
3794 **********************************************************************/
3797 iflib_if_init_locked(if_ctx_t ctx)
3800 iflib_init_locked(ctx);
3805 iflib_if_init(void *arg)
3810 iflib_if_init_locked(ctx);
3815 iflib_if_transmit(if_t ifp, struct mbuf *m)
3817 if_ctx_t ctx = if_getsoftc(ifp);
3822 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3823 DBG_COUNTER_INC(tx_frees);
3828 MPASS(m->m_nextpkt == NULL);
3830 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3831 qidx = QIDX(ctx, m);
3833 * XXX calculate buf_ring based on flowid (divvy up bits?)
3835 txq = &ctx->ifc_txqs[qidx];
3837 #ifdef DRIVER_BACKPRESSURE
3838 if (txq->ift_closed) {
3840 next = m->m_nextpkt;
3841 m->m_nextpkt = NULL;
3854 next = next->m_nextpkt;
3855 } while (next != NULL);
3857 if (count > nitems(marr))
3858 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3859 /* XXX check nextpkt */
3861 /* XXX simplify for now */
3862 DBG_COUNTER_INC(tx_frees);
3865 for (next = m, i = 0; next != NULL; i++) {
3867 next = next->m_nextpkt;
3868 mp[i]->m_nextpkt = NULL;
3871 DBG_COUNTER_INC(tx_seen);
3872 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3874 GROUPTASK_ENQUEUE(&txq->ift_task);
3876 /* support forthcoming later */
3877 #ifdef DRIVER_BACKPRESSURE
3878 txq->ift_closed = TRUE;
3880 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3888 iflib_if_qflush(if_t ifp)
3890 if_ctx_t ctx = if_getsoftc(ifp);
3891 iflib_txq_t txq = ctx->ifc_txqs;
3895 ctx->ifc_flags |= IFC_QFLUSH;
3897 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3898 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3899 iflib_txq_check_drain(txq, 0);
3901 ctx->ifc_flags &= ~IFC_QFLUSH;
3908 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3909 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3910 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3913 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3915 if_ctx_t ctx = if_getsoftc(ifp);
3916 struct ifreq *ifr = (struct ifreq *)data;
3917 #if defined(INET) || defined(INET6)
3918 struct ifaddr *ifa = (struct ifaddr *)data;
3920 bool avoid_reset = FALSE;
3921 int err = 0, reinit = 0, bits;
3926 if (ifa->ifa_addr->sa_family == AF_INET)
3930 if (ifa->ifa_addr->sa_family == AF_INET6)
3934 ** Calling init results in link renegotiation,
3935 ** so we avoid doing it when possible.
3938 if_setflagbits(ifp, IFF_UP,0);
3939 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3942 if (!(if_getflags(ifp) & IFF_NOARP))
3943 arp_ifinit(ifp, ifa);
3946 err = ether_ioctl(ifp, command, data);
3950 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3954 bits = if_getdrvflags(ifp);
3955 /* stop the driver and free any clusters before proceeding */
3958 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3960 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3961 ctx->ifc_flags |= IFC_MULTISEG;
3963 ctx->ifc_flags &= ~IFC_MULTISEG;
3965 err = if_setmtu(ifp, ifr->ifr_mtu);
3967 iflib_init_locked(ctx);
3969 if_setdrvflags(ifp, bits);
3975 if (if_getflags(ifp) & IFF_UP) {
3976 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3977 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3978 (IFF_PROMISC | IFF_ALLMULTI)) {
3979 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3983 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3986 ctx->ifc_if_flags = if_getflags(ifp);
3991 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3993 IFDI_INTR_DISABLE(ctx);
3994 IFDI_MULTI_SET(ctx);
3995 IFDI_INTR_ENABLE(ctx);
4001 IFDI_MEDIA_SET(ctx);
4006 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4010 struct ifi2creq i2c;
4012 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4015 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4019 if (i2c.len > sizeof(i2c.data)) {
4024 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4025 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4033 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4036 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4038 setmask |= (mask & IFCAP_FLAGS);
4040 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4041 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4042 if ((mask & IFCAP_WOL) &&
4043 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4044 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4047 * want to ensure that traffic has stopped before we change any of the flags
4051 bits = if_getdrvflags(ifp);
4052 if (bits & IFF_DRV_RUNNING)
4055 if_togglecapenable(ifp, setmask);
4057 if (bits & IFF_DRV_RUNNING)
4058 iflib_init_locked(ctx);
4060 if_setdrvflags(ifp, bits);
4066 case SIOCGPRIVATE_0:
4070 err = IFDI_PRIV_IOCTL(ctx, command, data);
4074 err = ether_ioctl(ifp, command, data);
4083 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4085 if_ctx_t ctx = if_getsoftc(ifp);
4087 return (IFDI_GET_COUNTER(ctx, cnt));
4090 /*********************************************************************
4092 * OTHER FUNCTIONS EXPORTED TO THE STACK
4094 **********************************************************************/
4097 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4099 if_ctx_t ctx = if_getsoftc(ifp);
4101 if ((void *)ctx != arg)
4104 if ((vtag == 0) || (vtag > 4095))
4108 IFDI_VLAN_REGISTER(ctx, vtag);
4109 /* Re-init to load the changes */
4110 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4111 iflib_if_init_locked(ctx);
4116 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4118 if_ctx_t ctx = if_getsoftc(ifp);
4120 if ((void *)ctx != arg)
4123 if ((vtag == 0) || (vtag > 4095))
4127 IFDI_VLAN_UNREGISTER(ctx, vtag);
4128 /* Re-init to load the changes */
4129 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4130 iflib_if_init_locked(ctx);
4135 iflib_led_func(void *arg, int onoff)
4140 IFDI_LED_FUNC(ctx, onoff);
4144 /*********************************************************************
4146 * BUS FUNCTION DEFINITIONS
4148 **********************************************************************/
4151 iflib_device_probe(device_t dev)
4153 pci_vendor_info_t *ent;
4155 uint16_t pci_vendor_id, pci_device_id;
4156 uint16_t pci_subvendor_id, pci_subdevice_id;
4157 uint16_t pci_rev_id;
4158 if_shared_ctx_t sctx;
4160 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4163 pci_vendor_id = pci_get_vendor(dev);
4164 pci_device_id = pci_get_device(dev);
4165 pci_subvendor_id = pci_get_subvendor(dev);
4166 pci_subdevice_id = pci_get_subdevice(dev);
4167 pci_rev_id = pci_get_revid(dev);
4168 if (sctx->isc_parse_devinfo != NULL)
4169 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4171 ent = sctx->isc_vendor_info;
4172 while (ent->pvi_vendor_id != 0) {
4173 if (pci_vendor_id != ent->pvi_vendor_id) {
4177 if ((pci_device_id == ent->pvi_device_id) &&
4178 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4179 (ent->pvi_subvendor_id == 0)) &&
4180 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4181 (ent->pvi_subdevice_id == 0)) &&
4182 ((pci_rev_id == ent->pvi_rev_id) ||
4183 (ent->pvi_rev_id == 0))) {
4185 device_set_desc_copy(dev, ent->pvi_name);
4186 /* this needs to be changed to zero if the bus probing code
4187 * ever stops re-probing on best match because the sctx
4188 * may have its values over written by register calls
4189 * in subsequent probes
4191 return (BUS_PROBE_DEFAULT);
4199 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4201 int err, rid, msix, msix_bar;
4204 if_softc_ctx_t scctx;
4210 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4213 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4214 device_set_softc(dev, ctx);
4215 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4218 ctx->ifc_sctx = sctx;
4220 ctx->ifc_softc = sc;
4222 if ((err = iflib_register(ctx)) != 0) {
4223 device_printf(dev, "iflib_register failed %d\n", err);
4226 iflib_add_device_sysctl_pre(ctx);
4228 scctx = &ctx->ifc_softc_ctx;
4230 ctx->ifc_nhwtxqs = sctx->isc_ntxqs;
4233 * XXX sanity check that ntxd & nrxd are a power of 2
4235 if (ctx->ifc_sysctl_ntxqs != 0)
4236 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4237 if (ctx->ifc_sysctl_nrxqs != 0)
4238 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4240 for (i = 0; i < sctx->isc_ntxqs; i++) {
4241 if (ctx->ifc_sysctl_ntxds[i] != 0)
4242 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4244 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4247 for (i = 0; i < sctx->isc_nrxqs; i++) {
4248 if (ctx->ifc_sysctl_nrxds[i] != 0)
4249 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4251 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4254 for (i = 0; i < sctx->isc_nrxqs; i++) {
4255 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4256 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4257 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4258 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4260 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4261 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4262 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4263 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4267 for (i = 0; i < sctx->isc_ntxqs; i++) {
4268 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4269 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4270 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4271 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4273 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4274 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4275 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4276 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4281 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4283 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4286 _iflib_pre_assert(scctx);
4287 ctx->ifc_txrx = *scctx->isc_txrx;
4290 MPASS(scctx->isc_capenable);
4291 if (scctx->isc_capenable & IFCAP_TXCSUM)
4292 MPASS(scctx->isc_tx_csum_flags);
4295 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4296 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4298 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4299 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4300 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4301 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4304 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4305 ctx->ifc_flags |= IFC_DMAR;
4306 #elif !(defined(__i386__) || defined(__amd64__))
4307 /* set unconditionally for !x86 */
4308 ctx->ifc_flags |= IFC_DMAR;
4311 msix_bar = scctx->isc_msix_bar;
4312 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4313 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4315 /* XXX change for per-queue sizes */
4316 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4317 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4318 for (i = 0; i < sctx->isc_nrxqs; i++) {
4319 if (!powerof2(scctx->isc_nrxd[i])) {
4320 /* round down instead? */
4321 device_printf(dev, "# rx descriptors must be a power of 2\n");
4326 for (i = 0; i < sctx->isc_ntxqs; i++) {
4327 if (!powerof2(scctx->isc_ntxd[i])) {
4329 "# tx descriptors must be a power of 2");
4335 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4336 MAX_SINGLE_PACKET_FRACTION)
4337 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4338 MAX_SINGLE_PACKET_FRACTION);
4339 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4340 MAX_SINGLE_PACKET_FRACTION)
4341 scctx->isc_tx_tso_segments_max = max(1,
4342 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4345 * Protect the stack against modern hardware
4347 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4348 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4350 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4351 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4352 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4353 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4354 if (scctx->isc_rss_table_size == 0)
4355 scctx->isc_rss_table_size = 64;
4356 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4358 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4359 /* XXX format name */
4360 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4362 /* Set up cpu set. If it fails, use the set of all CPUs. */
4363 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4364 device_printf(dev, "Unable to fetch CPU list\n");
4365 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4367 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4370 ** Now setup MSI or MSI/X, should
4371 ** return us the number of supported
4372 ** vectors. (Will be 1 for MSI)
4374 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4375 msix = scctx->isc_vectors;
4376 } else if (scctx->isc_msix_bar != 0)
4378 * The simple fact that isc_msix_bar is not 0 does not mean we
4379 * we have a good value there that is known to work.
4381 msix = iflib_msix_init(ctx);
4383 scctx->isc_vectors = 1;
4384 scctx->isc_ntxqsets = 1;
4385 scctx->isc_nrxqsets = 1;
4386 scctx->isc_intr = IFLIB_INTR_LEGACY;
4389 /* Get memory for the station queues */
4390 if ((err = iflib_queues_alloc(ctx))) {
4391 device_printf(dev, "Unable to allocate queue memory\n");
4395 if ((err = iflib_qset_structures_setup(ctx))) {
4396 device_printf(dev, "qset structure setup failed %d\n", err);
4401 * Group taskqueues aren't properly set up until SMP is started,
4402 * so we disable interrupts until we can handle them post
4405 * XXX: disabling interrupts doesn't actually work, at least for
4406 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4407 * we do null handling and depend on this not causing too large an
4410 IFDI_INTR_DISABLE(ctx);
4411 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4412 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4413 goto fail_intr_free;
4417 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4421 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4422 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4423 goto fail_intr_free;
4426 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4427 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4428 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4431 if ((err = iflib_netmap_attach(ctx))) {
4432 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4437 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4438 iflib_add_device_sysctl_post(ctx);
4439 ctx->ifc_flags |= IFC_INIT_DONE;
4443 ether_ifdetach(ctx->ifc_ifp);
4445 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4446 pci_release_msi(ctx->ifc_dev);
4448 /* XXX free queues */
4456 iflib_device_attach(device_t dev)
4459 if_shared_ctx_t sctx;
4461 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4464 pci_enable_busmaster(dev);
4466 return (iflib_device_register(dev, NULL, sctx, &ctx));
4470 iflib_device_deregister(if_ctx_t ctx)
4472 if_t ifp = ctx->ifc_ifp;
4475 device_t dev = ctx->ifc_dev;
4477 struct taskqgroup *tqg;
4480 /* Make sure VLANS are not using driver */
4481 if (if_vlantrunkinuse(ifp)) {
4482 device_printf(dev,"Vlan in use, detach first\n");
4487 ctx->ifc_in_detach = 1;
4491 /* Unregister VLAN events */
4492 if (ctx->ifc_vlan_attach_event != NULL)
4493 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4494 if (ctx->ifc_vlan_detach_event != NULL)
4495 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4497 iflib_netmap_detach(ifp);
4498 ether_ifdetach(ifp);
4499 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4500 CTX_LOCK_DESTROY(ctx);
4501 if (ctx->ifc_led_dev != NULL)
4502 led_destroy(ctx->ifc_led_dev);
4503 /* XXX drain any dependent tasks */
4504 tqg = qgroup_if_io_tqg;
4505 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4506 callout_drain(&txq->ift_timer);
4507 if (txq->ift_task.gt_uniq != NULL)
4508 taskqgroup_detach(tqg, &txq->ift_task);
4510 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4511 if (rxq->ifr_task.gt_uniq != NULL)
4512 taskqgroup_detach(tqg, &rxq->ifr_task);
4514 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4515 free(fl->ifl_rx_bitmap, M_IFLIB);
4518 tqg = qgroup_if_config_tqg;
4519 if (ctx->ifc_admin_task.gt_uniq != NULL)
4520 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4521 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4522 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4525 device_set_softc(ctx->ifc_dev, NULL);
4526 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4527 pci_release_msi(dev);
4529 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4530 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4532 if (ctx->ifc_msix_mem != NULL) {
4533 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4534 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4535 ctx->ifc_msix_mem = NULL;
4538 bus_generic_detach(dev);
4541 iflib_tx_structures_free(ctx);
4542 iflib_rx_structures_free(ctx);
4543 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4544 free(ctx->ifc_softc, M_IFLIB);
4551 iflib_device_detach(device_t dev)
4553 if_ctx_t ctx = device_get_softc(dev);
4555 return (iflib_device_deregister(ctx));
4559 iflib_device_suspend(device_t dev)
4561 if_ctx_t ctx = device_get_softc(dev);
4567 return bus_generic_suspend(dev);
4570 iflib_device_shutdown(device_t dev)
4572 if_ctx_t ctx = device_get_softc(dev);
4578 return bus_generic_suspend(dev);
4583 iflib_device_resume(device_t dev)
4585 if_ctx_t ctx = device_get_softc(dev);
4586 iflib_txq_t txq = ctx->ifc_txqs;
4590 iflib_init_locked(ctx);
4592 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4593 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4595 return (bus_generic_resume(dev));
4599 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4602 if_ctx_t ctx = device_get_softc(dev);
4605 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4612 iflib_device_iov_uninit(device_t dev)
4614 if_ctx_t ctx = device_get_softc(dev);
4617 IFDI_IOV_UNINIT(ctx);
4622 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4625 if_ctx_t ctx = device_get_softc(dev);
4628 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4634 /*********************************************************************
4636 * MODULE FUNCTION DEFINITIONS
4638 **********************************************************************/
4641 * - Start a fast taskqueue thread for each core
4642 * - Start a taskqueue for control operations
4645 iflib_module_init(void)
4651 iflib_module_event_handler(module_t mod, int what, void *arg)
4657 if ((err = iflib_module_init()) != 0)
4663 return (EOPNOTSUPP);
4669 /*********************************************************************
4671 * PUBLIC FUNCTION DEFINITIONS
4672 * ordered as in iflib.h
4674 **********************************************************************/
4678 _iflib_assert(if_shared_ctx_t sctx)
4680 MPASS(sctx->isc_tx_maxsize);
4681 MPASS(sctx->isc_tx_maxsegsize);
4683 MPASS(sctx->isc_rx_maxsize);
4684 MPASS(sctx->isc_rx_nsegments);
4685 MPASS(sctx->isc_rx_maxsegsize);
4687 MPASS(sctx->isc_nrxd_min[0]);
4688 MPASS(sctx->isc_nrxd_max[0]);
4689 MPASS(sctx->isc_nrxd_default[0]);
4690 MPASS(sctx->isc_ntxd_min[0]);
4691 MPASS(sctx->isc_ntxd_max[0]);
4692 MPASS(sctx->isc_ntxd_default[0]);
4696 _iflib_pre_assert(if_softc_ctx_t scctx)
4699 MPASS(scctx->isc_txrx->ift_txd_encap);
4700 MPASS(scctx->isc_txrx->ift_txd_flush);
4701 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4702 MPASS(scctx->isc_txrx->ift_rxd_available);
4703 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4704 MPASS(scctx->isc_txrx->ift_rxd_refill);
4705 MPASS(scctx->isc_txrx->ift_rxd_flush);
4709 iflib_register(if_ctx_t ctx)
4711 if_shared_ctx_t sctx = ctx->ifc_sctx;
4712 driver_t *driver = sctx->isc_driver;
4713 device_t dev = ctx->ifc_dev;
4716 _iflib_assert(sctx);
4719 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4720 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4722 device_printf(dev, "can not allocate ifnet structure\n");
4727 * Initialize our context's device specific methods
4729 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4730 kobj_class_compile((kobj_class_t) driver);
4733 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4734 if_setsoftc(ifp, ctx);
4735 if_setdev(ifp, dev);
4736 if_setinitfn(ifp, iflib_if_init);
4737 if_setioctlfn(ifp, iflib_if_ioctl);
4738 if_settransmitfn(ifp, iflib_if_transmit);
4739 if_setqflushfn(ifp, iflib_if_qflush);
4740 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4742 ctx->ifc_vlan_attach_event =
4743 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4744 EVENTHANDLER_PRI_FIRST);
4745 ctx->ifc_vlan_detach_event =
4746 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4747 EVENTHANDLER_PRI_FIRST);
4749 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4750 iflib_media_change, iflib_media_status);
4757 iflib_queues_alloc(if_ctx_t ctx)
4759 if_shared_ctx_t sctx = ctx->ifc_sctx;
4760 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4761 device_t dev = ctx->ifc_dev;
4762 int nrxqsets = scctx->isc_nrxqsets;
4763 int ntxqsets = scctx->isc_ntxqsets;
4766 iflib_fl_t fl = NULL;
4767 int i, j, cpu, err, txconf, rxconf;
4768 iflib_dma_info_t ifdip;
4769 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4770 uint32_t *txqsizes = scctx->isc_txqsizes;
4771 uint8_t nrxqs = sctx->isc_nrxqs;
4772 uint8_t ntxqs = sctx->isc_ntxqs;
4773 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4777 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4778 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4780 /* Allocate the TX ring struct memory */
4781 if (!(ctx->ifc_txqs =
4782 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4783 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4784 device_printf(dev, "Unable to allocate TX ring memory\n");
4789 /* Now allocate the RX */
4790 if (!(ctx->ifc_rxqs =
4791 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4792 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4793 device_printf(dev, "Unable to allocate RX ring memory\n");
4798 txq = ctx->ifc_txqs;
4799 rxq = ctx->ifc_rxqs;
4802 * XXX handle allocation failure
4804 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4805 /* Set up some basics */
4807 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4808 device_printf(dev, "failed to allocate iflib_dma_info\n");
4812 txq->ift_ifdi = ifdip;
4813 for (j = 0; j < ntxqs; j++, ifdip++) {
4814 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4815 device_printf(dev, "Unable to allocate Descriptor memory\n");
4819 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4820 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4824 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4825 txq->ift_br_offset = 1;
4827 txq->ift_br_offset = 0;
4830 txq->ift_timer.c_cpu = cpu;
4832 if (iflib_txsd_alloc(txq)) {
4833 device_printf(dev, "Critical Failure setting up TX buffers\n");
4838 /* Initialize the TX lock */
4839 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4840 device_get_nameunit(dev), txq->ift_id);
4841 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4842 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4844 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4845 device_get_nameunit(dev), txq->ift_id);
4847 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4848 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4850 /* XXX free any allocated rings */
4851 device_printf(dev, "Unable to allocate buf_ring\n");
4856 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4857 /* Set up some basics */
4859 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4860 device_printf(dev, "failed to allocate iflib_dma_info\n");
4865 rxq->ifr_ifdi = ifdip;
4866 /* XXX this needs to be changed if #rx queues != #tx queues */
4867 rxq->ifr_ntxqirq = 1;
4868 rxq->ifr_txqid[0] = i;
4869 for (j = 0; j < nrxqs; j++, ifdip++) {
4870 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4871 device_printf(dev, "Unable to allocate Descriptor memory\n");
4875 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4879 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4880 rxq->ifr_fl_offset = 1;
4882 rxq->ifr_fl_offset = 0;
4884 rxq->ifr_nfl = nfree_lists;
4886 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4887 device_printf(dev, "Unable to allocate free list memory\n");
4892 for (j = 0; j < nfree_lists; j++) {
4893 fl[j].ifl_rxq = rxq;
4895 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4896 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4898 /* Allocate receive buffers for the ring*/
4899 if (iflib_rxsd_alloc(rxq)) {
4901 "Critical Failure setting up receive buffers\n");
4906 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4907 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4911 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4912 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4913 for (i = 0; i < ntxqsets; i++) {
4914 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4916 for (j = 0; j < ntxqs; j++, di++) {
4917 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4918 paddrs[i*ntxqs + j] = di->idi_paddr;
4921 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4922 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4923 iflib_tx_structures_free(ctx);
4924 free(vaddrs, M_IFLIB);
4925 free(paddrs, M_IFLIB);
4928 free(vaddrs, M_IFLIB);
4929 free(paddrs, M_IFLIB);
4932 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4933 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4934 for (i = 0; i < nrxqsets; i++) {
4935 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4937 for (j = 0; j < nrxqs; j++, di++) {
4938 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4939 paddrs[i*nrxqs + j] = di->idi_paddr;
4942 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4943 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4944 iflib_tx_structures_free(ctx);
4945 free(vaddrs, M_IFLIB);
4946 free(paddrs, M_IFLIB);
4949 free(vaddrs, M_IFLIB);
4950 free(paddrs, M_IFLIB);
4954 /* XXX handle allocation failure changes */
4958 if (ctx->ifc_rxqs != NULL)
4959 free(ctx->ifc_rxqs, M_IFLIB);
4960 ctx->ifc_rxqs = NULL;
4961 if (ctx->ifc_txqs != NULL)
4962 free(ctx->ifc_txqs, M_IFLIB);
4963 ctx->ifc_txqs = NULL;
4969 iflib_tx_structures_setup(if_ctx_t ctx)
4971 iflib_txq_t txq = ctx->ifc_txqs;
4974 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4975 iflib_txq_setup(txq);
4981 iflib_tx_structures_free(if_ctx_t ctx)
4983 iflib_txq_t txq = ctx->ifc_txqs;
4986 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4987 iflib_txq_destroy(txq);
4988 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4989 iflib_dma_free(&txq->ift_ifdi[j]);
4991 free(ctx->ifc_txqs, M_IFLIB);
4992 ctx->ifc_txqs = NULL;
4993 IFDI_QUEUES_FREE(ctx);
4996 /*********************************************************************
4998 * Initialize all receive rings.
5000 **********************************************************************/
5002 iflib_rx_structures_setup(if_ctx_t ctx)
5004 iflib_rxq_t rxq = ctx->ifc_rxqs;
5006 #if defined(INET6) || defined(INET)
5010 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5011 #if defined(INET6) || defined(INET)
5012 tcp_lro_free(&rxq->ifr_lc);
5013 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5014 TCP_LRO_ENTRIES, min(1024,
5015 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5016 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5019 rxq->ifr_lro_enabled = TRUE;
5021 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5024 #if defined(INET6) || defined(INET)
5027 * Free RX software descriptors allocated so far, we will only handle
5028 * the rings that completed, the failing case will have
5029 * cleaned up for itself. 'q' failed, so its the terminus.
5031 rxq = ctx->ifc_rxqs;
5032 for (i = 0; i < q; ++i, rxq++) {
5033 iflib_rx_sds_free(rxq);
5034 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5040 /*********************************************************************
5042 * Free all receive rings.
5044 **********************************************************************/
5046 iflib_rx_structures_free(if_ctx_t ctx)
5048 iflib_rxq_t rxq = ctx->ifc_rxqs;
5050 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5051 iflib_rx_sds_free(rxq);
5056 iflib_qset_structures_setup(if_ctx_t ctx)
5060 if ((err = iflib_tx_structures_setup(ctx)) != 0)
5063 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
5064 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5065 iflib_tx_structures_free(ctx);
5066 iflib_rx_structures_free(ctx);
5072 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5073 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
5076 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5081 find_nth(if_ctx_t ctx, int qid)
5084 int i, cpuid, eqid, count;
5086 CPU_COPY(&ctx->ifc_cpus, &cpus);
5087 count = CPU_COUNT(&cpus);
5089 /* clear up to the qid'th bit */
5090 for (i = 0; i < eqid; i++) {
5091 cpuid = CPU_FFS(&cpus);
5093 CPU_CLR(cpuid-1, &cpus);
5095 cpuid = CPU_FFS(&cpus);
5101 extern struct cpu_group *cpu_top; /* CPU topology */
5104 find_child_with_core(int cpu, struct cpu_group *grp)
5108 if (grp->cg_children == 0)
5111 MPASS(grp->cg_child);
5112 for (i = 0; i < grp->cg_children; i++) {
5113 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5121 * Find the nth "close" core to the specified core
5122 * "close" is defined as the deepest level that shares
5123 * at least an L2 cache. With threads, this will be
5124 * threads on the same core. If the sahred cache is L3
5125 * or higher, simply returns the same core.
5128 find_close_core(int cpu, int core_offset)
5130 struct cpu_group *grp;
5139 while ((i = find_child_with_core(cpu, grp)) != -1) {
5140 /* If the child only has one cpu, don't descend */
5141 if (grp->cg_child[i].cg_count <= 1)
5143 grp = &grp->cg_child[i];
5146 /* If they don't share at least an L2 cache, use the same CPU */
5147 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5151 CPU_COPY(&grp->cg_mask, &cs);
5153 /* Add the selected CPU offset to core offset. */
5154 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5155 if (fcpu - 1 == cpu)
5157 CPU_CLR(fcpu - 1, &cs);
5163 CPU_COPY(&grp->cg_mask, &cs);
5164 for (i = core_offset % grp->cg_count; i > 0; i--) {
5165 MPASS(CPU_FFS(&cs));
5166 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5168 MPASS(CPU_FFS(&cs));
5169 return CPU_FFS(&cs) - 1;
5173 find_close_core(int cpu, int core_offset __unused)
5180 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5184 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5185 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5186 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5188 case IFLIB_INTR_RXTX:
5189 /* RX queues get the specified core */
5190 return qid / CPU_COUNT(&ctx->ifc_cpus);
5196 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5197 #define find_close_core(cpuid, tid) CPU_FIRST()
5198 #define find_nth(ctx, gid) CPU_FIRST()
5201 /* Just to avoid copy/paste */
5203 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5204 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name)
5209 cpuid = find_nth(ctx, qid);
5210 tid = get_core_offset(ctx, type, qid);
5212 cpuid = find_close_core(cpuid, tid);
5213 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5215 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5219 if (cpuid > ctx->ifc_cpuid_highest)
5220 ctx->ifc_cpuid_highest = cpuid;
5226 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5227 iflib_intr_type_t type, driver_filter_t *filter,
5228 void *filter_arg, int qid, char *name)
5230 struct grouptask *gtask;
5231 struct taskqgroup *tqg;
5232 iflib_filter_info_t info;
5235 driver_filter_t *intr_fast;
5238 info = &ctx->ifc_filter_info;
5242 /* XXX merge tx/rx for netmap? */
5244 q = &ctx->ifc_txqs[qid];
5245 info = &ctx->ifc_txqs[qid].ift_filter_info;
5246 gtask = &ctx->ifc_txqs[qid].ift_task;
5247 tqg = qgroup_if_io_tqg;
5249 intr_fast = iflib_fast_intr;
5250 GROUPTASK_INIT(gtask, 0, fn, q);
5253 q = &ctx->ifc_rxqs[qid];
5254 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5255 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5256 tqg = qgroup_if_io_tqg;
5258 intr_fast = iflib_fast_intr;
5259 GROUPTASK_INIT(gtask, 0, fn, q);
5261 case IFLIB_INTR_RXTX:
5262 q = &ctx->ifc_rxqs[qid];
5263 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5264 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5265 tqg = qgroup_if_io_tqg;
5267 intr_fast = iflib_fast_intr_rxtx;
5268 GROUPTASK_INIT(gtask, 0, fn, q);
5270 case IFLIB_INTR_ADMIN:
5273 info = &ctx->ifc_filter_info;
5274 gtask = &ctx->ifc_admin_task;
5275 tqg = qgroup_if_config_tqg;
5276 fn = _task_fn_admin;
5277 intr_fast = iflib_fast_intr_ctx;
5280 panic("unknown net intr type");
5283 info->ifi_filter = filter;
5284 info->ifi_filter_arg = filter_arg;
5285 info->ifi_task = gtask;
5288 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5290 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5293 if (type == IFLIB_INTR_ADMIN)
5297 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5301 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5308 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name)
5310 struct grouptask *gtask;
5311 struct taskqgroup *tqg;
5319 q = &ctx->ifc_txqs[qid];
5320 gtask = &ctx->ifc_txqs[qid].ift_task;
5321 tqg = qgroup_if_io_tqg;
5324 irq_num = rman_get_start(irq->ii_res);
5327 q = &ctx->ifc_rxqs[qid];
5328 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5329 tqg = qgroup_if_io_tqg;
5332 irq_num = rman_get_start(irq->ii_res);
5334 case IFLIB_INTR_IOV:
5336 gtask = &ctx->ifc_vflr_task;
5337 tqg = qgroup_if_config_tqg;
5341 panic("unknown net intr type");
5343 GROUPTASK_INIT(gtask, 0, fn, q);
5344 if (irq_num != -1) {
5345 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5347 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5350 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5355 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5358 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5361 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5365 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5367 iflib_txq_t txq = ctx->ifc_txqs;
5368 iflib_rxq_t rxq = ctx->ifc_rxqs;
5369 if_irq_t irq = &ctx->ifc_legacy_irq;
5370 iflib_filter_info_t info;
5371 struct grouptask *gtask;
5372 struct taskqgroup *tqg;
5378 q = &ctx->ifc_rxqs[0];
5379 info = &rxq[0].ifr_filter_info;
5380 gtask = &rxq[0].ifr_task;
5381 tqg = qgroup_if_io_tqg;
5382 tqrid = irq->ii_rid = *rid;
5385 ctx->ifc_flags |= IFC_LEGACY;
5386 info->ifi_filter = filter;
5387 info->ifi_filter_arg = filter_arg;
5388 info->ifi_task = gtask;
5389 info->ifi_ctx = ctx;
5391 /* We allocate a single interrupt resource */
5392 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5394 GROUPTASK_INIT(gtask, 0, fn, q);
5395 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5397 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5398 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5403 iflib_led_create(if_ctx_t ctx)
5406 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5407 device_get_nameunit(ctx->ifc_dev));
5411 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5414 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5418 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5421 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5425 iflib_admin_intr_deferred(if_ctx_t ctx)
5428 struct grouptask *gtask;
5430 gtask = &ctx->ifc_admin_task;
5431 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5434 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5438 iflib_iov_intr_deferred(if_ctx_t ctx)
5441 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5445 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5448 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5452 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5456 GROUPTASK_INIT(gtask, 0, fn, ctx);
5457 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5461 iflib_config_gtask_deinit(struct grouptask *gtask)
5464 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5468 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5470 if_t ifp = ctx->ifc_ifp;
5471 iflib_txq_t txq = ctx->ifc_txqs;
5473 if_setbaudrate(ifp, baudrate);
5474 if (baudrate >= IF_Gbps(10)) {
5476 ctx->ifc_flags |= IFC_PREFETCH;
5479 /* If link down, disable watchdog */
5480 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5481 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5482 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5484 ctx->ifc_link_state = link_state;
5485 if_link_state_change(ifp, link_state);
5489 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5493 int credits_pre = txq->ift_cidx_processed;
5496 if (ctx->isc_txd_credits_update == NULL)
5499 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5502 txq->ift_processed += credits;
5503 txq->ift_cidx_processed += credits;
5505 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5506 if (txq->ift_cidx_processed >= txq->ift_size)
5507 txq->ift_cidx_processed -= txq->ift_size;
5512 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5515 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5520 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5521 const char *description, if_int_delay_info_t info,
5522 int offset, int value)
5524 info->iidi_ctx = ctx;
5525 info->iidi_offset = offset;
5526 info->iidi_value = value;
5527 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5528 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5529 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5530 info, 0, iflib_sysctl_int_delay, "I", description);
5534 iflib_ctx_lock_get(if_ctx_t ctx)
5537 return (&ctx->ifc_ctx_sx);
5541 iflib_msix_init(if_ctx_t ctx)
5543 device_t dev = ctx->ifc_dev;
5544 if_shared_ctx_t sctx = ctx->ifc_sctx;
5545 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5546 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5547 int iflib_num_tx_queues, iflib_num_rx_queues;
5548 int err, admincnt, bar;
5550 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5551 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5553 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5555 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5556 admincnt = sctx->isc_admin_intrcnt;
5557 /* Override by global tuneable */
5560 size_t len = sizeof(i);
5561 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0);
5567 device_printf(dev, "unable to read hw.pci.enable_msix.");
5570 /* Override by tuneable */
5571 if (scctx->isc_disable_msix)
5575 ** When used in a virtualized environment
5576 ** PCI BUSMASTER capability may not be set
5577 ** so explicity set it here and rewrite
5578 ** the ENABLE in the MSIX control register
5579 ** at this point to cause the host to
5580 ** successfully initialize us.
5585 pci_enable_busmaster(dev);
5587 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5588 rid += PCIR_MSIX_CTRL;
5589 msix_ctrl = pci_read_config(dev, rid, 2);
5590 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5591 pci_write_config(dev, rid, msix_ctrl, 2);
5593 device_printf(dev, "PCIY_MSIX capability not found; "
5594 "or rid %d == 0.\n", rid);
5600 * bar == -1 => "trust me I know what I'm doing"
5601 * Some drivers are for hardware that is so shoddily
5602 * documented that no one knows which bars are which
5603 * so the developer has to map all bars. This hack
5604 * allows shoddy garbage to use msix in this framework.
5607 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5608 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5609 if (ctx->ifc_msix_mem == NULL) {
5610 /* May not be enabled */
5611 device_printf(dev, "Unable to map MSIX table \n");
5615 /* First try MSI/X */
5616 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5617 device_printf(dev, "System has MSIX disabled \n");
5618 bus_release_resource(dev, SYS_RES_MEMORY,
5619 bar, ctx->ifc_msix_mem);
5620 ctx->ifc_msix_mem = NULL;
5624 /* use only 1 qset in debug mode */
5625 queuemsgs = min(msgs - admincnt, 1);
5627 queuemsgs = msgs - admincnt;
5630 queues = imin(queuemsgs, rss_getnumbuckets());
5634 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5635 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5636 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5638 /* If we're doing RSS, clamp at the number of RSS buckets */
5639 if (queues > rss_getnumbuckets())
5640 queues = rss_getnumbuckets();
5642 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5643 rx_queues = iflib_num_rx_queues;
5647 if (rx_queues > scctx->isc_nrxqsets)
5648 rx_queues = scctx->isc_nrxqsets;
5651 * We want this to be all logical CPUs by default
5653 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5654 tx_queues = iflib_num_tx_queues;
5656 tx_queues = mp_ncpus;
5658 if (tx_queues > scctx->isc_ntxqsets)
5659 tx_queues = scctx->isc_ntxqsets;
5661 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5663 if (tx_queues != rx_queues)
5664 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5665 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5667 tx_queues = min(rx_queues, tx_queues);
5668 rx_queues = min(rx_queues, tx_queues);
5671 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5673 vectors = rx_queues + admincnt;
5674 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5676 "Using MSIX interrupts with %d vectors\n", vectors);
5677 scctx->isc_vectors = vectors;
5678 scctx->isc_nrxqsets = rx_queues;
5679 scctx->isc_ntxqsets = tx_queues;
5680 scctx->isc_intr = IFLIB_INTR_MSIX;
5684 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5687 vectors = pci_msi_count(dev);
5688 scctx->isc_nrxqsets = 1;
5689 scctx->isc_ntxqsets = 1;
5690 scctx->isc_vectors = vectors;
5691 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5692 device_printf(dev,"Using an MSI interrupt\n");
5693 scctx->isc_intr = IFLIB_INTR_MSI;
5695 device_printf(dev,"Using a Legacy interrupt\n");
5696 scctx->isc_intr = IFLIB_INTR_LEGACY;
5702 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5705 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5708 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5710 char *ring_state = "UNKNOWN";
5713 rc = sysctl_wire_old_buffer(req, 0);
5717 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5722 ring_state = ring_states[state[3]];
5724 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5725 state[0], state[1], state[2], ring_state);
5726 rc = sbuf_finish(sb);
5731 enum iflib_ndesc_handler {
5737 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5739 if_ctx_t ctx = (void *)arg1;
5740 enum iflib_ndesc_handler type = arg2;
5741 char buf[256] = {0};
5746 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5750 case IFLIB_NTXD_HANDLER:
5751 ndesc = ctx->ifc_sysctl_ntxds;
5753 nqs = ctx->ifc_sctx->isc_ntxqs;
5755 case IFLIB_NRXD_HANDLER:
5756 ndesc = ctx->ifc_sysctl_nrxds;
5758 nqs = ctx->ifc_sctx->isc_nrxqs;
5764 for (i=0; i<8; i++) {
5769 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5772 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5773 if (rc || req->newptr == NULL)
5776 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5777 i++, p = strsep(&next, " ,")) {
5778 ndesc[i] = strtoul(p, NULL, 10);
5784 #define NAME_BUFLEN 32
5786 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5788 device_t dev = iflib_get_dev(ctx);
5789 struct sysctl_oid_list *child, *oid_list;
5790 struct sysctl_ctx_list *ctx_list;
5791 struct sysctl_oid *node;
5793 ctx_list = device_get_sysctl_ctx(dev);
5794 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5795 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5796 CTLFLAG_RD, NULL, "IFLIB fields");
5797 oid_list = SYSCTL_CHILDREN(node);
5799 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5800 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5803 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5804 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5805 "# of txqs to use, 0 => use default #");
5806 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5807 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5808 "# of rxqs to use, 0 => use default #");
5809 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5810 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5811 "permit #txq != #rxq");
5812 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5813 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5814 "disable MSIX (default 0)");
5815 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
5816 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
5817 "set the rx budget");
5819 /* XXX change for per-queue sizes */
5820 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5821 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5822 mp_ndesc_handler, "A",
5823 "list of # of tx descriptors to use, 0 = use default #");
5824 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5825 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5826 mp_ndesc_handler, "A",
5827 "list of # of rx descriptors to use, 0 = use default #");
5831 iflib_add_device_sysctl_post(if_ctx_t ctx)
5833 if_shared_ctx_t sctx = ctx->ifc_sctx;
5834 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5835 device_t dev = iflib_get_dev(ctx);
5836 struct sysctl_oid_list *child;
5837 struct sysctl_ctx_list *ctx_list;
5842 char namebuf[NAME_BUFLEN];
5844 struct sysctl_oid *queue_node, *fl_node, *node;
5845 struct sysctl_oid_list *queue_list, *fl_list;
5846 ctx_list = device_get_sysctl_ctx(dev);
5848 node = ctx->ifc_sysctl_node;
5849 child = SYSCTL_CHILDREN(node);
5851 if (scctx->isc_ntxqsets > 100)
5853 else if (scctx->isc_ntxqsets > 10)
5857 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5858 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5859 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5860 CTLFLAG_RD, NULL, "Queue Name");
5861 queue_list = SYSCTL_CHILDREN(queue_node);
5863 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5865 &txq->ift_dequeued, "total mbufs freed");
5866 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5868 &txq->ift_enqueued, "total mbufs enqueued");
5870 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5872 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5873 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5875 &txq->ift_pullups, "# of times m_pullup was called");
5876 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5878 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5879 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5881 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5882 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5884 &txq->ift_map_failed, "# of times dma map failed");
5885 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5887 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5888 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5890 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5891 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5893 &txq->ift_pidx, 1, "Producer Index");
5894 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5896 &txq->ift_cidx, 1, "Consumer Index");
5897 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5899 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5900 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5902 &txq->ift_in_use, 1, "descriptors in use");
5903 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5905 &txq->ift_processed, "descriptors procesed for clean");
5906 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5908 &txq->ift_cleaned, "total cleaned");
5909 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5910 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5911 0, mp_ring_state_handler, "A", "soft ring state");
5912 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5913 CTLFLAG_RD, &txq->ift_br->enqueues,
5914 "# of enqueues to the mp_ring for this queue");
5915 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5916 CTLFLAG_RD, &txq->ift_br->drops,
5917 "# of drops in the mp_ring for this queue");
5918 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5919 CTLFLAG_RD, &txq->ift_br->starts,
5920 "# of normal consumer starts in the mp_ring for this queue");
5921 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5922 CTLFLAG_RD, &txq->ift_br->stalls,
5923 "# of consumer stalls in the mp_ring for this queue");
5924 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5925 CTLFLAG_RD, &txq->ift_br->restarts,
5926 "# of consumer restarts in the mp_ring for this queue");
5927 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5928 CTLFLAG_RD, &txq->ift_br->abdications,
5929 "# of consumer abdications in the mp_ring for this queue");
5932 if (scctx->isc_nrxqsets > 100)
5934 else if (scctx->isc_nrxqsets > 10)
5938 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5939 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5940 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5941 CTLFLAG_RD, NULL, "Queue Name");
5942 queue_list = SYSCTL_CHILDREN(queue_node);
5943 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5944 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5946 &rxq->ifr_cq_pidx, 1, "Producer Index");
5947 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5949 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5952 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5953 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5954 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5955 CTLFLAG_RD, NULL, "freelist Name");
5956 fl_list = SYSCTL_CHILDREN(fl_node);
5957 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5959 &fl->ifl_pidx, 1, "Producer Index");
5960 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5962 &fl->ifl_cidx, 1, "Consumer Index");
5963 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5965 &fl->ifl_credits, 1, "credits available");
5967 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5969 &fl->ifl_m_enqueued, "mbufs allocated");
5970 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5972 &fl->ifl_m_dequeued, "mbufs freed");
5973 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5975 &fl->ifl_cl_enqueued, "clusters allocated");
5976 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5978 &fl->ifl_cl_dequeued, "clusters freed");
5986 #ifndef __NO_STRICT_ALIGNMENT
5987 static struct mbuf *
5988 iflib_fixup_rx(struct mbuf *m)
5992 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5993 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5994 m->m_data += ETHER_HDR_LEN;
5997 MGETHDR(n, M_NOWAIT, MT_DATA);
6002 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6003 m->m_data += ETHER_HDR_LEN;
6004 m->m_len -= ETHER_HDR_LEN;
6005 n->m_len = ETHER_HDR_LEN;
6006 M_MOVE_PKTHDR(n, m);