2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/sockio.h>
41 #include <sys/kernel.h>
43 #include <sys/mutex.h>
44 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
57 #include <net/if_var.h>
58 #include <net/if_types.h>
59 #include <net/if_media.h>
61 #include <net/ethernet.h>
62 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet6/ip6_var.h>
76 #include <machine/bus.h>
77 #include <machine/in_cksum.h>
82 #include <dev/led/led.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85 #include <dev/pci/pci_private.h>
87 #include <net/iflib.h>
91 #if defined(__i386__) || defined(__amd64__)
92 #include <sys/memdesc.h>
93 #include <machine/bus.h>
94 #include <machine/md_var.h>
95 #include <machine/specialreg.h>
96 #include <x86/include/busdma_impl.h>
97 #include <x86/iommu/busdma_dmar.h>
100 #include <sys/bitstring.h>
102 * enable accounting of every mbuf as it comes in to and goes out of
103 * iflib's software descriptor references
105 #define MEMORY_LOGGING 0
107 * Enable mbuf vectors for compressing long mbuf chains
112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
113 * we prefetch needs to be determined by the time spent in m_free vis a vis
114 * the cost of a prefetch. This will of course vary based on the workload:
115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
116 * is quite expensive, thus suggesting very little prefetch.
117 * - small packet forwarding which is just returning a single mbuf to
118 * UMA will typically be very fast vis a vis the cost of a memory
125 * - private structures
126 * - iflib private utility functions
128 * - vlan registry and other exported functions
129 * - iflib public core functions
133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
168 uint16_t ifc_nhwtxqs;
169 uint16_t ifc_nhwrxqs;
171 iflib_txq_t ifc_txqs;
172 iflib_rxq_t ifc_rxqs;
173 uint32_t ifc_if_flags;
175 uint32_t ifc_max_fl_buf_size;
180 int ifc_watchdog_events;
181 struct cdev *ifc_led_dev;
182 struct resource *ifc_msix_mem;
184 struct if_irq ifc_legacy_irq;
185 struct grouptask ifc_admin_task;
186 struct grouptask ifc_vflr_task;
187 struct iflib_filter_info ifc_filter_info;
188 struct ifmedia ifc_media;
190 struct sysctl_oid *ifc_sysctl_node;
191 uint16_t ifc_sysctl_ntxqs;
192 uint16_t ifc_sysctl_nrxqs;
193 uint16_t ifc_sysctl_qs_eq_override;
194 uint16_t ifc_sysctl_rx_budget;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 uint8_t ifc_mac[ETHER_ADDR_LEN];
212 char ifc_mtx_name[16];
217 iflib_get_softc(if_ctx_t ctx)
220 return (ctx->ifc_softc);
224 iflib_get_dev(if_ctx_t ctx)
227 return (ctx->ifc_dev);
231 iflib_get_ifp(if_ctx_t ctx)
234 return (ctx->ifc_ifp);
238 iflib_get_media(if_ctx_t ctx)
241 return (&ctx->ifc_media);
245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
252 iflib_get_softc_ctx(if_ctx_t ctx)
255 return (&ctx->ifc_softc_ctx);
259 iflib_get_sctx(if_ctx_t ctx)
262 return (ctx->ifc_sctx);
265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
272 #define RX_SW_DESC_MAP_CREATED (1 << 0)
273 #define TX_SW_DESC_MAP_CREATED (1 << 1)
274 #define RX_SW_DESC_INUSE (1 << 3)
275 #define TX_SW_DESC_MAPPED (1 << 4)
277 #define M_TOOBIG M_PROTO1
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 struct mbuf **ifsd_m; /* pkthdr mbufs */
293 /* magic number that should be high enough for any hardware */
294 #define IFLIB_MAX_TX_SEGS 128
295 /* bnxt supports 64 with hardware LRO enabled */
296 #define IFLIB_MAX_RX_SEGS 64
297 #define IFLIB_RX_COPY_THRESH 128
298 #define IFLIB_MAX_RX_REFRESH 32
299 /* The minimum descriptors per second before we start coalescing */
300 #define IFLIB_MIN_DESC_SEC 16384
301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
302 #define IFLIB_QUEUE_IDLE 0
303 #define IFLIB_QUEUE_HUNG 1
304 #define IFLIB_QUEUE_WORKING 2
305 /* maximum number of txqs that can share an rx interrupt */
306 #define IFLIB_MAX_TX_SHARED_INTR 4
308 /* this should really scale with ring size - this is a fairly arbitrary value */
309 #define TX_BATCH_SIZE 32
311 #define IFLIB_RESTART_BUDGET 8
313 #define IFC_LEGACY 0x001
314 #define IFC_QFLUSH 0x002
315 #define IFC_MULTISEG 0x004
316 #define IFC_DMAR 0x008
317 #define IFC_SC_ALLOCATED 0x010
318 #define IFC_INIT_DONE 0x020
319 #define IFC_PREFETCH 0x040
320 #define IFC_DO_RESET 0x080
321 #define IFC_CHECK_HUNG 0x100
323 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
324 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
325 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
329 qidx_t ift_cidx_processed;
332 uint8_t ift_br_offset;
333 uint16_t ift_npending;
334 uint16_t ift_db_pending;
335 uint16_t ift_rs_pending;
337 uint8_t ift_txd_size[8];
338 uint64_t ift_processed;
339 uint64_t ift_cleaned;
340 uint64_t ift_cleaned_prev;
342 uint64_t ift_enqueued;
343 uint64_t ift_dequeued;
345 uint64_t ift_no_tx_dma_setup;
346 uint64_t ift_no_desc_avail;
347 uint64_t ift_mbuf_defrag_failed;
348 uint64_t ift_mbuf_defrag;
349 uint64_t ift_map_failed;
350 uint64_t ift_txd_encap_efbig;
351 uint64_t ift_pullups;
354 struct mtx ift_db_mtx;
356 /* constant values */
358 struct ifmp_ring *ift_br;
359 struct grouptask ift_task;
362 struct callout ift_timer;
364 if_txsd_vec_t ift_sds;
367 uint8_t ift_update_freq;
368 struct iflib_filter_info ift_filter_info;
369 bus_dma_tag_t ift_desc_tag;
370 bus_dma_tag_t ift_tso_desc_tag;
371 iflib_dma_info_t ift_ifdi;
372 #define MTX_NAME_LEN 16
373 char ift_mtx_name[MTX_NAME_LEN];
374 char ift_db_mtx_name[MTX_NAME_LEN];
375 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
376 #ifdef IFLIB_DIAGNOSTICS
377 uint64_t ift_cpu_exec_count[256];
379 } __aligned(CACHE_LINE_SIZE);
386 uint8_t ifl_rxd_size;
388 uint64_t ifl_m_enqueued;
389 uint64_t ifl_m_dequeued;
390 uint64_t ifl_cl_enqueued;
391 uint64_t ifl_cl_dequeued;
395 bitstr_t *ifl_rx_bitmap;
399 uint16_t ifl_buf_size;
402 iflib_rxsd_array_t ifl_sds;
405 bus_dma_tag_t ifl_desc_tag;
406 iflib_dma_info_t ifl_ifdi;
407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
408 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
409 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
410 } __aligned(CACHE_LINE_SIZE);
413 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
419 else if (pidx < cidx)
420 used = size - cidx + pidx;
421 else if (gen == 0 && pidx == cidx)
423 else if (gen == 1 && pidx == cidx)
431 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
433 #define IDXDIFF(head, tail, wrap) \
434 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
437 /* If there is a separate completion queue -
438 * these are the cq cidx and pidx. Otherwise
445 uint8_t ifr_fl_offset;
451 uint8_t ifr_lro_enabled;
454 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
455 struct lro_ctrl ifr_lc;
456 struct grouptask ifr_task;
457 struct iflib_filter_info ifr_filter_info;
458 iflib_dma_info_t ifr_ifdi;
460 /* dynamically allocate if any drivers need a value substantially larger than this */
461 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
462 #ifdef IFLIB_DIAGNOSTICS
463 uint64_t ifr_cpu_exec_count[256];
465 } __aligned(CACHE_LINE_SIZE);
467 typedef struct if_rxsd {
469 struct mbuf **ifsd_m;
474 /* multiple of word size */
476 #define PKT_INFO_SIZE 6
477 #define RXD_INFO_SIZE 5
478 #define PKT_TYPE uint64_t
480 #define PKT_INFO_SIZE 11
481 #define RXD_INFO_SIZE 8
482 #define PKT_TYPE uint32_t
484 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
485 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
487 typedef struct if_pkt_info_pad {
488 PKT_TYPE pkt_val[PKT_INFO_SIZE];
489 } *if_pkt_info_pad_t;
490 typedef struct if_rxd_info_pad {
491 PKT_TYPE rxd_val[RXD_INFO_SIZE];
492 } *if_rxd_info_pad_t;
494 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
495 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
499 pkt_info_zero(if_pkt_info_t pi)
501 if_pkt_info_pad_t pi_pad;
503 pi_pad = (if_pkt_info_pad_t)pi;
504 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
505 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
507 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
508 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
513 rxd_info_zero(if_rxd_info_t ri)
515 if_rxd_info_pad_t ri_pad;
518 ri_pad = (if_rxd_info_pad_t)ri;
519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
520 ri_pad->rxd_val[i] = 0;
521 ri_pad->rxd_val[i+1] = 0;
522 ri_pad->rxd_val[i+2] = 0;
523 ri_pad->rxd_val[i+3] = 0;
526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
531 * Only allow a single packet to take up most 1/nth of the tx ring
533 #define MAX_SINGLE_PACKET_FRACTION 12
534 #define IF_BAD_DMA (bus_addr_t)-1
536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
538 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
540 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
541 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
542 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
545 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
546 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
549 /* Our boot-time initialization hook */
550 static int iflib_module_event_handler(module_t, int, void *);
552 static moduledata_t iflib_moduledata = {
554 iflib_module_event_handler,
558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
559 MODULE_VERSION(iflib, 1);
561 MODULE_DEPEND(iflib, pci, 1, 1, 1);
562 MODULE_DEPEND(iflib, ether, 1, 1, 1);
564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
567 #ifndef IFLIB_DEBUG_COUNTERS
569 #define IFLIB_DEBUG_COUNTERS 1
571 #define IFLIB_DEBUG_COUNTERS 0
572 #endif /* !INVARIANTS */
575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
576 "iflib driver parameters");
579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
581 static int iflib_min_tx_latency = 0;
582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
584 static int iflib_no_tx_batch = 0;
585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
589 #if IFLIB_DEBUG_COUNTERS
591 static int iflib_tx_seen;
592 static int iflib_tx_sent;
593 static int iflib_tx_encap;
594 static int iflib_rx_allocs;
595 static int iflib_fl_refills;
596 static int iflib_fl_refills_large;
597 static int iflib_tx_frees;
599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
600 &iflib_tx_seen, 0, "# tx mbufs seen");
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
602 &iflib_tx_sent, 0, "# tx mbufs sent");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
604 &iflib_tx_encap, 0, "# tx mbufs encapped");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
606 &iflib_tx_frees, 0, "# tx frees");
607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
608 &iflib_rx_allocs, 0, "# rx allocations");
609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
610 &iflib_fl_refills, 0, "# refills");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
612 &iflib_fl_refills_large, 0, "# large refills");
615 static int iflib_txq_drain_flushing;
616 static int iflib_txq_drain_oactive;
617 static int iflib_txq_drain_notready;
618 static int iflib_txq_drain_encapfail;
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
621 &iflib_txq_drain_flushing, 0, "# drain flushes");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
623 &iflib_txq_drain_oactive, 0, "# drain oactives");
624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
625 &iflib_txq_drain_notready, 0, "# drain notready");
626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
627 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
630 static int iflib_encap_load_mbuf_fail;
631 static int iflib_encap_pad_mbuf_fail;
632 static int iflib_encap_txq_avail_fail;
633 static int iflib_encap_txd_encap_fail;
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
644 static int iflib_task_fn_rxs;
645 static int iflib_rx_intr_enables;
646 static int iflib_fast_intrs;
647 static int iflib_intr_link;
648 static int iflib_intr_msix;
649 static int iflib_rx_unavail;
650 static int iflib_rx_ctx_inactive;
651 static int iflib_rx_zero_len;
652 static int iflib_rx_if_input;
653 static int iflib_rx_mbuf_null;
654 static int iflib_rxd_flush;
656 static int iflib_verbose_debug;
658 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
659 &iflib_intr_link, 0, "# intr link calls");
660 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
661 &iflib_intr_msix, 0, "# intr msix calls");
662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
665 &iflib_rx_intr_enables, 0, "# rx intr enables");
666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
667 &iflib_fast_intrs, 0, "# fast_intr calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
669 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
673 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
675 &iflib_rx_if_input, 0, "# times rxeof called if_input");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
679 &iflib_rxd_flush, 0, "# times rxd_flush called");
680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
681 &iflib_verbose_debug, 0, "enable verbose debugging");
683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
685 iflib_debug_reset(void)
687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
689 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
690 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
694 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
695 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
696 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
700 #define DBG_COUNTER_INC(name)
701 static void iflib_debug_reset(void) {}
706 #define IFLIB_DEBUG 0
708 static void iflib_tx_structures_free(if_ctx_t ctx);
709 static void iflib_rx_structures_free(if_ctx_t ctx);
710 static int iflib_queues_alloc(if_ctx_t ctx);
711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
713 static int iflib_qset_structures_setup(if_ctx_t ctx);
714 static int iflib_msix_init(if_ctx_t ctx);
715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
718 static int iflib_register(if_ctx_t);
719 static void iflib_init_locked(if_ctx_t ctx);
720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
721 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
722 static void iflib_ifmp_purge(iflib_txq_t txq);
723 static void _iflib_pre_assert(if_softc_ctx_t scctx);
724 static void iflib_stop(if_ctx_t ctx);
725 static void iflib_if_init_locked(if_ctx_t ctx);
726 #ifndef __NO_STRICT_ALIGNMENT
727 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
731 #include <sys/selinfo.h>
732 #include <net/netmap.h>
733 #include <dev/netmap/netmap_kern.h>
735 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
740 * device-specific sysctl variables:
742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
743 * During regular operations the CRC is stripped, but on some
744 * hardware reception of frames not multiple of 64 is slower,
745 * so using crcstrip=0 helps in benchmarks.
747 * iflib_rx_miss, iflib_rx_miss_bufs:
748 * count packets that might be missed due to lost interrupts.
750 SYSCTL_DECL(_dev_netmap);
752 * The xl driver by default strips CRCs and we do not override it.
755 int iflib_crcstrip = 1;
756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
759 int iflib_rx_miss, iflib_rx_miss_bufs;
760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
766 * Register/unregister. We are already under netmap lock.
767 * Only called on the first register or the last unregister.
770 iflib_netmap_register(struct netmap_adapter *na, int onoff)
772 struct ifnet *ifp = na->ifp;
773 if_ctx_t ctx = ifp->if_softc;
777 IFDI_INTR_DISABLE(ctx);
779 /* Tell the stack that the interface is no longer active */
780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
785 /* enable or disable flags and callbacks in na and ifp */
787 nm_set_native_flags(na);
789 nm_clear_native_flags(na);
792 iflib_init_locked(ctx);
793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
796 nm_clear_native_flags(na);
802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
804 struct netmap_adapter *na = kring->na;
805 u_int const lim = kring->nkr_num_slots - 1;
806 u_int head = kring->rhead;
807 struct netmap_ring *ring = kring->ring;
809 struct if_rxd_update iru;
810 if_ctx_t ctx = rxq->ifr_ctx;
811 iflib_fl_t fl = &rxq->ifr_fl[0];
812 uint32_t refill_pidx, nic_i;
814 if (nm_i == head && __predict_true(!init))
816 iru_init(&iru, rxq, 0 /* flid */);
817 map = fl->ifl_sds.ifsd_map;
818 refill_pidx = netmap_idx_k2n(kring, nm_i);
820 * IMPORTANT: we must leave one free slot in the ring,
821 * so move head back by one unit
823 head = nm_prev(head, lim);
824 while (nm_i != head) {
825 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
826 struct netmap_slot *slot = &ring->slot[nm_i];
827 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
828 uint32_t nic_i_dma = refill_pidx;
829 nic_i = netmap_idx_k2n(kring, nm_i);
831 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
833 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
834 return netmap_ring_reinit(kring);
836 fl->ifl_vm_addrs[tmp_pidx] = addr;
837 if (__predict_false(init) && map) {
838 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
839 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
840 /* buffer has changed, reload map */
841 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
843 slot->flags &= ~NS_BUF_CHANGED;
845 nm_i = nm_next(nm_i, lim);
846 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
847 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
850 iru.iru_pidx = refill_pidx;
851 iru.iru_count = tmp_pidx+1;
852 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
858 for (int n = 0; n < iru.iru_count; n++) {
859 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
860 BUS_DMASYNC_PREREAD);
861 /* XXX - change this to not use the netmap func*/
862 nic_i_dma = nm_next(nic_i_dma, lim);
866 kring->nr_hwcur = head;
869 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
871 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
876 * Reconcile kernel and user view of the transmit ring.
878 * All information is in the kring.
879 * Userspace wants to send packets up to the one before kring->rhead,
880 * kernel knows kring->nr_hwcur is the first unsent packet.
882 * Here we push packets out (as many as possible), and possibly
883 * reclaim buffers from previously completed transmission.
885 * The caller (netmap) guarantees that there is only one instance
886 * running at any time. Any interference with other driver
887 * methods should be handled by the individual drivers.
890 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
892 struct netmap_adapter *na = kring->na;
893 struct ifnet *ifp = na->ifp;
894 struct netmap_ring *ring = kring->ring;
895 u_int nm_i; /* index into the netmap ring */
896 u_int nic_i; /* index into the NIC ring */
898 u_int const lim = kring->nkr_num_slots - 1;
899 u_int const head = kring->rhead;
900 struct if_pkt_info pi;
903 * interrupts on every tx packet are expensive so request
904 * them every half ring, or where NS_REPORT is set
906 u_int report_frequency = kring->nkr_num_slots >> 1;
907 /* device-specific */
908 if_ctx_t ctx = ifp->if_softc;
909 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
911 if (txq->ift_sds.ifsd_map)
912 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
913 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
917 * First part: process new packets to send.
918 * nm_i is the current index in the netmap ring,
919 * nic_i is the corresponding index in the NIC ring.
921 * If we have packets to send (nm_i != head)
922 * iterate over the netmap ring, fetch length and update
923 * the corresponding slot in the NIC ring. Some drivers also
924 * need to update the buffer's physical address in the NIC slot
925 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
927 * The netmap_reload_map() calls is especially expensive,
928 * even when (as in this case) the tag is 0, so do only
929 * when the buffer has actually changed.
931 * If possible do not set the report/intr bit on all slots,
932 * but only a few times per ring or when NS_REPORT is set.
934 * Finally, on 10G and faster drivers, it might be useful
935 * to prefetch the next slot and txr entry.
938 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
940 pi.ipi_segs = txq->ift_segs;
941 pi.ipi_qsidx = kring->ring_id;
942 if (nm_i != head) { /* we have new packets to send */
943 nic_i = netmap_idx_k2n(kring, nm_i);
945 __builtin_prefetch(&ring->slot[nm_i]);
946 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
947 if (txq->ift_sds.ifsd_map)
948 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
950 for (n = 0; nm_i != head; n++) {
951 struct netmap_slot *slot = &ring->slot[nm_i];
952 u_int len = slot->len;
954 void *addr = PNMB(na, slot, &paddr);
955 int flags = (slot->flags & NS_REPORT ||
956 nic_i == 0 || nic_i == report_frequency) ?
959 /* device-specific */
961 pi.ipi_segs[0].ds_addr = paddr;
962 pi.ipi_segs[0].ds_len = len;
966 pi.ipi_flags = flags;
968 /* Fill the slot in the NIC ring. */
969 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
971 /* prefetch for next round */
972 __builtin_prefetch(&ring->slot[nm_i + 1]);
973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
974 if (txq->ift_sds.ifsd_map) {
975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
977 NM_CHECK_ADDR_LEN(na, addr, len);
979 if (slot->flags & NS_BUF_CHANGED) {
980 /* buffer has changed, reload map */
981 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
983 /* make sure changes to the buffer are synced */
984 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
985 BUS_DMASYNC_PREWRITE);
987 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
988 nm_i = nm_next(nm_i, lim);
989 nic_i = nm_next(nic_i, lim);
991 kring->nr_hwcur = head;
993 /* synchronize the NIC ring */
994 if (txq->ift_sds.ifsd_map)
995 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
998 /* (re)start the tx unit up to slot nic_i (excluded) */
999 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1003 * Second part: reclaim buffers for completed transmissions.
1005 if (iflib_tx_credits_update(ctx, txq)) {
1006 /* some tx completed, increment avail */
1007 nic_i = txq->ift_cidx_processed;
1008 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1014 * Reconcile kernel and user view of the receive ring.
1015 * Same as for the txsync, this routine must be efficient.
1016 * The caller guarantees a single invocations, but races against
1017 * the rest of the driver should be handled here.
1019 * On call, kring->rhead is the first packet that userspace wants
1020 * to keep, and kring->rcur is the wakeup point.
1021 * The kernel has previously reported packets up to kring->rtail.
1023 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1024 * of whether or not we received an interrupt.
1027 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1029 struct netmap_adapter *na = kring->na;
1030 struct netmap_ring *ring = kring->ring;
1031 uint32_t nm_i; /* index into the netmap ring */
1032 uint32_t nic_i; /* index into the NIC ring */
1034 u_int const lim = kring->nkr_num_slots - 1;
1035 u_int const head = netmap_idx_n2k(kring, kring->rhead);
1036 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1037 struct if_rxd_info ri;
1039 struct ifnet *ifp = na->ifp;
1040 if_ctx_t ctx = ifp->if_softc;
1041 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1042 iflib_fl_t fl = rxq->ifr_fl;
1044 return netmap_ring_reinit(kring);
1046 /* XXX check sync modes */
1047 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1048 if (fl->ifl_sds.ifsd_map == NULL)
1050 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1054 * First part: import newly received packets.
1056 * nm_i is the index of the next free slot in the netmap ring,
1057 * nic_i is the index of the next received packet in the NIC ring,
1058 * and they may differ in case if_init() has been called while
1059 * in netmap mode. For the receive ring we have
1061 * nic_i = rxr->next_check;
1062 * nm_i = kring->nr_hwtail (previous)
1064 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1066 * rxr->next_check is set to 0 on a ring reinit
1068 if (netmap_no_pendintr || force_update) {
1069 int crclen = iflib_crcstrip ? 0 : 4;
1072 for (i = 0; i < rxq->ifr_nfl; i++) {
1073 fl = &rxq->ifr_fl[i];
1074 nic_i = fl->ifl_cidx;
1075 nm_i = netmap_idx_n2k(kring, nic_i);
1076 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1077 for (n = 0; avail > 0; n++, avail--) {
1079 ri.iri_frags = rxq->ifr_frags;
1080 ri.iri_qsidx = kring->ring_id;
1081 ri.iri_ifp = ctx->ifc_ifp;
1082 ri.iri_cidx = nic_i;
1084 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1085 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1086 ring->slot[nm_i].flags = 0;
1087 if (fl->ifl_sds.ifsd_map)
1088 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1089 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1090 nm_i = nm_next(nm_i, lim);
1091 nic_i = nm_next(nic_i, lim);
1093 if (n) { /* update the state variables */
1094 if (netmap_no_pendintr && !force_update) {
1097 iflib_rx_miss_bufs += n;
1099 fl->ifl_cidx = nic_i;
1100 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i);
1102 kring->nr_kflags &= ~NKR_PENDINTR;
1106 * Second part: skip past packets that userspace has released.
1107 * (kring->nr_hwcur to head excluded),
1108 * and make the buffers available for reception.
1109 * As usual nm_i is the index in the netmap ring,
1110 * nic_i is the index in the NIC ring, and
1111 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1113 /* XXX not sure how this will work with multiple free lists */
1114 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
1116 return (netmap_fl_refill(rxq, kring, nm_i, false));
1120 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1122 struct ifnet *ifp = na->ifp;
1123 if_ctx_t ctx = ifp->if_softc;
1127 IFDI_INTR_ENABLE(ctx);
1129 IFDI_INTR_DISABLE(ctx);
1136 iflib_netmap_attach(if_ctx_t ctx)
1138 struct netmap_adapter na;
1139 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1141 bzero(&na, sizeof(na));
1143 na.ifp = ctx->ifc_ifp;
1144 na.na_flags = NAF_BDG_MAYSLEEP;
1145 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1146 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1148 na.num_tx_desc = scctx->isc_ntxd[0];
1149 na.num_rx_desc = scctx->isc_nrxd[0];
1150 na.nm_txsync = iflib_netmap_txsync;
1151 na.nm_rxsync = iflib_netmap_rxsync;
1152 na.nm_register = iflib_netmap_register;
1153 na.nm_intr = iflib_netmap_intr;
1154 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1155 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1156 return (netmap_attach(&na));
1160 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1162 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1163 struct netmap_slot *slot;
1165 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1168 if (txq->ift_sds.ifsd_map == NULL)
1171 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1174 * In netmap mode, set the map for the packet buffer.
1175 * NOTE: Some drivers (not this one) also need to set
1176 * the physical buffer address in the NIC ring.
1177 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1178 * netmap slot index, si
1180 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1181 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1186 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1188 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1189 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1190 struct netmap_slot *slot;
1193 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1196 nm_i = netmap_idx_n2k(kring, 0);
1197 netmap_fl_refill(rxq, kring, nm_i, true);
1200 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1203 #define iflib_netmap_txq_init(ctx, txq)
1204 #define iflib_netmap_rxq_init(ctx, rxq)
1205 #define iflib_netmap_detach(ifp)
1207 #define iflib_netmap_attach(ctx) (0)
1208 #define netmap_rx_irq(ifp, qid, budget) (0)
1209 #define netmap_tx_irq(ifp, qid) do {} while (0)
1213 #if defined(__i386__) || defined(__amd64__)
1214 static __inline void
1217 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1219 static __inline void
1220 prefetch2cachelines(void *x)
1222 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1223 #if (CACHE_LINE_SIZE < 128)
1224 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1229 #define prefetch2cachelines(x)
1233 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1237 fl = &rxq->ifr_fl[flid];
1238 iru->iru_paddrs = fl->ifl_bus_addrs;
1239 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1240 iru->iru_idxs = fl->ifl_rxd_idxs;
1241 iru->iru_qsidx = rxq->ifr_id;
1242 iru->iru_buf_size = fl->ifl_buf_size;
1243 iru->iru_flidx = fl->ifl_id;
1247 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1251 *(bus_addr_t *) arg = segs[0].ds_addr;
1255 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1258 if_shared_ctx_t sctx = ctx->ifc_sctx;
1259 device_t dev = ctx->ifc_dev;
1261 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1263 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1264 sctx->isc_q_align, 0, /* alignment, bounds */
1265 BUS_SPACE_MAXADDR, /* lowaddr */
1266 BUS_SPACE_MAXADDR, /* highaddr */
1267 NULL, NULL, /* filter, filterarg */
1270 size, /* maxsegsize */
1271 BUS_DMA_ALLOCNOW, /* flags */
1272 NULL, /* lockfunc */
1277 "%s: bus_dma_tag_create failed: %d\n",
1282 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1283 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1286 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1287 __func__, (uintmax_t)size, err);
1291 dma->idi_paddr = IF_BAD_DMA;
1292 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1293 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1294 if (err || dma->idi_paddr == IF_BAD_DMA) {
1296 "%s: bus_dmamap_load failed: %d\n",
1301 dma->idi_size = size;
1305 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1307 bus_dma_tag_destroy(dma->idi_tag);
1309 dma->idi_tag = NULL;
1315 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1318 iflib_dma_info_t *dmaiter;
1321 for (i = 0; i < count; i++, dmaiter++) {
1322 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1326 iflib_dma_free_multi(dmalist, i);
1331 iflib_dma_free(iflib_dma_info_t dma)
1333 if (dma->idi_tag == NULL)
1335 if (dma->idi_paddr != IF_BAD_DMA) {
1336 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1338 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1339 dma->idi_paddr = IF_BAD_DMA;
1341 if (dma->idi_vaddr != NULL) {
1342 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1343 dma->idi_vaddr = NULL;
1345 bus_dma_tag_destroy(dma->idi_tag);
1346 dma->idi_tag = NULL;
1350 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1353 iflib_dma_info_t *dmaiter = dmalist;
1355 for (i = 0; i < count; i++, dmaiter++)
1356 iflib_dma_free(*dmaiter);
1359 #ifdef EARLY_AP_STARTUP
1360 static const int iflib_started = 1;
1363 * We used to abuse the smp_started flag to decide if the queues have been
1364 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1365 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1366 * is set. Run a SYSINIT() strictly after that to just set a usable
1370 static int iflib_started;
1373 iflib_record_started(void *arg)
1378 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1379 iflib_record_started, NULL);
1383 iflib_fast_intr(void *arg)
1385 iflib_filter_info_t info = arg;
1386 struct grouptask *gtask = info->ifi_task;
1388 return (FILTER_HANDLED);
1390 DBG_COUNTER_INC(fast_intrs);
1391 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1392 return (FILTER_HANDLED);
1394 GROUPTASK_ENQUEUE(gtask);
1395 return (FILTER_HANDLED);
1399 iflib_fast_intr_rxtx(void *arg)
1401 iflib_filter_info_t info = arg;
1402 struct grouptask *gtask = info->ifi_task;
1403 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1408 return (FILTER_HANDLED);
1410 DBG_COUNTER_INC(fast_intrs);
1411 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1412 return (FILTER_HANDLED);
1414 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1415 qidx_t txqid = rxq->ifr_txqid[i];
1419 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1420 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1423 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1425 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1426 cidx = rxq->ifr_cq_cidx;
1428 cidx = rxq->ifr_fl[0].ifl_cidx;
1429 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1430 GROUPTASK_ENQUEUE(gtask);
1432 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1433 return (FILTER_HANDLED);
1438 iflib_fast_intr_ctx(void *arg)
1440 iflib_filter_info_t info = arg;
1441 struct grouptask *gtask = info->ifi_task;
1444 return (FILTER_HANDLED);
1446 DBG_COUNTER_INC(fast_intrs);
1447 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1448 return (FILTER_HANDLED);
1450 GROUPTASK_ENQUEUE(gtask);
1451 return (FILTER_HANDLED);
1455 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1456 driver_filter_t filter, driver_intr_t handler, void *arg,
1460 struct resource *res;
1462 device_t dev = ctx->ifc_dev;
1465 if (ctx->ifc_flags & IFC_LEGACY)
1466 flags |= RF_SHAREABLE;
1469 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1472 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1476 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1477 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1478 filter, handler, arg, &tag);
1481 "failed to setup interrupt for rid %d, name %s: %d\n",
1482 rid, name ? name : "unknown", rc);
1485 bus_describe_intr(dev, res, tag, "%s", name);
1492 /*********************************************************************
1494 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1495 * the information needed to transmit a packet on the wire. This is
1496 * called only once at attach, setup is done every reset.
1498 **********************************************************************/
1501 iflib_txsd_alloc(iflib_txq_t txq)
1503 if_ctx_t ctx = txq->ift_ctx;
1504 if_shared_ctx_t sctx = ctx->ifc_sctx;
1505 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1506 device_t dev = ctx->ifc_dev;
1507 int err, nsegments, ntsosegments;
1509 nsegments = scctx->isc_tx_nsegments;
1510 ntsosegments = scctx->isc_tx_tso_segments_max;
1511 MPASS(scctx->isc_ntxd[0] > 0);
1512 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1513 MPASS(nsegments > 0);
1514 MPASS(ntsosegments > 0);
1516 * Setup DMA descriptor areas.
1518 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1519 1, 0, /* alignment, bounds */
1520 BUS_SPACE_MAXADDR, /* lowaddr */
1521 BUS_SPACE_MAXADDR, /* highaddr */
1522 NULL, NULL, /* filter, filterarg */
1523 sctx->isc_tx_maxsize, /* maxsize */
1524 nsegments, /* nsegments */
1525 sctx->isc_tx_maxsegsize, /* maxsegsize */
1527 NULL, /* lockfunc */
1528 NULL, /* lockfuncarg */
1529 &txq->ift_desc_tag))) {
1530 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1531 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1532 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1535 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1536 1, 0, /* alignment, bounds */
1537 BUS_SPACE_MAXADDR, /* lowaddr */
1538 BUS_SPACE_MAXADDR, /* highaddr */
1539 NULL, NULL, /* filter, filterarg */
1540 scctx->isc_tx_tso_size_max, /* maxsize */
1541 ntsosegments, /* nsegments */
1542 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1544 NULL, /* lockfunc */
1545 NULL, /* lockfuncarg */
1546 &txq->ift_tso_desc_tag))) {
1547 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1551 if (!(txq->ift_sds.ifsd_flags =
1552 (uint8_t *) malloc(sizeof(uint8_t) *
1553 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1554 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1558 if (!(txq->ift_sds.ifsd_m =
1559 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1560 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1561 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1566 /* Create the descriptor buffer dma maps */
1567 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1568 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1571 if (!(txq->ift_sds.ifsd_map =
1572 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1573 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1578 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1579 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1581 device_printf(dev, "Unable to create TX DMA map\n");
1588 /* We free all, it handles case where we are in the middle */
1589 iflib_tx_structures_free(ctx);
1594 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1599 if (txq->ift_sds.ifsd_map != NULL)
1600 map = txq->ift_sds.ifsd_map[i];
1602 bus_dmamap_unload(txq->ift_desc_tag, map);
1603 bus_dmamap_destroy(txq->ift_desc_tag, map);
1604 txq->ift_sds.ifsd_map[i] = NULL;
1609 iflib_txq_destroy(iflib_txq_t txq)
1611 if_ctx_t ctx = txq->ift_ctx;
1613 for (int i = 0; i < txq->ift_size; i++)
1614 iflib_txsd_destroy(ctx, txq, i);
1615 if (txq->ift_sds.ifsd_map != NULL) {
1616 free(txq->ift_sds.ifsd_map, M_IFLIB);
1617 txq->ift_sds.ifsd_map = NULL;
1619 if (txq->ift_sds.ifsd_m != NULL) {
1620 free(txq->ift_sds.ifsd_m, M_IFLIB);
1621 txq->ift_sds.ifsd_m = NULL;
1623 if (txq->ift_sds.ifsd_flags != NULL) {
1624 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1625 txq->ift_sds.ifsd_flags = NULL;
1627 if (txq->ift_desc_tag != NULL) {
1628 bus_dma_tag_destroy(txq->ift_desc_tag);
1629 txq->ift_desc_tag = NULL;
1631 if (txq->ift_tso_desc_tag != NULL) {
1632 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1633 txq->ift_tso_desc_tag = NULL;
1638 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1642 mp = &txq->ift_sds.ifsd_m[i];
1646 if (txq->ift_sds.ifsd_map != NULL) {
1647 bus_dmamap_sync(txq->ift_desc_tag,
1648 txq->ift_sds.ifsd_map[i],
1649 BUS_DMASYNC_POSTWRITE);
1650 bus_dmamap_unload(txq->ift_desc_tag,
1651 txq->ift_sds.ifsd_map[i]);
1654 DBG_COUNTER_INC(tx_frees);
1659 iflib_txq_setup(iflib_txq_t txq)
1661 if_ctx_t ctx = txq->ift_ctx;
1662 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1663 iflib_dma_info_t di;
1666 /* Set number of descriptors available */
1667 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1668 /* XXX make configurable */
1669 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1672 txq->ift_cidx_processed = 0;
1673 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1674 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1676 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1677 bzero((void *)di->idi_vaddr, di->idi_size);
1679 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1680 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1681 bus_dmamap_sync(di->idi_tag, di->idi_map,
1682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1686 /*********************************************************************
1688 * Allocate memory for rx_buffer structures. Since we use one
1689 * rx_buffer per received packet, the maximum number of rx_buffer's
1690 * that we'll need is equal to the number of receive descriptors
1691 * that we've allocated.
1693 **********************************************************************/
1695 iflib_rxsd_alloc(iflib_rxq_t rxq)
1697 if_ctx_t ctx = rxq->ifr_ctx;
1698 if_shared_ctx_t sctx = ctx->ifc_sctx;
1699 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1700 device_t dev = ctx->ifc_dev;
1704 MPASS(scctx->isc_nrxd[0] > 0);
1705 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1708 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1709 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1710 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1711 1, 0, /* alignment, bounds */
1712 BUS_SPACE_MAXADDR, /* lowaddr */
1713 BUS_SPACE_MAXADDR, /* highaddr */
1714 NULL, NULL, /* filter, filterarg */
1715 sctx->isc_rx_maxsize, /* maxsize */
1716 sctx->isc_rx_nsegments, /* nsegments */
1717 sctx->isc_rx_maxsegsize, /* maxsegsize */
1719 NULL, /* lockfunc */
1723 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1727 if (!(fl->ifl_sds.ifsd_flags =
1728 (uint8_t *) malloc(sizeof(uint8_t) *
1729 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1730 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1734 if (!(fl->ifl_sds.ifsd_m =
1735 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1736 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1737 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1741 if (!(fl->ifl_sds.ifsd_cl =
1742 (caddr_t *) malloc(sizeof(caddr_t) *
1743 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1744 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1749 /* Create the descriptor buffer dma maps */
1750 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1751 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1754 if (!(fl->ifl_sds.ifsd_map =
1755 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1756 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1761 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1762 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1764 device_printf(dev, "Unable to create RX buffer DMA map\n");
1773 iflib_rx_structures_free(ctx);
1779 * Internal service routines
1782 struct rxq_refill_cb_arg {
1784 bus_dma_segment_t seg;
1789 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1791 struct rxq_refill_cb_arg *cb_arg = arg;
1793 cb_arg->error = error;
1794 cb_arg->seg = segs[0];
1795 cb_arg->nseg = nseg;
1800 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1802 #define IS_DMAR(ctx) (0)
1806 * rxq_refill - refill an rxq free-buffer list
1807 * @ctx: the iflib context
1808 * @rxq: the free-list to refill
1809 * @n: the number of new buffers to allocate
1811 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1812 * The caller must assure that @n does not exceed the queue's capacity.
1815 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1818 int idx, frag_idx = fl->ifl_fragidx;
1819 int pidx = fl->ifl_pidx;
1823 struct if_rxd_update iru;
1824 bus_dmamap_t *sd_map;
1830 sd_m = fl->ifl_sds.ifsd_m;
1831 sd_map = fl->ifl_sds.ifsd_map;
1832 sd_cl = fl->ifl_sds.ifsd_cl;
1833 sd_flags = fl->ifl_sds.ifsd_flags;
1835 credits = fl->ifl_credits;
1839 MPASS(credits + n <= fl->ifl_size);
1841 if (pidx < fl->ifl_cidx)
1842 MPASS(pidx + n <= fl->ifl_cidx);
1843 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1844 MPASS(fl->ifl_gen == 0);
1845 if (pidx > fl->ifl_cidx)
1846 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1848 DBG_COUNTER_INC(fl_refills);
1850 DBG_COUNTER_INC(fl_refills_large);
1851 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1854 * We allocate an uninitialized mbuf + cluster, mbuf is
1855 * initialized after rx.
1857 * If the cluster is still set then we know a minimum sized packet was received
1859 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1860 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1861 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1862 if ((cl = sd_cl[frag_idx]) == NULL) {
1863 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1866 fl->ifl_cl_enqueued++;
1869 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1873 fl->ifl_m_enqueued++;
1876 DBG_COUNTER_INC(rx_allocs);
1877 #if defined(__i386__) || defined(__amd64__)
1878 if (!IS_DMAR(ctx)) {
1879 bus_addr = pmap_kextract((vm_offset_t)cl);
1883 struct rxq_refill_cb_arg cb_arg;
1888 MPASS(sd_map != NULL);
1889 MPASS(sd_map[frag_idx] != NULL);
1890 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1891 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1892 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1893 BUS_DMASYNC_PREREAD);
1895 if (err != 0 || cb_arg.error) {
1899 if (fl->ifl_zone == zone_pack)
1900 uma_zfree(fl->ifl_zone, cl);
1905 bus_addr = cb_arg.seg.ds_addr;
1907 bit_set(fl->ifl_rx_bitmap, frag_idx);
1908 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1910 MPASS(sd_m[frag_idx] == NULL);
1911 sd_cl[frag_idx] = cl;
1913 fl->ifl_rxd_idxs[i] = frag_idx;
1914 fl->ifl_bus_addrs[i] = bus_addr;
1915 fl->ifl_vm_addrs[i] = cl;
1918 MPASS(credits <= fl->ifl_size);
1919 if (++idx == fl->ifl_size) {
1923 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1924 iru.iru_pidx = pidx;
1926 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1930 fl->ifl_credits = credits;
1936 iru.iru_pidx = pidx;
1938 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1940 fl->ifl_credits = credits;
1942 DBG_COUNTER_INC(rxd_flush);
1943 if (fl->ifl_pidx == 0)
1944 pidx = fl->ifl_size - 1;
1946 pidx = fl->ifl_pidx - 1;
1949 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1950 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1951 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1952 fl->ifl_fragidx = frag_idx;
1955 static __inline void
1956 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1958 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1959 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1961 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1964 MPASS(fl->ifl_credits <= fl->ifl_size);
1965 MPASS(reclaimable == delta);
1967 if (reclaimable > 0)
1968 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1972 iflib_fl_bufs_free(iflib_fl_t fl)
1974 iflib_dma_info_t idi = fl->ifl_ifdi;
1977 for (i = 0; i < fl->ifl_size; i++) {
1978 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1979 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1980 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1982 if (*sd_flags & RX_SW_DESC_INUSE) {
1983 if (fl->ifl_sds.ifsd_map != NULL) {
1984 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1985 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1986 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
1987 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1989 if (*sd_m != NULL) {
1990 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1991 uma_zfree(zone_mbuf, *sd_m);
1994 uma_zfree(fl->ifl_zone, *sd_cl);
1997 MPASS(*sd_cl == NULL);
1998 MPASS(*sd_m == NULL);
2001 fl->ifl_m_dequeued++;
2002 fl->ifl_cl_dequeued++;
2008 for (i = 0; i < fl->ifl_size; i++) {
2009 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2010 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2011 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2015 * Reset free list values
2017 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2018 bzero(idi->idi_vaddr, idi->idi_size);
2021 /*********************************************************************
2023 * Initialize a receive ring and its buffers.
2025 **********************************************************************/
2027 iflib_fl_setup(iflib_fl_t fl)
2029 iflib_rxq_t rxq = fl->ifl_rxq;
2030 if_ctx_t ctx = rxq->ifr_ctx;
2031 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2033 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2035 ** Free current RX buffer structs and their mbufs
2037 iflib_fl_bufs_free(fl);
2038 /* Now replenish the mbufs */
2039 MPASS(fl->ifl_credits == 0);
2041 * XXX don't set the max_frame_size to larger
2042 * than the hardware can handle
2044 if (sctx->isc_max_frame_size <= 2048)
2045 fl->ifl_buf_size = MCLBYTES;
2046 #ifndef CONTIGMALLOC_WORKS
2048 fl->ifl_buf_size = MJUMPAGESIZE;
2050 else if (sctx->isc_max_frame_size <= 4096)
2051 fl->ifl_buf_size = MJUMPAGESIZE;
2052 else if (sctx->isc_max_frame_size <= 9216)
2053 fl->ifl_buf_size = MJUM9BYTES;
2055 fl->ifl_buf_size = MJUM16BYTES;
2057 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2058 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2059 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2060 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2063 /* avoid pre-allocating zillions of clusters to an idle card
2064 * potentially speeding up attach
2066 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2067 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2068 if (min(128, fl->ifl_size) != fl->ifl_credits)
2074 MPASS(fl->ifl_ifdi != NULL);
2075 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2080 /*********************************************************************
2082 * Free receive ring data structures
2084 **********************************************************************/
2086 iflib_rx_sds_free(iflib_rxq_t rxq)
2091 if (rxq->ifr_fl != NULL) {
2092 for (i = 0; i < rxq->ifr_nfl; i++) {
2093 fl = &rxq->ifr_fl[i];
2094 if (fl->ifl_desc_tag != NULL) {
2095 bus_dma_tag_destroy(fl->ifl_desc_tag);
2096 fl->ifl_desc_tag = NULL;
2098 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2099 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2100 /* XXX destroy maps first */
2101 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2102 fl->ifl_sds.ifsd_m = NULL;
2103 fl->ifl_sds.ifsd_cl = NULL;
2104 fl->ifl_sds.ifsd_map = NULL;
2106 free(rxq->ifr_fl, M_IFLIB);
2108 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2113 * MI independent logic
2117 iflib_timer(void *arg)
2119 iflib_txq_t txq = arg;
2120 if_ctx_t ctx = txq->ift_ctx;
2121 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2123 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2126 ** Check on the state of the TX queue(s), this
2127 ** can be done without the lock because its RO
2128 ** and the HUNG state will be static if set.
2130 IFDI_TIMER(ctx, txq->ift_id);
2131 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2132 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2133 (sctx->isc_pause_frames == 0)))
2136 if (ifmp_ring_is_stalled(txq->ift_br))
2137 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2138 txq->ift_cleaned_prev = txq->ift_cleaned;
2139 /* handle any laggards */
2140 if (txq->ift_db_pending)
2141 GROUPTASK_ENQUEUE(&txq->ift_task);
2143 sctx->isc_pause_frames = 0;
2144 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2145 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2149 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2150 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2151 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2153 IFDI_WATCHDOG_RESET(ctx);
2154 ctx->ifc_watchdog_events++;
2156 ctx->ifc_flags |= IFC_DO_RESET;
2157 iflib_admin_intr_deferred(ctx);
2162 iflib_init_locked(if_ctx_t ctx)
2164 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2166 if_t ifp = ctx->ifc_ifp;
2170 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2173 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2174 IFDI_INTR_DISABLE(ctx);
2176 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2177 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2178 /* Set hardware offload abilities */
2179 if_clearhwassist(ifp);
2180 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2181 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2182 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2183 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2184 if (if_getcapenable(ifp) & IFCAP_TSO4)
2185 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2186 if (if_getcapenable(ifp) & IFCAP_TSO6)
2187 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2189 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2191 callout_stop(&txq->ift_timer);
2192 CALLOUT_UNLOCK(txq);
2193 iflib_netmap_txq_init(ctx, txq);
2196 i = if_getdrvflags(ifp);
2199 MPASS(if_getdrvflags(ifp) == i);
2200 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2201 /* XXX this should really be done on a per-queue basis */
2202 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2203 MPASS(rxq->ifr_id == i);
2204 iflib_netmap_rxq_init(ctx, rxq);
2207 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2208 if (iflib_fl_setup(fl)) {
2209 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2215 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2216 IFDI_INTR_ENABLE(ctx);
2217 txq = ctx->ifc_txqs;
2218 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2219 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2220 txq->ift_timer.c_cpu);
2224 iflib_media_change(if_t ifp)
2226 if_ctx_t ctx = if_getsoftc(ifp);
2230 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2231 iflib_init_locked(ctx);
2237 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2239 if_ctx_t ctx = if_getsoftc(ifp);
2242 IFDI_UPDATE_ADMIN_STATUS(ctx);
2243 IFDI_MEDIA_STATUS(ctx, ifmr);
2248 iflib_stop(if_ctx_t ctx)
2250 iflib_txq_t txq = ctx->ifc_txqs;
2251 iflib_rxq_t rxq = ctx->ifc_rxqs;
2252 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2253 iflib_dma_info_t di;
2257 /* Tell the stack that the interface is no longer active */
2258 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2260 IFDI_INTR_DISABLE(ctx);
2265 iflib_debug_reset();
2266 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2267 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2268 /* make sure all transmitters have completed before proceeding XXX */
2271 callout_stop(&txq->ift_timer);
2272 CALLOUT_UNLOCK(txq);
2274 /* clean any enqueued buffers */
2275 iflib_ifmp_purge(txq);
2276 /* Free any existing tx buffers. */
2277 for (j = 0; j < txq->ift_size; j++) {
2278 iflib_txsd_free(ctx, txq, j);
2280 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2281 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2282 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2283 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2284 txq->ift_pullups = 0;
2285 ifmp_ring_reset_stats(txq->ift_br);
2286 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2287 bzero((void *)di->idi_vaddr, di->idi_size);
2289 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2290 /* make sure all transmitters have completed before proceeding XXX */
2292 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2293 bzero((void *)di->idi_vaddr, di->idi_size);
2294 /* also resets the free lists pidx/cidx */
2295 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2296 iflib_fl_bufs_free(fl);
2300 static inline caddr_t
2301 calc_next_rxd(iflib_fl_t fl, int cidx)
2305 caddr_t start, end, cur, next;
2307 nrxd = fl->ifl_size;
2308 size = fl->ifl_rxd_size;
2309 start = fl->ifl_ifdi->idi_vaddr;
2311 if (__predict_false(size == 0))
2313 cur = start + size*cidx;
2314 end = start + size*nrxd;
2315 next = CACHE_PTR_NEXT(cur);
2316 return (next < end ? next : start);
2320 prefetch_pkts(iflib_fl_t fl, int cidx)
2323 int nrxd = fl->ifl_size;
2327 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2328 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2329 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2330 next_rxd = calc_next_rxd(fl, cidx);
2332 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2333 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2334 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2335 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2336 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2337 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2338 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2339 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2343 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2348 iflib_dma_info_t di;
2352 flid = irf->irf_flid;
2353 cidx = irf->irf_idx;
2354 fl = &rxq->ifr_fl[flid];
2356 sd->ifsd_cidx = cidx;
2357 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2358 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2361 fl->ifl_m_dequeued++;
2363 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2364 prefetch_pkts(fl, cidx);
2365 if (fl->ifl_sds.ifsd_map != NULL) {
2366 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2367 prefetch(&fl->ifl_sds.ifsd_map[next]);
2368 map = fl->ifl_sds.ifsd_map[cidx];
2370 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2371 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2372 bus_dmamap_sync(di->idi_tag, di->idi_map,
2373 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2375 /* not valid assert if bxe really does SGE from non-contiguous elements */
2376 MPASS(fl->ifl_cidx == cidx);
2378 bus_dmamap_unload(fl->ifl_desc_tag, map);
2380 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2381 if (__predict_false(fl->ifl_cidx == 0))
2384 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2386 bit_clear(fl->ifl_rx_bitmap, cidx);
2389 static struct mbuf *
2390 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2392 int i, padlen , flags;
2393 struct mbuf *m, *mh, *mt;
2399 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2401 MPASS(*sd->ifsd_cl != NULL);
2402 MPASS(*sd->ifsd_m != NULL);
2404 /* Don't include zero-length frags */
2405 if (ri->iri_frags[i].irf_len == 0) {
2406 /* XXX we can save the cluster here, but not the mbuf */
2407 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2408 m_free(*sd->ifsd_m);
2415 flags = M_PKTHDR|M_EXT;
2417 padlen = ri->iri_pad;
2422 /* assuming padding is only on the first fragment */
2426 *sd->ifsd_cl = NULL;
2428 /* Can these two be made one ? */
2429 m_init(m, M_NOWAIT, MT_DATA, flags);
2430 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2432 * These must follow m_init and m_cljset
2434 m->m_data += padlen;
2435 ri->iri_len -= padlen;
2436 m->m_len = ri->iri_frags[i].irf_len;
2437 } while (++i < ri->iri_nfrags);
2443 * Process one software descriptor
2445 static struct mbuf *
2446 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2451 /* should I merge this back in now that the two paths are basically duplicated? */
2452 if (ri->iri_nfrags == 1 &&
2453 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2454 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2457 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2458 #ifndef __NO_STRICT_ALIGNMENT
2462 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2463 m->m_len = ri->iri_frags[0].irf_len;
2465 m = assemble_segments(rxq, ri, &sd);
2467 m->m_pkthdr.len = ri->iri_len;
2468 m->m_pkthdr.rcvif = ri->iri_ifp;
2469 m->m_flags |= ri->iri_flags;
2470 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2471 m->m_pkthdr.flowid = ri->iri_flowid;
2472 M_HASHTYPE_SET(m, ri->iri_rsstype);
2473 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2474 m->m_pkthdr.csum_data = ri->iri_csum_data;
2478 #if defined(INET6) || defined(INET)
2480 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2482 CURVNET_SET(lc->ifp->if_vnet);
2484 *v6 = VNET(ip6_forwarding);
2487 *v4 = VNET(ipforwarding);
2493 * Returns true if it's possible this packet could be LROed.
2494 * if it returns false, it is guaranteed that tcp_lro_rx()
2495 * would not return zero.
2498 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2500 struct ether_header *eh;
2503 eh = mtod(m, struct ether_header *);
2504 eh_type = ntohs(eh->ether_type);
2507 case ETHERTYPE_IPV6:
2508 return !v6_forwarding;
2512 return !v4_forwarding;
2520 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2526 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2528 if_ctx_t ctx = rxq->ifr_ctx;
2529 if_shared_ctx_t sctx = ctx->ifc_sctx;
2530 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2533 struct if_rxd_info ri;
2534 int err, budget_left, rx_bytes, rx_pkts;
2538 bool lro_possible = false;
2539 bool v4_forwarding, v6_forwarding;
2542 * XXX early demux data packets so that if_input processing only handles
2543 * acks in interrupt context
2545 struct mbuf *m, *mh, *mt, *mf;
2550 rx_pkts = rx_bytes = 0;
2551 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2552 cidxp = &rxq->ifr_cq_cidx;
2554 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2555 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2556 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2557 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2558 DBG_COUNTER_INC(rx_unavail);
2562 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2563 if (__predict_false(!CTX_ACTIVE(ctx))) {
2564 DBG_COUNTER_INC(rx_ctx_inactive);
2568 * Reset client set fields to their default values
2571 ri.iri_qsidx = rxq->ifr_id;
2572 ri.iri_cidx = *cidxp;
2574 ri.iri_frags = rxq->ifr_frags;
2575 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2579 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2580 *cidxp = ri.iri_cidx;
2581 /* Update our consumer index */
2582 /* XXX NB: shurd - check if this is still safe */
2583 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2584 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2585 rxq->ifr_cq_gen = 0;
2587 /* was this only a completion queue message? */
2588 if (__predict_false(ri.iri_nfrags == 0))
2591 MPASS(ri.iri_nfrags != 0);
2592 MPASS(ri.iri_len != 0);
2594 /* will advance the cidx on the corresponding free lists */
2595 m = iflib_rxd_pkt_get(rxq, &ri);
2596 if (avail == 0 && budget_left)
2597 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2599 if (__predict_false(m == NULL)) {
2600 DBG_COUNTER_INC(rx_mbuf_null);
2603 /* imm_pkt: -- cxgb */
2611 /* make sure that we can refill faster than drain */
2612 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2613 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2615 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2617 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2619 while (mh != NULL) {
2622 m->m_nextpkt = NULL;
2623 #ifndef __NO_STRICT_ALIGNMENT
2624 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2627 rx_bytes += m->m_pkthdr.len;
2629 #if defined(INET6) || defined(INET)
2631 if (!lro_possible) {
2632 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2633 if (lro_possible && mf != NULL) {
2634 ifp->if_input(ifp, mf);
2635 DBG_COUNTER_INC(rx_if_input);
2639 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2640 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2641 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2647 ifp->if_input(ifp, m);
2648 DBG_COUNTER_INC(rx_if_input);
2659 ifp->if_input(ifp, mf);
2660 DBG_COUNTER_INC(rx_if_input);
2663 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2664 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2667 * Flush any outstanding LRO work
2669 #if defined(INET6) || defined(INET)
2670 tcp_lro_flush_all(&rxq->ifr_lc);
2674 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2677 ctx->ifc_flags |= IFC_DO_RESET;
2678 iflib_admin_intr_deferred(ctx);
2683 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2684 static inline qidx_t
2685 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2687 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2688 qidx_t minthresh = txq->ift_size / 8;
2689 if (in_use > 4*minthresh)
2690 return (notify_count);
2691 if (in_use > 2*minthresh)
2692 return (notify_count >> 1);
2693 if (in_use > minthresh)
2694 return (notify_count >> 3);
2698 static inline qidx_t
2699 txq_max_rs_deferred(iflib_txq_t txq)
2701 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2702 qidx_t minthresh = txq->ift_size / 8;
2703 if (txq->ift_in_use > 4*minthresh)
2704 return (notify_count);
2705 if (txq->ift_in_use > 2*minthresh)
2706 return (notify_count >> 1);
2707 if (txq->ift_in_use > minthresh)
2708 return (notify_count >> 2);
2712 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2713 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2715 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2716 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2717 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2719 /* forward compatibility for cxgb */
2720 #define FIRST_QSET(ctx) 0
2721 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2722 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2723 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2724 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2726 /* XXX we should be setting this to something other than zero */
2727 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2728 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2731 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2737 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2738 if (ring || txq->ift_db_pending >= max) {
2739 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2740 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2741 txq->ift_db_pending = txq->ift_npending = 0;
2749 print_pkt(if_pkt_info_t pi)
2751 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2752 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2753 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2754 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2755 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2756 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2760 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2761 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2764 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2766 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2767 struct ether_vlan_header *eh;
2771 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2772 M_WRITABLE(m) == 0) {
2773 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2782 * Determine where frame payload starts.
2783 * Jump over vlan headers if already present,
2784 * helpful for QinQ too.
2786 if (__predict_false(m->m_len < sizeof(*eh))) {
2788 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2791 eh = mtod(m, struct ether_vlan_header *);
2792 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2793 pi->ipi_etype = ntohs(eh->evl_proto);
2794 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2796 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2797 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2800 switch (pi->ipi_etype) {
2804 struct ip *ip = NULL;
2805 struct tcphdr *th = NULL;
2808 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2809 if (__predict_false(m->m_len < minthlen)) {
2811 * if this code bloat is causing too much of a hit
2812 * move it to a separate function and mark it noinline
2814 if (m->m_len == pi->ipi_ehdrlen) {
2817 if (n->m_len >= sizeof(*ip)) {
2818 ip = (struct ip *)n->m_data;
2819 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2820 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2823 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2825 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2829 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2831 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2832 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2833 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2836 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2837 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2838 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2840 pi->ipi_ip_hlen = ip->ip_hl << 2;
2841 pi->ipi_ipproto = ip->ip_p;
2842 pi->ipi_flags |= IPI_TX_IPV4;
2844 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2848 if (pi->ipi_ipproto == IPPROTO_TCP) {
2849 if (__predict_false(th == NULL)) {
2851 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2853 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2855 pi->ipi_tcp_hflags = th->th_flags;
2856 pi->ipi_tcp_hlen = th->th_off << 2;
2857 pi->ipi_tcp_seq = th->th_seq;
2859 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2861 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2862 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2863 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2864 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2866 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2873 case ETHERTYPE_IPV6:
2875 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2877 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2879 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2880 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2883 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2885 /* XXX-BZ this will go badly in case of ext hdrs. */
2886 pi->ipi_ipproto = ip6->ip6_nxt;
2887 pi->ipi_flags |= IPI_TX_IPV6;
2890 if (pi->ipi_ipproto == IPPROTO_TCP) {
2891 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2892 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2895 pi->ipi_tcp_hflags = th->th_flags;
2896 pi->ipi_tcp_hlen = th->th_off << 2;
2899 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2902 * The corresponding flag is set by the stack in the IPv4
2903 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2904 * So, set it here because the rest of the flow requires it.
2906 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2907 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2908 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2914 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2915 pi->ipi_ip_hlen = 0;
2923 static __noinline struct mbuf *
2924 collapse_pkthdr(struct mbuf *m0)
2926 struct mbuf *m, *m_next, *tmp;
2930 while (m_next != NULL && m_next->m_len == 0) {
2934 m_next = m_next->m_next;
2938 if ((m_next->m_flags & M_EXT) == 0) {
2939 m = m_defrag(m, M_NOWAIT);
2941 tmp = m_next->m_next;
2942 memcpy(m_next, m, MPKTHSIZE);
2950 * If dodgy hardware rejects the scatter gather chain we've handed it
2951 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2954 static __noinline struct mbuf *
2955 iflib_remove_mbuf(iflib_txq_t txq)
2958 struct mbuf *m, *mh, **ifsd_m;
2960 pidx = txq->ift_pidx;
2961 ifsd_m = txq->ift_sds.ifsd_m;
2962 ntxd = txq->ift_size;
2963 mh = m = ifsd_m[pidx];
2964 ifsd_m[pidx] = NULL;
2966 txq->ift_dequeued++;
2971 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2973 txq->ift_dequeued++;
2982 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2983 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2984 int max_segs, int flags)
2987 if_shared_ctx_t sctx;
2988 if_softc_ctx_t scctx;
2989 int i, next, pidx, err, ntxd, count;
2990 struct mbuf *m, *tmp, **ifsd_m;
2995 * Please don't ever do this
2997 if (__predict_false(m->m_len == 0))
2998 *m0 = m = collapse_pkthdr(m);
3001 sctx = ctx->ifc_sctx;
3002 scctx = &ctx->ifc_softc_ctx;
3003 ifsd_m = txq->ift_sds.ifsd_m;
3004 ntxd = txq->ift_size;
3005 pidx = txq->ift_pidx;
3007 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3009 err = bus_dmamap_load_mbuf_sg(tag, map,
3010 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3013 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3017 if (__predict_false(m->m_len <= 0)) {
3026 } while (m != NULL);
3027 if (count > *nsegs) {
3029 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3035 next = (pidx + count) & (ntxd-1);
3036 MPASS(ifsd_m[next] == NULL);
3041 } while (m != NULL);
3043 int buflen, sgsize, maxsegsz, max_sgsize;
3049 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3050 maxsegsz = scctx->isc_tx_tso_segsize_max;
3052 maxsegsz = sctx->isc_tx_maxsegsize;
3055 if (__predict_false(m->m_len <= 0)) {
3063 vaddr = (vm_offset_t)m->m_data;
3065 * see if we can't be smarter about physically
3066 * contiguous mappings
3068 next = (pidx + count) & (ntxd-1);
3069 MPASS(ifsd_m[next] == NULL);
3071 txq->ift_enqueued++;
3074 while (buflen > 0) {
3077 max_sgsize = MIN(buflen, maxsegsz);
3078 curaddr = pmap_kextract(vaddr);
3079 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3080 sgsize = MIN(sgsize, max_sgsize);
3081 segs[i].ds_addr = curaddr;
3082 segs[i].ds_len = sgsize;
3090 } while (m != NULL);
3095 *m0 = iflib_remove_mbuf(txq);
3099 static inline caddr_t
3100 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3104 caddr_t start, end, cur, next;
3106 ntxd = txq->ift_size;
3107 size = txq->ift_txd_size[qid];
3108 start = txq->ift_ifdi[qid].idi_vaddr;
3110 if (__predict_false(size == 0))
3112 cur = start + size*cidx;
3113 end = start + size*ntxd;
3114 next = CACHE_PTR_NEXT(cur);
3115 return (next < end ? next : start);
3119 * Pad an mbuf to ensure a minimum ethernet frame size.
3120 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3122 static __noinline int
3123 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3126 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3127 * and ARP message is the smallest common payload I can think of
3129 static char pad[18]; /* just zeros */
3131 struct mbuf *new_head;
3133 if (!M_WRITABLE(*m_head)) {
3134 new_head = m_dup(*m_head, M_NOWAIT);
3135 if (new_head == NULL) {
3137 device_printf(dev, "cannot pad short frame, m_dup() failed");
3138 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3145 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3146 n > 0; n -= sizeof(pad))
3147 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3152 device_printf(dev, "cannot pad short frame\n");
3153 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3161 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3164 if_shared_ctx_t sctx;
3165 if_softc_ctx_t scctx;
3166 bus_dma_segment_t *segs;
3167 struct mbuf *m_head;
3170 struct if_pkt_info pi;
3172 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3173 bus_dma_tag_t desc_tag;
3175 segs = txq->ift_segs;
3177 sctx = ctx->ifc_sctx;
3178 scctx = &ctx->ifc_softc_ctx;
3179 segs = txq->ift_segs;
3180 ntxd = txq->ift_size;
3185 * If we're doing TSO the next descriptor to clean may be quite far ahead
3187 cidx = txq->ift_cidx;
3188 pidx = txq->ift_pidx;
3189 if (ctx->ifc_flags & IFC_PREFETCH) {
3190 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3191 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3192 next_txd = calc_next_txd(txq, cidx, 0);
3196 /* prefetch the next cache line of mbuf pointers and flags */
3197 prefetch(&txq->ift_sds.ifsd_m[next]);
3198 if (txq->ift_sds.ifsd_map != NULL) {
3199 prefetch(&txq->ift_sds.ifsd_map[next]);
3200 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3201 prefetch(&txq->ift_sds.ifsd_flags[next]);
3203 } else if (txq->ift_sds.ifsd_map != NULL)
3204 map = txq->ift_sds.ifsd_map[pidx];
3206 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3207 desc_tag = txq->ift_tso_desc_tag;
3208 max_segs = scctx->isc_tx_tso_segments_max;
3210 desc_tag = txq->ift_desc_tag;
3211 max_segs = scctx->isc_tx_nsegments;
3213 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3214 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3215 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3222 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3224 pi.ipi_qsidx = txq->ift_id;
3225 pi.ipi_len = m_head->m_pkthdr.len;
3226 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3227 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3229 /* deliberate bitwise OR to make one condition */
3230 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3231 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3237 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3239 if (__predict_false(err)) {
3242 /* try collapse once and defrag once */
3244 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3246 m_head = m_defrag(*m_headp, M_NOWAIT);
3248 if (__predict_false(m_head == NULL))
3250 txq->ift_mbuf_defrag++;
3255 txq->ift_no_tx_dma_setup++;
3258 txq->ift_no_tx_dma_setup++;
3260 DBG_COUNTER_INC(tx_frees);
3264 txq->ift_map_failed++;
3265 DBG_COUNTER_INC(encap_load_mbuf_fail);
3270 * XXX assumes a 1 to 1 relationship between segments and
3271 * descriptors - this does not hold true on all drivers, e.g.
3274 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3275 txq->ift_no_desc_avail++;
3277 bus_dmamap_unload(desc_tag, map);
3278 DBG_COUNTER_INC(encap_txq_avail_fail);
3279 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3280 GROUPTASK_ENQUEUE(&txq->ift_task);
3284 * On Intel cards we can greatly reduce the number of TX interrupts
3285 * we see by only setting report status on every Nth descriptor.
3286 * However, this also means that the driver will need to keep track
3287 * of the descriptors that RS was set on to check them for the DD bit.
3289 txq->ift_rs_pending += nsegs + 1;
3290 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3291 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3292 pi.ipi_flags |= IPI_TX_INTR;
3293 txq->ift_rs_pending = 0;
3297 pi.ipi_nsegs = nsegs;
3299 MPASS(pidx >= 0 && pidx < txq->ift_size);
3304 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3305 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3307 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3309 DBG_COUNTER_INC(tx_encap);
3310 MPASS(pi.ipi_new_pidx < txq->ift_size);
3312 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3313 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3314 ndesc += txq->ift_size;
3318 * drivers can need as many as
3321 MPASS(ndesc <= pi.ipi_nsegs + 2);
3322 MPASS(pi.ipi_new_pidx != pidx);
3324 txq->ift_in_use += ndesc;
3327 * We update the last software descriptor again here because there may
3328 * be a sentinel and/or there may be more mbufs than segments
3330 txq->ift_pidx = pi.ipi_new_pidx;
3331 txq->ift_npending += pi.ipi_ndescs;
3332 } else if (__predict_false(err == EFBIG && remap < 2)) {
3333 *m_headp = m_head = iflib_remove_mbuf(txq);
3335 txq->ift_txd_encap_efbig++;
3338 DBG_COUNTER_INC(encap_txd_encap_fail);
3342 txq->ift_mbuf_defrag_failed++;
3343 txq->ift_map_failed++;
3345 DBG_COUNTER_INC(tx_frees);
3351 iflib_tx_desc_free(iflib_txq_t txq, int n)
3354 uint32_t qsize, cidx, mask, gen;
3355 struct mbuf *m, **ifsd_m;
3356 uint8_t *ifsd_flags;
3357 bus_dmamap_t *ifsd_map;
3360 cidx = txq->ift_cidx;
3362 qsize = txq->ift_size;
3364 hasmap = txq->ift_sds.ifsd_map != NULL;
3365 ifsd_flags = txq->ift_sds.ifsd_flags;
3366 ifsd_m = txq->ift_sds.ifsd_m;
3367 ifsd_map = txq->ift_sds.ifsd_map;
3368 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3372 prefetch(ifsd_m[(cidx + 3) & mask]);
3373 prefetch(ifsd_m[(cidx + 4) & mask]);
3375 if (ifsd_m[cidx] != NULL) {
3376 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3377 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3378 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3380 * does it matter if it's not the TSO tag? If so we'll
3381 * have to add the type to flags
3383 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3384 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3386 if ((m = ifsd_m[cidx]) != NULL) {
3387 /* XXX we don't support any drivers that batch packets yet */
3388 MPASS(m->m_nextpkt == NULL);
3389 /* if the number of clusters exceeds the number of segments
3390 * there won't be space on the ring to save a pointer to each
3391 * cluster so we simply free the list here
3393 if (m->m_flags & M_TOOBIG) {
3398 ifsd_m[cidx] = NULL;
3400 txq->ift_dequeued++;
3402 DBG_COUNTER_INC(tx_frees);
3405 if (__predict_false(++cidx == qsize)) {
3410 txq->ift_cidx = cidx;
3415 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3418 if_ctx_t ctx = txq->ift_ctx;
3420 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3421 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3424 * Need a rate-limiting check so that this isn't called every time
3426 iflib_tx_credits_update(ctx, txq);
3427 reclaim = DESC_RECLAIMABLE(txq);
3429 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3431 if (iflib_verbose_debug) {
3432 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3433 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3440 iflib_tx_desc_free(txq, reclaim);
3441 txq->ift_cleaned += reclaim;
3442 txq->ift_in_use -= reclaim;
3447 static struct mbuf **
3448 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3451 struct mbuf **items;
3454 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3455 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3457 prefetch(items[(cidx + offset) & (size-1)]);
3458 if (remaining > 1) {
3459 prefetch2cachelines(&items[next]);
3460 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3461 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3462 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3464 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3468 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3471 ifmp_ring_check_drainage(txq->ift_br, budget);
3475 iflib_txq_can_drain(struct ifmp_ring *r)
3477 iflib_txq_t txq = r->cookie;
3478 if_ctx_t ctx = txq->ift_ctx;
3480 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3481 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3485 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3487 iflib_txq_t txq = r->cookie;
3488 if_ctx_t ctx = txq->ift_ctx;
3489 struct ifnet *ifp = ctx->ifc_ifp;
3490 struct mbuf **mp, *m;
3491 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3492 int reclaimed, err, in_use_prev, desc_used;
3493 bool do_prefetch, ring, rang;
3495 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3496 !LINK_ACTIVE(ctx))) {
3497 DBG_COUNTER_INC(txq_drain_notready);
3500 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3501 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3502 avail = IDXDIFF(pidx, cidx, r->size);
3503 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3504 DBG_COUNTER_INC(txq_drain_flushing);
3505 for (i = 0; i < avail; i++) {
3506 m_free(r->items[(cidx + i) & (r->size-1)]);
3507 r->items[(cidx + i) & (r->size-1)] = NULL;
3512 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3513 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3515 callout_stop(&txq->ift_timer);
3516 CALLOUT_UNLOCK(txq);
3517 DBG_COUNTER_INC(txq_drain_oactive);
3521 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3522 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3523 count = MIN(avail, TX_BATCH_SIZE);
3525 if (iflib_verbose_debug)
3526 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3527 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3529 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3530 avail = TXQ_AVAIL(txq);
3531 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3532 int pidx_prev, rem = do_prefetch ? count - i : 0;
3534 mp = _ring_peek_one(r, cidx, i, rem);
3535 MPASS(mp != NULL && *mp != NULL);
3536 if (__predict_false(*mp == (struct mbuf *)txq)) {
3541 in_use_prev = txq->ift_in_use;
3542 pidx_prev = txq->ift_pidx;
3543 err = iflib_encap(txq, mp);
3544 if (__predict_false(err)) {
3545 DBG_COUNTER_INC(txq_drain_encapfail);
3546 /* no room - bail out */
3550 DBG_COUNTER_INC(txq_drain_encapfail);
3551 /* we can't send this packet - skip it */
3557 DBG_COUNTER_INC(tx_sent);
3558 bytes_sent += m->m_pkthdr.len;
3559 mcast_sent += !!(m->m_flags & M_MCAST);
3560 avail = TXQ_AVAIL(txq);
3562 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3563 desc_used += (txq->ift_in_use - in_use_prev);
3564 ETHER_BPF_MTAP(ifp, m);
3565 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3567 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3570 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3571 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3572 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3573 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3574 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3576 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3578 if (iflib_verbose_debug)
3579 printf("consumed=%d\n", consumed);
3585 iflib_txq_drain_always(struct ifmp_ring *r)
3591 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3599 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3601 callout_stop(&txq->ift_timer);
3602 CALLOUT_UNLOCK(txq);
3604 avail = IDXDIFF(pidx, cidx, r->size);
3605 for (i = 0; i < avail; i++) {
3606 mp = _ring_peek_one(r, cidx, i, avail - i);
3607 if (__predict_false(*mp == (struct mbuf *)txq))
3611 MPASS(ifmp_ring_is_stalled(r) == 0);
3616 iflib_ifmp_purge(iflib_txq_t txq)
3618 struct ifmp_ring *r;
3621 r->drain = iflib_txq_drain_free;
3622 r->can_drain = iflib_txq_drain_always;
3624 ifmp_ring_check_drainage(r, r->size);
3626 r->drain = iflib_txq_drain;
3627 r->can_drain = iflib_txq_can_drain;
3631 _task_fn_tx(void *context)
3633 iflib_txq_t txq = context;
3634 if_ctx_t ctx = txq->ift_ctx;
3635 struct ifnet *ifp = ctx->ifc_ifp;
3638 #ifdef IFLIB_DIAGNOSTICS
3639 txq->ift_cpu_exec_count[curcpu]++;
3641 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3643 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3644 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3645 netmap_tx_irq(ifp, txq->ift_id);
3646 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3649 if (txq->ift_db_pending)
3650 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3651 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3652 if (ctx->ifc_flags & IFC_LEGACY)
3653 IFDI_INTR_ENABLE(ctx);
3655 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3656 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3661 _task_fn_rx(void *context)
3663 iflib_rxq_t rxq = context;
3664 if_ctx_t ctx = rxq->ifr_ctx;
3669 #ifdef IFLIB_DIAGNOSTICS
3670 rxq->ifr_cpu_exec_count[curcpu]++;
3672 DBG_COUNTER_INC(task_fn_rxs);
3673 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3677 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3679 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3684 budget = ctx->ifc_sysctl_rx_budget;
3686 budget = 16; /* XXX */
3687 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3688 if (ctx->ifc_flags & IFC_LEGACY)
3689 IFDI_INTR_ENABLE(ctx);
3691 DBG_COUNTER_INC(rx_intr_enables);
3692 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3693 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3696 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3699 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3703 _task_fn_admin(void *context)
3705 if_ctx_t ctx = context;
3706 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3710 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) {
3711 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3717 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3719 callout_stop(&txq->ift_timer);
3720 CALLOUT_UNLOCK(txq);
3722 IFDI_UPDATE_ADMIN_STATUS(ctx);
3723 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3724 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3725 IFDI_LINK_INTR_ENABLE(ctx);
3726 if (ctx->ifc_flags & IFC_DO_RESET) {
3727 ctx->ifc_flags &= ~IFC_DO_RESET;
3728 iflib_if_init_locked(ctx);
3732 if (LINK_ACTIVE(ctx) == 0)
3734 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3735 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3740 _task_fn_iov(void *context)
3742 if_ctx_t ctx = context;
3744 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3748 IFDI_VFLR_HANDLE(ctx);
3753 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3756 if_int_delay_info_t info;
3759 info = (if_int_delay_info_t)arg1;
3760 ctx = info->iidi_ctx;
3761 info->iidi_req = req;
3762 info->iidi_oidp = oidp;
3764 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3769 /*********************************************************************
3773 **********************************************************************/
3776 iflib_if_init_locked(if_ctx_t ctx)
3779 iflib_init_locked(ctx);
3784 iflib_if_init(void *arg)
3789 iflib_if_init_locked(ctx);
3794 iflib_if_transmit(if_t ifp, struct mbuf *m)
3796 if_ctx_t ctx = if_getsoftc(ifp);
3801 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3802 DBG_COUNTER_INC(tx_frees);
3807 MPASS(m->m_nextpkt == NULL);
3809 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3810 qidx = QIDX(ctx, m);
3812 * XXX calculate buf_ring based on flowid (divvy up bits?)
3814 txq = &ctx->ifc_txqs[qidx];
3816 #ifdef DRIVER_BACKPRESSURE
3817 if (txq->ift_closed) {
3819 next = m->m_nextpkt;
3820 m->m_nextpkt = NULL;
3833 next = next->m_nextpkt;
3834 } while (next != NULL);
3836 if (count > nitems(marr))
3837 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3838 /* XXX check nextpkt */
3840 /* XXX simplify for now */
3841 DBG_COUNTER_INC(tx_frees);
3844 for (next = m, i = 0; next != NULL; i++) {
3846 next = next->m_nextpkt;
3847 mp[i]->m_nextpkt = NULL;
3850 DBG_COUNTER_INC(tx_seen);
3851 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3853 GROUPTASK_ENQUEUE(&txq->ift_task);
3855 /* support forthcoming later */
3856 #ifdef DRIVER_BACKPRESSURE
3857 txq->ift_closed = TRUE;
3859 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3867 iflib_if_qflush(if_t ifp)
3869 if_ctx_t ctx = if_getsoftc(ifp);
3870 iflib_txq_t txq = ctx->ifc_txqs;
3874 ctx->ifc_flags |= IFC_QFLUSH;
3876 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3877 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3878 iflib_txq_check_drain(txq, 0);
3880 ctx->ifc_flags &= ~IFC_QFLUSH;
3887 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3888 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3889 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3892 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3894 if_ctx_t ctx = if_getsoftc(ifp);
3895 struct ifreq *ifr = (struct ifreq *)data;
3896 #if defined(INET) || defined(INET6)
3897 struct ifaddr *ifa = (struct ifaddr *)data;
3899 bool avoid_reset = FALSE;
3900 int err = 0, reinit = 0, bits;
3905 if (ifa->ifa_addr->sa_family == AF_INET)
3909 if (ifa->ifa_addr->sa_family == AF_INET6)
3913 ** Calling init results in link renegotiation,
3914 ** so we avoid doing it when possible.
3917 if_setflagbits(ifp, IFF_UP,0);
3918 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3921 if (!(if_getflags(ifp) & IFF_NOARP))
3922 arp_ifinit(ifp, ifa);
3925 err = ether_ioctl(ifp, command, data);
3929 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3933 bits = if_getdrvflags(ifp);
3934 /* stop the driver and free any clusters before proceeding */
3937 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3938 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3939 ctx->ifc_flags |= IFC_MULTISEG;
3941 ctx->ifc_flags &= ~IFC_MULTISEG;
3942 err = if_setmtu(ifp, ifr->ifr_mtu);
3944 iflib_init_locked(ctx);
3945 if_setdrvflags(ifp, bits);
3950 if (if_getflags(ifp) & IFF_UP) {
3951 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3952 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3953 (IFF_PROMISC | IFF_ALLMULTI)) {
3954 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3958 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3961 ctx->ifc_if_flags = if_getflags(ifp);
3966 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3968 IFDI_INTR_DISABLE(ctx);
3969 IFDI_MULTI_SET(ctx);
3970 IFDI_INTR_ENABLE(ctx);
3976 IFDI_MEDIA_SET(ctx);
3981 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3985 struct ifi2creq i2c;
3987 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3990 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3994 if (i2c.len > sizeof(i2c.data)) {
3999 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4000 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4008 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4011 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4013 setmask |= (mask & IFCAP_FLAGS);
4015 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4016 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4017 if ((mask & IFCAP_WOL) &&
4018 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4019 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4022 * want to ensure that traffic has stopped before we change any of the flags
4026 bits = if_getdrvflags(ifp);
4027 if (bits & IFF_DRV_RUNNING)
4029 if_togglecapenable(ifp, setmask);
4030 if (bits & IFF_DRV_RUNNING)
4031 iflib_init_locked(ctx);
4032 if_setdrvflags(ifp, bits);
4037 case SIOCGPRIVATE_0:
4041 err = IFDI_PRIV_IOCTL(ctx, command, data);
4045 err = ether_ioctl(ifp, command, data);
4054 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4056 if_ctx_t ctx = if_getsoftc(ifp);
4058 return (IFDI_GET_COUNTER(ctx, cnt));
4061 /*********************************************************************
4063 * OTHER FUNCTIONS EXPORTED TO THE STACK
4065 **********************************************************************/
4068 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4070 if_ctx_t ctx = if_getsoftc(ifp);
4072 if ((void *)ctx != arg)
4075 if ((vtag == 0) || (vtag > 4095))
4079 IFDI_VLAN_REGISTER(ctx, vtag);
4080 /* Re-init to load the changes */
4081 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4082 iflib_if_init_locked(ctx);
4087 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4089 if_ctx_t ctx = if_getsoftc(ifp);
4091 if ((void *)ctx != arg)
4094 if ((vtag == 0) || (vtag > 4095))
4098 IFDI_VLAN_UNREGISTER(ctx, vtag);
4099 /* Re-init to load the changes */
4100 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4101 iflib_if_init_locked(ctx);
4106 iflib_led_func(void *arg, int onoff)
4111 IFDI_LED_FUNC(ctx, onoff);
4115 /*********************************************************************
4117 * BUS FUNCTION DEFINITIONS
4119 **********************************************************************/
4122 iflib_device_probe(device_t dev)
4124 pci_vendor_info_t *ent;
4126 uint16_t pci_vendor_id, pci_device_id;
4127 uint16_t pci_subvendor_id, pci_subdevice_id;
4128 uint16_t pci_rev_id;
4129 if_shared_ctx_t sctx;
4131 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4134 pci_vendor_id = pci_get_vendor(dev);
4135 pci_device_id = pci_get_device(dev);
4136 pci_subvendor_id = pci_get_subvendor(dev);
4137 pci_subdevice_id = pci_get_subdevice(dev);
4138 pci_rev_id = pci_get_revid(dev);
4139 if (sctx->isc_parse_devinfo != NULL)
4140 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4142 ent = sctx->isc_vendor_info;
4143 while (ent->pvi_vendor_id != 0) {
4144 if (pci_vendor_id != ent->pvi_vendor_id) {
4148 if ((pci_device_id == ent->pvi_device_id) &&
4149 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4150 (ent->pvi_subvendor_id == 0)) &&
4151 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4152 (ent->pvi_subdevice_id == 0)) &&
4153 ((pci_rev_id == ent->pvi_rev_id) ||
4154 (ent->pvi_rev_id == 0))) {
4156 device_set_desc_copy(dev, ent->pvi_name);
4157 /* this needs to be changed to zero if the bus probing code
4158 * ever stops re-probing on best match because the sctx
4159 * may have its values over written by register calls
4160 * in subsequent probes
4162 return (BUS_PROBE_DEFAULT);
4170 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4172 int err, rid, msix, msix_bar;
4175 if_softc_ctx_t scctx;
4181 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4184 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4185 device_set_softc(dev, ctx);
4186 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4189 ctx->ifc_sctx = sctx;
4191 ctx->ifc_softc = sc;
4193 if ((err = iflib_register(ctx)) != 0) {
4194 device_printf(dev, "iflib_register failed %d\n", err);
4197 iflib_add_device_sysctl_pre(ctx);
4199 scctx = &ctx->ifc_softc_ctx;
4203 * XXX sanity check that ntxd & nrxd are a power of 2
4205 if (ctx->ifc_sysctl_ntxqs != 0)
4206 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4207 if (ctx->ifc_sysctl_nrxqs != 0)
4208 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4210 for (i = 0; i < sctx->isc_ntxqs; i++) {
4211 if (ctx->ifc_sysctl_ntxds[i] != 0)
4212 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4214 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4217 for (i = 0; i < sctx->isc_nrxqs; i++) {
4218 if (ctx->ifc_sysctl_nrxds[i] != 0)
4219 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4221 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4224 for (i = 0; i < sctx->isc_nrxqs; i++) {
4225 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4226 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4227 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4228 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4230 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4231 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4232 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4233 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4237 for (i = 0; i < sctx->isc_ntxqs; i++) {
4238 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4239 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4240 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4241 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4243 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4244 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4245 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4246 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4250 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4251 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4254 _iflib_pre_assert(scctx);
4255 ctx->ifc_txrx = *scctx->isc_txrx;
4258 MPASS(scctx->isc_capenable);
4259 if (scctx->isc_capenable & IFCAP_TXCSUM)
4260 MPASS(scctx->isc_tx_csum_flags);
4263 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4264 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4266 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4267 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4268 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4269 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4272 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4273 ctx->ifc_flags |= IFC_DMAR;
4274 #elif !(defined(__i386__) || defined(__amd64__))
4275 /* set unconditionally for !x86 */
4276 ctx->ifc_flags |= IFC_DMAR;
4279 msix_bar = scctx->isc_msix_bar;
4280 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4281 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4283 /* XXX change for per-queue sizes */
4284 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4285 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4286 for (i = 0; i < sctx->isc_nrxqs; i++) {
4287 if (!powerof2(scctx->isc_nrxd[i])) {
4288 /* round down instead? */
4289 device_printf(dev, "# rx descriptors must be a power of 2\n");
4294 for (i = 0; i < sctx->isc_ntxqs; i++) {
4295 if (!powerof2(scctx->isc_ntxd[i])) {
4297 "# tx descriptors must be a power of 2");
4303 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4304 MAX_SINGLE_PACKET_FRACTION)
4305 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4306 MAX_SINGLE_PACKET_FRACTION);
4307 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4308 MAX_SINGLE_PACKET_FRACTION)
4309 scctx->isc_tx_tso_segments_max = max(1,
4310 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4313 * Protect the stack against modern hardware
4315 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4316 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4318 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4319 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4320 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4321 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4322 if (scctx->isc_rss_table_size == 0)
4323 scctx->isc_rss_table_size = 64;
4324 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4326 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4327 /* XXX format name */
4328 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4330 /* Set up cpu set. If it fails, use the set of all CPUs. */
4331 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4332 device_printf(dev, "Unable to fetch CPU list\n");
4333 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4335 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4338 ** Now setup MSI or MSI/X, should
4339 ** return us the number of supported
4340 ** vectors. (Will be 1 for MSI)
4342 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4343 msix = scctx->isc_vectors;
4344 } else if (scctx->isc_msix_bar != 0)
4346 * The simple fact that isc_msix_bar is not 0 does not mean we
4347 * we have a good value there that is known to work.
4349 msix = iflib_msix_init(ctx);
4351 scctx->isc_vectors = 1;
4352 scctx->isc_ntxqsets = 1;
4353 scctx->isc_nrxqsets = 1;
4354 scctx->isc_intr = IFLIB_INTR_LEGACY;
4357 /* Get memory for the station queues */
4358 if ((err = iflib_queues_alloc(ctx))) {
4359 device_printf(dev, "Unable to allocate queue memory\n");
4363 if ((err = iflib_qset_structures_setup(ctx))) {
4364 device_printf(dev, "qset structure setup failed %d\n", err);
4369 * Group taskqueues aren't properly set up until SMP is started,
4370 * so we disable interrupts until we can handle them post
4373 * XXX: disabling interrupts doesn't actually work, at least for
4374 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4375 * we do null handling and depend on this not causing too large an
4378 IFDI_INTR_DISABLE(ctx);
4379 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4380 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4381 goto fail_intr_free;
4385 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4389 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4390 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4391 goto fail_intr_free;
4394 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4395 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4396 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4399 if ((err = iflib_netmap_attach(ctx))) {
4400 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4405 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4406 iflib_add_device_sysctl_post(ctx);
4407 ctx->ifc_flags |= IFC_INIT_DONE;
4410 ether_ifdetach(ctx->ifc_ifp);
4412 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4413 pci_release_msi(ctx->ifc_dev);
4415 /* XXX free queues */
4422 iflib_device_attach(device_t dev)
4425 if_shared_ctx_t sctx;
4427 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4430 pci_enable_busmaster(dev);
4432 return (iflib_device_register(dev, NULL, sctx, &ctx));
4436 iflib_device_deregister(if_ctx_t ctx)
4438 if_t ifp = ctx->ifc_ifp;
4441 device_t dev = ctx->ifc_dev;
4443 struct taskqgroup *tqg;
4446 /* Make sure VLANS are not using driver */
4447 if (if_vlantrunkinuse(ifp)) {
4448 device_printf(dev,"Vlan in use, detach first\n");
4453 ctx->ifc_in_detach = 1;
4457 /* Unregister VLAN events */
4458 if (ctx->ifc_vlan_attach_event != NULL)
4459 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4460 if (ctx->ifc_vlan_detach_event != NULL)
4461 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4463 iflib_netmap_detach(ifp);
4464 ether_ifdetach(ifp);
4465 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4466 CTX_LOCK_DESTROY(ctx);
4467 if (ctx->ifc_led_dev != NULL)
4468 led_destroy(ctx->ifc_led_dev);
4469 /* XXX drain any dependent tasks */
4470 tqg = qgroup_if_io_tqg;
4471 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4472 callout_drain(&txq->ift_timer);
4473 if (txq->ift_task.gt_uniq != NULL)
4474 taskqgroup_detach(tqg, &txq->ift_task);
4476 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4477 if (rxq->ifr_task.gt_uniq != NULL)
4478 taskqgroup_detach(tqg, &rxq->ifr_task);
4480 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4481 free(fl->ifl_rx_bitmap, M_IFLIB);
4484 tqg = qgroup_if_config_tqg;
4485 if (ctx->ifc_admin_task.gt_uniq != NULL)
4486 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4487 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4488 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4491 device_set_softc(ctx->ifc_dev, NULL);
4492 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4493 pci_release_msi(dev);
4495 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4496 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4498 if (ctx->ifc_msix_mem != NULL) {
4499 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4500 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4501 ctx->ifc_msix_mem = NULL;
4504 bus_generic_detach(dev);
4507 iflib_tx_structures_free(ctx);
4508 iflib_rx_structures_free(ctx);
4509 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4510 free(ctx->ifc_softc, M_IFLIB);
4517 iflib_device_detach(device_t dev)
4519 if_ctx_t ctx = device_get_softc(dev);
4521 return (iflib_device_deregister(ctx));
4525 iflib_device_suspend(device_t dev)
4527 if_ctx_t ctx = device_get_softc(dev);
4533 return bus_generic_suspend(dev);
4536 iflib_device_shutdown(device_t dev)
4538 if_ctx_t ctx = device_get_softc(dev);
4544 return bus_generic_suspend(dev);
4549 iflib_device_resume(device_t dev)
4551 if_ctx_t ctx = device_get_softc(dev);
4552 iflib_txq_t txq = ctx->ifc_txqs;
4556 iflib_init_locked(ctx);
4558 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4559 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4561 return (bus_generic_resume(dev));
4565 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4568 if_ctx_t ctx = device_get_softc(dev);
4571 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4578 iflib_device_iov_uninit(device_t dev)
4580 if_ctx_t ctx = device_get_softc(dev);
4583 IFDI_IOV_UNINIT(ctx);
4588 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4591 if_ctx_t ctx = device_get_softc(dev);
4594 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4600 /*********************************************************************
4602 * MODULE FUNCTION DEFINITIONS
4604 **********************************************************************/
4607 * - Start a fast taskqueue thread for each core
4608 * - Start a taskqueue for control operations
4611 iflib_module_init(void)
4617 iflib_module_event_handler(module_t mod, int what, void *arg)
4623 if ((err = iflib_module_init()) != 0)
4629 return (EOPNOTSUPP);
4635 /*********************************************************************
4637 * PUBLIC FUNCTION DEFINITIONS
4638 * ordered as in iflib.h
4640 **********************************************************************/
4644 _iflib_assert(if_shared_ctx_t sctx)
4646 MPASS(sctx->isc_tx_maxsize);
4647 MPASS(sctx->isc_tx_maxsegsize);
4649 MPASS(sctx->isc_rx_maxsize);
4650 MPASS(sctx->isc_rx_nsegments);
4651 MPASS(sctx->isc_rx_maxsegsize);
4653 MPASS(sctx->isc_nrxd_min[0]);
4654 MPASS(sctx->isc_nrxd_max[0]);
4655 MPASS(sctx->isc_nrxd_default[0]);
4656 MPASS(sctx->isc_ntxd_min[0]);
4657 MPASS(sctx->isc_ntxd_max[0]);
4658 MPASS(sctx->isc_ntxd_default[0]);
4662 _iflib_pre_assert(if_softc_ctx_t scctx)
4665 MPASS(scctx->isc_txrx->ift_txd_encap);
4666 MPASS(scctx->isc_txrx->ift_txd_flush);
4667 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4668 MPASS(scctx->isc_txrx->ift_rxd_available);
4669 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4670 MPASS(scctx->isc_txrx->ift_rxd_refill);
4671 MPASS(scctx->isc_txrx->ift_rxd_flush);
4675 iflib_register(if_ctx_t ctx)
4677 if_shared_ctx_t sctx = ctx->ifc_sctx;
4678 driver_t *driver = sctx->isc_driver;
4679 device_t dev = ctx->ifc_dev;
4682 _iflib_assert(sctx);
4684 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4686 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4688 device_printf(dev, "can not allocate ifnet structure\n");
4693 * Initialize our context's device specific methods
4695 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4696 kobj_class_compile((kobj_class_t) driver);
4699 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4700 if_setsoftc(ifp, ctx);
4701 if_setdev(ifp, dev);
4702 if_setinitfn(ifp, iflib_if_init);
4703 if_setioctlfn(ifp, iflib_if_ioctl);
4704 if_settransmitfn(ifp, iflib_if_transmit);
4705 if_setqflushfn(ifp, iflib_if_qflush);
4706 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4708 ctx->ifc_vlan_attach_event =
4709 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4710 EVENTHANDLER_PRI_FIRST);
4711 ctx->ifc_vlan_detach_event =
4712 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4713 EVENTHANDLER_PRI_FIRST);
4715 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4716 iflib_media_change, iflib_media_status);
4723 iflib_queues_alloc(if_ctx_t ctx)
4725 if_shared_ctx_t sctx = ctx->ifc_sctx;
4726 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4727 device_t dev = ctx->ifc_dev;
4728 int nrxqsets = scctx->isc_nrxqsets;
4729 int ntxqsets = scctx->isc_ntxqsets;
4732 iflib_fl_t fl = NULL;
4733 int i, j, cpu, err, txconf, rxconf;
4734 iflib_dma_info_t ifdip;
4735 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4736 uint32_t *txqsizes = scctx->isc_txqsizes;
4737 uint8_t nrxqs = sctx->isc_nrxqs;
4738 uint8_t ntxqs = sctx->isc_ntxqs;
4739 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4742 struct ifmp_ring **brscp;
4744 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4745 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4751 /* Allocate the TX ring struct memory */
4753 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4754 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4755 device_printf(dev, "Unable to allocate TX ring memory\n");
4760 /* Now allocate the RX */
4762 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4763 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4764 device_printf(dev, "Unable to allocate RX ring memory\n");
4769 ctx->ifc_txqs = txq;
4770 ctx->ifc_rxqs = rxq;
4773 * XXX handle allocation failure
4775 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4776 /* Set up some basics */
4778 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4779 device_printf(dev, "failed to allocate iflib_dma_info\n");
4783 txq->ift_ifdi = ifdip;
4784 for (j = 0; j < ntxqs; j++, ifdip++) {
4785 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4786 device_printf(dev, "Unable to allocate Descriptor memory\n");
4790 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4791 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4795 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4796 txq->ift_br_offset = 1;
4798 txq->ift_br_offset = 0;
4801 txq->ift_timer.c_cpu = cpu;
4803 if (iflib_txsd_alloc(txq)) {
4804 device_printf(dev, "Critical Failure setting up TX buffers\n");
4809 /* Initialize the TX lock */
4810 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4811 device_get_nameunit(dev), txq->ift_id);
4812 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4813 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4815 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4816 device_get_nameunit(dev), txq->ift_id);
4818 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4819 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4821 /* XXX free any allocated rings */
4822 device_printf(dev, "Unable to allocate buf_ring\n");
4827 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4828 /* Set up some basics */
4830 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4831 device_printf(dev, "failed to allocate iflib_dma_info\n");
4836 rxq->ifr_ifdi = ifdip;
4837 /* XXX this needs to be changed if #rx queues != #tx queues */
4838 rxq->ifr_ntxqirq = 1;
4839 rxq->ifr_txqid[0] = i;
4840 for (j = 0; j < nrxqs; j++, ifdip++) {
4841 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4842 device_printf(dev, "Unable to allocate Descriptor memory\n");
4846 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4850 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4851 rxq->ifr_fl_offset = 1;
4853 rxq->ifr_fl_offset = 0;
4855 rxq->ifr_nfl = nfree_lists;
4857 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4858 device_printf(dev, "Unable to allocate free list memory\n");
4863 for (j = 0; j < nfree_lists; j++) {
4864 fl[j].ifl_rxq = rxq;
4866 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4867 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4869 /* Allocate receive buffers for the ring*/
4870 if (iflib_rxsd_alloc(rxq)) {
4872 "Critical Failure setting up receive buffers\n");
4877 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4878 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4882 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4883 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4884 for (i = 0; i < ntxqsets; i++) {
4885 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4887 for (j = 0; j < ntxqs; j++, di++) {
4888 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4889 paddrs[i*ntxqs + j] = di->idi_paddr;
4892 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4893 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4894 iflib_tx_structures_free(ctx);
4895 free(vaddrs, M_IFLIB);
4896 free(paddrs, M_IFLIB);
4899 free(vaddrs, M_IFLIB);
4900 free(paddrs, M_IFLIB);
4903 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4904 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4905 for (i = 0; i < nrxqsets; i++) {
4906 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4908 for (j = 0; j < nrxqs; j++, di++) {
4909 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4910 paddrs[i*nrxqs + j] = di->idi_paddr;
4913 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4914 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4915 iflib_tx_structures_free(ctx);
4916 free(vaddrs, M_IFLIB);
4917 free(paddrs, M_IFLIB);
4920 free(vaddrs, M_IFLIB);
4921 free(paddrs, M_IFLIB);
4925 /* XXX handle allocation failure changes */
4928 if (ctx->ifc_rxqs != NULL)
4929 free(ctx->ifc_rxqs, M_IFLIB);
4930 ctx->ifc_rxqs = NULL;
4931 if (ctx->ifc_txqs != NULL)
4932 free(ctx->ifc_txqs, M_IFLIB);
4933 ctx->ifc_txqs = NULL;
4936 free(brscp, M_IFLIB);
4946 iflib_tx_structures_setup(if_ctx_t ctx)
4948 iflib_txq_t txq = ctx->ifc_txqs;
4951 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4952 iflib_txq_setup(txq);
4958 iflib_tx_structures_free(if_ctx_t ctx)
4960 iflib_txq_t txq = ctx->ifc_txqs;
4963 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4964 iflib_txq_destroy(txq);
4965 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4966 iflib_dma_free(&txq->ift_ifdi[j]);
4968 free(ctx->ifc_txqs, M_IFLIB);
4969 ctx->ifc_txqs = NULL;
4970 IFDI_QUEUES_FREE(ctx);
4973 /*********************************************************************
4975 * Initialize all receive rings.
4977 **********************************************************************/
4979 iflib_rx_structures_setup(if_ctx_t ctx)
4981 iflib_rxq_t rxq = ctx->ifc_rxqs;
4983 #if defined(INET6) || defined(INET)
4987 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4988 #if defined(INET6) || defined(INET)
4989 tcp_lro_free(&rxq->ifr_lc);
4990 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4991 TCP_LRO_ENTRIES, min(1024,
4992 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4993 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4996 rxq->ifr_lro_enabled = TRUE;
4998 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5001 #if defined(INET6) || defined(INET)
5004 * Free RX software descriptors allocated so far, we will only handle
5005 * the rings that completed, the failing case will have
5006 * cleaned up for itself. 'q' failed, so its the terminus.
5008 rxq = ctx->ifc_rxqs;
5009 for (i = 0; i < q; ++i, rxq++) {
5010 iflib_rx_sds_free(rxq);
5011 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5017 /*********************************************************************
5019 * Free all receive rings.
5021 **********************************************************************/
5023 iflib_rx_structures_free(if_ctx_t ctx)
5025 iflib_rxq_t rxq = ctx->ifc_rxqs;
5027 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5028 iflib_rx_sds_free(rxq);
5033 iflib_qset_structures_setup(if_ctx_t ctx)
5037 if ((err = iflib_tx_structures_setup(ctx)) != 0)
5040 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
5041 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5042 iflib_tx_structures_free(ctx);
5043 iflib_rx_structures_free(ctx);
5049 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5050 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
5053 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5058 find_nth(if_ctx_t ctx, int qid)
5061 int i, cpuid, eqid, count;
5063 CPU_COPY(&ctx->ifc_cpus, &cpus);
5064 count = CPU_COUNT(&cpus);
5066 /* clear up to the qid'th bit */
5067 for (i = 0; i < eqid; i++) {
5068 cpuid = CPU_FFS(&cpus);
5070 CPU_CLR(cpuid-1, &cpus);
5072 cpuid = CPU_FFS(&cpus);
5078 extern struct cpu_group *cpu_top; /* CPU topology */
5081 find_child_with_core(int cpu, struct cpu_group *grp)
5085 if (grp->cg_children == 0)
5088 MPASS(grp->cg_child);
5089 for (i = 0; i < grp->cg_children; i++) {
5090 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5098 * Find the nth thread on the specified core
5101 find_thread(int cpu, int thread_num)
5103 struct cpu_group *grp;
5111 while ((i = find_child_with_core(cpu, grp)) != -1) {
5112 /* If the child only has one cpu, don't descend */
5113 if (grp->cg_child[i].cg_count <= 1)
5115 grp = &grp->cg_child[i];
5118 /* If they don't share at least an L2 cache, use the same CPU */
5119 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5123 CPU_COPY(&grp->cg_mask, &cs);
5124 for (i = thread_num % grp->cg_count; i > 0; i--) {
5125 MPASS(CPU_FFS(&cs));
5126 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5128 MPASS(CPU_FFS(&cs));
5129 return CPU_FFS(&cs) - 1;
5133 find_thread(int cpu, int thread_num __unused)
5140 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5144 /* TX queues get threads on the same core as the corresponding RX queue */
5145 /* XXX handle multiple RX threads per core and more than two threads per core */
5146 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5148 case IFLIB_INTR_RXTX:
5149 /* RX queues get the first thread on their core */
5150 return qid / CPU_COUNT(&ctx->ifc_cpus);
5156 #define get_thread_num(ctx, type, qid) CPU_FIRST()
5157 #define find_thread(cpuid, tid) CPU_FIRST()
5158 #define find_nth(ctx, gid) CPU_FIRST()
5161 /* Just to avoid copy/paste */
5163 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5164 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name)
5169 cpuid = find_nth(ctx, qid);
5170 tid = get_thread_num(ctx, type, qid);
5172 cpuid = find_thread(cpuid, tid);
5173 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5175 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5179 if (cpuid > ctx->ifc_cpuid_highest)
5180 ctx->ifc_cpuid_highest = cpuid;
5186 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5187 iflib_intr_type_t type, driver_filter_t *filter,
5188 void *filter_arg, int qid, char *name)
5190 struct grouptask *gtask;
5191 struct taskqgroup *tqg;
5192 iflib_filter_info_t info;
5195 driver_filter_t *intr_fast;
5198 info = &ctx->ifc_filter_info;
5202 /* XXX merge tx/rx for netmap? */
5204 q = &ctx->ifc_txqs[qid];
5205 info = &ctx->ifc_txqs[qid].ift_filter_info;
5206 gtask = &ctx->ifc_txqs[qid].ift_task;
5207 tqg = qgroup_if_io_tqg;
5209 intr_fast = iflib_fast_intr;
5210 GROUPTASK_INIT(gtask, 0, fn, q);
5213 q = &ctx->ifc_rxqs[qid];
5214 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5215 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5216 tqg = qgroup_if_io_tqg;
5218 intr_fast = iflib_fast_intr;
5219 GROUPTASK_INIT(gtask, 0, fn, q);
5221 case IFLIB_INTR_RXTX:
5222 q = &ctx->ifc_rxqs[qid];
5223 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5224 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5225 tqg = qgroup_if_io_tqg;
5227 intr_fast = iflib_fast_intr_rxtx;
5228 GROUPTASK_INIT(gtask, 0, fn, q);
5230 case IFLIB_INTR_ADMIN:
5233 info = &ctx->ifc_filter_info;
5234 gtask = &ctx->ifc_admin_task;
5235 tqg = qgroup_if_config_tqg;
5236 fn = _task_fn_admin;
5237 intr_fast = iflib_fast_intr_ctx;
5240 panic("unknown net intr type");
5243 info->ifi_filter = filter;
5244 info->ifi_filter_arg = filter_arg;
5245 info->ifi_task = gtask;
5248 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5250 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5253 if (type == IFLIB_INTR_ADMIN)
5257 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5261 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5268 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name)
5270 struct grouptask *gtask;
5271 struct taskqgroup *tqg;
5279 q = &ctx->ifc_txqs[qid];
5280 gtask = &ctx->ifc_txqs[qid].ift_task;
5281 tqg = qgroup_if_io_tqg;
5284 irq_num = rman_get_start(irq->ii_res);
5287 q = &ctx->ifc_rxqs[qid];
5288 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5289 tqg = qgroup_if_io_tqg;
5292 irq_num = rman_get_start(irq->ii_res);
5294 case IFLIB_INTR_IOV:
5296 gtask = &ctx->ifc_vflr_task;
5297 tqg = qgroup_if_config_tqg;
5301 panic("unknown net intr type");
5303 GROUPTASK_INIT(gtask, 0, fn, q);
5304 if (irq_num != -1) {
5305 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5307 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5310 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5315 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5318 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5321 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5325 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5327 iflib_txq_t txq = ctx->ifc_txqs;
5328 iflib_rxq_t rxq = ctx->ifc_rxqs;
5329 if_irq_t irq = &ctx->ifc_legacy_irq;
5330 iflib_filter_info_t info;
5331 struct grouptask *gtask;
5332 struct taskqgroup *tqg;
5338 q = &ctx->ifc_rxqs[0];
5339 info = &rxq[0].ifr_filter_info;
5340 gtask = &rxq[0].ifr_task;
5341 tqg = qgroup_if_io_tqg;
5342 tqrid = irq->ii_rid = *rid;
5345 ctx->ifc_flags |= IFC_LEGACY;
5346 info->ifi_filter = filter;
5347 info->ifi_filter_arg = filter_arg;
5348 info->ifi_task = gtask;
5349 info->ifi_ctx = ctx;
5351 /* We allocate a single interrupt resource */
5352 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5354 GROUPTASK_INIT(gtask, 0, fn, q);
5355 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5357 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5358 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5363 iflib_led_create(if_ctx_t ctx)
5366 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5367 device_get_nameunit(ctx->ifc_dev));
5371 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5374 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5378 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5381 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5385 iflib_admin_intr_deferred(if_ctx_t ctx)
5388 struct grouptask *gtask;
5390 gtask = &ctx->ifc_admin_task;
5391 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5394 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5398 iflib_iov_intr_deferred(if_ctx_t ctx)
5401 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5405 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5408 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5412 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
5416 GROUPTASK_INIT(gtask, 0, fn, ctx);
5417 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5421 iflib_config_gtask_deinit(struct grouptask *gtask)
5424 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5428 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5430 if_t ifp = ctx->ifc_ifp;
5431 iflib_txq_t txq = ctx->ifc_txqs;
5433 if_setbaudrate(ifp, baudrate);
5434 if (baudrate >= IF_Gbps(10))
5435 ctx->ifc_flags |= IFC_PREFETCH;
5437 /* If link down, disable watchdog */
5438 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5439 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5440 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5442 ctx->ifc_link_state = link_state;
5443 if_link_state_change(ifp, link_state);
5447 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5451 int credits_pre = txq->ift_cidx_processed;
5454 if (ctx->isc_txd_credits_update == NULL)
5457 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5460 txq->ift_processed += credits;
5461 txq->ift_cidx_processed += credits;
5463 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5464 if (txq->ift_cidx_processed >= txq->ift_size)
5465 txq->ift_cidx_processed -= txq->ift_size;
5470 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5473 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5478 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5479 const char *description, if_int_delay_info_t info,
5480 int offset, int value)
5482 info->iidi_ctx = ctx;
5483 info->iidi_offset = offset;
5484 info->iidi_value = value;
5485 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5486 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5487 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5488 info, 0, iflib_sysctl_int_delay, "I", description);
5492 iflib_ctx_lock_get(if_ctx_t ctx)
5495 return (&ctx->ifc_mtx);
5499 iflib_msix_init(if_ctx_t ctx)
5501 device_t dev = ctx->ifc_dev;
5502 if_shared_ctx_t sctx = ctx->ifc_sctx;
5503 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5504 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5505 int iflib_num_tx_queues, iflib_num_rx_queues;
5506 int err, admincnt, bar;
5508 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5509 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5511 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5513 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5514 admincnt = sctx->isc_admin_intrcnt;
5515 /* Override by global tuneable */
5518 size_t len = sizeof(i);
5519 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0);
5525 device_printf(dev, "unable to read hw.pci.enable_msix.");
5528 /* Override by tuneable */
5529 if (scctx->isc_disable_msix)
5533 ** When used in a virtualized environment
5534 ** PCI BUSMASTER capability may not be set
5535 ** so explicity set it here and rewrite
5536 ** the ENABLE in the MSIX control register
5537 ** at this point to cause the host to
5538 ** successfully initialize us.
5543 pci_enable_busmaster(dev);
5545 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5546 rid += PCIR_MSIX_CTRL;
5547 msix_ctrl = pci_read_config(dev, rid, 2);
5548 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5549 pci_write_config(dev, rid, msix_ctrl, 2);
5551 device_printf(dev, "PCIY_MSIX capability not found; "
5552 "or rid %d == 0.\n", rid);
5558 * bar == -1 => "trust me I know what I'm doing"
5559 * Some drivers are for hardware that is so shoddily
5560 * documented that no one knows which bars are which
5561 * so the developer has to map all bars. This hack
5562 * allows shoddy garbage to use msix in this framework.
5565 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5566 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5567 if (ctx->ifc_msix_mem == NULL) {
5568 /* May not be enabled */
5569 device_printf(dev, "Unable to map MSIX table \n");
5573 /* First try MSI/X */
5574 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5575 device_printf(dev, "System has MSIX disabled \n");
5576 bus_release_resource(dev, SYS_RES_MEMORY,
5577 bar, ctx->ifc_msix_mem);
5578 ctx->ifc_msix_mem = NULL;
5582 /* use only 1 qset in debug mode */
5583 queuemsgs = min(msgs - admincnt, 1);
5585 queuemsgs = msgs - admincnt;
5588 queues = imin(queuemsgs, rss_getnumbuckets());
5592 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5593 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5594 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5596 /* If we're doing RSS, clamp at the number of RSS buckets */
5597 if (queues > rss_getnumbuckets())
5598 queues = rss_getnumbuckets();
5600 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5601 rx_queues = iflib_num_rx_queues;
5605 if (rx_queues > scctx->isc_nrxqsets)
5606 rx_queues = scctx->isc_nrxqsets;
5609 * We want this to be all logical CPUs by default
5611 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5612 tx_queues = iflib_num_tx_queues;
5614 tx_queues = mp_ncpus;
5616 if (tx_queues > scctx->isc_ntxqsets)
5617 tx_queues = scctx->isc_ntxqsets;
5619 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5621 if (tx_queues != rx_queues)
5622 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5623 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5625 tx_queues = min(rx_queues, tx_queues);
5626 rx_queues = min(rx_queues, tx_queues);
5629 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5631 vectors = rx_queues + admincnt;
5632 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5634 "Using MSIX interrupts with %d vectors\n", vectors);
5635 scctx->isc_vectors = vectors;
5636 scctx->isc_nrxqsets = rx_queues;
5637 scctx->isc_ntxqsets = tx_queues;
5638 scctx->isc_intr = IFLIB_INTR_MSIX;
5642 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5645 vectors = pci_msi_count(dev);
5646 scctx->isc_nrxqsets = 1;
5647 scctx->isc_ntxqsets = 1;
5648 scctx->isc_vectors = vectors;
5649 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5650 device_printf(dev,"Using an MSI interrupt\n");
5651 scctx->isc_intr = IFLIB_INTR_MSI;
5653 device_printf(dev,"Using a Legacy interrupt\n");
5654 scctx->isc_intr = IFLIB_INTR_LEGACY;
5660 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5663 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5666 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5668 char *ring_state = "UNKNOWN";
5671 rc = sysctl_wire_old_buffer(req, 0);
5675 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5680 ring_state = ring_states[state[3]];
5682 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5683 state[0], state[1], state[2], ring_state);
5684 rc = sbuf_finish(sb);
5689 enum iflib_ndesc_handler {
5695 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5697 if_ctx_t ctx = (void *)arg1;
5698 enum iflib_ndesc_handler type = arg2;
5699 char buf[256] = {0};
5704 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5708 case IFLIB_NTXD_HANDLER:
5709 ndesc = ctx->ifc_sysctl_ntxds;
5711 nqs = ctx->ifc_sctx->isc_ntxqs;
5713 case IFLIB_NRXD_HANDLER:
5714 ndesc = ctx->ifc_sysctl_nrxds;
5716 nqs = ctx->ifc_sctx->isc_nrxqs;
5722 for (i=0; i<8; i++) {
5727 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5730 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5731 if (rc || req->newptr == NULL)
5734 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5735 i++, p = strsep(&next, " ,")) {
5736 ndesc[i] = strtoul(p, NULL, 10);
5742 #define NAME_BUFLEN 32
5744 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5746 device_t dev = iflib_get_dev(ctx);
5747 struct sysctl_oid_list *child, *oid_list;
5748 struct sysctl_ctx_list *ctx_list;
5749 struct sysctl_oid *node;
5751 ctx_list = device_get_sysctl_ctx(dev);
5752 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5753 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5754 CTLFLAG_RD, NULL, "IFLIB fields");
5755 oid_list = SYSCTL_CHILDREN(node);
5757 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5758 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5761 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5762 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5763 "# of txqs to use, 0 => use default #");
5764 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5765 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5766 "# of rxqs to use, 0 => use default #");
5767 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5768 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5769 "permit #txq != #rxq");
5770 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5771 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5772 "disable MSIX (default 0)");
5773 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
5774 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
5775 "set the rx budget");
5777 /* XXX change for per-queue sizes */
5778 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5779 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5780 mp_ndesc_handler, "A",
5781 "list of # of tx descriptors to use, 0 = use default #");
5782 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5783 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5784 mp_ndesc_handler, "A",
5785 "list of # of rx descriptors to use, 0 = use default #");
5789 iflib_add_device_sysctl_post(if_ctx_t ctx)
5791 if_shared_ctx_t sctx = ctx->ifc_sctx;
5792 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5793 device_t dev = iflib_get_dev(ctx);
5794 struct sysctl_oid_list *child;
5795 struct sysctl_ctx_list *ctx_list;
5800 char namebuf[NAME_BUFLEN];
5802 struct sysctl_oid *queue_node, *fl_node, *node;
5803 struct sysctl_oid_list *queue_list, *fl_list;
5804 ctx_list = device_get_sysctl_ctx(dev);
5806 node = ctx->ifc_sysctl_node;
5807 child = SYSCTL_CHILDREN(node);
5809 if (scctx->isc_ntxqsets > 100)
5811 else if (scctx->isc_ntxqsets > 10)
5815 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5816 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5817 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5818 CTLFLAG_RD, NULL, "Queue Name");
5819 queue_list = SYSCTL_CHILDREN(queue_node);
5821 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5823 &txq->ift_dequeued, "total mbufs freed");
5824 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5826 &txq->ift_enqueued, "total mbufs enqueued");
5828 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5830 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5831 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5833 &txq->ift_pullups, "# of times m_pullup was called");
5834 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5836 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5837 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5839 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5840 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5842 &txq->ift_map_failed, "# of times dma map failed");
5843 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5845 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5846 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5848 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5849 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5851 &txq->ift_pidx, 1, "Producer Index");
5852 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5854 &txq->ift_cidx, 1, "Consumer Index");
5855 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5857 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5858 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5860 &txq->ift_in_use, 1, "descriptors in use");
5861 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5863 &txq->ift_processed, "descriptors procesed for clean");
5864 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5866 &txq->ift_cleaned, "total cleaned");
5867 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5868 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5869 0, mp_ring_state_handler, "A", "soft ring state");
5870 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5871 CTLFLAG_RD, &txq->ift_br->enqueues,
5872 "# of enqueues to the mp_ring for this queue");
5873 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5874 CTLFLAG_RD, &txq->ift_br->drops,
5875 "# of drops in the mp_ring for this queue");
5876 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5877 CTLFLAG_RD, &txq->ift_br->starts,
5878 "# of normal consumer starts in the mp_ring for this queue");
5879 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5880 CTLFLAG_RD, &txq->ift_br->stalls,
5881 "# of consumer stalls in the mp_ring for this queue");
5882 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5883 CTLFLAG_RD, &txq->ift_br->restarts,
5884 "# of consumer restarts in the mp_ring for this queue");
5885 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5886 CTLFLAG_RD, &txq->ift_br->abdications,
5887 "# of consumer abdications in the mp_ring for this queue");
5890 if (scctx->isc_nrxqsets > 100)
5892 else if (scctx->isc_nrxqsets > 10)
5896 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5897 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5898 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5899 CTLFLAG_RD, NULL, "Queue Name");
5900 queue_list = SYSCTL_CHILDREN(queue_node);
5901 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5902 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5904 &rxq->ifr_cq_pidx, 1, "Producer Index");
5905 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5907 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5910 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5911 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5912 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5913 CTLFLAG_RD, NULL, "freelist Name");
5914 fl_list = SYSCTL_CHILDREN(fl_node);
5915 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5917 &fl->ifl_pidx, 1, "Producer Index");
5918 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5920 &fl->ifl_cidx, 1, "Consumer Index");
5921 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5923 &fl->ifl_credits, 1, "credits available");
5925 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5927 &fl->ifl_m_enqueued, "mbufs allocated");
5928 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5930 &fl->ifl_m_dequeued, "mbufs freed");
5931 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5933 &fl->ifl_cl_enqueued, "clusters allocated");
5934 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5936 &fl->ifl_cl_dequeued, "clusters freed");
5944 #ifndef __NO_STRICT_ALIGNMENT
5945 static struct mbuf *
5946 iflib_fixup_rx(struct mbuf *m)
5950 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5951 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5952 m->m_data += ETHER_HDR_LEN;
5955 MGETHDR(n, M_NOWAIT, MT_DATA);
5960 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
5961 m->m_data += ETHER_HDR_LEN;
5962 m->m_len -= ETHER_HDR_LEN;
5963 n->m_len = ETHER_HDR_LEN;
5964 M_MOVE_PKTHDR(n, m);