2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 #define IFLIB_RXEOF_MORE (1U << 0)
132 #define IFLIB_RXEOF_EMPTY (2U << 0)
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
145 static void iflib_tqg_detach(if_ctx_t ctx);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 struct ether_addr ifc_mac;
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (ctx->ifc_mediap);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 struct callout ift_netmap_timer;
352 #endif /* DEV_NETMAP */
354 if_txsd_vec_t ift_sds;
357 uint8_t ift_update_freq;
358 struct iflib_filter_info ift_filter_info;
359 bus_dma_tag_t ift_buf_tag;
360 bus_dma_tag_t ift_tso_buf_tag;
361 iflib_dma_info_t ift_ifdi;
362 #define MTX_NAME_LEN 32
363 char ift_mtx_name[MTX_NAME_LEN];
364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
365 #ifdef IFLIB_DIAGNOSTICS
366 uint64_t ift_cpu_exec_count[256];
368 } __aligned(CACHE_LINE_SIZE);
375 uint8_t ifl_rxd_size;
377 uint64_t ifl_m_enqueued;
378 uint64_t ifl_m_dequeued;
379 uint64_t ifl_cl_enqueued;
380 uint64_t ifl_cl_dequeued;
383 bitstr_t *ifl_rx_bitmap;
387 uint16_t ifl_buf_size;
390 iflib_rxsd_array_t ifl_sds;
393 bus_dma_tag_t ifl_buf_tag;
394 iflib_dma_info_t ifl_ifdi;
395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 } __aligned(CACHE_LINE_SIZE);
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
406 else if (pidx < cidx)
407 used = size - cidx + pidx;
408 else if (gen == 0 && pidx == cidx)
410 else if (gen == 1 && pidx == cidx)
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
420 #define IDXDIFF(head, tail, wrap) \
421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
427 struct pfil_head *pfil;
429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
430 * the completion queue consumer index. Otherwise it's unused.
436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
437 uint8_t ifr_fl_offset;
438 struct lro_ctrl ifr_lc;
439 struct grouptask ifr_task;
440 struct callout ifr_watchdog;
441 struct iflib_filter_info ifr_filter_info;
442 iflib_dma_info_t ifr_ifdi;
444 /* dynamically allocate if any drivers need a value substantially larger than this */
445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
446 #ifdef IFLIB_DIAGNOSTICS
447 uint64_t ifr_cpu_exec_count[256];
449 } __aligned(CACHE_LINE_SIZE);
451 typedef struct if_rxsd {
456 /* multiple of word size */
458 #define PKT_INFO_SIZE 6
459 #define RXD_INFO_SIZE 5
460 #define PKT_TYPE uint64_t
462 #define PKT_INFO_SIZE 11
463 #define RXD_INFO_SIZE 8
464 #define PKT_TYPE uint32_t
466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
469 typedef struct if_pkt_info_pad {
470 PKT_TYPE pkt_val[PKT_INFO_SIZE];
471 } *if_pkt_info_pad_t;
472 typedef struct if_rxd_info_pad {
473 PKT_TYPE rxd_val[RXD_INFO_SIZE];
474 } *if_rxd_info_pad_t;
476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
480 pkt_info_zero(if_pkt_info_t pi)
482 if_pkt_info_pad_t pi_pad;
484 pi_pad = (if_pkt_info_pad_t)pi;
485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
493 static device_method_t iflib_pseudo_methods[] = {
494 DEVMETHOD(device_attach, noop_attach),
495 DEVMETHOD(device_detach, iflib_pseudo_detach),
499 driver_t iflib_pseudodriver = {
500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
504 rxd_info_zero(if_rxd_info_t ri)
506 if_rxd_info_pad_t ri_pad;
509 ri_pad = (if_rxd_info_pad_t)ri;
510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
511 ri_pad->rxd_val[i] = 0;
512 ri_pad->rxd_val[i+1] = 0;
513 ri_pad->rxd_val[i+2] = 0;
514 ri_pad->rxd_val[i+3] = 0;
517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
522 * Only allow a single packet to take up most 1/nth of the tx ring
524 #define MAX_SINGLE_PACKET_FRACTION 12
525 #define IF_BAD_DMA (bus_addr_t)-1
527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
543 iflib_set_detach(if_ctx_t ctx)
546 ctx->ifc_flags |= IFC_IN_DETACH;
550 /* Our boot-time initialization hook */
551 static int iflib_module_event_handler(module_t, int, void *);
553 static moduledata_t iflib_moduledata = {
555 iflib_module_event_handler,
559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
560 MODULE_VERSION(iflib, 1);
562 MODULE_DEPEND(iflib, pci, 1, 1, 1);
563 MODULE_DEPEND(iflib, ether, 1, 1, 1);
565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
568 #ifndef IFLIB_DEBUG_COUNTERS
570 #define IFLIB_DEBUG_COUNTERS 1
572 #define IFLIB_DEBUG_COUNTERS 0
573 #endif /* !INVARIANTS */
576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
577 "iflib driver parameters");
580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
582 static int iflib_min_tx_latency = 0;
583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
585 static int iflib_no_tx_batch = 0;
586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
589 #if IFLIB_DEBUG_COUNTERS
591 static int iflib_tx_seen;
592 static int iflib_tx_sent;
593 static int iflib_tx_encap;
594 static int iflib_rx_allocs;
595 static int iflib_fl_refills;
596 static int iflib_fl_refills_large;
597 static int iflib_tx_frees;
599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
600 &iflib_tx_seen, 0, "# TX mbufs seen");
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
602 &iflib_tx_sent, 0, "# TX mbufs sent");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
604 &iflib_tx_encap, 0, "# TX mbufs encapped");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
606 &iflib_tx_frees, 0, "# TX frees");
607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
608 &iflib_rx_allocs, 0, "# RX allocations");
609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
610 &iflib_fl_refills, 0, "# refills");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
612 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
625 static int iflib_encap_load_mbuf_fail;
626 static int iflib_encap_pad_mbuf_fail;
627 static int iflib_encap_txq_avail_fail;
628 static int iflib_encap_txd_encap_fail;
630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
631 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
633 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
635 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
637 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
639 static int iflib_task_fn_rxs;
640 static int iflib_rx_intr_enables;
641 static int iflib_fast_intrs;
642 static int iflib_rx_unavail;
643 static int iflib_rx_ctx_inactive;
644 static int iflib_rx_if_input;
645 static int iflib_rxd_flush;
647 static int iflib_verbose_debug;
649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
650 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
652 &iflib_rx_intr_enables, 0, "# RX intr enables");
653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
654 &iflib_fast_intrs, 0, "# fast_intr calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
656 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
660 &iflib_rx_if_input, 0, "# times rxeof called if_input");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
662 &iflib_rxd_flush, 0, "# times rxd_flush called");
663 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
664 &iflib_verbose_debug, 0, "enable verbose debugging");
666 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
668 iflib_debug_reset(void)
670 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
671 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
672 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
673 iflib_txq_drain_notready =
674 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
675 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
676 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
678 iflib_rx_ctx_inactive = iflib_rx_if_input =
683 #define DBG_COUNTER_INC(name)
684 static void iflib_debug_reset(void) {}
687 #define IFLIB_DEBUG 0
689 static void iflib_tx_structures_free(if_ctx_t ctx);
690 static void iflib_rx_structures_free(if_ctx_t ctx);
691 static int iflib_queues_alloc(if_ctx_t ctx);
692 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
693 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
694 static int iflib_qset_structures_setup(if_ctx_t ctx);
695 static int iflib_msix_init(if_ctx_t ctx);
696 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
697 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
698 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
700 static void iflib_altq_if_start(if_t ifp);
701 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
703 static int iflib_register(if_ctx_t);
704 static void iflib_deregister(if_ctx_t);
705 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
706 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
707 static void iflib_init_locked(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
710 static void iflib_ifmp_purge(iflib_txq_t txq);
711 static void _iflib_pre_assert(if_softc_ctx_t scctx);
712 static void iflib_if_init_locked(if_ctx_t ctx);
713 static void iflib_free_intr_mem(if_ctx_t ctx);
714 #ifndef __NO_STRICT_ALIGNMENT
715 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
719 SLIST_HEAD_INITIALIZER(cpu_offsets);
721 SLIST_ENTRY(cpu_offset) entries;
723 unsigned int refcount;
726 static struct mtx cpu_offset_mtx;
727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
730 DEBUGNET_DEFINE(iflib);
733 iflib_num_rx_descs(if_ctx_t ctx)
735 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
736 if_shared_ctx_t sctx = ctx->ifc_sctx;
737 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
739 return scctx->isc_nrxd[first_rxq];
743 iflib_num_tx_descs(if_ctx_t ctx)
745 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
746 if_shared_ctx_t sctx = ctx->ifc_sctx;
747 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
749 return scctx->isc_ntxd[first_txq];
753 #include <sys/selinfo.h>
754 #include <net/netmap.h>
755 #include <dev/netmap/netmap_kern.h>
757 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
760 static void iflib_netmap_timer(void *arg);
763 * device-specific sysctl variables:
765 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
766 * During regular operations the CRC is stripped, but on some
767 * hardware reception of frames not multiple of 64 is slower,
768 * so using crcstrip=0 helps in benchmarks.
770 * iflib_rx_miss, iflib_rx_miss_bufs:
771 * count packets that might be missed due to lost interrupts.
773 SYSCTL_DECL(_dev_netmap);
775 * The xl driver by default strips CRCs and we do not override it.
778 int iflib_crcstrip = 1;
779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
780 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
782 int iflib_rx_miss, iflib_rx_miss_bufs;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
784 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
786 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
789 * Register/unregister. We are already under netmap lock.
790 * Only called on the first register or the last unregister.
793 iflib_netmap_register(struct netmap_adapter *na, int onoff)
796 if_ctx_t ctx = ifp->if_softc;
800 IFDI_INTR_DISABLE(ctx);
802 /* Tell the stack that the interface is no longer active */
803 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
811 * Enable (or disable) netmap flags, and intercept (or restore)
812 * ifp->if_transmit. This is done once the device has been stopped
813 * to prevent race conditions.
816 nm_set_native_flags(na);
818 nm_clear_native_flags(na);
821 iflib_init_locked(ctx);
822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
825 nm_clear_native_flags(na);
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
833 struct netmap_adapter *na = kring->na;
834 u_int const lim = kring->nkr_num_slots - 1;
835 u_int nm_i = kring->nr_hwcur;
836 struct netmap_ring *ring = kring->ring;
838 struct if_rxd_update iru;
839 if_ctx_t ctx = rxq->ifr_ctx;
840 iflib_fl_t fl = &rxq->ifr_fl[0];
841 u_int nic_i_first, nic_i;
843 #if IFLIB_DEBUG_COUNTERS
848 * This function is used both at initialization and in rxsync.
849 * At initialization we need to prepare (with isc_rxd_refill())
850 * all the (N) netmap buffers in the ring, in such a way to keep
851 * fl->ifl_pidx and kring->nr_hwcur in sync (except for
852 * kring->nkr_hwofs); at rxsync time, both indexes point to the
853 * next buffer to be refilled.
854 * In any case we publish (with isc_rxd_flush()) up to
855 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
856 * pointer to overrun the head/cons pointer, although this is
857 * not necessary for some NICs (e.g. vmx).
859 if (__predict_false(init))
860 n = kring->nkr_num_slots;
862 n = kring->rhead - nm_i;
864 return (0); /* Nothing to do. */
866 n += kring->nkr_num_slots;
869 /* Start to refill from nr_hwcur, publishing n buffers. */
870 iru_init(&iru, rxq, 0 /* flid */);
871 map = fl->ifl_sds.ifsd_map;
872 nic_i = fl->ifl_pidx;
873 MPASS(nic_i == netmap_idx_k2n(kring, nm_i));
874 DBG_COUNTER_INC(fl_refills);
876 #if IFLIB_DEBUG_COUNTERS
878 DBG_COUNTER_INC(fl_refills_large);
881 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
882 struct netmap_slot *slot = &ring->slot[nm_i];
883 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
885 MPASS(i < IFLIB_MAX_RX_REFRESH);
887 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
888 return netmap_ring_reinit(kring);
890 fl->ifl_rxd_idxs[i] = nic_i;
892 if (__predict_false(init)) {
893 netmap_load_map(na, fl->ifl_buf_tag,
895 } else if (slot->flags & NS_BUF_CHANGED) {
896 /* buffer has changed, reload map */
897 netmap_reload_map(na, fl->ifl_buf_tag,
900 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
901 BUS_DMASYNC_PREREAD);
902 slot->flags &= ~NS_BUF_CHANGED;
904 nm_i = nm_next(nm_i, lim);
905 nic_i = nm_next(nic_i, lim);
908 iru.iru_pidx = nic_i_first;
910 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
912 fl->ifl_pidx = nic_i;
913 MPASS(!init || nm_i == 0);
914 MPASS(nm_i == kring->rhead);
915 kring->nr_hwcur = nm_i;
917 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
918 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
919 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
920 nm_prev(nic_i, lim));
921 DBG_COUNTER_INC(rxd_flush);
926 #define NETMAP_TX_TIMER_US 90
929 * Reconcile kernel and user view of the transmit ring.
931 * All information is in the kring.
932 * Userspace wants to send packets up to the one before kring->rhead,
933 * kernel knows kring->nr_hwcur is the first unsent packet.
935 * Here we push packets out (as many as possible), and possibly
936 * reclaim buffers from previously completed transmission.
938 * The caller (netmap) guarantees that there is only one instance
939 * running at any time. Any interference with other driver
940 * methods should be handled by the individual drivers.
943 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
945 struct netmap_adapter *na = kring->na;
947 struct netmap_ring *ring = kring->ring;
948 u_int nm_i; /* index into the netmap kring */
949 u_int nic_i; /* index into the NIC ring */
951 u_int const lim = kring->nkr_num_slots - 1;
952 u_int const head = kring->rhead;
953 struct if_pkt_info pi;
956 * interrupts on every tx packet are expensive so request
957 * them every half ring, or where NS_REPORT is set
959 u_int report_frequency = kring->nkr_num_slots >> 1;
960 /* device-specific */
961 if_ctx_t ctx = ifp->if_softc;
962 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
964 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
965 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
968 * First part: process new packets to send.
969 * nm_i is the current index in the netmap kring,
970 * nic_i is the corresponding index in the NIC ring.
972 * If we have packets to send (nm_i != head)
973 * iterate over the netmap ring, fetch length and update
974 * the corresponding slot in the NIC ring. Some drivers also
975 * need to update the buffer's physical address in the NIC slot
976 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
978 * The netmap_reload_map() calls is especially expensive,
979 * even when (as in this case) the tag is 0, so do only
980 * when the buffer has actually changed.
982 * If possible do not set the report/intr bit on all slots,
983 * but only a few times per ring or when NS_REPORT is set.
985 * Finally, on 10G and faster drivers, it might be useful
986 * to prefetch the next slot and txr entry.
989 nm_i = kring->nr_hwcur;
990 if (nm_i != head) { /* we have new packets to send */
992 pi.ipi_segs = txq->ift_segs;
993 pi.ipi_qsidx = kring->ring_id;
994 nic_i = netmap_idx_k2n(kring, nm_i);
996 __builtin_prefetch(&ring->slot[nm_i]);
997 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
998 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1000 for (n = 0; nm_i != head; n++) {
1001 struct netmap_slot *slot = &ring->slot[nm_i];
1002 u_int len = slot->len;
1004 void *addr = PNMB(na, slot, &paddr);
1005 int flags = (slot->flags & NS_REPORT ||
1006 nic_i == 0 || nic_i == report_frequency) ?
1009 /* device-specific */
1011 pi.ipi_segs[0].ds_addr = paddr;
1012 pi.ipi_segs[0].ds_len = len;
1015 pi.ipi_pidx = nic_i;
1016 pi.ipi_flags = flags;
1018 /* Fill the slot in the NIC ring. */
1019 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1020 DBG_COUNTER_INC(tx_encap);
1022 /* prefetch for next round */
1023 __builtin_prefetch(&ring->slot[nm_i + 1]);
1024 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1025 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1027 NM_CHECK_ADDR_LEN(na, addr, len);
1029 if (slot->flags & NS_BUF_CHANGED) {
1030 /* buffer has changed, reload map */
1031 netmap_reload_map(na, txq->ift_buf_tag,
1032 txq->ift_sds.ifsd_map[nic_i], addr);
1034 /* make sure changes to the buffer are synced */
1035 bus_dmamap_sync(txq->ift_buf_tag,
1036 txq->ift_sds.ifsd_map[nic_i],
1037 BUS_DMASYNC_PREWRITE);
1039 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1040 nm_i = nm_next(nm_i, lim);
1041 nic_i = nm_next(nic_i, lim);
1043 kring->nr_hwcur = nm_i;
1045 /* synchronize the NIC ring */
1046 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1049 /* (re)start the tx unit up to slot nic_i (excluded) */
1050 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1054 * Second part: reclaim buffers for completed transmissions.
1056 * If there are unclaimed buffers, attempt to reclaim them.
1057 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1058 * trigger a per-tx-queue timer to try again later.
1060 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1061 if (iflib_tx_credits_update(ctx, txq)) {
1062 /* some tx completed, increment avail */
1063 nic_i = txq->ift_cidx_processed;
1064 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1068 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1069 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1070 callout_reset_sbt_on(&txq->ift_netmap_timer,
1071 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1072 iflib_netmap_timer, txq,
1073 txq->ift_netmap_timer.c_cpu, 0);
1079 * Reconcile kernel and user view of the receive ring.
1080 * Same as for the txsync, this routine must be efficient.
1081 * The caller guarantees a single invocations, but races against
1082 * the rest of the driver should be handled here.
1084 * On call, kring->rhead is the first packet that userspace wants
1085 * to keep, and kring->rcur is the wakeup point.
1086 * The kernel has previously reported packets up to kring->rtail.
1088 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1089 * of whether or not we received an interrupt.
1092 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1094 struct netmap_adapter *na = kring->na;
1095 struct netmap_ring *ring = kring->ring;
1097 uint32_t nm_i; /* index into the netmap ring */
1098 uint32_t nic_i; /* index into the NIC ring */
1100 u_int const lim = kring->nkr_num_slots - 1;
1101 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1103 if_ctx_t ctx = ifp->if_softc;
1104 if_shared_ctx_t sctx = ctx->ifc_sctx;
1105 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1106 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1107 iflib_fl_t fl = &rxq->ifr_fl[0];
1108 struct if_rxd_info ri;
1112 * netmap only uses free list 0, to avoid out of order consumption
1113 * of receive buffers
1116 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1117 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1120 * First part: import newly received packets.
1122 * nm_i is the index of the next free slot in the netmap ring,
1123 * nic_i is the index of the next received packet in the NIC ring
1124 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1125 * differ in case if_init() has been called while
1126 * in netmap mode. For the receive ring we have
1128 * nic_i = fl->ifl_cidx;
1129 * nm_i = kring->nr_hwtail (previous)
1131 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1133 * fl->ifl_cidx is set to 0 on a ring reinit
1135 if (netmap_no_pendintr || force_update) {
1136 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1137 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1138 int crclen = iflib_crcstrip ? 0 : 4;
1142 * For the free list consumer index, we use the same
1143 * logic as in iflib_rxeof().
1146 cidxp = &rxq->ifr_cq_cidx;
1148 cidxp = &fl->ifl_cidx;
1149 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1150 rxq->ifr_id, *cidxp, USHRT_MAX);
1152 nic_i = fl->ifl_cidx;
1153 nm_i = netmap_idx_n2k(kring, nic_i);
1154 MPASS(nm_i == kring->nr_hwtail);
1155 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1157 ri.iri_frags = rxq->ifr_frags;
1158 ri.iri_qsidx = kring->ring_id;
1159 ri.iri_ifp = ctx->ifc_ifp;
1160 ri.iri_cidx = *cidxp;
1162 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1163 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1164 ring->slot[nm_i].flags = 0;
1166 *cidxp = ri.iri_cidx;
1167 while (*cidxp >= scctx->isc_nrxd[0])
1168 *cidxp -= scctx->isc_nrxd[0];
1170 bus_dmamap_sync(fl->ifl_buf_tag,
1171 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1172 nm_i = nm_next(nm_i, lim);
1173 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1175 if (n) { /* update the state variables */
1176 if (netmap_no_pendintr && !force_update) {
1179 iflib_rx_miss_bufs += n;
1181 kring->nr_hwtail = nm_i;
1183 kring->nr_kflags &= ~NKR_PENDINTR;
1186 * Second part: skip past packets that userspace has released.
1187 * (kring->nr_hwcur to head excluded),
1188 * and make the buffers available for reception.
1189 * As usual nm_i is the index in the netmap ring,
1190 * nic_i is the index in the NIC ring, and
1191 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1193 netmap_fl_refill(rxq, kring, false);
1199 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1201 if_ctx_t ctx = na->ifp->if_softc;
1205 IFDI_INTR_ENABLE(ctx);
1207 IFDI_INTR_DISABLE(ctx);
1213 iflib_netmap_attach(if_ctx_t ctx)
1215 struct netmap_adapter na;
1217 bzero(&na, sizeof(na));
1219 na.ifp = ctx->ifc_ifp;
1220 na.na_flags = NAF_BDG_MAYSLEEP;
1221 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1222 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1224 na.num_tx_desc = iflib_num_tx_descs(ctx);
1225 na.num_rx_desc = iflib_num_rx_descs(ctx);
1226 na.nm_txsync = iflib_netmap_txsync;
1227 na.nm_rxsync = iflib_netmap_rxsync;
1228 na.nm_register = iflib_netmap_register;
1229 na.nm_intr = iflib_netmap_intr;
1230 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1231 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1232 return (netmap_attach(&na));
1236 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1238 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1239 struct netmap_slot *slot;
1241 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1244 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1246 * In netmap mode, set the map for the packet buffer.
1247 * NOTE: Some drivers (not this one) also need to set
1248 * the physical buffer address in the NIC ring.
1249 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1250 * netmap slot index, si
1252 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1253 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1254 NMB(na, slot + si));
1260 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1262 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1263 struct netmap_kring *kring;
1264 struct netmap_slot *slot;
1266 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1269 kring = na->rx_rings[rxq->ifr_id];
1270 netmap_fl_refill(rxq, kring, true);
1275 iflib_netmap_timer(void *arg)
1277 iflib_txq_t txq = arg;
1278 if_ctx_t ctx = txq->ift_ctx;
1281 * Wake up the netmap application, to give it a chance to
1282 * call txsync and reclaim more completed TX buffers.
1284 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1287 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1290 #define iflib_netmap_txq_init(ctx, txq) (0)
1291 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1292 #define iflib_netmap_detach(ifp)
1294 #define iflib_netmap_attach(ctx) (0)
1295 #define netmap_rx_irq(ifp, qid, budget) (0)
1298 #if defined(__i386__) || defined(__amd64__)
1299 static __inline void
1302 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1304 static __inline void
1305 prefetch2cachelines(void *x)
1307 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1308 #if (CACHE_LINE_SIZE < 128)
1309 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1314 #define prefetch2cachelines(x)
1318 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1322 fl = &rxq->ifr_fl[flid];
1323 iru->iru_paddrs = fl->ifl_bus_addrs;
1324 iru->iru_idxs = fl->ifl_rxd_idxs;
1325 iru->iru_qsidx = rxq->ifr_id;
1326 iru->iru_buf_size = fl->ifl_buf_size;
1327 iru->iru_flidx = fl->ifl_id;
1331 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1335 *(bus_addr_t *) arg = segs[0].ds_addr;
1339 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1342 device_t dev = ctx->ifc_dev;
1344 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1345 align, 0, /* alignment, bounds */
1346 BUS_SPACE_MAXADDR, /* lowaddr */
1347 BUS_SPACE_MAXADDR, /* highaddr */
1348 NULL, NULL, /* filter, filterarg */
1351 size, /* maxsegsize */
1352 BUS_DMA_ALLOCNOW, /* flags */
1353 NULL, /* lockfunc */
1358 "%s: bus_dma_tag_create failed: %d\n",
1363 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1364 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1367 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1368 __func__, (uintmax_t)size, err);
1372 dma->idi_paddr = IF_BAD_DMA;
1373 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1374 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1375 if (err || dma->idi_paddr == IF_BAD_DMA) {
1377 "%s: bus_dmamap_load failed: %d\n",
1382 dma->idi_size = size;
1386 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1388 bus_dma_tag_destroy(dma->idi_tag);
1390 dma->idi_tag = NULL;
1396 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1398 if_shared_ctx_t sctx = ctx->ifc_sctx;
1400 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1402 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1406 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1409 iflib_dma_info_t *dmaiter;
1412 for (i = 0; i < count; i++, dmaiter++) {
1413 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1417 iflib_dma_free_multi(dmalist, i);
1422 iflib_dma_free(iflib_dma_info_t dma)
1424 if (dma->idi_tag == NULL)
1426 if (dma->idi_paddr != IF_BAD_DMA) {
1427 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1429 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1430 dma->idi_paddr = IF_BAD_DMA;
1432 if (dma->idi_vaddr != NULL) {
1433 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1434 dma->idi_vaddr = NULL;
1436 bus_dma_tag_destroy(dma->idi_tag);
1437 dma->idi_tag = NULL;
1441 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1444 iflib_dma_info_t *dmaiter = dmalist;
1446 for (i = 0; i < count; i++, dmaiter++)
1447 iflib_dma_free(*dmaiter);
1451 iflib_fast_intr(void *arg)
1453 iflib_filter_info_t info = arg;
1454 struct grouptask *gtask = info->ifi_task;
1457 DBG_COUNTER_INC(fast_intrs);
1458 if (info->ifi_filter != NULL) {
1459 result = info->ifi_filter(info->ifi_filter_arg);
1460 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1464 GROUPTASK_ENQUEUE(gtask);
1465 return (FILTER_HANDLED);
1469 iflib_fast_intr_rxtx(void *arg)
1471 iflib_filter_info_t info = arg;
1472 struct grouptask *gtask = info->ifi_task;
1474 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1477 int i, cidx, result;
1479 bool intr_enable, intr_legacy;
1481 DBG_COUNTER_INC(fast_intrs);
1482 if (info->ifi_filter != NULL) {
1483 result = info->ifi_filter(info->ifi_filter_arg);
1484 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1489 sc = ctx->ifc_softc;
1490 intr_enable = false;
1491 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1492 MPASS(rxq->ifr_ntxqirq);
1493 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1494 txqid = rxq->ifr_txqid[i];
1495 txq = &ctx->ifc_txqs[txqid];
1496 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1497 BUS_DMASYNC_POSTREAD);
1498 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1502 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1505 GROUPTASK_ENQUEUE(&txq->ift_task);
1507 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1508 cidx = rxq->ifr_cq_cidx;
1510 cidx = rxq->ifr_fl[0].ifl_cidx;
1511 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1512 GROUPTASK_ENQUEUE(gtask);
1517 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1518 DBG_COUNTER_INC(rx_intr_enables);
1521 IFDI_INTR_ENABLE(ctx);
1522 return (FILTER_HANDLED);
1526 iflib_fast_intr_ctx(void *arg)
1528 iflib_filter_info_t info = arg;
1529 struct grouptask *gtask = info->ifi_task;
1532 DBG_COUNTER_INC(fast_intrs);
1533 if (info->ifi_filter != NULL) {
1534 result = info->ifi_filter(info->ifi_filter_arg);
1535 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1539 GROUPTASK_ENQUEUE(gtask);
1540 return (FILTER_HANDLED);
1544 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1545 driver_filter_t filter, driver_intr_t handler, void *arg,
1548 struct resource *res;
1550 device_t dev = ctx->ifc_dev;
1554 if (ctx->ifc_flags & IFC_LEGACY)
1555 flags |= RF_SHAREABLE;
1558 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1561 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1565 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1566 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1567 filter, handler, arg, &tag);
1570 "failed to setup interrupt for rid %d, name %s: %d\n",
1571 rid, name ? name : "unknown", rc);
1574 bus_describe_intr(dev, res, tag, "%s", name);
1580 /*********************************************************************
1582 * Allocate DMA resources for TX buffers as well as memory for the TX
1583 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1584 * iflib_sw_tx_desc_array structure, storing all the information that
1585 * is needed to transmit a packet on the wire. This is called only
1586 * once at attach, setup is done every reset.
1588 **********************************************************************/
1590 iflib_txsd_alloc(iflib_txq_t txq)
1592 if_ctx_t ctx = txq->ift_ctx;
1593 if_shared_ctx_t sctx = ctx->ifc_sctx;
1594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1595 device_t dev = ctx->ifc_dev;
1596 bus_size_t tsomaxsize;
1597 int err, nsegments, ntsosegments;
1600 nsegments = scctx->isc_tx_nsegments;
1601 ntsosegments = scctx->isc_tx_tso_segments_max;
1602 tsomaxsize = scctx->isc_tx_tso_size_max;
1603 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1604 tsomaxsize += sizeof(struct ether_vlan_header);
1605 MPASS(scctx->isc_ntxd[0] > 0);
1606 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1607 MPASS(nsegments > 0);
1608 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1609 MPASS(ntsosegments > 0);
1610 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1614 * Set up DMA tags for TX buffers.
1616 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1617 1, 0, /* alignment, bounds */
1618 BUS_SPACE_MAXADDR, /* lowaddr */
1619 BUS_SPACE_MAXADDR, /* highaddr */
1620 NULL, NULL, /* filter, filterarg */
1621 sctx->isc_tx_maxsize, /* maxsize */
1622 nsegments, /* nsegments */
1623 sctx->isc_tx_maxsegsize, /* maxsegsize */
1625 NULL, /* lockfunc */
1626 NULL, /* lockfuncarg */
1627 &txq->ift_buf_tag))) {
1628 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1629 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1630 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1633 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1634 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1635 1, 0, /* alignment, bounds */
1636 BUS_SPACE_MAXADDR, /* lowaddr */
1637 BUS_SPACE_MAXADDR, /* highaddr */
1638 NULL, NULL, /* filter, filterarg */
1639 tsomaxsize, /* maxsize */
1640 ntsosegments, /* nsegments */
1641 sctx->isc_tso_maxsegsize,/* maxsegsize */
1643 NULL, /* lockfunc */
1644 NULL, /* lockfuncarg */
1645 &txq->ift_tso_buf_tag))) {
1646 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1651 /* Allocate memory for the TX mbuf map. */
1652 if (!(txq->ift_sds.ifsd_m =
1653 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1654 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1655 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1661 * Create the DMA maps for TX buffers.
1663 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1664 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1665 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1667 "Unable to allocate TX buffer DMA map memory\n");
1671 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1672 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1673 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1675 "Unable to allocate TSO TX buffer map memory\n");
1679 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1680 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1681 &txq->ift_sds.ifsd_map[i]);
1683 device_printf(dev, "Unable to create TX DMA map\n");
1688 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1689 &txq->ift_sds.ifsd_tso_map[i]);
1691 device_printf(dev, "Unable to create TSO TX DMA map\n");
1697 /* We free all, it handles case where we are in the middle */
1698 iflib_tx_structures_free(ctx);
1703 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1707 if (txq->ift_sds.ifsd_map != NULL) {
1708 map = txq->ift_sds.ifsd_map[i];
1709 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1710 bus_dmamap_unload(txq->ift_buf_tag, map);
1711 bus_dmamap_destroy(txq->ift_buf_tag, map);
1712 txq->ift_sds.ifsd_map[i] = NULL;
1715 if (txq->ift_sds.ifsd_tso_map != NULL) {
1716 map = txq->ift_sds.ifsd_tso_map[i];
1717 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1718 BUS_DMASYNC_POSTWRITE);
1719 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1720 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1721 txq->ift_sds.ifsd_tso_map[i] = NULL;
1726 iflib_txq_destroy(iflib_txq_t txq)
1728 if_ctx_t ctx = txq->ift_ctx;
1730 for (int i = 0; i < txq->ift_size; i++)
1731 iflib_txsd_destroy(ctx, txq, i);
1733 if (txq->ift_br != NULL) {
1734 ifmp_ring_free(txq->ift_br);
1738 mtx_destroy(&txq->ift_mtx);
1740 if (txq->ift_sds.ifsd_map != NULL) {
1741 free(txq->ift_sds.ifsd_map, M_IFLIB);
1742 txq->ift_sds.ifsd_map = NULL;
1744 if (txq->ift_sds.ifsd_tso_map != NULL) {
1745 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1746 txq->ift_sds.ifsd_tso_map = NULL;
1748 if (txq->ift_sds.ifsd_m != NULL) {
1749 free(txq->ift_sds.ifsd_m, M_IFLIB);
1750 txq->ift_sds.ifsd_m = NULL;
1752 if (txq->ift_buf_tag != NULL) {
1753 bus_dma_tag_destroy(txq->ift_buf_tag);
1754 txq->ift_buf_tag = NULL;
1756 if (txq->ift_tso_buf_tag != NULL) {
1757 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1758 txq->ift_tso_buf_tag = NULL;
1760 if (txq->ift_ifdi != NULL) {
1761 free(txq->ift_ifdi, M_IFLIB);
1766 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1770 mp = &txq->ift_sds.ifsd_m[i];
1774 if (txq->ift_sds.ifsd_map != NULL) {
1775 bus_dmamap_sync(txq->ift_buf_tag,
1776 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1777 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1779 if (txq->ift_sds.ifsd_tso_map != NULL) {
1780 bus_dmamap_sync(txq->ift_tso_buf_tag,
1781 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1782 bus_dmamap_unload(txq->ift_tso_buf_tag,
1783 txq->ift_sds.ifsd_tso_map[i]);
1786 DBG_COUNTER_INC(tx_frees);
1791 iflib_txq_setup(iflib_txq_t txq)
1793 if_ctx_t ctx = txq->ift_ctx;
1794 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1795 if_shared_ctx_t sctx = ctx->ifc_sctx;
1796 iflib_dma_info_t di;
1799 /* Set number of descriptors available */
1800 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1801 /* XXX make configurable */
1802 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1805 txq->ift_cidx_processed = 0;
1806 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1807 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1809 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1810 bzero((void *)di->idi_vaddr, di->idi_size);
1812 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1813 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1814 bus_dmamap_sync(di->idi_tag, di->idi_map,
1815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1819 /*********************************************************************
1821 * Allocate DMA resources for RX buffers as well as memory for the RX
1822 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1823 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1824 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1825 * Since we use use one entry in iflib_sw_rx_desc_array per received
1826 * packet, the maximum number of entries we'll need is equal to the
1827 * number of hardware receive descriptors that we've allocated.
1829 **********************************************************************/
1831 iflib_rxsd_alloc(iflib_rxq_t rxq)
1833 if_ctx_t ctx = rxq->ifr_ctx;
1834 if_shared_ctx_t sctx = ctx->ifc_sctx;
1835 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1836 device_t dev = ctx->ifc_dev;
1840 MPASS(scctx->isc_nrxd[0] > 0);
1841 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1844 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1845 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1846 /* Set up DMA tag for RX buffers. */
1847 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1848 1, 0, /* alignment, bounds */
1849 BUS_SPACE_MAXADDR, /* lowaddr */
1850 BUS_SPACE_MAXADDR, /* highaddr */
1851 NULL, NULL, /* filter, filterarg */
1852 sctx->isc_rx_maxsize, /* maxsize */
1853 sctx->isc_rx_nsegments, /* nsegments */
1854 sctx->isc_rx_maxsegsize, /* maxsegsize */
1856 NULL, /* lockfunc */
1861 "Unable to allocate RX DMA tag: %d\n", err);
1865 /* Allocate memory for the RX mbuf map. */
1866 if (!(fl->ifl_sds.ifsd_m =
1867 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1868 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1870 "Unable to allocate RX mbuf map memory\n");
1875 /* Allocate memory for the direct RX cluster pointer map. */
1876 if (!(fl->ifl_sds.ifsd_cl =
1877 (caddr_t *) malloc(sizeof(caddr_t) *
1878 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1880 "Unable to allocate RX cluster map memory\n");
1885 /* Allocate memory for the RX cluster bus address map. */
1886 if (!(fl->ifl_sds.ifsd_ba =
1887 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1888 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1890 "Unable to allocate RX bus address map memory\n");
1896 * Create the DMA maps for RX buffers.
1898 if (!(fl->ifl_sds.ifsd_map =
1899 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1901 "Unable to allocate RX buffer DMA map memory\n");
1905 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1906 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1907 &fl->ifl_sds.ifsd_map[i]);
1909 device_printf(dev, "Unable to create RX buffer DMA map\n");
1917 iflib_rx_structures_free(ctx);
1922 * Internal service routines
1925 struct rxq_refill_cb_arg {
1927 bus_dma_segment_t seg;
1932 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1934 struct rxq_refill_cb_arg *cb_arg = arg;
1936 cb_arg->error = error;
1937 cb_arg->seg = segs[0];
1938 cb_arg->nseg = nseg;
1942 * iflib_fl_refill - refill an rxq free-buffer list
1943 * @ctx: the iflib context
1944 * @fl: the free list to refill
1945 * @count: the number of new buffers to allocate
1947 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1948 * The caller must assure that @count does not exceed the queue's capacity
1949 * minus one (since we always leave a descriptor unavailable).
1952 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1954 struct if_rxd_update iru;
1955 struct rxq_refill_cb_arg cb_arg;
1959 bus_dmamap_t *sd_map;
1960 bus_addr_t bus_addr, *sd_ba;
1961 int err, frag_idx, i, idx, n, pidx;
1964 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
1966 sd_m = fl->ifl_sds.ifsd_m;
1967 sd_map = fl->ifl_sds.ifsd_map;
1968 sd_cl = fl->ifl_sds.ifsd_cl;
1969 sd_ba = fl->ifl_sds.ifsd_ba;
1970 pidx = fl->ifl_pidx;
1972 frag_idx = fl->ifl_fragidx;
1973 credits = fl->ifl_credits;
1978 MPASS(credits + n <= fl->ifl_size);
1980 if (pidx < fl->ifl_cidx)
1981 MPASS(pidx + n <= fl->ifl_cidx);
1982 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1983 MPASS(fl->ifl_gen == 0);
1984 if (pidx > fl->ifl_cidx)
1985 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1987 DBG_COUNTER_INC(fl_refills);
1989 DBG_COUNTER_INC(fl_refills_large);
1990 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1993 * We allocate an uninitialized mbuf + cluster, mbuf is
1994 * initialized after rx.
1996 * If the cluster is still set then we know a minimum sized
1997 * packet was received
1999 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2002 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2003 MPASS(frag_idx >= 0);
2004 if ((cl = sd_cl[frag_idx]) == NULL) {
2005 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2006 if (__predict_false(cl == NULL))
2010 MPASS(sd_map != NULL);
2011 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2012 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2014 if (__predict_false(err != 0 || cb_arg.error)) {
2015 uma_zfree(fl->ifl_zone, cl);
2019 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2020 sd_cl[frag_idx] = cl;
2022 fl->ifl_cl_enqueued++;
2025 bus_addr = sd_ba[frag_idx];
2027 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2028 BUS_DMASYNC_PREREAD);
2030 if (sd_m[frag_idx] == NULL) {
2031 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2032 if (__predict_false(m == NULL))
2036 bit_set(fl->ifl_rx_bitmap, frag_idx);
2038 fl->ifl_m_enqueued++;
2041 DBG_COUNTER_INC(rx_allocs);
2042 fl->ifl_rxd_idxs[i] = frag_idx;
2043 fl->ifl_bus_addrs[i] = bus_addr;
2046 MPASS(credits <= fl->ifl_size);
2047 if (++idx == fl->ifl_size) {
2053 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2054 iru.iru_pidx = pidx;
2056 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2058 fl->ifl_credits = credits;
2064 if (n < count - 1) {
2066 iru.iru_pidx = pidx;
2068 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2070 fl->ifl_credits = credits;
2072 DBG_COUNTER_INC(rxd_flush);
2073 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2074 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2075 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2076 fl->ifl_id, fl->ifl_pidx);
2077 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2078 fl->ifl_fragidx = frag_idx + 1;
2079 if (fl->ifl_fragidx == fl->ifl_size)
2080 fl->ifl_fragidx = 0;
2082 fl->ifl_fragidx = frag_idx;
2086 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2089 static inline uint8_t
2090 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2093 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2094 * This is important as it confuses most NICs. For instance,
2095 * Intel NICs have (per receive ring) RDH and RDT registers, where
2096 * RDH points to the next receive descriptor to be used by the NIC,
2097 * and RDT for the next receive descriptor to be published by the
2098 * driver to the NIC (RDT - 1 is thus the last valid one).
2099 * The condition RDH == RDT means no descriptors are available to
2100 * the NIC, and thus it would be ambiguous if it also meant that
2101 * all the descriptors are available to the NIC.
2103 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2105 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2108 MPASS(fl->ifl_credits <= fl->ifl_size);
2109 MPASS(reclaimable == delta);
2111 if (reclaimable > 0)
2112 return (iflib_fl_refill(ctx, fl, reclaimable));
2117 iflib_in_detach(if_ctx_t ctx)
2122 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2128 iflib_fl_bufs_free(iflib_fl_t fl)
2130 iflib_dma_info_t idi = fl->ifl_ifdi;
2131 bus_dmamap_t sd_map;
2134 for (i = 0; i < fl->ifl_size; i++) {
2135 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2136 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2138 if (*sd_cl != NULL) {
2139 sd_map = fl->ifl_sds.ifsd_map[i];
2140 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2141 BUS_DMASYNC_POSTREAD);
2142 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2143 uma_zfree(fl->ifl_zone, *sd_cl);
2145 if (*sd_m != NULL) {
2146 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2147 uma_zfree(zone_mbuf, *sd_m);
2151 MPASS(*sd_m == NULL);
2154 fl->ifl_m_dequeued++;
2155 fl->ifl_cl_dequeued++;
2159 for (i = 0; i < fl->ifl_size; i++) {
2160 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2161 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2165 * Reset free list values
2167 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2168 bzero(idi->idi_vaddr, idi->idi_size);
2171 /*********************************************************************
2173 * Initialize a free list and its buffers.
2175 **********************************************************************/
2177 iflib_fl_setup(iflib_fl_t fl)
2179 iflib_rxq_t rxq = fl->ifl_rxq;
2180 if_ctx_t ctx = rxq->ifr_ctx;
2181 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2184 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2186 ** Free current RX buffer structs and their mbufs
2188 iflib_fl_bufs_free(fl);
2189 /* Now replenish the mbufs */
2190 MPASS(fl->ifl_credits == 0);
2191 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2192 if (scctx->isc_rxd_buf_size[qidx] != 0)
2193 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2195 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2197 * ifl_buf_size may be a driver-supplied value, so pull it up
2198 * to the selected mbuf size.
2200 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2201 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2202 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2203 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2204 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2207 * Avoid pre-allocating zillions of clusters to an idle card
2208 * potentially speeding up attach. In any case make sure
2209 * to leave a descriptor unavailable. See the comment in
2210 * iflib_fl_refill_all().
2212 MPASS(fl->ifl_size > 0);
2213 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2214 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2220 MPASS(fl->ifl_ifdi != NULL);
2221 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2222 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2226 /*********************************************************************
2228 * Free receive ring data structures
2230 **********************************************************************/
2232 iflib_rx_sds_free(iflib_rxq_t rxq)
2237 if (rxq->ifr_fl != NULL) {
2238 for (i = 0; i < rxq->ifr_nfl; i++) {
2239 fl = &rxq->ifr_fl[i];
2240 if (fl->ifl_buf_tag != NULL) {
2241 if (fl->ifl_sds.ifsd_map != NULL) {
2242 for (j = 0; j < fl->ifl_size; j++) {
2245 fl->ifl_sds.ifsd_map[j],
2246 BUS_DMASYNC_POSTREAD);
2249 fl->ifl_sds.ifsd_map[j]);
2252 fl->ifl_sds.ifsd_map[j]);
2255 bus_dma_tag_destroy(fl->ifl_buf_tag);
2256 fl->ifl_buf_tag = NULL;
2258 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2259 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2260 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2261 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2262 fl->ifl_sds.ifsd_m = NULL;
2263 fl->ifl_sds.ifsd_cl = NULL;
2264 fl->ifl_sds.ifsd_ba = NULL;
2265 fl->ifl_sds.ifsd_map = NULL;
2267 free(rxq->ifr_fl, M_IFLIB);
2269 free(rxq->ifr_ifdi, M_IFLIB);
2270 rxq->ifr_ifdi = NULL;
2271 rxq->ifr_cq_cidx = 0;
2279 iflib_timer(void *arg)
2281 iflib_txq_t txq = arg;
2282 if_ctx_t ctx = txq->ift_ctx;
2283 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2284 uint64_t this_tick = ticks;
2286 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2290 ** Check on the state of the TX queue(s), this
2291 ** can be done without the lock because its RO
2292 ** and the HUNG state will be static if set.
2294 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2295 txq->ift_last_timer_tick = this_tick;
2296 IFDI_TIMER(ctx, txq->ift_id);
2297 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2298 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2299 (sctx->isc_pause_frames == 0)))
2302 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2303 ifmp_ring_is_stalled(txq->ift_br)) {
2304 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2305 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2307 txq->ift_cleaned_prev = txq->ift_cleaned;
2309 /* handle any laggards */
2310 if (txq->ift_db_pending)
2311 GROUPTASK_ENQUEUE(&txq->ift_task);
2313 sctx->isc_pause_frames = 0;
2314 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2315 callout_reset_on(&txq->ift_timer, hz / 2, iflib_timer, txq, txq->ift_timer.c_cpu);
2319 device_printf(ctx->ifc_dev,
2320 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2321 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2323 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2324 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2325 iflib_admin_intr_deferred(ctx);
2330 iflib_get_mbuf_size_for(unsigned int size)
2333 if (size <= MCLBYTES)
2336 return (MJUMPAGESIZE);
2340 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2342 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2345 * XXX don't set the max_frame_size to larger
2346 * than the hardware can handle
2348 ctx->ifc_rx_mbuf_sz =
2349 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2353 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2356 return (ctx->ifc_rx_mbuf_sz);
2360 iflib_init_locked(if_ctx_t ctx)
2362 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2363 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2364 if_t ifp = ctx->ifc_ifp;
2368 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2370 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2371 IFDI_INTR_DISABLE(ctx);
2373 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2374 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2375 /* Set hardware offload abilities */
2376 if_clearhwassist(ifp);
2377 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2378 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2379 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2380 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2381 if (if_getcapenable(ifp) & IFCAP_TSO4)
2382 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2383 if (if_getcapenable(ifp) & IFCAP_TSO6)
2384 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2386 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2388 callout_stop(&txq->ift_timer);
2390 callout_stop(&txq->ift_netmap_timer);
2391 #endif /* DEV_NETMAP */
2392 CALLOUT_UNLOCK(txq);
2393 iflib_netmap_txq_init(ctx, txq);
2397 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2398 * that drivers can use the value when setting up the hardware receive
2401 iflib_calc_rx_mbuf_sz(ctx);
2404 i = if_getdrvflags(ifp);
2407 MPASS(if_getdrvflags(ifp) == i);
2408 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2409 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2410 /* This rxq is in netmap mode. Skip normal init. */
2413 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2414 if (iflib_fl_setup(fl)) {
2415 device_printf(ctx->ifc_dev,
2416 "setting up free list %d failed - "
2417 "check cluster settings\n", j);
2423 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2424 IFDI_INTR_ENABLE(ctx);
2425 txq = ctx->ifc_txqs;
2426 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2427 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2428 txq->ift_timer.c_cpu);
2432 iflib_media_change(if_t ifp)
2434 if_ctx_t ctx = if_getsoftc(ifp);
2438 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2439 iflib_init_locked(ctx);
2445 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2447 if_ctx_t ctx = if_getsoftc(ifp);
2450 IFDI_UPDATE_ADMIN_STATUS(ctx);
2451 IFDI_MEDIA_STATUS(ctx, ifmr);
2456 iflib_stop(if_ctx_t ctx)
2458 iflib_txq_t txq = ctx->ifc_txqs;
2459 iflib_rxq_t rxq = ctx->ifc_rxqs;
2460 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2461 if_shared_ctx_t sctx = ctx->ifc_sctx;
2462 iflib_dma_info_t di;
2466 /* Tell the stack that the interface is no longer active */
2467 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2469 IFDI_INTR_DISABLE(ctx);
2474 iflib_debug_reset();
2475 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2476 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2477 /* make sure all transmitters have completed before proceeding XXX */
2480 callout_stop(&txq->ift_timer);
2482 callout_stop(&txq->ift_netmap_timer);
2483 #endif /* DEV_NETMAP */
2484 CALLOUT_UNLOCK(txq);
2486 /* clean any enqueued buffers */
2487 iflib_ifmp_purge(txq);
2488 /* Free any existing tx buffers. */
2489 for (j = 0; j < txq->ift_size; j++) {
2490 iflib_txsd_free(ctx, txq, j);
2492 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2493 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2494 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2495 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2496 txq->ift_pullups = 0;
2497 ifmp_ring_reset_stats(txq->ift_br);
2498 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2499 bzero((void *)di->idi_vaddr, di->idi_size);
2501 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2502 /* make sure all transmitters have completed before proceeding XXX */
2504 rxq->ifr_cq_cidx = 0;
2505 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2506 bzero((void *)di->idi_vaddr, di->idi_size);
2507 /* also resets the free lists pidx/cidx */
2508 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2509 iflib_fl_bufs_free(fl);
2513 static inline caddr_t
2514 calc_next_rxd(iflib_fl_t fl, int cidx)
2518 caddr_t start, end, cur, next;
2520 nrxd = fl->ifl_size;
2521 size = fl->ifl_rxd_size;
2522 start = fl->ifl_ifdi->idi_vaddr;
2524 if (__predict_false(size == 0))
2526 cur = start + size*cidx;
2527 end = start + size*nrxd;
2528 next = CACHE_PTR_NEXT(cur);
2529 return (next < end ? next : start);
2533 prefetch_pkts(iflib_fl_t fl, int cidx)
2536 int nrxd = fl->ifl_size;
2539 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2540 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2541 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2542 next_rxd = calc_next_rxd(fl, cidx);
2544 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2545 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2546 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2547 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2548 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2549 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2550 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2551 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2554 static struct mbuf *
2555 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2556 int *pf_rv, if_rxd_info_t ri)
2562 int flid, cidx, len, next;
2565 flid = irf->irf_flid;
2566 cidx = irf->irf_idx;
2567 fl = &rxq->ifr_fl[flid];
2569 m = fl->ifl_sds.ifsd_m[cidx];
2570 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2573 fl->ifl_m_dequeued++;
2575 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2576 prefetch_pkts(fl, cidx);
2577 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2578 prefetch(&fl->ifl_sds.ifsd_map[next]);
2579 map = fl->ifl_sds.ifsd_map[cidx];
2581 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2583 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2584 irf->irf_len != 0) {
2585 payload = *sd->ifsd_cl;
2586 payload += ri->iri_pad;
2587 len = ri->iri_len - ri->iri_pad;
2588 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2589 len | PFIL_MEMPTR | PFIL_IN, NULL);
2594 * The filter ate it. Everything is recycled.
2599 case PFIL_REALLOCED:
2601 * The filter copied it. Everything is recycled.
2603 m = pfil_mem2mbuf(payload);
2608 * Filter said it was OK, so receive like
2611 fl->ifl_sds.ifsd_m[cidx] = NULL;
2617 fl->ifl_sds.ifsd_m[cidx] = NULL;
2621 if (unload && irf->irf_len != 0)
2622 bus_dmamap_unload(fl->ifl_buf_tag, map);
2623 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2624 if (__predict_false(fl->ifl_cidx == 0))
2626 bit_clear(fl->ifl_rx_bitmap, cidx);
2630 static struct mbuf *
2631 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2633 struct mbuf *m, *mh, *mt;
2635 int *pf_rv_ptr, flags, i, padlen;
2644 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2647 MPASS(*sd->ifsd_cl != NULL);
2650 * Exclude zero-length frags & frags from
2651 * packets the filter has consumed or dropped
2653 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2654 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2656 /* everything saved here */
2661 /* XXX we can save the cluster here, but not the mbuf */
2662 m_init(m, M_NOWAIT, MT_DATA, 0);
2667 flags = M_PKTHDR|M_EXT;
2669 padlen = ri->iri_pad;
2674 /* assuming padding is only on the first fragment */
2678 *sd->ifsd_cl = NULL;
2680 /* Can these two be made one ? */
2681 m_init(m, M_NOWAIT, MT_DATA, flags);
2682 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2684 * These must follow m_init and m_cljset
2686 m->m_data += padlen;
2687 ri->iri_len -= padlen;
2688 m->m_len = ri->iri_frags[i].irf_len;
2689 } while (++i < ri->iri_nfrags);
2695 * Process one software descriptor
2697 static struct mbuf *
2698 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2704 /* should I merge this back in now that the two paths are basically duplicated? */
2705 if (ri->iri_nfrags == 1 &&
2706 ri->iri_frags[0].irf_len != 0 &&
2707 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2708 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2710 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2712 if (pf_rv == PFIL_PASS) {
2713 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2714 #ifndef __NO_STRICT_ALIGNMENT
2718 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2719 m->m_len = ri->iri_frags[0].irf_len;
2722 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2725 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2728 m->m_pkthdr.len = ri->iri_len;
2729 m->m_pkthdr.rcvif = ri->iri_ifp;
2730 m->m_flags |= ri->iri_flags;
2731 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2732 m->m_pkthdr.flowid = ri->iri_flowid;
2733 M_HASHTYPE_SET(m, ri->iri_rsstype);
2734 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2735 m->m_pkthdr.csum_data = ri->iri_csum_data;
2739 #if defined(INET6) || defined(INET)
2741 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2743 CURVNET_SET(lc->ifp->if_vnet);
2745 *v6 = V_ip6_forwarding;
2748 *v4 = V_ipforwarding;
2754 * Returns true if it's possible this packet could be LROed.
2755 * if it returns false, it is guaranteed that tcp_lro_rx()
2756 * would not return zero.
2759 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2761 struct ether_header *eh;
2763 eh = mtod(m, struct ether_header *);
2764 switch (eh->ether_type) {
2766 case htons(ETHERTYPE_IPV6):
2767 return (!v6_forwarding);
2770 case htons(ETHERTYPE_IP):
2771 return (!v4_forwarding);
2779 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2785 _task_fn_rx_watchdog(void *context)
2787 iflib_rxq_t rxq = context;
2789 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2793 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2796 if_ctx_t ctx = rxq->ifr_ctx;
2797 if_shared_ctx_t sctx = ctx->ifc_sctx;
2798 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2801 struct if_rxd_info ri;
2802 int err, budget_left, rx_bytes, rx_pkts;
2805 bool v4_forwarding, v6_forwarding, lro_possible;
2809 * XXX early demux data packets so that if_input processing only handles
2810 * acks in interrupt context
2812 struct mbuf *m, *mh, *mt, *mf;
2816 lro_possible = v4_forwarding = v6_forwarding = false;
2820 rx_pkts = rx_bytes = 0;
2821 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2822 cidxp = &rxq->ifr_cq_cidx;
2824 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2825 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2826 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2827 retval |= iflib_fl_refill_all(ctx, fl);
2828 DBG_COUNTER_INC(rx_unavail);
2832 /* pfil needs the vnet to be set */
2833 CURVNET_SET_QUIET(ifp->if_vnet);
2834 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2835 if (__predict_false(!CTX_ACTIVE(ctx))) {
2836 DBG_COUNTER_INC(rx_ctx_inactive);
2840 * Reset client set fields to their default values
2843 ri.iri_qsidx = rxq->ifr_id;
2844 ri.iri_cidx = *cidxp;
2846 ri.iri_frags = rxq->ifr_frags;
2847 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2852 rx_bytes += ri.iri_len;
2853 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2854 *cidxp = ri.iri_cidx;
2855 /* Update our consumer index */
2856 /* XXX NB: shurd - check if this is still safe */
2857 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2858 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2859 /* was this only a completion queue message? */
2860 if (__predict_false(ri.iri_nfrags == 0))
2863 MPASS(ri.iri_nfrags != 0);
2864 MPASS(ri.iri_len != 0);
2866 /* will advance the cidx on the corresponding free lists */
2867 m = iflib_rxd_pkt_get(rxq, &ri);
2870 if (avail == 0 && budget_left)
2871 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2873 if (__predict_false(m == NULL))
2876 /* imm_pkt: -- cxgb */
2885 /* make sure that we can refill faster than drain */
2886 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2887 retval |= iflib_fl_refill_all(ctx, fl);
2889 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2891 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2893 while (mh != NULL) {
2896 m->m_nextpkt = NULL;
2897 #ifndef __NO_STRICT_ALIGNMENT
2898 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2901 rx_bytes += m->m_pkthdr.len;
2903 #if defined(INET6) || defined(INET)
2905 if (!lro_possible) {
2906 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2907 if (lro_possible && mf != NULL) {
2908 ifp->if_input(ifp, mf);
2909 DBG_COUNTER_INC(rx_if_input);
2913 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2914 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2915 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2921 ifp->if_input(ifp, m);
2922 DBG_COUNTER_INC(rx_if_input);
2933 ifp->if_input(ifp, mf);
2934 DBG_COUNTER_INC(rx_if_input);
2937 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2938 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2941 * Flush any outstanding LRO work
2943 #if defined(INET6) || defined(INET)
2944 tcp_lro_flush_all(&rxq->ifr_lc);
2946 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2947 retval |= IFLIB_RXEOF_MORE;
2951 ctx->ifc_flags |= IFC_DO_RESET;
2952 iflib_admin_intr_deferred(ctx);
2957 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2958 static inline qidx_t
2959 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2961 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2962 qidx_t minthresh = txq->ift_size / 8;
2963 if (in_use > 4*minthresh)
2964 return (notify_count);
2965 if (in_use > 2*minthresh)
2966 return (notify_count >> 1);
2967 if (in_use > minthresh)
2968 return (notify_count >> 3);
2972 static inline qidx_t
2973 txq_max_rs_deferred(iflib_txq_t txq)
2975 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2976 qidx_t minthresh = txq->ift_size / 8;
2977 if (txq->ift_in_use > 4*minthresh)
2978 return (notify_count);
2979 if (txq->ift_in_use > 2*minthresh)
2980 return (notify_count >> 1);
2981 if (txq->ift_in_use > minthresh)
2982 return (notify_count >> 2);
2986 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2987 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2989 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2990 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2991 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2993 /* forward compatibility for cxgb */
2994 #define FIRST_QSET(ctx) 0
2995 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2996 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2997 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2998 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3000 /* XXX we should be setting this to something other than zero */
3001 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3002 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3003 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3006 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
3012 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
3013 if (ring || txq->ift_db_pending >= max) {
3014 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3015 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3016 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3017 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3018 txq->ift_db_pending = txq->ift_npending = 0;
3026 print_pkt(if_pkt_info_t pi)
3028 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3029 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3030 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3031 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3032 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3033 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3037 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3038 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3039 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3040 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3043 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3045 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3046 struct ether_vlan_header *eh;
3050 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3051 M_WRITABLE(m) == 0) {
3052 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3056 DBG_COUNTER_INC(tx_frees);
3062 * Determine where frame payload starts.
3063 * Jump over vlan headers if already present,
3064 * helpful for QinQ too.
3066 if (__predict_false(m->m_len < sizeof(*eh))) {
3068 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3071 eh = mtod(m, struct ether_vlan_header *);
3072 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3073 pi->ipi_etype = ntohs(eh->evl_proto);
3074 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3076 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3077 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3080 switch (pi->ipi_etype) {
3085 struct ip *ip = NULL;
3086 struct tcphdr *th = NULL;
3089 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3090 if (__predict_false(m->m_len < minthlen)) {
3092 * if this code bloat is causing too much of a hit
3093 * move it to a separate function and mark it noinline
3095 if (m->m_len == pi->ipi_ehdrlen) {
3098 if (n->m_len >= sizeof(*ip)) {
3099 ip = (struct ip *)n->m_data;
3100 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3101 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3104 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3106 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3110 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3112 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3113 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3114 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3117 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3118 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3119 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3121 pi->ipi_ip_hlen = ip->ip_hl << 2;
3122 pi->ipi_ipproto = ip->ip_p;
3123 pi->ipi_flags |= IPI_TX_IPV4;
3125 /* TCP checksum offload may require TCP header length */
3126 if (IS_TX_OFFLOAD4(pi)) {
3127 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3128 if (__predict_false(th == NULL)) {
3130 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3132 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3134 pi->ipi_tcp_hflags = th->th_flags;
3135 pi->ipi_tcp_hlen = th->th_off << 2;
3136 pi->ipi_tcp_seq = th->th_seq;
3139 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3142 * TSO always requires hardware checksum offload.
3144 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3145 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3146 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3147 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3148 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3150 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3154 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3161 case ETHERTYPE_IPV6:
3163 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3165 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3167 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3169 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3172 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3174 /* XXX-BZ this will go badly in case of ext hdrs. */
3175 pi->ipi_ipproto = ip6->ip6_nxt;
3176 pi->ipi_flags |= IPI_TX_IPV6;
3178 /* TCP checksum offload may require TCP header length */
3179 if (IS_TX_OFFLOAD6(pi)) {
3180 if (pi->ipi_ipproto == IPPROTO_TCP) {
3181 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3183 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3186 pi->ipi_tcp_hflags = th->th_flags;
3187 pi->ipi_tcp_hlen = th->th_off << 2;
3188 pi->ipi_tcp_seq = th->th_seq;
3191 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3194 * TSO always requires hardware checksum offload.
3196 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3197 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3198 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3205 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3206 pi->ipi_ip_hlen = 0;
3215 * If dodgy hardware rejects the scatter gather chain we've handed it
3216 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3219 static __noinline struct mbuf *
3220 iflib_remove_mbuf(iflib_txq_t txq)
3223 struct mbuf *m, **ifsd_m;
3225 ifsd_m = txq->ift_sds.ifsd_m;
3226 ntxd = txq->ift_size;
3227 pidx = txq->ift_pidx & (ntxd - 1);
3228 ifsd_m = txq->ift_sds.ifsd_m;
3230 ifsd_m[pidx] = NULL;
3231 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3232 if (txq->ift_sds.ifsd_tso_map != NULL)
3233 bus_dmamap_unload(txq->ift_tso_buf_tag,
3234 txq->ift_sds.ifsd_tso_map[pidx]);
3236 txq->ift_dequeued++;
3241 static inline caddr_t
3242 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3246 caddr_t start, end, cur, next;
3248 ntxd = txq->ift_size;
3249 size = txq->ift_txd_size[qid];
3250 start = txq->ift_ifdi[qid].idi_vaddr;
3252 if (__predict_false(size == 0))
3254 cur = start + size*cidx;
3255 end = start + size*ntxd;
3256 next = CACHE_PTR_NEXT(cur);
3257 return (next < end ? next : start);
3261 * Pad an mbuf to ensure a minimum ethernet frame size.
3262 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3264 static __noinline int
3265 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3268 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3269 * and ARP message is the smallest common payload I can think of
3271 static char pad[18]; /* just zeros */
3273 struct mbuf *new_head;
3275 if (!M_WRITABLE(*m_head)) {
3276 new_head = m_dup(*m_head, M_NOWAIT);
3277 if (new_head == NULL) {
3279 device_printf(dev, "cannot pad short frame, m_dup() failed");
3280 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3281 DBG_COUNTER_INC(tx_frees);
3288 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3289 n > 0; n -= sizeof(pad))
3290 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3295 device_printf(dev, "cannot pad short frame\n");
3296 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3297 DBG_COUNTER_INC(tx_frees);
3305 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3308 if_shared_ctx_t sctx;
3309 if_softc_ctx_t scctx;
3310 bus_dma_tag_t buf_tag;
3311 bus_dma_segment_t *segs;
3312 struct mbuf *m_head, **ifsd_m;
3315 struct if_pkt_info pi;
3317 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3320 sctx = ctx->ifc_sctx;
3321 scctx = &ctx->ifc_softc_ctx;
3322 segs = txq->ift_segs;
3323 ntxd = txq->ift_size;
3328 * If we're doing TSO the next descriptor to clean may be quite far ahead
3330 cidx = txq->ift_cidx;
3331 pidx = txq->ift_pidx;
3332 if (ctx->ifc_flags & IFC_PREFETCH) {
3333 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3334 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3335 next_txd = calc_next_txd(txq, cidx, 0);
3339 /* prefetch the next cache line of mbuf pointers and flags */
3340 prefetch(&txq->ift_sds.ifsd_m[next]);
3341 prefetch(&txq->ift_sds.ifsd_map[next]);
3342 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3344 map = txq->ift_sds.ifsd_map[pidx];
3345 ifsd_m = txq->ift_sds.ifsd_m;
3347 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3348 buf_tag = txq->ift_tso_buf_tag;
3349 max_segs = scctx->isc_tx_tso_segments_max;
3350 map = txq->ift_sds.ifsd_tso_map[pidx];
3351 MPASS(buf_tag != NULL);
3352 MPASS(max_segs > 0);
3354 buf_tag = txq->ift_buf_tag;
3355 max_segs = scctx->isc_tx_nsegments;
3356 map = txq->ift_sds.ifsd_map[pidx];
3358 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3359 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3360 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3362 DBG_COUNTER_INC(encap_txd_encap_fail);
3369 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3371 pi.ipi_qsidx = txq->ift_id;
3372 pi.ipi_len = m_head->m_pkthdr.len;
3373 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3374 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3376 /* deliberate bitwise OR to make one condition */
3377 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3378 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3379 DBG_COUNTER_INC(encap_txd_encap_fail);
3386 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3389 if (__predict_false(err)) {
3392 /* try collapse once and defrag once */
3394 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3395 /* try defrag if collapsing fails */
3400 txq->ift_mbuf_defrag++;
3401 m_head = m_defrag(*m_headp, M_NOWAIT);
3404 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3405 * failed to map an mbuf that was run through m_defrag
3408 if (__predict_false(m_head == NULL || remap > 1))
3415 txq->ift_no_tx_dma_setup++;
3418 txq->ift_no_tx_dma_setup++;
3420 DBG_COUNTER_INC(tx_frees);
3424 txq->ift_map_failed++;
3425 DBG_COUNTER_INC(encap_load_mbuf_fail);
3426 DBG_COUNTER_INC(encap_txd_encap_fail);
3429 ifsd_m[pidx] = m_head;
3431 * XXX assumes a 1 to 1 relationship between segments and
3432 * descriptors - this does not hold true on all drivers, e.g.
3435 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3436 txq->ift_no_desc_avail++;
3437 bus_dmamap_unload(buf_tag, map);
3438 DBG_COUNTER_INC(encap_txq_avail_fail);
3439 DBG_COUNTER_INC(encap_txd_encap_fail);
3440 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3441 GROUPTASK_ENQUEUE(&txq->ift_task);
3445 * On Intel cards we can greatly reduce the number of TX interrupts
3446 * we see by only setting report status on every Nth descriptor.
3447 * However, this also means that the driver will need to keep track
3448 * of the descriptors that RS was set on to check them for the DD bit.
3450 txq->ift_rs_pending += nsegs + 1;
3451 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3452 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3453 pi.ipi_flags |= IPI_TX_INTR;
3454 txq->ift_rs_pending = 0;
3458 pi.ipi_nsegs = nsegs;
3460 MPASS(pidx >= 0 && pidx < txq->ift_size);
3464 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3465 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3466 DBG_COUNTER_INC(tx_encap);
3467 MPASS(pi.ipi_new_pidx < txq->ift_size);
3469 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3470 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3471 ndesc += txq->ift_size;
3475 * drivers can need as many as
3478 MPASS(ndesc <= pi.ipi_nsegs + 2);
3479 MPASS(pi.ipi_new_pidx != pidx);
3481 txq->ift_in_use += ndesc;
3484 * We update the last software descriptor again here because there may
3485 * be a sentinel and/or there may be more mbufs than segments
3487 txq->ift_pidx = pi.ipi_new_pidx;
3488 txq->ift_npending += pi.ipi_ndescs;
3490 *m_headp = m_head = iflib_remove_mbuf(txq);
3492 txq->ift_txd_encap_efbig++;
3501 * err can't possibly be non-zero here, so we don't neet to test it
3502 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3507 txq->ift_mbuf_defrag_failed++;
3508 txq->ift_map_failed++;
3510 DBG_COUNTER_INC(tx_frees);
3512 DBG_COUNTER_INC(encap_txd_encap_fail);
3517 iflib_tx_desc_free(iflib_txq_t txq, int n)
3519 uint32_t qsize, cidx, mask, gen;
3520 struct mbuf *m, **ifsd_m;
3523 cidx = txq->ift_cidx;
3525 qsize = txq->ift_size;
3527 ifsd_m = txq->ift_sds.ifsd_m;
3528 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3532 prefetch(ifsd_m[(cidx + 3) & mask]);
3533 prefetch(ifsd_m[(cidx + 4) & mask]);
3535 if ((m = ifsd_m[cidx]) != NULL) {
3536 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3537 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3538 bus_dmamap_sync(txq->ift_tso_buf_tag,
3539 txq->ift_sds.ifsd_tso_map[cidx],
3540 BUS_DMASYNC_POSTWRITE);
3541 bus_dmamap_unload(txq->ift_tso_buf_tag,
3542 txq->ift_sds.ifsd_tso_map[cidx]);
3544 bus_dmamap_sync(txq->ift_buf_tag,
3545 txq->ift_sds.ifsd_map[cidx],
3546 BUS_DMASYNC_POSTWRITE);
3547 bus_dmamap_unload(txq->ift_buf_tag,
3548 txq->ift_sds.ifsd_map[cidx]);
3550 /* XXX we don't support any drivers that batch packets yet */
3551 MPASS(m->m_nextpkt == NULL);
3553 ifsd_m[cidx] = NULL;
3555 txq->ift_dequeued++;
3557 DBG_COUNTER_INC(tx_frees);
3559 if (__predict_false(++cidx == qsize)) {
3564 txq->ift_cidx = cidx;
3569 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3572 if_ctx_t ctx = txq->ift_ctx;
3574 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3575 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3578 * Need a rate-limiting check so that this isn't called every time
3580 iflib_tx_credits_update(ctx, txq);
3581 reclaim = DESC_RECLAIMABLE(txq);
3583 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3585 if (iflib_verbose_debug) {
3586 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3587 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3593 iflib_tx_desc_free(txq, reclaim);
3594 txq->ift_cleaned += reclaim;
3595 txq->ift_in_use -= reclaim;
3600 static struct mbuf **
3601 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3604 struct mbuf **items;
3607 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3608 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3610 prefetch(items[(cidx + offset) & (size-1)]);
3611 if (remaining > 1) {
3612 prefetch2cachelines(&items[next]);
3613 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3614 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3615 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3617 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3621 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3624 ifmp_ring_check_drainage(txq->ift_br, budget);
3628 iflib_txq_can_drain(struct ifmp_ring *r)
3630 iflib_txq_t txq = r->cookie;
3631 if_ctx_t ctx = txq->ift_ctx;
3633 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3635 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3636 BUS_DMASYNC_POSTREAD);
3637 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3642 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3644 iflib_txq_t txq = r->cookie;
3645 if_ctx_t ctx = txq->ift_ctx;
3646 if_t ifp = ctx->ifc_ifp;
3647 struct mbuf *m, **mp;
3648 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3649 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3650 bool do_prefetch, rang, ring;
3652 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3653 !LINK_ACTIVE(ctx))) {
3654 DBG_COUNTER_INC(txq_drain_notready);
3657 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3658 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3659 avail = IDXDIFF(pidx, cidx, r->size);
3660 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3661 DBG_COUNTER_INC(txq_drain_flushing);
3662 for (i = 0; i < avail; i++) {
3663 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3664 m_freem(r->items[(cidx + i) & (r->size-1)]);
3665 r->items[(cidx + i) & (r->size-1)] = NULL;
3670 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3671 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3673 callout_stop(&txq->ift_timer);
3674 CALLOUT_UNLOCK(txq);
3675 DBG_COUNTER_INC(txq_drain_oactive);
3679 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3680 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3681 count = MIN(avail, TX_BATCH_SIZE);
3683 if (iflib_verbose_debug)
3684 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3685 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3687 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3688 txq_avail = TXQ_AVAIL(txq);
3690 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3691 int rem = do_prefetch ? count - i : 0;
3693 mp = _ring_peek_one(r, cidx, i, rem);
3694 MPASS(mp != NULL && *mp != NULL);
3695 if (__predict_false(*mp == (struct mbuf *)txq)) {
3699 in_use_prev = txq->ift_in_use;
3700 err = iflib_encap(txq, mp);
3701 if (__predict_false(err)) {
3702 /* no room - bail out */
3706 /* we can't send this packet - skip it */
3712 DBG_COUNTER_INC(tx_sent);
3713 bytes_sent += m->m_pkthdr.len;
3714 mcast_sent += !!(m->m_flags & M_MCAST);
3715 txq_avail = TXQ_AVAIL(txq);
3717 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3718 ETHER_BPF_MTAP(ifp, m);
3719 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3721 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3724 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3725 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3726 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3727 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3728 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3730 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3732 if (iflib_verbose_debug)
3733 printf("consumed=%d\n", consumed);
3739 iflib_txq_drain_always(struct ifmp_ring *r)
3745 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3753 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3755 callout_stop(&txq->ift_timer);
3756 CALLOUT_UNLOCK(txq);
3758 avail = IDXDIFF(pidx, cidx, r->size);
3759 for (i = 0; i < avail; i++) {
3760 mp = _ring_peek_one(r, cidx, i, avail - i);
3761 if (__predict_false(*mp == (struct mbuf *)txq))
3764 DBG_COUNTER_INC(tx_frees);
3766 MPASS(ifmp_ring_is_stalled(r) == 0);
3771 iflib_ifmp_purge(iflib_txq_t txq)
3773 struct ifmp_ring *r;
3776 r->drain = iflib_txq_drain_free;
3777 r->can_drain = iflib_txq_drain_always;
3779 ifmp_ring_check_drainage(r, r->size);
3781 r->drain = iflib_txq_drain;
3782 r->can_drain = iflib_txq_can_drain;
3786 _task_fn_tx(void *context)
3788 iflib_txq_t txq = context;
3789 if_ctx_t ctx = txq->ift_ctx;
3790 if_t ifp = ctx->ifc_ifp;
3791 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3793 #ifdef IFLIB_DIAGNOSTICS
3794 txq->ift_cpu_exec_count[curcpu]++;
3796 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3799 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3800 netmap_tx_irq(ifp, txq->ift_id))
3804 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3805 iflib_altq_if_start(ifp);
3807 if (txq->ift_db_pending)
3808 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3810 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3812 * When abdicating, we always need to check drainage, not just when we don't enqueue
3815 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3819 if (ctx->ifc_flags & IFC_LEGACY)
3820 IFDI_INTR_ENABLE(ctx);
3822 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3826 _task_fn_rx(void *context)
3828 iflib_rxq_t rxq = context;
3829 if_ctx_t ctx = rxq->ifr_ctx;
3837 #ifdef IFLIB_DIAGNOSTICS
3838 rxq->ifr_cpu_exec_count[curcpu]++;
3840 DBG_COUNTER_INC(task_fn_rxs);
3841 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3844 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3845 if (nmirq != NM_IRQ_PASS) {
3846 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3850 budget = ctx->ifc_sysctl_rx_budget;
3852 budget = 16; /* XXX */
3853 more = iflib_rxeof(rxq, budget);
3857 if ((more & IFLIB_RXEOF_MORE) == 0) {
3858 if (ctx->ifc_flags & IFC_LEGACY)
3859 IFDI_INTR_ENABLE(ctx);
3861 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3862 DBG_COUNTER_INC(rx_intr_enables);
3864 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3867 if (more & IFLIB_RXEOF_MORE)
3868 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3869 else if (more & IFLIB_RXEOF_EMPTY)
3870 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3874 _task_fn_admin(void *context)
3876 if_ctx_t ctx = context;
3877 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3880 bool oactive, running, do_reset, do_watchdog, in_detach;
3883 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3884 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3885 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3886 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3887 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3888 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3891 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3897 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3899 callout_stop(&txq->ift_timer);
3900 CALLOUT_UNLOCK(txq);
3903 ctx->ifc_watchdog_events++;
3904 IFDI_WATCHDOG_RESET(ctx);
3906 IFDI_UPDATE_ADMIN_STATUS(ctx);
3907 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3908 callout_reset_on(&txq->ift_timer, hz / 2, iflib_timer, txq,
3909 txq->ift_timer.c_cpu);
3911 IFDI_LINK_INTR_ENABLE(ctx);
3913 iflib_if_init_locked(ctx);
3916 if (LINK_ACTIVE(ctx) == 0)
3918 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3919 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3923 _task_fn_iov(void *context)
3925 if_ctx_t ctx = context;
3927 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3928 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3932 IFDI_VFLR_HANDLE(ctx);
3937 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3940 if_int_delay_info_t info;
3943 info = (if_int_delay_info_t)arg1;
3944 ctx = info->iidi_ctx;
3945 info->iidi_req = req;
3946 info->iidi_oidp = oidp;
3948 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3953 /*********************************************************************
3957 **********************************************************************/
3960 iflib_if_init_locked(if_ctx_t ctx)
3963 iflib_init_locked(ctx);
3967 iflib_if_init(void *arg)
3972 iflib_if_init_locked(ctx);
3977 iflib_if_transmit(if_t ifp, struct mbuf *m)
3979 if_ctx_t ctx = if_getsoftc(ifp);
3983 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3985 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3986 DBG_COUNTER_INC(tx_frees);
3991 MPASS(m->m_nextpkt == NULL);
3992 /* ALTQ-enabled interfaces always use queue 0. */
3994 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3995 qidx = QIDX(ctx, m);
3997 * XXX calculate buf_ring based on flowid (divvy up bits?)
3999 txq = &ctx->ifc_txqs[qidx];
4001 #ifdef DRIVER_BACKPRESSURE
4002 if (txq->ift_closed) {
4004 next = m->m_nextpkt;
4005 m->m_nextpkt = NULL;
4007 DBG_COUNTER_INC(tx_frees);
4019 next = next->m_nextpkt;
4020 } while (next != NULL);
4022 if (count > nitems(marr))
4023 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4024 /* XXX check nextpkt */
4026 /* XXX simplify for now */
4027 DBG_COUNTER_INC(tx_frees);
4030 for (next = m, i = 0; next != NULL; i++) {
4032 next = next->m_nextpkt;
4033 mp[i]->m_nextpkt = NULL;
4036 DBG_COUNTER_INC(tx_seen);
4037 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4040 GROUPTASK_ENQUEUE(&txq->ift_task);
4043 GROUPTASK_ENQUEUE(&txq->ift_task);
4044 /* support forthcoming later */
4045 #ifdef DRIVER_BACKPRESSURE
4046 txq->ift_closed = TRUE;
4048 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4050 DBG_COUNTER_INC(tx_frees);
4058 * The overall approach to integrating iflib with ALTQ is to continue to use
4059 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4060 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4061 * is redundant/unnecessary, but doing so minimizes the amount of
4062 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4063 * redundantly queueing to an intermediate mp_ring is swamped by the
4064 * performance limitations inherent in using ALTQ.
4066 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4067 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4068 * given interface. If ALTQ is enabled for an interface, then all
4069 * transmitted packets for that interface will be submitted to the ALTQ
4070 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4071 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4072 * update stats that the iflib machinery handles, and which is sensitve to
4073 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4074 * will be installed as the start routine for use by ALTQ facilities that
4075 * need to trigger queue drains on a scheduled basis.
4079 iflib_altq_if_start(if_t ifp)
4081 struct ifaltq *ifq = &ifp->if_snd;
4085 IFQ_DEQUEUE_NOLOCK(ifq, m);
4087 iflib_if_transmit(ifp, m);
4088 IFQ_DEQUEUE_NOLOCK(ifq, m);
4094 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4098 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4099 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4101 iflib_altq_if_start(ifp);
4103 err = iflib_if_transmit(ifp, m);
4110 iflib_if_qflush(if_t ifp)
4112 if_ctx_t ctx = if_getsoftc(ifp);
4113 iflib_txq_t txq = ctx->ifc_txqs;
4117 ctx->ifc_flags |= IFC_QFLUSH;
4119 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4120 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4121 iflib_txq_check_drain(txq, 0);
4123 ctx->ifc_flags &= ~IFC_QFLUSH;
4127 * When ALTQ is enabled, this will also take care of purging the
4133 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4134 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4135 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4136 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4139 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4141 if_ctx_t ctx = if_getsoftc(ifp);
4142 struct ifreq *ifr = (struct ifreq *)data;
4143 #if defined(INET) || defined(INET6)
4144 struct ifaddr *ifa = (struct ifaddr *)data;
4146 bool avoid_reset = false;
4147 int err = 0, reinit = 0, bits;
4152 if (ifa->ifa_addr->sa_family == AF_INET)
4156 if (ifa->ifa_addr->sa_family == AF_INET6)
4160 ** Calling init results in link renegotiation,
4161 ** so we avoid doing it when possible.
4164 if_setflagbits(ifp, IFF_UP,0);
4165 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4168 if (!(if_getflags(ifp) & IFF_NOARP))
4169 arp_ifinit(ifp, ifa);
4172 err = ether_ioctl(ifp, command, data);
4176 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4180 bits = if_getdrvflags(ifp);
4181 /* stop the driver and free any clusters before proceeding */
4184 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4186 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4187 ctx->ifc_flags |= IFC_MULTISEG;
4189 ctx->ifc_flags &= ~IFC_MULTISEG;
4191 err = if_setmtu(ifp, ifr->ifr_mtu);
4193 iflib_init_locked(ctx);
4195 if_setdrvflags(ifp, bits);
4201 if (if_getflags(ifp) & IFF_UP) {
4202 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4203 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4204 (IFF_PROMISC | IFF_ALLMULTI)) {
4206 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4211 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4214 ctx->ifc_if_flags = if_getflags(ifp);
4219 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4221 IFDI_INTR_DISABLE(ctx);
4222 IFDI_MULTI_SET(ctx);
4223 IFDI_INTR_ENABLE(ctx);
4229 IFDI_MEDIA_SET(ctx);
4234 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4238 struct ifi2creq i2c;
4240 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4243 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4247 if (i2c.len > sizeof(i2c.data)) {
4252 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4253 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4259 int mask, setmask, oldmask;
4261 oldmask = if_getcapenable(ifp);
4262 mask = ifr->ifr_reqcap ^ oldmask;
4263 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4266 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4268 setmask |= (mask & IFCAP_FLAGS);
4269 setmask |= (mask & IFCAP_WOL);
4272 * If any RX csum has changed, change all the ones that
4273 * are supported by the driver.
4275 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4276 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4277 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4281 * want to ensure that traffic has stopped before we change any of the flags
4285 bits = if_getdrvflags(ifp);
4286 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4289 if_togglecapenable(ifp, setmask);
4291 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4292 iflib_init_locked(ctx);
4294 if_setdrvflags(ifp, bits);
4301 case SIOCGPRIVATE_0:
4305 err = IFDI_PRIV_IOCTL(ctx, command, data);
4309 err = ether_ioctl(ifp, command, data);
4318 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4320 if_ctx_t ctx = if_getsoftc(ifp);
4322 return (IFDI_GET_COUNTER(ctx, cnt));
4325 /*********************************************************************
4327 * OTHER FUNCTIONS EXPORTED TO THE STACK
4329 **********************************************************************/
4332 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4334 if_ctx_t ctx = if_getsoftc(ifp);
4336 if ((void *)ctx != arg)
4339 if ((vtag == 0) || (vtag > 4095))
4342 if (iflib_in_detach(ctx))
4346 /* Driver may need all untagged packets to be flushed */
4347 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4349 IFDI_VLAN_REGISTER(ctx, vtag);
4350 /* Re-init to load the changes, if required */
4351 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4352 iflib_init_locked(ctx);
4357 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4359 if_ctx_t ctx = if_getsoftc(ifp);
4361 if ((void *)ctx != arg)
4364 if ((vtag == 0) || (vtag > 4095))
4368 /* Driver may need all tagged packets to be flushed */
4369 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4371 IFDI_VLAN_UNREGISTER(ctx, vtag);
4372 /* Re-init to load the changes, if required */
4373 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4374 iflib_init_locked(ctx);
4379 iflib_led_func(void *arg, int onoff)
4384 IFDI_LED_FUNC(ctx, onoff);
4388 /*********************************************************************
4390 * BUS FUNCTION DEFINITIONS
4392 **********************************************************************/
4395 iflib_device_probe(device_t dev)
4397 const pci_vendor_info_t *ent;
4398 if_shared_ctx_t sctx;
4399 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4400 uint16_t pci_vendor_id;
4402 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4405 pci_vendor_id = pci_get_vendor(dev);
4406 pci_device_id = pci_get_device(dev);
4407 pci_subvendor_id = pci_get_subvendor(dev);
4408 pci_subdevice_id = pci_get_subdevice(dev);
4409 pci_rev_id = pci_get_revid(dev);
4410 if (sctx->isc_parse_devinfo != NULL)
4411 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4413 ent = sctx->isc_vendor_info;
4414 while (ent->pvi_vendor_id != 0) {
4415 if (pci_vendor_id != ent->pvi_vendor_id) {
4419 if ((pci_device_id == ent->pvi_device_id) &&
4420 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4421 (ent->pvi_subvendor_id == 0)) &&
4422 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4423 (ent->pvi_subdevice_id == 0)) &&
4424 ((pci_rev_id == ent->pvi_rev_id) ||
4425 (ent->pvi_rev_id == 0))) {
4426 device_set_desc_copy(dev, ent->pvi_name);
4427 /* this needs to be changed to zero if the bus probing code
4428 * ever stops re-probing on best match because the sctx
4429 * may have its values over written by register calls
4430 * in subsequent probes
4432 return (BUS_PROBE_DEFAULT);
4440 iflib_device_probe_vendor(device_t dev)
4444 probe = iflib_device_probe(dev);
4445 if (probe == BUS_PROBE_DEFAULT)
4446 return (BUS_PROBE_VENDOR);
4452 iflib_reset_qvalues(if_ctx_t ctx)
4454 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4455 if_shared_ctx_t sctx = ctx->ifc_sctx;
4456 device_t dev = ctx->ifc_dev;
4459 if (ctx->ifc_sysctl_ntxqs != 0)
4460 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4461 if (ctx->ifc_sysctl_nrxqs != 0)
4462 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4464 for (i = 0; i < sctx->isc_ntxqs; i++) {
4465 if (ctx->ifc_sysctl_ntxds[i] != 0)
4466 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4468 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4471 for (i = 0; i < sctx->isc_nrxqs; i++) {
4472 if (ctx->ifc_sysctl_nrxds[i] != 0)
4473 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4475 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4478 for (i = 0; i < sctx->isc_nrxqs; i++) {
4479 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4480 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4481 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4482 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4484 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4485 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4486 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4487 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4489 if (!powerof2(scctx->isc_nrxd[i])) {
4490 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4491 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4492 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4496 for (i = 0; i < sctx->isc_ntxqs; i++) {
4497 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4498 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4499 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4500 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4502 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4503 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4504 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4505 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4507 if (!powerof2(scctx->isc_ntxd[i])) {
4508 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4509 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4510 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4516 iflib_add_pfil(if_ctx_t ctx)
4518 struct pfil_head *pfil;
4519 struct pfil_head_args pa;
4523 pa.pa_version = PFIL_VERSION;
4524 pa.pa_flags = PFIL_IN;
4525 pa.pa_type = PFIL_TYPE_ETHERNET;
4526 pa.pa_headname = ctx->ifc_ifp->if_xname;
4527 pfil = pfil_head_register(&pa);
4529 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4535 iflib_rem_pfil(if_ctx_t ctx)
4537 struct pfil_head *pfil;
4541 rxq = ctx->ifc_rxqs;
4543 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4546 pfil_head_unregister(pfil);
4550 get_ctx_core_offset(if_ctx_t ctx)
4552 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4553 struct cpu_offset *op;
4555 uint16_t ret = ctx->ifc_sysctl_core_offset;
4557 if (ret != CORE_OFFSET_UNSPECIFIED)
4560 if (ctx->ifc_sysctl_separate_txrx)
4561 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4563 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4565 mtx_lock(&cpu_offset_mtx);
4566 SLIST_FOREACH(op, &cpu_offsets, entries) {
4567 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4570 MPASS(op->refcount < UINT_MAX);
4575 if (ret == CORE_OFFSET_UNSPECIFIED) {
4577 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4580 device_printf(ctx->ifc_dev,
4581 "allocation for cpu offset failed.\n");
4585 CPU_COPY(&ctx->ifc_cpus, &op->set);
4586 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4589 mtx_unlock(&cpu_offset_mtx);
4595 unref_ctx_core_offset(if_ctx_t ctx)
4597 struct cpu_offset *op, *top;
4599 mtx_lock(&cpu_offset_mtx);
4600 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4601 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4602 MPASS(op->refcount > 0);
4604 if (op->refcount == 0) {
4605 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4611 mtx_unlock(&cpu_offset_mtx);
4615 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4619 if_softc_ctx_t scctx;
4620 kobjop_desc_t kobj_desc;
4621 kobj_method_t *kobj_method;
4623 int num_txd, num_rxd;
4625 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4628 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4629 device_set_softc(dev, ctx);
4630 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4633 ctx->ifc_sctx = sctx;
4635 ctx->ifc_softc = sc;
4637 if ((err = iflib_register(ctx)) != 0) {
4638 device_printf(dev, "iflib_register failed %d\n", err);
4641 iflib_add_device_sysctl_pre(ctx);
4643 scctx = &ctx->ifc_softc_ctx;
4646 iflib_reset_qvalues(ctx);
4648 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4649 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4652 _iflib_pre_assert(scctx);
4653 ctx->ifc_txrx = *scctx->isc_txrx;
4655 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4656 ctx->ifc_mediap = scctx->isc_media;
4659 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4660 MPASS(scctx->isc_tx_csum_flags);
4663 if_setcapabilities(ifp,
4664 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4665 if_setcapenable(ifp,
4666 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4668 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4669 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4670 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4671 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4673 num_txd = iflib_num_tx_descs(ctx);
4674 num_rxd = iflib_num_rx_descs(ctx);
4676 /* XXX change for per-queue sizes */
4677 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4680 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4681 scctx->isc_tx_nsegments = max(1, num_txd /
4682 MAX_SINGLE_PACKET_FRACTION);
4683 if (scctx->isc_tx_tso_segments_max > num_txd /
4684 MAX_SINGLE_PACKET_FRACTION)
4685 scctx->isc_tx_tso_segments_max = max(1,
4686 num_txd / MAX_SINGLE_PACKET_FRACTION);
4688 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4689 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4691 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4694 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4697 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4698 * into account. In the worst case, each of these calls will
4699 * add another mbuf and, thus, the requirement for another DMA
4700 * segment. So for best performance, it doesn't make sense to
4701 * advertize a maximum of TSO segments that typically will
4702 * require defragmentation in iflib_encap().
4704 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4705 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4707 if (scctx->isc_rss_table_size == 0)
4708 scctx->isc_rss_table_size = 64;
4709 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4711 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4712 /* XXX format name */
4713 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4714 NULL, NULL, "admin");
4716 /* Set up cpu set. If it fails, use the set of all CPUs. */
4717 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4718 device_printf(dev, "Unable to fetch CPU list\n");
4719 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4721 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4724 ** Now set up MSI or MSI-X, should return us the number of supported
4725 ** vectors (will be 1 for a legacy interrupt and MSI).
4727 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4728 msix = scctx->isc_vectors;
4729 } else if (scctx->isc_msix_bar != 0)
4731 * The simple fact that isc_msix_bar is not 0 does not mean we
4732 * we have a good value there that is known to work.
4734 msix = iflib_msix_init(ctx);
4736 scctx->isc_vectors = 1;
4737 scctx->isc_ntxqsets = 1;
4738 scctx->isc_nrxqsets = 1;
4739 scctx->isc_intr = IFLIB_INTR_LEGACY;
4742 /* Get memory for the station queues */
4743 if ((err = iflib_queues_alloc(ctx))) {
4744 device_printf(dev, "Unable to allocate queue memory\n");
4745 goto fail_intr_free;
4748 if ((err = iflib_qset_structures_setup(ctx)))
4752 * Now that we know how many queues there are, get the core offset.
4754 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4758 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4759 * aren't the default NULL implementation.
4761 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4762 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4764 if (kobj_method == &kobj_desc->deflt) {
4766 "MSI-X requires ifdi_rx_queue_intr_enable method");
4770 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4771 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4773 if (kobj_method == &kobj_desc->deflt) {
4775 "MSI-X requires ifdi_tx_queue_intr_enable method");
4781 * Assign the MSI-X vectors.
4782 * Note that the default NULL ifdi_msix_intr_assign method will
4785 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4787 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4791 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4793 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4797 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4798 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4803 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4805 goto fail_intr_free;
4808 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4810 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4811 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4816 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4817 * This must appear after the call to ether_ifattach() because
4818 * ether_ifattach() sets if_hdrlen to the default value.
4820 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4821 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4823 if ((err = iflib_netmap_attach(ctx))) {
4824 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4829 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4831 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4832 iflib_add_device_sysctl_post(ctx);
4833 iflib_add_pfil(ctx);
4834 ctx->ifc_flags |= IFC_INIT_DONE;
4840 ether_ifdetach(ctx->ifc_ifp);
4842 iflib_free_intr_mem(ctx);
4844 iflib_tx_structures_free(ctx);
4845 iflib_rx_structures_free(ctx);
4846 iflib_tqg_detach(ctx);
4850 iflib_deregister(ctx);
4852 device_set_softc(ctx->ifc_dev, NULL);
4853 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4854 free(ctx->ifc_softc, M_IFLIB);
4860 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4861 struct iflib_cloneattach_ctx *clctx)
4863 int num_txd, num_rxd;
4867 if_softc_ctx_t scctx;
4871 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4872 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4873 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4874 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4875 ctx->ifc_flags |= IFC_PSEUDO;
4877 ctx->ifc_sctx = sctx;
4878 ctx->ifc_softc = sc;
4881 if ((err = iflib_register(ctx)) != 0) {
4882 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4885 iflib_add_device_sysctl_pre(ctx);
4887 scctx = &ctx->ifc_softc_ctx;
4890 iflib_reset_qvalues(ctx);
4892 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4893 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4896 if (sctx->isc_flags & IFLIB_GEN_MAC)
4897 ether_gen_addr(ifp, &ctx->ifc_mac);
4898 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4899 clctx->cc_params)) != 0) {
4900 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4904 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4905 MPASS(scctx->isc_tx_csum_flags);
4908 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4909 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4911 ifp->if_flags |= IFF_NOGROUP;
4912 if (sctx->isc_flags & IFLIB_PSEUDO) {
4913 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4914 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4915 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4916 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4918 if_attach(ctx->ifc_ifp);
4919 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4922 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4923 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4929 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4930 * This must appear after the call to ether_ifattach() because
4931 * ether_ifattach() sets if_hdrlen to the default value.
4933 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4934 if_setifheaderlen(ifp,
4935 sizeof(struct ether_vlan_header));
4937 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4938 iflib_add_device_sysctl_post(ctx);
4939 ctx->ifc_flags |= IFC_INIT_DONE;
4943 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4944 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4945 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4947 _iflib_pre_assert(scctx);
4948 ctx->ifc_txrx = *scctx->isc_txrx;
4950 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4951 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4952 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4953 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4955 num_txd = iflib_num_tx_descs(ctx);
4956 num_rxd = iflib_num_rx_descs(ctx);
4958 /* XXX change for per-queue sizes */
4959 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4962 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4963 scctx->isc_tx_nsegments = max(1, num_txd /
4964 MAX_SINGLE_PACKET_FRACTION);
4965 if (scctx->isc_tx_tso_segments_max > num_txd /
4966 MAX_SINGLE_PACKET_FRACTION)
4967 scctx->isc_tx_tso_segments_max = max(1,
4968 num_txd / MAX_SINGLE_PACKET_FRACTION);
4970 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4971 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4973 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4976 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4979 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4980 * into account. In the worst case, each of these calls will
4981 * add another mbuf and, thus, the requirement for another DMA
4982 * segment. So for best performance, it doesn't make sense to
4983 * advertize a maximum of TSO segments that typically will
4984 * require defragmentation in iflib_encap().
4986 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4987 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4989 if (scctx->isc_rss_table_size == 0)
4990 scctx->isc_rss_table_size = 64;
4991 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4993 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4994 /* XXX format name */
4995 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4996 NULL, NULL, "admin");
4998 /* XXX --- can support > 1 -- but keep it simple for now */
4999 scctx->isc_intr = IFLIB_INTR_LEGACY;
5001 /* Get memory for the station queues */
5002 if ((err = iflib_queues_alloc(ctx))) {
5003 device_printf(dev, "Unable to allocate queue memory\n");
5004 goto fail_iflib_detach;
5007 if ((err = iflib_qset_structures_setup(ctx))) {
5008 device_printf(dev, "qset structure setup failed %d\n", err);
5013 * XXX What if anything do we want to do about interrupts?
5015 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5016 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5017 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5022 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5023 * This must appear after the call to ether_ifattach() because
5024 * ether_ifattach() sets if_hdrlen to the default value.
5026 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5027 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5029 /* XXX handle more than one queue */
5030 for (i = 0; i < scctx->isc_nrxqsets; i++)
5031 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5035 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5036 iflib_add_device_sysctl_post(ctx);
5037 ctx->ifc_flags |= IFC_INIT_DONE;
5042 ether_ifdetach(ctx->ifc_ifp);
5044 iflib_tx_structures_free(ctx);
5045 iflib_rx_structures_free(ctx);
5046 iflib_tqg_detach(ctx);
5051 iflib_deregister(ctx);
5053 free(ctx->ifc_softc, M_IFLIB);
5059 iflib_pseudo_deregister(if_ctx_t ctx)
5061 if_t ifp = ctx->ifc_ifp;
5062 if_shared_ctx_t sctx = ctx->ifc_sctx;
5064 /* Unregister VLAN event handlers early */
5065 iflib_unregister_vlan_handlers(ctx);
5067 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5068 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5072 ether_ifdetach(ifp);
5075 iflib_tqg_detach(ctx);
5076 iflib_tx_structures_free(ctx);
5077 iflib_rx_structures_free(ctx);
5079 iflib_deregister(ctx);
5081 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5082 free(ctx->ifc_softc, M_IFLIB);
5088 iflib_device_attach(device_t dev)
5091 if_shared_ctx_t sctx;
5093 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5096 pci_enable_busmaster(dev);
5098 return (iflib_device_register(dev, NULL, sctx, &ctx));
5102 iflib_device_deregister(if_ctx_t ctx)
5104 if_t ifp = ctx->ifc_ifp;
5105 device_t dev = ctx->ifc_dev;
5107 /* Make sure VLANS are not using driver */
5108 if (if_vlantrunkinuse(ifp)) {
5109 device_printf(dev, "Vlan in use, detach first\n");
5113 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5114 device_printf(dev, "SR-IOV in use; detach first.\n");
5120 ctx->ifc_flags |= IFC_IN_DETACH;
5123 /* Unregister VLAN handlers before calling iflib_stop() */
5124 iflib_unregister_vlan_handlers(ctx);
5126 iflib_netmap_detach(ifp);
5127 ether_ifdetach(ifp);
5133 iflib_rem_pfil(ctx);
5134 if (ctx->ifc_led_dev != NULL)
5135 led_destroy(ctx->ifc_led_dev);
5137 iflib_tqg_detach(ctx);
5142 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5143 iflib_free_intr_mem(ctx);
5145 bus_generic_detach(dev);
5147 iflib_tx_structures_free(ctx);
5148 iflib_rx_structures_free(ctx);
5150 iflib_deregister(ctx);
5152 device_set_softc(ctx->ifc_dev, NULL);
5153 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5154 free(ctx->ifc_softc, M_IFLIB);
5155 unref_ctx_core_offset(ctx);
5161 iflib_tqg_detach(if_ctx_t ctx)
5166 struct taskqgroup *tqg;
5168 /* XXX drain any dependent tasks */
5169 tqg = qgroup_if_io_tqg;
5170 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5171 callout_drain(&txq->ift_timer);
5173 callout_drain(&txq->ift_netmap_timer);
5174 #endif /* DEV_NETMAP */
5175 if (txq->ift_task.gt_uniq != NULL)
5176 taskqgroup_detach(tqg, &txq->ift_task);
5178 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5179 if (rxq->ifr_task.gt_uniq != NULL)
5180 taskqgroup_detach(tqg, &rxq->ifr_task);
5182 tqg = qgroup_if_config_tqg;
5183 if (ctx->ifc_admin_task.gt_uniq != NULL)
5184 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5185 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5186 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5190 iflib_free_intr_mem(if_ctx_t ctx)
5193 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5194 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5196 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5197 pci_release_msi(ctx->ifc_dev);
5199 if (ctx->ifc_msix_mem != NULL) {
5200 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5201 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5202 ctx->ifc_msix_mem = NULL;
5207 iflib_device_detach(device_t dev)
5209 if_ctx_t ctx = device_get_softc(dev);
5211 return (iflib_device_deregister(ctx));
5215 iflib_device_suspend(device_t dev)
5217 if_ctx_t ctx = device_get_softc(dev);
5223 return bus_generic_suspend(dev);
5226 iflib_device_shutdown(device_t dev)
5228 if_ctx_t ctx = device_get_softc(dev);
5234 return bus_generic_suspend(dev);
5238 iflib_device_resume(device_t dev)
5240 if_ctx_t ctx = device_get_softc(dev);
5241 iflib_txq_t txq = ctx->ifc_txqs;
5245 iflib_if_init_locked(ctx);
5247 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5248 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5250 return (bus_generic_resume(dev));
5254 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5257 if_ctx_t ctx = device_get_softc(dev);
5260 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5267 iflib_device_iov_uninit(device_t dev)
5269 if_ctx_t ctx = device_get_softc(dev);
5272 IFDI_IOV_UNINIT(ctx);
5277 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5280 if_ctx_t ctx = device_get_softc(dev);
5283 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5289 /*********************************************************************
5291 * MODULE FUNCTION DEFINITIONS
5293 **********************************************************************/
5296 * - Start a fast taskqueue thread for each core
5297 * - Start a taskqueue for control operations
5300 iflib_module_init(void)
5306 iflib_module_event_handler(module_t mod, int what, void *arg)
5312 if ((err = iflib_module_init()) != 0)
5318 return (EOPNOTSUPP);
5324 /*********************************************************************
5326 * PUBLIC FUNCTION DEFINITIONS
5327 * ordered as in iflib.h
5329 **********************************************************************/
5332 _iflib_assert(if_shared_ctx_t sctx)
5336 MPASS(sctx->isc_tx_maxsize);
5337 MPASS(sctx->isc_tx_maxsegsize);
5339 MPASS(sctx->isc_rx_maxsize);
5340 MPASS(sctx->isc_rx_nsegments);
5341 MPASS(sctx->isc_rx_maxsegsize);
5343 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5344 for (i = 0; i < sctx->isc_nrxqs; i++) {
5345 MPASS(sctx->isc_nrxd_min[i]);
5346 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5347 MPASS(sctx->isc_nrxd_max[i]);
5348 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5349 MPASS(sctx->isc_nrxd_default[i]);
5350 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5353 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5354 for (i = 0; i < sctx->isc_ntxqs; i++) {
5355 MPASS(sctx->isc_ntxd_min[i]);
5356 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5357 MPASS(sctx->isc_ntxd_max[i]);
5358 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5359 MPASS(sctx->isc_ntxd_default[i]);
5360 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5365 _iflib_pre_assert(if_softc_ctx_t scctx)
5368 MPASS(scctx->isc_txrx->ift_txd_encap);
5369 MPASS(scctx->isc_txrx->ift_txd_flush);
5370 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5371 MPASS(scctx->isc_txrx->ift_rxd_available);
5372 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5373 MPASS(scctx->isc_txrx->ift_rxd_refill);
5374 MPASS(scctx->isc_txrx->ift_rxd_flush);
5378 iflib_register(if_ctx_t ctx)
5380 if_shared_ctx_t sctx = ctx->ifc_sctx;
5381 driver_t *driver = sctx->isc_driver;
5382 device_t dev = ctx->ifc_dev;
5387 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5388 _iflib_assert(sctx);
5391 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5392 if (sctx->isc_flags & IFLIB_PSEUDO) {
5393 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5399 ifp = ctx->ifc_ifp = if_alloc(type);
5401 device_printf(dev, "can not allocate ifnet structure\n");
5406 * Initialize our context's device specific methods
5408 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5409 kobj_class_compile((kobj_class_t) driver);
5411 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5412 if_setsoftc(ifp, ctx);
5413 if_setdev(ifp, dev);
5414 if_setinitfn(ifp, iflib_if_init);
5415 if_setioctlfn(ifp, iflib_if_ioctl);
5417 if_setstartfn(ifp, iflib_altq_if_start);
5418 if_settransmitfn(ifp, iflib_altq_if_transmit);
5419 if_setsendqready(ifp);
5421 if_settransmitfn(ifp, iflib_if_transmit);
5423 if_setqflushfn(ifp, iflib_if_qflush);
5424 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5426 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5427 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5428 iflags |= IFF_POINTOPOINT;
5430 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5431 if_setflags(ifp, iflags);
5432 ctx->ifc_vlan_attach_event =
5433 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5434 EVENTHANDLER_PRI_FIRST);
5435 ctx->ifc_vlan_detach_event =
5436 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5437 EVENTHANDLER_PRI_FIRST);
5439 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5440 ctx->ifc_mediap = &ctx->ifc_media;
5441 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5442 iflib_media_change, iflib_media_status);
5448 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5450 /* Unregister VLAN events */
5451 if (ctx->ifc_vlan_attach_event != NULL) {
5452 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5453 ctx->ifc_vlan_attach_event = NULL;
5455 if (ctx->ifc_vlan_detach_event != NULL) {
5456 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5457 ctx->ifc_vlan_detach_event = NULL;
5463 iflib_deregister(if_ctx_t ctx)
5465 if_t ifp = ctx->ifc_ifp;
5467 /* Remove all media */
5468 ifmedia_removeall(&ctx->ifc_media);
5470 /* Ensure that VLAN event handlers are unregistered */
5471 iflib_unregister_vlan_handlers(ctx);
5473 /* Release kobject reference */
5474 kobj_delete((kobj_t) ctx, NULL);
5476 /* Free the ifnet structure */
5479 STATE_LOCK_DESTROY(ctx);
5481 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5482 CTX_LOCK_DESTROY(ctx);
5486 iflib_queues_alloc(if_ctx_t ctx)
5488 if_shared_ctx_t sctx = ctx->ifc_sctx;
5489 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5490 device_t dev = ctx->ifc_dev;
5491 int nrxqsets = scctx->isc_nrxqsets;
5492 int ntxqsets = scctx->isc_ntxqsets;
5495 iflib_fl_t fl = NULL;
5496 int i, j, cpu, err, txconf, rxconf;
5497 iflib_dma_info_t ifdip;
5498 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5499 uint32_t *txqsizes = scctx->isc_txqsizes;
5500 uint8_t nrxqs = sctx->isc_nrxqs;
5501 uint8_t ntxqs = sctx->isc_ntxqs;
5502 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5506 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5507 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5509 /* Allocate the TX ring struct memory */
5510 if (!(ctx->ifc_txqs =
5511 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5512 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5513 device_printf(dev, "Unable to allocate TX ring memory\n");
5518 /* Now allocate the RX */
5519 if (!(ctx->ifc_rxqs =
5520 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5521 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5522 device_printf(dev, "Unable to allocate RX ring memory\n");
5527 txq = ctx->ifc_txqs;
5528 rxq = ctx->ifc_rxqs;
5531 * XXX handle allocation failure
5533 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5534 /* Set up some basics */
5536 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5537 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5539 "Unable to allocate TX DMA info memory\n");
5543 txq->ift_ifdi = ifdip;
5544 for (j = 0; j < ntxqs; j++, ifdip++) {
5545 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5547 "Unable to allocate TX descriptors\n");
5551 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5552 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5556 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5557 txq->ift_br_offset = 1;
5559 txq->ift_br_offset = 0;
5562 if (iflib_txsd_alloc(txq)) {
5563 device_printf(dev, "Critical Failure setting up TX buffers\n");
5568 /* Initialize the TX lock */
5569 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5570 device_get_nameunit(dev), txq->ift_id);
5571 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5572 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5573 txq->ift_timer.c_cpu = cpu;
5575 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
5576 txq->ift_netmap_timer.c_cpu = cpu;
5577 #endif /* DEV_NETMAP */
5579 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5580 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5582 /* XXX free any allocated rings */
5583 device_printf(dev, "Unable to allocate buf_ring\n");
5588 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5589 /* Set up some basics */
5590 callout_init(&rxq->ifr_watchdog, 1);
5592 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5593 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5595 "Unable to allocate RX DMA info memory\n");
5600 rxq->ifr_ifdi = ifdip;
5601 /* XXX this needs to be changed if #rx queues != #tx queues */
5602 rxq->ifr_ntxqirq = 1;
5603 rxq->ifr_txqid[0] = i;
5604 for (j = 0; j < nrxqs; j++, ifdip++) {
5605 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5607 "Unable to allocate RX descriptors\n");
5611 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5615 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5616 rxq->ifr_fl_offset = 1;
5618 rxq->ifr_fl_offset = 0;
5620 rxq->ifr_nfl = nfree_lists;
5622 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5623 device_printf(dev, "Unable to allocate free list memory\n");
5628 for (j = 0; j < nfree_lists; j++) {
5629 fl[j].ifl_rxq = rxq;
5631 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5632 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5634 /* Allocate receive buffers for the ring */
5635 if (iflib_rxsd_alloc(rxq)) {
5637 "Critical Failure setting up receive buffers\n");
5642 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5643 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5648 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5649 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5650 for (i = 0; i < ntxqsets; i++) {
5651 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5653 for (j = 0; j < ntxqs; j++, di++) {
5654 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5655 paddrs[i*ntxqs + j] = di->idi_paddr;
5658 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5659 device_printf(ctx->ifc_dev,
5660 "Unable to allocate device TX queue\n");
5661 iflib_tx_structures_free(ctx);
5662 free(vaddrs, M_IFLIB);
5663 free(paddrs, M_IFLIB);
5666 free(vaddrs, M_IFLIB);
5667 free(paddrs, M_IFLIB);
5670 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5671 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5672 for (i = 0; i < nrxqsets; i++) {
5673 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5675 for (j = 0; j < nrxqs; j++, di++) {
5676 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5677 paddrs[i*nrxqs + j] = di->idi_paddr;
5680 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5681 device_printf(ctx->ifc_dev,
5682 "Unable to allocate device RX queue\n");
5683 iflib_tx_structures_free(ctx);
5684 free(vaddrs, M_IFLIB);
5685 free(paddrs, M_IFLIB);
5688 free(vaddrs, M_IFLIB);
5689 free(paddrs, M_IFLIB);
5693 /* XXX handle allocation failure changes */
5697 if (ctx->ifc_rxqs != NULL)
5698 free(ctx->ifc_rxqs, M_IFLIB);
5699 ctx->ifc_rxqs = NULL;
5700 if (ctx->ifc_txqs != NULL)
5701 free(ctx->ifc_txqs, M_IFLIB);
5702 ctx->ifc_txqs = NULL;
5708 iflib_tx_structures_setup(if_ctx_t ctx)
5710 iflib_txq_t txq = ctx->ifc_txqs;
5713 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5714 iflib_txq_setup(txq);
5720 iflib_tx_structures_free(if_ctx_t ctx)
5722 iflib_txq_t txq = ctx->ifc_txqs;
5723 if_shared_ctx_t sctx = ctx->ifc_sctx;
5726 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5727 for (j = 0; j < sctx->isc_ntxqs; j++)
5728 iflib_dma_free(&txq->ift_ifdi[j]);
5729 iflib_txq_destroy(txq);
5731 free(ctx->ifc_txqs, M_IFLIB);
5732 ctx->ifc_txqs = NULL;
5733 IFDI_QUEUES_FREE(ctx);
5736 /*********************************************************************
5738 * Initialize all receive rings.
5740 **********************************************************************/
5742 iflib_rx_structures_setup(if_ctx_t ctx)
5744 iflib_rxq_t rxq = ctx->ifc_rxqs;
5746 #if defined(INET6) || defined(INET)
5750 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5751 #if defined(INET6) || defined(INET)
5752 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5753 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5754 TCP_LRO_ENTRIES, min(1024,
5755 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5757 device_printf(ctx->ifc_dev,
5758 "LRO Initialization failed!\n");
5763 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5766 #if defined(INET6) || defined(INET)
5769 * Free LRO resources allocated so far, we will only handle
5770 * the rings that completed, the failing case will have
5771 * cleaned up for itself. 'q' failed, so its the terminus.
5773 rxq = ctx->ifc_rxqs;
5774 for (i = 0; i < q; ++i, rxq++) {
5775 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5776 tcp_lro_free(&rxq->ifr_lc);
5782 /*********************************************************************
5784 * Free all receive rings.
5786 **********************************************************************/
5788 iflib_rx_structures_free(if_ctx_t ctx)
5790 iflib_rxq_t rxq = ctx->ifc_rxqs;
5791 if_shared_ctx_t sctx = ctx->ifc_sctx;
5794 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5795 for (j = 0; j < sctx->isc_nrxqs; j++)
5796 iflib_dma_free(&rxq->ifr_ifdi[j]);
5797 iflib_rx_sds_free(rxq);
5798 #if defined(INET6) || defined(INET)
5799 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5800 tcp_lro_free(&rxq->ifr_lc);
5803 free(ctx->ifc_rxqs, M_IFLIB);
5804 ctx->ifc_rxqs = NULL;
5808 iflib_qset_structures_setup(if_ctx_t ctx)
5813 * It is expected that the caller takes care of freeing queues if this
5816 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5817 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5821 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5822 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5828 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5829 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5832 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5837 find_nth(if_ctx_t ctx, int qid)
5840 int i, cpuid, eqid, count;
5842 CPU_COPY(&ctx->ifc_cpus, &cpus);
5843 count = CPU_COUNT(&cpus);
5845 /* clear up to the qid'th bit */
5846 for (i = 0; i < eqid; i++) {
5847 cpuid = CPU_FFS(&cpus);
5849 CPU_CLR(cpuid-1, &cpus);
5851 cpuid = CPU_FFS(&cpus);
5857 extern struct cpu_group *cpu_top; /* CPU topology */
5860 find_child_with_core(int cpu, struct cpu_group *grp)
5864 if (grp->cg_children == 0)
5867 MPASS(grp->cg_child);
5868 for (i = 0; i < grp->cg_children; i++) {
5869 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5877 * Find the nth "close" core to the specified core
5878 * "close" is defined as the deepest level that shares
5879 * at least an L2 cache. With threads, this will be
5880 * threads on the same core. If the shared cache is L3
5881 * or higher, simply returns the same core.
5884 find_close_core(int cpu, int core_offset)
5886 struct cpu_group *grp;
5895 while ((i = find_child_with_core(cpu, grp)) != -1) {
5896 /* If the child only has one cpu, don't descend */
5897 if (grp->cg_child[i].cg_count <= 1)
5899 grp = &grp->cg_child[i];
5902 /* If they don't share at least an L2 cache, use the same CPU */
5903 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5907 CPU_COPY(&grp->cg_mask, &cs);
5909 /* Add the selected CPU offset to core offset. */
5910 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5911 if (fcpu - 1 == cpu)
5913 CPU_CLR(fcpu - 1, &cs);
5919 CPU_COPY(&grp->cg_mask, &cs);
5920 for (i = core_offset % grp->cg_count; i > 0; i--) {
5921 MPASS(CPU_FFS(&cs));
5922 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5924 MPASS(CPU_FFS(&cs));
5925 return CPU_FFS(&cs) - 1;
5929 find_close_core(int cpu, int core_offset __unused)
5936 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5940 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5941 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5942 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5944 case IFLIB_INTR_RXTX:
5945 /* RX queues get the specified core */
5946 return qid / CPU_COUNT(&ctx->ifc_cpus);
5952 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5953 #define find_close_core(cpuid, tid) CPU_FIRST()
5954 #define find_nth(ctx, gid) CPU_FIRST()
5957 /* Just to avoid copy/paste */
5959 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5960 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5964 int co, cpuid, err, tid;
5967 co = ctx->ifc_sysctl_core_offset;
5968 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5969 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5970 cpuid = find_nth(ctx, qid + co);
5971 tid = get_core_offset(ctx, type, qid);
5973 device_printf(dev, "get_core_offset failed\n");
5974 return (EOPNOTSUPP);
5976 cpuid = find_close_core(cpuid, tid);
5977 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5980 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5984 if (cpuid > ctx->ifc_cpuid_highest)
5985 ctx->ifc_cpuid_highest = cpuid;
5991 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5992 iflib_intr_type_t type, driver_filter_t *filter,
5993 void *filter_arg, int qid, const char *name)
5996 struct grouptask *gtask;
5997 struct taskqgroup *tqg;
5998 iflib_filter_info_t info;
6001 driver_filter_t *intr_fast;
6004 info = &ctx->ifc_filter_info;
6008 /* XXX merge tx/rx for netmap? */
6010 q = &ctx->ifc_txqs[qid];
6011 info = &ctx->ifc_txqs[qid].ift_filter_info;
6012 gtask = &ctx->ifc_txqs[qid].ift_task;
6013 tqg = qgroup_if_io_tqg;
6015 intr_fast = iflib_fast_intr;
6016 GROUPTASK_INIT(gtask, 0, fn, q);
6017 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6020 q = &ctx->ifc_rxqs[qid];
6021 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6022 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6023 tqg = qgroup_if_io_tqg;
6025 intr_fast = iflib_fast_intr;
6026 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6028 case IFLIB_INTR_RXTX:
6029 q = &ctx->ifc_rxqs[qid];
6030 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6031 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6032 tqg = qgroup_if_io_tqg;
6034 intr_fast = iflib_fast_intr_rxtx;
6035 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6037 case IFLIB_INTR_ADMIN:
6040 info = &ctx->ifc_filter_info;
6041 gtask = &ctx->ifc_admin_task;
6042 tqg = qgroup_if_config_tqg;
6043 fn = _task_fn_admin;
6044 intr_fast = iflib_fast_intr_ctx;
6047 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6052 info->ifi_filter = filter;
6053 info->ifi_filter_arg = filter_arg;
6054 info->ifi_task = gtask;
6058 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6060 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6063 if (type == IFLIB_INTR_ADMIN)
6067 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6072 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6079 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6081 struct grouptask *gtask;
6082 struct taskqgroup *tqg;
6089 q = &ctx->ifc_txqs[qid];
6090 gtask = &ctx->ifc_txqs[qid].ift_task;
6091 tqg = qgroup_if_io_tqg;
6093 GROUPTASK_INIT(gtask, 0, fn, q);
6096 q = &ctx->ifc_rxqs[qid];
6097 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6098 tqg = qgroup_if_io_tqg;
6100 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6102 case IFLIB_INTR_IOV:
6104 gtask = &ctx->ifc_vflr_task;
6105 tqg = qgroup_if_config_tqg;
6107 GROUPTASK_INIT(gtask, 0, fn, q);
6110 panic("unknown net intr type");
6113 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6116 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6119 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6124 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6128 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6131 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6132 rman_get_rid(irq->ii_res), irq->ii_res);
6136 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6138 iflib_txq_t txq = ctx->ifc_txqs;
6139 iflib_rxq_t rxq = ctx->ifc_rxqs;
6140 if_irq_t irq = &ctx->ifc_legacy_irq;
6141 iflib_filter_info_t info;
6143 struct grouptask *gtask;
6144 struct resource *res;
6145 struct taskqgroup *tqg;
6150 q = &ctx->ifc_rxqs[0];
6151 info = &rxq[0].ifr_filter_info;
6152 gtask = &rxq[0].ifr_task;
6153 tqg = qgroup_if_io_tqg;
6155 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6157 ctx->ifc_flags |= IFC_LEGACY;
6158 info->ifi_filter = filter;
6159 info->ifi_filter_arg = filter_arg;
6160 info->ifi_task = gtask;
6161 info->ifi_ctx = rx_only ? ctx : q;
6164 /* We allocate a single interrupt resource */
6165 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6166 iflib_fast_intr_rxtx, NULL, info, name);
6169 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6171 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6173 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6174 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6180 iflib_led_create(if_ctx_t ctx)
6183 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6184 device_get_nameunit(ctx->ifc_dev));
6188 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6191 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6195 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6198 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6202 iflib_admin_intr_deferred(if_ctx_t ctx)
6205 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6206 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6210 iflib_iov_intr_deferred(if_ctx_t ctx)
6213 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6217 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6220 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6225 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6229 GROUPTASK_INIT(gtask, 0, fn, ctx);
6230 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6235 iflib_config_gtask_deinit(struct grouptask *gtask)
6238 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6242 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6244 if_t ifp = ctx->ifc_ifp;
6245 iflib_txq_t txq = ctx->ifc_txqs;
6247 if_setbaudrate(ifp, baudrate);
6248 if (baudrate >= IF_Gbps(10)) {
6250 ctx->ifc_flags |= IFC_PREFETCH;
6253 /* If link down, disable watchdog */
6254 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6255 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6256 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6258 ctx->ifc_link_state = link_state;
6259 if_link_state_change(ifp, link_state);
6263 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6267 int credits_pre = txq->ift_cidx_processed;
6270 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6271 BUS_DMASYNC_POSTREAD);
6272 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6275 txq->ift_processed += credits;
6276 txq->ift_cidx_processed += credits;
6278 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6279 if (txq->ift_cidx_processed >= txq->ift_size)
6280 txq->ift_cidx_processed -= txq->ift_size;
6285 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6290 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6291 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6292 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6293 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6298 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6299 const char *description, if_int_delay_info_t info,
6300 int offset, int value)
6302 info->iidi_ctx = ctx;
6303 info->iidi_offset = offset;
6304 info->iidi_value = value;
6305 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6306 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6307 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6308 info, 0, iflib_sysctl_int_delay, "I", description);
6312 iflib_ctx_lock_get(if_ctx_t ctx)
6315 return (&ctx->ifc_ctx_sx);
6319 iflib_msix_init(if_ctx_t ctx)
6321 device_t dev = ctx->ifc_dev;
6322 if_shared_ctx_t sctx = ctx->ifc_sctx;
6323 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6324 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6325 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6327 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6328 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6331 device_printf(dev, "msix_init qsets capped at %d\n",
6332 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6334 /* Override by tuneable */
6335 if (scctx->isc_disable_msix)
6338 /* First try MSI-X */
6339 if ((msgs = pci_msix_count(dev)) == 0) {
6341 device_printf(dev, "MSI-X not supported or disabled\n");
6345 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6347 * bar == -1 => "trust me I know what I'm doing"
6348 * Some drivers are for hardware that is so shoddily
6349 * documented that no one knows which bars are which
6350 * so the developer has to map all bars. This hack
6351 * allows shoddy garbage to use MSI-X in this framework.
6354 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6355 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6356 if (ctx->ifc_msix_mem == NULL) {
6357 device_printf(dev, "Unable to map MSI-X table\n");
6362 admincnt = sctx->isc_admin_intrcnt;
6364 /* use only 1 qset in debug mode */
6365 queuemsgs = min(msgs - admincnt, 1);
6367 queuemsgs = msgs - admincnt;
6370 queues = imin(queuemsgs, rss_getnumbuckets());
6374 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6377 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6378 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6380 /* If we're doing RSS, clamp at the number of RSS buckets */
6381 if (queues > rss_getnumbuckets())
6382 queues = rss_getnumbuckets();
6384 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6385 rx_queues = iflib_num_rx_queues;
6389 if (rx_queues > scctx->isc_nrxqsets)
6390 rx_queues = scctx->isc_nrxqsets;
6393 * We want this to be all logical CPUs by default
6395 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6396 tx_queues = iflib_num_tx_queues;
6398 tx_queues = mp_ncpus;
6400 if (tx_queues > scctx->isc_ntxqsets)
6401 tx_queues = scctx->isc_ntxqsets;
6403 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6405 if (tx_queues != rx_queues)
6407 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6408 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6410 tx_queues = min(rx_queues, tx_queues);
6411 rx_queues = min(rx_queues, tx_queues);
6414 vectors = rx_queues + admincnt;
6415 if (msgs < vectors) {
6417 "insufficient number of MSI-X vectors "
6418 "(supported %d, need %d)\n", msgs, vectors);
6422 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6425 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6426 if (vectors != msgs) {
6428 "Unable to allocate sufficient MSI-X vectors "
6429 "(got %d, need %d)\n", vectors, msgs);
6430 pci_release_msi(dev);
6432 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6434 ctx->ifc_msix_mem = NULL;
6438 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6440 scctx->isc_vectors = vectors;
6441 scctx->isc_nrxqsets = rx_queues;
6442 scctx->isc_ntxqsets = tx_queues;
6443 scctx->isc_intr = IFLIB_INTR_MSIX;
6448 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6451 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6453 ctx->ifc_msix_mem = NULL;
6458 vectors = pci_msi_count(dev);
6459 scctx->isc_nrxqsets = 1;
6460 scctx->isc_ntxqsets = 1;
6461 scctx->isc_vectors = vectors;
6462 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6463 device_printf(dev,"Using an MSI interrupt\n");
6464 scctx->isc_intr = IFLIB_INTR_MSI;
6466 scctx->isc_vectors = 1;
6467 device_printf(dev,"Using a Legacy interrupt\n");
6468 scctx->isc_intr = IFLIB_INTR_LEGACY;
6474 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6477 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6480 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6482 const char *ring_state = "UNKNOWN";
6485 rc = sysctl_wire_old_buffer(req, 0);
6489 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6494 ring_state = ring_states[state[3]];
6496 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6497 state[0], state[1], state[2], ring_state);
6498 rc = sbuf_finish(sb);
6503 enum iflib_ndesc_handler {
6509 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6511 if_ctx_t ctx = (void *)arg1;
6512 enum iflib_ndesc_handler type = arg2;
6513 char buf[256] = {0};
6520 case IFLIB_NTXD_HANDLER:
6521 ndesc = ctx->ifc_sysctl_ntxds;
6523 nqs = ctx->ifc_sctx->isc_ntxqs;
6525 case IFLIB_NRXD_HANDLER:
6526 ndesc = ctx->ifc_sysctl_nrxds;
6528 nqs = ctx->ifc_sctx->isc_nrxqs;
6531 printf("%s: unhandled type\n", __func__);
6537 for (i=0; i<8; i++) {
6542 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6545 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6546 if (rc || req->newptr == NULL)
6549 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6550 i++, p = strsep(&next, " ,")) {
6551 ndesc[i] = strtoul(p, NULL, 10);
6557 #define NAME_BUFLEN 32
6559 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6561 device_t dev = iflib_get_dev(ctx);
6562 struct sysctl_oid_list *child, *oid_list;
6563 struct sysctl_ctx_list *ctx_list;
6564 struct sysctl_oid *node;
6566 ctx_list = device_get_sysctl_ctx(dev);
6567 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6568 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6569 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6570 oid_list = SYSCTL_CHILDREN(node);
6572 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6573 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6576 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6577 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6578 "# of txqs to use, 0 => use default #");
6579 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6580 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6581 "# of rxqs to use, 0 => use default #");
6582 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6583 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6584 "permit #txq != #rxq");
6585 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6586 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6587 "disable MSI-X (default 0)");
6588 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6589 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6590 "set the RX budget");
6591 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6592 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6593 "cause TX to abdicate instead of running to completion");
6594 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6595 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6596 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6597 "offset to start using cores at");
6598 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6599 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6600 "use separate cores for TX and RX");
6602 /* XXX change for per-queue sizes */
6603 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6604 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6605 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6606 "list of # of TX descriptors to use, 0 = use default #");
6607 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6608 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6609 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6610 "list of # of RX descriptors to use, 0 = use default #");
6614 iflib_add_device_sysctl_post(if_ctx_t ctx)
6616 if_shared_ctx_t sctx = ctx->ifc_sctx;
6617 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6618 device_t dev = iflib_get_dev(ctx);
6619 struct sysctl_oid_list *child;
6620 struct sysctl_ctx_list *ctx_list;
6625 char namebuf[NAME_BUFLEN];
6627 struct sysctl_oid *queue_node, *fl_node, *node;
6628 struct sysctl_oid_list *queue_list, *fl_list;
6629 ctx_list = device_get_sysctl_ctx(dev);
6631 node = ctx->ifc_sysctl_node;
6632 child = SYSCTL_CHILDREN(node);
6634 if (scctx->isc_ntxqsets > 100)
6636 else if (scctx->isc_ntxqsets > 10)
6640 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6641 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6642 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6643 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6644 queue_list = SYSCTL_CHILDREN(queue_node);
6646 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6648 &txq->ift_dequeued, "total mbufs freed");
6649 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6651 &txq->ift_enqueued, "total mbufs enqueued");
6653 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6655 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6656 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6658 &txq->ift_pullups, "# of times m_pullup was called");
6659 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6661 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6662 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6664 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6665 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6667 &txq->ift_map_failed, "# of times DMA map failed");
6668 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6670 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6671 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6673 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6674 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6676 &txq->ift_pidx, 1, "Producer Index");
6677 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6679 &txq->ift_cidx, 1, "Consumer Index");
6680 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6682 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6683 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6685 &txq->ift_in_use, 1, "descriptors in use");
6686 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6688 &txq->ift_processed, "descriptors procesed for clean");
6689 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6691 &txq->ift_cleaned, "total cleaned");
6692 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6693 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6694 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6695 mp_ring_state_handler, "A", "soft ring state");
6696 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6697 CTLFLAG_RD, &txq->ift_br->enqueues,
6698 "# of enqueues to the mp_ring for this queue");
6699 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6700 CTLFLAG_RD, &txq->ift_br->drops,
6701 "# of drops in the mp_ring for this queue");
6702 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6703 CTLFLAG_RD, &txq->ift_br->starts,
6704 "# of normal consumer starts in the mp_ring for this queue");
6705 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6706 CTLFLAG_RD, &txq->ift_br->stalls,
6707 "# of consumer stalls in the mp_ring for this queue");
6708 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6709 CTLFLAG_RD, &txq->ift_br->restarts,
6710 "# of consumer restarts in the mp_ring for this queue");
6711 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6712 CTLFLAG_RD, &txq->ift_br->abdications,
6713 "# of consumer abdications in the mp_ring for this queue");
6716 if (scctx->isc_nrxqsets > 100)
6718 else if (scctx->isc_nrxqsets > 10)
6722 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6723 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6724 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6725 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6726 queue_list = SYSCTL_CHILDREN(queue_node);
6727 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6728 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6730 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6733 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6734 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6735 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6736 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6737 fl_list = SYSCTL_CHILDREN(fl_node);
6738 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6740 &fl->ifl_pidx, 1, "Producer Index");
6741 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6743 &fl->ifl_cidx, 1, "Consumer Index");
6744 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6746 &fl->ifl_credits, 1, "credits available");
6747 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6749 &fl->ifl_buf_size, 1, "buffer size");
6751 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6753 &fl->ifl_m_enqueued, "mbufs allocated");
6754 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6756 &fl->ifl_m_dequeued, "mbufs freed");
6757 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6759 &fl->ifl_cl_enqueued, "clusters allocated");
6760 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6762 &fl->ifl_cl_dequeued, "clusters freed");
6770 iflib_request_reset(if_ctx_t ctx)
6774 ctx->ifc_flags |= IFC_DO_RESET;
6778 #ifndef __NO_STRICT_ALIGNMENT
6779 static struct mbuf *
6780 iflib_fixup_rx(struct mbuf *m)
6784 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6785 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6786 m->m_data += ETHER_HDR_LEN;
6789 MGETHDR(n, M_NOWAIT, MT_DATA);
6794 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6795 m->m_data += ETHER_HDR_LEN;
6796 m->m_len -= ETHER_HDR_LEN;
6797 n->m_len = ETHER_HDR_LEN;
6798 M_MOVE_PKTHDR(n, m);
6807 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6811 ctx = if_getsoftc(ifp);
6813 *nrxr = NRXQSETS(ctx);
6814 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6815 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6820 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6823 if_softc_ctx_t scctx;
6828 ctx = if_getsoftc(ifp);
6829 scctx = &ctx->ifc_softc_ctx;
6832 case DEBUGNET_START:
6833 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6834 rxq = &ctx->ifc_rxqs[i];
6835 for (j = 0; j < rxq->ifr_nfl; j++) {
6837 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6840 iflib_no_tx_batch = 1;
6848 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6854 ctx = if_getsoftc(ifp);
6855 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6859 txq = &ctx->ifc_txqs[0];
6860 error = iflib_encap(txq, &m);
6862 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6867 iflib_debugnet_poll(if_t ifp, int count)
6869 struct epoch_tracker et;
6871 if_softc_ctx_t scctx;
6875 ctx = if_getsoftc(ifp);
6876 scctx = &ctx->ifc_softc_ctx;
6878 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6882 txq = &ctx->ifc_txqs[0];
6883 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6885 NET_EPOCH_ENTER(et);
6886 for (i = 0; i < scctx->isc_nrxqsets; i++)
6887 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6891 #endif /* DEBUGNET */