2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 #define IFLIB_RXEOF_MORE (1U << 0)
132 #define IFLIB_RXEOF_EMPTY (2U << 0)
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
145 static void iflib_tqg_detach(if_ctx_t ctx);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
198 uint8_t ifc_sysctl_use_logical_cores;
199 bool ifc_cpus_are_physical_cores;
201 qidx_t ifc_sysctl_ntxds[8];
202 qidx_t ifc_sysctl_nrxds[8];
203 struct if_txrx ifc_txrx;
204 #define isc_txd_encap ifc_txrx.ift_txd_encap
205 #define isc_txd_flush ifc_txrx.ift_txd_flush
206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
207 #define isc_rxd_available ifc_txrx.ift_rxd_available
208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
212 eventhandler_tag ifc_vlan_attach_event;
213 eventhandler_tag ifc_vlan_detach_event;
214 struct ether_addr ifc_mac;
218 iflib_get_softc(if_ctx_t ctx)
221 return (ctx->ifc_softc);
225 iflib_get_dev(if_ctx_t ctx)
228 return (ctx->ifc_dev);
232 iflib_get_ifp(if_ctx_t ctx)
235 return (ctx->ifc_ifp);
239 iflib_get_media(if_ctx_t ctx)
242 return (ctx->ifc_mediap);
246 iflib_get_flags(if_ctx_t ctx)
248 return (ctx->ifc_flags);
252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
259 iflib_get_softc_ctx(if_ctx_t ctx)
262 return (&ctx->ifc_softc_ctx);
266 iflib_get_sctx(if_ctx_t ctx)
269 return (ctx->ifc_sctx);
272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
289 struct mbuf **ifsd_m; /* pkthdr mbufs */
292 /* magic number that should be high enough for any hardware */
293 #define IFLIB_MAX_TX_SEGS 128
294 #define IFLIB_RX_COPY_THRESH 128
295 #define IFLIB_MAX_RX_REFRESH 32
296 /* The minimum descriptors per second before we start coalescing */
297 #define IFLIB_MIN_DESC_SEC 16384
298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
299 #define IFLIB_QUEUE_IDLE 0
300 #define IFLIB_QUEUE_HUNG 1
301 #define IFLIB_QUEUE_WORKING 2
302 /* maximum number of txqs that can share an rx interrupt */
303 #define IFLIB_MAX_TX_SHARED_INTR 4
305 /* this should really scale with ring size - this is a fairly arbitrary value */
306 #define TX_BATCH_SIZE 32
308 #define IFLIB_RESTART_BUDGET 8
310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
317 qidx_t ift_cidx_processed;
320 uint8_t ift_br_offset;
321 uint16_t ift_npending;
322 uint16_t ift_db_pending;
323 uint16_t ift_rs_pending;
325 uint8_t ift_txd_size[8];
326 uint64_t ift_processed;
327 uint64_t ift_cleaned;
328 uint64_t ift_cleaned_prev;
330 uint64_t ift_enqueued;
331 uint64_t ift_dequeued;
333 uint64_t ift_no_tx_dma_setup;
334 uint64_t ift_no_desc_avail;
335 uint64_t ift_mbuf_defrag_failed;
336 uint64_t ift_mbuf_defrag;
337 uint64_t ift_map_failed;
338 uint64_t ift_txd_encap_efbig;
339 uint64_t ift_pullups;
340 uint64_t ift_last_timer_tick;
343 struct mtx ift_db_mtx;
345 /* constant values */
347 struct ifmp_ring *ift_br;
348 struct grouptask ift_task;
351 struct callout ift_timer;
353 struct callout ift_netmap_timer;
354 #endif /* DEV_NETMAP */
356 if_txsd_vec_t ift_sds;
359 uint8_t ift_update_freq;
360 struct iflib_filter_info ift_filter_info;
361 bus_dma_tag_t ift_buf_tag;
362 bus_dma_tag_t ift_tso_buf_tag;
363 iflib_dma_info_t ift_ifdi;
364 #define MTX_NAME_LEN 32
365 char ift_mtx_name[MTX_NAME_LEN];
366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
367 #ifdef IFLIB_DIAGNOSTICS
368 uint64_t ift_cpu_exec_count[256];
370 } __aligned(CACHE_LINE_SIZE);
377 uint8_t ifl_rxd_size;
379 uint64_t ifl_m_enqueued;
380 uint64_t ifl_m_dequeued;
381 uint64_t ifl_cl_enqueued;
382 uint64_t ifl_cl_dequeued;
385 bitstr_t *ifl_rx_bitmap;
389 uint16_t ifl_buf_size;
392 iflib_rxsd_array_t ifl_sds;
395 bus_dma_tag_t ifl_buf_tag;
396 iflib_dma_info_t ifl_ifdi;
397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
399 } __aligned(CACHE_LINE_SIZE);
402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
408 else if (pidx < cidx)
409 used = size - cidx + pidx;
410 else if (gen == 0 && pidx == cidx)
412 else if (gen == 1 && pidx == cidx)
420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
422 #define IDXDIFF(head, tail, wrap) \
423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
429 struct pfil_head *pfil;
431 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
432 * the completion queue consumer index. Otherwise it's unused.
438 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
439 uint8_t ifr_fl_offset;
440 struct lro_ctrl ifr_lc;
441 struct grouptask ifr_task;
442 struct callout ifr_watchdog;
443 struct iflib_filter_info ifr_filter_info;
444 iflib_dma_info_t ifr_ifdi;
446 /* dynamically allocate if any drivers need a value substantially larger than this */
447 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
448 #ifdef IFLIB_DIAGNOSTICS
449 uint64_t ifr_cpu_exec_count[256];
451 } __aligned(CACHE_LINE_SIZE);
453 typedef struct if_rxsd {
458 /* multiple of word size */
460 #define PKT_INFO_SIZE 6
461 #define RXD_INFO_SIZE 5
462 #define PKT_TYPE uint64_t
464 #define PKT_INFO_SIZE 11
465 #define RXD_INFO_SIZE 8
466 #define PKT_TYPE uint32_t
468 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
469 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
471 typedef struct if_pkt_info_pad {
472 PKT_TYPE pkt_val[PKT_INFO_SIZE];
473 } *if_pkt_info_pad_t;
474 typedef struct if_rxd_info_pad {
475 PKT_TYPE rxd_val[RXD_INFO_SIZE];
476 } *if_rxd_info_pad_t;
478 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
479 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
482 pkt_info_zero(if_pkt_info_t pi)
484 if_pkt_info_pad_t pi_pad;
486 pi_pad = (if_pkt_info_pad_t)pi;
487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
495 static device_method_t iflib_pseudo_methods[] = {
496 DEVMETHOD(device_attach, noop_attach),
497 DEVMETHOD(device_detach, iflib_pseudo_detach),
501 driver_t iflib_pseudodriver = {
502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
506 rxd_info_zero(if_rxd_info_t ri)
508 if_rxd_info_pad_t ri_pad;
511 ri_pad = (if_rxd_info_pad_t)ri;
512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
513 ri_pad->rxd_val[i] = 0;
514 ri_pad->rxd_val[i+1] = 0;
515 ri_pad->rxd_val[i+2] = 0;
516 ri_pad->rxd_val[i+3] = 0;
519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
524 * Only allow a single packet to take up most 1/nth of the tx ring
526 #define MAX_SINGLE_PACKET_FRACTION 12
527 #define IF_BAD_DMA (bus_addr_t)-1
529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
545 iflib_set_detach(if_ctx_t ctx)
548 ctx->ifc_flags |= IFC_IN_DETACH;
552 /* Our boot-time initialization hook */
553 static int iflib_module_event_handler(module_t, int, void *);
555 static moduledata_t iflib_moduledata = {
557 iflib_module_event_handler,
561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
562 MODULE_VERSION(iflib, 1);
564 MODULE_DEPEND(iflib, pci, 1, 1, 1);
565 MODULE_DEPEND(iflib, ether, 1, 1, 1);
567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
570 #ifndef IFLIB_DEBUG_COUNTERS
572 #define IFLIB_DEBUG_COUNTERS 1
574 #define IFLIB_DEBUG_COUNTERS 0
575 #endif /* !INVARIANTS */
578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
579 "iflib driver parameters");
582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
584 static int iflib_min_tx_latency = 0;
585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
587 static int iflib_no_tx_batch = 0;
588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
590 static int iflib_timer_default = 1000;
591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
595 #if IFLIB_DEBUG_COUNTERS
597 static int iflib_tx_seen;
598 static int iflib_tx_sent;
599 static int iflib_tx_encap;
600 static int iflib_rx_allocs;
601 static int iflib_fl_refills;
602 static int iflib_fl_refills_large;
603 static int iflib_tx_frees;
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
606 &iflib_tx_seen, 0, "# TX mbufs seen");
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
608 &iflib_tx_sent, 0, "# TX mbufs sent");
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
610 &iflib_tx_encap, 0, "# TX mbufs encapped");
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
612 &iflib_tx_frees, 0, "# TX frees");
613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
614 &iflib_rx_allocs, 0, "# RX allocations");
615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
616 &iflib_fl_refills, 0, "# refills");
617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
618 &iflib_fl_refills_large, 0, "# large refills");
620 static int iflib_txq_drain_flushing;
621 static int iflib_txq_drain_oactive;
622 static int iflib_txq_drain_notready;
624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
625 &iflib_txq_drain_flushing, 0, "# drain flushes");
626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
627 &iflib_txq_drain_oactive, 0, "# drain oactives");
628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
629 &iflib_txq_drain_notready, 0, "# drain notready");
631 static int iflib_encap_load_mbuf_fail;
632 static int iflib_encap_pad_mbuf_fail;
633 static int iflib_encap_txq_avail_fail;
634 static int iflib_encap_txd_encap_fail;
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
645 static int iflib_task_fn_rxs;
646 static int iflib_rx_intr_enables;
647 static int iflib_fast_intrs;
648 static int iflib_rx_unavail;
649 static int iflib_rx_ctx_inactive;
650 static int iflib_rx_if_input;
651 static int iflib_rxd_flush;
653 static int iflib_verbose_debug;
655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
658 &iflib_rx_intr_enables, 0, "# RX intr enables");
659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
660 &iflib_fast_intrs, 0, "# fast_intr calls");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
662 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
666 &iflib_rx_if_input, 0, "# times rxeof called if_input");
667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
668 &iflib_rxd_flush, 0, "# times rxd_flush called");
669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
670 &iflib_verbose_debug, 0, "enable verbose debugging");
672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
674 iflib_debug_reset(void)
676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
678 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
679 iflib_txq_drain_notready =
680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
684 iflib_rx_ctx_inactive = iflib_rx_if_input =
689 #define DBG_COUNTER_INC(name)
690 static void iflib_debug_reset(void) {}
693 #define IFLIB_DEBUG 0
695 static void iflib_tx_structures_free(if_ctx_t ctx);
696 static void iflib_rx_structures_free(if_ctx_t ctx);
697 static int iflib_queues_alloc(if_ctx_t ctx);
698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
700 static int iflib_qset_structures_setup(if_ctx_t ctx);
701 static int iflib_msix_init(if_ctx_t ctx);
702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
706 static void iflib_altq_if_start(if_t ifp);
707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
709 static int iflib_register(if_ctx_t);
710 static void iflib_deregister(if_ctx_t);
711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
712 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
713 static void iflib_init_locked(if_ctx_t ctx);
714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
715 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
716 static void iflib_ifmp_purge(iflib_txq_t txq);
717 static void _iflib_pre_assert(if_softc_ctx_t scctx);
718 static void iflib_if_init_locked(if_ctx_t ctx);
719 static void iflib_free_intr_mem(if_ctx_t ctx);
720 #ifndef __NO_STRICT_ALIGNMENT
721 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
724 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
725 SLIST_HEAD_INITIALIZER(cpu_offsets);
727 SLIST_ENTRY(cpu_offset) entries;
729 unsigned int refcount;
732 static struct mtx cpu_offset_mtx;
733 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
736 DEBUGNET_DEFINE(iflib);
739 iflib_num_rx_descs(if_ctx_t ctx)
741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
742 if_shared_ctx_t sctx = ctx->ifc_sctx;
743 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
745 return scctx->isc_nrxd[first_rxq];
749 iflib_num_tx_descs(if_ctx_t ctx)
751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
752 if_shared_ctx_t sctx = ctx->ifc_sctx;
753 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
755 return scctx->isc_ntxd[first_txq];
759 #include <sys/selinfo.h>
760 #include <net/netmap.h>
761 #include <dev/netmap/netmap_kern.h>
763 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
765 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
766 static void iflib_netmap_timer(void *arg);
769 * device-specific sysctl variables:
771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
772 * During regular operations the CRC is stripped, but on some
773 * hardware reception of frames not multiple of 64 is slower,
774 * so using crcstrip=0 helps in benchmarks.
776 * iflib_rx_miss, iflib_rx_miss_bufs:
777 * count packets that might be missed due to lost interrupts.
779 SYSCTL_DECL(_dev_netmap);
781 * The xl driver by default strips CRCs and we do not override it.
784 int iflib_crcstrip = 1;
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
788 int iflib_rx_miss, iflib_rx_miss_bufs;
789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
795 * Register/unregister. We are already under netmap lock.
796 * Only called on the first register or the last unregister.
799 iflib_netmap_register(struct netmap_adapter *na, int onoff)
802 if_ctx_t ctx = ifp->if_softc;
807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
812 * Enable (or disable) netmap flags, and intercept (or restore)
813 * ifp->if_transmit. This is done once the device has been stopped
814 * to prevent race conditions. Also, this must be done after
815 * calling netmap_disable_all_rings() and before calling
816 * netmap_enable_all_rings(), so that these two functions see the
817 * updated state of the NAF_NETMAP_ON bit.
820 nm_set_native_flags(na);
822 nm_clear_native_flags(na);
825 iflib_init_locked(ctx);
826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
829 nm_clear_native_flags(na);
835 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
838 if_ctx_t ctx = ifp->if_softc;
839 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
840 iflib_fl_t fl = &rxq->ifr_fl[0];
842 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
843 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
844 info->num_tx_descs = iflib_num_tx_descs(ctx);
845 info->num_rx_descs = iflib_num_rx_descs(ctx);
846 info->rx_buf_maxsize = fl->ifl_buf_size;
847 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
848 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
849 info->num_rx_descs, info->rx_buf_maxsize);
855 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
857 struct netmap_adapter *na = kring->na;
858 u_int const lim = kring->nkr_num_slots - 1;
859 struct netmap_ring *ring = kring->ring;
861 struct if_rxd_update iru;
862 if_ctx_t ctx = rxq->ifr_ctx;
863 iflib_fl_t fl = &rxq->ifr_fl[0];
864 u_int nic_i_first, nic_i;
867 #if IFLIB_DEBUG_COUNTERS
872 * This function is used both at initialization and in rxsync.
873 * At initialization we need to prepare (with isc_rxd_refill())
874 * all the netmap buffers currently owned by the kernel, in
875 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
876 * (except for kring->nkr_hwofs). These may be less than
877 * kring->nkr_num_slots if netmap_reset() was called while
878 * an application using the kring that still owned some
880 * At rxsync time, both indexes point to the next buffer to be
882 * In any case we publish (with isc_rxd_flush()) up to
883 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
884 * pointer to overrun the head/cons pointer, although this is
885 * not necessary for some NICs (e.g. vmx).
887 if (__predict_false(init)) {
888 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
890 n = kring->rhead - kring->nr_hwcur;
892 return (0); /* Nothing to do. */
894 n += kring->nkr_num_slots;
897 iru_init(&iru, rxq, 0 /* flid */);
898 map = fl->ifl_sds.ifsd_map;
899 nic_i = fl->ifl_pidx;
900 nm_i = netmap_idx_n2k(kring, nic_i);
901 if (__predict_false(init)) {
903 * On init/reset, nic_i must be 0, and we must
904 * start to refill from hwtail (see netmap_reset()).
907 MPASS(nm_i == kring->nr_hwtail);
909 MPASS(nm_i == kring->nr_hwcur);
910 DBG_COUNTER_INC(fl_refills);
912 #if IFLIB_DEBUG_COUNTERS
914 DBG_COUNTER_INC(fl_refills_large);
917 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
918 struct netmap_slot *slot = &ring->slot[nm_i];
919 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
921 MPASS(i < IFLIB_MAX_RX_REFRESH);
923 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
924 return netmap_ring_reinit(kring);
926 fl->ifl_rxd_idxs[i] = nic_i;
928 if (__predict_false(init)) {
929 netmap_load_map(na, fl->ifl_buf_tag,
931 } else if (slot->flags & NS_BUF_CHANGED) {
932 /* buffer has changed, reload map */
933 netmap_reload_map(na, fl->ifl_buf_tag,
936 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
937 BUS_DMASYNC_PREREAD);
938 slot->flags &= ~NS_BUF_CHANGED;
940 nm_i = nm_next(nm_i, lim);
941 nic_i = nm_next(nic_i, lim);
944 iru.iru_pidx = nic_i_first;
946 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
948 fl->ifl_pidx = nic_i;
950 * At the end of the loop we must have refilled everything
951 * we could possibly refill.
953 MPASS(nm_i == kring->rhead);
954 kring->nr_hwcur = nm_i;
956 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
958 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
959 nm_prev(nic_i, lim));
960 DBG_COUNTER_INC(rxd_flush);
965 #define NETMAP_TX_TIMER_US 90
968 * Reconcile kernel and user view of the transmit ring.
970 * All information is in the kring.
971 * Userspace wants to send packets up to the one before kring->rhead,
972 * kernel knows kring->nr_hwcur is the first unsent packet.
974 * Here we push packets out (as many as possible), and possibly
975 * reclaim buffers from previously completed transmission.
977 * The caller (netmap) guarantees that there is only one instance
978 * running at any time. Any interference with other driver
979 * methods should be handled by the individual drivers.
982 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
984 struct netmap_adapter *na = kring->na;
986 struct netmap_ring *ring = kring->ring;
987 u_int nm_i; /* index into the netmap kring */
988 u_int nic_i; /* index into the NIC ring */
990 u_int const lim = kring->nkr_num_slots - 1;
991 u_int const head = kring->rhead;
992 struct if_pkt_info pi;
993 int tx_pkts = 0, tx_bytes = 0;
996 * interrupts on every tx packet are expensive so request
997 * them every half ring, or where NS_REPORT is set
999 u_int report_frequency = kring->nkr_num_slots >> 1;
1000 /* device-specific */
1001 if_ctx_t ctx = ifp->if_softc;
1002 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1005 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1008 * First part: process new packets to send.
1009 * nm_i is the current index in the netmap kring,
1010 * nic_i is the corresponding index in the NIC ring.
1012 * If we have packets to send (nm_i != head)
1013 * iterate over the netmap ring, fetch length and update
1014 * the corresponding slot in the NIC ring. Some drivers also
1015 * need to update the buffer's physical address in the NIC slot
1016 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1018 * The netmap_reload_map() calls is especially expensive,
1019 * even when (as in this case) the tag is 0, so do only
1020 * when the buffer has actually changed.
1022 * If possible do not set the report/intr bit on all slots,
1023 * but only a few times per ring or when NS_REPORT is set.
1025 * Finally, on 10G and faster drivers, it might be useful
1026 * to prefetch the next slot and txr entry.
1029 nm_i = kring->nr_hwcur;
1030 if (nm_i != head) { /* we have new packets to send */
1031 uint32_t pkt_len = 0, seg_idx = 0;
1032 int nic_i_start = -1, flags = 0;
1034 pi.ipi_segs = txq->ift_segs;
1035 pi.ipi_qsidx = kring->ring_id;
1036 nic_i = netmap_idx_k2n(kring, nm_i);
1038 __builtin_prefetch(&ring->slot[nm_i]);
1039 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1040 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1042 for (n = 0; nm_i != head; n++) {
1043 struct netmap_slot *slot = &ring->slot[nm_i];
1044 u_int len = slot->len;
1046 void *addr = PNMB(na, slot, &paddr);
1048 flags |= (slot->flags & NS_REPORT ||
1049 nic_i == 0 || nic_i == report_frequency) ?
1053 * If this is the first packet fragment, save the
1054 * index of the first NIC slot for later.
1056 if (nic_i_start < 0)
1057 nic_i_start = nic_i;
1059 pi.ipi_segs[seg_idx].ds_addr = paddr;
1060 pi.ipi_segs[seg_idx].ds_len = len;
1066 if (!(slot->flags & NS_MOREFRAG)) {
1067 pi.ipi_len = pkt_len;
1068 pi.ipi_nsegs = seg_idx;
1069 pi.ipi_pidx = nic_i_start;
1071 pi.ipi_flags = flags;
1073 /* Prepare the NIC TX ring. */
1074 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1075 DBG_COUNTER_INC(tx_encap);
1077 /* Update transmit counters */
1078 tx_bytes += pi.ipi_len;
1081 /* Reinit per-packet info for the next one. */
1082 flags = seg_idx = pkt_len = 0;
1086 /* prefetch for next round */
1087 __builtin_prefetch(&ring->slot[nm_i + 1]);
1088 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1089 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1091 NM_CHECK_ADDR_LEN(na, addr, len);
1093 if (slot->flags & NS_BUF_CHANGED) {
1094 /* buffer has changed, reload map */
1095 netmap_reload_map(na, txq->ift_buf_tag,
1096 txq->ift_sds.ifsd_map[nic_i], addr);
1098 /* make sure changes to the buffer are synced */
1099 bus_dmamap_sync(txq->ift_buf_tag,
1100 txq->ift_sds.ifsd_map[nic_i],
1101 BUS_DMASYNC_PREWRITE);
1103 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1104 nm_i = nm_next(nm_i, lim);
1105 nic_i = nm_next(nic_i, lim);
1107 kring->nr_hwcur = nm_i;
1109 /* synchronize the NIC ring */
1110 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1113 /* (re)start the tx unit up to slot nic_i (excluded) */
1114 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1118 * Second part: reclaim buffers for completed transmissions.
1120 * If there are unclaimed buffers, attempt to reclaim them.
1121 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1122 * trigger a per-tx-queue timer to try again later.
1124 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1125 if (iflib_tx_credits_update(ctx, txq)) {
1126 /* some tx completed, increment avail */
1127 nic_i = txq->ift_cidx_processed;
1128 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1132 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1133 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1134 callout_reset_sbt_on(&txq->ift_netmap_timer,
1135 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1136 iflib_netmap_timer, txq,
1137 txq->ift_netmap_timer.c_cpu, 0);
1140 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes);
1141 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts);
1147 * Reconcile kernel and user view of the receive ring.
1148 * Same as for the txsync, this routine must be efficient.
1149 * The caller guarantees a single invocations, but races against
1150 * the rest of the driver should be handled here.
1152 * On call, kring->rhead is the first packet that userspace wants
1153 * to keep, and kring->rcur is the wakeup point.
1154 * The kernel has previously reported packets up to kring->rtail.
1156 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1157 * of whether or not we received an interrupt.
1160 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1162 struct netmap_adapter *na = kring->na;
1163 struct netmap_ring *ring = kring->ring;
1165 uint32_t nm_i; /* index into the netmap ring */
1166 uint32_t nic_i; /* index into the NIC ring */
1168 u_int const lim = kring->nkr_num_slots - 1;
1169 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1170 int i = 0, rx_bytes = 0, rx_pkts = 0;
1172 if_ctx_t ctx = ifp->if_softc;
1173 if_shared_ctx_t sctx = ctx->ifc_sctx;
1174 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1175 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1176 iflib_fl_t fl = &rxq->ifr_fl[0];
1177 struct if_rxd_info ri;
1181 * netmap only uses free list 0, to avoid out of order consumption
1182 * of receive buffers
1185 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1186 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1189 * First part: import newly received packets.
1191 * nm_i is the index of the next free slot in the netmap ring,
1192 * nic_i is the index of the next received packet in the NIC ring
1193 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1194 * differ in case if_init() has been called while
1195 * in netmap mode. For the receive ring we have
1197 * nic_i = fl->ifl_cidx;
1198 * nm_i = kring->nr_hwtail (previous)
1200 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1202 * fl->ifl_cidx is set to 0 on a ring reinit
1204 if (netmap_no_pendintr || force_update) {
1205 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1206 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1207 int crclen = iflib_crcstrip ? 0 : 4;
1211 * For the free list consumer index, we use the same
1212 * logic as in iflib_rxeof().
1215 cidxp = &rxq->ifr_cq_cidx;
1217 cidxp = &fl->ifl_cidx;
1218 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1219 rxq->ifr_id, *cidxp, USHRT_MAX);
1221 nic_i = fl->ifl_cidx;
1222 nm_i = netmap_idx_n2k(kring, nic_i);
1223 MPASS(nm_i == kring->nr_hwtail);
1224 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1226 ri.iri_frags = rxq->ifr_frags;
1227 ri.iri_qsidx = kring->ring_id;
1228 ri.iri_ifp = ctx->ifc_ifp;
1229 ri.iri_cidx = *cidxp;
1231 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1232 for (i = 0; i < ri.iri_nfrags; i++) {
1234 ring->slot[nm_i].len = 0;
1235 ring->slot[nm_i].flags = 0;
1237 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1238 if (i == (ri.iri_nfrags - 1)) {
1239 ring->slot[nm_i].len -= crclen;
1240 ring->slot[nm_i].flags = 0;
1242 /* Update receive counters */
1243 rx_bytes += ri.iri_len;
1246 ring->slot[nm_i].flags = NS_MOREFRAG;
1249 bus_dmamap_sync(fl->ifl_buf_tag,
1250 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1251 nm_i = nm_next(nm_i, lim);
1252 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1256 *cidxp = ri.iri_cidx;
1257 while (*cidxp >= scctx->isc_nrxd[0])
1258 *cidxp -= scctx->isc_nrxd[0];
1262 if (n) { /* update the state variables */
1263 if (netmap_no_pendintr && !force_update) {
1266 iflib_rx_miss_bufs += n;
1268 kring->nr_hwtail = nm_i;
1270 kring->nr_kflags &= ~NKR_PENDINTR;
1273 * Second part: skip past packets that userspace has released.
1274 * (kring->nr_hwcur to head excluded),
1275 * and make the buffers available for reception.
1276 * As usual nm_i is the index in the netmap ring,
1277 * nic_i is the index in the NIC ring, and
1278 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1280 netmap_fl_refill(rxq, kring, false);
1282 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
1283 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
1289 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1291 if_ctx_t ctx = na->ifp->if_softc;
1295 IFDI_INTR_ENABLE(ctx);
1297 IFDI_INTR_DISABLE(ctx);
1303 iflib_netmap_attach(if_ctx_t ctx)
1305 struct netmap_adapter na;
1307 bzero(&na, sizeof(na));
1309 na.ifp = ctx->ifc_ifp;
1310 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG;
1311 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1312 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1314 na.num_tx_desc = iflib_num_tx_descs(ctx);
1315 na.num_rx_desc = iflib_num_rx_descs(ctx);
1316 na.nm_txsync = iflib_netmap_txsync;
1317 na.nm_rxsync = iflib_netmap_rxsync;
1318 na.nm_register = iflib_netmap_register;
1319 na.nm_intr = iflib_netmap_intr;
1320 na.nm_config = iflib_netmap_config;
1321 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1322 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1323 return (netmap_attach(&na));
1327 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1329 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1330 struct netmap_slot *slot;
1332 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1335 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1337 * In netmap mode, set the map for the packet buffer.
1338 * NOTE: Some drivers (not this one) also need to set
1339 * the physical buffer address in the NIC ring.
1340 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1341 * netmap slot index, si
1343 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1344 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1345 NMB(na, slot + si));
1351 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1353 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1354 struct netmap_kring *kring;
1355 struct netmap_slot *slot;
1357 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1360 kring = na->rx_rings[rxq->ifr_id];
1361 netmap_fl_refill(rxq, kring, true);
1366 iflib_netmap_timer(void *arg)
1368 iflib_txq_t txq = arg;
1369 if_ctx_t ctx = txq->ift_ctx;
1372 * Wake up the netmap application, to give it a chance to
1373 * call txsync and reclaim more completed TX buffers.
1375 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1378 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1381 #define iflib_netmap_txq_init(ctx, txq) (0)
1382 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1383 #define iflib_netmap_detach(ifp)
1384 #define netmap_enable_all_rings(ifp)
1385 #define netmap_disable_all_rings(ifp)
1387 #define iflib_netmap_attach(ctx) (0)
1388 #define netmap_rx_irq(ifp, qid, budget) (0)
1391 #if defined(__i386__) || defined(__amd64__)
1392 static __inline void
1395 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1397 static __inline void
1398 prefetch2cachelines(void *x)
1400 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1401 #if (CACHE_LINE_SIZE < 128)
1402 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1407 #define prefetch2cachelines(x)
1411 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1415 fl = &rxq->ifr_fl[flid];
1416 iru->iru_paddrs = fl->ifl_bus_addrs;
1417 iru->iru_idxs = fl->ifl_rxd_idxs;
1418 iru->iru_qsidx = rxq->ifr_id;
1419 iru->iru_buf_size = fl->ifl_buf_size;
1420 iru->iru_flidx = fl->ifl_id;
1424 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1428 *(bus_addr_t *) arg = segs[0].ds_addr;
1432 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1435 device_t dev = ctx->ifc_dev;
1437 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1438 align, 0, /* alignment, bounds */
1439 BUS_SPACE_MAXADDR, /* lowaddr */
1440 BUS_SPACE_MAXADDR, /* highaddr */
1441 NULL, NULL, /* filter, filterarg */
1444 size, /* maxsegsize */
1445 BUS_DMA_ALLOCNOW, /* flags */
1446 NULL, /* lockfunc */
1451 "%s: bus_dma_tag_create failed: %d\n",
1456 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1457 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1460 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1461 __func__, (uintmax_t)size, err);
1465 dma->idi_paddr = IF_BAD_DMA;
1466 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1467 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1468 if (err || dma->idi_paddr == IF_BAD_DMA) {
1470 "%s: bus_dmamap_load failed: %d\n",
1475 dma->idi_size = size;
1479 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1481 bus_dma_tag_destroy(dma->idi_tag);
1483 dma->idi_tag = NULL;
1489 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1491 if_shared_ctx_t sctx = ctx->ifc_sctx;
1493 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1495 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1499 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1502 iflib_dma_info_t *dmaiter;
1505 for (i = 0; i < count; i++, dmaiter++) {
1506 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1510 iflib_dma_free_multi(dmalist, i);
1515 iflib_dma_free(iflib_dma_info_t dma)
1517 if (dma->idi_tag == NULL)
1519 if (dma->idi_paddr != IF_BAD_DMA) {
1520 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1521 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1522 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1523 dma->idi_paddr = IF_BAD_DMA;
1525 if (dma->idi_vaddr != NULL) {
1526 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1527 dma->idi_vaddr = NULL;
1529 bus_dma_tag_destroy(dma->idi_tag);
1530 dma->idi_tag = NULL;
1534 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1537 iflib_dma_info_t *dmaiter = dmalist;
1539 for (i = 0; i < count; i++, dmaiter++)
1540 iflib_dma_free(*dmaiter);
1544 iflib_fast_intr(void *arg)
1546 iflib_filter_info_t info = arg;
1547 struct grouptask *gtask = info->ifi_task;
1550 DBG_COUNTER_INC(fast_intrs);
1551 if (info->ifi_filter != NULL) {
1552 result = info->ifi_filter(info->ifi_filter_arg);
1553 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1557 GROUPTASK_ENQUEUE(gtask);
1558 return (FILTER_HANDLED);
1562 iflib_fast_intr_rxtx(void *arg)
1564 iflib_filter_info_t info = arg;
1565 struct grouptask *gtask = info->ifi_task;
1567 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1570 int i, cidx, result;
1572 bool intr_enable, intr_legacy;
1574 DBG_COUNTER_INC(fast_intrs);
1575 if (info->ifi_filter != NULL) {
1576 result = info->ifi_filter(info->ifi_filter_arg);
1577 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1582 sc = ctx->ifc_softc;
1583 intr_enable = false;
1584 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1585 MPASS(rxq->ifr_ntxqirq);
1586 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1587 txqid = rxq->ifr_txqid[i];
1588 txq = &ctx->ifc_txqs[txqid];
1589 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1590 BUS_DMASYNC_POSTREAD);
1591 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1595 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1598 GROUPTASK_ENQUEUE(&txq->ift_task);
1600 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1601 cidx = rxq->ifr_cq_cidx;
1603 cidx = rxq->ifr_fl[0].ifl_cidx;
1604 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1605 GROUPTASK_ENQUEUE(gtask);
1610 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1611 DBG_COUNTER_INC(rx_intr_enables);
1614 IFDI_INTR_ENABLE(ctx);
1615 return (FILTER_HANDLED);
1619 iflib_fast_intr_ctx(void *arg)
1621 iflib_filter_info_t info = arg;
1622 struct grouptask *gtask = info->ifi_task;
1625 DBG_COUNTER_INC(fast_intrs);
1626 if (info->ifi_filter != NULL) {
1627 result = info->ifi_filter(info->ifi_filter_arg);
1628 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1632 GROUPTASK_ENQUEUE(gtask);
1633 return (FILTER_HANDLED);
1637 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1638 driver_filter_t filter, driver_intr_t handler, void *arg,
1641 struct resource *res;
1643 device_t dev = ctx->ifc_dev;
1647 if (ctx->ifc_flags & IFC_LEGACY)
1648 flags |= RF_SHAREABLE;
1651 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1654 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1658 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1659 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1660 filter, handler, arg, &tag);
1663 "failed to setup interrupt for rid %d, name %s: %d\n",
1664 rid, name ? name : "unknown", rc);
1667 bus_describe_intr(dev, res, tag, "%s", name);
1673 /*********************************************************************
1675 * Allocate DMA resources for TX buffers as well as memory for the TX
1676 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1677 * iflib_sw_tx_desc_array structure, storing all the information that
1678 * is needed to transmit a packet on the wire. This is called only
1679 * once at attach, setup is done every reset.
1681 **********************************************************************/
1683 iflib_txsd_alloc(iflib_txq_t txq)
1685 if_ctx_t ctx = txq->ift_ctx;
1686 if_shared_ctx_t sctx = ctx->ifc_sctx;
1687 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1688 device_t dev = ctx->ifc_dev;
1689 bus_size_t tsomaxsize;
1690 int err, nsegments, ntsosegments;
1693 nsegments = scctx->isc_tx_nsegments;
1694 ntsosegments = scctx->isc_tx_tso_segments_max;
1695 tsomaxsize = scctx->isc_tx_tso_size_max;
1696 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1697 tsomaxsize += sizeof(struct ether_vlan_header);
1698 MPASS(scctx->isc_ntxd[0] > 0);
1699 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1700 MPASS(nsegments > 0);
1701 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1702 MPASS(ntsosegments > 0);
1703 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1707 * Set up DMA tags for TX buffers.
1709 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1710 1, 0, /* alignment, bounds */
1711 BUS_SPACE_MAXADDR, /* lowaddr */
1712 BUS_SPACE_MAXADDR, /* highaddr */
1713 NULL, NULL, /* filter, filterarg */
1714 sctx->isc_tx_maxsize, /* maxsize */
1715 nsegments, /* nsegments */
1716 sctx->isc_tx_maxsegsize, /* maxsegsize */
1718 NULL, /* lockfunc */
1719 NULL, /* lockfuncarg */
1720 &txq->ift_buf_tag))) {
1721 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1722 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1723 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1726 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1727 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1728 1, 0, /* alignment, bounds */
1729 BUS_SPACE_MAXADDR, /* lowaddr */
1730 BUS_SPACE_MAXADDR, /* highaddr */
1731 NULL, NULL, /* filter, filterarg */
1732 tsomaxsize, /* maxsize */
1733 ntsosegments, /* nsegments */
1734 sctx->isc_tso_maxsegsize,/* maxsegsize */
1736 NULL, /* lockfunc */
1737 NULL, /* lockfuncarg */
1738 &txq->ift_tso_buf_tag))) {
1739 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1744 /* Allocate memory for the TX mbuf map. */
1745 if (!(txq->ift_sds.ifsd_m =
1746 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1747 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1748 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1754 * Create the DMA maps for TX buffers.
1756 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1757 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1758 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1760 "Unable to allocate TX buffer DMA map memory\n");
1764 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1765 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1766 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1768 "Unable to allocate TSO TX buffer map memory\n");
1772 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1773 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1774 &txq->ift_sds.ifsd_map[i]);
1776 device_printf(dev, "Unable to create TX DMA map\n");
1781 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1782 &txq->ift_sds.ifsd_tso_map[i]);
1784 device_printf(dev, "Unable to create TSO TX DMA map\n");
1790 /* We free all, it handles case where we are in the middle */
1791 iflib_tx_structures_free(ctx);
1796 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1800 if (txq->ift_sds.ifsd_map != NULL) {
1801 map = txq->ift_sds.ifsd_map[i];
1802 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1803 bus_dmamap_unload(txq->ift_buf_tag, map);
1804 bus_dmamap_destroy(txq->ift_buf_tag, map);
1805 txq->ift_sds.ifsd_map[i] = NULL;
1808 if (txq->ift_sds.ifsd_tso_map != NULL) {
1809 map = txq->ift_sds.ifsd_tso_map[i];
1810 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1811 BUS_DMASYNC_POSTWRITE);
1812 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1813 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1814 txq->ift_sds.ifsd_tso_map[i] = NULL;
1819 iflib_txq_destroy(iflib_txq_t txq)
1821 if_ctx_t ctx = txq->ift_ctx;
1823 for (int i = 0; i < txq->ift_size; i++)
1824 iflib_txsd_destroy(ctx, txq, i);
1826 if (txq->ift_br != NULL) {
1827 ifmp_ring_free(txq->ift_br);
1831 mtx_destroy(&txq->ift_mtx);
1833 if (txq->ift_sds.ifsd_map != NULL) {
1834 free(txq->ift_sds.ifsd_map, M_IFLIB);
1835 txq->ift_sds.ifsd_map = NULL;
1837 if (txq->ift_sds.ifsd_tso_map != NULL) {
1838 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1839 txq->ift_sds.ifsd_tso_map = NULL;
1841 if (txq->ift_sds.ifsd_m != NULL) {
1842 free(txq->ift_sds.ifsd_m, M_IFLIB);
1843 txq->ift_sds.ifsd_m = NULL;
1845 if (txq->ift_buf_tag != NULL) {
1846 bus_dma_tag_destroy(txq->ift_buf_tag);
1847 txq->ift_buf_tag = NULL;
1849 if (txq->ift_tso_buf_tag != NULL) {
1850 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1851 txq->ift_tso_buf_tag = NULL;
1853 if (txq->ift_ifdi != NULL) {
1854 free(txq->ift_ifdi, M_IFLIB);
1859 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1863 mp = &txq->ift_sds.ifsd_m[i];
1867 if (txq->ift_sds.ifsd_map != NULL) {
1868 bus_dmamap_sync(txq->ift_buf_tag,
1869 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1870 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1872 if (txq->ift_sds.ifsd_tso_map != NULL) {
1873 bus_dmamap_sync(txq->ift_tso_buf_tag,
1874 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1875 bus_dmamap_unload(txq->ift_tso_buf_tag,
1876 txq->ift_sds.ifsd_tso_map[i]);
1879 DBG_COUNTER_INC(tx_frees);
1884 iflib_txq_setup(iflib_txq_t txq)
1886 if_ctx_t ctx = txq->ift_ctx;
1887 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1888 if_shared_ctx_t sctx = ctx->ifc_sctx;
1889 iflib_dma_info_t di;
1892 /* Set number of descriptors available */
1893 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1894 /* XXX make configurable */
1895 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1898 txq->ift_cidx_processed = 0;
1899 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1900 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1902 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1903 bzero((void *)di->idi_vaddr, di->idi_size);
1905 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1906 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1907 bus_dmamap_sync(di->idi_tag, di->idi_map,
1908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1912 /*********************************************************************
1914 * Allocate DMA resources for RX buffers as well as memory for the RX
1915 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1916 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1917 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1918 * Since we use use one entry in iflib_sw_rx_desc_array per received
1919 * packet, the maximum number of entries we'll need is equal to the
1920 * number of hardware receive descriptors that we've allocated.
1922 **********************************************************************/
1924 iflib_rxsd_alloc(iflib_rxq_t rxq)
1926 if_ctx_t ctx = rxq->ifr_ctx;
1927 if_shared_ctx_t sctx = ctx->ifc_sctx;
1928 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1929 device_t dev = ctx->ifc_dev;
1933 MPASS(scctx->isc_nrxd[0] > 0);
1934 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1937 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1938 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1939 /* Set up DMA tag for RX buffers. */
1940 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1941 1, 0, /* alignment, bounds */
1942 BUS_SPACE_MAXADDR, /* lowaddr */
1943 BUS_SPACE_MAXADDR, /* highaddr */
1944 NULL, NULL, /* filter, filterarg */
1945 sctx->isc_rx_maxsize, /* maxsize */
1946 sctx->isc_rx_nsegments, /* nsegments */
1947 sctx->isc_rx_maxsegsize, /* maxsegsize */
1949 NULL, /* lockfunc */
1954 "Unable to allocate RX DMA tag: %d\n", err);
1958 /* Allocate memory for the RX mbuf map. */
1959 if (!(fl->ifl_sds.ifsd_m =
1960 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1961 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1963 "Unable to allocate RX mbuf map memory\n");
1968 /* Allocate memory for the direct RX cluster pointer map. */
1969 if (!(fl->ifl_sds.ifsd_cl =
1970 (caddr_t *) malloc(sizeof(caddr_t) *
1971 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1973 "Unable to allocate RX cluster map memory\n");
1978 /* Allocate memory for the RX cluster bus address map. */
1979 if (!(fl->ifl_sds.ifsd_ba =
1980 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1981 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1983 "Unable to allocate RX bus address map memory\n");
1989 * Create the DMA maps for RX buffers.
1991 if (!(fl->ifl_sds.ifsd_map =
1992 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1994 "Unable to allocate RX buffer DMA map memory\n");
1998 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1999 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
2000 &fl->ifl_sds.ifsd_map[i]);
2002 device_printf(dev, "Unable to create RX buffer DMA map\n");
2010 iflib_rx_structures_free(ctx);
2015 * Internal service routines
2018 struct rxq_refill_cb_arg {
2020 bus_dma_segment_t seg;
2025 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2027 struct rxq_refill_cb_arg *cb_arg = arg;
2029 cb_arg->error = error;
2030 cb_arg->seg = segs[0];
2031 cb_arg->nseg = nseg;
2035 * iflib_fl_refill - refill an rxq free-buffer list
2036 * @ctx: the iflib context
2037 * @fl: the free list to refill
2038 * @count: the number of new buffers to allocate
2040 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2041 * The caller must assure that @count does not exceed the queue's capacity
2042 * minus one (since we always leave a descriptor unavailable).
2045 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2047 struct if_rxd_update iru;
2048 struct rxq_refill_cb_arg cb_arg;
2052 bus_dmamap_t *sd_map;
2053 bus_addr_t bus_addr, *sd_ba;
2054 int err, frag_idx, i, idx, n, pidx;
2057 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2059 sd_m = fl->ifl_sds.ifsd_m;
2060 sd_map = fl->ifl_sds.ifsd_map;
2061 sd_cl = fl->ifl_sds.ifsd_cl;
2062 sd_ba = fl->ifl_sds.ifsd_ba;
2063 pidx = fl->ifl_pidx;
2065 frag_idx = fl->ifl_fragidx;
2066 credits = fl->ifl_credits;
2071 MPASS(credits + n <= fl->ifl_size);
2073 if (pidx < fl->ifl_cidx)
2074 MPASS(pidx + n <= fl->ifl_cidx);
2075 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2076 MPASS(fl->ifl_gen == 0);
2077 if (pidx > fl->ifl_cidx)
2078 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2080 DBG_COUNTER_INC(fl_refills);
2082 DBG_COUNTER_INC(fl_refills_large);
2083 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2086 * We allocate an uninitialized mbuf + cluster, mbuf is
2087 * initialized after rx.
2089 * If the cluster is still set then we know a minimum sized
2090 * packet was received
2092 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2095 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2096 MPASS(frag_idx >= 0);
2097 if ((cl = sd_cl[frag_idx]) == NULL) {
2098 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2099 if (__predict_false(cl == NULL))
2103 MPASS(sd_map != NULL);
2104 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2105 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2107 if (__predict_false(err != 0 || cb_arg.error)) {
2108 uma_zfree(fl->ifl_zone, cl);
2112 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2113 sd_cl[frag_idx] = cl;
2115 fl->ifl_cl_enqueued++;
2118 bus_addr = sd_ba[frag_idx];
2120 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2121 BUS_DMASYNC_PREREAD);
2123 if (sd_m[frag_idx] == NULL) {
2124 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2125 if (__predict_false(m == NULL))
2129 bit_set(fl->ifl_rx_bitmap, frag_idx);
2131 fl->ifl_m_enqueued++;
2134 DBG_COUNTER_INC(rx_allocs);
2135 fl->ifl_rxd_idxs[i] = frag_idx;
2136 fl->ifl_bus_addrs[i] = bus_addr;
2139 MPASS(credits <= fl->ifl_size);
2140 if (++idx == fl->ifl_size) {
2146 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2147 iru.iru_pidx = pidx;
2149 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2151 fl->ifl_credits = credits;
2157 if (n < count - 1) {
2159 iru.iru_pidx = pidx;
2161 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2163 fl->ifl_credits = credits;
2165 DBG_COUNTER_INC(rxd_flush);
2166 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2167 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2168 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2169 fl->ifl_id, fl->ifl_pidx);
2170 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2171 fl->ifl_fragidx = frag_idx + 1;
2172 if (fl->ifl_fragidx == fl->ifl_size)
2173 fl->ifl_fragidx = 0;
2175 fl->ifl_fragidx = frag_idx;
2179 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2182 static inline uint8_t
2183 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2186 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2187 * This is important as it confuses most NICs. For instance,
2188 * Intel NICs have (per receive ring) RDH and RDT registers, where
2189 * RDH points to the next receive descriptor to be used by the NIC,
2190 * and RDT for the next receive descriptor to be published by the
2191 * driver to the NIC (RDT - 1 is thus the last valid one).
2192 * The condition RDH == RDT means no descriptors are available to
2193 * the NIC, and thus it would be ambiguous if it also meant that
2194 * all the descriptors are available to the NIC.
2196 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2198 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2201 MPASS(fl->ifl_credits <= fl->ifl_size);
2202 MPASS(reclaimable == delta);
2204 if (reclaimable > 0)
2205 return (iflib_fl_refill(ctx, fl, reclaimable));
2210 iflib_in_detach(if_ctx_t ctx)
2215 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2221 iflib_fl_bufs_free(iflib_fl_t fl)
2223 iflib_dma_info_t idi = fl->ifl_ifdi;
2224 bus_dmamap_t sd_map;
2227 for (i = 0; i < fl->ifl_size; i++) {
2228 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2229 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2231 if (*sd_cl != NULL) {
2232 sd_map = fl->ifl_sds.ifsd_map[i];
2233 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2234 BUS_DMASYNC_POSTREAD);
2235 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2236 uma_zfree(fl->ifl_zone, *sd_cl);
2238 if (*sd_m != NULL) {
2239 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2244 MPASS(*sd_m == NULL);
2247 fl->ifl_m_dequeued++;
2248 fl->ifl_cl_dequeued++;
2252 for (i = 0; i < fl->ifl_size; i++) {
2253 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2254 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2258 * Reset free list values
2260 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2261 bzero(idi->idi_vaddr, idi->idi_size);
2264 /*********************************************************************
2266 * Initialize a free list and its buffers.
2268 **********************************************************************/
2270 iflib_fl_setup(iflib_fl_t fl)
2272 iflib_rxq_t rxq = fl->ifl_rxq;
2273 if_ctx_t ctx = rxq->ifr_ctx;
2274 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2277 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2279 ** Free current RX buffer structs and their mbufs
2281 iflib_fl_bufs_free(fl);
2282 /* Now replenish the mbufs */
2283 MPASS(fl->ifl_credits == 0);
2284 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2285 if (scctx->isc_rxd_buf_size[qidx] != 0)
2286 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2288 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2290 * ifl_buf_size may be a driver-supplied value, so pull it up
2291 * to the selected mbuf size.
2293 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2294 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2295 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2296 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2297 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2300 * Avoid pre-allocating zillions of clusters to an idle card
2301 * potentially speeding up attach. In any case make sure
2302 * to leave a descriptor unavailable. See the comment in
2303 * iflib_fl_refill_all().
2305 MPASS(fl->ifl_size > 0);
2306 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2307 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2313 MPASS(fl->ifl_ifdi != NULL);
2314 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2315 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2319 /*********************************************************************
2321 * Free receive ring data structures
2323 **********************************************************************/
2325 iflib_rx_sds_free(iflib_rxq_t rxq)
2330 if (rxq->ifr_fl != NULL) {
2331 for (i = 0; i < rxq->ifr_nfl; i++) {
2332 fl = &rxq->ifr_fl[i];
2333 if (fl->ifl_buf_tag != NULL) {
2334 if (fl->ifl_sds.ifsd_map != NULL) {
2335 for (j = 0; j < fl->ifl_size; j++) {
2338 fl->ifl_sds.ifsd_map[j],
2339 BUS_DMASYNC_POSTREAD);
2342 fl->ifl_sds.ifsd_map[j]);
2345 fl->ifl_sds.ifsd_map[j]);
2348 bus_dma_tag_destroy(fl->ifl_buf_tag);
2349 fl->ifl_buf_tag = NULL;
2351 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2352 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2353 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2354 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2355 free(fl->ifl_rx_bitmap, M_IFLIB);
2356 fl->ifl_sds.ifsd_m = NULL;
2357 fl->ifl_sds.ifsd_cl = NULL;
2358 fl->ifl_sds.ifsd_ba = NULL;
2359 fl->ifl_sds.ifsd_map = NULL;
2360 fl->ifl_rx_bitmap = NULL;
2362 free(rxq->ifr_fl, M_IFLIB);
2364 free(rxq->ifr_ifdi, M_IFLIB);
2365 rxq->ifr_ifdi = NULL;
2366 rxq->ifr_cq_cidx = 0;
2374 iflib_timer(void *arg)
2376 iflib_txq_t txq = arg;
2377 if_ctx_t ctx = txq->ift_ctx;
2378 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2379 uint64_t this_tick = ticks;
2381 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2385 ** Check on the state of the TX queue(s), this
2386 ** can be done without the lock because its RO
2387 ** and the HUNG state will be static if set.
2389 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2390 txq->ift_last_timer_tick = this_tick;
2391 IFDI_TIMER(ctx, txq->ift_id);
2392 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2393 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2394 (sctx->isc_pause_frames == 0)))
2397 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2398 ifmp_ring_is_stalled(txq->ift_br)) {
2399 KASSERT(ctx->ifc_link_state == LINK_STATE_UP,
2400 ("queue can't be marked as hung if interface is down"));
2401 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2403 txq->ift_cleaned_prev = txq->ift_cleaned;
2405 /* handle any laggards */
2406 if (txq->ift_db_pending)
2407 GROUPTASK_ENQUEUE(&txq->ift_task);
2409 sctx->isc_pause_frames = 0;
2410 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2411 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2412 txq, txq->ift_timer.c_cpu);
2416 device_printf(ctx->ifc_dev,
2417 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2418 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2420 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2421 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2422 iflib_admin_intr_deferred(ctx);
2427 iflib_get_mbuf_size_for(unsigned int size)
2430 if (size <= MCLBYTES)
2433 return (MJUMPAGESIZE);
2437 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2439 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2442 * XXX don't set the max_frame_size to larger
2443 * than the hardware can handle
2445 ctx->ifc_rx_mbuf_sz =
2446 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2450 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2453 return (ctx->ifc_rx_mbuf_sz);
2457 iflib_init_locked(if_ctx_t ctx)
2459 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2460 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2461 if_t ifp = ctx->ifc_ifp;
2465 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2467 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2468 IFDI_INTR_DISABLE(ctx);
2471 * See iflib_stop(). Useful in case iflib_init_locked() is
2472 * called without first calling iflib_stop().
2474 netmap_disable_all_rings(ifp);
2476 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2477 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2478 /* Set hardware offload abilities */
2479 if_clearhwassist(ifp);
2480 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2481 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2482 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2483 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2484 if (if_getcapenable(ifp) & IFCAP_TSO4)
2485 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2486 if (if_getcapenable(ifp) & IFCAP_TSO6)
2487 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2489 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2491 callout_stop(&txq->ift_timer);
2493 callout_stop(&txq->ift_netmap_timer);
2494 #endif /* DEV_NETMAP */
2495 CALLOUT_UNLOCK(txq);
2496 iflib_netmap_txq_init(ctx, txq);
2500 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2501 * that drivers can use the value when setting up the hardware receive
2504 iflib_calc_rx_mbuf_sz(ctx);
2507 i = if_getdrvflags(ifp);
2510 MPASS(if_getdrvflags(ifp) == i);
2511 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2512 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2513 /* This rxq is in netmap mode. Skip normal init. */
2516 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2517 if (iflib_fl_setup(fl)) {
2518 device_printf(ctx->ifc_dev,
2519 "setting up free list %d failed - "
2520 "check cluster settings\n", j);
2526 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2527 IFDI_INTR_ENABLE(ctx);
2528 txq = ctx->ifc_txqs;
2529 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2530 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2531 txq->ift_timer.c_cpu);
2533 /* Re-enable txsync/rxsync. */
2534 netmap_enable_all_rings(ifp);
2538 iflib_media_change(if_t ifp)
2540 if_ctx_t ctx = if_getsoftc(ifp);
2544 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2545 iflib_if_init_locked(ctx);
2551 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2553 if_ctx_t ctx = if_getsoftc(ifp);
2556 IFDI_UPDATE_ADMIN_STATUS(ctx);
2557 IFDI_MEDIA_STATUS(ctx, ifmr);
2562 iflib_stop(if_ctx_t ctx)
2564 iflib_txq_t txq = ctx->ifc_txqs;
2565 iflib_rxq_t rxq = ctx->ifc_rxqs;
2566 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2567 if_shared_ctx_t sctx = ctx->ifc_sctx;
2568 iflib_dma_info_t di;
2572 /* Tell the stack that the interface is no longer active */
2573 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2575 IFDI_INTR_DISABLE(ctx);
2581 * Stop any pending txsync/rxsync and prevent new ones
2582 * form starting. Processes blocked in poll() will get
2585 netmap_disable_all_rings(ctx->ifc_ifp);
2587 iflib_debug_reset();
2588 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2589 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2590 /* make sure all transmitters have completed before proceeding XXX */
2593 callout_stop(&txq->ift_timer);
2595 callout_stop(&txq->ift_netmap_timer);
2596 #endif /* DEV_NETMAP */
2597 CALLOUT_UNLOCK(txq);
2599 /* clean any enqueued buffers */
2600 iflib_ifmp_purge(txq);
2601 /* Free any existing tx buffers. */
2602 for (j = 0; j < txq->ift_size; j++) {
2603 iflib_txsd_free(ctx, txq, j);
2605 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2606 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2607 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2608 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2609 txq->ift_pullups = 0;
2610 ifmp_ring_reset_stats(txq->ift_br);
2611 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2612 bzero((void *)di->idi_vaddr, di->idi_size);
2614 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2615 /* make sure all transmitters have completed before proceeding XXX */
2617 rxq->ifr_cq_cidx = 0;
2618 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2619 bzero((void *)di->idi_vaddr, di->idi_size);
2620 /* also resets the free lists pidx/cidx */
2621 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2622 iflib_fl_bufs_free(fl);
2626 static inline caddr_t
2627 calc_next_rxd(iflib_fl_t fl, int cidx)
2631 caddr_t start, end, cur, next;
2633 nrxd = fl->ifl_size;
2634 size = fl->ifl_rxd_size;
2635 start = fl->ifl_ifdi->idi_vaddr;
2637 if (__predict_false(size == 0))
2639 cur = start + size*cidx;
2640 end = start + size*nrxd;
2641 next = CACHE_PTR_NEXT(cur);
2642 return (next < end ? next : start);
2646 prefetch_pkts(iflib_fl_t fl, int cidx)
2649 int nrxd = fl->ifl_size;
2652 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2653 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2654 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2655 next_rxd = calc_next_rxd(fl, cidx);
2657 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2658 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2659 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2660 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2661 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2662 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2663 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2664 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2667 static struct mbuf *
2668 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2669 int *pf_rv, if_rxd_info_t ri)
2675 int flid, cidx, len, next;
2678 flid = irf->irf_flid;
2679 cidx = irf->irf_idx;
2680 fl = &rxq->ifr_fl[flid];
2682 m = fl->ifl_sds.ifsd_m[cidx];
2683 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2686 fl->ifl_m_dequeued++;
2688 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2689 prefetch_pkts(fl, cidx);
2690 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2691 prefetch(&fl->ifl_sds.ifsd_map[next]);
2692 map = fl->ifl_sds.ifsd_map[cidx];
2694 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2696 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2697 irf->irf_len != 0) {
2698 payload = *sd->ifsd_cl;
2699 payload += ri->iri_pad;
2700 len = ri->iri_len - ri->iri_pad;
2701 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2702 len | PFIL_MEMPTR | PFIL_IN, NULL);
2707 * The filter ate it. Everything is recycled.
2712 case PFIL_REALLOCED:
2714 * The filter copied it. Everything is recycled.
2716 m = pfil_mem2mbuf(payload);
2721 * Filter said it was OK, so receive like
2724 fl->ifl_sds.ifsd_m[cidx] = NULL;
2730 fl->ifl_sds.ifsd_m[cidx] = NULL;
2735 if (unload && irf->irf_len != 0)
2736 bus_dmamap_unload(fl->ifl_buf_tag, map);
2737 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2738 if (__predict_false(fl->ifl_cidx == 0))
2740 bit_clear(fl->ifl_rx_bitmap, cidx);
2744 static struct mbuf *
2745 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2747 struct mbuf *m, *mh, *mt;
2749 int *pf_rv_ptr, flags, i, padlen;
2758 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2761 MPASS(*sd->ifsd_cl != NULL);
2764 * Exclude zero-length frags & frags from
2765 * packets the filter has consumed or dropped
2767 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2768 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2770 /* everything saved here */
2775 /* XXX we can save the cluster here, but not the mbuf */
2776 m_init(m, M_NOWAIT, MT_DATA, 0);
2781 flags = M_PKTHDR|M_EXT;
2783 padlen = ri->iri_pad;
2788 /* assuming padding is only on the first fragment */
2792 *sd->ifsd_cl = NULL;
2794 /* Can these two be made one ? */
2795 m_init(m, M_NOWAIT, MT_DATA, flags);
2796 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2798 * These must follow m_init and m_cljset
2800 m->m_data += padlen;
2801 ri->iri_len -= padlen;
2802 m->m_len = ri->iri_frags[i].irf_len;
2803 } while (++i < ri->iri_nfrags);
2809 * Process one software descriptor
2811 static struct mbuf *
2812 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2818 /* should I merge this back in now that the two paths are basically duplicated? */
2819 if (ri->iri_nfrags == 1 &&
2820 ri->iri_frags[0].irf_len != 0 &&
2821 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2822 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2824 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2826 if (pf_rv == PFIL_PASS) {
2827 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2828 #ifndef __NO_STRICT_ALIGNMENT
2832 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2833 m->m_len = ri->iri_frags[0].irf_len;
2836 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2839 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2842 m->m_pkthdr.len = ri->iri_len;
2843 m->m_pkthdr.rcvif = ri->iri_ifp;
2844 m->m_flags |= ri->iri_flags;
2845 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2846 m->m_pkthdr.flowid = ri->iri_flowid;
2847 M_HASHTYPE_SET(m, ri->iri_rsstype);
2848 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2849 m->m_pkthdr.csum_data = ri->iri_csum_data;
2853 #if defined(INET6) || defined(INET)
2855 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2857 CURVNET_SET(lc->ifp->if_vnet);
2859 *v6 = V_ip6_forwarding;
2862 *v4 = V_ipforwarding;
2868 * Returns true if it's possible this packet could be LROed.
2869 * if it returns false, it is guaranteed that tcp_lro_rx()
2870 * would not return zero.
2873 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2875 struct ether_header *eh;
2877 eh = mtod(m, struct ether_header *);
2878 switch (eh->ether_type) {
2880 case htons(ETHERTYPE_IPV6):
2881 return (!v6_forwarding);
2884 case htons(ETHERTYPE_IP):
2885 return (!v4_forwarding);
2893 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2899 _task_fn_rx_watchdog(void *context)
2901 iflib_rxq_t rxq = context;
2903 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2907 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2910 if_ctx_t ctx = rxq->ifr_ctx;
2911 if_shared_ctx_t sctx = ctx->ifc_sctx;
2912 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2915 struct if_rxd_info ri;
2916 int err, budget_left, rx_bytes, rx_pkts;
2919 bool v4_forwarding, v6_forwarding, lro_possible;
2923 * XXX early demux data packets so that if_input processing only handles
2924 * acks in interrupt context
2926 struct mbuf *m, *mh, *mt, *mf;
2930 lro_possible = v4_forwarding = v6_forwarding = false;
2934 rx_pkts = rx_bytes = 0;
2935 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2936 cidxp = &rxq->ifr_cq_cidx;
2938 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2939 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2940 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2941 retval |= iflib_fl_refill_all(ctx, fl);
2942 DBG_COUNTER_INC(rx_unavail);
2946 /* pfil needs the vnet to be set */
2947 CURVNET_SET_QUIET(ifp->if_vnet);
2948 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2949 if (__predict_false(!CTX_ACTIVE(ctx))) {
2950 DBG_COUNTER_INC(rx_ctx_inactive);
2954 * Reset client set fields to their default values
2957 ri.iri_qsidx = rxq->ifr_id;
2958 ri.iri_cidx = *cidxp;
2960 ri.iri_frags = rxq->ifr_frags;
2961 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2966 rx_bytes += ri.iri_len;
2967 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2968 *cidxp = ri.iri_cidx;
2969 /* Update our consumer index */
2970 /* XXX NB: shurd - check if this is still safe */
2971 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2972 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2973 /* was this only a completion queue message? */
2974 if (__predict_false(ri.iri_nfrags == 0))
2977 MPASS(ri.iri_nfrags != 0);
2978 MPASS(ri.iri_len != 0);
2980 /* will advance the cidx on the corresponding free lists */
2981 m = iflib_rxd_pkt_get(rxq, &ri);
2984 if (avail == 0 && budget_left)
2985 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2987 if (__predict_false(m == NULL))
2990 /* imm_pkt: -- cxgb */
2999 /* make sure that we can refill faster than drain */
3000 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3001 retval |= iflib_fl_refill_all(ctx, fl);
3003 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
3005 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
3007 while (mh != NULL) {
3010 m->m_nextpkt = NULL;
3011 #ifndef __NO_STRICT_ALIGNMENT
3012 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
3015 #if defined(INET6) || defined(INET)
3017 if (!lro_possible) {
3018 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
3019 if (lro_possible && mf != NULL) {
3020 ifp->if_input(ifp, mf);
3021 DBG_COUNTER_INC(rx_if_input);
3025 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
3026 (CSUM_L4_CALC|CSUM_L4_VALID)) {
3027 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
3033 ifp->if_input(ifp, m);
3034 DBG_COUNTER_INC(rx_if_input);
3045 ifp->if_input(ifp, mf);
3046 DBG_COUNTER_INC(rx_if_input);
3049 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3050 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3053 * Flush any outstanding LRO work
3055 #if defined(INET6) || defined(INET)
3056 tcp_lro_flush_all(&rxq->ifr_lc);
3058 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3059 retval |= IFLIB_RXEOF_MORE;
3063 ctx->ifc_flags |= IFC_DO_RESET;
3064 iflib_admin_intr_deferred(ctx);
3069 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
3070 static inline qidx_t
3071 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3073 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3074 qidx_t minthresh = txq->ift_size / 8;
3075 if (in_use > 4*minthresh)
3076 return (notify_count);
3077 if (in_use > 2*minthresh)
3078 return (notify_count >> 1);
3079 if (in_use > minthresh)
3080 return (notify_count >> 3);
3084 static inline qidx_t
3085 txq_max_rs_deferred(iflib_txq_t txq)
3087 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3088 qidx_t minthresh = txq->ift_size / 8;
3089 if (txq->ift_in_use > 4*minthresh)
3090 return (notify_count);
3091 if (txq->ift_in_use > 2*minthresh)
3092 return (notify_count >> 1);
3093 if (txq->ift_in_use > minthresh)
3094 return (notify_count >> 2);
3098 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3099 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3101 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3102 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3103 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3105 /* forward compatibility for cxgb */
3106 #define FIRST_QSET(ctx) 0
3107 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3108 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3109 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3110 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3112 /* XXX we should be setting this to something other than zero */
3113 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3114 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3115 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3118 iflib_txd_db_check(iflib_txq_t txq, int ring)
3120 if_ctx_t ctx = txq->ift_ctx;
3123 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3125 /* force || threshold exceeded || at the edge of the ring */
3126 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) {
3129 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3130 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3131 * producer index explicitly (INTC).
3133 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3134 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3135 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3136 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3139 * Absent bugs there are zero packets pending so reset pending counts to zero.
3141 txq->ift_db_pending = txq->ift_npending = 0;
3149 print_pkt(if_pkt_info_t pi)
3151 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3152 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3153 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3154 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3155 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3156 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3160 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3161 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3162 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3163 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3166 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3168 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3169 struct ether_vlan_header *eh;
3173 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3174 M_WRITABLE(m) == 0) {
3175 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3179 DBG_COUNTER_INC(tx_frees);
3185 * Determine where frame payload starts.
3186 * Jump over vlan headers if already present,
3187 * helpful for QinQ too.
3189 if (__predict_false(m->m_len < sizeof(*eh))) {
3191 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3194 eh = mtod(m, struct ether_vlan_header *);
3195 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3196 pi->ipi_etype = ntohs(eh->evl_proto);
3197 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3199 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3200 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3203 switch (pi->ipi_etype) {
3208 struct ip *ip = NULL;
3209 struct tcphdr *th = NULL;
3212 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3213 if (__predict_false(m->m_len < minthlen)) {
3215 * if this code bloat is causing too much of a hit
3216 * move it to a separate function and mark it noinline
3218 if (m->m_len == pi->ipi_ehdrlen) {
3221 if (n->m_len >= sizeof(*ip)) {
3222 ip = (struct ip *)n->m_data;
3223 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3224 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3227 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3229 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3233 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3235 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3236 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3237 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3240 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3241 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3242 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3244 pi->ipi_ip_hlen = ip->ip_hl << 2;
3245 pi->ipi_ipproto = ip->ip_p;
3246 pi->ipi_flags |= IPI_TX_IPV4;
3248 /* TCP checksum offload may require TCP header length */
3249 if (IS_TX_OFFLOAD4(pi)) {
3250 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3251 if (__predict_false(th == NULL)) {
3253 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3255 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3257 pi->ipi_tcp_hflags = th->th_flags;
3258 pi->ipi_tcp_hlen = th->th_off << 2;
3259 pi->ipi_tcp_seq = th->th_seq;
3262 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3265 * TSO always requires hardware checksum offload.
3267 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3268 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3269 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3270 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3271 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3273 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3277 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3284 case ETHERTYPE_IPV6:
3286 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3288 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3290 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3292 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3295 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3297 /* XXX-BZ this will go badly in case of ext hdrs. */
3298 pi->ipi_ipproto = ip6->ip6_nxt;
3299 pi->ipi_flags |= IPI_TX_IPV6;
3301 /* TCP checksum offload may require TCP header length */
3302 if (IS_TX_OFFLOAD6(pi)) {
3303 if (pi->ipi_ipproto == IPPROTO_TCP) {
3304 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3306 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3309 pi->ipi_tcp_hflags = th->th_flags;
3310 pi->ipi_tcp_hlen = th->th_off << 2;
3311 pi->ipi_tcp_seq = th->th_seq;
3314 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3317 * TSO always requires hardware checksum offload.
3319 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3320 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3321 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3328 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3329 pi->ipi_ip_hlen = 0;
3338 * If dodgy hardware rejects the scatter gather chain we've handed it
3339 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3342 static __noinline struct mbuf *
3343 iflib_remove_mbuf(iflib_txq_t txq)
3346 struct mbuf *m, **ifsd_m;
3348 ifsd_m = txq->ift_sds.ifsd_m;
3349 ntxd = txq->ift_size;
3350 pidx = txq->ift_pidx & (ntxd - 1);
3351 ifsd_m = txq->ift_sds.ifsd_m;
3353 ifsd_m[pidx] = NULL;
3354 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3355 if (txq->ift_sds.ifsd_tso_map != NULL)
3356 bus_dmamap_unload(txq->ift_tso_buf_tag,
3357 txq->ift_sds.ifsd_tso_map[pidx]);
3359 txq->ift_dequeued++;
3364 static inline caddr_t
3365 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3369 caddr_t start, end, cur, next;
3371 ntxd = txq->ift_size;
3372 size = txq->ift_txd_size[qid];
3373 start = txq->ift_ifdi[qid].idi_vaddr;
3375 if (__predict_false(size == 0))
3377 cur = start + size*cidx;
3378 end = start + size*ntxd;
3379 next = CACHE_PTR_NEXT(cur);
3380 return (next < end ? next : start);
3384 * Pad an mbuf to ensure a minimum ethernet frame size.
3385 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3387 static __noinline int
3388 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3391 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3392 * and ARP message is the smallest common payload I can think of
3394 static char pad[18]; /* just zeros */
3396 struct mbuf *new_head;
3398 if (!M_WRITABLE(*m_head)) {
3399 new_head = m_dup(*m_head, M_NOWAIT);
3400 if (new_head == NULL) {
3402 device_printf(dev, "cannot pad short frame, m_dup() failed");
3403 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3404 DBG_COUNTER_INC(tx_frees);
3411 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3412 n > 0; n -= sizeof(pad))
3413 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3418 device_printf(dev, "cannot pad short frame\n");
3419 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3420 DBG_COUNTER_INC(tx_frees);
3428 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3431 if_shared_ctx_t sctx;
3432 if_softc_ctx_t scctx;
3433 bus_dma_tag_t buf_tag;
3434 bus_dma_segment_t *segs;
3435 struct mbuf *m_head, **ifsd_m;
3438 struct if_pkt_info pi;
3440 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3443 sctx = ctx->ifc_sctx;
3444 scctx = &ctx->ifc_softc_ctx;
3445 segs = txq->ift_segs;
3446 ntxd = txq->ift_size;
3451 * If we're doing TSO the next descriptor to clean may be quite far ahead
3453 cidx = txq->ift_cidx;
3454 pidx = txq->ift_pidx;
3455 if (ctx->ifc_flags & IFC_PREFETCH) {
3456 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3457 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3458 next_txd = calc_next_txd(txq, cidx, 0);
3462 /* prefetch the next cache line of mbuf pointers and flags */
3463 prefetch(&txq->ift_sds.ifsd_m[next]);
3464 prefetch(&txq->ift_sds.ifsd_map[next]);
3465 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3467 map = txq->ift_sds.ifsd_map[pidx];
3468 ifsd_m = txq->ift_sds.ifsd_m;
3470 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3471 buf_tag = txq->ift_tso_buf_tag;
3472 max_segs = scctx->isc_tx_tso_segments_max;
3473 map = txq->ift_sds.ifsd_tso_map[pidx];
3474 MPASS(buf_tag != NULL);
3475 MPASS(max_segs > 0);
3477 buf_tag = txq->ift_buf_tag;
3478 max_segs = scctx->isc_tx_nsegments;
3479 map = txq->ift_sds.ifsd_map[pidx];
3481 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3482 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3483 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3485 DBG_COUNTER_INC(encap_txd_encap_fail);
3492 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3494 pi.ipi_qsidx = txq->ift_id;
3495 pi.ipi_len = m_head->m_pkthdr.len;
3496 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3497 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3499 /* deliberate bitwise OR to make one condition */
3500 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3501 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3502 DBG_COUNTER_INC(encap_txd_encap_fail);
3509 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3512 if (__predict_false(err)) {
3515 /* try collapse once and defrag once */
3517 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3518 /* try defrag if collapsing fails */
3523 txq->ift_mbuf_defrag++;
3524 m_head = m_defrag(*m_headp, M_NOWAIT);
3527 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3528 * failed to map an mbuf that was run through m_defrag
3531 if (__predict_false(m_head == NULL || remap > 1))
3538 txq->ift_no_tx_dma_setup++;
3541 txq->ift_no_tx_dma_setup++;
3543 DBG_COUNTER_INC(tx_frees);
3547 txq->ift_map_failed++;
3548 DBG_COUNTER_INC(encap_load_mbuf_fail);
3549 DBG_COUNTER_INC(encap_txd_encap_fail);
3552 ifsd_m[pidx] = m_head;
3554 * XXX assumes a 1 to 1 relationship between segments and
3555 * descriptors - this does not hold true on all drivers, e.g.
3558 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3559 txq->ift_no_desc_avail++;
3560 bus_dmamap_unload(buf_tag, map);
3561 DBG_COUNTER_INC(encap_txq_avail_fail);
3562 DBG_COUNTER_INC(encap_txd_encap_fail);
3563 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3564 GROUPTASK_ENQUEUE(&txq->ift_task);
3568 * On Intel cards we can greatly reduce the number of TX interrupts
3569 * we see by only setting report status on every Nth descriptor.
3570 * However, this also means that the driver will need to keep track
3571 * of the descriptors that RS was set on to check them for the DD bit.
3573 txq->ift_rs_pending += nsegs + 1;
3574 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3575 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3576 pi.ipi_flags |= IPI_TX_INTR;
3577 txq->ift_rs_pending = 0;
3581 pi.ipi_nsegs = nsegs;
3583 MPASS(pidx >= 0 && pidx < txq->ift_size);
3587 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3588 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3589 DBG_COUNTER_INC(tx_encap);
3590 MPASS(pi.ipi_new_pidx < txq->ift_size);
3592 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3593 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3594 ndesc += txq->ift_size;
3598 * drivers can need as many as
3601 MPASS(ndesc <= pi.ipi_nsegs + 2);
3602 MPASS(pi.ipi_new_pidx != pidx);
3604 txq->ift_in_use += ndesc;
3605 txq->ift_db_pending += ndesc;
3608 * We update the last software descriptor again here because there may
3609 * be a sentinel and/or there may be more mbufs than segments
3611 txq->ift_pidx = pi.ipi_new_pidx;
3612 txq->ift_npending += pi.ipi_ndescs;
3614 *m_headp = m_head = iflib_remove_mbuf(txq);
3616 txq->ift_txd_encap_efbig++;
3625 * err can't possibly be non-zero here, so we don't neet to test it
3626 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3631 txq->ift_mbuf_defrag_failed++;
3632 txq->ift_map_failed++;
3634 DBG_COUNTER_INC(tx_frees);
3636 DBG_COUNTER_INC(encap_txd_encap_fail);
3641 iflib_tx_desc_free(iflib_txq_t txq, int n)
3643 uint32_t qsize, cidx, mask, gen;
3644 struct mbuf *m, **ifsd_m;
3647 cidx = txq->ift_cidx;
3649 qsize = txq->ift_size;
3651 ifsd_m = txq->ift_sds.ifsd_m;
3652 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3656 prefetch(ifsd_m[(cidx + 3) & mask]);
3657 prefetch(ifsd_m[(cidx + 4) & mask]);
3659 if ((m = ifsd_m[cidx]) != NULL) {
3660 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3661 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3662 bus_dmamap_sync(txq->ift_tso_buf_tag,
3663 txq->ift_sds.ifsd_tso_map[cidx],
3664 BUS_DMASYNC_POSTWRITE);
3665 bus_dmamap_unload(txq->ift_tso_buf_tag,
3666 txq->ift_sds.ifsd_tso_map[cidx]);
3668 bus_dmamap_sync(txq->ift_buf_tag,
3669 txq->ift_sds.ifsd_map[cidx],
3670 BUS_DMASYNC_POSTWRITE);
3671 bus_dmamap_unload(txq->ift_buf_tag,
3672 txq->ift_sds.ifsd_map[cidx]);
3674 /* XXX we don't support any drivers that batch packets yet */
3675 MPASS(m->m_nextpkt == NULL);
3677 ifsd_m[cidx] = NULL;
3679 txq->ift_dequeued++;
3681 DBG_COUNTER_INC(tx_frees);
3683 if (__predict_false(++cidx == qsize)) {
3688 txq->ift_cidx = cidx;
3693 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3696 if_ctx_t ctx = txq->ift_ctx;
3698 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3699 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3702 * Need a rate-limiting check so that this isn't called every time
3704 iflib_tx_credits_update(ctx, txq);
3705 reclaim = DESC_RECLAIMABLE(txq);
3707 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3709 if (iflib_verbose_debug) {
3710 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3711 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3717 iflib_tx_desc_free(txq, reclaim);
3718 txq->ift_cleaned += reclaim;
3719 txq->ift_in_use -= reclaim;
3724 static struct mbuf **
3725 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3728 struct mbuf **items;
3731 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3732 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3734 prefetch(items[(cidx + offset) & (size-1)]);
3735 if (remaining > 1) {
3736 prefetch2cachelines(&items[next]);
3737 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3738 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3739 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3741 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3745 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3748 ifmp_ring_check_drainage(txq->ift_br, budget);
3752 iflib_txq_can_drain(struct ifmp_ring *r)
3754 iflib_txq_t txq = r->cookie;
3755 if_ctx_t ctx = txq->ift_ctx;
3757 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3759 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3760 BUS_DMASYNC_POSTREAD);
3761 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3766 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3768 iflib_txq_t txq = r->cookie;
3769 if_ctx_t ctx = txq->ift_ctx;
3770 if_t ifp = ctx->ifc_ifp;
3771 struct mbuf *m, **mp;
3772 int avail, bytes_sent, skipped, count, err, i;
3773 int mcast_sent, pkt_sent, reclaimed;
3774 bool do_prefetch, rang, ring;
3776 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3777 !LINK_ACTIVE(ctx))) {
3778 DBG_COUNTER_INC(txq_drain_notready);
3781 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3782 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3783 avail = IDXDIFF(pidx, cidx, r->size);
3785 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3787 * The driver is unloading so we need to free all pending packets.
3789 DBG_COUNTER_INC(txq_drain_flushing);
3790 for (i = 0; i < avail; i++) {
3791 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3792 m_freem(r->items[(cidx + i) & (r->size-1)]);
3793 r->items[(cidx + i) & (r->size-1)] = NULL;
3798 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3799 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3801 callout_stop(&txq->ift_timer);
3802 CALLOUT_UNLOCK(txq);
3803 DBG_COUNTER_INC(txq_drain_oactive);
3808 * If we've reclaimed any packets this queue cannot be hung.
3811 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3812 skipped = mcast_sent = bytes_sent = pkt_sent = 0;
3813 count = MIN(avail, TX_BATCH_SIZE);
3815 if (iflib_verbose_debug)
3816 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3817 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3819 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3821 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) {
3822 int rem = do_prefetch ? count - i : 0;
3824 mp = _ring_peek_one(r, cidx, i, rem);
3825 MPASS(mp != NULL && *mp != NULL);
3828 * Completion interrupts will use the address of the txq
3829 * as a sentinel to enqueue _something_ in order to acquire
3830 * the lock on the mp_ring (there's no direct lock call).
3831 * We obviously whave to check for these sentinel cases
3834 if (__predict_false(*mp == (struct mbuf *)txq)) {
3838 err = iflib_encap(txq, mp);
3839 if (__predict_false(err)) {
3840 /* no room - bail out */
3844 /* we can't send this packet - skip it */
3849 DBG_COUNTER_INC(tx_sent);
3850 bytes_sent += m->m_pkthdr.len;
3851 mcast_sent += !!(m->m_flags & M_MCAST);
3853 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3855 ETHER_BPF_MTAP(ifp, m);
3856 rang = iflib_txd_db_check(txq, false);
3859 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3860 ring = rang ? false : (iflib_min_tx_latency | err);
3861 iflib_txd_db_check(txq, ring);
3862 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3863 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3865 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3867 if (iflib_verbose_debug)
3868 printf("consumed=%d\n", skipped + pkt_sent);
3870 return (skipped + pkt_sent);
3874 iflib_txq_drain_always(struct ifmp_ring *r)
3880 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3888 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3890 callout_stop(&txq->ift_timer);
3891 CALLOUT_UNLOCK(txq);
3893 avail = IDXDIFF(pidx, cidx, r->size);
3894 for (i = 0; i < avail; i++) {
3895 mp = _ring_peek_one(r, cidx, i, avail - i);
3896 if (__predict_false(*mp == (struct mbuf *)txq))
3899 DBG_COUNTER_INC(tx_frees);
3901 MPASS(ifmp_ring_is_stalled(r) == 0);
3906 iflib_ifmp_purge(iflib_txq_t txq)
3908 struct ifmp_ring *r;
3911 r->drain = iflib_txq_drain_free;
3912 r->can_drain = iflib_txq_drain_always;
3914 ifmp_ring_check_drainage(r, r->size);
3916 r->drain = iflib_txq_drain;
3917 r->can_drain = iflib_txq_can_drain;
3921 _task_fn_tx(void *context)
3923 iflib_txq_t txq = context;
3924 if_ctx_t ctx = txq->ift_ctx;
3925 if_t ifp = ctx->ifc_ifp;
3926 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3928 #ifdef IFLIB_DIAGNOSTICS
3929 txq->ift_cpu_exec_count[curcpu]++;
3931 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3934 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3935 netmap_tx_irq(ifp, txq->ift_id))
3939 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3940 iflib_altq_if_start(ifp);
3942 if (txq->ift_db_pending)
3943 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3945 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3947 * When abdicating, we always need to check drainage, not just when we don't enqueue
3950 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3954 if (ctx->ifc_flags & IFC_LEGACY)
3955 IFDI_INTR_ENABLE(ctx);
3957 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3961 _task_fn_rx(void *context)
3963 iflib_rxq_t rxq = context;
3964 if_ctx_t ctx = rxq->ifr_ctx;
3972 #ifdef IFLIB_DIAGNOSTICS
3973 rxq->ifr_cpu_exec_count[curcpu]++;
3975 DBG_COUNTER_INC(task_fn_rxs);
3976 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3979 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3980 if (nmirq != NM_IRQ_PASS) {
3981 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3985 budget = ctx->ifc_sysctl_rx_budget;
3987 budget = 16; /* XXX */
3988 more = iflib_rxeof(rxq, budget);
3992 if ((more & IFLIB_RXEOF_MORE) == 0) {
3993 if (ctx->ifc_flags & IFC_LEGACY)
3994 IFDI_INTR_ENABLE(ctx);
3996 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3997 DBG_COUNTER_INC(rx_intr_enables);
3999 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4002 if (more & IFLIB_RXEOF_MORE)
4003 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4004 else if (more & IFLIB_RXEOF_EMPTY)
4005 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4009 _task_fn_admin(void *context)
4011 if_ctx_t ctx = context;
4012 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4015 bool oactive, running, do_reset, do_watchdog, in_detach;
4018 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4019 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4020 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4021 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4022 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4023 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
4026 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4032 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4034 callout_stop(&txq->ift_timer);
4035 CALLOUT_UNLOCK(txq);
4038 ctx->ifc_watchdog_events++;
4039 IFDI_WATCHDOG_RESET(ctx);
4041 IFDI_UPDATE_ADMIN_STATUS(ctx);
4042 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4043 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4044 txq->ift_timer.c_cpu);
4046 IFDI_LINK_INTR_ENABLE(ctx);
4048 iflib_if_init_locked(ctx);
4051 if (LINK_ACTIVE(ctx) == 0)
4053 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4054 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4058 _task_fn_iov(void *context)
4060 if_ctx_t ctx = context;
4062 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4063 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4067 IFDI_VFLR_HANDLE(ctx);
4072 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4075 if_int_delay_info_t info;
4078 info = (if_int_delay_info_t)arg1;
4079 ctx = info->iidi_ctx;
4080 info->iidi_req = req;
4081 info->iidi_oidp = oidp;
4083 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4088 /*********************************************************************
4092 **********************************************************************/
4095 iflib_if_init_locked(if_ctx_t ctx)
4098 iflib_init_locked(ctx);
4102 iflib_if_init(void *arg)
4107 iflib_if_init_locked(ctx);
4112 iflib_if_transmit(if_t ifp, struct mbuf *m)
4114 if_ctx_t ctx = if_getsoftc(ifp);
4118 int abdicate = ctx->ifc_sysctl_tx_abdicate;
4120 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4121 DBG_COUNTER_INC(tx_frees);
4126 MPASS(m->m_nextpkt == NULL);
4127 /* ALTQ-enabled interfaces always use queue 0. */
4129 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
4130 qidx = QIDX(ctx, m);
4132 * XXX calculate buf_ring based on flowid (divvy up bits?)
4134 txq = &ctx->ifc_txqs[qidx];
4136 #ifdef DRIVER_BACKPRESSURE
4137 if (txq->ift_closed) {
4139 next = m->m_nextpkt;
4140 m->m_nextpkt = NULL;
4142 DBG_COUNTER_INC(tx_frees);
4154 next = next->m_nextpkt;
4155 } while (next != NULL);
4157 if (count > nitems(marr))
4158 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4159 /* XXX check nextpkt */
4161 /* XXX simplify for now */
4162 DBG_COUNTER_INC(tx_frees);
4165 for (next = m, i = 0; next != NULL; i++) {
4167 next = next->m_nextpkt;
4168 mp[i]->m_nextpkt = NULL;
4171 DBG_COUNTER_INC(tx_seen);
4172 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4175 GROUPTASK_ENQUEUE(&txq->ift_task);
4178 GROUPTASK_ENQUEUE(&txq->ift_task);
4179 /* support forthcoming later */
4180 #ifdef DRIVER_BACKPRESSURE
4181 txq->ift_closed = TRUE;
4183 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4185 DBG_COUNTER_INC(tx_frees);
4193 * The overall approach to integrating iflib with ALTQ is to continue to use
4194 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4195 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4196 * is redundant/unnecessary, but doing so minimizes the amount of
4197 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4198 * redundantly queueing to an intermediate mp_ring is swamped by the
4199 * performance limitations inherent in using ALTQ.
4201 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4202 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4203 * given interface. If ALTQ is enabled for an interface, then all
4204 * transmitted packets for that interface will be submitted to the ALTQ
4205 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4206 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4207 * update stats that the iflib machinery handles, and which is sensitve to
4208 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4209 * will be installed as the start routine for use by ALTQ facilities that
4210 * need to trigger queue drains on a scheduled basis.
4214 iflib_altq_if_start(if_t ifp)
4216 struct ifaltq *ifq = &ifp->if_snd;
4220 IFQ_DEQUEUE_NOLOCK(ifq, m);
4222 iflib_if_transmit(ifp, m);
4223 IFQ_DEQUEUE_NOLOCK(ifq, m);
4229 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4233 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4234 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4236 iflib_altq_if_start(ifp);
4238 err = iflib_if_transmit(ifp, m);
4245 iflib_if_qflush(if_t ifp)
4247 if_ctx_t ctx = if_getsoftc(ifp);
4248 iflib_txq_t txq = ctx->ifc_txqs;
4252 ctx->ifc_flags |= IFC_QFLUSH;
4254 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4255 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4256 iflib_txq_check_drain(txq, 0);
4258 ctx->ifc_flags &= ~IFC_QFLUSH;
4262 * When ALTQ is enabled, this will also take care of purging the
4268 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4269 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4270 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4271 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4274 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4276 if_ctx_t ctx = if_getsoftc(ifp);
4277 struct ifreq *ifr = (struct ifreq *)data;
4278 #if defined(INET) || defined(INET6)
4279 struct ifaddr *ifa = (struct ifaddr *)data;
4281 bool avoid_reset = false;
4282 int err = 0, reinit = 0, bits;
4287 if (ifa->ifa_addr->sa_family == AF_INET)
4291 if (ifa->ifa_addr->sa_family == AF_INET6)
4295 ** Calling init results in link renegotiation,
4296 ** so we avoid doing it when possible.
4299 if_setflagbits(ifp, IFF_UP,0);
4300 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4303 if (!(if_getflags(ifp) & IFF_NOARP))
4304 arp_ifinit(ifp, ifa);
4307 err = ether_ioctl(ifp, command, data);
4311 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4315 bits = if_getdrvflags(ifp);
4316 /* stop the driver and free any clusters before proceeding */
4319 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4321 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4322 ctx->ifc_flags |= IFC_MULTISEG;
4324 ctx->ifc_flags &= ~IFC_MULTISEG;
4326 err = if_setmtu(ifp, ifr->ifr_mtu);
4328 iflib_init_locked(ctx);
4330 if_setdrvflags(ifp, bits);
4336 if (if_getflags(ifp) & IFF_UP) {
4337 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4338 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4339 (IFF_PROMISC | IFF_ALLMULTI)) {
4341 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4346 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4349 ctx->ifc_if_flags = if_getflags(ifp);
4354 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4356 IFDI_INTR_DISABLE(ctx);
4357 IFDI_MULTI_SET(ctx);
4358 IFDI_INTR_ENABLE(ctx);
4364 IFDI_MEDIA_SET(ctx);
4369 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4373 struct ifi2creq i2c;
4375 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4378 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4382 if (i2c.len > sizeof(i2c.data)) {
4387 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4388 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4394 int mask, setmask, oldmask;
4396 oldmask = if_getcapenable(ifp);
4397 mask = ifr->ifr_reqcap ^ oldmask;
4398 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4401 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4403 setmask |= (mask & IFCAP_FLAGS);
4404 setmask |= (mask & IFCAP_WOL);
4407 * If any RX csum has changed, change all the ones that
4408 * are supported by the driver.
4410 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4411 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4412 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4416 * want to ensure that traffic has stopped before we change any of the flags
4420 bits = if_getdrvflags(ifp);
4421 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4424 if_togglecapenable(ifp, setmask);
4426 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4427 iflib_init_locked(ctx);
4429 if_setdrvflags(ifp, bits);
4436 case SIOCGPRIVATE_0:
4440 err = IFDI_PRIV_IOCTL(ctx, command, data);
4444 err = ether_ioctl(ifp, command, data);
4453 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4455 if_ctx_t ctx = if_getsoftc(ifp);
4457 return (IFDI_GET_COUNTER(ctx, cnt));
4460 /*********************************************************************
4462 * OTHER FUNCTIONS EXPORTED TO THE STACK
4464 **********************************************************************/
4467 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4469 if_ctx_t ctx = if_getsoftc(ifp);
4471 if ((void *)ctx != arg)
4474 if ((vtag == 0) || (vtag > 4095))
4477 if (iflib_in_detach(ctx))
4481 /* Driver may need all untagged packets to be flushed */
4482 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4484 IFDI_VLAN_REGISTER(ctx, vtag);
4485 /* Re-init to load the changes, if required */
4486 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4487 iflib_init_locked(ctx);
4492 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4494 if_ctx_t ctx = if_getsoftc(ifp);
4496 if ((void *)ctx != arg)
4499 if ((vtag == 0) || (vtag > 4095))
4503 /* Driver may need all tagged packets to be flushed */
4504 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4506 IFDI_VLAN_UNREGISTER(ctx, vtag);
4507 /* Re-init to load the changes, if required */
4508 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4509 iflib_init_locked(ctx);
4514 iflib_led_func(void *arg, int onoff)
4519 IFDI_LED_FUNC(ctx, onoff);
4523 /*********************************************************************
4525 * BUS FUNCTION DEFINITIONS
4527 **********************************************************************/
4530 iflib_device_probe(device_t dev)
4532 const pci_vendor_info_t *ent;
4533 if_shared_ctx_t sctx;
4534 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4535 uint16_t pci_vendor_id;
4537 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4540 pci_vendor_id = pci_get_vendor(dev);
4541 pci_device_id = pci_get_device(dev);
4542 pci_subvendor_id = pci_get_subvendor(dev);
4543 pci_subdevice_id = pci_get_subdevice(dev);
4544 pci_rev_id = pci_get_revid(dev);
4545 if (sctx->isc_parse_devinfo != NULL)
4546 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4548 ent = sctx->isc_vendor_info;
4549 while (ent->pvi_vendor_id != 0) {
4550 if (pci_vendor_id != ent->pvi_vendor_id) {
4554 if ((pci_device_id == ent->pvi_device_id) &&
4555 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4556 (ent->pvi_subvendor_id == 0)) &&
4557 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4558 (ent->pvi_subdevice_id == 0)) &&
4559 ((pci_rev_id == ent->pvi_rev_id) ||
4560 (ent->pvi_rev_id == 0))) {
4561 device_set_desc_copy(dev, ent->pvi_name);
4562 /* this needs to be changed to zero if the bus probing code
4563 * ever stops re-probing on best match because the sctx
4564 * may have its values over written by register calls
4565 * in subsequent probes
4567 return (BUS_PROBE_DEFAULT);
4575 iflib_device_probe_vendor(device_t dev)
4579 probe = iflib_device_probe(dev);
4580 if (probe == BUS_PROBE_DEFAULT)
4581 return (BUS_PROBE_VENDOR);
4587 iflib_reset_qvalues(if_ctx_t ctx)
4589 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4590 if_shared_ctx_t sctx = ctx->ifc_sctx;
4591 device_t dev = ctx->ifc_dev;
4594 if (ctx->ifc_sysctl_ntxqs != 0)
4595 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4596 if (ctx->ifc_sysctl_nrxqs != 0)
4597 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4599 for (i = 0; i < sctx->isc_ntxqs; i++) {
4600 if (ctx->ifc_sysctl_ntxds[i] != 0)
4601 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4603 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4606 for (i = 0; i < sctx->isc_nrxqs; i++) {
4607 if (ctx->ifc_sysctl_nrxds[i] != 0)
4608 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4610 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4613 for (i = 0; i < sctx->isc_nrxqs; i++) {
4614 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4615 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4616 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4617 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4619 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4620 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4621 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4622 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4624 if (!powerof2(scctx->isc_nrxd[i])) {
4625 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4626 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4627 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4631 for (i = 0; i < sctx->isc_ntxqs; i++) {
4632 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4633 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4634 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4635 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4637 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4638 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4639 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4640 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4642 if (!powerof2(scctx->isc_ntxd[i])) {
4643 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4644 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4645 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4651 iflib_add_pfil(if_ctx_t ctx)
4653 struct pfil_head *pfil;
4654 struct pfil_head_args pa;
4658 pa.pa_version = PFIL_VERSION;
4659 pa.pa_flags = PFIL_IN;
4660 pa.pa_type = PFIL_TYPE_ETHERNET;
4661 pa.pa_headname = ctx->ifc_ifp->if_xname;
4662 pfil = pfil_head_register(&pa);
4664 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4670 iflib_rem_pfil(if_ctx_t ctx)
4672 struct pfil_head *pfil;
4676 rxq = ctx->ifc_rxqs;
4678 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4681 pfil_head_unregister(pfil);
4686 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from
4687 * cpuid and wrapping as necessary.
4690 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n)
4692 unsigned int first_valid;
4693 unsigned int last_valid;
4695 /* cpuid should always be in the valid set */
4696 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus));
4698 /* valid set should never be empty */
4699 MPASS(!CPU_EMPTY(&ctx->ifc_cpus));
4701 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4702 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4703 n = n % CPU_COUNT(&ctx->ifc_cpus);
4707 if (cpuid > last_valid)
4708 cpuid = first_valid;
4709 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus));
4716 #if defined(SMP) && defined(SCHED_ULE)
4717 extern struct cpu_group *cpu_top; /* CPU topology */
4720 find_child_with_core(int cpu, struct cpu_group *grp)
4724 if (grp->cg_children == 0)
4727 MPASS(grp->cg_child);
4728 for (i = 0; i < grp->cg_children; i++) {
4729 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
4738 * Find an L2 neighbor of the given CPU or return -1 if none found. This
4739 * does not distinguish among multiple L2 neighbors if the given CPU has
4740 * more than one (it will always return the same result in that case).
4743 find_l2_neighbor(int cpu)
4745 struct cpu_group *grp;
4753 * Find the smallest CPU group that contains the given core.
4756 while ((i = find_child_with_core(cpu, grp)) != -1) {
4758 * If the smallest group containing the given CPU has less
4759 * than two members, we conclude the given CPU has no
4762 if (grp->cg_child[i].cg_count <= 1)
4764 grp = &grp->cg_child[i];
4767 /* Must share L2. */
4768 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
4772 * Select the first member of the set that isn't the reference
4773 * CPU, which at this point is guaranteed to exist.
4775 for (i = 0; i < CPU_SETSIZE; i++) {
4776 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu)
4780 /* Should never be reached */
4786 find_l2_neighbor(int cpu)
4794 * CPU mapping behaviors
4795 * ---------------------
4796 * 'separate txrx' refers to the separate_txrx sysctl
4797 * 'use logical' refers to the use_logical_cores sysctl
4798 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded
4801 * txrx logical CPUS result
4802 * ---------- --------- ------ ------------------------------------------------
4803 * - - X RX and TX queues mapped to consecutive physical
4804 * cores with RX/TX pairs on same core and excess
4805 * of either following
4806 * - X X RX and TX queues mapped to consecutive cores
4807 * of any type with RX/TX pairs on same core and
4808 * excess of either following
4809 * X - X RX and TX queues mapped to consecutive physical
4810 * cores; all RX then all TX
4811 * X X X RX queues mapped to consecutive physical cores
4812 * first, then TX queues mapped to L2 neighbor of
4813 * the corresponding RX queue if one exists,
4814 * otherwise to consecutive physical cores
4815 * - n/a - RX and TX queues mapped to consecutive cores of
4816 * any type with RX/TX pairs on same core and excess
4817 * of either following
4818 * X n/a - RX and TX queues mapped to consecutive cores of
4819 * any type; all RX then all TX
4822 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid,
4825 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4826 unsigned int core_index;
4828 if (ctx->ifc_sysctl_separate_txrx) {
4830 * When using separate CPUs for TX and RX, the assignment
4831 * will always be of a consecutive CPU out of the set of
4832 * context CPUs, except for the specific case where the
4833 * context CPUs are phsyical cores, the use of logical cores
4834 * has been enabled, the assignment is for TX, the TX qid
4835 * corresponds to an RX qid, and the CPU assigned to the
4836 * corresponding RX queue has an L2 neighbor.
4838 if (ctx->ifc_sysctl_use_logical_cores &&
4839 ctx->ifc_cpus_are_physical_cores &&
4840 is_tx && qid < scctx->isc_nrxqsets) {
4842 unsigned int rx_cpuid;
4844 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid);
4845 l2_neighbor = find_l2_neighbor(rx_cpuid);
4846 if (l2_neighbor != -1) {
4847 return (l2_neighbor);
4850 * ... else fall through to the normal
4851 * consecutive-after-RX assignment scheme.
4853 * Note that we are assuming that all RX queue CPUs
4854 * have an L2 neighbor, or all do not. If a mixed
4855 * scenario is possible, we will have to keep track
4856 * separately of how many queues prior to this one
4857 * were not able to be assigned to an L2 neighbor.
4861 core_index = scctx->isc_nrxqsets + qid;
4868 return (cpuid_advance(ctx, base_cpuid, core_index));
4872 get_ctx_core_offset(if_ctx_t ctx)
4874 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4875 struct cpu_offset *op;
4876 cpuset_t assigned_cpus;
4877 unsigned int cores_consumed;
4878 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset;
4879 unsigned int first_valid;
4880 unsigned int last_valid;
4883 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4884 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4886 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) {
4888 * Align the user-chosen base CPU ID to the next valid CPU
4889 * for this device. If the chosen base CPU ID is smaller
4890 * than the first valid CPU or larger than the last valid
4891 * CPU, we assume the user does not know what the valid
4892 * range is for this device and is thinking in terms of a
4893 * zero-based reference frame, and so we shift the given
4894 * value into the valid range (and wrap accordingly) so the
4895 * intent is translated to the proper frame of reference.
4896 * If the base CPU ID is within the valid first/last, but
4897 * does not correspond to a valid CPU, it is advanced to the
4898 * next valid CPU (wrapping if necessary).
4900 if (base_cpuid < first_valid || base_cpuid > last_valid) {
4901 /* shift from zero-based to first_valid-based */
4902 base_cpuid += first_valid;
4903 /* wrap to range [first_valid, last_valid] */
4904 base_cpuid = (base_cpuid - first_valid) %
4905 (last_valid - first_valid + 1);
4907 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) {
4909 * base_cpuid is in [first_valid, last_valid], but
4910 * not a member of the valid set. In this case,
4911 * there will always be a member of the valid set
4912 * with a CPU ID that is greater than base_cpuid,
4913 * and we simply advance to it.
4915 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus))
4918 return (base_cpuid);
4922 * Determine how many cores will be consumed by performing the CPU
4923 * assignments and counting how many of the assigned CPUs correspond
4924 * to CPUs in the set of context CPUs. This is done using the CPU
4925 * ID first_valid as the base CPU ID, as the base CPU must be within
4926 * the set of context CPUs.
4928 * Note not all assigned CPUs will be in the set of context CPUs
4929 * when separate CPUs are being allocated to TX and RX queues,
4930 * assignment to logical cores has been enabled, the set of context
4931 * CPUs contains only physical CPUs, and TX queues are mapped to L2
4932 * neighbors of CPUs that RX queues have been mapped to - in this
4933 * case we do only want to count how many CPUs in the set of context
4934 * CPUs have been consumed, as that determines the next CPU in that
4935 * set to start allocating at for the next device for which
4936 * core_offset is not set.
4938 CPU_ZERO(&assigned_cpus);
4939 for (i = 0; i < scctx->isc_ntxqsets; i++)
4940 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true),
4942 for (i = 0; i < scctx->isc_nrxqsets; i++)
4943 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false),
4945 CPU_AND(&assigned_cpus, &ctx->ifc_cpus);
4946 cores_consumed = CPU_COUNT(&assigned_cpus);
4948 mtx_lock(&cpu_offset_mtx);
4949 SLIST_FOREACH(op, &cpu_offsets, entries) {
4950 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4951 base_cpuid = op->next_cpuid;
4952 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid,
4954 MPASS(op->refcount < UINT_MAX);
4959 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) {
4960 base_cpuid = first_valid;
4961 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4964 device_printf(ctx->ifc_dev,
4965 "allocation for cpu offset failed.\n");
4967 op->next_cpuid = cpuid_advance(ctx, base_cpuid,
4970 CPU_COPY(&ctx->ifc_cpus, &op->set);
4971 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4974 mtx_unlock(&cpu_offset_mtx);
4976 return (base_cpuid);
4980 unref_ctx_core_offset(if_ctx_t ctx)
4982 struct cpu_offset *op, *top;
4984 mtx_lock(&cpu_offset_mtx);
4985 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4986 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4987 MPASS(op->refcount > 0);
4989 if (op->refcount == 0) {
4990 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4996 mtx_unlock(&cpu_offset_mtx);
5000 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
5004 if_softc_ctx_t scctx;
5005 kobjop_desc_t kobj_desc;
5006 kobj_method_t *kobj_method;
5008 int num_txd, num_rxd;
5010 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
5013 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5014 device_set_softc(dev, ctx);
5015 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5018 ctx->ifc_sctx = sctx;
5020 ctx->ifc_softc = sc;
5022 if ((err = iflib_register(ctx)) != 0) {
5023 device_printf(dev, "iflib_register failed %d\n", err);
5026 iflib_add_device_sysctl_pre(ctx);
5028 scctx = &ctx->ifc_softc_ctx;
5031 iflib_reset_qvalues(ctx);
5033 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5034 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5037 _iflib_pre_assert(scctx);
5038 ctx->ifc_txrx = *scctx->isc_txrx;
5040 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
5041 ctx->ifc_mediap = scctx->isc_media;
5044 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5045 MPASS(scctx->isc_tx_csum_flags);
5048 if_setcapabilities(ifp,
5049 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
5050 if_setcapenable(ifp,
5051 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
5053 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5054 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5055 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5056 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5058 num_txd = iflib_num_tx_descs(ctx);
5059 num_rxd = iflib_num_rx_descs(ctx);
5061 /* XXX change for per-queue sizes */
5062 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5065 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5066 scctx->isc_tx_nsegments = max(1, num_txd /
5067 MAX_SINGLE_PACKET_FRACTION);
5068 if (scctx->isc_tx_tso_segments_max > num_txd /
5069 MAX_SINGLE_PACKET_FRACTION)
5070 scctx->isc_tx_tso_segments_max = max(1,
5071 num_txd / MAX_SINGLE_PACKET_FRACTION);
5073 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5074 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5076 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5079 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5082 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5083 * into account. In the worst case, each of these calls will
5084 * add another mbuf and, thus, the requirement for another DMA
5085 * segment. So for best performance, it doesn't make sense to
5086 * advertize a maximum of TSO segments that typically will
5087 * require defragmentation in iflib_encap().
5089 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5090 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5092 if (scctx->isc_rss_table_size == 0)
5093 scctx->isc_rss_table_size = 64;
5094 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5096 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5097 /* XXX format name */
5098 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5099 NULL, NULL, "admin");
5101 /* Set up cpu set. If it fails, use the set of all CPUs. */
5102 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
5103 device_printf(dev, "Unable to fetch CPU list\n");
5104 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
5105 ctx->ifc_cpus_are_physical_cores = false;
5107 ctx->ifc_cpus_are_physical_cores = true;
5108 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
5111 ** Now set up MSI or MSI-X, should return us the number of supported
5112 ** vectors (will be 1 for a legacy interrupt and MSI).
5114 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
5115 msix = scctx->isc_vectors;
5116 } else if (scctx->isc_msix_bar != 0)
5118 * The simple fact that isc_msix_bar is not 0 does not mean we
5119 * we have a good value there that is known to work.
5121 msix = iflib_msix_init(ctx);
5123 scctx->isc_vectors = 1;
5124 scctx->isc_ntxqsets = 1;
5125 scctx->isc_nrxqsets = 1;
5126 scctx->isc_intr = IFLIB_INTR_LEGACY;
5129 /* Get memory for the station queues */
5130 if ((err = iflib_queues_alloc(ctx))) {
5131 device_printf(dev, "Unable to allocate queue memory\n");
5132 goto fail_intr_free;
5135 if ((err = iflib_qset_structures_setup(ctx)))
5139 * Now that we know how many queues there are, get the core offset.
5141 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
5145 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
5146 * aren't the default NULL implementation.
5148 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
5149 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5151 if (kobj_method == &kobj_desc->deflt) {
5153 "MSI-X requires ifdi_rx_queue_intr_enable method");
5157 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
5158 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5160 if (kobj_method == &kobj_desc->deflt) {
5162 "MSI-X requires ifdi_tx_queue_intr_enable method");
5168 * Assign the MSI-X vectors.
5169 * Note that the default NULL ifdi_msix_intr_assign method will
5172 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
5174 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
5178 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
5180 if (scctx->isc_intr == IFLIB_INTR_MSI) {
5184 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
5185 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
5190 "Cannot use iflib with only 1 MSI-X interrupt!\n");
5195 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5197 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5198 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5203 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5204 * This must appear after the call to ether_ifattach() because
5205 * ether_ifattach() sets if_hdrlen to the default value.
5207 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5208 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5210 if ((err = iflib_netmap_attach(ctx))) {
5211 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
5216 DEBUGNET_SET(ctx->ifc_ifp, iflib);
5218 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5219 iflib_add_device_sysctl_post(ctx);
5220 iflib_add_pfil(ctx);
5221 ctx->ifc_flags |= IFC_INIT_DONE;
5227 ether_ifdetach(ctx->ifc_ifp);
5229 iflib_tqg_detach(ctx);
5230 iflib_tx_structures_free(ctx);
5231 iflib_rx_structures_free(ctx);
5233 IFDI_QUEUES_FREE(ctx);
5235 iflib_free_intr_mem(ctx);
5238 iflib_deregister(ctx);
5240 device_set_softc(ctx->ifc_dev, NULL);
5241 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5242 free(ctx->ifc_softc, M_IFLIB);
5248 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
5249 struct iflib_cloneattach_ctx *clctx)
5251 int num_txd, num_rxd;
5255 if_softc_ctx_t scctx;
5259 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
5260 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5261 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5262 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
5263 ctx->ifc_flags |= IFC_PSEUDO;
5265 ctx->ifc_sctx = sctx;
5266 ctx->ifc_softc = sc;
5269 if ((err = iflib_register(ctx)) != 0) {
5270 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
5273 iflib_add_device_sysctl_pre(ctx);
5275 scctx = &ctx->ifc_softc_ctx;
5278 iflib_reset_qvalues(ctx);
5280 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5281 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5284 if (sctx->isc_flags & IFLIB_GEN_MAC)
5285 ether_gen_addr(ifp, &ctx->ifc_mac);
5286 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
5287 clctx->cc_params)) != 0) {
5288 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
5292 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5293 MPASS(scctx->isc_tx_csum_flags);
5296 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5297 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5299 ifp->if_flags |= IFF_NOGROUP;
5300 if (sctx->isc_flags & IFLIB_PSEUDO) {
5301 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5302 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5303 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
5304 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5306 if_attach(ctx->ifc_ifp);
5307 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
5310 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5311 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5317 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5318 * This must appear after the call to ether_ifattach() because
5319 * ether_ifattach() sets if_hdrlen to the default value.
5321 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5322 if_setifheaderlen(ifp,
5323 sizeof(struct ether_vlan_header));
5325 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5326 iflib_add_device_sysctl_post(ctx);
5327 ctx->ifc_flags |= IFC_INIT_DONE;
5331 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
5332 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5333 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5335 _iflib_pre_assert(scctx);
5336 ctx->ifc_txrx = *scctx->isc_txrx;
5338 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5339 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5340 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5341 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5343 num_txd = iflib_num_tx_descs(ctx);
5344 num_rxd = iflib_num_rx_descs(ctx);
5346 /* XXX change for per-queue sizes */
5347 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5350 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5351 scctx->isc_tx_nsegments = max(1, num_txd /
5352 MAX_SINGLE_PACKET_FRACTION);
5353 if (scctx->isc_tx_tso_segments_max > num_txd /
5354 MAX_SINGLE_PACKET_FRACTION)
5355 scctx->isc_tx_tso_segments_max = max(1,
5356 num_txd / MAX_SINGLE_PACKET_FRACTION);
5358 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5359 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5361 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5364 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5367 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5368 * into account. In the worst case, each of these calls will
5369 * add another mbuf and, thus, the requirement for another DMA
5370 * segment. So for best performance, it doesn't make sense to
5371 * advertize a maximum of TSO segments that typically will
5372 * require defragmentation in iflib_encap().
5374 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5375 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5377 if (scctx->isc_rss_table_size == 0)
5378 scctx->isc_rss_table_size = 64;
5379 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5381 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5382 /* XXX format name */
5383 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5384 NULL, NULL, "admin");
5386 /* XXX --- can support > 1 -- but keep it simple for now */
5387 scctx->isc_intr = IFLIB_INTR_LEGACY;
5389 /* Get memory for the station queues */
5390 if ((err = iflib_queues_alloc(ctx))) {
5391 device_printf(dev, "Unable to allocate queue memory\n");
5392 goto fail_iflib_detach;
5395 if ((err = iflib_qset_structures_setup(ctx))) {
5396 device_printf(dev, "qset structure setup failed %d\n", err);
5401 * XXX What if anything do we want to do about interrupts?
5403 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5404 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5405 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5410 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5411 * This must appear after the call to ether_ifattach() because
5412 * ether_ifattach() sets if_hdrlen to the default value.
5414 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5415 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5417 /* XXX handle more than one queue */
5418 for (i = 0; i < scctx->isc_nrxqsets; i++)
5419 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5423 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5424 iflib_add_device_sysctl_post(ctx);
5425 ctx->ifc_flags |= IFC_INIT_DONE;
5430 ether_ifdetach(ctx->ifc_ifp);
5432 iflib_tqg_detach(ctx);
5433 iflib_tx_structures_free(ctx);
5434 iflib_rx_structures_free(ctx);
5437 IFDI_QUEUES_FREE(ctx);
5440 iflib_deregister(ctx);
5442 free(ctx->ifc_softc, M_IFLIB);
5448 iflib_pseudo_deregister(if_ctx_t ctx)
5450 if_t ifp = ctx->ifc_ifp;
5451 if_shared_ctx_t sctx = ctx->ifc_sctx;
5453 /* Unregister VLAN event handlers early */
5454 iflib_unregister_vlan_handlers(ctx);
5456 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5457 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5461 ether_ifdetach(ifp);
5464 iflib_tqg_detach(ctx);
5465 iflib_tx_structures_free(ctx);
5466 iflib_rx_structures_free(ctx);
5468 IFDI_QUEUES_FREE(ctx);
5470 iflib_deregister(ctx);
5472 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5473 free(ctx->ifc_softc, M_IFLIB);
5479 iflib_device_attach(device_t dev)
5482 if_shared_ctx_t sctx;
5484 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5487 pci_enable_busmaster(dev);
5489 return (iflib_device_register(dev, NULL, sctx, &ctx));
5493 iflib_device_deregister(if_ctx_t ctx)
5495 if_t ifp = ctx->ifc_ifp;
5496 device_t dev = ctx->ifc_dev;
5498 /* Make sure VLANS are not using driver */
5499 if (if_vlantrunkinuse(ifp)) {
5500 device_printf(dev, "Vlan in use, detach first\n");
5504 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5505 device_printf(dev, "SR-IOV in use; detach first.\n");
5511 ctx->ifc_flags |= IFC_IN_DETACH;
5514 /* Unregister VLAN handlers before calling iflib_stop() */
5515 iflib_unregister_vlan_handlers(ctx);
5517 iflib_netmap_detach(ifp);
5518 ether_ifdetach(ifp);
5524 iflib_rem_pfil(ctx);
5525 if (ctx->ifc_led_dev != NULL)
5526 led_destroy(ctx->ifc_led_dev);
5528 iflib_tqg_detach(ctx);
5529 iflib_tx_structures_free(ctx);
5530 iflib_rx_structures_free(ctx);
5534 IFDI_QUEUES_FREE(ctx);
5537 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5538 iflib_free_intr_mem(ctx);
5540 bus_generic_detach(dev);
5542 iflib_deregister(ctx);
5544 device_set_softc(ctx->ifc_dev, NULL);
5545 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5546 free(ctx->ifc_softc, M_IFLIB);
5547 unref_ctx_core_offset(ctx);
5553 iflib_tqg_detach(if_ctx_t ctx)
5558 struct taskqgroup *tqg;
5560 /* XXX drain any dependent tasks */
5561 tqg = qgroup_if_io_tqg;
5562 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5563 callout_drain(&txq->ift_timer);
5565 callout_drain(&txq->ift_netmap_timer);
5566 #endif /* DEV_NETMAP */
5567 if (txq->ift_task.gt_uniq != NULL)
5568 taskqgroup_detach(tqg, &txq->ift_task);
5570 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5571 if (rxq->ifr_task.gt_uniq != NULL)
5572 taskqgroup_detach(tqg, &rxq->ifr_task);
5574 tqg = qgroup_if_config_tqg;
5575 if (ctx->ifc_admin_task.gt_uniq != NULL)
5576 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5577 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5578 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5582 iflib_free_intr_mem(if_ctx_t ctx)
5585 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5586 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5588 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5589 pci_release_msi(ctx->ifc_dev);
5591 if (ctx->ifc_msix_mem != NULL) {
5592 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5593 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5594 ctx->ifc_msix_mem = NULL;
5599 iflib_device_detach(device_t dev)
5601 if_ctx_t ctx = device_get_softc(dev);
5603 return (iflib_device_deregister(ctx));
5607 iflib_device_suspend(device_t dev)
5609 if_ctx_t ctx = device_get_softc(dev);
5615 return bus_generic_suspend(dev);
5618 iflib_device_shutdown(device_t dev)
5620 if_ctx_t ctx = device_get_softc(dev);
5626 return bus_generic_suspend(dev);
5630 iflib_device_resume(device_t dev)
5632 if_ctx_t ctx = device_get_softc(dev);
5633 iflib_txq_t txq = ctx->ifc_txqs;
5637 iflib_if_init_locked(ctx);
5639 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5640 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5642 return (bus_generic_resume(dev));
5646 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5649 if_ctx_t ctx = device_get_softc(dev);
5652 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5659 iflib_device_iov_uninit(device_t dev)
5661 if_ctx_t ctx = device_get_softc(dev);
5664 IFDI_IOV_UNINIT(ctx);
5669 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5672 if_ctx_t ctx = device_get_softc(dev);
5675 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5681 /*********************************************************************
5683 * MODULE FUNCTION DEFINITIONS
5685 **********************************************************************/
5688 * - Start a fast taskqueue thread for each core
5689 * - Start a taskqueue for control operations
5692 iflib_module_init(void)
5694 iflib_timer_default = hz / 2;
5699 iflib_module_event_handler(module_t mod, int what, void *arg)
5705 if ((err = iflib_module_init()) != 0)
5711 return (EOPNOTSUPP);
5717 /*********************************************************************
5719 * PUBLIC FUNCTION DEFINITIONS
5720 * ordered as in iflib.h
5722 **********************************************************************/
5725 _iflib_assert(if_shared_ctx_t sctx)
5729 MPASS(sctx->isc_tx_maxsize);
5730 MPASS(sctx->isc_tx_maxsegsize);
5732 MPASS(sctx->isc_rx_maxsize);
5733 MPASS(sctx->isc_rx_nsegments);
5734 MPASS(sctx->isc_rx_maxsegsize);
5736 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5737 for (i = 0; i < sctx->isc_nrxqs; i++) {
5738 MPASS(sctx->isc_nrxd_min[i]);
5739 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5740 MPASS(sctx->isc_nrxd_max[i]);
5741 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5742 MPASS(sctx->isc_nrxd_default[i]);
5743 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5746 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5747 for (i = 0; i < sctx->isc_ntxqs; i++) {
5748 MPASS(sctx->isc_ntxd_min[i]);
5749 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5750 MPASS(sctx->isc_ntxd_max[i]);
5751 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5752 MPASS(sctx->isc_ntxd_default[i]);
5753 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5758 _iflib_pre_assert(if_softc_ctx_t scctx)
5761 MPASS(scctx->isc_txrx->ift_txd_encap);
5762 MPASS(scctx->isc_txrx->ift_txd_flush);
5763 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5764 MPASS(scctx->isc_txrx->ift_rxd_available);
5765 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5766 MPASS(scctx->isc_txrx->ift_rxd_refill);
5767 MPASS(scctx->isc_txrx->ift_rxd_flush);
5771 iflib_register(if_ctx_t ctx)
5773 if_shared_ctx_t sctx = ctx->ifc_sctx;
5774 driver_t *driver = sctx->isc_driver;
5775 device_t dev = ctx->ifc_dev;
5780 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5781 _iflib_assert(sctx);
5784 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5785 if (sctx->isc_flags & IFLIB_PSEUDO) {
5786 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5792 ifp = ctx->ifc_ifp = if_alloc(type);
5794 device_printf(dev, "can not allocate ifnet structure\n");
5799 * Initialize our context's device specific methods
5801 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5802 kobj_class_compile((kobj_class_t) driver);
5804 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5805 if_setsoftc(ifp, ctx);
5806 if_setdev(ifp, dev);
5807 if_setinitfn(ifp, iflib_if_init);
5808 if_setioctlfn(ifp, iflib_if_ioctl);
5810 if_setstartfn(ifp, iflib_altq_if_start);
5811 if_settransmitfn(ifp, iflib_altq_if_transmit);
5812 if_setsendqready(ifp);
5814 if_settransmitfn(ifp, iflib_if_transmit);
5816 if_setqflushfn(ifp, iflib_if_qflush);
5817 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5819 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5820 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5821 iflags |= IFF_POINTOPOINT;
5823 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5824 if_setflags(ifp, iflags);
5825 ctx->ifc_vlan_attach_event =
5826 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5827 EVENTHANDLER_PRI_FIRST);
5828 ctx->ifc_vlan_detach_event =
5829 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5830 EVENTHANDLER_PRI_FIRST);
5832 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5833 ctx->ifc_mediap = &ctx->ifc_media;
5834 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5835 iflib_media_change, iflib_media_status);
5841 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5843 /* Unregister VLAN events */
5844 if (ctx->ifc_vlan_attach_event != NULL) {
5845 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5846 ctx->ifc_vlan_attach_event = NULL;
5848 if (ctx->ifc_vlan_detach_event != NULL) {
5849 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5850 ctx->ifc_vlan_detach_event = NULL;
5856 iflib_deregister(if_ctx_t ctx)
5858 if_t ifp = ctx->ifc_ifp;
5860 /* Remove all media */
5861 ifmedia_removeall(&ctx->ifc_media);
5863 /* Ensure that VLAN event handlers are unregistered */
5864 iflib_unregister_vlan_handlers(ctx);
5866 /* Release kobject reference */
5867 kobj_delete((kobj_t) ctx, NULL);
5869 /* Free the ifnet structure */
5872 STATE_LOCK_DESTROY(ctx);
5874 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5875 CTX_LOCK_DESTROY(ctx);
5879 iflib_queues_alloc(if_ctx_t ctx)
5881 if_shared_ctx_t sctx = ctx->ifc_sctx;
5882 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5883 device_t dev = ctx->ifc_dev;
5884 int nrxqsets = scctx->isc_nrxqsets;
5885 int ntxqsets = scctx->isc_ntxqsets;
5888 iflib_fl_t fl = NULL;
5889 int i, j, cpu, err, txconf, rxconf;
5890 iflib_dma_info_t ifdip;
5891 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5892 uint32_t *txqsizes = scctx->isc_txqsizes;
5893 uint8_t nrxqs = sctx->isc_nrxqs;
5894 uint8_t ntxqs = sctx->isc_ntxqs;
5895 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5896 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
5900 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5901 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5902 KASSERT(nrxqs >= fl_offset + nfree_lists,
5903 ("there must be at least a rxq for each free list"));
5905 /* Allocate the TX ring struct memory */
5906 if (!(ctx->ifc_txqs =
5907 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5908 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5909 device_printf(dev, "Unable to allocate TX ring memory\n");
5914 /* Now allocate the RX */
5915 if (!(ctx->ifc_rxqs =
5916 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5917 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5918 device_printf(dev, "Unable to allocate RX ring memory\n");
5923 txq = ctx->ifc_txqs;
5924 rxq = ctx->ifc_rxqs;
5927 * XXX handle allocation failure
5929 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5930 /* Set up some basics */
5932 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5933 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5935 "Unable to allocate TX DMA info memory\n");
5939 txq->ift_ifdi = ifdip;
5940 for (j = 0; j < ntxqs; j++, ifdip++) {
5941 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5943 "Unable to allocate TX descriptors\n");
5947 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5948 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5952 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5953 txq->ift_br_offset = 1;
5955 txq->ift_br_offset = 0;
5958 if (iflib_txsd_alloc(txq)) {
5959 device_printf(dev, "Critical Failure setting up TX buffers\n");
5964 /* Initialize the TX lock */
5965 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5966 device_get_nameunit(dev), txq->ift_id);
5967 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5968 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5969 txq->ift_timer.c_cpu = cpu;
5971 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
5972 txq->ift_netmap_timer.c_cpu = cpu;
5973 #endif /* DEV_NETMAP */
5975 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5976 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5978 /* XXX free any allocated rings */
5979 device_printf(dev, "Unable to allocate buf_ring\n");
5984 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5985 /* Set up some basics */
5986 callout_init(&rxq->ifr_watchdog, 1);
5988 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5989 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5991 "Unable to allocate RX DMA info memory\n");
5996 rxq->ifr_ifdi = ifdip;
5997 /* XXX this needs to be changed if #rx queues != #tx queues */
5998 rxq->ifr_ntxqirq = 1;
5999 rxq->ifr_txqid[0] = i;
6000 for (j = 0; j < nrxqs; j++, ifdip++) {
6001 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
6003 "Unable to allocate RX descriptors\n");
6007 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
6011 rxq->ifr_fl_offset = fl_offset;
6012 rxq->ifr_nfl = nfree_lists;
6014 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
6015 device_printf(dev, "Unable to allocate free list memory\n");
6020 for (j = 0; j < nfree_lists; j++) {
6021 fl[j].ifl_rxq = rxq;
6023 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
6024 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
6026 /* Allocate receive buffers for the ring */
6027 if (iflib_rxsd_alloc(rxq)) {
6029 "Critical Failure setting up receive buffers\n");
6034 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
6035 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
6040 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
6041 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
6042 for (i = 0; i < ntxqsets; i++) {
6043 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
6045 for (j = 0; j < ntxqs; j++, di++) {
6046 vaddrs[i*ntxqs + j] = di->idi_vaddr;
6047 paddrs[i*ntxqs + j] = di->idi_paddr;
6050 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
6051 device_printf(ctx->ifc_dev,
6052 "Unable to allocate device TX queue\n");
6053 iflib_tx_structures_free(ctx);
6054 free(vaddrs, M_IFLIB);
6055 free(paddrs, M_IFLIB);
6058 free(vaddrs, M_IFLIB);
6059 free(paddrs, M_IFLIB);
6062 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6063 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6064 for (i = 0; i < nrxqsets; i++) {
6065 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
6067 for (j = 0; j < nrxqs; j++, di++) {
6068 vaddrs[i*nrxqs + j] = di->idi_vaddr;
6069 paddrs[i*nrxqs + j] = di->idi_paddr;
6072 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
6073 device_printf(ctx->ifc_dev,
6074 "Unable to allocate device RX queue\n");
6075 iflib_tx_structures_free(ctx);
6076 free(vaddrs, M_IFLIB);
6077 free(paddrs, M_IFLIB);
6080 free(vaddrs, M_IFLIB);
6081 free(paddrs, M_IFLIB);
6085 /* XXX handle allocation failure changes */
6089 if (ctx->ifc_rxqs != NULL)
6090 free(ctx->ifc_rxqs, M_IFLIB);
6091 ctx->ifc_rxqs = NULL;
6092 if (ctx->ifc_txqs != NULL)
6093 free(ctx->ifc_txqs, M_IFLIB);
6094 ctx->ifc_txqs = NULL;
6100 iflib_tx_structures_setup(if_ctx_t ctx)
6102 iflib_txq_t txq = ctx->ifc_txqs;
6105 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
6106 iflib_txq_setup(txq);
6112 iflib_tx_structures_free(if_ctx_t ctx)
6114 iflib_txq_t txq = ctx->ifc_txqs;
6115 if_shared_ctx_t sctx = ctx->ifc_sctx;
6118 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6119 for (j = 0; j < sctx->isc_ntxqs; j++)
6120 iflib_dma_free(&txq->ift_ifdi[j]);
6121 iflib_txq_destroy(txq);
6123 free(ctx->ifc_txqs, M_IFLIB);
6124 ctx->ifc_txqs = NULL;
6127 /*********************************************************************
6129 * Initialize all receive rings.
6131 **********************************************************************/
6133 iflib_rx_structures_setup(if_ctx_t ctx)
6135 iflib_rxq_t rxq = ctx->ifc_rxqs;
6137 #if defined(INET6) || defined(INET)
6141 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
6142 #if defined(INET6) || defined(INET)
6143 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
6144 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
6145 TCP_LRO_ENTRIES, min(1024,
6146 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
6148 device_printf(ctx->ifc_dev,
6149 "LRO Initialization failed!\n");
6154 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
6157 #if defined(INET6) || defined(INET)
6160 * Free LRO resources allocated so far, we will only handle
6161 * the rings that completed, the failing case will have
6162 * cleaned up for itself. 'q' failed, so its the terminus.
6164 rxq = ctx->ifc_rxqs;
6165 for (i = 0; i < q; ++i, rxq++) {
6166 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
6167 tcp_lro_free(&rxq->ifr_lc);
6173 /*********************************************************************
6175 * Free all receive rings.
6177 **********************************************************************/
6179 iflib_rx_structures_free(if_ctx_t ctx)
6181 iflib_rxq_t rxq = ctx->ifc_rxqs;
6182 if_shared_ctx_t sctx = ctx->ifc_sctx;
6185 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
6186 for (j = 0; j < sctx->isc_nrxqs; j++)
6187 iflib_dma_free(&rxq->ifr_ifdi[j]);
6188 iflib_rx_sds_free(rxq);
6189 #if defined(INET6) || defined(INET)
6190 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
6191 tcp_lro_free(&rxq->ifr_lc);
6194 free(ctx->ifc_rxqs, M_IFLIB);
6195 ctx->ifc_rxqs = NULL;
6199 iflib_qset_structures_setup(if_ctx_t ctx)
6204 * It is expected that the caller takes care of freeing queues if this
6207 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
6208 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
6212 if ((err = iflib_rx_structures_setup(ctx)) != 0)
6213 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
6219 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
6220 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
6223 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
6226 /* Just to avoid copy/paste */
6228 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6229 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6233 unsigned int base_cpuid, cpuid;
6237 base_cpuid = ctx->ifc_sysctl_core_offset;
6238 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX);
6239 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev,
6240 irq ? irq->ii_res : NULL, name);
6242 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6246 if (cpuid > ctx->ifc_cpuid_highest)
6247 ctx->ifc_cpuid_highest = cpuid;
6253 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6254 iflib_intr_type_t type, driver_filter_t *filter,
6255 void *filter_arg, int qid, const char *name)
6258 struct grouptask *gtask;
6259 struct taskqgroup *tqg;
6260 iflib_filter_info_t info;
6263 driver_filter_t *intr_fast;
6266 info = &ctx->ifc_filter_info;
6270 /* XXX merge tx/rx for netmap? */
6272 q = &ctx->ifc_txqs[qid];
6273 info = &ctx->ifc_txqs[qid].ift_filter_info;
6274 gtask = &ctx->ifc_txqs[qid].ift_task;
6275 tqg = qgroup_if_io_tqg;
6277 intr_fast = iflib_fast_intr;
6278 GROUPTASK_INIT(gtask, 0, fn, q);
6279 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6282 q = &ctx->ifc_rxqs[qid];
6283 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6284 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6285 tqg = qgroup_if_io_tqg;
6287 intr_fast = iflib_fast_intr;
6288 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6290 case IFLIB_INTR_RXTX:
6291 q = &ctx->ifc_rxqs[qid];
6292 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6293 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6294 tqg = qgroup_if_io_tqg;
6296 intr_fast = iflib_fast_intr_rxtx;
6297 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6299 case IFLIB_INTR_ADMIN:
6302 info = &ctx->ifc_filter_info;
6303 gtask = &ctx->ifc_admin_task;
6304 tqg = qgroup_if_config_tqg;
6305 fn = _task_fn_admin;
6306 intr_fast = iflib_fast_intr_ctx;
6309 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6314 info->ifi_filter = filter;
6315 info->ifi_filter_arg = filter_arg;
6316 info->ifi_task = gtask;
6320 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6322 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6325 if (type == IFLIB_INTR_ADMIN)
6329 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6334 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6341 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6344 struct grouptask *gtask;
6345 struct taskqgroup *tqg;
6352 q = &ctx->ifc_txqs[qid];
6353 gtask = &ctx->ifc_txqs[qid].ift_task;
6354 tqg = qgroup_if_io_tqg;
6356 GROUPTASK_INIT(gtask, 0, fn, q);
6359 q = &ctx->ifc_rxqs[qid];
6360 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6361 tqg = qgroup_if_io_tqg;
6363 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6365 case IFLIB_INTR_IOV:
6367 gtask = &ctx->ifc_vflr_task;
6368 tqg = qgroup_if_config_tqg;
6370 GROUPTASK_INIT(gtask, 0, fn, q);
6373 panic("unknown net intr type");
6375 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name);
6378 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL,
6384 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6388 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6391 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6392 rman_get_rid(irq->ii_res), irq->ii_res);
6396 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6398 iflib_txq_t txq = ctx->ifc_txqs;
6399 iflib_rxq_t rxq = ctx->ifc_rxqs;
6400 if_irq_t irq = &ctx->ifc_legacy_irq;
6401 iflib_filter_info_t info;
6403 struct grouptask *gtask;
6404 struct resource *res;
6405 struct taskqgroup *tqg;
6410 q = &ctx->ifc_rxqs[0];
6411 info = &rxq[0].ifr_filter_info;
6412 gtask = &rxq[0].ifr_task;
6413 tqg = qgroup_if_io_tqg;
6415 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6417 ctx->ifc_flags |= IFC_LEGACY;
6418 info->ifi_filter = filter;
6419 info->ifi_filter_arg = filter_arg;
6420 info->ifi_task = gtask;
6421 info->ifi_ctx = rx_only ? ctx : q;
6424 /* We allocate a single interrupt resource */
6425 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6426 iflib_fast_intr_rxtx, NULL, info, name);
6429 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6431 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6433 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6434 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6440 iflib_led_create(if_ctx_t ctx)
6443 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6444 device_get_nameunit(ctx->ifc_dev));
6448 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6451 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6455 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6458 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6462 iflib_admin_intr_deferred(if_ctx_t ctx)
6465 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6466 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6470 iflib_iov_intr_deferred(if_ctx_t ctx)
6473 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6477 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6480 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6485 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6489 GROUPTASK_INIT(gtask, 0, fn, ctx);
6490 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6495 iflib_config_gtask_deinit(struct grouptask *gtask)
6498 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6502 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6504 if_t ifp = ctx->ifc_ifp;
6505 iflib_txq_t txq = ctx->ifc_txqs;
6507 if_setbaudrate(ifp, baudrate);
6508 if (baudrate >= IF_Gbps(10)) {
6510 ctx->ifc_flags |= IFC_PREFETCH;
6513 /* If link down, disable watchdog */
6514 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6515 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6516 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6518 ctx->ifc_link_state = link_state;
6519 if_link_state_change(ifp, link_state);
6523 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6527 int credits_pre = txq->ift_cidx_processed;
6530 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6531 BUS_DMASYNC_POSTREAD);
6532 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6535 txq->ift_processed += credits;
6536 txq->ift_cidx_processed += credits;
6538 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6539 if (txq->ift_cidx_processed >= txq->ift_size)
6540 txq->ift_cidx_processed -= txq->ift_size;
6545 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6550 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6551 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6552 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6553 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6558 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6559 const char *description, if_int_delay_info_t info,
6560 int offset, int value)
6562 info->iidi_ctx = ctx;
6563 info->iidi_offset = offset;
6564 info->iidi_value = value;
6565 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6566 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6567 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6568 info, 0, iflib_sysctl_int_delay, "I", description);
6572 iflib_ctx_lock_get(if_ctx_t ctx)
6575 return (&ctx->ifc_ctx_sx);
6579 iflib_msix_init(if_ctx_t ctx)
6581 device_t dev = ctx->ifc_dev;
6582 if_shared_ctx_t sctx = ctx->ifc_sctx;
6583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6584 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6585 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6587 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6588 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6591 device_printf(dev, "msix_init qsets capped at %d\n",
6592 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6594 /* Override by tuneable */
6595 if (scctx->isc_disable_msix)
6598 /* First try MSI-X */
6599 if ((msgs = pci_msix_count(dev)) == 0) {
6601 device_printf(dev, "MSI-X not supported or disabled\n");
6605 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6607 * bar == -1 => "trust me I know what I'm doing"
6608 * Some drivers are for hardware that is so shoddily
6609 * documented that no one knows which bars are which
6610 * so the developer has to map all bars. This hack
6611 * allows shoddy garbage to use MSI-X in this framework.
6614 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6615 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6616 if (ctx->ifc_msix_mem == NULL) {
6617 device_printf(dev, "Unable to map MSI-X table\n");
6622 admincnt = sctx->isc_admin_intrcnt;
6624 /* use only 1 qset in debug mode */
6625 queuemsgs = min(msgs - admincnt, 1);
6627 queuemsgs = msgs - admincnt;
6630 queues = imin(queuemsgs, rss_getnumbuckets());
6634 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6637 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6638 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6640 /* If we're doing RSS, clamp at the number of RSS buckets */
6641 if (queues > rss_getnumbuckets())
6642 queues = rss_getnumbuckets();
6644 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6645 rx_queues = iflib_num_rx_queues;
6649 if (rx_queues > scctx->isc_nrxqsets)
6650 rx_queues = scctx->isc_nrxqsets;
6653 * We want this to be all logical CPUs by default
6655 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6656 tx_queues = iflib_num_tx_queues;
6658 tx_queues = mp_ncpus;
6660 if (tx_queues > scctx->isc_ntxqsets)
6661 tx_queues = scctx->isc_ntxqsets;
6663 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6665 if (tx_queues != rx_queues)
6667 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6668 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6670 tx_queues = min(rx_queues, tx_queues);
6671 rx_queues = min(rx_queues, tx_queues);
6674 vectors = rx_queues + admincnt;
6675 if (msgs < vectors) {
6677 "insufficient number of MSI-X vectors "
6678 "(supported %d, need %d)\n", msgs, vectors);
6682 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6685 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6686 if (vectors != msgs) {
6688 "Unable to allocate sufficient MSI-X vectors "
6689 "(got %d, need %d)\n", vectors, msgs);
6690 pci_release_msi(dev);
6692 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6694 ctx->ifc_msix_mem = NULL;
6698 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6700 scctx->isc_vectors = vectors;
6701 scctx->isc_nrxqsets = rx_queues;
6702 scctx->isc_ntxqsets = tx_queues;
6703 scctx->isc_intr = IFLIB_INTR_MSIX;
6708 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6711 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6713 ctx->ifc_msix_mem = NULL;
6718 vectors = pci_msi_count(dev);
6719 scctx->isc_nrxqsets = 1;
6720 scctx->isc_ntxqsets = 1;
6721 scctx->isc_vectors = vectors;
6722 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6723 device_printf(dev,"Using an MSI interrupt\n");
6724 scctx->isc_intr = IFLIB_INTR_MSI;
6726 scctx->isc_vectors = 1;
6727 device_printf(dev,"Using a Legacy interrupt\n");
6728 scctx->isc_intr = IFLIB_INTR_LEGACY;
6734 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6737 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6740 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6742 const char *ring_state = "UNKNOWN";
6745 rc = sysctl_wire_old_buffer(req, 0);
6749 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6754 ring_state = ring_states[state[3]];
6756 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6757 state[0], state[1], state[2], ring_state);
6758 rc = sbuf_finish(sb);
6763 enum iflib_ndesc_handler {
6769 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6771 if_ctx_t ctx = (void *)arg1;
6772 enum iflib_ndesc_handler type = arg2;
6773 char buf[256] = {0};
6780 case IFLIB_NTXD_HANDLER:
6781 ndesc = ctx->ifc_sysctl_ntxds;
6783 nqs = ctx->ifc_sctx->isc_ntxqs;
6785 case IFLIB_NRXD_HANDLER:
6786 ndesc = ctx->ifc_sysctl_nrxds;
6788 nqs = ctx->ifc_sctx->isc_nrxqs;
6791 printf("%s: unhandled type\n", __func__);
6797 for (i=0; i<8; i++) {
6802 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6805 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6806 if (rc || req->newptr == NULL)
6809 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6810 i++, p = strsep(&next, " ,")) {
6811 ndesc[i] = strtoul(p, NULL, 10);
6817 #define NAME_BUFLEN 32
6819 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6821 device_t dev = iflib_get_dev(ctx);
6822 struct sysctl_oid_list *child, *oid_list;
6823 struct sysctl_ctx_list *ctx_list;
6824 struct sysctl_oid *node;
6826 ctx_list = device_get_sysctl_ctx(dev);
6827 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6828 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6829 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6830 oid_list = SYSCTL_CHILDREN(node);
6832 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6833 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6836 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6837 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6838 "# of txqs to use, 0 => use default #");
6839 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6840 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6841 "# of rxqs to use, 0 => use default #");
6842 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6843 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6844 "permit #txq != #rxq");
6845 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6846 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6847 "disable MSI-X (default 0)");
6848 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6849 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6850 "set the RX budget");
6851 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6852 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6853 "cause TX to abdicate instead of running to completion");
6854 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6855 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6856 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6857 "offset to start using cores at");
6858 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6859 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6860 "use separate cores for TX and RX");
6861 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores",
6862 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0,
6863 "try to make use of logical cores for TX and RX");
6865 /* XXX change for per-queue sizes */
6866 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6867 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6868 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6869 "list of # of TX descriptors to use, 0 = use default #");
6870 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6871 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6872 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6873 "list of # of RX descriptors to use, 0 = use default #");
6877 iflib_add_device_sysctl_post(if_ctx_t ctx)
6879 if_shared_ctx_t sctx = ctx->ifc_sctx;
6880 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6881 device_t dev = iflib_get_dev(ctx);
6882 struct sysctl_oid_list *child;
6883 struct sysctl_ctx_list *ctx_list;
6888 char namebuf[NAME_BUFLEN];
6890 struct sysctl_oid *queue_node, *fl_node, *node;
6891 struct sysctl_oid_list *queue_list, *fl_list;
6892 ctx_list = device_get_sysctl_ctx(dev);
6894 node = ctx->ifc_sysctl_node;
6895 child = SYSCTL_CHILDREN(node);
6897 if (scctx->isc_ntxqsets > 100)
6899 else if (scctx->isc_ntxqsets > 10)
6903 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6904 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6905 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6906 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6907 queue_list = SYSCTL_CHILDREN(queue_node);
6908 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6910 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to");
6912 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6914 &txq->ift_dequeued, "total mbufs freed");
6915 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6917 &txq->ift_enqueued, "total mbufs enqueued");
6919 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6921 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6922 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6924 &txq->ift_pullups, "# of times m_pullup was called");
6925 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6927 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6928 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6930 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6931 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6933 &txq->ift_map_failed, "# of times DMA map failed");
6934 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6936 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6937 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6939 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6940 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6942 &txq->ift_pidx, 1, "Producer Index");
6943 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6945 &txq->ift_cidx, 1, "Consumer Index");
6946 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6948 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6949 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6951 &txq->ift_in_use, 1, "descriptors in use");
6952 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6954 &txq->ift_processed, "descriptors procesed for clean");
6955 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6957 &txq->ift_cleaned, "total cleaned");
6958 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6959 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6960 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6961 mp_ring_state_handler, "A", "soft ring state");
6962 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6963 CTLFLAG_RD, &txq->ift_br->enqueues,
6964 "# of enqueues to the mp_ring for this queue");
6965 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6966 CTLFLAG_RD, &txq->ift_br->drops,
6967 "# of drops in the mp_ring for this queue");
6968 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6969 CTLFLAG_RD, &txq->ift_br->starts,
6970 "# of normal consumer starts in the mp_ring for this queue");
6971 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6972 CTLFLAG_RD, &txq->ift_br->stalls,
6973 "# of consumer stalls in the mp_ring for this queue");
6974 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6975 CTLFLAG_RD, &txq->ift_br->restarts,
6976 "# of consumer restarts in the mp_ring for this queue");
6977 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6978 CTLFLAG_RD, &txq->ift_br->abdications,
6979 "# of consumer abdications in the mp_ring for this queue");
6982 if (scctx->isc_nrxqsets > 100)
6984 else if (scctx->isc_nrxqsets > 10)
6988 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6989 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6990 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6991 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6992 queue_list = SYSCTL_CHILDREN(queue_node);
6993 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6995 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to");
6996 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6997 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6999 &rxq->ifr_cq_cidx, 1, "Consumer Index");
7002 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
7003 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
7004 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
7005 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
7006 fl_list = SYSCTL_CHILDREN(fl_node);
7007 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
7009 &fl->ifl_pidx, 1, "Producer Index");
7010 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
7012 &fl->ifl_cidx, 1, "Consumer Index");
7013 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
7015 &fl->ifl_credits, 1, "credits available");
7016 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
7018 &fl->ifl_buf_size, 1, "buffer size");
7020 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
7022 &fl->ifl_m_enqueued, "mbufs allocated");
7023 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
7025 &fl->ifl_m_dequeued, "mbufs freed");
7026 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
7028 &fl->ifl_cl_enqueued, "clusters allocated");
7029 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
7031 &fl->ifl_cl_dequeued, "clusters freed");
7039 iflib_request_reset(if_ctx_t ctx)
7043 ctx->ifc_flags |= IFC_DO_RESET;
7047 #ifndef __NO_STRICT_ALIGNMENT
7048 static struct mbuf *
7049 iflib_fixup_rx(struct mbuf *m)
7053 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
7054 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
7055 m->m_data += ETHER_HDR_LEN;
7058 MGETHDR(n, M_NOWAIT, MT_DATA);
7063 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
7064 m->m_data += ETHER_HDR_LEN;
7065 m->m_len -= ETHER_HDR_LEN;
7066 n->m_len = ETHER_HDR_LEN;
7067 M_MOVE_PKTHDR(n, m);
7076 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
7080 ctx = if_getsoftc(ifp);
7082 *nrxr = NRXQSETS(ctx);
7083 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
7084 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
7089 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
7092 if_softc_ctx_t scctx;
7097 ctx = if_getsoftc(ifp);
7098 scctx = &ctx->ifc_softc_ctx;
7101 case DEBUGNET_START:
7102 for (i = 0; i < scctx->isc_nrxqsets; i++) {
7103 rxq = &ctx->ifc_rxqs[i];
7104 for (j = 0; j < rxq->ifr_nfl; j++) {
7106 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
7109 iflib_no_tx_batch = 1;
7117 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
7123 ctx = if_getsoftc(ifp);
7124 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7128 txq = &ctx->ifc_txqs[0];
7129 error = iflib_encap(txq, &m);
7131 (void)iflib_txd_db_check(txq, true);
7136 iflib_debugnet_poll(if_t ifp, int count)
7138 struct epoch_tracker et;
7140 if_softc_ctx_t scctx;
7144 ctx = if_getsoftc(ifp);
7145 scctx = &ctx->ifc_softc_ctx;
7147 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7151 txq = &ctx->ifc_txqs[0];
7152 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
7154 NET_EPOCH_ENTER(et);
7155 for (i = 0; i < scctx->isc_nrxqsets; i++)
7156 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7160 #endif /* DEBUGNET */