2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet/netdump/netdump.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
133 typedef struct iflib_txq *iflib_txq_t;
135 typedef struct iflib_rxq *iflib_rxq_t;
137 typedef struct iflib_fl *iflib_fl_t;
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
144 typedef struct iflib_filter_info {
145 driver_filter_t *ifi_filter;
146 void *ifi_filter_arg;
147 struct grouptask *ifi_task;
149 } *iflib_filter_info_t;
154 * Pointer to hardware driver's softc
161 if_shared_ctx_t ifc_sctx;
162 struct if_softc_ctx ifc_softc_ctx;
164 struct sx ifc_ctx_sx;
165 struct mtx ifc_state_mtx;
167 iflib_txq_t ifc_txqs;
168 iflib_rxq_t ifc_rxqs;
169 uint32_t ifc_if_flags;
171 uint32_t ifc_max_fl_buf_size;
172 uint32_t ifc_rx_mbuf_sz;
175 int ifc_watchdog_events;
176 struct cdev *ifc_led_dev;
177 struct resource *ifc_msix_mem;
179 struct if_irq ifc_legacy_irq;
180 struct grouptask ifc_admin_task;
181 struct grouptask ifc_vflr_task;
182 struct iflib_filter_info ifc_filter_info;
183 struct ifmedia ifc_media;
184 struct ifmedia *ifc_mediap;
186 struct sysctl_oid *ifc_sysctl_node;
187 uint16_t ifc_sysctl_ntxqs;
188 uint16_t ifc_sysctl_nrxqs;
189 uint16_t ifc_sysctl_qs_eq_override;
190 uint16_t ifc_sysctl_rx_budget;
191 uint16_t ifc_sysctl_tx_abdicate;
192 uint16_t ifc_sysctl_core_offset;
193 #define CORE_OFFSET_UNSPECIFIED 0xffff
194 uint8_t ifc_sysctl_separate_txrx;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 struct ether_addr ifc_mac;
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (ctx->ifc_mediap);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 #define IFLIB_RX_COPY_THRESH 128
292 #define IFLIB_MAX_RX_REFRESH 32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC 16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
296 #define IFLIB_QUEUE_IDLE 0
297 #define IFLIB_QUEUE_HUNG 1
298 #define IFLIB_QUEUE_WORKING 2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR 4
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE 32
305 #define IFLIB_RESTART_BUDGET 8
307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
314 qidx_t ift_cidx_processed;
317 uint8_t ift_br_offset;
318 uint16_t ift_npending;
319 uint16_t ift_db_pending;
320 uint16_t ift_rs_pending;
322 uint8_t ift_txd_size[8];
323 uint64_t ift_processed;
324 uint64_t ift_cleaned;
325 uint64_t ift_cleaned_prev;
327 uint64_t ift_enqueued;
328 uint64_t ift_dequeued;
330 uint64_t ift_no_tx_dma_setup;
331 uint64_t ift_no_desc_avail;
332 uint64_t ift_mbuf_defrag_failed;
333 uint64_t ift_mbuf_defrag;
334 uint64_t ift_map_failed;
335 uint64_t ift_txd_encap_efbig;
336 uint64_t ift_pullups;
337 uint64_t ift_last_timer_tick;
340 struct mtx ift_db_mtx;
342 /* constant values */
344 struct ifmp_ring *ift_br;
345 struct grouptask ift_task;
348 struct callout ift_timer;
350 if_txsd_vec_t ift_sds;
353 uint8_t ift_update_freq;
354 struct iflib_filter_info ift_filter_info;
355 bus_dma_tag_t ift_buf_tag;
356 bus_dma_tag_t ift_tso_buf_tag;
357 iflib_dma_info_t ift_ifdi;
358 #define MTX_NAME_LEN 16
359 char ift_mtx_name[MTX_NAME_LEN];
360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 uint64_t ift_cpu_exec_count[256];
364 } __aligned(CACHE_LINE_SIZE);
371 uint8_t ifl_rxd_size;
373 uint64_t ifl_m_enqueued;
374 uint64_t ifl_m_dequeued;
375 uint64_t ifl_cl_enqueued;
376 uint64_t ifl_cl_dequeued;
380 bitstr_t *ifl_rx_bitmap;
384 uint16_t ifl_buf_size;
387 iflib_rxsd_array_t ifl_sds;
390 bus_dma_tag_t ifl_buf_tag;
391 iflib_dma_info_t ifl_ifdi;
392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
393 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
394 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
395 } __aligned(CACHE_LINE_SIZE);
398 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
404 else if (pidx < cidx)
405 used = size - cidx + pidx;
406 else if (gen == 0 && pidx == cidx)
408 else if (gen == 1 && pidx == cidx)
416 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
418 #define IDXDIFF(head, tail, wrap) \
419 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
425 struct pfil_head *pfil;
427 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
428 * the command queue consumer index. Otherwise it's unused.
434 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
435 uint8_t ifr_fl_offset;
436 struct lro_ctrl ifr_lc;
437 struct grouptask ifr_task;
438 struct iflib_filter_info ifr_filter_info;
439 iflib_dma_info_t ifr_ifdi;
441 /* dynamically allocate if any drivers need a value substantially larger than this */
442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 uint64_t ifr_cpu_exec_count[256];
446 } __aligned(CACHE_LINE_SIZE);
448 typedef struct if_rxsd {
454 /* multiple of word size */
456 #define PKT_INFO_SIZE 6
457 #define RXD_INFO_SIZE 5
458 #define PKT_TYPE uint64_t
460 #define PKT_INFO_SIZE 11
461 #define RXD_INFO_SIZE 8
462 #define PKT_TYPE uint32_t
464 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
465 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
467 typedef struct if_pkt_info_pad {
468 PKT_TYPE pkt_val[PKT_INFO_SIZE];
469 } *if_pkt_info_pad_t;
470 typedef struct if_rxd_info_pad {
471 PKT_TYPE rxd_val[RXD_INFO_SIZE];
472 } *if_rxd_info_pad_t;
474 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
475 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
479 pkt_info_zero(if_pkt_info_t pi)
481 if_pkt_info_pad_t pi_pad;
483 pi_pad = (if_pkt_info_pad_t)pi;
484 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
485 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
487 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
488 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
492 static device_method_t iflib_pseudo_methods[] = {
493 DEVMETHOD(device_attach, noop_attach),
494 DEVMETHOD(device_detach, iflib_pseudo_detach),
498 driver_t iflib_pseudodriver = {
499 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
503 rxd_info_zero(if_rxd_info_t ri)
505 if_rxd_info_pad_t ri_pad;
508 ri_pad = (if_rxd_info_pad_t)ri;
509 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
510 ri_pad->rxd_val[i] = 0;
511 ri_pad->rxd_val[i+1] = 0;
512 ri_pad->rxd_val[i+2] = 0;
513 ri_pad->rxd_val[i+3] = 0;
516 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
521 * Only allow a single packet to take up most 1/nth of the tx ring
523 #define MAX_SINGLE_PACKET_FRACTION 12
524 #define IF_BAD_DMA (bus_addr_t)-1
526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
528 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
529 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
531 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
533 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
534 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
535 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
536 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
538 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
539 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
542 iflib_set_detach(if_ctx_t ctx)
545 ctx->ifc_flags |= IFC_IN_DETACH;
549 /* Our boot-time initialization hook */
550 static int iflib_module_event_handler(module_t, int, void *);
552 static moduledata_t iflib_moduledata = {
554 iflib_module_event_handler,
558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
559 MODULE_VERSION(iflib, 1);
561 MODULE_DEPEND(iflib, pci, 1, 1, 1);
562 MODULE_DEPEND(iflib, ether, 1, 1, 1);
564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
567 #ifndef IFLIB_DEBUG_COUNTERS
569 #define IFLIB_DEBUG_COUNTERS 1
571 #define IFLIB_DEBUG_COUNTERS 0
572 #endif /* !INVARIANTS */
575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
576 "iflib driver parameters");
579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
581 static int iflib_min_tx_latency = 0;
582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
584 static int iflib_no_tx_batch = 0;
585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
589 #if IFLIB_DEBUG_COUNTERS
591 static int iflib_tx_seen;
592 static int iflib_tx_sent;
593 static int iflib_tx_encap;
594 static int iflib_rx_allocs;
595 static int iflib_fl_refills;
596 static int iflib_fl_refills_large;
597 static int iflib_tx_frees;
599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
600 &iflib_tx_seen, 0, "# TX mbufs seen");
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
602 &iflib_tx_sent, 0, "# TX mbufs sent");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
604 &iflib_tx_encap, 0, "# TX mbufs encapped");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
606 &iflib_tx_frees, 0, "# TX frees");
607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
608 &iflib_rx_allocs, 0, "# RX allocations");
609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
610 &iflib_fl_refills, 0, "# refills");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
612 &iflib_fl_refills_large, 0, "# large refills");
615 static int iflib_txq_drain_flushing;
616 static int iflib_txq_drain_oactive;
617 static int iflib_txq_drain_notready;
619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
620 &iflib_txq_drain_flushing, 0, "# drain flushes");
621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
622 &iflib_txq_drain_oactive, 0, "# drain oactives");
623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
624 &iflib_txq_drain_notready, 0, "# drain notready");
627 static int iflib_encap_load_mbuf_fail;
628 static int iflib_encap_pad_mbuf_fail;
629 static int iflib_encap_txq_avail_fail;
630 static int iflib_encap_txd_encap_fail;
632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
633 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
635 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
637 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
639 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
641 static int iflib_task_fn_rxs;
642 static int iflib_rx_intr_enables;
643 static int iflib_fast_intrs;
644 static int iflib_rx_unavail;
645 static int iflib_rx_ctx_inactive;
646 static int iflib_rx_if_input;
647 static int iflib_rxd_flush;
649 static int iflib_verbose_debug;
651 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
652 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
654 &iflib_rx_intr_enables, 0, "# RX intr enables");
655 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
656 &iflib_fast_intrs, 0, "# fast_intr calls");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
658 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
660 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
662 &iflib_rx_if_input, 0, "# times rxeof called if_input");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
664 &iflib_rxd_flush, 0, "# times rxd_flush called");
665 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
666 &iflib_verbose_debug, 0, "enable verbose debugging");
668 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
670 iflib_debug_reset(void)
672 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
673 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
674 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
675 iflib_txq_drain_notready =
676 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
677 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
678 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
680 iflib_rx_ctx_inactive = iflib_rx_if_input =
685 #define DBG_COUNTER_INC(name)
686 static void iflib_debug_reset(void) {}
689 #define IFLIB_DEBUG 0
691 static void iflib_tx_structures_free(if_ctx_t ctx);
692 static void iflib_rx_structures_free(if_ctx_t ctx);
693 static int iflib_queues_alloc(if_ctx_t ctx);
694 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
695 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
696 static int iflib_qset_structures_setup(if_ctx_t ctx);
697 static int iflib_msix_init(if_ctx_t ctx);
698 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
699 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
700 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
702 static void iflib_altq_if_start(if_t ifp);
703 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
705 static int iflib_register(if_ctx_t);
706 static void iflib_init_locked(if_ctx_t ctx);
707 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
709 static void iflib_ifmp_purge(iflib_txq_t txq);
710 static void _iflib_pre_assert(if_softc_ctx_t scctx);
711 static void iflib_if_init_locked(if_ctx_t ctx);
712 static void iflib_free_intr_mem(if_ctx_t ctx);
713 #ifndef __NO_STRICT_ALIGNMENT
714 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
718 SLIST_HEAD_INITIALIZER(cpu_offsets);
720 SLIST_ENTRY(cpu_offset) entries;
722 unsigned int refcount;
725 static struct mtx cpu_offset_mtx;
726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
729 NETDUMP_DEFINE(iflib);
732 #include <sys/selinfo.h>
733 #include <net/netmap.h>
734 #include <dev/netmap/netmap_kern.h>
736 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
738 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
741 * device-specific sysctl variables:
743 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
744 * During regular operations the CRC is stripped, but on some
745 * hardware reception of frames not multiple of 64 is slower,
746 * so using crcstrip=0 helps in benchmarks.
748 * iflib_rx_miss, iflib_rx_miss_bufs:
749 * count packets that might be missed due to lost interrupts.
751 SYSCTL_DECL(_dev_netmap);
753 * The xl driver by default strips CRCs and we do not override it.
756 int iflib_crcstrip = 1;
757 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
758 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
760 int iflib_rx_miss, iflib_rx_miss_bufs;
761 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
762 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
764 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
767 * Register/unregister. We are already under netmap lock.
768 * Only called on the first register or the last unregister.
771 iflib_netmap_register(struct netmap_adapter *na, int onoff)
774 if_ctx_t ctx = ifp->if_softc;
778 IFDI_INTR_DISABLE(ctx);
780 /* Tell the stack that the interface is no longer active */
781 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
784 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
786 /* enable or disable flags and callbacks in na and ifp */
788 nm_set_native_flags(na);
790 nm_clear_native_flags(na);
793 iflib_init_locked(ctx);
794 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
795 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
797 nm_clear_native_flags(na);
803 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
805 struct netmap_adapter *na = kring->na;
806 u_int const lim = kring->nkr_num_slots - 1;
807 u_int head = kring->rhead;
808 struct netmap_ring *ring = kring->ring;
810 struct if_rxd_update iru;
811 if_ctx_t ctx = rxq->ifr_ctx;
812 iflib_fl_t fl = &rxq->ifr_fl[0];
813 uint32_t refill_pidx, nic_i;
814 #if IFLIB_DEBUG_COUNTERS
818 if (nm_i == head && __predict_true(!init))
820 iru_init(&iru, rxq, 0 /* flid */);
821 map = fl->ifl_sds.ifsd_map;
822 refill_pidx = netmap_idx_k2n(kring, nm_i);
824 * IMPORTANT: we must leave one free slot in the ring,
825 * so move head back by one unit
827 head = nm_prev(head, lim);
829 DBG_COUNTER_INC(fl_refills);
830 while (nm_i != head) {
831 #if IFLIB_DEBUG_COUNTERS
833 DBG_COUNTER_INC(fl_refills_large);
835 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
836 struct netmap_slot *slot = &ring->slot[nm_i];
837 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
838 uint32_t nic_i_dma = refill_pidx;
839 nic_i = netmap_idx_k2n(kring, nm_i);
841 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
843 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
844 return netmap_ring_reinit(kring);
846 fl->ifl_vm_addrs[tmp_pidx] = addr;
847 if (__predict_false(init)) {
848 netmap_load_map(na, fl->ifl_buf_tag,
850 } else if (slot->flags & NS_BUF_CHANGED) {
851 /* buffer has changed, reload map */
852 netmap_reload_map(na, fl->ifl_buf_tag,
855 slot->flags &= ~NS_BUF_CHANGED;
857 nm_i = nm_next(nm_i, lim);
858 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
859 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
862 iru.iru_pidx = refill_pidx;
863 iru.iru_count = tmp_pidx+1;
864 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
866 for (int n = 0; n < iru.iru_count; n++) {
867 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
868 BUS_DMASYNC_PREREAD);
869 /* XXX - change this to not use the netmap func*/
870 nic_i_dma = nm_next(nic_i_dma, lim);
874 kring->nr_hwcur = head;
876 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
878 if (__predict_true(nic_i != UINT_MAX)) {
879 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
880 DBG_COUNTER_INC(rxd_flush);
886 * Reconcile kernel and user view of the transmit ring.
888 * All information is in the kring.
889 * Userspace wants to send packets up to the one before kring->rhead,
890 * kernel knows kring->nr_hwcur is the first unsent packet.
892 * Here we push packets out (as many as possible), and possibly
893 * reclaim buffers from previously completed transmission.
895 * The caller (netmap) guarantees that there is only one instance
896 * running at any time. Any interference with other driver
897 * methods should be handled by the individual drivers.
900 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
902 struct netmap_adapter *na = kring->na;
904 struct netmap_ring *ring = kring->ring;
905 u_int nm_i; /* index into the netmap kring */
906 u_int nic_i; /* index into the NIC ring */
908 u_int const lim = kring->nkr_num_slots - 1;
909 u_int const head = kring->rhead;
910 struct if_pkt_info pi;
913 * interrupts on every tx packet are expensive so request
914 * them every half ring, or where NS_REPORT is set
916 u_int report_frequency = kring->nkr_num_slots >> 1;
917 /* device-specific */
918 if_ctx_t ctx = ifp->if_softc;
919 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
921 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
922 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
925 * First part: process new packets to send.
926 * nm_i is the current index in the netmap kring,
927 * nic_i is the corresponding index in the NIC ring.
929 * If we have packets to send (nm_i != head)
930 * iterate over the netmap ring, fetch length and update
931 * the corresponding slot in the NIC ring. Some drivers also
932 * need to update the buffer's physical address in the NIC slot
933 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
935 * The netmap_reload_map() calls is especially expensive,
936 * even when (as in this case) the tag is 0, so do only
937 * when the buffer has actually changed.
939 * If possible do not set the report/intr bit on all slots,
940 * but only a few times per ring or when NS_REPORT is set.
942 * Finally, on 10G and faster drivers, it might be useful
943 * to prefetch the next slot and txr entry.
946 nm_i = kring->nr_hwcur;
947 if (nm_i != head) { /* we have new packets to send */
949 pi.ipi_segs = txq->ift_segs;
950 pi.ipi_qsidx = kring->ring_id;
951 nic_i = netmap_idx_k2n(kring, nm_i);
953 __builtin_prefetch(&ring->slot[nm_i]);
954 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
955 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
957 for (n = 0; nm_i != head; n++) {
958 struct netmap_slot *slot = &ring->slot[nm_i];
959 u_int len = slot->len;
961 void *addr = PNMB(na, slot, &paddr);
962 int flags = (slot->flags & NS_REPORT ||
963 nic_i == 0 || nic_i == report_frequency) ?
966 /* device-specific */
968 pi.ipi_segs[0].ds_addr = paddr;
969 pi.ipi_segs[0].ds_len = len;
973 pi.ipi_flags = flags;
975 /* Fill the slot in the NIC ring. */
976 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
977 DBG_COUNTER_INC(tx_encap);
979 /* prefetch for next round */
980 __builtin_prefetch(&ring->slot[nm_i + 1]);
981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
982 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
984 NM_CHECK_ADDR_LEN(na, addr, len);
986 if (slot->flags & NS_BUF_CHANGED) {
987 /* buffer has changed, reload map */
988 netmap_reload_map(na, txq->ift_buf_tag,
989 txq->ift_sds.ifsd_map[nic_i], addr);
991 /* make sure changes to the buffer are synced */
992 bus_dmamap_sync(txq->ift_buf_tag,
993 txq->ift_sds.ifsd_map[nic_i],
994 BUS_DMASYNC_PREWRITE);
996 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
997 nm_i = nm_next(nm_i, lim);
998 nic_i = nm_next(nic_i, lim);
1000 kring->nr_hwcur = nm_i;
1002 /* synchronize the NIC ring */
1003 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1006 /* (re)start the tx unit up to slot nic_i (excluded) */
1007 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1011 * Second part: reclaim buffers for completed transmissions.
1013 * If there are unclaimed buffers, attempt to reclaim them.
1014 * If none are reclaimed, and TX IRQs are not in use, do an initial
1015 * minimal delay, then trigger the tx handler which will spin in the
1018 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1019 if (iflib_tx_credits_update(ctx, txq)) {
1020 /* some tx completed, increment avail */
1021 nic_i = txq->ift_cidx_processed;
1022 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1025 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1026 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1027 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1028 iflib_timer, txq, txq->ift_timer.c_cpu);
1034 * Reconcile kernel and user view of the receive ring.
1035 * Same as for the txsync, this routine must be efficient.
1036 * The caller guarantees a single invocations, but races against
1037 * the rest of the driver should be handled here.
1039 * On call, kring->rhead is the first packet that userspace wants
1040 * to keep, and kring->rcur is the wakeup point.
1041 * The kernel has previously reported packets up to kring->rtail.
1043 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1044 * of whether or not we received an interrupt.
1047 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1049 struct netmap_adapter *na = kring->na;
1050 struct netmap_ring *ring = kring->ring;
1053 uint32_t nm_i; /* index into the netmap ring */
1054 uint32_t nic_i; /* index into the NIC ring */
1056 u_int const lim = kring->nkr_num_slots - 1;
1057 u_int const head = kring->rhead;
1058 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1059 struct if_rxd_info ri;
1061 if_ctx_t ctx = ifp->if_softc;
1062 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1064 return netmap_ring_reinit(kring);
1067 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1070 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1071 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1072 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1076 * First part: import newly received packets.
1078 * nm_i is the index of the next free slot in the netmap ring,
1079 * nic_i is the index of the next received packet in the NIC ring,
1080 * and they may differ in case if_init() has been called while
1081 * in netmap mode. For the receive ring we have
1083 * nic_i = rxr->next_check;
1084 * nm_i = kring->nr_hwtail (previous)
1086 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1088 * rxr->next_check is set to 0 on a ring reinit
1090 if (netmap_no_pendintr || force_update) {
1091 int crclen = iflib_crcstrip ? 0 : 4;
1094 for (i = 0; i < rxq->ifr_nfl; i++) {
1095 fl = &rxq->ifr_fl[i];
1096 nic_i = fl->ifl_cidx;
1097 nm_i = netmap_idx_n2k(kring, nic_i);
1098 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1099 rxq->ifr_id, nic_i, USHRT_MAX);
1100 for (n = 0; avail > 0; n++, avail--) {
1102 ri.iri_frags = rxq->ifr_frags;
1103 ri.iri_qsidx = kring->ring_id;
1104 ri.iri_ifp = ctx->ifc_ifp;
1105 ri.iri_cidx = nic_i;
1107 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1108 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1109 ring->slot[nm_i].flags = 0;
1110 bus_dmamap_sync(fl->ifl_buf_tag,
1111 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1112 nm_i = nm_next(nm_i, lim);
1113 nic_i = nm_next(nic_i, lim);
1115 if (n) { /* update the state variables */
1116 if (netmap_no_pendintr && !force_update) {
1119 iflib_rx_miss_bufs += n;
1121 fl->ifl_cidx = nic_i;
1122 kring->nr_hwtail = nm_i;
1124 kring->nr_kflags &= ~NKR_PENDINTR;
1128 * Second part: skip past packets that userspace has released.
1129 * (kring->nr_hwcur to head excluded),
1130 * and make the buffers available for reception.
1131 * As usual nm_i is the index in the netmap ring,
1132 * nic_i is the index in the NIC ring, and
1133 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1135 /* XXX not sure how this will work with multiple free lists */
1136 nm_i = kring->nr_hwcur;
1138 return (netmap_fl_refill(rxq, kring, nm_i, false));
1142 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1144 if_ctx_t ctx = na->ifp->if_softc;
1148 IFDI_INTR_ENABLE(ctx);
1150 IFDI_INTR_DISABLE(ctx);
1157 iflib_netmap_attach(if_ctx_t ctx)
1159 struct netmap_adapter na;
1160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1162 bzero(&na, sizeof(na));
1164 na.ifp = ctx->ifc_ifp;
1165 na.na_flags = NAF_BDG_MAYSLEEP;
1166 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1167 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1169 na.num_tx_desc = scctx->isc_ntxd[0];
1170 na.num_rx_desc = scctx->isc_nrxd[0];
1171 na.nm_txsync = iflib_netmap_txsync;
1172 na.nm_rxsync = iflib_netmap_rxsync;
1173 na.nm_register = iflib_netmap_register;
1174 na.nm_intr = iflib_netmap_intr;
1175 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1176 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1177 return (netmap_attach(&na));
1181 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1183 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1184 struct netmap_slot *slot;
1186 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1189 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1192 * In netmap mode, set the map for the packet buffer.
1193 * NOTE: Some drivers (not this one) also need to set
1194 * the physical buffer address in the NIC ring.
1195 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1196 * netmap slot index, si
1198 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1199 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1200 NMB(na, slot + si));
1205 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1207 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1208 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1209 struct netmap_slot *slot;
1212 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1215 nm_i = netmap_idx_n2k(kring, 0);
1216 netmap_fl_refill(rxq, kring, nm_i, true);
1220 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1222 struct netmap_kring *kring;
1225 txqid = txq->ift_id;
1226 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1228 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1229 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1230 BUS_DMASYNC_POSTREAD);
1231 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1232 netmap_tx_irq(ctx->ifc_ifp, txqid);
1233 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1237 *reset_on = hz / 1000;
1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1245 #define iflib_netmap_txq_init(ctx, txq)
1246 #define iflib_netmap_rxq_init(ctx, rxq)
1247 #define iflib_netmap_detach(ifp)
1249 #define iflib_netmap_attach(ctx) (0)
1250 #define netmap_rx_irq(ifp, qid, budget) (0)
1251 #define netmap_tx_irq(ifp, qid) do {} while (0)
1252 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1256 #if defined(__i386__) || defined(__amd64__)
1257 static __inline void
1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1262 static __inline void
1263 prefetch2cachelines(void *x)
1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1266 #if (CACHE_LINE_SIZE < 128)
1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1272 #define prefetch2cachelines(x)
1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1280 fl = &rxq->ifr_fl[flid];
1281 iru->iru_paddrs = fl->ifl_bus_addrs;
1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1283 iru->iru_idxs = fl->ifl_rxd_idxs;
1284 iru->iru_qsidx = rxq->ifr_id;
1285 iru->iru_buf_size = fl->ifl_buf_size;
1286 iru->iru_flidx = fl->ifl_id;
1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1294 *(bus_addr_t *) arg = segs[0].ds_addr;
1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1301 device_t dev = ctx->ifc_dev;
1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1304 align, 0, /* alignment, bounds */
1305 BUS_SPACE_MAXADDR, /* lowaddr */
1306 BUS_SPACE_MAXADDR, /* highaddr */
1307 NULL, NULL, /* filter, filterarg */
1310 size, /* maxsegsize */
1311 BUS_DMA_ALLOCNOW, /* flags */
1312 NULL, /* lockfunc */
1317 "%s: bus_dma_tag_create failed: %d\n",
1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1327 __func__, (uintmax_t)size, err);
1331 dma->idi_paddr = IF_BAD_DMA;
1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1334 if (err || dma->idi_paddr == IF_BAD_DMA) {
1336 "%s: bus_dmamap_load failed: %d\n",
1341 dma->idi_size = size;
1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1347 bus_dma_tag_destroy(dma->idi_tag);
1349 dma->idi_tag = NULL;
1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1357 if_shared_ctx_t sctx = ctx->ifc_sctx;
1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1368 iflib_dma_info_t *dmaiter;
1371 for (i = 0; i < count; i++, dmaiter++) {
1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1376 iflib_dma_free_multi(dmalist, i);
1381 iflib_dma_free(iflib_dma_info_t dma)
1383 if (dma->idi_tag == NULL)
1385 if (dma->idi_paddr != IF_BAD_DMA) {
1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1389 dma->idi_paddr = IF_BAD_DMA;
1391 if (dma->idi_vaddr != NULL) {
1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1393 dma->idi_vaddr = NULL;
1395 bus_dma_tag_destroy(dma->idi_tag);
1396 dma->idi_tag = NULL;
1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1403 iflib_dma_info_t *dmaiter = dmalist;
1405 for (i = 0; i < count; i++, dmaiter++)
1406 iflib_dma_free(*dmaiter);
1409 #ifdef EARLY_AP_STARTUP
1410 static const int iflib_started = 1;
1413 * We used to abuse the smp_started flag to decide if the queues have been
1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1416 * is set. Run a SYSINIT() strictly after that to just set a usable
1420 static int iflib_started;
1423 iflib_record_started(void *arg)
1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1429 iflib_record_started, NULL);
1433 iflib_fast_intr(void *arg)
1435 iflib_filter_info_t info = arg;
1436 struct grouptask *gtask = info->ifi_task;
1440 return (FILTER_STRAY);
1442 DBG_COUNTER_INC(fast_intrs);
1443 if (info->ifi_filter != NULL) {
1444 result = info->ifi_filter(info->ifi_filter_arg);
1445 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1449 GROUPTASK_ENQUEUE(gtask);
1450 return (FILTER_HANDLED);
1454 iflib_fast_intr_rxtx(void *arg)
1456 iflib_filter_info_t info = arg;
1457 struct grouptask *gtask = info->ifi_task;
1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1462 int i, cidx, result;
1464 bool intr_enable, intr_legacy;
1467 return (FILTER_STRAY);
1469 DBG_COUNTER_INC(fast_intrs);
1470 if (info->ifi_filter != NULL) {
1471 result = info->ifi_filter(info->ifi_filter_arg);
1472 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1477 sc = ctx->ifc_softc;
1478 intr_enable = false;
1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1480 MPASS(rxq->ifr_ntxqirq);
1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1482 txqid = rxq->ifr_txqid[i];
1483 txq = &ctx->ifc_txqs[txqid];
1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1485 BUS_DMASYNC_POSTREAD);
1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1493 GROUPTASK_ENQUEUE(&txq->ift_task);
1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1496 cidx = rxq->ifr_cq_cidx;
1498 cidx = rxq->ifr_fl[0].ifl_cidx;
1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1500 GROUPTASK_ENQUEUE(gtask);
1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1506 DBG_COUNTER_INC(rx_intr_enables);
1509 IFDI_INTR_ENABLE(ctx);
1510 return (FILTER_HANDLED);
1515 iflib_fast_intr_ctx(void *arg)
1517 iflib_filter_info_t info = arg;
1518 struct grouptask *gtask = info->ifi_task;
1522 return (FILTER_STRAY);
1524 DBG_COUNTER_INC(fast_intrs);
1525 if (info->ifi_filter != NULL) {
1526 result = info->ifi_filter(info->ifi_filter_arg);
1527 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1531 GROUPTASK_ENQUEUE(gtask);
1532 return (FILTER_HANDLED);
1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1537 driver_filter_t filter, driver_intr_t handler, void *arg,
1541 struct resource *res;
1543 device_t dev = ctx->ifc_dev;
1546 if (ctx->ifc_flags & IFC_LEGACY)
1547 flags |= RF_SHAREABLE;
1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1559 filter, handler, arg, &tag);
1562 "failed to setup interrupt for rid %d, name %s: %d\n",
1563 rid, name ? name : "unknown", rc);
1566 bus_describe_intr(dev, res, tag, "%s", name);
1573 /*********************************************************************
1575 * Allocate DMA resources for TX buffers as well as memory for the TX
1576 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1577 * iflib_sw_tx_desc_array structure, storing all the information that
1578 * is needed to transmit a packet on the wire. This is called only
1579 * once at attach, setup is done every reset.
1581 **********************************************************************/
1583 iflib_txsd_alloc(iflib_txq_t txq)
1585 if_ctx_t ctx = txq->ift_ctx;
1586 if_shared_ctx_t sctx = ctx->ifc_sctx;
1587 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1588 device_t dev = ctx->ifc_dev;
1589 bus_size_t tsomaxsize;
1590 int err, nsegments, ntsosegments;
1593 nsegments = scctx->isc_tx_nsegments;
1594 ntsosegments = scctx->isc_tx_tso_segments_max;
1595 tsomaxsize = scctx->isc_tx_tso_size_max;
1596 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1597 tsomaxsize += sizeof(struct ether_vlan_header);
1598 MPASS(scctx->isc_ntxd[0] > 0);
1599 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1600 MPASS(nsegments > 0);
1601 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1602 MPASS(ntsosegments > 0);
1603 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1607 * Set up DMA tags for TX buffers.
1609 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1610 1, 0, /* alignment, bounds */
1611 BUS_SPACE_MAXADDR, /* lowaddr */
1612 BUS_SPACE_MAXADDR, /* highaddr */
1613 NULL, NULL, /* filter, filterarg */
1614 sctx->isc_tx_maxsize, /* maxsize */
1615 nsegments, /* nsegments */
1616 sctx->isc_tx_maxsegsize, /* maxsegsize */
1618 NULL, /* lockfunc */
1619 NULL, /* lockfuncarg */
1620 &txq->ift_buf_tag))) {
1621 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1622 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1623 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1626 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1627 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1628 1, 0, /* alignment, bounds */
1629 BUS_SPACE_MAXADDR, /* lowaddr */
1630 BUS_SPACE_MAXADDR, /* highaddr */
1631 NULL, NULL, /* filter, filterarg */
1632 tsomaxsize, /* maxsize */
1633 ntsosegments, /* nsegments */
1634 sctx->isc_tso_maxsegsize,/* maxsegsize */
1636 NULL, /* lockfunc */
1637 NULL, /* lockfuncarg */
1638 &txq->ift_tso_buf_tag))) {
1639 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1644 /* Allocate memory for the TX mbuf map. */
1645 if (!(txq->ift_sds.ifsd_m =
1646 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1647 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1648 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1654 * Create the DMA maps for TX buffers.
1656 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1657 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1658 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1660 "Unable to allocate TX buffer DMA map memory\n");
1664 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1665 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1666 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1668 "Unable to allocate TSO TX buffer map memory\n");
1672 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1673 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1674 &txq->ift_sds.ifsd_map[i]);
1676 device_printf(dev, "Unable to create TX DMA map\n");
1681 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1682 &txq->ift_sds.ifsd_tso_map[i]);
1684 device_printf(dev, "Unable to create TSO TX DMA map\n");
1690 /* We free all, it handles case where we are in the middle */
1691 iflib_tx_structures_free(ctx);
1696 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1701 if (txq->ift_sds.ifsd_map != NULL)
1702 map = txq->ift_sds.ifsd_map[i];
1704 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1705 bus_dmamap_unload(txq->ift_buf_tag, map);
1706 bus_dmamap_destroy(txq->ift_buf_tag, map);
1707 txq->ift_sds.ifsd_map[i] = NULL;
1711 if (txq->ift_sds.ifsd_tso_map != NULL)
1712 map = txq->ift_sds.ifsd_tso_map[i];
1714 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1715 BUS_DMASYNC_POSTWRITE);
1716 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1717 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1718 txq->ift_sds.ifsd_tso_map[i] = NULL;
1723 iflib_txq_destroy(iflib_txq_t txq)
1725 if_ctx_t ctx = txq->ift_ctx;
1727 for (int i = 0; i < txq->ift_size; i++)
1728 iflib_txsd_destroy(ctx, txq, i);
1729 if (txq->ift_sds.ifsd_map != NULL) {
1730 free(txq->ift_sds.ifsd_map, M_IFLIB);
1731 txq->ift_sds.ifsd_map = NULL;
1733 if (txq->ift_sds.ifsd_tso_map != NULL) {
1734 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1735 txq->ift_sds.ifsd_tso_map = NULL;
1737 if (txq->ift_sds.ifsd_m != NULL) {
1738 free(txq->ift_sds.ifsd_m, M_IFLIB);
1739 txq->ift_sds.ifsd_m = NULL;
1741 if (txq->ift_buf_tag != NULL) {
1742 bus_dma_tag_destroy(txq->ift_buf_tag);
1743 txq->ift_buf_tag = NULL;
1745 if (txq->ift_tso_buf_tag != NULL) {
1746 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1747 txq->ift_tso_buf_tag = NULL;
1752 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1756 mp = &txq->ift_sds.ifsd_m[i];
1760 if (txq->ift_sds.ifsd_map != NULL) {
1761 bus_dmamap_sync(txq->ift_buf_tag,
1762 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1763 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1765 if (txq->ift_sds.ifsd_tso_map != NULL) {
1766 bus_dmamap_sync(txq->ift_tso_buf_tag,
1767 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1768 bus_dmamap_unload(txq->ift_tso_buf_tag,
1769 txq->ift_sds.ifsd_tso_map[i]);
1772 DBG_COUNTER_INC(tx_frees);
1777 iflib_txq_setup(iflib_txq_t txq)
1779 if_ctx_t ctx = txq->ift_ctx;
1780 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1781 if_shared_ctx_t sctx = ctx->ifc_sctx;
1782 iflib_dma_info_t di;
1785 /* Set number of descriptors available */
1786 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1787 /* XXX make configurable */
1788 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1791 txq->ift_cidx_processed = 0;
1792 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1793 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1795 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1796 bzero((void *)di->idi_vaddr, di->idi_size);
1798 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1799 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1800 bus_dmamap_sync(di->idi_tag, di->idi_map,
1801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1805 /*********************************************************************
1807 * Allocate DMA resources for RX buffers as well as memory for the RX
1808 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1809 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1810 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1811 * Since we use use one entry in iflib_sw_rx_desc_array per received
1812 * packet, the maximum number of entries we'll need is equal to the
1813 * number of hardware receive descriptors that we've allocated.
1815 **********************************************************************/
1817 iflib_rxsd_alloc(iflib_rxq_t rxq)
1819 if_ctx_t ctx = rxq->ifr_ctx;
1820 if_shared_ctx_t sctx = ctx->ifc_sctx;
1821 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1822 device_t dev = ctx->ifc_dev;
1826 MPASS(scctx->isc_nrxd[0] > 0);
1827 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1830 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1831 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1832 /* Set up DMA tag for RX buffers. */
1833 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1834 1, 0, /* alignment, bounds */
1835 BUS_SPACE_MAXADDR, /* lowaddr */
1836 BUS_SPACE_MAXADDR, /* highaddr */
1837 NULL, NULL, /* filter, filterarg */
1838 sctx->isc_rx_maxsize, /* maxsize */
1839 sctx->isc_rx_nsegments, /* nsegments */
1840 sctx->isc_rx_maxsegsize, /* maxsegsize */
1842 NULL, /* lockfunc */
1847 "Unable to allocate RX DMA tag: %d\n", err);
1851 /* Allocate memory for the RX mbuf map. */
1852 if (!(fl->ifl_sds.ifsd_m =
1853 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1854 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1856 "Unable to allocate RX mbuf map memory\n");
1861 /* Allocate memory for the direct RX cluster pointer map. */
1862 if (!(fl->ifl_sds.ifsd_cl =
1863 (caddr_t *) malloc(sizeof(caddr_t) *
1864 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1866 "Unable to allocate RX cluster map memory\n");
1871 /* Allocate memory for the RX cluster bus address map. */
1872 if (!(fl->ifl_sds.ifsd_ba =
1873 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1874 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1876 "Unable to allocate RX bus address map memory\n");
1882 * Create the DMA maps for RX buffers.
1884 if (!(fl->ifl_sds.ifsd_map =
1885 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1887 "Unable to allocate RX buffer DMA map memory\n");
1891 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1892 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1893 &fl->ifl_sds.ifsd_map[i]);
1895 device_printf(dev, "Unable to create RX buffer DMA map\n");
1903 iflib_rx_structures_free(ctx);
1909 * Internal service routines
1912 struct rxq_refill_cb_arg {
1914 bus_dma_segment_t seg;
1919 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1921 struct rxq_refill_cb_arg *cb_arg = arg;
1923 cb_arg->error = error;
1924 cb_arg->seg = segs[0];
1925 cb_arg->nseg = nseg;
1929 * _iflib_fl_refill - refill an rxq free-buffer list
1930 * @ctx: the iflib context
1931 * @fl: the free list to refill
1932 * @count: the number of new buffers to allocate
1934 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1935 * The caller must assure that @count does not exceed the queue's capacity.
1938 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1940 struct if_rxd_update iru;
1941 struct rxq_refill_cb_arg cb_arg;
1945 bus_dmamap_t *sd_map;
1946 bus_addr_t bus_addr, *sd_ba;
1947 int err, frag_idx, i, idx, n, pidx;
1950 sd_m = fl->ifl_sds.ifsd_m;
1951 sd_map = fl->ifl_sds.ifsd_map;
1952 sd_cl = fl->ifl_sds.ifsd_cl;
1953 sd_ba = fl->ifl_sds.ifsd_ba;
1954 pidx = fl->ifl_pidx;
1956 frag_idx = fl->ifl_fragidx;
1957 credits = fl->ifl_credits;
1962 MPASS(credits + n <= fl->ifl_size);
1964 if (pidx < fl->ifl_cidx)
1965 MPASS(pidx + n <= fl->ifl_cidx);
1966 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1967 MPASS(fl->ifl_gen == 0);
1968 if (pidx > fl->ifl_cidx)
1969 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1971 DBG_COUNTER_INC(fl_refills);
1973 DBG_COUNTER_INC(fl_refills_large);
1974 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1977 * We allocate an uninitialized mbuf + cluster, mbuf is
1978 * initialized after rx.
1980 * If the cluster is still set then we know a minimum sized packet was received
1982 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1985 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1986 MPASS(frag_idx >= 0);
1987 if ((cl = sd_cl[frag_idx]) == NULL) {
1988 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1992 MPASS(sd_map != NULL);
1993 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1994 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1996 if (err != 0 || cb_arg.error) {
2000 if (fl->ifl_zone == zone_pack)
2001 uma_zfree(fl->ifl_zone, cl);
2005 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2006 sd_cl[frag_idx] = cl;
2008 fl->ifl_cl_enqueued++;
2011 bus_addr = sd_ba[frag_idx];
2013 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2014 BUS_DMASYNC_PREREAD);
2016 if (sd_m[frag_idx] == NULL) {
2017 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2022 bit_set(fl->ifl_rx_bitmap, frag_idx);
2024 fl->ifl_m_enqueued++;
2027 DBG_COUNTER_INC(rx_allocs);
2028 fl->ifl_rxd_idxs[i] = frag_idx;
2029 fl->ifl_bus_addrs[i] = bus_addr;
2030 fl->ifl_vm_addrs[i] = cl;
2033 MPASS(credits <= fl->ifl_size);
2034 if (++idx == fl->ifl_size) {
2038 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2039 iru.iru_pidx = pidx;
2041 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2045 fl->ifl_credits = credits;
2050 iru.iru_pidx = pidx;
2052 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2054 fl->ifl_credits = credits;
2056 DBG_COUNTER_INC(rxd_flush);
2057 if (fl->ifl_pidx == 0)
2058 pidx = fl->ifl_size - 1;
2060 pidx = fl->ifl_pidx - 1;
2062 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2063 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2064 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2065 fl->ifl_fragidx = frag_idx;
2068 static __inline void
2069 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2071 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2072 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2074 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2077 MPASS(fl->ifl_credits <= fl->ifl_size);
2078 MPASS(reclaimable == delta);
2080 if (reclaimable > 0)
2081 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2085 iflib_in_detach(if_ctx_t ctx)
2090 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2096 iflib_fl_bufs_free(iflib_fl_t fl)
2098 iflib_dma_info_t idi = fl->ifl_ifdi;
2099 bus_dmamap_t sd_map;
2102 for (i = 0; i < fl->ifl_size; i++) {
2103 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2104 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2106 if (*sd_cl != NULL) {
2107 sd_map = fl->ifl_sds.ifsd_map[i];
2108 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2109 BUS_DMASYNC_POSTREAD);
2110 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2112 uma_zfree(fl->ifl_zone, *sd_cl);
2113 // XXX: Should this get moved out?
2114 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2115 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2116 if (*sd_m != NULL) {
2117 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2118 uma_zfree(zone_mbuf, *sd_m);
2121 MPASS(*sd_cl == NULL);
2122 MPASS(*sd_m == NULL);
2125 fl->ifl_m_dequeued++;
2126 fl->ifl_cl_dequeued++;
2132 for (i = 0; i < fl->ifl_size; i++) {
2133 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2134 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2138 * Reset free list values
2140 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2141 bzero(idi->idi_vaddr, idi->idi_size);
2144 /*********************************************************************
2146 * Initialize a free list and its buffers.
2148 **********************************************************************/
2150 iflib_fl_setup(iflib_fl_t fl)
2152 iflib_rxq_t rxq = fl->ifl_rxq;
2153 if_ctx_t ctx = rxq->ifr_ctx;
2155 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2157 ** Free current RX buffer structs and their mbufs
2159 iflib_fl_bufs_free(fl);
2160 /* Now replenish the mbufs */
2161 MPASS(fl->ifl_credits == 0);
2162 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2163 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2164 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2165 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2166 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2169 /* avoid pre-allocating zillions of clusters to an idle card
2170 * potentially speeding up attach
2172 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2173 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2174 if (min(128, fl->ifl_size) != fl->ifl_credits)
2180 MPASS(fl->ifl_ifdi != NULL);
2181 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2182 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2186 /*********************************************************************
2188 * Free receive ring data structures
2190 **********************************************************************/
2192 iflib_rx_sds_free(iflib_rxq_t rxq)
2197 if (rxq->ifr_fl != NULL) {
2198 for (i = 0; i < rxq->ifr_nfl; i++) {
2199 fl = &rxq->ifr_fl[i];
2200 if (fl->ifl_buf_tag != NULL) {
2201 if (fl->ifl_sds.ifsd_map != NULL) {
2202 for (j = 0; j < fl->ifl_size; j++) {
2203 if (fl->ifl_sds.ifsd_map[j] ==
2208 fl->ifl_sds.ifsd_map[j],
2209 BUS_DMASYNC_POSTREAD);
2212 fl->ifl_sds.ifsd_map[j]);
2215 bus_dma_tag_destroy(fl->ifl_buf_tag);
2216 fl->ifl_buf_tag = NULL;
2218 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2219 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2220 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2221 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2222 fl->ifl_sds.ifsd_m = NULL;
2223 fl->ifl_sds.ifsd_cl = NULL;
2224 fl->ifl_sds.ifsd_ba = NULL;
2225 fl->ifl_sds.ifsd_map = NULL;
2227 free(rxq->ifr_fl, M_IFLIB);
2229 rxq->ifr_cq_cidx = 0;
2237 iflib_timer(void *arg)
2239 iflib_txq_t txq = arg;
2240 if_ctx_t ctx = txq->ift_ctx;
2241 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2242 uint64_t this_tick = ticks;
2243 uint32_t reset_on = hz / 2;
2245 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2249 ** Check on the state of the TX queue(s), this
2250 ** can be done without the lock because its RO
2251 ** and the HUNG state will be static if set.
2253 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2254 txq->ift_last_timer_tick = this_tick;
2255 IFDI_TIMER(ctx, txq->ift_id);
2256 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2257 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2258 (sctx->isc_pause_frames == 0)))
2261 if (ifmp_ring_is_stalled(txq->ift_br))
2262 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2263 txq->ift_cleaned_prev = txq->ift_cleaned;
2266 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2267 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2269 /* handle any laggards */
2270 if (txq->ift_db_pending)
2271 GROUPTASK_ENQUEUE(&txq->ift_task);
2273 sctx->isc_pause_frames = 0;
2274 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2275 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2279 device_printf(ctx->ifc_dev,
2280 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2281 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2283 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2284 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2285 iflib_admin_intr_deferred(ctx);
2290 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2292 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2295 * XXX don't set the max_frame_size to larger
2296 * than the hardware can handle
2298 if (sctx->isc_max_frame_size <= MCLBYTES)
2299 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2301 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2305 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2308 return (ctx->ifc_rx_mbuf_sz);
2312 iflib_init_locked(if_ctx_t ctx)
2314 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2315 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2316 if_t ifp = ctx->ifc_ifp;
2320 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2322 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2323 IFDI_INTR_DISABLE(ctx);
2325 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2326 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2327 /* Set hardware offload abilities */
2328 if_clearhwassist(ifp);
2329 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2330 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2331 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2332 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2333 if (if_getcapenable(ifp) & IFCAP_TSO4)
2334 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2335 if (if_getcapenable(ifp) & IFCAP_TSO6)
2336 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2338 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2340 callout_stop(&txq->ift_timer);
2341 CALLOUT_UNLOCK(txq);
2342 iflib_netmap_txq_init(ctx, txq);
2346 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2347 * that drivers can use the value when setting up the hardware receive
2350 iflib_calc_rx_mbuf_sz(ctx);
2353 i = if_getdrvflags(ifp);
2356 MPASS(if_getdrvflags(ifp) == i);
2357 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2358 /* XXX this should really be done on a per-queue basis */
2359 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2360 MPASS(rxq->ifr_id == i);
2361 iflib_netmap_rxq_init(ctx, rxq);
2364 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2365 if (iflib_fl_setup(fl)) {
2366 device_printf(ctx->ifc_dev,
2367 "setting up free list %d failed - "
2368 "check cluster settings\n", j);
2374 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2375 IFDI_INTR_ENABLE(ctx);
2376 txq = ctx->ifc_txqs;
2377 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2378 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2379 txq->ift_timer.c_cpu);
2383 iflib_media_change(if_t ifp)
2385 if_ctx_t ctx = if_getsoftc(ifp);
2389 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2390 iflib_init_locked(ctx);
2396 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2398 if_ctx_t ctx = if_getsoftc(ifp);
2401 IFDI_UPDATE_ADMIN_STATUS(ctx);
2402 IFDI_MEDIA_STATUS(ctx, ifmr);
2407 iflib_stop(if_ctx_t ctx)
2409 iflib_txq_t txq = ctx->ifc_txqs;
2410 iflib_rxq_t rxq = ctx->ifc_rxqs;
2411 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2412 if_shared_ctx_t sctx = ctx->ifc_sctx;
2413 iflib_dma_info_t di;
2417 /* Tell the stack that the interface is no longer active */
2418 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2420 IFDI_INTR_DISABLE(ctx);
2425 iflib_debug_reset();
2426 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2427 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2428 /* make sure all transmitters have completed before proceeding XXX */
2431 callout_stop(&txq->ift_timer);
2432 CALLOUT_UNLOCK(txq);
2434 /* clean any enqueued buffers */
2435 iflib_ifmp_purge(txq);
2436 /* Free any existing tx buffers. */
2437 for (j = 0; j < txq->ift_size; j++) {
2438 iflib_txsd_free(ctx, txq, j);
2440 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2441 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2442 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2443 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2444 txq->ift_pullups = 0;
2445 ifmp_ring_reset_stats(txq->ift_br);
2446 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2447 bzero((void *)di->idi_vaddr, di->idi_size);
2449 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2450 /* make sure all transmitters have completed before proceeding XXX */
2452 rxq->ifr_cq_cidx = 0;
2453 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2454 bzero((void *)di->idi_vaddr, di->idi_size);
2455 /* also resets the free lists pidx/cidx */
2456 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2457 iflib_fl_bufs_free(fl);
2461 static inline caddr_t
2462 calc_next_rxd(iflib_fl_t fl, int cidx)
2466 caddr_t start, end, cur, next;
2468 nrxd = fl->ifl_size;
2469 size = fl->ifl_rxd_size;
2470 start = fl->ifl_ifdi->idi_vaddr;
2472 if (__predict_false(size == 0))
2474 cur = start + size*cidx;
2475 end = start + size*nrxd;
2476 next = CACHE_PTR_NEXT(cur);
2477 return (next < end ? next : start);
2481 prefetch_pkts(iflib_fl_t fl, int cidx)
2484 int nrxd = fl->ifl_size;
2488 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2489 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2490 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2491 next_rxd = calc_next_rxd(fl, cidx);
2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2494 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2495 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2496 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2498 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2499 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2500 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2503 static struct mbuf *
2504 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2505 int *pf_rv, if_rxd_info_t ri)
2511 int flid, cidx, len, next;
2514 flid = irf->irf_flid;
2515 cidx = irf->irf_idx;
2516 fl = &rxq->ifr_fl[flid];
2518 sd->ifsd_cidx = cidx;
2519 m = fl->ifl_sds.ifsd_m[cidx];
2520 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2523 fl->ifl_m_dequeued++;
2525 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2526 prefetch_pkts(fl, cidx);
2527 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2528 prefetch(&fl->ifl_sds.ifsd_map[next]);
2529 map = fl->ifl_sds.ifsd_map[cidx];
2530 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2532 /* not valid assert if bxe really does SGE from non-contiguous elements */
2533 MPASS(fl->ifl_cidx == cidx);
2534 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2536 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2537 payload = *sd->ifsd_cl;
2538 payload += ri->iri_pad;
2539 len = ri->iri_len - ri->iri_pad;
2540 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2541 len | PFIL_MEMPTR | PFIL_IN, NULL);
2546 * The filter ate it. Everything is recycled.
2551 case PFIL_REALLOCED:
2553 * The filter copied it. Everything is recycled.
2555 m = pfil_mem2mbuf(payload);
2560 * Filter said it was OK, so receive like
2563 fl->ifl_sds.ifsd_m[cidx] = NULL;
2569 fl->ifl_sds.ifsd_m[cidx] = NULL;
2574 bus_dmamap_unload(fl->ifl_buf_tag, map);
2575 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2576 if (__predict_false(fl->ifl_cidx == 0))
2578 bit_clear(fl->ifl_rx_bitmap, cidx);
2582 static struct mbuf *
2583 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2585 struct mbuf *m, *mh, *mt;
2587 int *pf_rv_ptr, flags, i, padlen;
2596 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2599 MPASS(*sd->ifsd_cl != NULL);
2602 * Exclude zero-length frags & frags from
2603 * packets the filter has consumed or dropped
2605 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2606 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2608 /* everything saved here */
2613 /* XXX we can save the cluster here, but not the mbuf */
2614 m_init(m, M_NOWAIT, MT_DATA, 0);
2619 flags = M_PKTHDR|M_EXT;
2621 padlen = ri->iri_pad;
2626 /* assuming padding is only on the first fragment */
2630 *sd->ifsd_cl = NULL;
2632 /* Can these two be made one ? */
2633 m_init(m, M_NOWAIT, MT_DATA, flags);
2634 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2636 * These must follow m_init and m_cljset
2638 m->m_data += padlen;
2639 ri->iri_len -= padlen;
2640 m->m_len = ri->iri_frags[i].irf_len;
2641 } while (++i < ri->iri_nfrags);
2647 * Process one software descriptor
2649 static struct mbuf *
2650 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2656 /* should I merge this back in now that the two paths are basically duplicated? */
2657 if (ri->iri_nfrags == 1 &&
2658 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2659 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2661 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2663 if (pf_rv == PFIL_PASS) {
2664 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2665 #ifndef __NO_STRICT_ALIGNMENT
2669 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2670 m->m_len = ri->iri_frags[0].irf_len;
2673 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2674 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2677 m->m_pkthdr.len = ri->iri_len;
2678 m->m_pkthdr.rcvif = ri->iri_ifp;
2679 m->m_flags |= ri->iri_flags;
2680 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2681 m->m_pkthdr.flowid = ri->iri_flowid;
2682 M_HASHTYPE_SET(m, ri->iri_rsstype);
2683 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2684 m->m_pkthdr.csum_data = ri->iri_csum_data;
2688 #if defined(INET6) || defined(INET)
2690 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2692 CURVNET_SET(lc->ifp->if_vnet);
2694 *v6 = VNET(ip6_forwarding);
2697 *v4 = VNET(ipforwarding);
2703 * Returns true if it's possible this packet could be LROed.
2704 * if it returns false, it is guaranteed that tcp_lro_rx()
2705 * would not return zero.
2708 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2710 struct ether_header *eh;
2713 eh = mtod(m, struct ether_header *);
2714 eh_type = ntohs(eh->ether_type);
2717 case ETHERTYPE_IPV6:
2718 return !v6_forwarding;
2722 return !v4_forwarding;
2730 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2736 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2739 if_ctx_t ctx = rxq->ifr_ctx;
2740 if_shared_ctx_t sctx = ctx->ifc_sctx;
2741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2744 struct if_rxd_info ri;
2745 int err, budget_left, rx_bytes, rx_pkts;
2748 bool v4_forwarding, v6_forwarding, lro_possible;
2751 * XXX early demux data packets so that if_input processing only handles
2752 * acks in interrupt context
2754 struct mbuf *m, *mh, *mt, *mf;
2756 lro_possible = v4_forwarding = v6_forwarding = false;
2760 rx_pkts = rx_bytes = 0;
2761 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2762 cidxp = &rxq->ifr_cq_cidx;
2764 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2765 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2766 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2767 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2768 DBG_COUNTER_INC(rx_unavail);
2772 /* pfil needs the vnet to be set */
2773 CURVNET_SET_QUIET(ifp->if_vnet);
2774 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2775 if (__predict_false(!CTX_ACTIVE(ctx))) {
2776 DBG_COUNTER_INC(rx_ctx_inactive);
2780 * Reset client set fields to their default values
2783 ri.iri_qsidx = rxq->ifr_id;
2784 ri.iri_cidx = *cidxp;
2786 ri.iri_frags = rxq->ifr_frags;
2787 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2792 rx_bytes += ri.iri_len;
2793 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2794 *cidxp = ri.iri_cidx;
2795 /* Update our consumer index */
2796 /* XXX NB: shurd - check if this is still safe */
2797 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2798 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2799 /* was this only a completion queue message? */
2800 if (__predict_false(ri.iri_nfrags == 0))
2803 MPASS(ri.iri_nfrags != 0);
2804 MPASS(ri.iri_len != 0);
2806 /* will advance the cidx on the corresponding free lists */
2807 m = iflib_rxd_pkt_get(rxq, &ri);
2810 if (avail == 0 && budget_left)
2811 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2813 if (__predict_false(m == NULL))
2816 /* imm_pkt: -- cxgb */
2825 /* make sure that we can refill faster than drain */
2826 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2827 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2829 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2831 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2833 while (mh != NULL) {
2836 m->m_nextpkt = NULL;
2837 #ifndef __NO_STRICT_ALIGNMENT
2838 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2841 rx_bytes += m->m_pkthdr.len;
2843 #if defined(INET6) || defined(INET)
2845 if (!lro_possible) {
2846 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2847 if (lro_possible && mf != NULL) {
2848 ifp->if_input(ifp, mf);
2849 DBG_COUNTER_INC(rx_if_input);
2853 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2854 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2855 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2861 ifp->if_input(ifp, m);
2862 DBG_COUNTER_INC(rx_if_input);
2873 ifp->if_input(ifp, mf);
2874 DBG_COUNTER_INC(rx_if_input);
2877 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2878 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2881 * Flush any outstanding LRO work
2883 #if defined(INET6) || defined(INET)
2884 tcp_lro_flush_all(&rxq->ifr_lc);
2888 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2891 ctx->ifc_flags |= IFC_DO_RESET;
2892 iflib_admin_intr_deferred(ctx);
2897 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2898 static inline qidx_t
2899 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2901 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2902 qidx_t minthresh = txq->ift_size / 8;
2903 if (in_use > 4*minthresh)
2904 return (notify_count);
2905 if (in_use > 2*minthresh)
2906 return (notify_count >> 1);
2907 if (in_use > minthresh)
2908 return (notify_count >> 3);
2912 static inline qidx_t
2913 txq_max_rs_deferred(iflib_txq_t txq)
2915 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2916 qidx_t minthresh = txq->ift_size / 8;
2917 if (txq->ift_in_use > 4*minthresh)
2918 return (notify_count);
2919 if (txq->ift_in_use > 2*minthresh)
2920 return (notify_count >> 1);
2921 if (txq->ift_in_use > minthresh)
2922 return (notify_count >> 2);
2926 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2927 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2929 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2930 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2931 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2933 /* forward compatibility for cxgb */
2934 #define FIRST_QSET(ctx) 0
2935 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2936 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2937 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2938 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2940 /* XXX we should be setting this to something other than zero */
2941 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2942 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2943 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2946 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2952 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2953 if (ring || txq->ift_db_pending >= max) {
2954 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2955 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2957 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2958 txq->ift_db_pending = txq->ift_npending = 0;
2966 print_pkt(if_pkt_info_t pi)
2968 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2969 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2970 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2971 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2972 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2973 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2977 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2978 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2979 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2980 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2983 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2985 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2986 struct ether_vlan_header *eh;
2990 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2991 M_WRITABLE(m) == 0) {
2992 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2996 DBG_COUNTER_INC(tx_frees);
3002 * Determine where frame payload starts.
3003 * Jump over vlan headers if already present,
3004 * helpful for QinQ too.
3006 if (__predict_false(m->m_len < sizeof(*eh))) {
3008 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3011 eh = mtod(m, struct ether_vlan_header *);
3012 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3013 pi->ipi_etype = ntohs(eh->evl_proto);
3014 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3016 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3017 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3020 switch (pi->ipi_etype) {
3025 struct ip *ip = NULL;
3026 struct tcphdr *th = NULL;
3029 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3030 if (__predict_false(m->m_len < minthlen)) {
3032 * if this code bloat is causing too much of a hit
3033 * move it to a separate function and mark it noinline
3035 if (m->m_len == pi->ipi_ehdrlen) {
3038 if (n->m_len >= sizeof(*ip)) {
3039 ip = (struct ip *)n->m_data;
3040 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3041 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3044 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3046 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3050 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3052 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3053 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3057 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3058 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3059 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3061 pi->ipi_ip_hlen = ip->ip_hl << 2;
3062 pi->ipi_ipproto = ip->ip_p;
3063 pi->ipi_flags |= IPI_TX_IPV4;
3065 /* TCP checksum offload may require TCP header length */
3066 if (IS_TX_OFFLOAD4(pi)) {
3067 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3068 if (__predict_false(th == NULL)) {
3070 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3072 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3074 pi->ipi_tcp_hflags = th->th_flags;
3075 pi->ipi_tcp_hlen = th->th_off << 2;
3076 pi->ipi_tcp_seq = th->th_seq;
3079 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3082 * TSO always requires hardware checksum offload.
3084 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3085 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3086 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3087 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3088 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3090 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3094 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3101 case ETHERTYPE_IPV6:
3103 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3105 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3107 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3109 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3112 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3114 /* XXX-BZ this will go badly in case of ext hdrs. */
3115 pi->ipi_ipproto = ip6->ip6_nxt;
3116 pi->ipi_flags |= IPI_TX_IPV6;
3118 /* TCP checksum offload may require TCP header length */
3119 if (IS_TX_OFFLOAD6(pi)) {
3120 if (pi->ipi_ipproto == IPPROTO_TCP) {
3121 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3123 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3126 pi->ipi_tcp_hflags = th->th_flags;
3127 pi->ipi_tcp_hlen = th->th_off << 2;
3128 pi->ipi_tcp_seq = th->th_seq;
3131 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3134 * TSO always requires hardware checksum offload.
3136 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3137 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3138 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3145 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3146 pi->ipi_ip_hlen = 0;
3155 * If dodgy hardware rejects the scatter gather chain we've handed it
3156 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3159 static __noinline struct mbuf *
3160 iflib_remove_mbuf(iflib_txq_t txq)
3163 struct mbuf *m, **ifsd_m;
3165 ifsd_m = txq->ift_sds.ifsd_m;
3166 ntxd = txq->ift_size;
3167 pidx = txq->ift_pidx & (ntxd - 1);
3168 ifsd_m = txq->ift_sds.ifsd_m;
3170 ifsd_m[pidx] = NULL;
3171 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3172 if (txq->ift_sds.ifsd_tso_map != NULL)
3173 bus_dmamap_unload(txq->ift_tso_buf_tag,
3174 txq->ift_sds.ifsd_tso_map[pidx]);
3176 txq->ift_dequeued++;
3181 static inline caddr_t
3182 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3186 caddr_t start, end, cur, next;
3188 ntxd = txq->ift_size;
3189 size = txq->ift_txd_size[qid];
3190 start = txq->ift_ifdi[qid].idi_vaddr;
3192 if (__predict_false(size == 0))
3194 cur = start + size*cidx;
3195 end = start + size*ntxd;
3196 next = CACHE_PTR_NEXT(cur);
3197 return (next < end ? next : start);
3201 * Pad an mbuf to ensure a minimum ethernet frame size.
3202 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3204 static __noinline int
3205 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3208 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3209 * and ARP message is the smallest common payload I can think of
3211 static char pad[18]; /* just zeros */
3213 struct mbuf *new_head;
3215 if (!M_WRITABLE(*m_head)) {
3216 new_head = m_dup(*m_head, M_NOWAIT);
3217 if (new_head == NULL) {
3219 device_printf(dev, "cannot pad short frame, m_dup() failed");
3220 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3221 DBG_COUNTER_INC(tx_frees);
3228 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3229 n > 0; n -= sizeof(pad))
3230 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3235 device_printf(dev, "cannot pad short frame\n");
3236 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3237 DBG_COUNTER_INC(tx_frees);
3245 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3248 if_shared_ctx_t sctx;
3249 if_softc_ctx_t scctx;
3250 bus_dma_tag_t buf_tag;
3251 bus_dma_segment_t *segs;
3252 struct mbuf *m_head, **ifsd_m;
3255 struct if_pkt_info pi;
3257 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3260 sctx = ctx->ifc_sctx;
3261 scctx = &ctx->ifc_softc_ctx;
3262 segs = txq->ift_segs;
3263 ntxd = txq->ift_size;
3268 * If we're doing TSO the next descriptor to clean may be quite far ahead
3270 cidx = txq->ift_cidx;
3271 pidx = txq->ift_pidx;
3272 if (ctx->ifc_flags & IFC_PREFETCH) {
3273 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3274 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3275 next_txd = calc_next_txd(txq, cidx, 0);
3279 /* prefetch the next cache line of mbuf pointers and flags */
3280 prefetch(&txq->ift_sds.ifsd_m[next]);
3281 prefetch(&txq->ift_sds.ifsd_map[next]);
3282 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3284 map = txq->ift_sds.ifsd_map[pidx];
3285 ifsd_m = txq->ift_sds.ifsd_m;
3287 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3288 buf_tag = txq->ift_tso_buf_tag;
3289 max_segs = scctx->isc_tx_tso_segments_max;
3290 map = txq->ift_sds.ifsd_tso_map[pidx];
3291 MPASS(buf_tag != NULL);
3292 MPASS(max_segs > 0);
3294 buf_tag = txq->ift_buf_tag;
3295 max_segs = scctx->isc_tx_nsegments;
3296 map = txq->ift_sds.ifsd_map[pidx];
3298 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3299 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3300 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3302 DBG_COUNTER_INC(encap_txd_encap_fail);
3309 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3311 pi.ipi_qsidx = txq->ift_id;
3312 pi.ipi_len = m_head->m_pkthdr.len;
3313 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3314 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3316 /* deliberate bitwise OR to make one condition */
3317 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3318 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3319 DBG_COUNTER_INC(encap_txd_encap_fail);
3326 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3329 if (__predict_false(err)) {
3332 /* try collapse once and defrag once */
3334 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3335 /* try defrag if collapsing fails */
3340 txq->ift_mbuf_defrag++;
3341 m_head = m_defrag(*m_headp, M_NOWAIT);
3344 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3345 * failed to map an mbuf that was run through m_defrag
3348 if (__predict_false(m_head == NULL || remap > 1))
3355 txq->ift_no_tx_dma_setup++;
3358 txq->ift_no_tx_dma_setup++;
3360 DBG_COUNTER_INC(tx_frees);
3364 txq->ift_map_failed++;
3365 DBG_COUNTER_INC(encap_load_mbuf_fail);
3366 DBG_COUNTER_INC(encap_txd_encap_fail);
3369 ifsd_m[pidx] = m_head;
3371 * XXX assumes a 1 to 1 relationship between segments and
3372 * descriptors - this does not hold true on all drivers, e.g.
3375 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3376 txq->ift_no_desc_avail++;
3377 bus_dmamap_unload(buf_tag, map);
3378 DBG_COUNTER_INC(encap_txq_avail_fail);
3379 DBG_COUNTER_INC(encap_txd_encap_fail);
3380 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3381 GROUPTASK_ENQUEUE(&txq->ift_task);
3385 * On Intel cards we can greatly reduce the number of TX interrupts
3386 * we see by only setting report status on every Nth descriptor.
3387 * However, this also means that the driver will need to keep track
3388 * of the descriptors that RS was set on to check them for the DD bit.
3390 txq->ift_rs_pending += nsegs + 1;
3391 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3392 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3393 pi.ipi_flags |= IPI_TX_INTR;
3394 txq->ift_rs_pending = 0;
3398 pi.ipi_nsegs = nsegs;
3400 MPASS(pidx >= 0 && pidx < txq->ift_size);
3404 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3405 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3406 DBG_COUNTER_INC(tx_encap);
3407 MPASS(pi.ipi_new_pidx < txq->ift_size);
3409 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3410 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3411 ndesc += txq->ift_size;
3415 * drivers can need as many as
3418 MPASS(ndesc <= pi.ipi_nsegs + 2);
3419 MPASS(pi.ipi_new_pidx != pidx);
3421 txq->ift_in_use += ndesc;
3424 * We update the last software descriptor again here because there may
3425 * be a sentinel and/or there may be more mbufs than segments
3427 txq->ift_pidx = pi.ipi_new_pidx;
3428 txq->ift_npending += pi.ipi_ndescs;
3430 *m_headp = m_head = iflib_remove_mbuf(txq);
3432 txq->ift_txd_encap_efbig++;
3441 * err can't possibly be non-zero here, so we don't neet to test it
3442 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3447 txq->ift_mbuf_defrag_failed++;
3448 txq->ift_map_failed++;
3450 DBG_COUNTER_INC(tx_frees);
3452 DBG_COUNTER_INC(encap_txd_encap_fail);
3457 iflib_tx_desc_free(iflib_txq_t txq, int n)
3459 uint32_t qsize, cidx, mask, gen;
3460 struct mbuf *m, **ifsd_m;
3463 cidx = txq->ift_cidx;
3465 qsize = txq->ift_size;
3467 ifsd_m = txq->ift_sds.ifsd_m;
3468 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3472 prefetch(ifsd_m[(cidx + 3) & mask]);
3473 prefetch(ifsd_m[(cidx + 4) & mask]);
3475 if ((m = ifsd_m[cidx]) != NULL) {
3476 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3477 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3478 bus_dmamap_sync(txq->ift_tso_buf_tag,
3479 txq->ift_sds.ifsd_tso_map[cidx],
3480 BUS_DMASYNC_POSTWRITE);
3481 bus_dmamap_unload(txq->ift_tso_buf_tag,
3482 txq->ift_sds.ifsd_tso_map[cidx]);
3484 bus_dmamap_sync(txq->ift_buf_tag,
3485 txq->ift_sds.ifsd_map[cidx],
3486 BUS_DMASYNC_POSTWRITE);
3487 bus_dmamap_unload(txq->ift_buf_tag,
3488 txq->ift_sds.ifsd_map[cidx]);
3490 /* XXX we don't support any drivers that batch packets yet */
3491 MPASS(m->m_nextpkt == NULL);
3493 ifsd_m[cidx] = NULL;
3495 txq->ift_dequeued++;
3497 DBG_COUNTER_INC(tx_frees);
3499 if (__predict_false(++cidx == qsize)) {
3504 txq->ift_cidx = cidx;
3509 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3512 if_ctx_t ctx = txq->ift_ctx;
3514 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3515 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3518 * Need a rate-limiting check so that this isn't called every time
3520 iflib_tx_credits_update(ctx, txq);
3521 reclaim = DESC_RECLAIMABLE(txq);
3523 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3525 if (iflib_verbose_debug) {
3526 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3527 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3534 iflib_tx_desc_free(txq, reclaim);
3535 txq->ift_cleaned += reclaim;
3536 txq->ift_in_use -= reclaim;
3541 static struct mbuf **
3542 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3545 struct mbuf **items;
3548 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3549 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3551 prefetch(items[(cidx + offset) & (size-1)]);
3552 if (remaining > 1) {
3553 prefetch2cachelines(&items[next]);
3554 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3555 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3556 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3558 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3562 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3565 ifmp_ring_check_drainage(txq->ift_br, budget);
3569 iflib_txq_can_drain(struct ifmp_ring *r)
3571 iflib_txq_t txq = r->cookie;
3572 if_ctx_t ctx = txq->ift_ctx;
3574 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3576 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3577 BUS_DMASYNC_POSTREAD);
3578 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3583 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3585 iflib_txq_t txq = r->cookie;
3586 if_ctx_t ctx = txq->ift_ctx;
3587 if_t ifp = ctx->ifc_ifp;
3588 struct mbuf **mp, *m;
3589 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3590 int reclaimed, err, in_use_prev, desc_used;
3591 bool do_prefetch, ring, rang;
3593 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3594 !LINK_ACTIVE(ctx))) {
3595 DBG_COUNTER_INC(txq_drain_notready);
3598 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3599 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3600 avail = IDXDIFF(pidx, cidx, r->size);
3601 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3602 DBG_COUNTER_INC(txq_drain_flushing);
3603 for (i = 0; i < avail; i++) {
3604 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3605 m_free(r->items[(cidx + i) & (r->size-1)]);
3606 r->items[(cidx + i) & (r->size-1)] = NULL;
3611 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3612 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3614 callout_stop(&txq->ift_timer);
3615 CALLOUT_UNLOCK(txq);
3616 DBG_COUNTER_INC(txq_drain_oactive);
3620 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3621 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3622 count = MIN(avail, TX_BATCH_SIZE);
3624 if (iflib_verbose_debug)
3625 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3626 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3628 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3629 avail = TXQ_AVAIL(txq);
3631 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3632 int rem = do_prefetch ? count - i : 0;
3634 mp = _ring_peek_one(r, cidx, i, rem);
3635 MPASS(mp != NULL && *mp != NULL);
3636 if (__predict_false(*mp == (struct mbuf *)txq)) {
3641 in_use_prev = txq->ift_in_use;
3642 err = iflib_encap(txq, mp);
3643 if (__predict_false(err)) {
3644 /* no room - bail out */
3648 /* we can't send this packet - skip it */
3654 DBG_COUNTER_INC(tx_sent);
3655 bytes_sent += m->m_pkthdr.len;
3656 mcast_sent += !!(m->m_flags & M_MCAST);
3657 avail = TXQ_AVAIL(txq);
3659 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3660 desc_used += (txq->ift_in_use - in_use_prev);
3661 ETHER_BPF_MTAP(ifp, m);
3662 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3664 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3667 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3668 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3669 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3670 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3671 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3673 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3675 if (iflib_verbose_debug)
3676 printf("consumed=%d\n", consumed);
3682 iflib_txq_drain_always(struct ifmp_ring *r)
3688 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3696 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3698 callout_stop(&txq->ift_timer);
3699 CALLOUT_UNLOCK(txq);
3701 avail = IDXDIFF(pidx, cidx, r->size);
3702 for (i = 0; i < avail; i++) {
3703 mp = _ring_peek_one(r, cidx, i, avail - i);
3704 if (__predict_false(*mp == (struct mbuf *)txq))
3707 DBG_COUNTER_INC(tx_frees);
3709 MPASS(ifmp_ring_is_stalled(r) == 0);
3714 iflib_ifmp_purge(iflib_txq_t txq)
3716 struct ifmp_ring *r;
3719 r->drain = iflib_txq_drain_free;
3720 r->can_drain = iflib_txq_drain_always;
3722 ifmp_ring_check_drainage(r, r->size);
3724 r->drain = iflib_txq_drain;
3725 r->can_drain = iflib_txq_can_drain;
3729 _task_fn_tx(void *context)
3731 iflib_txq_t txq = context;
3732 if_ctx_t ctx = txq->ift_ctx;
3733 #if defined(ALTQ) || defined(DEV_NETMAP)
3734 if_t ifp = ctx->ifc_ifp;
3736 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3738 #ifdef IFLIB_DIAGNOSTICS
3739 txq->ift_cpu_exec_count[curcpu]++;
3741 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3744 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3745 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3746 BUS_DMASYNC_POSTREAD);
3747 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3748 netmap_tx_irq(ifp, txq->ift_id);
3749 if (ctx->ifc_flags & IFC_LEGACY)
3750 IFDI_INTR_ENABLE(ctx);
3752 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3757 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3758 iflib_altq_if_start(ifp);
3760 if (txq->ift_db_pending)
3761 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3763 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3765 * When abdicating, we always need to check drainage, not just when we don't enqueue
3768 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3769 if (ctx->ifc_flags & IFC_LEGACY)
3770 IFDI_INTR_ENABLE(ctx);
3772 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3776 _task_fn_rx(void *context)
3778 iflib_rxq_t rxq = context;
3779 if_ctx_t ctx = rxq->ifr_ctx;
3783 #ifdef IFLIB_DIAGNOSTICS
3784 rxq->ifr_cpu_exec_count[curcpu]++;
3786 DBG_COUNTER_INC(task_fn_rxs);
3787 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3791 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3793 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3798 budget = ctx->ifc_sysctl_rx_budget;
3800 budget = 16; /* XXX */
3801 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3802 if (ctx->ifc_flags & IFC_LEGACY)
3803 IFDI_INTR_ENABLE(ctx);
3805 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3806 DBG_COUNTER_INC(rx_intr_enables);
3808 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3811 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3815 _task_fn_admin(void *context)
3817 if_ctx_t ctx = context;
3818 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3821 bool oactive, running, do_reset, do_watchdog, in_detach;
3822 uint32_t reset_on = hz / 2;
3825 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3826 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3827 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3828 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3829 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3830 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3833 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3839 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3841 callout_stop(&txq->ift_timer);
3842 CALLOUT_UNLOCK(txq);
3845 ctx->ifc_watchdog_events++;
3846 IFDI_WATCHDOG_RESET(ctx);
3848 IFDI_UPDATE_ADMIN_STATUS(ctx);
3849 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3852 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3853 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3855 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3857 IFDI_LINK_INTR_ENABLE(ctx);
3859 iflib_if_init_locked(ctx);
3862 if (LINK_ACTIVE(ctx) == 0)
3864 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3865 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3870 _task_fn_iov(void *context)
3872 if_ctx_t ctx = context;
3874 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3875 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3879 IFDI_VFLR_HANDLE(ctx);
3884 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3887 if_int_delay_info_t info;
3890 info = (if_int_delay_info_t)arg1;
3891 ctx = info->iidi_ctx;
3892 info->iidi_req = req;
3893 info->iidi_oidp = oidp;
3895 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3900 /*********************************************************************
3904 **********************************************************************/
3907 iflib_if_init_locked(if_ctx_t ctx)
3910 iflib_init_locked(ctx);
3915 iflib_if_init(void *arg)
3920 iflib_if_init_locked(ctx);
3925 iflib_if_transmit(if_t ifp, struct mbuf *m)
3927 if_ctx_t ctx = if_getsoftc(ifp);
3931 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3933 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3934 DBG_COUNTER_INC(tx_frees);
3939 MPASS(m->m_nextpkt == NULL);
3940 /* ALTQ-enabled interfaces always use queue 0. */
3942 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3943 qidx = QIDX(ctx, m);
3945 * XXX calculate buf_ring based on flowid (divvy up bits?)
3947 txq = &ctx->ifc_txqs[qidx];
3949 #ifdef DRIVER_BACKPRESSURE
3950 if (txq->ift_closed) {
3952 next = m->m_nextpkt;
3953 m->m_nextpkt = NULL;
3955 DBG_COUNTER_INC(tx_frees);
3967 next = next->m_nextpkt;
3968 } while (next != NULL);
3970 if (count > nitems(marr))
3971 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3972 /* XXX check nextpkt */
3974 /* XXX simplify for now */
3975 DBG_COUNTER_INC(tx_frees);
3978 for (next = m, i = 0; next != NULL; i++) {
3980 next = next->m_nextpkt;
3981 mp[i]->m_nextpkt = NULL;
3984 DBG_COUNTER_INC(tx_seen);
3985 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3988 GROUPTASK_ENQUEUE(&txq->ift_task);
3991 GROUPTASK_ENQUEUE(&txq->ift_task);
3992 /* support forthcoming later */
3993 #ifdef DRIVER_BACKPRESSURE
3994 txq->ift_closed = TRUE;
3996 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3998 DBG_COUNTER_INC(tx_frees);
4006 * The overall approach to integrating iflib with ALTQ is to continue to use
4007 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4008 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4009 * is redundant/unnecessary, but doing so minimizes the amount of
4010 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4011 * redundantly queueing to an intermediate mp_ring is swamped by the
4012 * performance limitations inherent in using ALTQ.
4014 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4015 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4016 * given interface. If ALTQ is enabled for an interface, then all
4017 * transmitted packets for that interface will be submitted to the ALTQ
4018 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4019 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4020 * update stats that the iflib machinery handles, and which is sensitve to
4021 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4022 * will be installed as the start routine for use by ALTQ facilities that
4023 * need to trigger queue drains on a scheduled basis.
4027 iflib_altq_if_start(if_t ifp)
4029 struct ifaltq *ifq = &ifp->if_snd;
4033 IFQ_DEQUEUE_NOLOCK(ifq, m);
4035 iflib_if_transmit(ifp, m);
4036 IFQ_DEQUEUE_NOLOCK(ifq, m);
4042 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4046 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4047 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4049 iflib_altq_if_start(ifp);
4051 err = iflib_if_transmit(ifp, m);
4058 iflib_if_qflush(if_t ifp)
4060 if_ctx_t ctx = if_getsoftc(ifp);
4061 iflib_txq_t txq = ctx->ifc_txqs;
4065 ctx->ifc_flags |= IFC_QFLUSH;
4067 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4068 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4069 iflib_txq_check_drain(txq, 0);
4071 ctx->ifc_flags &= ~IFC_QFLUSH;
4075 * When ALTQ is enabled, this will also take care of purging the
4082 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4083 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4084 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4085 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4088 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4090 if_ctx_t ctx = if_getsoftc(ifp);
4091 struct ifreq *ifr = (struct ifreq *)data;
4092 #if defined(INET) || defined(INET6)
4093 struct ifaddr *ifa = (struct ifaddr *)data;
4095 bool avoid_reset = false;
4096 int err = 0, reinit = 0, bits;
4101 if (ifa->ifa_addr->sa_family == AF_INET)
4105 if (ifa->ifa_addr->sa_family == AF_INET6)
4109 ** Calling init results in link renegotiation,
4110 ** so we avoid doing it when possible.
4113 if_setflagbits(ifp, IFF_UP,0);
4114 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4117 if (!(if_getflags(ifp) & IFF_NOARP))
4118 arp_ifinit(ifp, ifa);
4121 err = ether_ioctl(ifp, command, data);
4125 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4129 bits = if_getdrvflags(ifp);
4130 /* stop the driver and free any clusters before proceeding */
4133 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4135 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4136 ctx->ifc_flags |= IFC_MULTISEG;
4138 ctx->ifc_flags &= ~IFC_MULTISEG;
4140 err = if_setmtu(ifp, ifr->ifr_mtu);
4142 iflib_init_locked(ctx);
4144 if_setdrvflags(ifp, bits);
4150 if (if_getflags(ifp) & IFF_UP) {
4151 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4152 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4153 (IFF_PROMISC | IFF_ALLMULTI)) {
4154 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4158 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4161 ctx->ifc_if_flags = if_getflags(ifp);
4166 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4168 IFDI_INTR_DISABLE(ctx);
4169 IFDI_MULTI_SET(ctx);
4170 IFDI_INTR_ENABLE(ctx);
4176 IFDI_MEDIA_SET(ctx);
4181 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4185 struct ifi2creq i2c;
4187 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4190 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4194 if (i2c.len > sizeof(i2c.data)) {
4199 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4200 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4206 int mask, setmask, oldmask;
4208 oldmask = if_getcapenable(ifp);
4209 mask = ifr->ifr_reqcap ^ oldmask;
4210 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4213 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4215 setmask |= (mask & IFCAP_FLAGS);
4216 setmask |= (mask & IFCAP_WOL);
4219 * If any RX csum has changed, change all the ones that
4220 * are supported by the driver.
4222 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4223 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4224 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4228 * want to ensure that traffic has stopped before we change any of the flags
4232 bits = if_getdrvflags(ifp);
4233 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4236 if_togglecapenable(ifp, setmask);
4238 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4239 iflib_init_locked(ctx);
4241 if_setdrvflags(ifp, bits);
4248 case SIOCGPRIVATE_0:
4252 err = IFDI_PRIV_IOCTL(ctx, command, data);
4256 err = ether_ioctl(ifp, command, data);
4265 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4267 if_ctx_t ctx = if_getsoftc(ifp);
4269 return (IFDI_GET_COUNTER(ctx, cnt));
4272 /*********************************************************************
4274 * OTHER FUNCTIONS EXPORTED TO THE STACK
4276 **********************************************************************/
4279 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4281 if_ctx_t ctx = if_getsoftc(ifp);
4283 if ((void *)ctx != arg)
4286 if ((vtag == 0) || (vtag > 4095))
4290 IFDI_VLAN_REGISTER(ctx, vtag);
4291 /* Re-init to load the changes */
4292 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4293 iflib_if_init_locked(ctx);
4298 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4300 if_ctx_t ctx = if_getsoftc(ifp);
4302 if ((void *)ctx != arg)
4305 if ((vtag == 0) || (vtag > 4095))
4309 IFDI_VLAN_UNREGISTER(ctx, vtag);
4310 /* Re-init to load the changes */
4311 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4312 iflib_if_init_locked(ctx);
4317 iflib_led_func(void *arg, int onoff)
4322 IFDI_LED_FUNC(ctx, onoff);
4326 /*********************************************************************
4328 * BUS FUNCTION DEFINITIONS
4330 **********************************************************************/
4333 iflib_device_probe(device_t dev)
4335 pci_vendor_info_t *ent;
4337 uint16_t pci_vendor_id, pci_device_id;
4338 uint16_t pci_subvendor_id, pci_subdevice_id;
4339 uint16_t pci_rev_id;
4340 if_shared_ctx_t sctx;
4342 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4345 pci_vendor_id = pci_get_vendor(dev);
4346 pci_device_id = pci_get_device(dev);
4347 pci_subvendor_id = pci_get_subvendor(dev);
4348 pci_subdevice_id = pci_get_subdevice(dev);
4349 pci_rev_id = pci_get_revid(dev);
4350 if (sctx->isc_parse_devinfo != NULL)
4351 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4353 ent = sctx->isc_vendor_info;
4354 while (ent->pvi_vendor_id != 0) {
4355 if (pci_vendor_id != ent->pvi_vendor_id) {
4359 if ((pci_device_id == ent->pvi_device_id) &&
4360 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4361 (ent->pvi_subvendor_id == 0)) &&
4362 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4363 (ent->pvi_subdevice_id == 0)) &&
4364 ((pci_rev_id == ent->pvi_rev_id) ||
4365 (ent->pvi_rev_id == 0))) {
4367 device_set_desc_copy(dev, ent->pvi_name);
4368 /* this needs to be changed to zero if the bus probing code
4369 * ever stops re-probing on best match because the sctx
4370 * may have its values over written by register calls
4371 * in subsequent probes
4373 return (BUS_PROBE_DEFAULT);
4381 iflib_reset_qvalues(if_ctx_t ctx)
4383 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4384 if_shared_ctx_t sctx = ctx->ifc_sctx;
4385 device_t dev = ctx->ifc_dev;
4388 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4389 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4390 if (ctx->ifc_sysctl_ntxqs != 0)
4391 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4392 if (ctx->ifc_sysctl_nrxqs != 0)
4393 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4395 for (i = 0; i < sctx->isc_ntxqs; i++) {
4396 if (ctx->ifc_sysctl_ntxds[i] != 0)
4397 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4399 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4402 for (i = 0; i < sctx->isc_nrxqs; i++) {
4403 if (ctx->ifc_sysctl_nrxds[i] != 0)
4404 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4406 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4409 for (i = 0; i < sctx->isc_nrxqs; i++) {
4410 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4411 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4412 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4413 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4415 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4416 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4417 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4418 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4420 if (!powerof2(scctx->isc_nrxd[i])) {
4421 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4422 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4423 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4427 for (i = 0; i < sctx->isc_ntxqs; i++) {
4428 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4429 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4430 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4431 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4433 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4434 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4435 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4436 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4438 if (!powerof2(scctx->isc_ntxd[i])) {
4439 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4440 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4441 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4447 iflib_add_pfil(if_ctx_t ctx)
4449 struct pfil_head *pfil;
4450 struct pfil_head_args pa;
4454 pa.pa_version = PFIL_VERSION;
4455 pa.pa_flags = PFIL_IN;
4456 pa.pa_type = PFIL_TYPE_ETHERNET;
4457 pa.pa_headname = ctx->ifc_ifp->if_xname;
4458 pfil = pfil_head_register(&pa);
4460 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4466 iflib_rem_pfil(if_ctx_t ctx)
4468 struct pfil_head *pfil;
4472 rxq = ctx->ifc_rxqs;
4474 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4477 pfil_head_unregister(pfil);
4481 get_ctx_core_offset(if_ctx_t ctx)
4483 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4484 struct cpu_offset *op;
4486 uint16_t ret = ctx->ifc_sysctl_core_offset;
4488 if (ret != CORE_OFFSET_UNSPECIFIED)
4491 if (ctx->ifc_sysctl_separate_txrx)
4492 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4494 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4496 mtx_lock(&cpu_offset_mtx);
4497 SLIST_FOREACH(op, &cpu_offsets, entries) {
4498 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4501 MPASS(op->refcount < UINT_MAX);
4506 if (ret == CORE_OFFSET_UNSPECIFIED) {
4508 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4511 device_printf(ctx->ifc_dev,
4512 "allocation for cpu offset failed.\n");
4516 CPU_COPY(&ctx->ifc_cpus, &op->set);
4517 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4520 mtx_unlock(&cpu_offset_mtx);
4526 unref_ctx_core_offset(if_ctx_t ctx)
4528 struct cpu_offset *op, *top;
4530 mtx_lock(&cpu_offset_mtx);
4531 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4532 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4533 MPASS(op->refcount > 0);
4535 if (op->refcount == 0) {
4536 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4542 mtx_unlock(&cpu_offset_mtx);
4546 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4550 if_softc_ctx_t scctx;
4551 kobjop_desc_t kobj_desc;
4552 kobj_method_t *kobj_method;
4554 uint16_t main_rxq, main_txq;
4556 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4559 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4560 device_set_softc(dev, ctx);
4561 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4564 ctx->ifc_sctx = sctx;
4566 ctx->ifc_softc = sc;
4568 if ((err = iflib_register(ctx)) != 0) {
4569 device_printf(dev, "iflib_register failed %d\n", err);
4572 iflib_add_device_sysctl_pre(ctx);
4574 scctx = &ctx->ifc_softc_ctx;
4577 iflib_reset_qvalues(ctx);
4579 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4580 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4583 _iflib_pre_assert(scctx);
4584 ctx->ifc_txrx = *scctx->isc_txrx;
4586 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4587 ctx->ifc_mediap = scctx->isc_media;
4590 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4591 MPASS(scctx->isc_tx_csum_flags);
4594 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4595 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4597 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4598 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4599 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4600 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4602 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4603 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4605 /* XXX change for per-queue sizes */
4606 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4607 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4609 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4610 MAX_SINGLE_PACKET_FRACTION)
4611 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4612 MAX_SINGLE_PACKET_FRACTION);
4613 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4614 MAX_SINGLE_PACKET_FRACTION)
4615 scctx->isc_tx_tso_segments_max = max(1,
4616 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4618 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4619 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4621 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4624 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4627 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4628 * into account. In the worst case, each of these calls will
4629 * add another mbuf and, thus, the requirement for another DMA
4630 * segment. So for best performance, it doesn't make sense to
4631 * advertize a maximum of TSO segments that typically will
4632 * require defragmentation in iflib_encap().
4634 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4635 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4637 if (scctx->isc_rss_table_size == 0)
4638 scctx->isc_rss_table_size = 64;
4639 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4641 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4642 /* XXX format name */
4643 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4644 NULL, NULL, "admin");
4646 /* Set up cpu set. If it fails, use the set of all CPUs. */
4647 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4648 device_printf(dev, "Unable to fetch CPU list\n");
4649 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4651 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4654 ** Now set up MSI or MSI-X, should return us the number of supported
4655 ** vectors (will be 1 for a legacy interrupt and MSI).
4657 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4658 msix = scctx->isc_vectors;
4659 } else if (scctx->isc_msix_bar != 0)
4661 * The simple fact that isc_msix_bar is not 0 does not mean we
4662 * we have a good value there that is known to work.
4664 msix = iflib_msix_init(ctx);
4666 scctx->isc_vectors = 1;
4667 scctx->isc_ntxqsets = 1;
4668 scctx->isc_nrxqsets = 1;
4669 scctx->isc_intr = IFLIB_INTR_LEGACY;
4672 /* Get memory for the station queues */
4673 if ((err = iflib_queues_alloc(ctx))) {
4674 device_printf(dev, "Unable to allocate queue memory\n");
4675 goto fail_intr_free;
4678 if ((err = iflib_qset_structures_setup(ctx)))
4682 * Now that we know how many queues there are, get the core offset.
4684 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4687 * Group taskqueues aren't properly set up until SMP is started,
4688 * so we disable interrupts until we can handle them post
4691 * XXX: disabling interrupts doesn't actually work, at least for
4692 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4693 * we do null handling and depend on this not causing too large an
4696 IFDI_INTR_DISABLE(ctx);
4700 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4701 * aren't the default NULL implementation.
4703 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4704 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4706 if (kobj_method == &kobj_desc->deflt) {
4708 "MSI-X requires ifdi_rx_queue_intr_enable method");
4712 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4713 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4715 if (kobj_method == &kobj_desc->deflt) {
4717 "MSI-X requires ifdi_tx_queue_intr_enable method");
4723 * Assign the MSI-X vectors.
4724 * Note that the default NULL ifdi_msix_intr_assign method will
4727 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4729 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4735 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4739 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4740 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4745 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4747 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4748 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4753 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4754 * This must appear after the call to ether_ifattach() because
4755 * ether_ifattach() sets if_hdrlen to the default value.
4757 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4758 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4760 if ((err = iflib_netmap_attach(ctx))) {
4761 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4766 NETDUMP_SET(ctx->ifc_ifp, iflib);
4768 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4769 iflib_add_device_sysctl_post(ctx);
4770 iflib_add_pfil(ctx);
4771 ctx->ifc_flags |= IFC_INIT_DONE;
4777 ether_ifdetach(ctx->ifc_ifp);
4779 iflib_free_intr_mem(ctx);
4781 iflib_tx_structures_free(ctx);
4782 iflib_rx_structures_free(ctx);
4787 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4788 free(ctx->ifc_softc, M_IFLIB);
4794 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4795 struct iflib_cloneattach_ctx *clctx)
4800 if_softc_ctx_t scctx;
4806 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4807 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4808 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4809 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4810 ctx->ifc_flags |= IFC_PSEUDO;
4812 ctx->ifc_sctx = sctx;
4813 ctx->ifc_softc = sc;
4816 if ((err = iflib_register(ctx)) != 0) {
4817 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4820 iflib_add_device_sysctl_pre(ctx);
4822 scctx = &ctx->ifc_softc_ctx;
4825 iflib_reset_qvalues(ctx);
4827 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4828 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4831 if (sctx->isc_flags & IFLIB_GEN_MAC)
4832 ether_gen_addr(ifp, &ctx->ifc_mac);
4833 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4834 clctx->cc_params)) != 0) {
4835 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4838 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4839 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4840 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4843 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4844 MPASS(scctx->isc_tx_csum_flags);
4847 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4848 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4850 ifp->if_flags |= IFF_NOGROUP;
4851 if (sctx->isc_flags & IFLIB_PSEUDO) {
4852 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4854 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4855 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4861 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4862 * This must appear after the call to ether_ifattach() because
4863 * ether_ifattach() sets if_hdrlen to the default value.
4865 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4866 if_setifheaderlen(ifp,
4867 sizeof(struct ether_vlan_header));
4869 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4870 iflib_add_device_sysctl_post(ctx);
4871 ctx->ifc_flags |= IFC_INIT_DONE;
4874 _iflib_pre_assert(scctx);
4875 ctx->ifc_txrx = *scctx->isc_txrx;
4877 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4878 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4879 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4880 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4882 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4883 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4885 /* XXX change for per-queue sizes */
4886 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4887 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4889 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4890 MAX_SINGLE_PACKET_FRACTION)
4891 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4892 MAX_SINGLE_PACKET_FRACTION);
4893 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4894 MAX_SINGLE_PACKET_FRACTION)
4895 scctx->isc_tx_tso_segments_max = max(1,
4896 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4898 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4899 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4901 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4904 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4907 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4908 * into account. In the worst case, each of these calls will
4909 * add another mbuf and, thus, the requirement for another DMA
4910 * segment. So for best performance, it doesn't make sense to
4911 * advertize a maximum of TSO segments that typically will
4912 * require defragmentation in iflib_encap().
4914 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4915 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4917 if (scctx->isc_rss_table_size == 0)
4918 scctx->isc_rss_table_size = 64;
4919 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4921 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4922 /* XXX format name */
4923 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4924 NULL, NULL, "admin");
4926 /* XXX --- can support > 1 -- but keep it simple for now */
4927 scctx->isc_intr = IFLIB_INTR_LEGACY;
4929 /* Get memory for the station queues */
4930 if ((err = iflib_queues_alloc(ctx))) {
4931 device_printf(dev, "Unable to allocate queue memory\n");
4932 goto fail_iflib_detach;
4935 if ((err = iflib_qset_structures_setup(ctx))) {
4936 device_printf(dev, "qset structure setup failed %d\n", err);
4941 * XXX What if anything do we want to do about interrupts?
4943 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4944 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4945 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4950 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4951 * This must appear after the call to ether_ifattach() because
4952 * ether_ifattach() sets if_hdrlen to the default value.
4954 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4955 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4957 /* XXX handle more than one queue */
4958 for (i = 0; i < scctx->isc_nrxqsets; i++)
4959 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4963 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4964 iflib_add_device_sysctl_post(ctx);
4965 ctx->ifc_flags |= IFC_INIT_DONE;
4970 ether_ifdetach(ctx->ifc_ifp);
4972 iflib_tx_structures_free(ctx);
4973 iflib_rx_structures_free(ctx);
4979 free(ctx->ifc_softc, M_IFLIB);
4985 iflib_pseudo_deregister(if_ctx_t ctx)
4987 if_t ifp = ctx->ifc_ifp;
4991 struct taskqgroup *tqg;
4994 /* Unregister VLAN events */
4995 if (ctx->ifc_vlan_attach_event != NULL)
4996 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4997 if (ctx->ifc_vlan_detach_event != NULL)
4998 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5000 ether_ifdetach(ifp);
5001 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5002 CTX_LOCK_DESTROY(ctx);
5003 /* XXX drain any dependent tasks */
5004 tqg = qgroup_if_io_tqg;
5005 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5006 callout_drain(&txq->ift_timer);
5007 if (txq->ift_task.gt_uniq != NULL)
5008 taskqgroup_detach(tqg, &txq->ift_task);
5010 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5011 if (rxq->ifr_task.gt_uniq != NULL)
5012 taskqgroup_detach(tqg, &rxq->ifr_task);
5014 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5015 free(fl->ifl_rx_bitmap, M_IFLIB);
5017 tqg = qgroup_if_config_tqg;
5018 if (ctx->ifc_admin_task.gt_uniq != NULL)
5019 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5020 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5021 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5025 iflib_tx_structures_free(ctx);
5026 iflib_rx_structures_free(ctx);
5027 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5028 free(ctx->ifc_softc, M_IFLIB);
5034 iflib_device_attach(device_t dev)
5037 if_shared_ctx_t sctx;
5039 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5042 pci_enable_busmaster(dev);
5044 return (iflib_device_register(dev, NULL, sctx, &ctx));
5048 iflib_device_deregister(if_ctx_t ctx)
5050 if_t ifp = ctx->ifc_ifp;
5053 device_t dev = ctx->ifc_dev;
5055 struct taskqgroup *tqg;
5058 /* Make sure VLANS are not using driver */
5059 if (if_vlantrunkinuse(ifp)) {
5060 device_printf(dev, "Vlan in use, detach first\n");
5064 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5065 device_printf(dev, "SR-IOV in use; detach first.\n");
5071 ctx->ifc_flags |= IFC_IN_DETACH;
5078 /* Unregister VLAN events */
5079 if (ctx->ifc_vlan_attach_event != NULL)
5080 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5081 if (ctx->ifc_vlan_detach_event != NULL)
5082 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5084 iflib_netmap_detach(ifp);
5085 ether_ifdetach(ifp);
5086 iflib_rem_pfil(ctx);
5087 if (ctx->ifc_led_dev != NULL)
5088 led_destroy(ctx->ifc_led_dev);
5089 /* XXX drain any dependent tasks */
5090 tqg = qgroup_if_io_tqg;
5091 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5092 callout_drain(&txq->ift_timer);
5093 if (txq->ift_task.gt_uniq != NULL)
5094 taskqgroup_detach(tqg, &txq->ift_task);
5096 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5097 if (rxq->ifr_task.gt_uniq != NULL)
5098 taskqgroup_detach(tqg, &rxq->ifr_task);
5100 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5101 free(fl->ifl_rx_bitmap, M_IFLIB);
5103 tqg = qgroup_if_config_tqg;
5104 if (ctx->ifc_admin_task.gt_uniq != NULL)
5105 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5106 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5107 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5112 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5113 CTX_LOCK_DESTROY(ctx);
5114 device_set_softc(ctx->ifc_dev, NULL);
5115 iflib_free_intr_mem(ctx);
5117 bus_generic_detach(dev);
5120 iflib_tx_structures_free(ctx);
5121 iflib_rx_structures_free(ctx);
5122 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5123 free(ctx->ifc_softc, M_IFLIB);
5124 unref_ctx_core_offset(ctx);
5125 STATE_LOCK_DESTROY(ctx);
5131 iflib_free_intr_mem(if_ctx_t ctx)
5134 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5135 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5137 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5138 pci_release_msi(ctx->ifc_dev);
5140 if (ctx->ifc_msix_mem != NULL) {
5141 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5142 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5143 ctx->ifc_msix_mem = NULL;
5148 iflib_device_detach(device_t dev)
5150 if_ctx_t ctx = device_get_softc(dev);
5152 return (iflib_device_deregister(ctx));
5156 iflib_device_suspend(device_t dev)
5158 if_ctx_t ctx = device_get_softc(dev);
5164 return bus_generic_suspend(dev);
5167 iflib_device_shutdown(device_t dev)
5169 if_ctx_t ctx = device_get_softc(dev);
5175 return bus_generic_suspend(dev);
5180 iflib_device_resume(device_t dev)
5182 if_ctx_t ctx = device_get_softc(dev);
5183 iflib_txq_t txq = ctx->ifc_txqs;
5187 iflib_if_init_locked(ctx);
5189 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5190 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5192 return (bus_generic_resume(dev));
5196 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5199 if_ctx_t ctx = device_get_softc(dev);
5202 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5209 iflib_device_iov_uninit(device_t dev)
5211 if_ctx_t ctx = device_get_softc(dev);
5214 IFDI_IOV_UNINIT(ctx);
5219 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5222 if_ctx_t ctx = device_get_softc(dev);
5225 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5231 /*********************************************************************
5233 * MODULE FUNCTION DEFINITIONS
5235 **********************************************************************/
5238 * - Start a fast taskqueue thread for each core
5239 * - Start a taskqueue for control operations
5242 iflib_module_init(void)
5248 iflib_module_event_handler(module_t mod, int what, void *arg)
5254 if ((err = iflib_module_init()) != 0)
5260 return (EOPNOTSUPP);
5266 /*********************************************************************
5268 * PUBLIC FUNCTION DEFINITIONS
5269 * ordered as in iflib.h
5271 **********************************************************************/
5275 _iflib_assert(if_shared_ctx_t sctx)
5279 MPASS(sctx->isc_tx_maxsize);
5280 MPASS(sctx->isc_tx_maxsegsize);
5282 MPASS(sctx->isc_rx_maxsize);
5283 MPASS(sctx->isc_rx_nsegments);
5284 MPASS(sctx->isc_rx_maxsegsize);
5286 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5287 for (i = 0; i < sctx->isc_nrxqs; i++) {
5288 MPASS(sctx->isc_nrxd_min[i]);
5289 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5290 MPASS(sctx->isc_nrxd_max[i]);
5291 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5292 MPASS(sctx->isc_nrxd_default[i]);
5293 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5296 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5297 for (i = 0; i < sctx->isc_ntxqs; i++) {
5298 MPASS(sctx->isc_ntxd_min[i]);
5299 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5300 MPASS(sctx->isc_ntxd_max[i]);
5301 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5302 MPASS(sctx->isc_ntxd_default[i]);
5303 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5308 _iflib_pre_assert(if_softc_ctx_t scctx)
5311 MPASS(scctx->isc_txrx->ift_txd_encap);
5312 MPASS(scctx->isc_txrx->ift_txd_flush);
5313 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5314 MPASS(scctx->isc_txrx->ift_rxd_available);
5315 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5316 MPASS(scctx->isc_txrx->ift_rxd_refill);
5317 MPASS(scctx->isc_txrx->ift_rxd_flush);
5321 iflib_register(if_ctx_t ctx)
5323 if_shared_ctx_t sctx = ctx->ifc_sctx;
5324 driver_t *driver = sctx->isc_driver;
5325 device_t dev = ctx->ifc_dev;
5328 _iflib_assert(sctx);
5331 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5332 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5334 device_printf(dev, "can not allocate ifnet structure\n");
5339 * Initialize our context's device specific methods
5341 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5342 kobj_class_compile((kobj_class_t) driver);
5345 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5346 if_setsoftc(ifp, ctx);
5347 if_setdev(ifp, dev);
5348 if_setinitfn(ifp, iflib_if_init);
5349 if_setioctlfn(ifp, iflib_if_ioctl);
5351 if_setstartfn(ifp, iflib_altq_if_start);
5352 if_settransmitfn(ifp, iflib_altq_if_transmit);
5353 if_setsendqready(ifp);
5355 if_settransmitfn(ifp, iflib_if_transmit);
5357 if_setqflushfn(ifp, iflib_if_qflush);
5358 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5360 ctx->ifc_vlan_attach_event =
5361 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5362 EVENTHANDLER_PRI_FIRST);
5363 ctx->ifc_vlan_detach_event =
5364 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5365 EVENTHANDLER_PRI_FIRST);
5367 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5368 ctx->ifc_mediap = &ctx->ifc_media;
5369 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5370 iflib_media_change, iflib_media_status);
5376 iflib_queues_alloc(if_ctx_t ctx)
5378 if_shared_ctx_t sctx = ctx->ifc_sctx;
5379 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5380 device_t dev = ctx->ifc_dev;
5381 int nrxqsets = scctx->isc_nrxqsets;
5382 int ntxqsets = scctx->isc_ntxqsets;
5385 iflib_fl_t fl = NULL;
5386 int i, j, cpu, err, txconf, rxconf;
5387 iflib_dma_info_t ifdip;
5388 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5389 uint32_t *txqsizes = scctx->isc_txqsizes;
5390 uint8_t nrxqs = sctx->isc_nrxqs;
5391 uint8_t ntxqs = sctx->isc_ntxqs;
5392 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5396 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5397 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5399 /* Allocate the TX ring struct memory */
5400 if (!(ctx->ifc_txqs =
5401 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5402 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5403 device_printf(dev, "Unable to allocate TX ring memory\n");
5408 /* Now allocate the RX */
5409 if (!(ctx->ifc_rxqs =
5410 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5411 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5412 device_printf(dev, "Unable to allocate RX ring memory\n");
5417 txq = ctx->ifc_txqs;
5418 rxq = ctx->ifc_rxqs;
5421 * XXX handle allocation failure
5423 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5424 /* Set up some basics */
5426 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5427 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5429 "Unable to allocate TX DMA info memory\n");
5433 txq->ift_ifdi = ifdip;
5434 for (j = 0; j < ntxqs; j++, ifdip++) {
5435 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5437 "Unable to allocate TX descriptors\n");
5441 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5442 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5446 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5447 txq->ift_br_offset = 1;
5449 txq->ift_br_offset = 0;
5452 txq->ift_timer.c_cpu = cpu;
5454 if (iflib_txsd_alloc(txq)) {
5455 device_printf(dev, "Critical Failure setting up TX buffers\n");
5460 /* Initialize the TX lock */
5461 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5462 device_get_nameunit(dev), txq->ift_id);
5463 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5464 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5466 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5467 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5469 /* XXX free any allocated rings */
5470 device_printf(dev, "Unable to allocate buf_ring\n");
5475 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5476 /* Set up some basics */
5478 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5479 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5481 "Unable to allocate RX DMA info memory\n");
5486 rxq->ifr_ifdi = ifdip;
5487 /* XXX this needs to be changed if #rx queues != #tx queues */
5488 rxq->ifr_ntxqirq = 1;
5489 rxq->ifr_txqid[0] = i;
5490 for (j = 0; j < nrxqs; j++, ifdip++) {
5491 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5493 "Unable to allocate RX descriptors\n");
5497 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5501 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5502 rxq->ifr_fl_offset = 1;
5504 rxq->ifr_fl_offset = 0;
5506 rxq->ifr_nfl = nfree_lists;
5508 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5509 device_printf(dev, "Unable to allocate free list memory\n");
5514 for (j = 0; j < nfree_lists; j++) {
5515 fl[j].ifl_rxq = rxq;
5517 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5518 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5520 /* Allocate receive buffers for the ring */
5521 if (iflib_rxsd_alloc(rxq)) {
5523 "Critical Failure setting up receive buffers\n");
5528 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5529 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5534 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5535 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5536 for (i = 0; i < ntxqsets; i++) {
5537 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5539 for (j = 0; j < ntxqs; j++, di++) {
5540 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5541 paddrs[i*ntxqs + j] = di->idi_paddr;
5544 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5545 device_printf(ctx->ifc_dev,
5546 "Unable to allocate device TX queue\n");
5547 iflib_tx_structures_free(ctx);
5548 free(vaddrs, M_IFLIB);
5549 free(paddrs, M_IFLIB);
5552 free(vaddrs, M_IFLIB);
5553 free(paddrs, M_IFLIB);
5556 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5557 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5558 for (i = 0; i < nrxqsets; i++) {
5559 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5561 for (j = 0; j < nrxqs; j++, di++) {
5562 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5563 paddrs[i*nrxqs + j] = di->idi_paddr;
5566 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5567 device_printf(ctx->ifc_dev,
5568 "Unable to allocate device RX queue\n");
5569 iflib_tx_structures_free(ctx);
5570 free(vaddrs, M_IFLIB);
5571 free(paddrs, M_IFLIB);
5574 free(vaddrs, M_IFLIB);
5575 free(paddrs, M_IFLIB);
5579 /* XXX handle allocation failure changes */
5583 if (ctx->ifc_rxqs != NULL)
5584 free(ctx->ifc_rxqs, M_IFLIB);
5585 ctx->ifc_rxqs = NULL;
5586 if (ctx->ifc_txqs != NULL)
5587 free(ctx->ifc_txqs, M_IFLIB);
5588 ctx->ifc_txqs = NULL;
5594 iflib_tx_structures_setup(if_ctx_t ctx)
5596 iflib_txq_t txq = ctx->ifc_txqs;
5599 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5600 iflib_txq_setup(txq);
5606 iflib_tx_structures_free(if_ctx_t ctx)
5608 iflib_txq_t txq = ctx->ifc_txqs;
5609 if_shared_ctx_t sctx = ctx->ifc_sctx;
5612 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5613 iflib_txq_destroy(txq);
5614 for (j = 0; j < sctx->isc_ntxqs; j++)
5615 iflib_dma_free(&txq->ift_ifdi[j]);
5617 free(ctx->ifc_txqs, M_IFLIB);
5618 ctx->ifc_txqs = NULL;
5619 IFDI_QUEUES_FREE(ctx);
5622 /*********************************************************************
5624 * Initialize all receive rings.
5626 **********************************************************************/
5628 iflib_rx_structures_setup(if_ctx_t ctx)
5630 iflib_rxq_t rxq = ctx->ifc_rxqs;
5632 #if defined(INET6) || defined(INET)
5636 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5637 #if defined(INET6) || defined(INET)
5638 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5639 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5640 TCP_LRO_ENTRIES, min(1024,
5641 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5643 device_printf(ctx->ifc_dev,
5644 "LRO Initialization failed!\n");
5649 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5652 #if defined(INET6) || defined(INET)
5655 * Free LRO resources allocated so far, we will only handle
5656 * the rings that completed, the failing case will have
5657 * cleaned up for itself. 'q' failed, so its the terminus.
5659 rxq = ctx->ifc_rxqs;
5660 for (i = 0; i < q; ++i, rxq++) {
5661 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5662 tcp_lro_free(&rxq->ifr_lc);
5668 /*********************************************************************
5670 * Free all receive rings.
5672 **********************************************************************/
5674 iflib_rx_structures_free(if_ctx_t ctx)
5676 iflib_rxq_t rxq = ctx->ifc_rxqs;
5679 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5680 iflib_rx_sds_free(rxq);
5681 #if defined(INET6) || defined(INET)
5682 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5683 tcp_lro_free(&rxq->ifr_lc);
5686 free(ctx->ifc_rxqs, M_IFLIB);
5687 ctx->ifc_rxqs = NULL;
5691 iflib_qset_structures_setup(if_ctx_t ctx)
5696 * It is expected that the caller takes care of freeing queues if this
5699 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5700 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5704 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5705 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5711 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5712 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5715 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5720 find_nth(if_ctx_t ctx, int qid)
5723 int i, cpuid, eqid, count;
5725 CPU_COPY(&ctx->ifc_cpus, &cpus);
5726 count = CPU_COUNT(&cpus);
5728 /* clear up to the qid'th bit */
5729 for (i = 0; i < eqid; i++) {
5730 cpuid = CPU_FFS(&cpus);
5732 CPU_CLR(cpuid-1, &cpus);
5734 cpuid = CPU_FFS(&cpus);
5740 extern struct cpu_group *cpu_top; /* CPU topology */
5743 find_child_with_core(int cpu, struct cpu_group *grp)
5747 if (grp->cg_children == 0)
5750 MPASS(grp->cg_child);
5751 for (i = 0; i < grp->cg_children; i++) {
5752 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5760 * Find the nth "close" core to the specified core
5761 * "close" is defined as the deepest level that shares
5762 * at least an L2 cache. With threads, this will be
5763 * threads on the same core. If the shared cache is L3
5764 * or higher, simply returns the same core.
5767 find_close_core(int cpu, int core_offset)
5769 struct cpu_group *grp;
5778 while ((i = find_child_with_core(cpu, grp)) != -1) {
5779 /* If the child only has one cpu, don't descend */
5780 if (grp->cg_child[i].cg_count <= 1)
5782 grp = &grp->cg_child[i];
5785 /* If they don't share at least an L2 cache, use the same CPU */
5786 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5790 CPU_COPY(&grp->cg_mask, &cs);
5792 /* Add the selected CPU offset to core offset. */
5793 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5794 if (fcpu - 1 == cpu)
5796 CPU_CLR(fcpu - 1, &cs);
5802 CPU_COPY(&grp->cg_mask, &cs);
5803 for (i = core_offset % grp->cg_count; i > 0; i--) {
5804 MPASS(CPU_FFS(&cs));
5805 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5807 MPASS(CPU_FFS(&cs));
5808 return CPU_FFS(&cs) - 1;
5812 find_close_core(int cpu, int core_offset __unused)
5819 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5823 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5824 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5825 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5827 case IFLIB_INTR_RXTX:
5828 /* RX queues get the specified core */
5829 return qid / CPU_COUNT(&ctx->ifc_cpus);
5835 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5836 #define find_close_core(cpuid, tid) CPU_FIRST()
5837 #define find_nth(ctx, gid) CPU_FIRST()
5840 /* Just to avoid copy/paste */
5842 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5843 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5847 int co, cpuid, err, tid;
5850 co = ctx->ifc_sysctl_core_offset;
5851 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5852 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5853 cpuid = find_nth(ctx, qid + co);
5854 tid = get_core_offset(ctx, type, qid);
5856 device_printf(dev, "get_core_offset failed\n");
5857 return (EOPNOTSUPP);
5859 cpuid = find_close_core(cpuid, tid);
5860 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5863 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5867 if (cpuid > ctx->ifc_cpuid_highest)
5868 ctx->ifc_cpuid_highest = cpuid;
5874 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5875 iflib_intr_type_t type, driver_filter_t *filter,
5876 void *filter_arg, int qid, const char *name)
5879 struct grouptask *gtask;
5880 struct taskqgroup *tqg;
5881 iflib_filter_info_t info;
5884 driver_filter_t *intr_fast;
5887 info = &ctx->ifc_filter_info;
5891 /* XXX merge tx/rx for netmap? */
5893 q = &ctx->ifc_txqs[qid];
5894 info = &ctx->ifc_txqs[qid].ift_filter_info;
5895 gtask = &ctx->ifc_txqs[qid].ift_task;
5896 tqg = qgroup_if_io_tqg;
5898 intr_fast = iflib_fast_intr;
5899 GROUPTASK_INIT(gtask, 0, fn, q);
5900 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5903 q = &ctx->ifc_rxqs[qid];
5904 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5905 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5906 tqg = qgroup_if_io_tqg;
5908 intr_fast = iflib_fast_intr;
5909 GROUPTASK_INIT(gtask, 0, fn, q);
5911 case IFLIB_INTR_RXTX:
5912 q = &ctx->ifc_rxqs[qid];
5913 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5914 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5915 tqg = qgroup_if_io_tqg;
5917 intr_fast = iflib_fast_intr_rxtx;
5918 GROUPTASK_INIT(gtask, 0, fn, q);
5920 case IFLIB_INTR_ADMIN:
5923 info = &ctx->ifc_filter_info;
5924 gtask = &ctx->ifc_admin_task;
5925 tqg = qgroup_if_config_tqg;
5926 fn = _task_fn_admin;
5927 intr_fast = iflib_fast_intr_ctx;
5930 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5935 info->ifi_filter = filter;
5936 info->ifi_filter_arg = filter_arg;
5937 info->ifi_task = gtask;
5941 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5943 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5946 if (type == IFLIB_INTR_ADMIN)
5950 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5955 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
5962 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5964 struct grouptask *gtask;
5965 struct taskqgroup *tqg;
5972 q = &ctx->ifc_txqs[qid];
5973 gtask = &ctx->ifc_txqs[qid].ift_task;
5974 tqg = qgroup_if_io_tqg;
5978 q = &ctx->ifc_rxqs[qid];
5979 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5980 tqg = qgroup_if_io_tqg;
5983 case IFLIB_INTR_IOV:
5985 gtask = &ctx->ifc_vflr_task;
5986 tqg = qgroup_if_config_tqg;
5990 panic("unknown net intr type");
5992 GROUPTASK_INIT(gtask, 0, fn, q);
5994 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5997 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6000 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6005 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6009 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6012 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6013 rman_get_rid(irq->ii_res), irq->ii_res);
6017 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6019 iflib_txq_t txq = ctx->ifc_txqs;
6020 iflib_rxq_t rxq = ctx->ifc_rxqs;
6021 if_irq_t irq = &ctx->ifc_legacy_irq;
6022 iflib_filter_info_t info;
6024 struct grouptask *gtask;
6025 struct resource *res;
6026 struct taskqgroup *tqg;
6032 q = &ctx->ifc_rxqs[0];
6033 info = &rxq[0].ifr_filter_info;
6034 gtask = &rxq[0].ifr_task;
6035 tqg = qgroup_if_io_tqg;
6036 tqrid = irq->ii_rid = *rid;
6039 ctx->ifc_flags |= IFC_LEGACY;
6040 info->ifi_filter = filter;
6041 info->ifi_filter_arg = filter_arg;
6042 info->ifi_task = gtask;
6046 /* We allocate a single interrupt resource */
6047 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx,
6048 NULL, info, name)) != 0)
6050 GROUPTASK_INIT(gtask, 0, fn, q);
6052 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6054 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6055 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6061 iflib_led_create(if_ctx_t ctx)
6064 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6065 device_get_nameunit(ctx->ifc_dev));
6069 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6072 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6076 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6079 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6083 iflib_admin_intr_deferred(if_ctx_t ctx)
6086 struct grouptask *gtask;
6088 gtask = &ctx->ifc_admin_task;
6089 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6092 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6096 iflib_iov_intr_deferred(if_ctx_t ctx)
6099 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6103 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
6106 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6111 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6115 GROUPTASK_INIT(gtask, 0, fn, ctx);
6116 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6121 iflib_config_gtask_deinit(struct grouptask *gtask)
6124 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6128 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6130 if_t ifp = ctx->ifc_ifp;
6131 iflib_txq_t txq = ctx->ifc_txqs;
6133 if_setbaudrate(ifp, baudrate);
6134 if (baudrate >= IF_Gbps(10)) {
6136 ctx->ifc_flags |= IFC_PREFETCH;
6139 /* If link down, disable watchdog */
6140 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6141 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6142 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6144 ctx->ifc_link_state = link_state;
6145 if_link_state_change(ifp, link_state);
6149 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6153 int credits_pre = txq->ift_cidx_processed;
6156 if (ctx->isc_txd_credits_update == NULL)
6159 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6160 BUS_DMASYNC_POSTREAD);
6161 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6164 txq->ift_processed += credits;
6165 txq->ift_cidx_processed += credits;
6167 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6168 if (txq->ift_cidx_processed >= txq->ift_size)
6169 txq->ift_cidx_processed -= txq->ift_size;
6174 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6179 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6180 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6181 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6182 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6187 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6188 const char *description, if_int_delay_info_t info,
6189 int offset, int value)
6191 info->iidi_ctx = ctx;
6192 info->iidi_offset = offset;
6193 info->iidi_value = value;
6194 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6195 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6196 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6197 info, 0, iflib_sysctl_int_delay, "I", description);
6201 iflib_ctx_lock_get(if_ctx_t ctx)
6204 return (&ctx->ifc_ctx_sx);
6208 iflib_msix_init(if_ctx_t ctx)
6210 device_t dev = ctx->ifc_dev;
6211 if_shared_ctx_t sctx = ctx->ifc_sctx;
6212 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6213 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6214 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6216 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6217 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6220 device_printf(dev, "msix_init qsets capped at %d\n",
6221 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6223 /* Override by tuneable */
6224 if (scctx->isc_disable_msix)
6227 /* First try MSI-X */
6228 if ((msgs = pci_msix_count(dev)) == 0) {
6230 device_printf(dev, "MSI-X not supported or disabled\n");
6234 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6236 * bar == -1 => "trust me I know what I'm doing"
6237 * Some drivers are for hardware that is so shoddily
6238 * documented that no one knows which bars are which
6239 * so the developer has to map all bars. This hack
6240 * allows shoddy garbage to use MSI-X in this framework.
6243 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6244 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6245 if (ctx->ifc_msix_mem == NULL) {
6246 device_printf(dev, "Unable to map MSI-X table\n");
6251 admincnt = sctx->isc_admin_intrcnt;
6253 /* use only 1 qset in debug mode */
6254 queuemsgs = min(msgs - admincnt, 1);
6256 queuemsgs = msgs - admincnt;
6259 queues = imin(queuemsgs, rss_getnumbuckets());
6263 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6266 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6267 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6269 /* If we're doing RSS, clamp at the number of RSS buckets */
6270 if (queues > rss_getnumbuckets())
6271 queues = rss_getnumbuckets();
6273 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6274 rx_queues = iflib_num_rx_queues;
6278 if (rx_queues > scctx->isc_nrxqsets)
6279 rx_queues = scctx->isc_nrxqsets;
6282 * We want this to be all logical CPUs by default
6284 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6285 tx_queues = iflib_num_tx_queues;
6287 tx_queues = mp_ncpus;
6289 if (tx_queues > scctx->isc_ntxqsets)
6290 tx_queues = scctx->isc_ntxqsets;
6292 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6294 if (tx_queues != rx_queues)
6296 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6297 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6299 tx_queues = min(rx_queues, tx_queues);
6300 rx_queues = min(rx_queues, tx_queues);
6303 vectors = rx_queues + admincnt;
6304 if (msgs < vectors) {
6306 "insufficient number of MSI-X vectors "
6307 "(supported %d, need %d)\n", msgs, vectors);
6311 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6314 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6315 if (vectors != msgs) {
6317 "Unable to allocate sufficient MSI-X vectors "
6318 "(got %d, need %d)\n", vectors, msgs);
6319 pci_release_msi(dev);
6321 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6323 ctx->ifc_msix_mem = NULL;
6327 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6329 scctx->isc_vectors = vectors;
6330 scctx->isc_nrxqsets = rx_queues;
6331 scctx->isc_ntxqsets = tx_queues;
6332 scctx->isc_intr = IFLIB_INTR_MSIX;
6337 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6340 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6342 ctx->ifc_msix_mem = NULL;
6347 vectors = pci_msi_count(dev);
6348 scctx->isc_nrxqsets = 1;
6349 scctx->isc_ntxqsets = 1;
6350 scctx->isc_vectors = vectors;
6351 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6352 device_printf(dev,"Using an MSI interrupt\n");
6353 scctx->isc_intr = IFLIB_INTR_MSI;
6355 scctx->isc_vectors = 1;
6356 device_printf(dev,"Using a Legacy interrupt\n");
6357 scctx->isc_intr = IFLIB_INTR_LEGACY;
6363 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6366 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6369 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6371 const char *ring_state = "UNKNOWN";
6374 rc = sysctl_wire_old_buffer(req, 0);
6378 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6383 ring_state = ring_states[state[3]];
6385 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6386 state[0], state[1], state[2], ring_state);
6387 rc = sbuf_finish(sb);
6392 enum iflib_ndesc_handler {
6398 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6400 if_ctx_t ctx = (void *)arg1;
6401 enum iflib_ndesc_handler type = arg2;
6402 char buf[256] = {0};
6409 case IFLIB_NTXD_HANDLER:
6410 ndesc = ctx->ifc_sysctl_ntxds;
6412 nqs = ctx->ifc_sctx->isc_ntxqs;
6414 case IFLIB_NRXD_HANDLER:
6415 ndesc = ctx->ifc_sysctl_nrxds;
6417 nqs = ctx->ifc_sctx->isc_nrxqs;
6420 printf("%s: unhandled type\n", __func__);
6426 for (i=0; i<8; i++) {
6431 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6434 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6435 if (rc || req->newptr == NULL)
6438 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6439 i++, p = strsep(&next, " ,")) {
6440 ndesc[i] = strtoul(p, NULL, 10);
6446 #define NAME_BUFLEN 32
6448 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6450 device_t dev = iflib_get_dev(ctx);
6451 struct sysctl_oid_list *child, *oid_list;
6452 struct sysctl_ctx_list *ctx_list;
6453 struct sysctl_oid *node;
6455 ctx_list = device_get_sysctl_ctx(dev);
6456 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6457 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6458 CTLFLAG_RD, NULL, "IFLIB fields");
6459 oid_list = SYSCTL_CHILDREN(node);
6461 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6462 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6465 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6466 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6467 "# of txqs to use, 0 => use default #");
6468 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6469 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6470 "# of rxqs to use, 0 => use default #");
6471 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6472 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6473 "permit #txq != #rxq");
6474 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6475 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6476 "disable MSI-X (default 0)");
6477 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6478 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6479 "set the RX budget");
6480 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6481 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6482 "cause TX to abdicate instead of running to completion");
6483 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6484 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6485 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6486 "offset to start using cores at");
6487 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6488 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6489 "use separate cores for TX and RX");
6491 /* XXX change for per-queue sizes */
6492 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6493 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6494 mp_ndesc_handler, "A",
6495 "list of # of TX descriptors to use, 0 = use default #");
6496 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6497 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6498 mp_ndesc_handler, "A",
6499 "list of # of RX descriptors to use, 0 = use default #");
6503 iflib_add_device_sysctl_post(if_ctx_t ctx)
6505 if_shared_ctx_t sctx = ctx->ifc_sctx;
6506 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6507 device_t dev = iflib_get_dev(ctx);
6508 struct sysctl_oid_list *child;
6509 struct sysctl_ctx_list *ctx_list;
6514 char namebuf[NAME_BUFLEN];
6516 struct sysctl_oid *queue_node, *fl_node, *node;
6517 struct sysctl_oid_list *queue_list, *fl_list;
6518 ctx_list = device_get_sysctl_ctx(dev);
6520 node = ctx->ifc_sysctl_node;
6521 child = SYSCTL_CHILDREN(node);
6523 if (scctx->isc_ntxqsets > 100)
6525 else if (scctx->isc_ntxqsets > 10)
6529 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6530 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6531 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6532 CTLFLAG_RD, NULL, "Queue Name");
6533 queue_list = SYSCTL_CHILDREN(queue_node);
6535 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6537 &txq->ift_dequeued, "total mbufs freed");
6538 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6540 &txq->ift_enqueued, "total mbufs enqueued");
6542 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6544 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6545 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6547 &txq->ift_pullups, "# of times m_pullup was called");
6548 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6550 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6551 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6553 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6554 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6556 &txq->ift_map_failed, "# of times DMA map failed");
6557 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6559 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6560 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6562 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6563 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6565 &txq->ift_pidx, 1, "Producer Index");
6566 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6568 &txq->ift_cidx, 1, "Consumer Index");
6569 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6571 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6572 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6574 &txq->ift_in_use, 1, "descriptors in use");
6575 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6577 &txq->ift_processed, "descriptors procesed for clean");
6578 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6580 &txq->ift_cleaned, "total cleaned");
6581 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6582 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6583 0, mp_ring_state_handler, "A", "soft ring state");
6584 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6585 CTLFLAG_RD, &txq->ift_br->enqueues,
6586 "# of enqueues to the mp_ring for this queue");
6587 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6588 CTLFLAG_RD, &txq->ift_br->drops,
6589 "# of drops in the mp_ring for this queue");
6590 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6591 CTLFLAG_RD, &txq->ift_br->starts,
6592 "# of normal consumer starts in the mp_ring for this queue");
6593 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6594 CTLFLAG_RD, &txq->ift_br->stalls,
6595 "# of consumer stalls in the mp_ring for this queue");
6596 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6597 CTLFLAG_RD, &txq->ift_br->restarts,
6598 "# of consumer restarts in the mp_ring for this queue");
6599 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6600 CTLFLAG_RD, &txq->ift_br->abdications,
6601 "# of consumer abdications in the mp_ring for this queue");
6604 if (scctx->isc_nrxqsets > 100)
6606 else if (scctx->isc_nrxqsets > 10)
6610 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6611 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6612 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6613 CTLFLAG_RD, NULL, "Queue Name");
6614 queue_list = SYSCTL_CHILDREN(queue_node);
6615 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6616 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6618 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6621 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6622 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6623 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6624 CTLFLAG_RD, NULL, "freelist Name");
6625 fl_list = SYSCTL_CHILDREN(fl_node);
6626 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6628 &fl->ifl_pidx, 1, "Producer Index");
6629 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6631 &fl->ifl_cidx, 1, "Consumer Index");
6632 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6634 &fl->ifl_credits, 1, "credits available");
6636 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6638 &fl->ifl_m_enqueued, "mbufs allocated");
6639 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6641 &fl->ifl_m_dequeued, "mbufs freed");
6642 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6644 &fl->ifl_cl_enqueued, "clusters allocated");
6645 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6647 &fl->ifl_cl_dequeued, "clusters freed");
6656 iflib_request_reset(if_ctx_t ctx)
6660 ctx->ifc_flags |= IFC_DO_RESET;
6664 #ifndef __NO_STRICT_ALIGNMENT
6665 static struct mbuf *
6666 iflib_fixup_rx(struct mbuf *m)
6670 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6671 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6672 m->m_data += ETHER_HDR_LEN;
6675 MGETHDR(n, M_NOWAIT, MT_DATA);
6680 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6681 m->m_data += ETHER_HDR_LEN;
6682 m->m_len -= ETHER_HDR_LEN;
6683 n->m_len = ETHER_HDR_LEN;
6684 M_MOVE_PKTHDR(n, m);
6693 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6697 ctx = if_getsoftc(ifp);
6699 *nrxr = NRXQSETS(ctx);
6700 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6701 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6706 iflib_netdump_event(if_t ifp, enum netdump_ev event)
6709 if_softc_ctx_t scctx;
6714 ctx = if_getsoftc(ifp);
6715 scctx = &ctx->ifc_softc_ctx;
6719 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6720 rxq = &ctx->ifc_rxqs[i];
6721 for (j = 0; j < rxq->ifr_nfl; j++) {
6723 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6726 iflib_no_tx_batch = 1;
6734 iflib_netdump_transmit(if_t ifp, struct mbuf *m)
6740 ctx = if_getsoftc(ifp);
6741 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6745 txq = &ctx->ifc_txqs[0];
6746 error = iflib_encap(txq, &m);
6748 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6753 iflib_netdump_poll(if_t ifp, int count)
6756 if_softc_ctx_t scctx;
6760 ctx = if_getsoftc(ifp);
6761 scctx = &ctx->ifc_softc_ctx;
6763 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6767 txq = &ctx->ifc_txqs[0];
6768 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6770 for (i = 0; i < scctx->isc_nrxqsets; i++)
6771 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6774 #endif /* NETDUMP */