2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
63 #include <netinet/in.h>
64 #include <netinet/in_pcb.h>
65 #include <netinet/tcp_lro.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/if_ether.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
78 #include <dev/led/led.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pci_private.h>
83 #include <net/iflib.h>
87 #if defined(__i386__) || defined(__amd64__)
88 #include <sys/memdesc.h>
89 #include <machine/bus.h>
90 #include <machine/md_var.h>
91 #include <machine/specialreg.h>
92 #include <x86/include/busdma_impl.h>
93 #include <x86/iommu/busdma_dmar.h>
97 * enable accounting of every mbuf as it comes in to and goes out of iflib's software descriptor references
99 #define MEMORY_LOGGING 0
101 * Enable mbuf vectors for compressing long mbuf chains
106 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
107 * we prefetch needs to be determined by the time spent in m_free vis a vis
108 * the cost of a prefetch. This will of course vary based on the workload:
109 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
110 * is quite expensive, thus suggesting very little prefetch.
111 * - small packet forwarding which is just returning a single mbuf to
112 * UMA will typically be very fast vis a vis the cost of a memory
119 * - private structures
120 * - iflib private utility functions
122 * - vlan registry and other exported functions
123 * - iflib public core functions
127 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
130 typedef struct iflib_txq *iflib_txq_t;
132 typedef struct iflib_rxq *iflib_rxq_t;
134 typedef struct iflib_fl *iflib_fl_t;
138 typedef struct iflib_filter_info {
139 driver_filter_t *ifi_filter;
140 void *ifi_filter_arg;
141 struct grouptask *ifi_task;
142 struct iflib_ctx *ifi_ctx;
143 } *iflib_filter_info_t;
148 * Pointer to hardware driver's softc
155 if_shared_ctx_t ifc_sctx;
156 struct if_softc_ctx ifc_softc_ctx;
160 uint16_t ifc_nhwtxqs;
161 uint16_t ifc_nhwrxqs;
163 iflib_txq_t ifc_txqs;
164 iflib_rxq_t ifc_rxqs;
165 uint32_t ifc_if_flags;
167 uint32_t ifc_max_fl_buf_size;
172 int ifc_pause_frames;
173 int ifc_watchdog_events;
174 struct cdev *ifc_led_dev;
175 struct resource *ifc_msix_mem;
177 struct if_irq ifc_legacy_irq;
178 struct grouptask ifc_admin_task;
179 struct grouptask ifc_vflr_task;
180 struct iflib_filter_info ifc_filter_info;
181 struct ifmedia ifc_media;
183 struct sysctl_oid *ifc_sysctl_node;
184 uint16_t ifc_sysctl_ntxqs;
185 uint16_t ifc_sysctl_nrxqs;
186 uint16_t ifc_sysctl_qs_eq_override;
188 uint16_t ifc_sysctl_ntxds[8];
189 uint16_t ifc_sysctl_nrxds[8];
190 struct if_txrx ifc_txrx;
191 #define isc_txd_encap ifc_txrx.ift_txd_encap
192 #define isc_txd_flush ifc_txrx.ift_txd_flush
193 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
194 #define isc_rxd_available ifc_txrx.ift_rxd_available
195 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
196 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
197 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
198 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
200 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
201 eventhandler_tag ifc_vlan_attach_event;
202 eventhandler_tag ifc_vlan_detach_event;
203 uint8_t ifc_mac[ETHER_ADDR_LEN];
204 char ifc_mtx_name[16];
209 iflib_get_softc(if_ctx_t ctx)
212 return (ctx->ifc_softc);
216 iflib_get_dev(if_ctx_t ctx)
219 return (ctx->ifc_dev);
223 iflib_get_ifp(if_ctx_t ctx)
226 return (ctx->ifc_ifp);
230 iflib_get_media(if_ctx_t ctx)
233 return (&ctx->ifc_media);
237 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
240 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
244 iflib_get_softc_ctx(if_ctx_t ctx)
247 return (&ctx->ifc_softc_ctx);
251 iflib_get_sctx(if_ctx_t ctx)
254 return (ctx->ifc_sctx);
257 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
259 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
260 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
262 #define RX_SW_DESC_MAP_CREATED (1 << 0)
263 #define TX_SW_DESC_MAP_CREATED (1 << 1)
264 #define RX_SW_DESC_INUSE (1 << 3)
265 #define TX_SW_DESC_MAPPED (1 << 4)
267 typedef struct iflib_sw_rx_desc_array {
268 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
269 struct mbuf **ifsd_m; /* pkthdr mbufs */
270 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
272 } iflib_rxsd_array_t;
274 typedef struct iflib_sw_tx_desc_array {
275 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
276 struct mbuf **ifsd_m; /* pkthdr mbufs */
278 } iflib_txsd_array_t;
281 /* magic number that should be high enough for any hardware */
282 #define IFLIB_MAX_TX_SEGS 128
283 #define IFLIB_MAX_RX_SEGS 32
284 #define IFLIB_RX_COPY_THRESH 63
285 #define IFLIB_MAX_RX_REFRESH 32
286 #define IFLIB_QUEUE_IDLE 0
287 #define IFLIB_QUEUE_HUNG 1
288 #define IFLIB_QUEUE_WORKING 2
290 /* this should really scale with ring size - 32 is a fairly arbitrary value for this */
291 #define TX_BATCH_SIZE 16
293 #define IFLIB_RESTART_BUDGET 8
295 #define IFC_LEGACY 0x01
296 #define IFC_QFLUSH 0x02
297 #define IFC_MULTISEG 0x04
298 #define IFC_DMAR 0x08
299 #define IFC_SC_ALLOCATED 0x10
300 #define IFC_INIT_DONE 0x20
303 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
304 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
305 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
309 uint16_t ift_cidx_processed;
312 uint8_t ift_db_pending;
313 uint8_t ift_db_pending_queued;
314 uint8_t ift_npending;
315 uint8_t ift_br_offset;
317 uint64_t ift_processed;
318 uint64_t ift_cleaned;
320 uint64_t ift_enqueued;
321 uint64_t ift_dequeued;
323 uint64_t ift_no_tx_dma_setup;
324 uint64_t ift_no_desc_avail;
325 uint64_t ift_mbuf_defrag_failed;
326 uint64_t ift_mbuf_defrag;
327 uint64_t ift_map_failed;
328 uint64_t ift_txd_encap_efbig;
329 uint64_t ift_pullups;
332 struct mtx ift_db_mtx;
334 /* constant values */
336 struct ifmp_ring **ift_br;
337 struct grouptask ift_task;
340 struct callout ift_timer;
341 struct callout ift_db_check;
343 iflib_txsd_array_t ift_sds;
348 int ift_watchdog_time;
349 struct iflib_filter_info ift_filter_info;
350 bus_dma_tag_t ift_desc_tag;
351 bus_dma_tag_t ift_tso_desc_tag;
352 iflib_dma_info_t ift_ifdi;
353 #define MTX_NAME_LEN 16
354 char ift_mtx_name[MTX_NAME_LEN];
355 char ift_db_mtx_name[MTX_NAME_LEN];
356 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
357 #ifdef IFLIB_DIAGNOSTICS
358 uint64_t ift_cpu_exec_count[256];
360 } __aligned(CACHE_LINE_SIZE);
365 uint16_t ifl_credits;
368 uint64_t ifl_m_enqueued;
369 uint64_t ifl_m_dequeued;
370 uint64_t ifl_cl_enqueued;
371 uint64_t ifl_cl_dequeued;
377 uint16_t ifl_buf_size;
380 iflib_rxsd_array_t ifl_sds;
383 bus_dma_tag_t ifl_desc_tag;
384 iflib_dma_info_t ifl_ifdi;
385 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
386 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
387 } __aligned(CACHE_LINE_SIZE);
390 get_inuse(int size, int cidx, int pidx, int gen)
396 else if (pidx < cidx)
397 used = size - cidx + pidx;
398 else if (gen == 0 && pidx == cidx)
400 else if (gen == 1 && pidx == cidx)
408 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
410 #define IDXDIFF(head, tail, wrap) \
411 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
414 /* If there is a separate completion queue -
415 * these are the cq cidx and pidx. Otherwise
419 uint16_t ifr_cq_cidx;
420 uint16_t ifr_cq_pidx;
422 uint8_t ifr_fl_offset;
428 uint8_t ifr_lro_enabled;
430 struct lro_ctrl ifr_lc;
431 struct grouptask ifr_task;
432 struct iflib_filter_info ifr_filter_info;
433 iflib_dma_info_t ifr_ifdi;
434 /* dynamically allocate if any drivers need a value substantially larger than this */
435 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
436 #ifdef IFLIB_DIAGNOSTICS
437 uint64_t ifr_cpu_exec_count[256];
439 } __aligned(CACHE_LINE_SIZE);
442 * Only allow a single packet to take up most 1/nth of the tx ring
444 #define MAX_SINGLE_PACKET_FRACTION 12
445 #define IF_BAD_DMA (bus_addr_t)-1
447 static int enable_msix = 1;
449 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
451 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
453 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
454 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
455 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
458 #define TXDB_LOCK_INIT(txq) mtx_init(&(txq)->ift_db_mtx, (txq)->ift_db_mtx_name, NULL, MTX_DEF)
459 #define TXDB_TRYLOCK(txq) mtx_trylock(&(txq)->ift_db_mtx)
460 #define TXDB_LOCK(txq) mtx_lock(&(txq)->ift_db_mtx)
461 #define TXDB_UNLOCK(txq) mtx_unlock(&(txq)->ift_db_mtx)
462 #define TXDB_LOCK_DESTROY(txq) mtx_destroy(&(txq)->ift_db_mtx)
464 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
465 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
468 /* Our boot-time initialization hook */
469 static int iflib_module_event_handler(module_t, int, void *);
471 static moduledata_t iflib_moduledata = {
473 iflib_module_event_handler,
477 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
478 MODULE_VERSION(iflib, 1);
480 MODULE_DEPEND(iflib, pci, 1, 1, 1);
481 MODULE_DEPEND(iflib, ether, 1, 1, 1);
483 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
485 #ifndef IFLIB_DEBUG_COUNTERS
487 #define IFLIB_DEBUG_COUNTERS 1
489 #define IFLIB_DEBUG_COUNTERS 0
490 #endif /* !INVARIANTS */
493 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
494 "iflib driver parameters");
497 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
499 static int iflib_min_tx_latency = 0;
501 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
502 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
505 #if IFLIB_DEBUG_COUNTERS
507 static int iflib_tx_seen;
508 static int iflib_tx_sent;
509 static int iflib_tx_encap;
510 static int iflib_rx_allocs;
511 static int iflib_fl_refills;
512 static int iflib_fl_refills_large;
513 static int iflib_tx_frees;
515 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
516 &iflib_tx_seen, 0, "# tx mbufs seen");
517 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
518 &iflib_tx_sent, 0, "# tx mbufs sent");
519 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
520 &iflib_tx_encap, 0, "# tx mbufs encapped");
521 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
522 &iflib_tx_frees, 0, "# tx frees");
523 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
524 &iflib_rx_allocs, 0, "# rx allocations");
525 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
526 &iflib_fl_refills, 0, "# refills");
527 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
528 &iflib_fl_refills_large, 0, "# large refills");
531 static int iflib_txq_drain_flushing;
532 static int iflib_txq_drain_oactive;
533 static int iflib_txq_drain_notready;
534 static int iflib_txq_drain_encapfail;
536 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
537 &iflib_txq_drain_flushing, 0, "# drain flushes");
538 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
539 &iflib_txq_drain_oactive, 0, "# drain oactives");
540 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
541 &iflib_txq_drain_notready, 0, "# drain notready");
542 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
543 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
546 static int iflib_encap_load_mbuf_fail;
547 static int iflib_encap_txq_avail_fail;
548 static int iflib_encap_txd_encap_fail;
550 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
551 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
552 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
553 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
554 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
555 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
557 static int iflib_task_fn_rxs;
558 static int iflib_rx_intr_enables;
559 static int iflib_fast_intrs;
560 static int iflib_intr_link;
561 static int iflib_intr_msix;
562 static int iflib_rx_unavail;
563 static int iflib_rx_ctx_inactive;
564 static int iflib_rx_zero_len;
565 static int iflib_rx_if_input;
566 static int iflib_rx_mbuf_null;
567 static int iflib_rxd_flush;
569 static int iflib_verbose_debug;
571 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
572 &iflib_intr_link, 0, "# intr link calls");
573 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
574 &iflib_intr_msix, 0, "# intr msix calls");
575 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
576 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
577 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
578 &iflib_rx_intr_enables, 0, "# rx intr enables");
579 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
580 &iflib_fast_intrs, 0, "# fast_intr calls");
581 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
582 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
583 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
584 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
585 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
586 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
587 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
588 &iflib_rx_if_input, 0, "# times rxeof called if_input");
589 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
590 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
591 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
592 &iflib_rxd_flush, 0, "# times rxd_flush called");
593 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
594 &iflib_verbose_debug, 0, "enable verbose debugging");
596 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
598 iflib_debug_reset(void)
600 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
601 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
602 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
603 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
604 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail =
605 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables =
606 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
607 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
608 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
612 #define DBG_COUNTER_INC(name)
613 static void iflib_debug_reset(void) {}
618 #define IFLIB_DEBUG 0
620 static void iflib_tx_structures_free(if_ctx_t ctx);
621 static void iflib_rx_structures_free(if_ctx_t ctx);
622 static int iflib_queues_alloc(if_ctx_t ctx);
623 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
624 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget);
625 static int iflib_qset_structures_setup(if_ctx_t ctx);
626 static int iflib_msix_init(if_ctx_t ctx);
627 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
628 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
629 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
630 static int iflib_register(if_ctx_t);
631 static void iflib_init_locked(if_ctx_t ctx);
632 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
633 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
634 static void iflib_ifmp_purge(iflib_txq_t txq);
635 static void _iflib_pre_assert(if_softc_ctx_t scctx);
638 #include <sys/selinfo.h>
639 #include <net/netmap.h>
640 #include <dev/netmap/netmap_kern.h>
642 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
645 * device-specific sysctl variables:
647 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
648 * During regular operations the CRC is stripped, but on some
649 * hardware reception of frames not multiple of 64 is slower,
650 * so using crcstrip=0 helps in benchmarks.
652 * iflib_rx_miss, iflib_rx_miss_bufs:
653 * count packets that might be missed due to lost interrupts.
655 SYSCTL_DECL(_dev_netmap);
657 * The xl driver by default strips CRCs and we do not override it.
660 int iflib_crcstrip = 1;
661 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
662 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
664 int iflib_rx_miss, iflib_rx_miss_bufs;
665 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
666 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
667 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
668 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
671 * Register/unregister. We are already under netmap lock.
672 * Only called on the first register or the last unregister.
675 iflib_netmap_register(struct netmap_adapter *na, int onoff)
677 struct ifnet *ifp = na->ifp;
678 if_ctx_t ctx = ifp->if_softc;
681 IFDI_INTR_DISABLE(ctx);
683 /* Tell the stack that the interface is no longer active */
684 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
687 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
689 /* enable or disable flags and callbacks in na and ifp */
691 nm_set_native_flags(na);
693 nm_clear_native_flags(na);
696 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
698 return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1);
702 * Reconcile kernel and user view of the transmit ring.
704 * All information is in the kring.
705 * Userspace wants to send packets up to the one before kring->rhead,
706 * kernel knows kring->nr_hwcur is the first unsent packet.
708 * Here we push packets out (as many as possible), and possibly
709 * reclaim buffers from previously completed transmission.
711 * The caller (netmap) guarantees that there is only one instance
712 * running at any time. Any interference with other driver
713 * methods should be handled by the individual drivers.
716 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
718 struct netmap_adapter *na = kring->na;
719 struct ifnet *ifp = na->ifp;
720 struct netmap_ring *ring = kring->ring;
721 u_int nm_i; /* index into the netmap ring */
722 u_int nic_i; /* index into the NIC ring */
724 u_int const lim = kring->nkr_num_slots - 1;
725 u_int const head = kring->rhead;
726 struct if_pkt_info pi;
729 * interrupts on every tx packet are expensive so request
730 * them every half ring, or where NS_REPORT is set
732 u_int report_frequency = kring->nkr_num_slots >> 1;
733 /* device-specific */
734 if_ctx_t ctx = ifp->if_softc;
735 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
737 pi.ipi_segs = txq->ift_segs;
738 pi.ipi_qsidx = kring->ring_id;
741 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
742 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
746 * First part: process new packets to send.
747 * nm_i is the current index in the netmap ring,
748 * nic_i is the corresponding index in the NIC ring.
750 * If we have packets to send (nm_i != head)
751 * iterate over the netmap ring, fetch length and update
752 * the corresponding slot in the NIC ring. Some drivers also
753 * need to update the buffer's physical address in the NIC slot
754 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
756 * The netmap_reload_map() calls is especially expensive,
757 * even when (as in this case) the tag is 0, so do only
758 * when the buffer has actually changed.
760 * If possible do not set the report/intr bit on all slots,
761 * but only a few times per ring or when NS_REPORT is set.
763 * Finally, on 10G and faster drivers, it might be useful
764 * to prefetch the next slot and txr entry.
767 nm_i = kring->nr_hwcur;
768 if (nm_i != head) { /* we have new packets to send */
769 nic_i = netmap_idx_k2n(kring, nm_i);
771 __builtin_prefetch(&ring->slot[nm_i]);
772 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
773 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
775 for (n = 0; nm_i != head; n++) {
776 struct netmap_slot *slot = &ring->slot[nm_i];
777 u_int len = slot->len;
779 void *addr = PNMB(na, slot, &paddr);
780 int flags = (slot->flags & NS_REPORT ||
781 nic_i == 0 || nic_i == report_frequency) ?
784 /* device-specific */
786 pi.ipi_flags = flags;
788 /* Fill the slot in the NIC ring. */
789 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
791 /* prefetch for next round */
792 __builtin_prefetch(&ring->slot[nm_i + 1]);
793 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
794 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
796 NM_CHECK_ADDR_LEN(na, addr, len);
798 if (slot->flags & NS_BUF_CHANGED) {
799 /* buffer has changed, reload map */
800 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
802 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
804 /* make sure changes to the buffer are synced */
805 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
806 BUS_DMASYNC_PREWRITE);
808 nm_i = nm_next(nm_i, lim);
809 nic_i = nm_next(nic_i, lim);
811 kring->nr_hwcur = head;
813 /* synchronize the NIC ring */
814 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
817 /* (re)start the tx unit up to slot nic_i (excluded) */
818 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
822 * Second part: reclaim buffers for completed transmissions.
824 if (iflib_tx_credits_update(ctx, txq)) {
825 /* some tx completed, increment avail */
826 nic_i = txq->ift_cidx_processed;
827 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
833 * Reconcile kernel and user view of the receive ring.
834 * Same as for the txsync, this routine must be efficient.
835 * The caller guarantees a single invocations, but races against
836 * the rest of the driver should be handled here.
838 * On call, kring->rhead is the first packet that userspace wants
839 * to keep, and kring->rcur is the wakeup point.
840 * The kernel has previously reported packets up to kring->rtail.
842 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
843 * of whether or not we received an interrupt.
846 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
848 struct netmap_adapter *na = kring->na;
849 struct ifnet *ifp = na->ifp;
850 struct netmap_ring *ring = kring->ring;
851 u_int nm_i; /* index into the netmap ring */
852 u_int nic_i; /* index into the NIC ring */
854 u_int const lim = kring->nkr_num_slots - 1;
855 u_int const head = kring->rhead;
856 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
857 struct if_rxd_info ri;
858 /* device-specific */
859 if_ctx_t ctx = ifp->if_softc;
860 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
861 iflib_fl_t fl = rxq->ifr_fl;
863 return netmap_ring_reinit(kring);
865 bzero(&ri, sizeof(ri));
866 ri.iri_qsidx = kring->ring_id;
867 ri.iri_ifp = ctx->ifc_ifp;
868 /* XXX check sync modes */
869 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++)
870 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
871 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
874 * First part: import newly received packets.
876 * nm_i is the index of the next free slot in the netmap ring,
877 * nic_i is the index of the next received packet in the NIC ring,
878 * and they may differ in case if_init() has been called while
879 * in netmap mode. For the receive ring we have
881 * nic_i = rxr->next_check;
882 * nm_i = kring->nr_hwtail (previous)
884 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
886 * rxr->next_check is set to 0 on a ring reinit
888 if (netmap_no_pendintr || force_update) {
889 int crclen = iflib_crcstrip ? 0 : 4;
891 uint16_t slot_flags = kring->nkr_slot_flags;
893 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) {
894 nic_i = fl->ifl_cidx;
895 nm_i = netmap_idx_n2k(kring, nic_i);
896 avail = ctx->isc_rxd_available(ctx->ifc_softc, kring->ring_id, nic_i, INT_MAX);
897 for (n = 0; avail > 0; n++, avail--) {
898 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
900 ring->slot[nm_i].len = 0;
902 ring->slot[nm_i].len = ri.iri_len - crclen;
903 ring->slot[nm_i].flags = slot_flags;
904 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
905 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
906 nm_i = nm_next(nm_i, lim);
907 nic_i = nm_next(nic_i, lim);
909 if (n) { /* update the state variables */
910 if (netmap_no_pendintr && !force_update) {
913 iflib_rx_miss_bufs += n;
915 fl->ifl_cidx = nic_i;
916 kring->nr_hwtail = nm_i;
918 kring->nr_kflags &= ~NKR_PENDINTR;
922 * Second part: skip past packets that userspace has released.
923 * (kring->nr_hwcur to head excluded),
924 * and make the buffers available for reception.
925 * As usual nm_i is the index in the netmap ring,
926 * nic_i is the index in the NIC ring, and
927 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
929 /* XXX not sure how this will work with multiple free lists */
930 nm_i = kring->nr_hwcur;
932 nic_i = netmap_idx_k2n(kring, nm_i);
933 for (n = 0; nm_i != head; n++) {
934 struct netmap_slot *slot = &ring->slot[nm_i];
937 void *addr = PNMB(na, slot, &paddr);
939 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
943 if (slot->flags & NS_BUF_CHANGED) {
944 /* buffer has changed, reload map */
945 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr);
946 slot->flags &= ~NS_BUF_CHANGED;
949 * XXX we should be batching this operation - TODO
951 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i, &paddr, &vaddr, 1, fl->ifl_buf_size);
952 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i],
953 BUS_DMASYNC_PREREAD);
954 nm_i = nm_next(nm_i, lim);
955 nic_i = nm_next(nic_i, lim);
957 kring->nr_hwcur = head;
959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
962 * IMPORTANT: we must leave one free slot in the ring,
963 * so move nic_i back by one unit
965 nic_i = nm_prev(nic_i, lim);
966 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
972 return netmap_ring_reinit(kring);
976 iflib_netmap_attach(if_ctx_t ctx)
978 struct netmap_adapter na;
979 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
981 bzero(&na, sizeof(na));
983 na.ifp = ctx->ifc_ifp;
984 na.na_flags = NAF_BDG_MAYSLEEP;
985 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
986 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
988 na.num_tx_desc = scctx->isc_ntxd[0];
989 na.num_rx_desc = scctx->isc_nrxd[0];
990 na.nm_txsync = iflib_netmap_txsync;
991 na.nm_rxsync = iflib_netmap_rxsync;
992 na.nm_register = iflib_netmap_register;
993 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
994 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
995 return (netmap_attach(&na));
999 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1001 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1002 struct netmap_slot *slot;
1004 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1008 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1011 * In netmap mode, set the map for the packet buffer.
1012 * NOTE: Some drivers (not this one) also need to set
1013 * the physical buffer address in the NIC ring.
1014 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1015 * netmap slot index, si
1017 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1018 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1022 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1024 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1025 struct netmap_slot *slot;
1029 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1032 map = rxq->ifr_fl[0].ifl_sds.ifsd_map;
1033 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0];
1034 for (int i = 0; i < nrxd; i++, map++) {
1035 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i);
1040 vaddr = addr = PNMB(na, slot + sj, &paddr);
1041 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr);
1042 /* Update descriptor and the cached value */
1043 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, i, &paddr, &vaddr, 1, rxq->ifr_fl[0].ifl_buf_size);
1045 /* preserve queue */
1046 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) {
1047 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1048 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1049 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t);
1051 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1);
1054 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1057 #define iflib_netmap_txq_init(ctx, txq)
1058 #define iflib_netmap_rxq_init(ctx, rxq)
1059 #define iflib_netmap_detach(ifp)
1061 #define iflib_netmap_attach(ctx) (0)
1062 #define netmap_rx_irq(ifp, qid, budget) (0)
1066 #if defined(__i386__) || defined(__amd64__)
1067 static __inline void
1070 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1077 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1081 *(bus_addr_t *) arg = segs[0].ds_addr;
1085 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1088 if_shared_ctx_t sctx = ctx->ifc_sctx;
1089 device_t dev = ctx->ifc_dev;
1091 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1093 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1094 sctx->isc_q_align, 0, /* alignment, bounds */
1095 BUS_SPACE_MAXADDR, /* lowaddr */
1096 BUS_SPACE_MAXADDR, /* highaddr */
1097 NULL, NULL, /* filter, filterarg */
1100 size, /* maxsegsize */
1101 BUS_DMA_ALLOCNOW, /* flags */
1102 NULL, /* lockfunc */
1107 "%s: bus_dma_tag_create failed: %d\n",
1112 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1113 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1116 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1117 __func__, (uintmax_t)size, err);
1121 dma->idi_paddr = IF_BAD_DMA;
1122 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1123 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1124 if (err || dma->idi_paddr == IF_BAD_DMA) {
1126 "%s: bus_dmamap_load failed: %d\n",
1131 dma->idi_size = size;
1135 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1137 bus_dma_tag_destroy(dma->idi_tag);
1139 dma->idi_tag = NULL;
1145 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1148 iflib_dma_info_t *dmaiter;
1151 for (i = 0; i < count; i++, dmaiter++) {
1152 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1156 iflib_dma_free_multi(dmalist, i);
1161 iflib_dma_free(iflib_dma_info_t dma)
1163 if (dma->idi_tag == NULL)
1165 if (dma->idi_paddr != IF_BAD_DMA) {
1166 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1167 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1168 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1169 dma->idi_paddr = IF_BAD_DMA;
1171 if (dma->idi_vaddr != NULL) {
1172 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1173 dma->idi_vaddr = NULL;
1175 bus_dma_tag_destroy(dma->idi_tag);
1176 dma->idi_tag = NULL;
1180 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1183 iflib_dma_info_t *dmaiter = dmalist;
1185 for (i = 0; i < count; i++, dmaiter++)
1186 iflib_dma_free(*dmaiter);
1189 #ifdef EARLY_AP_STARTUP
1190 static const int iflib_started = 1;
1193 * We used to abuse the smp_started flag to decide if the queues have been
1194 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1195 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1196 * is set. Run a SYSINIT() strictly after that to just set a usable
1200 static int iflib_started;
1203 iflib_record_started(void *arg)
1208 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1209 iflib_record_started, NULL);
1213 iflib_fast_intr(void *arg)
1215 iflib_filter_info_t info = arg;
1216 struct grouptask *gtask = info->ifi_task;
1219 return (FILTER_HANDLED);
1221 DBG_COUNTER_INC(fast_intrs);
1222 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1223 return (FILTER_HANDLED);
1225 GROUPTASK_ENQUEUE(gtask);
1226 return (FILTER_HANDLED);
1230 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1231 driver_filter_t filter, driver_intr_t handler, void *arg,
1235 struct resource *res;
1237 device_t dev = ctx->ifc_dev;
1241 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid,
1242 RF_SHAREABLE | RF_ACTIVE);
1245 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1249 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1250 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1251 filter, handler, arg, &tag);
1254 "failed to setup interrupt for rid %d, name %s: %d\n",
1255 rid, name ? name : "unknown", rc);
1258 bus_describe_intr(dev, res, tag, "%s", name);
1265 /*********************************************************************
1267 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1268 * the information needed to transmit a packet on the wire. This is
1269 * called only once at attach, setup is done every reset.
1271 **********************************************************************/
1274 iflib_txsd_alloc(iflib_txq_t txq)
1276 if_ctx_t ctx = txq->ift_ctx;
1277 if_shared_ctx_t sctx = ctx->ifc_sctx;
1278 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1279 device_t dev = ctx->ifc_dev;
1280 int err, nsegments, ntsosegments;
1282 nsegments = scctx->isc_tx_nsegments;
1283 ntsosegments = scctx->isc_tx_tso_segments_max;
1284 MPASS(scctx->isc_ntxd[0] > 0);
1285 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1286 MPASS(nsegments > 0);
1287 MPASS(ntsosegments > 0);
1289 * Setup DMA descriptor areas.
1291 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1292 1, 0, /* alignment, bounds */
1293 BUS_SPACE_MAXADDR, /* lowaddr */
1294 BUS_SPACE_MAXADDR, /* highaddr */
1295 NULL, NULL, /* filter, filterarg */
1296 sctx->isc_tx_maxsize, /* maxsize */
1297 nsegments, /* nsegments */
1298 sctx->isc_tx_maxsegsize, /* maxsegsize */
1300 NULL, /* lockfunc */
1301 NULL, /* lockfuncarg */
1302 &txq->ift_desc_tag))) {
1303 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1304 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n",
1305 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize);
1308 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1309 1, 0, /* alignment, bounds */
1310 BUS_SPACE_MAXADDR, /* lowaddr */
1311 BUS_SPACE_MAXADDR, /* highaddr */
1312 NULL, NULL, /* filter, filterarg */
1313 scctx->isc_tx_tso_size_max, /* maxsize */
1314 ntsosegments, /* nsegments */
1315 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1317 NULL, /* lockfunc */
1318 NULL, /* lockfuncarg */
1319 &txq->ift_tso_desc_tag))) {
1320 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1324 if (!(txq->ift_sds.ifsd_flags =
1325 (uint8_t *) malloc(sizeof(uint8_t) *
1326 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1327 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1331 if (!(txq->ift_sds.ifsd_m =
1332 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1333 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1334 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1339 /* Create the descriptor buffer dma maps */
1340 #if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__)))
1341 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1344 if (!(txq->ift_sds.ifsd_map =
1345 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1346 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1351 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1352 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1354 device_printf(dev, "Unable to create TX DMA map\n");
1361 /* We free all, it handles case where we are in the middle */
1362 iflib_tx_structures_free(ctx);
1367 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1372 if (txq->ift_sds.ifsd_map != NULL)
1373 map = txq->ift_sds.ifsd_map[i];
1375 bus_dmamap_unload(txq->ift_desc_tag, map);
1376 bus_dmamap_destroy(txq->ift_desc_tag, map);
1377 txq->ift_sds.ifsd_map[i] = NULL;
1382 iflib_txq_destroy(iflib_txq_t txq)
1384 if_ctx_t ctx = txq->ift_ctx;
1386 for (int i = 0; i < txq->ift_size; i++)
1387 iflib_txsd_destroy(ctx, txq, i);
1388 if (txq->ift_sds.ifsd_map != NULL) {
1389 free(txq->ift_sds.ifsd_map, M_IFLIB);
1390 txq->ift_sds.ifsd_map = NULL;
1392 if (txq->ift_sds.ifsd_m != NULL) {
1393 free(txq->ift_sds.ifsd_m, M_IFLIB);
1394 txq->ift_sds.ifsd_m = NULL;
1396 if (txq->ift_sds.ifsd_flags != NULL) {
1397 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1398 txq->ift_sds.ifsd_flags = NULL;
1400 if (txq->ift_desc_tag != NULL) {
1401 bus_dma_tag_destroy(txq->ift_desc_tag);
1402 txq->ift_desc_tag = NULL;
1404 if (txq->ift_tso_desc_tag != NULL) {
1405 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1406 txq->ift_tso_desc_tag = NULL;
1411 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1415 mp = &txq->ift_sds.ifsd_m[i];
1419 if (txq->ift_sds.ifsd_map != NULL) {
1420 bus_dmamap_sync(txq->ift_desc_tag,
1421 txq->ift_sds.ifsd_map[i],
1422 BUS_DMASYNC_POSTWRITE);
1423 bus_dmamap_unload(txq->ift_desc_tag,
1424 txq->ift_sds.ifsd_map[i]);
1427 DBG_COUNTER_INC(tx_frees);
1432 iflib_txq_setup(iflib_txq_t txq)
1434 if_ctx_t ctx = txq->ift_ctx;
1435 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1436 iflib_dma_info_t di;
1439 /* Set number of descriptors available */
1440 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1443 txq->ift_cidx_processed = txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1444 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1446 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1447 bzero((void *)di->idi_vaddr, di->idi_size);
1449 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1450 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1451 bus_dmamap_sync(di->idi_tag, di->idi_map,
1452 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1456 /*********************************************************************
1458 * Allocate memory for rx_buffer structures. Since we use one
1459 * rx_buffer per received packet, the maximum number of rx_buffer's
1460 * that we'll need is equal to the number of receive descriptors
1461 * that we've allocated.
1463 **********************************************************************/
1465 iflib_rxsd_alloc(iflib_rxq_t rxq)
1467 if_ctx_t ctx = rxq->ifr_ctx;
1468 if_shared_ctx_t sctx = ctx->ifc_sctx;
1469 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1470 device_t dev = ctx->ifc_dev;
1474 MPASS(scctx->isc_nrxd[0] > 0);
1475 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1478 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1479 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1480 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1481 1, 0, /* alignment, bounds */
1482 BUS_SPACE_MAXADDR, /* lowaddr */
1483 BUS_SPACE_MAXADDR, /* highaddr */
1484 NULL, NULL, /* filter, filterarg */
1485 sctx->isc_rx_maxsize, /* maxsize */
1486 sctx->isc_rx_nsegments, /* nsegments */
1487 sctx->isc_rx_maxsegsize, /* maxsegsize */
1489 NULL, /* lockfunc */
1493 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1497 if (!(fl->ifl_sds.ifsd_flags =
1498 (uint8_t *) malloc(sizeof(uint8_t) *
1499 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1500 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1504 if (!(fl->ifl_sds.ifsd_m =
1505 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1506 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1507 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1511 if (!(fl->ifl_sds.ifsd_cl =
1512 (caddr_t *) malloc(sizeof(caddr_t) *
1513 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1514 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1519 /* Create the descriptor buffer dma maps */
1520 #if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__)))
1521 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1524 if (!(fl->ifl_sds.ifsd_map =
1525 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1526 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1531 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1532 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1534 device_printf(dev, "Unable to create TX DMA map\n");
1543 iflib_rx_structures_free(ctx);
1549 * Internal service routines
1552 struct rxq_refill_cb_arg {
1554 bus_dma_segment_t seg;
1559 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1561 struct rxq_refill_cb_arg *cb_arg = arg;
1563 cb_arg->error = error;
1564 cb_arg->seg = segs[0];
1565 cb_arg->nseg = nseg;
1570 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1572 #define IS_DMAR(ctx) (0)
1576 * rxq_refill - refill an rxq free-buffer list
1577 * @ctx: the iflib context
1578 * @rxq: the free-list to refill
1579 * @n: the number of new buffers to allocate
1581 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1582 * The caller must assure that @n does not exceed the queue's capacity.
1585 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1588 int idx, pidx = fl->ifl_pidx;
1592 bus_dmamap_t *sd_map;
1597 sd_m = fl->ifl_sds.ifsd_m;
1598 sd_map = fl->ifl_sds.ifsd_map;
1599 sd_cl = fl->ifl_sds.ifsd_cl;
1600 sd_flags = fl->ifl_sds.ifsd_flags;
1605 MPASS(fl->ifl_credits + n <= fl->ifl_size);
1607 if (pidx < fl->ifl_cidx)
1608 MPASS(pidx + n <= fl->ifl_cidx);
1609 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size))
1610 MPASS(fl->ifl_gen == 0);
1611 if (pidx > fl->ifl_cidx)
1612 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1614 DBG_COUNTER_INC(fl_refills);
1616 DBG_COUNTER_INC(fl_refills_large);
1620 * We allocate an uninitialized mbuf + cluster, mbuf is
1621 * initialized after rx.
1623 * If the cluster is still set then we know a minimum sized packet was received
1625 if ((cl = sd_cl[idx]) == NULL) {
1626 if ((cl = sd_cl[idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1629 fl->ifl_cl_enqueued++;
1632 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1636 fl->ifl_m_enqueued++;
1639 DBG_COUNTER_INC(rx_allocs);
1641 if ((sd_flags[pidx] & RX_SW_DESC_MAP_CREATED) == 0) {
1644 if ((err = bus_dmamap_create(fl->ifl_ifdi->idi_tag, 0, &sd_map[idx]))) {
1645 log(LOG_WARNING, "bus_dmamap_create failed %d\n", err);
1646 uma_zfree(fl->ifl_zone, cl);
1650 sd_flags[idx] |= RX_SW_DESC_MAP_CREATED;
1653 #if defined(__i386__) || defined(__amd64__)
1654 if (!IS_DMAR(ctx)) {
1655 bus_addr = pmap_kextract((vm_offset_t)cl);
1659 struct rxq_refill_cb_arg cb_arg;
1664 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[idx],
1665 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1667 if (err != 0 || cb_arg.error) {
1671 if (fl->ifl_zone == zone_pack)
1672 uma_zfree(fl->ifl_zone, cl);
1677 bus_addr = cb_arg.seg.ds_addr;
1679 sd_flags[idx] |= RX_SW_DESC_INUSE;
1681 MPASS(sd_m[idx] == NULL);
1684 fl->ifl_bus_addrs[i] = bus_addr;
1685 fl->ifl_vm_addrs[i] = cl;
1688 MPASS(fl->ifl_credits <= fl->ifl_size);
1689 if (++idx == fl->ifl_size) {
1693 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1694 ctx->isc_rxd_refill(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx,
1695 fl->ifl_bus_addrs, fl->ifl_vm_addrs, i, fl->ifl_buf_size);
1703 DBG_COUNTER_INC(rxd_flush);
1704 if (fl->ifl_pidx == 0)
1705 pidx = fl->ifl_size - 1;
1707 pidx = fl->ifl_pidx - 1;
1708 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1711 static __inline void
1712 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1714 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1715 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1717 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1720 MPASS(fl->ifl_credits <= fl->ifl_size);
1721 MPASS(reclaimable == delta);
1723 if (reclaimable > 0)
1724 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1728 iflib_fl_bufs_free(iflib_fl_t fl)
1730 iflib_dma_info_t idi = fl->ifl_ifdi;
1733 for (i = 0; i < fl->ifl_size; i++) {
1734 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1735 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1736 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1738 if (*sd_flags & RX_SW_DESC_INUSE) {
1739 if (fl->ifl_sds.ifsd_map != NULL) {
1740 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1741 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1742 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1744 if (*sd_m != NULL) {
1745 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1746 uma_zfree(zone_mbuf, *sd_m);
1749 uma_zfree(fl->ifl_zone, *sd_cl);
1752 MPASS(*sd_cl == NULL);
1753 MPASS(*sd_m == NULL);
1756 fl->ifl_m_dequeued++;
1757 fl->ifl_cl_dequeued++;
1763 * Reset free list values
1765 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;;
1766 bzero(idi->idi_vaddr, idi->idi_size);
1769 /*********************************************************************
1771 * Initialize a receive ring and its buffers.
1773 **********************************************************************/
1775 iflib_fl_setup(iflib_fl_t fl)
1777 iflib_rxq_t rxq = fl->ifl_rxq;
1778 if_ctx_t ctx = rxq->ifr_ctx;
1779 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
1782 ** Free current RX buffer structs and their mbufs
1784 iflib_fl_bufs_free(fl);
1785 /* Now replenish the mbufs */
1786 MPASS(fl->ifl_credits == 0);
1788 * XXX don't set the max_frame_size to larger
1789 * than the hardware can handle
1791 if (sctx->isc_max_frame_size <= 2048)
1792 fl->ifl_buf_size = MCLBYTES;
1793 else if (sctx->isc_max_frame_size <= 4096)
1794 fl->ifl_buf_size = MJUMPAGESIZE;
1795 else if (sctx->isc_max_frame_size <= 9216)
1796 fl->ifl_buf_size = MJUM9BYTES;
1798 fl->ifl_buf_size = MJUM16BYTES;
1799 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
1800 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
1801 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
1802 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
1805 /* avoid pre-allocating zillions of clusters to an idle card
1806 * potentially speeding up attach
1808 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
1809 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
1810 if (min(128, fl->ifl_size) != fl->ifl_credits)
1816 MPASS(fl->ifl_ifdi != NULL);
1817 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1818 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1822 /*********************************************************************
1824 * Free receive ring data structures
1826 **********************************************************************/
1828 iflib_rx_sds_free(iflib_rxq_t rxq)
1833 if (rxq->ifr_fl != NULL) {
1834 for (i = 0; i < rxq->ifr_nfl; i++) {
1835 fl = &rxq->ifr_fl[i];
1836 if (fl->ifl_desc_tag != NULL) {
1837 bus_dma_tag_destroy(fl->ifl_desc_tag);
1838 fl->ifl_desc_tag = NULL;
1840 free(fl->ifl_sds.ifsd_m, M_IFLIB);
1841 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
1842 /* XXX destroy maps first */
1843 free(fl->ifl_sds.ifsd_map, M_IFLIB);
1844 fl->ifl_sds.ifsd_m = NULL;
1845 fl->ifl_sds.ifsd_cl = NULL;
1846 fl->ifl_sds.ifsd_map = NULL;
1848 free(rxq->ifr_fl, M_IFLIB);
1850 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
1855 * MI independent logic
1859 iflib_timer(void *arg)
1861 iflib_txq_t txq = arg;
1862 if_ctx_t ctx = txq->ift_ctx;
1863 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1865 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
1868 ** Check on the state of the TX queue(s), this
1869 ** can be done without the lock because its RO
1870 ** and the HUNG state will be static if set.
1872 IFDI_TIMER(ctx, txq->ift_id);
1873 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
1874 (ctx->ifc_pause_frames == 0))
1877 if (TXQ_AVAIL(txq) <= 2*scctx->isc_tx_nsegments ||
1878 ifmp_ring_is_stalled(txq->ift_br[0]))
1879 GROUPTASK_ENQUEUE(&txq->ift_task);
1881 ctx->ifc_pause_frames = 0;
1882 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
1883 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
1887 if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING);
1888 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
1889 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
1891 IFDI_WATCHDOG_RESET(ctx);
1892 ctx->ifc_watchdog_events++;
1893 ctx->ifc_pause_frames = 0;
1895 iflib_init_locked(ctx);
1900 iflib_init_locked(if_ctx_t ctx)
1902 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
1903 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1904 if_t ifp = ctx->ifc_ifp;
1908 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
1911 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
1912 IFDI_INTR_DISABLE(ctx);
1914 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
1915 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
1916 /* Set hardware offload abilities */
1917 if_clearhwassist(ifp);
1918 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
1919 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
1920 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
1921 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
1922 if (if_getcapenable(ifp) & IFCAP_TSO4)
1923 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
1924 if (if_getcapenable(ifp) & IFCAP_TSO6)
1925 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
1927 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
1929 callout_stop(&txq->ift_timer);
1930 callout_stop(&txq->ift_db_check);
1931 CALLOUT_UNLOCK(txq);
1932 iflib_netmap_txq_init(ctx, txq);
1934 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
1935 iflib_netmap_rxq_init(ctx, rxq);
1938 i = if_getdrvflags(ifp);
1941 MPASS(if_getdrvflags(ifp) == i);
1942 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
1943 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
1944 if (iflib_fl_setup(fl)) {
1945 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
1951 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1952 IFDI_INTR_ENABLE(ctx);
1953 txq = ctx->ifc_txqs;
1954 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
1955 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
1956 txq->ift_timer.c_cpu);
1960 iflib_media_change(if_t ifp)
1962 if_ctx_t ctx = if_getsoftc(ifp);
1966 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
1967 iflib_init_locked(ctx);
1973 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
1975 if_ctx_t ctx = if_getsoftc(ifp);
1978 IFDI_UPDATE_ADMIN_STATUS(ctx);
1979 IFDI_MEDIA_STATUS(ctx, ifmr);
1984 iflib_stop(if_ctx_t ctx)
1986 iflib_txq_t txq = ctx->ifc_txqs;
1987 iflib_rxq_t rxq = ctx->ifc_rxqs;
1988 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1989 iflib_dma_info_t di;
1993 /* Tell the stack that the interface is no longer active */
1994 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
1996 IFDI_INTR_DISABLE(ctx);
2001 iflib_debug_reset();
2002 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2003 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2004 /* make sure all transmitters have completed before proceeding XXX */
2006 /* clean any enqueued buffers */
2007 iflib_ifmp_purge(txq);
2008 /* Free any existing tx buffers. */
2009 for (j = 0; j < txq->ift_size; j++) {
2010 iflib_txsd_free(ctx, txq, j);
2012 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2013 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2014 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2015 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2016 txq->ift_pullups = 0;
2017 ifmp_ring_reset_stats(txq->ift_br[0]);
2018 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2019 bzero((void *)di->idi_vaddr, di->idi_size);
2021 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2022 /* make sure all transmitters have completed before proceeding XXX */
2024 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2025 bzero((void *)di->idi_vaddr, di->idi_size);
2026 /* also resets the free lists pidx/cidx */
2027 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2028 iflib_fl_bufs_free(fl);
2033 prefetch_pkts(iflib_fl_t fl, int cidx)
2036 int nrxd = fl->ifl_size;
2038 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2039 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2040 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2041 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2042 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2043 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2044 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2045 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2046 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2047 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2048 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2052 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int *cltype, int unload, iflib_fl_t *pfl, int *pcidx)
2057 iflib_dma_info_t di;
2060 flid = irf->irf_flid;
2061 cidx = irf->irf_idx;
2062 fl = &rxq->ifr_fl[flid];
2065 fl->ifl_m_dequeued++;
2067 fl->ifl_cl_dequeued++;
2069 prefetch_pkts(fl, cidx);
2070 if (fl->ifl_sds.ifsd_map != NULL) {
2071 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2072 prefetch(&fl->ifl_sds.ifsd_map[next]);
2073 map = fl->ifl_sds.ifsd_map[cidx];
2075 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2076 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2077 bus_dmamap_sync(di->idi_tag, di->idi_map,
2078 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2080 /* not valid assert if bxe really does SGE from non-contiguous elements */
2081 MPASS(fl->ifl_cidx == cidx);
2083 bus_dmamap_unload(fl->ifl_desc_tag, map);
2085 if (__predict_false(++fl->ifl_cidx == fl->ifl_size)) {
2091 *cltype = fl->ifl_cltype;
2096 static struct mbuf *
2097 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri)
2099 int i, padlen , flags, cltype;
2100 struct mbuf *m, *mh, *mt, *sd_m;
2108 rxd_frag_to_sd(rxq, &ri->iri_frags[i], &cltype, TRUE, &fl, &cidx);
2109 sd_m = fl->ifl_sds.ifsd_m[cidx];
2110 sd_cl = fl->ifl_sds.ifsd_cl[cidx];
2112 MPASS(sd_cl != NULL);
2113 MPASS(sd_m != NULL);
2115 /* Don't include zero-length frags */
2116 if (ri->iri_frags[i].irf_len == 0) {
2117 /* XXX we can save the cluster here, but not the mbuf */
2118 m_init(sd_m, M_NOWAIT, MT_DATA, 0);
2120 fl->ifl_sds.ifsd_m[cidx] = NULL;
2125 flags = M_PKTHDR|M_EXT;
2127 padlen = ri->iri_pad;
2132 /* assuming padding is only on the first fragment */
2135 fl->ifl_sds.ifsd_m[cidx] = NULL;
2136 cl = fl->ifl_sds.ifsd_cl[cidx];
2137 fl->ifl_sds.ifsd_cl[cidx] = NULL;
2139 /* Can these two be made one ? */
2140 m_init(m, M_NOWAIT, MT_DATA, flags);
2141 m_cljset(m, cl, cltype);
2143 * These must follow m_init and m_cljset
2145 m->m_data += padlen;
2146 ri->iri_len -= padlen;
2147 m->m_len = ri->iri_frags[i].irf_len;
2148 } while (++i < ri->iri_nfrags);
2154 * Process one software descriptor
2156 static struct mbuf *
2157 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2164 /* should I merge this back in now that the two paths are basically duplicated? */
2165 if (ri->iri_nfrags == 1 &&
2166 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2167 rxd_frag_to_sd(rxq, &ri->iri_frags[0], NULL, FALSE, &fl, &cidx);
2168 m = fl->ifl_sds.ifsd_m[cidx];
2169 fl->ifl_sds.ifsd_m[cidx] = NULL;
2170 sd_cl = fl->ifl_sds.ifsd_cl[cidx];
2171 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2172 memcpy(m->m_data, sd_cl, ri->iri_len);
2173 m->m_len = ri->iri_frags[0].irf_len;
2175 m = assemble_segments(rxq, ri);
2177 m->m_pkthdr.len = ri->iri_len;
2178 m->m_pkthdr.rcvif = ri->iri_ifp;
2179 m->m_flags |= ri->iri_flags;
2180 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2181 m->m_pkthdr.flowid = ri->iri_flowid;
2182 M_HASHTYPE_SET(m, ri->iri_rsstype);
2183 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2184 m->m_pkthdr.csum_data = ri->iri_csum_data;
2189 iflib_rxeof(iflib_rxq_t rxq, int budget)
2191 if_ctx_t ctx = rxq->ifr_ctx;
2192 if_shared_ctx_t sctx = ctx->ifc_sctx;
2193 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2196 struct if_rxd_info ri;
2197 int err, budget_left, rx_bytes, rx_pkts;
2202 * XXX early demux data packets so that if_input processing only handles
2203 * acks in interrupt context
2205 struct mbuf *m, *mh, *mt;
2207 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &budget)) {
2213 rx_pkts = rx_bytes = 0;
2214 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2215 cidxp = &rxq->ifr_cq_cidx;
2217 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2218 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2219 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2220 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2221 DBG_COUNTER_INC(rx_unavail);
2225 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2226 if (__predict_false(!CTX_ACTIVE(ctx))) {
2227 DBG_COUNTER_INC(rx_ctx_inactive);
2231 * Reset client set fields to their default values
2233 bzero(&ri, sizeof(ri));
2234 ri.iri_qsidx = rxq->ifr_id;
2235 ri.iri_cidx = *cidxp;
2236 ri.iri_ifp = ctx->ifc_ifp;
2237 ri.iri_frags = rxq->ifr_frags;
2238 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2240 /* in lieu of handling correctly - make sure it isn't being unhandled */
2242 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2243 *cidxp = ri.iri_cidx;
2244 /* Update our consumer index */
2245 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2246 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2247 rxq->ifr_cq_gen = 0;
2249 /* was this only a completion queue message? */
2250 if (__predict_false(ri.iri_nfrags == 0))
2253 MPASS(ri.iri_nfrags != 0);
2254 MPASS(ri.iri_len != 0);
2256 /* will advance the cidx on the corresponding free lists */
2257 m = iflib_rxd_pkt_get(rxq, &ri);
2258 if (avail == 0 && budget_left)
2259 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2261 if (__predict_false(m == NULL)) {
2262 DBG_COUNTER_INC(rx_mbuf_null);
2265 /* imm_pkt: -- cxgb */
2273 /* make sure that we can refill faster than drain */
2274 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2275 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2278 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2279 while (mh != NULL) {
2282 m->m_nextpkt = NULL;
2283 rx_bytes += m->m_pkthdr.len;
2285 #if defined(INET6) || defined(INET)
2286 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2289 DBG_COUNTER_INC(rx_if_input);
2290 ifp->if_input(ifp, m);
2293 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2294 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2297 * Flush any outstanding LRO work
2299 #if defined(INET6) || defined(INET)
2300 tcp_lro_flush_all(&rxq->ifr_lc);
2304 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2307 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2308 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2309 #define TXQ_MAX_DB_DEFERRED(size) (size >> 5)
2310 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2312 static __inline void
2313 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring)
2317 if (ring || txq->ift_db_pending >=
2318 TXQ_MAX_DB_DEFERRED(txq->ift_size)) {
2320 /* the lock will only ever be contended in the !min_latency case */
2321 if (!TXDB_TRYLOCK(txq))
2323 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2324 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2325 txq->ift_db_pending = txq->ift_npending = 0;
2331 iflib_txd_deferred_db_check(void * arg)
2333 iflib_txq_t txq = arg;
2335 /* simple non-zero boolean so use bitwise OR */
2336 if ((txq->ift_db_pending | txq->ift_npending) &&
2337 txq->ift_db_pending >= txq->ift_db_pending_queued)
2338 iflib_txd_db_check(txq->ift_ctx, txq, TRUE);
2339 txq->ift_db_pending_queued = 0;
2340 if (ifmp_ring_is_stalled(txq->ift_br[0]))
2341 iflib_txq_check_drain(txq, 4);
2346 print_pkt(if_pkt_info_t pi)
2348 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2349 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2350 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2351 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2352 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2353 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2357 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2358 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2361 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2363 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2364 struct ether_vlan_header *eh;
2368 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2369 M_WRITABLE(m) == 0) {
2370 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2379 * Determine where frame payload starts.
2380 * Jump over vlan headers if already present,
2381 * helpful for QinQ too.
2383 if (__predict_false(m->m_len < sizeof(*eh))) {
2385 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2388 eh = mtod(m, struct ether_vlan_header *);
2389 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2390 pi->ipi_etype = ntohs(eh->evl_proto);
2391 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2393 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2394 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2397 switch (pi->ipi_etype) {
2401 struct ip *ip = NULL;
2402 struct tcphdr *th = NULL;
2405 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2406 if (__predict_false(m->m_len < minthlen)) {
2408 * if this code bloat is causing too much of a hit
2409 * move it to a separate function and mark it noinline
2411 if (m->m_len == pi->ipi_ehdrlen) {
2414 if (n->m_len >= sizeof(*ip)) {
2415 ip = (struct ip *)n->m_data;
2416 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2417 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2420 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2422 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2426 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2428 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2429 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2430 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2433 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2434 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2435 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2437 pi->ipi_ip_hlen = ip->ip_hl << 2;
2438 pi->ipi_ipproto = ip->ip_p;
2439 pi->ipi_flags |= IPI_TX_IPV4;
2441 if (pi->ipi_csum_flags & CSUM_IP)
2444 if (pi->ipi_ipproto == IPPROTO_TCP) {
2445 if (__predict_false(th == NULL)) {
2447 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2449 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2451 pi->ipi_tcp_hflags = th->th_flags;
2452 pi->ipi_tcp_hlen = th->th_off << 2;
2453 pi->ipi_tcp_seq = th->th_seq;
2456 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2458 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2459 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2460 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2461 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2463 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2470 case ETHERTYPE_IPV6:
2472 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2474 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2476 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2477 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2480 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2482 /* XXX-BZ this will go badly in case of ext hdrs. */
2483 pi->ipi_ipproto = ip6->ip6_nxt;
2484 pi->ipi_flags |= IPI_TX_IPV6;
2486 if (pi->ipi_ipproto == IPPROTO_TCP) {
2487 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2488 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2491 pi->ipi_tcp_hflags = th->th_flags;
2492 pi->ipi_tcp_hlen = th->th_off << 2;
2496 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2499 * The corresponding flag is set by the stack in the IPv4
2500 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2501 * So, set it here because the rest of the flow requires it.
2503 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2504 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2505 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2511 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2512 pi->ipi_ip_hlen = 0;
2520 static __noinline struct mbuf *
2521 collapse_pkthdr(struct mbuf *m0)
2523 struct mbuf *m, *m_next, *tmp;
2527 while (m_next != NULL && m_next->m_len == 0) {
2531 m_next = m_next->m_next;
2535 if ((m_next->m_flags & M_EXT) == 0) {
2536 m = m_defrag(m, M_NOWAIT);
2538 tmp = m_next->m_next;
2539 memcpy(m_next, m, MPKTHSIZE);
2547 * If dodgy hardware rejects the scatter gather chain we've handed it
2548 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2551 static __noinline struct mbuf *
2552 iflib_remove_mbuf(iflib_txq_t txq)
2555 struct mbuf *m, *mh, **ifsd_m;
2557 pidx = txq->ift_pidx;
2558 ifsd_m = txq->ift_sds.ifsd_m;
2559 ntxd = txq->ift_size;
2560 mh = m = ifsd_m[pidx];
2561 ifsd_m[pidx] = NULL;
2563 txq->ift_dequeued++;
2568 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2570 txq->ift_dequeued++;
2579 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2580 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2581 int max_segs, int flags)
2584 if_shared_ctx_t sctx;
2585 if_softc_ctx_t scctx;
2586 int i, next, pidx, mask, err, maxsegsz, ntxd, count;
2587 struct mbuf *m, *tmp, **ifsd_m, **mp;
2592 * Please don't ever do this
2594 if (__predict_false(m->m_len == 0))
2595 *m0 = m = collapse_pkthdr(m);
2598 sctx = ctx->ifc_sctx;
2599 scctx = &ctx->ifc_softc_ctx;
2600 ifsd_m = txq->ift_sds.ifsd_m;
2601 ntxd = txq->ift_size;
2602 pidx = txq->ift_pidx;
2604 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2606 err = bus_dmamap_load_mbuf_sg(tag, map,
2607 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2610 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
2613 mask = (txq->ift_size-1);
2619 if (__predict_false((*mp)->m_len == 0)) {
2623 next = (pidx + i) & (ntxd-1);
2624 } while (m != NULL);
2626 int buflen, sgsize, max_sgsize;
2631 maxsegsz = sctx->isc_tx_maxsize;
2634 if (__predict_false(m->m_len <= 0)) {
2642 vaddr = (vm_offset_t)m->m_data;
2644 * see if we can't be smarter about physically
2645 * contiguous mappings
2647 next = (pidx + count) & (ntxd-1);
2648 MPASS(ifsd_m[next] == NULL);
2650 txq->ift_enqueued++;
2653 while (buflen > 0) {
2654 max_sgsize = MIN(buflen, maxsegsz);
2655 curaddr = pmap_kextract(vaddr);
2656 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
2657 sgsize = MIN(sgsize, max_sgsize);
2658 segs[i].ds_addr = curaddr;
2659 segs[i].ds_len = sgsize;
2669 } while (m != NULL);
2674 *m0 = iflib_remove_mbuf(txq);
2679 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
2682 if_shared_ctx_t sctx;
2683 if_softc_ctx_t scctx;
2684 bus_dma_segment_t *segs;
2685 struct mbuf *m_head;
2687 struct if_pkt_info pi;
2689 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
2690 bus_dma_tag_t desc_tag;
2692 segs = txq->ift_segs;
2694 sctx = ctx->ifc_sctx;
2695 scctx = &ctx->ifc_softc_ctx;
2696 segs = txq->ift_segs;
2697 ntxd = txq->ift_size;
2702 * If we're doing TSO the next descriptor to clean may be quite far ahead
2704 cidx = txq->ift_cidx;
2705 pidx = txq->ift_pidx;
2706 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
2708 /* prefetch the next cache line of mbuf pointers and flags */
2709 prefetch(&txq->ift_sds.ifsd_m[next]);
2710 if (txq->ift_sds.ifsd_map != NULL) {
2711 prefetch(&txq->ift_sds.ifsd_map[next]);
2712 map = txq->ift_sds.ifsd_map[pidx];
2713 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
2714 prefetch(&txq->ift_sds.ifsd_flags[next]);
2718 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2719 desc_tag = txq->ift_tso_desc_tag;
2720 max_segs = scctx->isc_tx_tso_segments_max;
2722 desc_tag = txq->ift_desc_tag;
2723 max_segs = scctx->isc_tx_nsegments;
2726 bzero(&pi, sizeof(pi));
2727 pi.ipi_len = m_head->m_pkthdr.len;
2728 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
2729 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
2730 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
2732 pi.ipi_qsidx = txq->ift_id;
2734 /* deliberate bitwise OR to make one condition */
2735 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
2736 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
2742 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
2744 if (__predict_false(err)) {
2747 /* try collapse once and defrag once */
2749 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
2751 m_head = m_defrag(*m_headp, M_NOWAIT);
2753 if (__predict_false(m_head == NULL))
2755 txq->ift_mbuf_defrag++;
2760 txq->ift_no_tx_dma_setup++;
2763 txq->ift_no_tx_dma_setup++;
2765 DBG_COUNTER_INC(tx_frees);
2769 txq->ift_map_failed++;
2770 DBG_COUNTER_INC(encap_load_mbuf_fail);
2775 * XXX assumes a 1 to 1 relationship between segments and
2776 * descriptors - this does not hold true on all drivers, e.g.
2779 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
2780 txq->ift_no_desc_avail++;
2782 bus_dmamap_unload(desc_tag, map);
2783 DBG_COUNTER_INC(encap_txq_avail_fail);
2784 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
2785 GROUPTASK_ENQUEUE(&txq->ift_task);
2789 pi.ipi_nsegs = nsegs;
2791 MPASS(pidx >= 0 && pidx < txq->ift_size);
2795 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
2796 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2797 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2799 DBG_COUNTER_INC(tx_encap);
2800 MPASS(pi.ipi_new_pidx >= 0 &&
2801 pi.ipi_new_pidx < txq->ift_size);
2803 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
2804 if (pi.ipi_new_pidx < pi.ipi_pidx) {
2805 ndesc += txq->ift_size;
2809 * drivers can need as many as
2812 MPASS(ndesc <= pi.ipi_nsegs + 2);
2813 MPASS(pi.ipi_new_pidx != pidx);
2815 txq->ift_in_use += ndesc;
2817 * We update the last software descriptor again here because there may
2818 * be a sentinel and/or there may be more mbufs than segments
2820 txq->ift_pidx = pi.ipi_new_pidx;
2821 txq->ift_npending += pi.ipi_ndescs;
2822 } else if (__predict_false(err == EFBIG && remap < 2)) {
2823 *m_headp = m_head = iflib_remove_mbuf(txq);
2825 txq->ift_txd_encap_efbig++;
2828 DBG_COUNTER_INC(encap_txd_encap_fail);
2832 txq->ift_mbuf_defrag_failed++;
2833 txq->ift_map_failed++;
2835 DBG_COUNTER_INC(tx_frees);
2840 /* forward compatibility for cxgb */
2841 #define FIRST_QSET(ctx) 0
2843 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2844 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2845 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2846 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2847 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2848 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2852 /* if there are more than TXQ_MIN_OCCUPANCY packets pending we consider deferring
2855 * ORing with 2 assures that min occupancy is never less than 2 without any conditional logic
2857 #define TXQ_MIN_OCCUPANCY(size) ((size >> 6)| 0x2)
2860 iflib_txq_min_occupancy(iflib_txq_t txq)
2865 return (get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx,
2866 txq->ift_gen) < TXQ_MIN_OCCUPANCY(txq->ift_size) +
2871 iflib_tx_desc_free(iflib_txq_t txq, int n)
2874 uint32_t qsize, cidx, mask, gen;
2875 struct mbuf *m, **ifsd_m;
2876 uint8_t *ifsd_flags;
2877 bus_dmamap_t *ifsd_map;
2879 cidx = txq->ift_cidx;
2881 qsize = txq->ift_size;
2883 hasmap = txq->ift_sds.ifsd_map != NULL;
2884 ifsd_flags = txq->ift_sds.ifsd_flags;
2885 ifsd_m = txq->ift_sds.ifsd_m;
2886 ifsd_map = txq->ift_sds.ifsd_map;
2889 prefetch(ifsd_m[(cidx + 3) & mask]);
2890 prefetch(ifsd_m[(cidx + 4) & mask]);
2892 if (ifsd_m[cidx] != NULL) {
2893 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
2894 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
2895 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
2897 * does it matter if it's not the TSO tag? If so we'll
2898 * have to add the type to flags
2900 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
2901 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
2903 if ((m = ifsd_m[cidx]) != NULL) {
2904 /* XXX we don't support any drivers that batch packets yet */
2905 MPASS(m->m_nextpkt == NULL);
2908 ifsd_m[cidx] = NULL;
2910 txq->ift_dequeued++;
2912 DBG_COUNTER_INC(tx_frees);
2915 if (__predict_false(++cidx == qsize)) {
2920 txq->ift_cidx = cidx;
2925 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
2928 if_ctx_t ctx = txq->ift_ctx;
2930 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
2931 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
2934 * Need a rate-limiting check so that this isn't called every time
2936 iflib_tx_credits_update(ctx, txq);
2937 reclaim = DESC_RECLAIMABLE(txq);
2939 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
2941 if (iflib_verbose_debug) {
2942 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
2943 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
2950 iflib_tx_desc_free(txq, reclaim);
2951 txq->ift_cleaned += reclaim;
2952 txq->ift_in_use -= reclaim;
2954 if (txq->ift_active == FALSE)
2955 txq->ift_active = TRUE;
2960 static struct mbuf **
2961 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset)
2964 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (r->size-1)]));
2968 iflib_txq_check_drain(iflib_txq_t txq, int budget)
2971 ifmp_ring_check_drainage(txq->ift_br[0], budget);
2975 iflib_txq_can_drain(struct ifmp_ring *r)
2977 iflib_txq_t txq = r->cookie;
2978 if_ctx_t ctx = txq->ift_ctx;
2980 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
2981 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, false));
2985 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
2987 iflib_txq_t txq = r->cookie;
2988 if_ctx_t ctx = txq->ift_ctx;
2989 if_t ifp = ctx->ifc_ifp;
2990 struct mbuf **mp, *m;
2991 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail, err, in_use_prev, desc_used;
2993 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
2994 !LINK_ACTIVE(ctx))) {
2995 DBG_COUNTER_INC(txq_drain_notready);
2999 avail = IDXDIFF(pidx, cidx, r->size);
3000 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3001 DBG_COUNTER_INC(txq_drain_flushing);
3002 for (i = 0; i < avail; i++) {
3003 m_free(r->items[(cidx + i) & (r->size-1)]);
3004 r->items[(cidx + i) & (r->size-1)] = NULL;
3008 iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3009 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3010 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3012 callout_stop(&txq->ift_timer);
3013 callout_stop(&txq->ift_db_check);
3014 CALLOUT_UNLOCK(txq);
3015 DBG_COUNTER_INC(txq_drain_oactive);
3018 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3019 count = MIN(avail, TX_BATCH_SIZE);
3021 if (iflib_verbose_debug)
3022 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3023 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3026 for (desc_used = i = 0; i < count && TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2; i++) {
3027 mp = _ring_peek_one(r, cidx, i);
3028 MPASS(mp != NULL && *mp != NULL);
3029 in_use_prev = txq->ift_in_use;
3030 if ((err = iflib_encap(txq, mp)) == ENOBUFS) {
3031 DBG_COUNTER_INC(txq_drain_encapfail);
3032 /* no room - bail out */
3037 DBG_COUNTER_INC(txq_drain_encapfail);
3038 /* we can't send this packet - skip it */
3043 DBG_COUNTER_INC(tx_sent);
3044 bytes_sent += m->m_pkthdr.len;
3045 if (m->m_flags & M_MCAST)
3048 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3049 desc_used += (txq->ift_in_use - in_use_prev);
3050 iflib_txd_db_check(ctx, txq, FALSE);
3051 ETHER_BPF_MTAP(ifp, m);
3052 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3055 if (desc_used >= TXQ_MAX_DB_CONSUMED(txq->ift_size))
3059 if ((iflib_min_tx_latency || iflib_txq_min_occupancy(txq)) && txq->ift_db_pending)
3060 iflib_txd_db_check(ctx, txq, TRUE);
3061 else if ((txq->ift_db_pending || TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2) &&
3062 (callout_pending(&txq->ift_db_check) == 0)) {
3063 txq->ift_db_pending_queued = txq->ift_db_pending;
3064 callout_reset_on(&txq->ift_db_check, 1, iflib_txd_deferred_db_check,
3065 txq, txq->ift_db_check.c_cpu);
3067 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3068 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3070 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3072 if (iflib_verbose_debug)
3073 printf("consumed=%d\n", consumed);
3079 iflib_txq_drain_always(struct ifmp_ring *r)
3085 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3093 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3095 callout_stop(&txq->ift_timer);
3096 callout_stop(&txq->ift_db_check);
3097 CALLOUT_UNLOCK(txq);
3099 avail = IDXDIFF(pidx, cidx, r->size);
3100 for (i = 0; i < avail; i++) {
3101 mp = _ring_peek_one(r, cidx, i);
3104 MPASS(ifmp_ring_is_stalled(r) == 0);
3109 iflib_ifmp_purge(iflib_txq_t txq)
3111 struct ifmp_ring *r;
3114 r->drain = iflib_txq_drain_free;
3115 r->can_drain = iflib_txq_drain_always;
3117 ifmp_ring_check_drainage(r, r->size);
3119 r->drain = iflib_txq_drain;
3120 r->can_drain = iflib_txq_can_drain;
3124 _task_fn_tx(void *context)
3126 iflib_txq_t txq = context;
3127 if_ctx_t ctx = txq->ift_ctx;
3129 #ifdef IFLIB_DIAGNOSTICS
3130 txq->ift_cpu_exec_count[curcpu]++;
3132 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3134 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE);
3138 _task_fn_rx(void *context)
3140 iflib_rxq_t rxq = context;
3141 if_ctx_t ctx = rxq->ifr_ctx;
3145 #ifdef IFLIB_DIAGNOSTICS
3146 rxq->ifr_cpu_exec_count[curcpu]++;
3148 DBG_COUNTER_INC(task_fn_rxs);
3149 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3152 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) {
3153 if (ctx->ifc_flags & IFC_LEGACY)
3154 IFDI_INTR_ENABLE(ctx);
3156 DBG_COUNTER_INC(rx_intr_enables);
3157 rc = IFDI_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3158 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3161 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3164 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3168 _task_fn_admin(void *context)
3170 if_ctx_t ctx = context;
3171 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3175 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3179 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3181 callout_stop(&txq->ift_timer);
3182 CALLOUT_UNLOCK(txq);
3184 IFDI_UPDATE_ADMIN_STATUS(ctx);
3185 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3186 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3187 IFDI_LINK_INTR_ENABLE(ctx);
3190 if (LINK_ACTIVE(ctx) == 0)
3192 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3193 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3198 _task_fn_iov(void *context)
3200 if_ctx_t ctx = context;
3202 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3206 IFDI_VFLR_HANDLE(ctx);
3211 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3214 if_int_delay_info_t info;
3217 info = (if_int_delay_info_t)arg1;
3218 ctx = info->iidi_ctx;
3219 info->iidi_req = req;
3220 info->iidi_oidp = oidp;
3222 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3227 /*********************************************************************
3231 **********************************************************************/
3234 iflib_if_init_locked(if_ctx_t ctx)
3237 iflib_init_locked(ctx);
3242 iflib_if_init(void *arg)
3247 iflib_if_init_locked(ctx);
3252 iflib_if_transmit(if_t ifp, struct mbuf *m)
3254 if_ctx_t ctx = if_getsoftc(ifp);
3259 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3260 DBG_COUNTER_INC(tx_frees);
3265 MPASS(m->m_nextpkt == NULL);
3267 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3268 qidx = QIDX(ctx, m);
3270 * XXX calculate buf_ring based on flowid (divvy up bits?)
3272 txq = &ctx->ifc_txqs[qidx];
3274 #ifdef DRIVER_BACKPRESSURE
3275 if (txq->ift_closed) {
3277 next = m->m_nextpkt;
3278 m->m_nextpkt = NULL;
3291 next = next->m_nextpkt;
3292 } while (next != NULL);
3294 if (count > nitems(marr))
3295 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3296 /* XXX check nextpkt */
3298 /* XXX simplify for now */
3299 DBG_COUNTER_INC(tx_frees);
3302 for (next = m, i = 0; next != NULL; i++) {
3304 next = next->m_nextpkt;
3305 mp[i]->m_nextpkt = NULL;
3308 DBG_COUNTER_INC(tx_seen);
3309 err = ifmp_ring_enqueue(txq->ift_br[0], (void **)&m, 1, TX_BATCH_SIZE);
3312 GROUPTASK_ENQUEUE(&txq->ift_task);
3313 /* support forthcoming later */
3314 #ifdef DRIVER_BACKPRESSURE
3315 txq->ift_closed = TRUE;
3317 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE);
3319 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) {
3320 GROUPTASK_ENQUEUE(&txq->ift_task);
3327 iflib_if_qflush(if_t ifp)
3329 if_ctx_t ctx = if_getsoftc(ifp);
3330 iflib_txq_t txq = ctx->ifc_txqs;
3334 ctx->ifc_flags |= IFC_QFLUSH;
3336 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3337 while (!(ifmp_ring_is_idle(txq->ift_br[0]) || ifmp_ring_is_stalled(txq->ift_br[0])))
3338 iflib_txq_check_drain(txq, 0);
3340 ctx->ifc_flags &= ~IFC_QFLUSH;
3347 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3348 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \
3349 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3352 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3354 if_ctx_t ctx = if_getsoftc(ifp);
3355 struct ifreq *ifr = (struct ifreq *)data;
3356 #if defined(INET) || defined(INET6)
3357 struct ifaddr *ifa = (struct ifaddr *)data;
3359 bool avoid_reset = FALSE;
3360 int err = 0, reinit = 0, bits;
3365 if (ifa->ifa_addr->sa_family == AF_INET)
3369 if (ifa->ifa_addr->sa_family == AF_INET6)
3373 ** Calling init results in link renegotiation,
3374 ** so we avoid doing it when possible.
3377 if_setflagbits(ifp, IFF_UP,0);
3378 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3381 if (!(if_getflags(ifp) & IFF_NOARP))
3382 arp_ifinit(ifp, ifa);
3385 err = ether_ioctl(ifp, command, data);
3389 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3393 bits = if_getdrvflags(ifp);
3394 /* stop the driver and free any clusters before proceeding */
3397 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3398 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3399 ctx->ifc_flags |= IFC_MULTISEG;
3401 ctx->ifc_flags &= ~IFC_MULTISEG;
3402 err = if_setmtu(ifp, ifr->ifr_mtu);
3404 iflib_init_locked(ctx);
3405 if_setdrvflags(ifp, bits);
3410 if (if_getflags(ifp) & IFF_UP) {
3411 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3412 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3413 (IFF_PROMISC | IFF_ALLMULTI)) {
3414 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3418 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3421 ctx->ifc_if_flags = if_getflags(ifp);
3426 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3428 IFDI_INTR_DISABLE(ctx);
3429 IFDI_MULTI_SET(ctx);
3430 IFDI_INTR_ENABLE(ctx);
3436 IFDI_MEDIA_SET(ctx);
3440 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3444 struct ifi2creq i2c;
3446 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3449 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3453 if (i2c.len > sizeof(i2c.data)) {
3458 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3459 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3466 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3469 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3471 setmask |= (mask & IFCAP_FLAGS);
3473 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
3474 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
3475 if ((mask & IFCAP_WOL) &&
3476 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3477 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3480 * want to ensure that traffic has stopped before we change any of the flags
3484 bits = if_getdrvflags(ifp);
3485 if (bits & IFF_DRV_RUNNING)
3487 if_togglecapenable(ifp, setmask);
3488 if (bits & IFF_DRV_RUNNING)
3489 iflib_init_locked(ctx);
3490 if_setdrvflags(ifp, bits);
3495 case SIOCGPRIVATE_0:
3499 err = IFDI_PRIV_IOCTL(ctx, command, data);
3503 err = ether_ioctl(ifp, command, data);
3512 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3514 if_ctx_t ctx = if_getsoftc(ifp);
3516 return (IFDI_GET_COUNTER(ctx, cnt));
3519 /*********************************************************************
3521 * OTHER FUNCTIONS EXPORTED TO THE STACK
3523 **********************************************************************/
3526 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
3528 if_ctx_t ctx = if_getsoftc(ifp);
3530 if ((void *)ctx != arg)
3533 if ((vtag == 0) || (vtag > 4095))
3537 IFDI_VLAN_REGISTER(ctx, vtag);
3538 /* Re-init to load the changes */
3539 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3540 iflib_init_locked(ctx);
3545 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
3547 if_ctx_t ctx = if_getsoftc(ifp);
3549 if ((void *)ctx != arg)
3552 if ((vtag == 0) || (vtag > 4095))
3556 IFDI_VLAN_UNREGISTER(ctx, vtag);
3557 /* Re-init to load the changes */
3558 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3559 iflib_init_locked(ctx);
3564 iflib_led_func(void *arg, int onoff)
3569 IFDI_LED_FUNC(ctx, onoff);
3573 /*********************************************************************
3575 * BUS FUNCTION DEFINITIONS
3577 **********************************************************************/
3580 iflib_device_probe(device_t dev)
3582 pci_vendor_info_t *ent;
3584 uint16_t pci_vendor_id, pci_device_id;
3585 uint16_t pci_subvendor_id, pci_subdevice_id;
3586 uint16_t pci_rev_id;
3587 if_shared_ctx_t sctx;
3589 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3592 pci_vendor_id = pci_get_vendor(dev);
3593 pci_device_id = pci_get_device(dev);
3594 pci_subvendor_id = pci_get_subvendor(dev);
3595 pci_subdevice_id = pci_get_subdevice(dev);
3596 pci_rev_id = pci_get_revid(dev);
3597 if (sctx->isc_parse_devinfo != NULL)
3598 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
3600 ent = sctx->isc_vendor_info;
3601 while (ent->pvi_vendor_id != 0) {
3602 if (pci_vendor_id != ent->pvi_vendor_id) {
3606 if ((pci_device_id == ent->pvi_device_id) &&
3607 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
3608 (ent->pvi_subvendor_id == 0)) &&
3609 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
3610 (ent->pvi_subdevice_id == 0)) &&
3611 ((pci_rev_id == ent->pvi_rev_id) ||
3612 (ent->pvi_rev_id == 0))) {
3614 device_set_desc_copy(dev, ent->pvi_name);
3615 /* this needs to be changed to zero if the bus probing code
3616 * ever stops re-probing on best match because the sctx
3617 * may have its values over written by register calls
3618 * in subsequent probes
3620 return (BUS_PROBE_DEFAULT);
3628 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
3630 int err, rid, msix, msix_bar;
3633 if_softc_ctx_t scctx;
3639 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
3642 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
3643 device_set_softc(dev, ctx);
3644 ctx->ifc_flags |= IFC_SC_ALLOCATED;
3647 ctx->ifc_sctx = sctx;
3649 ctx->ifc_softc = sc;
3651 if ((err = iflib_register(ctx)) != 0) {
3652 device_printf(dev, "iflib_register failed %d\n", err);
3655 iflib_add_device_sysctl_pre(ctx);
3657 scctx = &ctx->ifc_softc_ctx;
3661 * XXX sanity check that ntxd & nrxd are a power of 2
3663 if (ctx->ifc_sysctl_ntxqs != 0)
3664 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
3665 if (ctx->ifc_sysctl_nrxqs != 0)
3666 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
3668 for (i = 0; i < sctx->isc_ntxqs; i++) {
3669 if (ctx->ifc_sysctl_ntxds[i] != 0)
3670 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
3672 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
3675 for (i = 0; i < sctx->isc_nrxqs; i++) {
3676 if (ctx->ifc_sysctl_nrxds[i] != 0)
3677 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
3679 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
3682 for (i = 0; i < sctx->isc_nrxqs; i++) {
3683 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
3684 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
3685 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
3686 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
3688 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
3689 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
3690 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
3691 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
3695 for (i = 0; i < sctx->isc_ntxqs; i++) {
3696 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
3697 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
3698 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
3699 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
3701 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
3702 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
3703 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
3704 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
3708 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
3709 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
3712 _iflib_pre_assert(scctx);
3713 ctx->ifc_txrx = *scctx->isc_txrx;
3716 MPASS(scctx->isc_capenable);
3717 if (scctx->isc_capenable & IFCAP_TXCSUM)
3718 MPASS(scctx->isc_tx_csum_flags);
3721 if_setcapabilities(ifp, scctx->isc_capenable);
3722 if_setcapenable(ifp, scctx->isc_capenable);
3724 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
3725 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
3726 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
3727 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
3730 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
3731 ctx->ifc_flags |= IFC_DMAR;
3734 msix_bar = scctx->isc_msix_bar;
3736 if(sctx->isc_flags & IFLIB_HAS_TXCQ)
3741 if(sctx->isc_flags & IFLIB_HAS_RXCQ)
3746 /* XXX change for per-queue sizes */
3747 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
3748 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
3749 for (i = 0; i < sctx->isc_nrxqs; i++) {
3750 if (!powerof2(scctx->isc_nrxd[i])) {
3751 /* round down instead? */
3752 device_printf(dev, "# rx descriptors must be a power of 2\n");
3757 for (i = 0; i < sctx->isc_ntxqs; i++) {
3758 if (!powerof2(scctx->isc_ntxd[i])) {
3760 "# tx descriptors must be a power of 2");
3766 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
3767 MAX_SINGLE_PACKET_FRACTION)
3768 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
3769 MAX_SINGLE_PACKET_FRACTION);
3770 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
3771 MAX_SINGLE_PACKET_FRACTION)
3772 scctx->isc_tx_tso_segments_max = max(1,
3773 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
3776 * Protect the stack against modern hardware
3778 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
3779 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
3781 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
3782 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
3783 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
3784 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
3785 if (scctx->isc_rss_table_size == 0)
3786 scctx->isc_rss_table_size = 64;
3787 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
3789 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
3790 /* XXX format name */
3791 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
3793 ** Now setup MSI or MSI/X, should
3794 ** return us the number of supported
3795 ** vectors. (Will be 1 for MSI)
3797 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
3798 msix = scctx->isc_vectors;
3799 } else if (scctx->isc_msix_bar != 0)
3801 * The simple fact that isc_msix_bar is not 0 does not mean we
3802 * we have a good value there that is known to work.
3804 msix = iflib_msix_init(ctx);
3806 scctx->isc_vectors = 1;
3807 scctx->isc_ntxqsets = 1;
3808 scctx->isc_nrxqsets = 1;
3809 scctx->isc_intr = IFLIB_INTR_LEGACY;
3812 /* Get memory for the station queues */
3813 if ((err = iflib_queues_alloc(ctx))) {
3814 device_printf(dev, "Unable to allocate queue memory\n");
3818 if ((err = iflib_qset_structures_setup(ctx))) {
3819 device_printf(dev, "qset structure setup failed %d\n", err);
3824 * Group taskqueues aren't properly set up until SMP is started,
3825 * so we disable interrupts until we can handle them post
3828 * XXX: disabling interrupts doesn't actually work, at least for
3829 * the non-MSI case. When they occur before SI_SUB_SMP completes,
3830 * we do null handling and depend on this not causing too large an
3833 IFDI_INTR_DISABLE(ctx);
3834 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
3835 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
3836 goto fail_intr_free;
3840 if (scctx->isc_intr == IFLIB_INTR_MSI) {
3844 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
3845 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
3846 goto fail_intr_free;
3849 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
3850 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
3851 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
3854 if ((err = iflib_netmap_attach(ctx))) {
3855 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
3860 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
3861 iflib_add_device_sysctl_post(ctx);
3862 ctx->ifc_flags |= IFC_INIT_DONE;
3865 ether_ifdetach(ctx->ifc_ifp);
3867 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
3868 pci_release_msi(ctx->ifc_dev);
3870 /* XXX free queues */
3877 iflib_device_attach(device_t dev)
3880 if_shared_ctx_t sctx;
3882 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3885 pci_enable_busmaster(dev);
3887 return (iflib_device_register(dev, NULL, sctx, &ctx));
3891 iflib_device_deregister(if_ctx_t ctx)
3893 if_t ifp = ctx->ifc_ifp;
3896 device_t dev = ctx->ifc_dev;
3898 struct taskqgroup *tqg;
3900 /* Make sure VLANS are not using driver */
3901 if (if_vlantrunkinuse(ifp)) {
3902 device_printf(dev,"Vlan in use, detach first\n");
3907 ctx->ifc_in_detach = 1;
3911 /* Unregister VLAN events */
3912 if (ctx->ifc_vlan_attach_event != NULL)
3913 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
3914 if (ctx->ifc_vlan_detach_event != NULL)
3915 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
3917 iflib_netmap_detach(ifp);
3918 ether_ifdetach(ifp);
3919 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
3920 CTX_LOCK_DESTROY(ctx);
3921 if (ctx->ifc_led_dev != NULL)
3922 led_destroy(ctx->ifc_led_dev);
3923 /* XXX drain any dependent tasks */
3924 tqg = qgroup_softirq;
3925 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
3926 callout_drain(&txq->ift_timer);
3927 callout_drain(&txq->ift_db_check);
3928 if (txq->ift_task.gt_uniq != NULL)
3929 taskqgroup_detach(tqg, &txq->ift_task);
3931 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
3932 if (rxq->ifr_task.gt_uniq != NULL)
3933 taskqgroup_detach(tqg, &rxq->ifr_task);
3935 tqg = qgroup_if_config_tqg;
3936 if (ctx->ifc_admin_task.gt_uniq != NULL)
3937 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
3938 if (ctx->ifc_vflr_task.gt_uniq != NULL)
3939 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
3942 device_set_softc(ctx->ifc_dev, NULL);
3943 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
3944 pci_release_msi(dev);
3946 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
3947 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
3949 if (ctx->ifc_msix_mem != NULL) {
3950 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
3951 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
3952 ctx->ifc_msix_mem = NULL;
3955 bus_generic_detach(dev);
3958 iflib_tx_structures_free(ctx);
3959 iflib_rx_structures_free(ctx);
3960 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
3961 free(ctx->ifc_softc, M_IFLIB);
3968 iflib_device_detach(device_t dev)
3970 if_ctx_t ctx = device_get_softc(dev);
3972 return (iflib_device_deregister(ctx));
3976 iflib_device_suspend(device_t dev)
3978 if_ctx_t ctx = device_get_softc(dev);
3984 return bus_generic_suspend(dev);
3987 iflib_device_shutdown(device_t dev)
3989 if_ctx_t ctx = device_get_softc(dev);
3995 return bus_generic_suspend(dev);
4000 iflib_device_resume(device_t dev)
4002 if_ctx_t ctx = device_get_softc(dev);
4003 iflib_txq_t txq = ctx->ifc_txqs;
4007 iflib_init_locked(ctx);
4009 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4010 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4012 return (bus_generic_resume(dev));
4016 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4019 if_ctx_t ctx = device_get_softc(dev);
4022 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4029 iflib_device_iov_uninit(device_t dev)
4031 if_ctx_t ctx = device_get_softc(dev);
4034 IFDI_IOV_UNINIT(ctx);
4039 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4042 if_ctx_t ctx = device_get_softc(dev);
4045 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4051 /*********************************************************************
4053 * MODULE FUNCTION DEFINITIONS
4055 **********************************************************************/
4058 * - Start a fast taskqueue thread for each core
4059 * - Start a taskqueue for control operations
4062 iflib_module_init(void)
4068 iflib_module_event_handler(module_t mod, int what, void *arg)
4074 if ((err = iflib_module_init()) != 0)
4080 return (EOPNOTSUPP);
4086 /*********************************************************************
4088 * PUBLIC FUNCTION DEFINITIONS
4089 * ordered as in iflib.h
4091 **********************************************************************/
4095 _iflib_assert(if_shared_ctx_t sctx)
4097 MPASS(sctx->isc_tx_maxsize);
4098 MPASS(sctx->isc_tx_maxsegsize);
4100 MPASS(sctx->isc_rx_maxsize);
4101 MPASS(sctx->isc_rx_nsegments);
4102 MPASS(sctx->isc_rx_maxsegsize);
4104 MPASS(sctx->isc_nrxd_min[0]);
4105 MPASS(sctx->isc_nrxd_max[0]);
4106 MPASS(sctx->isc_nrxd_default[0]);
4107 MPASS(sctx->isc_ntxd_min[0]);
4108 MPASS(sctx->isc_ntxd_max[0]);
4109 MPASS(sctx->isc_ntxd_default[0]);
4113 _iflib_pre_assert(if_softc_ctx_t scctx)
4116 MPASS(scctx->isc_txrx->ift_txd_encap);
4117 MPASS(scctx->isc_txrx->ift_txd_flush);
4118 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4119 MPASS(scctx->isc_txrx->ift_rxd_available);
4120 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4121 MPASS(scctx->isc_txrx->ift_rxd_refill);
4122 MPASS(scctx->isc_txrx->ift_rxd_flush);
4126 iflib_register(if_ctx_t ctx)
4128 if_shared_ctx_t sctx = ctx->ifc_sctx;
4129 driver_t *driver = sctx->isc_driver;
4130 device_t dev = ctx->ifc_dev;
4133 _iflib_assert(sctx);
4135 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4137 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4139 device_printf(dev, "can not allocate ifnet structure\n");
4144 * Initialize our context's device specific methods
4146 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4147 kobj_class_compile((kobj_class_t) driver);
4150 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4151 if_setsoftc(ifp, ctx);
4152 if_setdev(ifp, dev);
4153 if_setinitfn(ifp, iflib_if_init);
4154 if_setioctlfn(ifp, iflib_if_ioctl);
4155 if_settransmitfn(ifp, iflib_if_transmit);
4156 if_setqflushfn(ifp, iflib_if_qflush);
4157 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4159 ctx->ifc_vlan_attach_event =
4160 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4161 EVENTHANDLER_PRI_FIRST);
4162 ctx->ifc_vlan_detach_event =
4163 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4164 EVENTHANDLER_PRI_FIRST);
4166 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4167 iflib_media_change, iflib_media_status);
4174 iflib_queues_alloc(if_ctx_t ctx)
4176 if_shared_ctx_t sctx = ctx->ifc_sctx;
4177 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4178 device_t dev = ctx->ifc_dev;
4179 int nrxqsets = scctx->isc_nrxqsets;
4180 int ntxqsets = scctx->isc_ntxqsets;
4183 iflib_fl_t fl = NULL;
4184 int i, j, cpu, err, txconf, rxconf;
4185 iflib_dma_info_t ifdip;
4186 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4187 uint32_t *txqsizes = scctx->isc_txqsizes;
4188 uint8_t nrxqs = sctx->isc_nrxqs;
4189 uint8_t ntxqs = sctx->isc_ntxqs;
4190 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4193 struct ifmp_ring **brscp;
4194 int nbuf_rings = 1; /* XXX determine dynamically */
4196 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4197 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4203 /* Allocate the TX ring struct memory */
4205 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4206 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4207 device_printf(dev, "Unable to allocate TX ring memory\n");
4212 /* Now allocate the RX */
4214 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4215 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4216 device_printf(dev, "Unable to allocate RX ring memory\n");
4220 if (!(brscp = malloc(sizeof(void *) * nbuf_rings * nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4221 device_printf(dev, "Unable to buf_ring_sc * memory\n");
4226 ctx->ifc_txqs = txq;
4227 ctx->ifc_rxqs = rxq;
4230 * XXX handle allocation failure
4232 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4233 /* Set up some basics */
4235 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4236 device_printf(dev, "failed to allocate iflib_dma_info\n");
4240 txq->ift_ifdi = ifdip;
4241 for (j = 0; j < ntxqs; j++, ifdip++) {
4242 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4243 device_printf(dev, "Unable to allocate Descriptor memory\n");
4247 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4251 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4252 txq->ift_br_offset = 1;
4254 txq->ift_br_offset = 0;
4257 txq->ift_timer.c_cpu = cpu;
4258 txq->ift_db_check.c_cpu = cpu;
4259 txq->ift_nbr = nbuf_rings;
4261 if (iflib_txsd_alloc(txq)) {
4262 device_printf(dev, "Critical Failure setting up TX buffers\n");
4267 /* Initialize the TX lock */
4268 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4269 device_get_nameunit(dev), txq->ift_id);
4270 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4271 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4272 callout_init_mtx(&txq->ift_db_check, &txq->ift_mtx, 0);
4274 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4275 device_get_nameunit(dev), txq->ift_id);
4276 TXDB_LOCK_INIT(txq);
4278 txq->ift_br = brscp + i*nbuf_rings;
4279 for (j = 0; j < nbuf_rings; j++) {
4280 err = ifmp_ring_alloc(&txq->ift_br[j], 2048, txq, iflib_txq_drain,
4281 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4283 /* XXX free any allocated rings */
4284 device_printf(dev, "Unable to allocate buf_ring\n");
4290 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4291 /* Set up some basics */
4293 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4294 device_printf(dev, "failed to allocate iflib_dma_info\n");
4299 rxq->ifr_ifdi = ifdip;
4300 for (j = 0; j < nrxqs; j++, ifdip++) {
4301 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4302 device_printf(dev, "Unable to allocate Descriptor memory\n");
4306 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4310 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4311 rxq->ifr_fl_offset = 1;
4313 rxq->ifr_fl_offset = 0;
4315 rxq->ifr_nfl = nfree_lists;
4317 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4318 device_printf(dev, "Unable to allocate free list memory\n");
4323 for (j = 0; j < nfree_lists; j++) {
4324 rxq->ifr_fl[j].ifl_rxq = rxq;
4325 rxq->ifr_fl[j].ifl_id = j;
4326 rxq->ifr_fl[j].ifl_ifdi =
4327 &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4329 /* Allocate receive buffers for the ring*/
4330 if (iflib_rxsd_alloc(rxq)) {
4332 "Critical Failure setting up receive buffers\n");
4339 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4340 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4341 for (i = 0; i < ntxqsets; i++) {
4342 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4344 for (j = 0; j < ntxqs; j++, di++) {
4345 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4346 paddrs[i*ntxqs + j] = di->idi_paddr;
4349 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4350 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4351 iflib_tx_structures_free(ctx);
4352 free(vaddrs, M_IFLIB);
4353 free(paddrs, M_IFLIB);
4356 free(vaddrs, M_IFLIB);
4357 free(paddrs, M_IFLIB);
4360 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4361 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4362 for (i = 0; i < nrxqsets; i++) {
4363 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4365 for (j = 0; j < nrxqs; j++, di++) {
4366 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4367 paddrs[i*nrxqs + j] = di->idi_paddr;
4370 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4371 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4372 iflib_tx_structures_free(ctx);
4373 free(vaddrs, M_IFLIB);
4374 free(paddrs, M_IFLIB);
4377 free(vaddrs, M_IFLIB);
4378 free(paddrs, M_IFLIB);
4382 /* XXX handle allocation failure changes */
4385 if (ctx->ifc_rxqs != NULL)
4386 free(ctx->ifc_rxqs, M_IFLIB);
4387 ctx->ifc_rxqs = NULL;
4388 if (ctx->ifc_txqs != NULL)
4389 free(ctx->ifc_txqs, M_IFLIB);
4390 ctx->ifc_txqs = NULL;
4393 free(brscp, M_IFLIB);
4403 iflib_tx_structures_setup(if_ctx_t ctx)
4405 iflib_txq_t txq = ctx->ifc_txqs;
4408 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4409 iflib_txq_setup(txq);
4415 iflib_tx_structures_free(if_ctx_t ctx)
4417 iflib_txq_t txq = ctx->ifc_txqs;
4420 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4421 iflib_txq_destroy(txq);
4422 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4423 iflib_dma_free(&txq->ift_ifdi[j]);
4425 free(ctx->ifc_txqs, M_IFLIB);
4426 ctx->ifc_txqs = NULL;
4427 IFDI_QUEUES_FREE(ctx);
4430 /*********************************************************************
4432 * Initialize all receive rings.
4434 **********************************************************************/
4436 iflib_rx_structures_setup(if_ctx_t ctx)
4438 iflib_rxq_t rxq = ctx->ifc_rxqs;
4440 #if defined(INET6) || defined(INET)
4444 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4445 #if defined(INET6) || defined(INET)
4446 tcp_lro_free(&rxq->ifr_lc);
4447 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4448 TCP_LRO_ENTRIES, min(1024,
4449 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4450 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4453 rxq->ifr_lro_enabled = TRUE;
4455 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4458 #if defined(INET6) || defined(INET)
4461 * Free RX software descriptors allocated so far, we will only handle
4462 * the rings that completed, the failing case will have
4463 * cleaned up for itself. 'q' failed, so its the terminus.
4465 rxq = ctx->ifc_rxqs;
4466 for (i = 0; i < q; ++i, rxq++) {
4467 iflib_rx_sds_free(rxq);
4468 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4474 /*********************************************************************
4476 * Free all receive rings.
4478 **********************************************************************/
4480 iflib_rx_structures_free(if_ctx_t ctx)
4482 iflib_rxq_t rxq = ctx->ifc_rxqs;
4484 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4485 iflib_rx_sds_free(rxq);
4490 iflib_qset_structures_setup(if_ctx_t ctx)
4494 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4497 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4498 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4499 iflib_tx_structures_free(ctx);
4500 iflib_rx_structures_free(ctx);
4506 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4507 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4510 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4514 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4516 int i, cpuid, eqid, count;
4518 CPU_COPY(&ctx->ifc_cpus, cpus);
4519 count = CPU_COUNT(&ctx->ifc_cpus);
4521 /* clear up to the qid'th bit */
4522 for (i = 0; i < eqid; i++) {
4523 cpuid = CPU_FFS(cpus);
4525 CPU_CLR(cpuid-1, cpus);
4527 cpuid = CPU_FFS(cpus);
4533 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
4534 iflib_intr_type_t type, driver_filter_t *filter,
4535 void *filter_arg, int qid, char *name)
4537 struct grouptask *gtask;
4538 struct taskqgroup *tqg;
4539 iflib_filter_info_t info;
4542 int tqrid, err, cpuid;
4545 info = &ctx->ifc_filter_info;
4549 /* XXX merge tx/rx for netmap? */
4551 q = &ctx->ifc_txqs[qid];
4552 info = &ctx->ifc_txqs[qid].ift_filter_info;
4553 gtask = &ctx->ifc_txqs[qid].ift_task;
4554 tqg = qgroup_softirq;
4556 GROUPTASK_INIT(gtask, 0, fn, q);
4559 q = &ctx->ifc_rxqs[qid];
4560 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4561 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4562 tqg = qgroup_softirq;
4564 GROUPTASK_INIT(gtask, 0, fn, q);
4566 case IFLIB_INTR_ADMIN:
4569 info = &ctx->ifc_filter_info;
4570 gtask = &ctx->ifc_admin_task;
4571 tqg = qgroup_if_config_tqg;
4572 fn = _task_fn_admin;
4575 panic("unknown net intr type");
4578 info->ifi_filter = filter;
4579 info->ifi_filter_arg = filter_arg;
4580 info->ifi_task = gtask;
4581 info->ifi_ctx = ctx;
4583 err = _iflib_irq_alloc(ctx, irq, rid, iflib_fast_intr, NULL, info, name);
4585 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
4588 if (type == IFLIB_INTR_ADMIN)
4592 cpuid = find_nth(ctx, &cpus, qid);
4593 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name);
4595 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4602 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name)
4604 struct grouptask *gtask;
4605 struct taskqgroup *tqg;
4611 q = &ctx->ifc_txqs[qid];
4612 gtask = &ctx->ifc_txqs[qid].ift_task;
4613 tqg = qgroup_softirq;
4617 q = &ctx->ifc_rxqs[qid];
4618 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4619 tqg = qgroup_softirq;
4622 case IFLIB_INTR_IOV:
4624 gtask = &ctx->ifc_vflr_task;
4625 tqg = qgroup_if_config_tqg;
4630 panic("unknown net intr type");
4632 GROUPTASK_INIT(gtask, 0, fn, q);
4633 taskqgroup_attach(tqg, gtask, q, rid, name);
4637 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
4640 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
4643 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
4647 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
4649 iflib_txq_t txq = ctx->ifc_txqs;
4650 iflib_rxq_t rxq = ctx->ifc_rxqs;
4651 if_irq_t irq = &ctx->ifc_legacy_irq;
4652 iflib_filter_info_t info;
4653 struct grouptask *gtask;
4654 struct taskqgroup *tqg;
4660 q = &ctx->ifc_rxqs[0];
4661 info = &rxq[0].ifr_filter_info;
4662 gtask = &rxq[0].ifr_task;
4663 tqg = qgroup_softirq;
4664 tqrid = irq->ii_rid = *rid;
4667 ctx->ifc_flags |= IFC_LEGACY;
4668 info->ifi_filter = filter;
4669 info->ifi_filter_arg = filter_arg;
4670 info->ifi_task = gtask;
4671 info->ifi_ctx = ctx;
4673 /* We allocate a single interrupt resource */
4674 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr, NULL, info, name)) != 0)
4676 GROUPTASK_INIT(gtask, 0, fn, q);
4677 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4679 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
4680 taskqgroup_attach(qgroup_softirq, &txq->ift_task, txq, tqrid, "tx");
4685 iflib_led_create(if_ctx_t ctx)
4688 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
4689 device_get_nameunit(ctx->ifc_dev));
4693 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
4696 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
4700 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
4703 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
4707 iflib_admin_intr_deferred(if_ctx_t ctx)
4710 struct grouptask *gtask;
4712 gtask = &ctx->ifc_admin_task;
4713 MPASS(gtask->gt_taskqueue != NULL);
4716 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
4720 iflib_iov_intr_deferred(if_ctx_t ctx)
4723 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
4727 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
4730 taskqgroup_attach_cpu(qgroup_softirq, gt, uniq, cpu, -1, name);
4734 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
4738 GROUPTASK_INIT(gtask, 0, fn, ctx);
4739 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
4743 iflib_config_gtask_deinit(struct grouptask *gtask)
4746 taskqgroup_detach(qgroup_if_config_tqg, gtask);
4750 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
4752 if_t ifp = ctx->ifc_ifp;
4753 iflib_txq_t txq = ctx->ifc_txqs;
4755 if_setbaudrate(ifp, baudrate);
4757 /* If link down, disable watchdog */
4758 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
4759 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
4760 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
4762 ctx->ifc_link_state = link_state;
4763 if_link_state_change(ifp, link_state);
4767 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
4771 int credits_pre = txq->ift_cidx_processed;
4774 if (ctx->isc_txd_credits_update == NULL)
4777 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, true)) == 0)
4780 txq->ift_processed += credits;
4781 txq->ift_cidx_processed += credits;
4783 MPASS(credits_pre + credits == txq->ift_cidx_processed);
4784 if (txq->ift_cidx_processed >= txq->ift_size)
4785 txq->ift_cidx_processed -= txq->ift_size;
4790 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget)
4793 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
4798 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
4799 const char *description, if_int_delay_info_t info,
4800 int offset, int value)
4802 info->iidi_ctx = ctx;
4803 info->iidi_offset = offset;
4804 info->iidi_value = value;
4805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
4806 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
4807 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4808 info, 0, iflib_sysctl_int_delay, "I", description);
4812 iflib_ctx_lock_get(if_ctx_t ctx)
4815 return (&ctx->ifc_mtx);
4819 iflib_msix_init(if_ctx_t ctx)
4821 device_t dev = ctx->ifc_dev;
4822 if_shared_ctx_t sctx = ctx->ifc_sctx;
4823 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4824 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
4825 int iflib_num_tx_queues, iflib_num_rx_queues;
4826 int err, admincnt, bar;
4828 iflib_num_tx_queues = scctx->isc_ntxqsets;
4829 iflib_num_rx_queues = scctx->isc_nrxqsets;
4831 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues);
4833 bar = ctx->ifc_softc_ctx.isc_msix_bar;
4834 admincnt = sctx->isc_admin_intrcnt;
4835 /* Override by tuneable */
4836 if (enable_msix == 0)
4840 ** When used in a virtualized environment
4841 ** PCI BUSMASTER capability may not be set
4842 ** so explicity set it here and rewrite
4843 ** the ENABLE in the MSIX control register
4844 ** at this point to cause the host to
4845 ** successfully initialize us.
4850 pci_enable_busmaster(dev);
4852 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
4853 rid += PCIR_MSIX_CTRL;
4854 msix_ctrl = pci_read_config(dev, rid, 2);
4855 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
4856 pci_write_config(dev, rid, msix_ctrl, 2);
4858 device_printf(dev, "PCIY_MSIX capability not found; "
4859 "or rid %d == 0.\n", rid);
4865 * bar == -1 => "trust me I know what I'm doing"
4866 * https://www.youtube.com/watch?v=nnwWKkNau4I
4867 * Some drivers are for hardware that is so shoddily
4868 * documented that no one knows which bars are which
4869 * so the developer has to map all bars. This hack
4870 * allows shoddy garbage to use msix in this framework.
4873 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
4874 SYS_RES_MEMORY, &bar, RF_ACTIVE);
4875 if (ctx->ifc_msix_mem == NULL) {
4876 /* May not be enabled */
4877 device_printf(dev, "Unable to map MSIX table \n");
4881 /* First try MSI/X */
4882 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
4883 device_printf(dev, "System has MSIX disabled \n");
4884 bus_release_resource(dev, SYS_RES_MEMORY,
4885 bar, ctx->ifc_msix_mem);
4886 ctx->ifc_msix_mem = NULL;
4890 /* use only 1 qset in debug mode */
4891 queuemsgs = min(msgs - admincnt, 1);
4893 queuemsgs = msgs - admincnt;
4895 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
4897 queues = imin(queuemsgs, rss_getnumbuckets());
4901 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
4902 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
4903 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
4905 device_printf(dev, "Unable to fetch CPU list\n");
4906 /* Figure out a reasonable auto config value */
4907 queues = min(queuemsgs, mp_ncpus);
4910 /* If we're doing RSS, clamp at the number of RSS buckets */
4911 if (queues > rss_getnumbuckets())
4912 queues = rss_getnumbuckets();
4914 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
4915 rx_queues = iflib_num_rx_queues;
4919 * We want this to be all logical CPUs by default
4921 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
4922 tx_queues = iflib_num_tx_queues;
4924 tx_queues = mp_ncpus;
4926 if (ctx->ifc_sysctl_qs_eq_override == 0) {
4928 if (tx_queues != rx_queues)
4929 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
4930 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
4932 tx_queues = min(rx_queues, tx_queues);
4933 rx_queues = min(rx_queues, tx_queues);
4936 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
4938 vectors = rx_queues + admincnt;
4939 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
4941 "Using MSIX interrupts with %d vectors\n", vectors);
4942 scctx->isc_vectors = vectors;
4943 scctx->isc_nrxqsets = rx_queues;
4944 scctx->isc_ntxqsets = tx_queues;
4945 scctx->isc_intr = IFLIB_INTR_MSIX;
4949 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
4952 vectors = pci_msi_count(dev);
4953 scctx->isc_nrxqsets = 1;
4954 scctx->isc_ntxqsets = 1;
4955 scctx->isc_vectors = vectors;
4956 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
4957 device_printf(dev,"Using an MSI interrupt\n");
4958 scctx->isc_intr = IFLIB_INTR_MSI;
4960 device_printf(dev,"Using a Legacy interrupt\n");
4961 scctx->isc_intr = IFLIB_INTR_LEGACY;
4967 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
4970 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
4973 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
4975 char *ring_state = "UNKNOWN";
4978 rc = sysctl_wire_old_buffer(req, 0);
4982 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
4987 ring_state = ring_states[state[3]];
4989 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
4990 state[0], state[1], state[2], ring_state);
4991 rc = sbuf_finish(sb);
4996 enum iflib_ndesc_handler {
5002 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5004 if_ctx_t ctx = (void *)arg1;
5005 enum iflib_ndesc_handler type = arg2;
5006 char buf[256] = {0};
5011 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5015 case IFLIB_NTXD_HANDLER:
5016 ndesc = ctx->ifc_sysctl_ntxds;
5018 nqs = ctx->ifc_sctx->isc_ntxqs;
5020 case IFLIB_NRXD_HANDLER:
5021 ndesc = ctx->ifc_sysctl_nrxds;
5023 nqs = ctx->ifc_sctx->isc_nrxqs;
5029 for (i=0; i<8; i++) {
5034 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5037 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5038 if (rc || req->newptr == NULL)
5041 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5042 i++, p = strsep(&next, " ,")) {
5043 ndesc[i] = strtoul(p, NULL, 10);
5049 #define NAME_BUFLEN 32
5051 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5053 device_t dev = iflib_get_dev(ctx);
5054 struct sysctl_oid_list *child, *oid_list;
5055 struct sysctl_ctx_list *ctx_list;
5056 struct sysctl_oid *node;
5058 ctx_list = device_get_sysctl_ctx(dev);
5059 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5060 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5061 CTLFLAG_RD, NULL, "IFLIB fields");
5062 oid_list = SYSCTL_CHILDREN(node);
5064 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5065 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5068 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5069 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5070 "# of txqs to use, 0 => use default #");
5071 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5072 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5073 "# of rxqs to use, 0 => use default #");
5074 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5075 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5076 "permit #txq != #rxq");
5078 /* XXX change for per-queue sizes */
5079 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5080 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5081 mp_ndesc_handler, "A",
5082 "list of # of tx descriptors to use, 0 = use default #");
5083 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5084 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5085 mp_ndesc_handler, "A",
5086 "list of # of rx descriptors to use, 0 = use default #");
5090 iflib_add_device_sysctl_post(if_ctx_t ctx)
5092 if_shared_ctx_t sctx = ctx->ifc_sctx;
5093 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5094 device_t dev = iflib_get_dev(ctx);
5095 struct sysctl_oid_list *child;
5096 struct sysctl_ctx_list *ctx_list;
5101 char namebuf[NAME_BUFLEN];
5103 struct sysctl_oid *queue_node, *fl_node, *node;
5104 struct sysctl_oid_list *queue_list, *fl_list;
5105 ctx_list = device_get_sysctl_ctx(dev);
5107 node = ctx->ifc_sysctl_node;
5108 child = SYSCTL_CHILDREN(node);
5110 if (scctx->isc_ntxqsets > 100)
5112 else if (scctx->isc_ntxqsets > 10)
5116 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5117 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5118 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5119 CTLFLAG_RD, NULL, "Queue Name");
5120 queue_list = SYSCTL_CHILDREN(queue_node);
5122 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5124 &txq->ift_dequeued, "total mbufs freed");
5125 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5127 &txq->ift_enqueued, "total mbufs enqueued");
5129 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5131 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5132 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5134 &txq->ift_pullups, "# of times m_pullup was called");
5135 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5137 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5138 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5140 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5141 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5143 &txq->ift_map_failed, "# of times dma map failed");
5144 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5146 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5147 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5149 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5150 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5152 &txq->ift_pidx, 1, "Producer Index");
5153 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5155 &txq->ift_cidx, 1, "Consumer Index");
5156 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5158 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5159 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5161 &txq->ift_in_use, 1, "descriptors in use");
5162 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5164 &txq->ift_processed, "descriptors procesed for clean");
5165 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5167 &txq->ift_cleaned, "total cleaned");
5168 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5169 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br[0]->state),
5170 0, mp_ring_state_handler, "A", "soft ring state");
5171 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5172 CTLFLAG_RD, &txq->ift_br[0]->enqueues,
5173 "# of enqueues to the mp_ring for this queue");
5174 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5175 CTLFLAG_RD, &txq->ift_br[0]->drops,
5176 "# of drops in the mp_ring for this queue");
5177 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5178 CTLFLAG_RD, &txq->ift_br[0]->starts,
5179 "# of normal consumer starts in the mp_ring for this queue");
5180 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5181 CTLFLAG_RD, &txq->ift_br[0]->stalls,
5182 "# of consumer stalls in the mp_ring for this queue");
5183 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5184 CTLFLAG_RD, &txq->ift_br[0]->restarts,
5185 "# of consumer restarts in the mp_ring for this queue");
5186 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5187 CTLFLAG_RD, &txq->ift_br[0]->abdications,
5188 "# of consumer abdications in the mp_ring for this queue");
5191 if (scctx->isc_nrxqsets > 100)
5193 else if (scctx->isc_nrxqsets > 10)
5197 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5198 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5199 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5200 CTLFLAG_RD, NULL, "Queue Name");
5201 queue_list = SYSCTL_CHILDREN(queue_node);
5202 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5203 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5205 &rxq->ifr_cq_pidx, 1, "Producer Index");
5206 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5208 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5211 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5212 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5213 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5214 CTLFLAG_RD, NULL, "freelist Name");
5215 fl_list = SYSCTL_CHILDREN(fl_node);
5216 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5218 &fl->ifl_pidx, 1, "Producer Index");
5219 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5221 &fl->ifl_cidx, 1, "Consumer Index");
5222 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5224 &fl->ifl_credits, 1, "credits available");
5226 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5228 &fl->ifl_m_enqueued, "mbufs allocated");
5229 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5231 &fl->ifl_m_dequeued, "mbufs freed");
5232 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5234 &fl->ifl_cl_enqueued, "clusters allocated");
5235 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5237 &fl->ifl_cl_dequeued, "clusters freed");