2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 #define IFLIB_RXEOF_MORE (1U << 0)
132 #define IFLIB_RXEOF_EMPTY (2U << 0)
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
174 uint32_t ifc_rx_mbuf_sz;
177 int ifc_watchdog_events;
178 struct cdev *ifc_led_dev;
179 struct resource *ifc_msix_mem;
181 struct if_irq ifc_legacy_irq;
182 struct grouptask ifc_admin_task;
183 struct grouptask ifc_vflr_task;
184 struct iflib_filter_info ifc_filter_info;
185 struct ifmedia ifc_media;
186 struct ifmedia *ifc_mediap;
188 struct sysctl_oid *ifc_sysctl_node;
189 uint16_t ifc_sysctl_ntxqs;
190 uint16_t ifc_sysctl_nrxqs;
191 uint16_t ifc_sysctl_qs_eq_override;
192 uint16_t ifc_sysctl_rx_budget;
193 uint16_t ifc_sysctl_tx_abdicate;
194 uint16_t ifc_sysctl_core_offset;
195 #define CORE_OFFSET_UNSPECIFIED 0xffff
196 uint8_t ifc_sysctl_separate_txrx;
198 qidx_t ifc_sysctl_ntxds[8];
199 qidx_t ifc_sysctl_nrxds[8];
200 struct if_txrx ifc_txrx;
201 #define isc_txd_encap ifc_txrx.ift_txd_encap
202 #define isc_txd_flush ifc_txrx.ift_txd_flush
203 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
204 #define isc_rxd_available ifc_txrx.ift_rxd_available
205 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 struct ether_addr ifc_mac;
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (ctx->ifc_mediap);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 #define IFLIB_RX_COPY_THRESH 128
292 #define IFLIB_MAX_RX_REFRESH 32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC 16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
296 #define IFLIB_QUEUE_IDLE 0
297 #define IFLIB_QUEUE_HUNG 1
298 #define IFLIB_QUEUE_WORKING 2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR 4
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE 32
305 #define IFLIB_RESTART_BUDGET 8
307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
314 qidx_t ift_cidx_processed;
317 uint8_t ift_br_offset;
318 uint16_t ift_npending;
319 uint16_t ift_db_pending;
320 uint16_t ift_rs_pending;
322 uint8_t ift_txd_size[8];
323 uint64_t ift_processed;
324 uint64_t ift_cleaned;
325 uint64_t ift_cleaned_prev;
327 uint64_t ift_enqueued;
328 uint64_t ift_dequeued;
330 uint64_t ift_no_tx_dma_setup;
331 uint64_t ift_no_desc_avail;
332 uint64_t ift_mbuf_defrag_failed;
333 uint64_t ift_mbuf_defrag;
334 uint64_t ift_map_failed;
335 uint64_t ift_txd_encap_efbig;
336 uint64_t ift_pullups;
337 uint64_t ift_last_timer_tick;
340 struct mtx ift_db_mtx;
342 /* constant values */
344 struct ifmp_ring *ift_br;
345 struct grouptask ift_task;
348 struct callout ift_timer;
350 if_txsd_vec_t ift_sds;
353 uint8_t ift_update_freq;
354 struct iflib_filter_info ift_filter_info;
355 bus_dma_tag_t ift_buf_tag;
356 bus_dma_tag_t ift_tso_buf_tag;
357 iflib_dma_info_t ift_ifdi;
358 #define MTX_NAME_LEN 32
359 char ift_mtx_name[MTX_NAME_LEN];
360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 uint64_t ift_cpu_exec_count[256];
364 } __aligned(CACHE_LINE_SIZE);
371 uint8_t ifl_rxd_size;
373 uint64_t ifl_m_enqueued;
374 uint64_t ifl_m_dequeued;
375 uint64_t ifl_cl_enqueued;
376 uint64_t ifl_cl_dequeued;
379 bitstr_t *ifl_rx_bitmap;
383 uint16_t ifl_buf_size;
386 iflib_rxsd_array_t ifl_sds;
389 bus_dma_tag_t ifl_buf_tag;
390 iflib_dma_info_t ifl_ifdi;
391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
392 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
393 } __aligned(CACHE_LINE_SIZE);
396 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
402 else if (pidx < cidx)
403 used = size - cidx + pidx;
404 else if (gen == 0 && pidx == cidx)
406 else if (gen == 1 && pidx == cidx)
414 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
416 #define IDXDIFF(head, tail, wrap) \
417 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
423 struct pfil_head *pfil;
425 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
426 * the completion queue consumer index. Otherwise it's unused.
432 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
433 uint8_t ifr_fl_offset;
434 struct lro_ctrl ifr_lc;
435 struct grouptask ifr_task;
436 struct callout ifr_watchdog;
437 struct iflib_filter_info ifr_filter_info;
438 iflib_dma_info_t ifr_ifdi;
440 /* dynamically allocate if any drivers need a value substantially larger than this */
441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
442 #ifdef IFLIB_DIAGNOSTICS
443 uint64_t ifr_cpu_exec_count[256];
445 } __aligned(CACHE_LINE_SIZE);
447 typedef struct if_rxsd {
452 /* multiple of word size */
454 #define PKT_INFO_SIZE 6
455 #define RXD_INFO_SIZE 5
456 #define PKT_TYPE uint64_t
458 #define PKT_INFO_SIZE 11
459 #define RXD_INFO_SIZE 8
460 #define PKT_TYPE uint32_t
462 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
463 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
465 typedef struct if_pkt_info_pad {
466 PKT_TYPE pkt_val[PKT_INFO_SIZE];
467 } *if_pkt_info_pad_t;
468 typedef struct if_rxd_info_pad {
469 PKT_TYPE rxd_val[RXD_INFO_SIZE];
470 } *if_rxd_info_pad_t;
472 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
473 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
476 pkt_info_zero(if_pkt_info_t pi)
478 if_pkt_info_pad_t pi_pad;
480 pi_pad = (if_pkt_info_pad_t)pi;
481 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
482 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
484 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
485 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
489 static device_method_t iflib_pseudo_methods[] = {
490 DEVMETHOD(device_attach, noop_attach),
491 DEVMETHOD(device_detach, iflib_pseudo_detach),
495 driver_t iflib_pseudodriver = {
496 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
500 rxd_info_zero(if_rxd_info_t ri)
502 if_rxd_info_pad_t ri_pad;
505 ri_pad = (if_rxd_info_pad_t)ri;
506 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
507 ri_pad->rxd_val[i] = 0;
508 ri_pad->rxd_val[i+1] = 0;
509 ri_pad->rxd_val[i+2] = 0;
510 ri_pad->rxd_val[i+3] = 0;
513 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
518 * Only allow a single packet to take up most 1/nth of the tx ring
520 #define MAX_SINGLE_PACKET_FRACTION 12
521 #define IF_BAD_DMA (bus_addr_t)-1
523 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
525 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
526 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
527 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
528 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
530 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
531 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
532 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
533 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
539 iflib_set_detach(if_ctx_t ctx)
542 ctx->ifc_flags |= IFC_IN_DETACH;
546 /* Our boot-time initialization hook */
547 static int iflib_module_event_handler(module_t, int, void *);
549 static moduledata_t iflib_moduledata = {
551 iflib_module_event_handler,
555 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
556 MODULE_VERSION(iflib, 1);
558 MODULE_DEPEND(iflib, pci, 1, 1, 1);
559 MODULE_DEPEND(iflib, ether, 1, 1, 1);
561 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
562 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
564 #ifndef IFLIB_DEBUG_COUNTERS
566 #define IFLIB_DEBUG_COUNTERS 1
568 #define IFLIB_DEBUG_COUNTERS 0
569 #endif /* !INVARIANTS */
572 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
573 "iflib driver parameters");
576 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
578 static int iflib_min_tx_latency = 0;
579 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
580 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
581 static int iflib_no_tx_batch = 0;
582 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
583 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
585 #if IFLIB_DEBUG_COUNTERS
587 static int iflib_tx_seen;
588 static int iflib_tx_sent;
589 static int iflib_tx_encap;
590 static int iflib_rx_allocs;
591 static int iflib_fl_refills;
592 static int iflib_fl_refills_large;
593 static int iflib_tx_frees;
595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
596 &iflib_tx_seen, 0, "# TX mbufs seen");
597 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
598 &iflib_tx_sent, 0, "# TX mbufs sent");
599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
600 &iflib_tx_encap, 0, "# TX mbufs encapped");
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
602 &iflib_tx_frees, 0, "# TX frees");
603 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
604 &iflib_rx_allocs, 0, "# RX allocations");
605 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
606 &iflib_fl_refills, 0, "# refills");
607 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
608 &iflib_fl_refills_large, 0, "# large refills");
610 static int iflib_txq_drain_flushing;
611 static int iflib_txq_drain_oactive;
612 static int iflib_txq_drain_notready;
614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
615 &iflib_txq_drain_flushing, 0, "# drain flushes");
616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
617 &iflib_txq_drain_oactive, 0, "# drain oactives");
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
619 &iflib_txq_drain_notready, 0, "# drain notready");
621 static int iflib_encap_load_mbuf_fail;
622 static int iflib_encap_pad_mbuf_fail;
623 static int iflib_encap_txq_avail_fail;
624 static int iflib_encap_txd_encap_fail;
626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
627 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
629 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
631 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
633 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
635 static int iflib_task_fn_rxs;
636 static int iflib_rx_intr_enables;
637 static int iflib_fast_intrs;
638 static int iflib_rx_unavail;
639 static int iflib_rx_ctx_inactive;
640 static int iflib_rx_if_input;
641 static int iflib_rxd_flush;
643 static int iflib_verbose_debug;
645 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
646 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
647 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
648 &iflib_rx_intr_enables, 0, "# RX intr enables");
649 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
650 &iflib_fast_intrs, 0, "# fast_intr calls");
651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
652 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
654 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
656 &iflib_rx_if_input, 0, "# times rxeof called if_input");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
658 &iflib_rxd_flush, 0, "# times rxd_flush called");
659 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
660 &iflib_verbose_debug, 0, "enable verbose debugging");
662 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
664 iflib_debug_reset(void)
666 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
667 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
668 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
669 iflib_txq_drain_notready =
670 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
671 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
672 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
674 iflib_rx_ctx_inactive = iflib_rx_if_input =
679 #define DBG_COUNTER_INC(name)
680 static void iflib_debug_reset(void) {}
683 #define IFLIB_DEBUG 0
685 static void iflib_tx_structures_free(if_ctx_t ctx);
686 static void iflib_rx_structures_free(if_ctx_t ctx);
687 static int iflib_queues_alloc(if_ctx_t ctx);
688 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
689 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
690 static int iflib_qset_structures_setup(if_ctx_t ctx);
691 static int iflib_msix_init(if_ctx_t ctx);
692 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
693 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
694 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
696 static void iflib_altq_if_start(if_t ifp);
697 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
699 static int iflib_register(if_ctx_t);
700 static void iflib_deregister(if_ctx_t);
701 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
702 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
703 static void iflib_init_locked(if_ctx_t ctx);
704 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
705 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
706 static void iflib_ifmp_purge(iflib_txq_t txq);
707 static void _iflib_pre_assert(if_softc_ctx_t scctx);
708 static void iflib_if_init_locked(if_ctx_t ctx);
709 static void iflib_free_intr_mem(if_ctx_t ctx);
710 #ifndef __NO_STRICT_ALIGNMENT
711 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
714 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
715 SLIST_HEAD_INITIALIZER(cpu_offsets);
717 SLIST_ENTRY(cpu_offset) entries;
719 unsigned int refcount;
722 static struct mtx cpu_offset_mtx;
723 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
726 DEBUGNET_DEFINE(iflib);
729 iflib_num_rx_descs(if_ctx_t ctx)
731 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
732 if_shared_ctx_t sctx = ctx->ifc_sctx;
733 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
735 return scctx->isc_nrxd[first_rxq];
739 iflib_num_tx_descs(if_ctx_t ctx)
741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
742 if_shared_ctx_t sctx = ctx->ifc_sctx;
743 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
745 return scctx->isc_ntxd[first_txq];
749 #include <sys/selinfo.h>
750 #include <net/netmap.h>
751 #include <dev/netmap/netmap_kern.h>
753 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
755 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
758 * device-specific sysctl variables:
760 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
761 * During regular operations the CRC is stripped, but on some
762 * hardware reception of frames not multiple of 64 is slower,
763 * so using crcstrip=0 helps in benchmarks.
765 * iflib_rx_miss, iflib_rx_miss_bufs:
766 * count packets that might be missed due to lost interrupts.
768 SYSCTL_DECL(_dev_netmap);
770 * The xl driver by default strips CRCs and we do not override it.
773 int iflib_crcstrip = 1;
774 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
775 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
777 int iflib_rx_miss, iflib_rx_miss_bufs;
778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
779 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
781 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
784 * Register/unregister. We are already under netmap lock.
785 * Only called on the first register or the last unregister.
788 iflib_netmap_register(struct netmap_adapter *na, int onoff)
791 if_ctx_t ctx = ifp->if_softc;
795 IFDI_INTR_DISABLE(ctx);
797 /* Tell the stack that the interface is no longer active */
798 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
801 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
806 * Enable (or disable) netmap flags, and intercept (or restore)
807 * ifp->if_transmit. This is done once the device has been stopped
808 * to prevent race conditions.
811 nm_set_native_flags(na);
813 nm_clear_native_flags(na);
816 iflib_init_locked(ctx);
817 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
818 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
820 nm_clear_native_flags(na);
826 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
828 struct netmap_adapter *na = kring->na;
829 u_int const lim = kring->nkr_num_slots - 1;
830 u_int nm_i = kring->nr_hwcur;
831 struct netmap_ring *ring = kring->ring;
833 struct if_rxd_update iru;
834 if_ctx_t ctx = rxq->ifr_ctx;
835 iflib_fl_t fl = &rxq->ifr_fl[0];
836 u_int nic_i_first, nic_i;
838 #if IFLIB_DEBUG_COUNTERS
843 * This function is used both at initialization and in rxsync.
844 * At initialization we need to prepare (with isc_rxd_refill())
845 * all the (N) netmap buffers in the ring, in such a way to keep
846 * fl->ifl_pidx and kring->nr_hwcur in sync (except for
847 * kring->nkr_hwofs); at rxsync time, both indexes point to the
848 * next buffer to be refilled.
849 * In any case we publish (with isc_rxd_flush()) up to
850 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
851 * pointer to overrun the head/cons pointer, although this is
852 * not necessary for some NICs (e.g. vmx).
854 if (__predict_false(init))
855 n = kring->nkr_num_slots;
857 n = kring->rhead - nm_i;
859 return (0); /* Nothing to do. */
861 n += kring->nkr_num_slots;
864 /* Start to refill from nr_hwcur, publishing n buffers. */
865 iru_init(&iru, rxq, 0 /* flid */);
866 map = fl->ifl_sds.ifsd_map;
867 nic_i = fl->ifl_pidx;
868 MPASS(nic_i == netmap_idx_k2n(kring, nm_i));
869 DBG_COUNTER_INC(fl_refills);
871 #if IFLIB_DEBUG_COUNTERS
873 DBG_COUNTER_INC(fl_refills_large);
876 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
877 struct netmap_slot *slot = &ring->slot[nm_i];
878 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
880 MPASS(i < IFLIB_MAX_RX_REFRESH);
882 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
883 return netmap_ring_reinit(kring);
885 fl->ifl_rxd_idxs[i] = nic_i;
887 if (__predict_false(init)) {
888 netmap_load_map(na, fl->ifl_buf_tag,
890 } else if (slot->flags & NS_BUF_CHANGED) {
891 /* buffer has changed, reload map */
892 netmap_reload_map(na, fl->ifl_buf_tag,
895 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
896 BUS_DMASYNC_PREREAD);
897 slot->flags &= ~NS_BUF_CHANGED;
899 nm_i = nm_next(nm_i, lim);
900 nic_i = nm_next(nic_i, lim);
903 iru.iru_pidx = nic_i_first;
905 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
907 fl->ifl_pidx = nic_i;
908 MPASS(!init || nm_i == 0);
909 MPASS(nm_i == kring->rhead);
910 kring->nr_hwcur = nm_i;
912 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
913 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
914 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
915 nm_prev(nic_i, lim));
916 DBG_COUNTER_INC(rxd_flush);
922 * Reconcile kernel and user view of the transmit ring.
924 * All information is in the kring.
925 * Userspace wants to send packets up to the one before kring->rhead,
926 * kernel knows kring->nr_hwcur is the first unsent packet.
928 * Here we push packets out (as many as possible), and possibly
929 * reclaim buffers from previously completed transmission.
931 * The caller (netmap) guarantees that there is only one instance
932 * running at any time. Any interference with other driver
933 * methods should be handled by the individual drivers.
936 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
938 struct netmap_adapter *na = kring->na;
940 struct netmap_ring *ring = kring->ring;
941 u_int nm_i; /* index into the netmap kring */
942 u_int nic_i; /* index into the NIC ring */
944 u_int const lim = kring->nkr_num_slots - 1;
945 u_int const head = kring->rhead;
946 struct if_pkt_info pi;
949 * interrupts on every tx packet are expensive so request
950 * them every half ring, or where NS_REPORT is set
952 u_int report_frequency = kring->nkr_num_slots >> 1;
953 /* device-specific */
954 if_ctx_t ctx = ifp->if_softc;
955 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
957 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
958 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
961 * First part: process new packets to send.
962 * nm_i is the current index in the netmap kring,
963 * nic_i is the corresponding index in the NIC ring.
965 * If we have packets to send (nm_i != head)
966 * iterate over the netmap ring, fetch length and update
967 * the corresponding slot in the NIC ring. Some drivers also
968 * need to update the buffer's physical address in the NIC slot
969 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
971 * The netmap_reload_map() calls is especially expensive,
972 * even when (as in this case) the tag is 0, so do only
973 * when the buffer has actually changed.
975 * If possible do not set the report/intr bit on all slots,
976 * but only a few times per ring or when NS_REPORT is set.
978 * Finally, on 10G and faster drivers, it might be useful
979 * to prefetch the next slot and txr entry.
982 nm_i = kring->nr_hwcur;
983 if (nm_i != head) { /* we have new packets to send */
985 pi.ipi_segs = txq->ift_segs;
986 pi.ipi_qsidx = kring->ring_id;
987 nic_i = netmap_idx_k2n(kring, nm_i);
989 __builtin_prefetch(&ring->slot[nm_i]);
990 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
991 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
993 for (n = 0; nm_i != head; n++) {
994 struct netmap_slot *slot = &ring->slot[nm_i];
995 u_int len = slot->len;
997 void *addr = PNMB(na, slot, &paddr);
998 int flags = (slot->flags & NS_REPORT ||
999 nic_i == 0 || nic_i == report_frequency) ?
1002 /* device-specific */
1004 pi.ipi_segs[0].ds_addr = paddr;
1005 pi.ipi_segs[0].ds_len = len;
1008 pi.ipi_pidx = nic_i;
1009 pi.ipi_flags = flags;
1011 /* Fill the slot in the NIC ring. */
1012 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1013 DBG_COUNTER_INC(tx_encap);
1015 /* prefetch for next round */
1016 __builtin_prefetch(&ring->slot[nm_i + 1]);
1017 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1018 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1020 NM_CHECK_ADDR_LEN(na, addr, len);
1022 if (slot->flags & NS_BUF_CHANGED) {
1023 /* buffer has changed, reload map */
1024 netmap_reload_map(na, txq->ift_buf_tag,
1025 txq->ift_sds.ifsd_map[nic_i], addr);
1027 /* make sure changes to the buffer are synced */
1028 bus_dmamap_sync(txq->ift_buf_tag,
1029 txq->ift_sds.ifsd_map[nic_i],
1030 BUS_DMASYNC_PREWRITE);
1032 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1033 nm_i = nm_next(nm_i, lim);
1034 nic_i = nm_next(nic_i, lim);
1036 kring->nr_hwcur = nm_i;
1038 /* synchronize the NIC ring */
1039 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1040 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1042 /* (re)start the tx unit up to slot nic_i (excluded) */
1043 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1047 * Second part: reclaim buffers for completed transmissions.
1049 * If there are unclaimed buffers, attempt to reclaim them.
1050 * If none are reclaimed, and TX IRQs are not in use, do an initial
1051 * minimal delay, then trigger the tx handler which will spin in the
1054 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1055 if (iflib_tx_credits_update(ctx, txq)) {
1056 /* some tx completed, increment avail */
1057 nic_i = txq->ift_cidx_processed;
1058 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1061 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1062 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1063 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1064 iflib_timer, txq, txq->ift_timer.c_cpu);
1070 * Reconcile kernel and user view of the receive ring.
1071 * Same as for the txsync, this routine must be efficient.
1072 * The caller guarantees a single invocations, but races against
1073 * the rest of the driver should be handled here.
1075 * On call, kring->rhead is the first packet that userspace wants
1076 * to keep, and kring->rcur is the wakeup point.
1077 * The kernel has previously reported packets up to kring->rtail.
1079 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1080 * of whether or not we received an interrupt.
1083 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1085 struct netmap_adapter *na = kring->na;
1086 struct netmap_ring *ring = kring->ring;
1088 uint32_t nm_i; /* index into the netmap ring */
1089 uint32_t nic_i; /* index into the NIC ring */
1091 u_int const lim = kring->nkr_num_slots - 1;
1092 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1094 if_ctx_t ctx = ifp->if_softc;
1095 if_shared_ctx_t sctx = ctx->ifc_sctx;
1096 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1097 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1098 iflib_fl_t fl = &rxq->ifr_fl[0];
1099 struct if_rxd_info ri;
1103 * netmap only uses free list 0, to avoid out of order consumption
1104 * of receive buffers
1107 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1108 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1111 * First part: import newly received packets.
1113 * nm_i is the index of the next free slot in the netmap ring,
1114 * nic_i is the index of the next received packet in the NIC ring
1115 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1116 * differ in case if_init() has been called while
1117 * in netmap mode. For the receive ring we have
1119 * nic_i = fl->ifl_cidx;
1120 * nm_i = kring->nr_hwtail (previous)
1122 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1124 * fl->ifl_cidx is set to 0 on a ring reinit
1126 if (netmap_no_pendintr || force_update) {
1127 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1128 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1129 int crclen = iflib_crcstrip ? 0 : 4;
1133 * For the free list consumer index, we use the same
1134 * logic as in iflib_rxeof().
1137 cidxp = &rxq->ifr_cq_cidx;
1139 cidxp = &fl->ifl_cidx;
1140 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1141 rxq->ifr_id, *cidxp, USHRT_MAX);
1143 nic_i = fl->ifl_cidx;
1144 nm_i = netmap_idx_n2k(kring, nic_i);
1145 MPASS(nm_i == kring->nr_hwtail);
1146 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1148 ri.iri_frags = rxq->ifr_frags;
1149 ri.iri_qsidx = kring->ring_id;
1150 ri.iri_ifp = ctx->ifc_ifp;
1151 ri.iri_cidx = *cidxp;
1153 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1154 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1155 ring->slot[nm_i].flags = 0;
1157 *cidxp = ri.iri_cidx;
1158 while (*cidxp >= scctx->isc_nrxd[0])
1159 *cidxp -= scctx->isc_nrxd[0];
1161 bus_dmamap_sync(fl->ifl_buf_tag,
1162 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1163 nm_i = nm_next(nm_i, lim);
1164 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1166 if (n) { /* update the state variables */
1167 if (netmap_no_pendintr && !force_update) {
1170 iflib_rx_miss_bufs += n;
1172 kring->nr_hwtail = nm_i;
1174 kring->nr_kflags &= ~NKR_PENDINTR;
1177 * Second part: skip past packets that userspace has released.
1178 * (kring->nr_hwcur to head excluded),
1179 * and make the buffers available for reception.
1180 * As usual nm_i is the index in the netmap ring,
1181 * nic_i is the index in the NIC ring, and
1182 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1184 netmap_fl_refill(rxq, kring, false);
1190 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1192 if_ctx_t ctx = na->ifp->if_softc;
1196 IFDI_INTR_ENABLE(ctx);
1198 IFDI_INTR_DISABLE(ctx);
1204 iflib_netmap_attach(if_ctx_t ctx)
1206 struct netmap_adapter na;
1208 bzero(&na, sizeof(na));
1210 na.ifp = ctx->ifc_ifp;
1211 na.na_flags = NAF_BDG_MAYSLEEP;
1212 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1213 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1215 na.num_tx_desc = iflib_num_tx_descs(ctx);
1216 na.num_rx_desc = iflib_num_rx_descs(ctx);
1217 na.nm_txsync = iflib_netmap_txsync;
1218 na.nm_rxsync = iflib_netmap_rxsync;
1219 na.nm_register = iflib_netmap_register;
1220 na.nm_intr = iflib_netmap_intr;
1221 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1222 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1223 return (netmap_attach(&na));
1227 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1229 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1230 struct netmap_slot *slot;
1232 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1235 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1237 * In netmap mode, set the map for the packet buffer.
1238 * NOTE: Some drivers (not this one) also need to set
1239 * the physical buffer address in the NIC ring.
1240 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1241 * netmap slot index, si
1243 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1244 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1245 NMB(na, slot + si));
1251 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1253 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1254 struct netmap_kring *kring;
1255 struct netmap_slot *slot;
1257 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1260 kring = na->rx_rings[rxq->ifr_id];
1261 netmap_fl_refill(rxq, kring, true);
1266 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1268 struct netmap_kring *kring;
1271 txqid = txq->ift_id;
1272 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX);
1276 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1277 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1278 BUS_DMASYNC_POSTREAD);
1279 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1280 netmap_tx_irq(ctx->ifc_ifp, txqid);
1281 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1285 *reset_on = hz / 1000;
1290 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1293 #define iflib_netmap_txq_init(ctx, txq) (0)
1294 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1295 #define iflib_netmap_detach(ifp)
1297 #define iflib_netmap_attach(ctx) (0)
1298 #define netmap_rx_irq(ifp, qid, budget) (0)
1299 #define netmap_tx_irq(ifp, qid) do {} while (0)
1300 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1303 #if defined(__i386__) || defined(__amd64__)
1304 static __inline void
1307 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1309 static __inline void
1310 prefetch2cachelines(void *x)
1312 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1313 #if (CACHE_LINE_SIZE < 128)
1314 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1319 #define prefetch2cachelines(x)
1323 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1327 fl = &rxq->ifr_fl[flid];
1328 iru->iru_paddrs = fl->ifl_bus_addrs;
1329 iru->iru_idxs = fl->ifl_rxd_idxs;
1330 iru->iru_qsidx = rxq->ifr_id;
1331 iru->iru_buf_size = fl->ifl_buf_size;
1332 iru->iru_flidx = fl->ifl_id;
1336 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1340 *(bus_addr_t *) arg = segs[0].ds_addr;
1344 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1347 device_t dev = ctx->ifc_dev;
1349 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1350 align, 0, /* alignment, bounds */
1351 BUS_SPACE_MAXADDR, /* lowaddr */
1352 BUS_SPACE_MAXADDR, /* highaddr */
1353 NULL, NULL, /* filter, filterarg */
1356 size, /* maxsegsize */
1357 BUS_DMA_ALLOCNOW, /* flags */
1358 NULL, /* lockfunc */
1363 "%s: bus_dma_tag_create failed: %d\n",
1368 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1369 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1372 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1373 __func__, (uintmax_t)size, err);
1377 dma->idi_paddr = IF_BAD_DMA;
1378 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1379 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1380 if (err || dma->idi_paddr == IF_BAD_DMA) {
1382 "%s: bus_dmamap_load failed: %d\n",
1387 dma->idi_size = size;
1391 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1393 bus_dma_tag_destroy(dma->idi_tag);
1395 dma->idi_tag = NULL;
1401 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1403 if_shared_ctx_t sctx = ctx->ifc_sctx;
1405 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1407 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1411 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1414 iflib_dma_info_t *dmaiter;
1417 for (i = 0; i < count; i++, dmaiter++) {
1418 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1422 iflib_dma_free_multi(dmalist, i);
1427 iflib_dma_free(iflib_dma_info_t dma)
1429 if (dma->idi_tag == NULL)
1431 if (dma->idi_paddr != IF_BAD_DMA) {
1432 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1434 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1435 dma->idi_paddr = IF_BAD_DMA;
1437 if (dma->idi_vaddr != NULL) {
1438 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1439 dma->idi_vaddr = NULL;
1441 bus_dma_tag_destroy(dma->idi_tag);
1442 dma->idi_tag = NULL;
1446 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1449 iflib_dma_info_t *dmaiter = dmalist;
1451 for (i = 0; i < count; i++, dmaiter++)
1452 iflib_dma_free(*dmaiter);
1456 iflib_fast_intr(void *arg)
1458 iflib_filter_info_t info = arg;
1459 struct grouptask *gtask = info->ifi_task;
1462 DBG_COUNTER_INC(fast_intrs);
1463 if (info->ifi_filter != NULL) {
1464 result = info->ifi_filter(info->ifi_filter_arg);
1465 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1469 GROUPTASK_ENQUEUE(gtask);
1470 return (FILTER_HANDLED);
1474 iflib_fast_intr_rxtx(void *arg)
1476 iflib_filter_info_t info = arg;
1477 struct grouptask *gtask = info->ifi_task;
1479 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1482 int i, cidx, result;
1484 bool intr_enable, intr_legacy;
1486 DBG_COUNTER_INC(fast_intrs);
1487 if (info->ifi_filter != NULL) {
1488 result = info->ifi_filter(info->ifi_filter_arg);
1489 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1494 sc = ctx->ifc_softc;
1495 intr_enable = false;
1496 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1497 MPASS(rxq->ifr_ntxqirq);
1498 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1499 txqid = rxq->ifr_txqid[i];
1500 txq = &ctx->ifc_txqs[txqid];
1501 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1502 BUS_DMASYNC_POSTREAD);
1503 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1507 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1510 GROUPTASK_ENQUEUE(&txq->ift_task);
1512 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1513 cidx = rxq->ifr_cq_cidx;
1515 cidx = rxq->ifr_fl[0].ifl_cidx;
1516 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1517 GROUPTASK_ENQUEUE(gtask);
1522 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1523 DBG_COUNTER_INC(rx_intr_enables);
1526 IFDI_INTR_ENABLE(ctx);
1527 return (FILTER_HANDLED);
1531 iflib_fast_intr_ctx(void *arg)
1533 iflib_filter_info_t info = arg;
1534 struct grouptask *gtask = info->ifi_task;
1537 DBG_COUNTER_INC(fast_intrs);
1538 if (info->ifi_filter != NULL) {
1539 result = info->ifi_filter(info->ifi_filter_arg);
1540 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1544 GROUPTASK_ENQUEUE(gtask);
1545 return (FILTER_HANDLED);
1549 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1550 driver_filter_t filter, driver_intr_t handler, void *arg,
1553 struct resource *res;
1555 device_t dev = ctx->ifc_dev;
1559 if (ctx->ifc_flags & IFC_LEGACY)
1560 flags |= RF_SHAREABLE;
1563 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1566 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1570 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1571 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1572 filter, handler, arg, &tag);
1575 "failed to setup interrupt for rid %d, name %s: %d\n",
1576 rid, name ? name : "unknown", rc);
1579 bus_describe_intr(dev, res, tag, "%s", name);
1585 /*********************************************************************
1587 * Allocate DMA resources for TX buffers as well as memory for the TX
1588 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1589 * iflib_sw_tx_desc_array structure, storing all the information that
1590 * is needed to transmit a packet on the wire. This is called only
1591 * once at attach, setup is done every reset.
1593 **********************************************************************/
1595 iflib_txsd_alloc(iflib_txq_t txq)
1597 if_ctx_t ctx = txq->ift_ctx;
1598 if_shared_ctx_t sctx = ctx->ifc_sctx;
1599 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1600 device_t dev = ctx->ifc_dev;
1601 bus_size_t tsomaxsize;
1602 int err, nsegments, ntsosegments;
1605 nsegments = scctx->isc_tx_nsegments;
1606 ntsosegments = scctx->isc_tx_tso_segments_max;
1607 tsomaxsize = scctx->isc_tx_tso_size_max;
1608 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1609 tsomaxsize += sizeof(struct ether_vlan_header);
1610 MPASS(scctx->isc_ntxd[0] > 0);
1611 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1612 MPASS(nsegments > 0);
1613 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1614 MPASS(ntsosegments > 0);
1615 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1619 * Set up DMA tags for TX buffers.
1621 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1622 1, 0, /* alignment, bounds */
1623 BUS_SPACE_MAXADDR, /* lowaddr */
1624 BUS_SPACE_MAXADDR, /* highaddr */
1625 NULL, NULL, /* filter, filterarg */
1626 sctx->isc_tx_maxsize, /* maxsize */
1627 nsegments, /* nsegments */
1628 sctx->isc_tx_maxsegsize, /* maxsegsize */
1630 NULL, /* lockfunc */
1631 NULL, /* lockfuncarg */
1632 &txq->ift_buf_tag))) {
1633 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1634 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1635 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1638 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1639 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1640 1, 0, /* alignment, bounds */
1641 BUS_SPACE_MAXADDR, /* lowaddr */
1642 BUS_SPACE_MAXADDR, /* highaddr */
1643 NULL, NULL, /* filter, filterarg */
1644 tsomaxsize, /* maxsize */
1645 ntsosegments, /* nsegments */
1646 sctx->isc_tso_maxsegsize,/* maxsegsize */
1648 NULL, /* lockfunc */
1649 NULL, /* lockfuncarg */
1650 &txq->ift_tso_buf_tag))) {
1651 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1656 /* Allocate memory for the TX mbuf map. */
1657 if (!(txq->ift_sds.ifsd_m =
1658 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1659 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1660 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1666 * Create the DMA maps for TX buffers.
1668 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1669 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1670 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1672 "Unable to allocate TX buffer DMA map memory\n");
1676 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1677 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1678 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1680 "Unable to allocate TSO TX buffer map memory\n");
1684 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1685 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1686 &txq->ift_sds.ifsd_map[i]);
1688 device_printf(dev, "Unable to create TX DMA map\n");
1693 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1694 &txq->ift_sds.ifsd_tso_map[i]);
1696 device_printf(dev, "Unable to create TSO TX DMA map\n");
1702 /* We free all, it handles case where we are in the middle */
1703 iflib_tx_structures_free(ctx);
1708 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1712 if (txq->ift_sds.ifsd_map != NULL) {
1713 map = txq->ift_sds.ifsd_map[i];
1714 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1715 bus_dmamap_unload(txq->ift_buf_tag, map);
1716 bus_dmamap_destroy(txq->ift_buf_tag, map);
1717 txq->ift_sds.ifsd_map[i] = NULL;
1720 if (txq->ift_sds.ifsd_tso_map != NULL) {
1721 map = txq->ift_sds.ifsd_tso_map[i];
1722 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1723 BUS_DMASYNC_POSTWRITE);
1724 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1725 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1726 txq->ift_sds.ifsd_tso_map[i] = NULL;
1731 iflib_txq_destroy(iflib_txq_t txq)
1733 if_ctx_t ctx = txq->ift_ctx;
1735 for (int i = 0; i < txq->ift_size; i++)
1736 iflib_txsd_destroy(ctx, txq, i);
1738 if (txq->ift_br != NULL) {
1739 ifmp_ring_free(txq->ift_br);
1743 mtx_destroy(&txq->ift_mtx);
1745 if (txq->ift_sds.ifsd_map != NULL) {
1746 free(txq->ift_sds.ifsd_map, M_IFLIB);
1747 txq->ift_sds.ifsd_map = NULL;
1749 if (txq->ift_sds.ifsd_tso_map != NULL) {
1750 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1751 txq->ift_sds.ifsd_tso_map = NULL;
1753 if (txq->ift_sds.ifsd_m != NULL) {
1754 free(txq->ift_sds.ifsd_m, M_IFLIB);
1755 txq->ift_sds.ifsd_m = NULL;
1757 if (txq->ift_buf_tag != NULL) {
1758 bus_dma_tag_destroy(txq->ift_buf_tag);
1759 txq->ift_buf_tag = NULL;
1761 if (txq->ift_tso_buf_tag != NULL) {
1762 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1763 txq->ift_tso_buf_tag = NULL;
1765 if (txq->ift_ifdi != NULL) {
1766 free(txq->ift_ifdi, M_IFLIB);
1771 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1775 mp = &txq->ift_sds.ifsd_m[i];
1779 if (txq->ift_sds.ifsd_map != NULL) {
1780 bus_dmamap_sync(txq->ift_buf_tag,
1781 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1782 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1784 if (txq->ift_sds.ifsd_tso_map != NULL) {
1785 bus_dmamap_sync(txq->ift_tso_buf_tag,
1786 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1787 bus_dmamap_unload(txq->ift_tso_buf_tag,
1788 txq->ift_sds.ifsd_tso_map[i]);
1791 DBG_COUNTER_INC(tx_frees);
1796 iflib_txq_setup(iflib_txq_t txq)
1798 if_ctx_t ctx = txq->ift_ctx;
1799 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1800 if_shared_ctx_t sctx = ctx->ifc_sctx;
1801 iflib_dma_info_t di;
1804 /* Set number of descriptors available */
1805 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1806 /* XXX make configurable */
1807 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1810 txq->ift_cidx_processed = 0;
1811 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1812 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1814 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1815 bzero((void *)di->idi_vaddr, di->idi_size);
1817 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1818 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1819 bus_dmamap_sync(di->idi_tag, di->idi_map,
1820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1824 /*********************************************************************
1826 * Allocate DMA resources for RX buffers as well as memory for the RX
1827 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1828 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1829 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1830 * Since we use use one entry in iflib_sw_rx_desc_array per received
1831 * packet, the maximum number of entries we'll need is equal to the
1832 * number of hardware receive descriptors that we've allocated.
1834 **********************************************************************/
1836 iflib_rxsd_alloc(iflib_rxq_t rxq)
1838 if_ctx_t ctx = rxq->ifr_ctx;
1839 if_shared_ctx_t sctx = ctx->ifc_sctx;
1840 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1841 device_t dev = ctx->ifc_dev;
1845 MPASS(scctx->isc_nrxd[0] > 0);
1846 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1849 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1850 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1851 /* Set up DMA tag for RX buffers. */
1852 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1853 1, 0, /* alignment, bounds */
1854 BUS_SPACE_MAXADDR, /* lowaddr */
1855 BUS_SPACE_MAXADDR, /* highaddr */
1856 NULL, NULL, /* filter, filterarg */
1857 sctx->isc_rx_maxsize, /* maxsize */
1858 sctx->isc_rx_nsegments, /* nsegments */
1859 sctx->isc_rx_maxsegsize, /* maxsegsize */
1861 NULL, /* lockfunc */
1866 "Unable to allocate RX DMA tag: %d\n", err);
1870 /* Allocate memory for the RX mbuf map. */
1871 if (!(fl->ifl_sds.ifsd_m =
1872 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1873 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1875 "Unable to allocate RX mbuf map memory\n");
1880 /* Allocate memory for the direct RX cluster pointer map. */
1881 if (!(fl->ifl_sds.ifsd_cl =
1882 (caddr_t *) malloc(sizeof(caddr_t) *
1883 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1885 "Unable to allocate RX cluster map memory\n");
1890 /* Allocate memory for the RX cluster bus address map. */
1891 if (!(fl->ifl_sds.ifsd_ba =
1892 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1893 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1895 "Unable to allocate RX bus address map memory\n");
1901 * Create the DMA maps for RX buffers.
1903 if (!(fl->ifl_sds.ifsd_map =
1904 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1906 "Unable to allocate RX buffer DMA map memory\n");
1910 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1911 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1912 &fl->ifl_sds.ifsd_map[i]);
1914 device_printf(dev, "Unable to create RX buffer DMA map\n");
1922 iflib_rx_structures_free(ctx);
1927 * Internal service routines
1930 struct rxq_refill_cb_arg {
1932 bus_dma_segment_t seg;
1937 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1939 struct rxq_refill_cb_arg *cb_arg = arg;
1941 cb_arg->error = error;
1942 cb_arg->seg = segs[0];
1943 cb_arg->nseg = nseg;
1947 * iflib_fl_refill - refill an rxq free-buffer list
1948 * @ctx: the iflib context
1949 * @fl: the free list to refill
1950 * @count: the number of new buffers to allocate
1952 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1953 * The caller must assure that @count does not exceed the queue's capacity
1954 * minus one (since we always leave a descriptor unavailable).
1957 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1959 struct if_rxd_update iru;
1960 struct rxq_refill_cb_arg cb_arg;
1964 bus_dmamap_t *sd_map;
1965 bus_addr_t bus_addr, *sd_ba;
1966 int err, frag_idx, i, idx, n, pidx;
1969 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
1971 sd_m = fl->ifl_sds.ifsd_m;
1972 sd_map = fl->ifl_sds.ifsd_map;
1973 sd_cl = fl->ifl_sds.ifsd_cl;
1974 sd_ba = fl->ifl_sds.ifsd_ba;
1975 pidx = fl->ifl_pidx;
1977 frag_idx = fl->ifl_fragidx;
1978 credits = fl->ifl_credits;
1983 MPASS(credits + n <= fl->ifl_size);
1985 if (pidx < fl->ifl_cidx)
1986 MPASS(pidx + n <= fl->ifl_cidx);
1987 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1988 MPASS(fl->ifl_gen == 0);
1989 if (pidx > fl->ifl_cidx)
1990 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1992 DBG_COUNTER_INC(fl_refills);
1994 DBG_COUNTER_INC(fl_refills_large);
1995 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1998 * We allocate an uninitialized mbuf + cluster, mbuf is
1999 * initialized after rx.
2001 * If the cluster is still set then we know a minimum sized
2002 * packet was received
2004 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2007 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2008 MPASS(frag_idx >= 0);
2009 if ((cl = sd_cl[frag_idx]) == NULL) {
2010 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2011 if (__predict_false(cl == NULL))
2015 MPASS(sd_map != NULL);
2016 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2017 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2019 if (__predict_false(err != 0 || cb_arg.error)) {
2020 uma_zfree(fl->ifl_zone, cl);
2024 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2025 sd_cl[frag_idx] = cl;
2027 fl->ifl_cl_enqueued++;
2030 bus_addr = sd_ba[frag_idx];
2032 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2033 BUS_DMASYNC_PREREAD);
2035 if (sd_m[frag_idx] == NULL) {
2036 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2037 if (__predict_false(m == NULL))
2041 bit_set(fl->ifl_rx_bitmap, frag_idx);
2043 fl->ifl_m_enqueued++;
2046 DBG_COUNTER_INC(rx_allocs);
2047 fl->ifl_rxd_idxs[i] = frag_idx;
2048 fl->ifl_bus_addrs[i] = bus_addr;
2051 MPASS(credits <= fl->ifl_size);
2052 if (++idx == fl->ifl_size) {
2058 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2059 iru.iru_pidx = pidx;
2061 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2063 fl->ifl_credits = credits;
2069 if (n < count - 1) {
2071 iru.iru_pidx = pidx;
2073 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2075 fl->ifl_credits = credits;
2077 DBG_COUNTER_INC(rxd_flush);
2078 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2079 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2080 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2081 fl->ifl_id, fl->ifl_pidx);
2082 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2083 fl->ifl_fragidx = frag_idx + 1;
2084 if (fl->ifl_fragidx == fl->ifl_size)
2085 fl->ifl_fragidx = 0;
2087 fl->ifl_fragidx = frag_idx;
2091 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2094 static inline uint8_t
2095 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2098 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2099 * This is important as it confuses most NICs. For instance,
2100 * Intel NICs have (per receive ring) RDH and RDT registers, where
2101 * RDH points to the next receive descriptor to be used by the NIC,
2102 * and RDT for the next receive descriptor to be published by the
2103 * driver to the NIC (RDT - 1 is thus the last valid one).
2104 * The condition RDH == RDT means no descriptors are available to
2105 * the NIC, and thus it would be ambiguous if it also meant that
2106 * all the descriptors are available to the NIC.
2108 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2110 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2113 MPASS(fl->ifl_credits <= fl->ifl_size);
2114 MPASS(reclaimable == delta);
2116 if (reclaimable > 0)
2117 return (iflib_fl_refill(ctx, fl, reclaimable));
2122 iflib_in_detach(if_ctx_t ctx)
2127 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2133 iflib_fl_bufs_free(iflib_fl_t fl)
2135 iflib_dma_info_t idi = fl->ifl_ifdi;
2136 bus_dmamap_t sd_map;
2139 for (i = 0; i < fl->ifl_size; i++) {
2140 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2141 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2143 if (*sd_cl != NULL) {
2144 sd_map = fl->ifl_sds.ifsd_map[i];
2145 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2146 BUS_DMASYNC_POSTREAD);
2147 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2148 uma_zfree(fl->ifl_zone, *sd_cl);
2150 if (*sd_m != NULL) {
2151 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2152 uma_zfree(zone_mbuf, *sd_m);
2156 MPASS(*sd_m == NULL);
2159 fl->ifl_m_dequeued++;
2160 fl->ifl_cl_dequeued++;
2164 for (i = 0; i < fl->ifl_size; i++) {
2165 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2166 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2170 * Reset free list values
2172 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2173 bzero(idi->idi_vaddr, idi->idi_size);
2176 /*********************************************************************
2178 * Initialize a free list and its buffers.
2180 **********************************************************************/
2182 iflib_fl_setup(iflib_fl_t fl)
2184 iflib_rxq_t rxq = fl->ifl_rxq;
2185 if_ctx_t ctx = rxq->ifr_ctx;
2186 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2189 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2191 ** Free current RX buffer structs and their mbufs
2193 iflib_fl_bufs_free(fl);
2194 /* Now replenish the mbufs */
2195 MPASS(fl->ifl_credits == 0);
2196 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2197 if (scctx->isc_rxd_buf_size[qidx] != 0)
2198 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2200 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2202 * ifl_buf_size may be a driver-supplied value, so pull it up
2203 * to the selected mbuf size.
2205 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2206 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2207 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2208 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2209 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2212 * Avoid pre-allocating zillions of clusters to an idle card
2213 * potentially speeding up attach. In any case make sure
2214 * to leave a descriptor unavailable. See the comment in
2215 * iflib_fl_refill_all().
2217 MPASS(fl->ifl_size > 0);
2218 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2219 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2225 MPASS(fl->ifl_ifdi != NULL);
2226 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2227 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2231 /*********************************************************************
2233 * Free receive ring data structures
2235 **********************************************************************/
2237 iflib_rx_sds_free(iflib_rxq_t rxq)
2242 if (rxq->ifr_fl != NULL) {
2243 for (i = 0; i < rxq->ifr_nfl; i++) {
2244 fl = &rxq->ifr_fl[i];
2245 if (fl->ifl_buf_tag != NULL) {
2246 if (fl->ifl_sds.ifsd_map != NULL) {
2247 for (j = 0; j < fl->ifl_size; j++) {
2250 fl->ifl_sds.ifsd_map[j],
2251 BUS_DMASYNC_POSTREAD);
2254 fl->ifl_sds.ifsd_map[j]);
2257 fl->ifl_sds.ifsd_map[j]);
2260 bus_dma_tag_destroy(fl->ifl_buf_tag);
2261 fl->ifl_buf_tag = NULL;
2263 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2264 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2265 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2266 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2267 fl->ifl_sds.ifsd_m = NULL;
2268 fl->ifl_sds.ifsd_cl = NULL;
2269 fl->ifl_sds.ifsd_ba = NULL;
2270 fl->ifl_sds.ifsd_map = NULL;
2272 free(rxq->ifr_fl, M_IFLIB);
2274 free(rxq->ifr_ifdi, M_IFLIB);
2275 rxq->ifr_ifdi = NULL;
2276 rxq->ifr_cq_cidx = 0;
2284 iflib_timer(void *arg)
2286 iflib_txq_t txq = arg;
2287 if_ctx_t ctx = txq->ift_ctx;
2288 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2289 uint64_t this_tick = ticks;
2290 uint32_t reset_on = hz / 2;
2292 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2296 ** Check on the state of the TX queue(s), this
2297 ** can be done without the lock because its RO
2298 ** and the HUNG state will be static if set.
2300 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2301 txq->ift_last_timer_tick = this_tick;
2302 IFDI_TIMER(ctx, txq->ift_id);
2303 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2304 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2305 (sctx->isc_pause_frames == 0)))
2308 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2309 ifmp_ring_is_stalled(txq->ift_br)) {
2310 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2311 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2313 txq->ift_cleaned_prev = txq->ift_cleaned;
2316 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2317 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2319 /* handle any laggards */
2320 if (txq->ift_db_pending)
2321 GROUPTASK_ENQUEUE(&txq->ift_task);
2323 sctx->isc_pause_frames = 0;
2324 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2325 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2329 device_printf(ctx->ifc_dev,
2330 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2331 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2333 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2334 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2335 iflib_admin_intr_deferred(ctx);
2340 iflib_get_mbuf_size_for(unsigned int size)
2343 if (size <= MCLBYTES)
2346 return (MJUMPAGESIZE);
2350 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2352 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2355 * XXX don't set the max_frame_size to larger
2356 * than the hardware can handle
2358 ctx->ifc_rx_mbuf_sz =
2359 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2363 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2366 return (ctx->ifc_rx_mbuf_sz);
2370 iflib_init_locked(if_ctx_t ctx)
2372 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2373 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2374 if_t ifp = ctx->ifc_ifp;
2378 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2380 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2381 IFDI_INTR_DISABLE(ctx);
2383 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2384 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2385 /* Set hardware offload abilities */
2386 if_clearhwassist(ifp);
2387 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2388 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2389 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2390 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2391 if (if_getcapenable(ifp) & IFCAP_TSO4)
2392 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2393 if (if_getcapenable(ifp) & IFCAP_TSO6)
2394 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2396 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2398 callout_stop(&txq->ift_timer);
2399 CALLOUT_UNLOCK(txq);
2400 iflib_netmap_txq_init(ctx, txq);
2404 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2405 * that drivers can use the value when setting up the hardware receive
2408 iflib_calc_rx_mbuf_sz(ctx);
2411 i = if_getdrvflags(ifp);
2414 MPASS(if_getdrvflags(ifp) == i);
2415 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2416 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2417 /* This rxq is in netmap mode. Skip normal init. */
2420 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2421 if (iflib_fl_setup(fl)) {
2422 device_printf(ctx->ifc_dev,
2423 "setting up free list %d failed - "
2424 "check cluster settings\n", j);
2430 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2431 IFDI_INTR_ENABLE(ctx);
2432 txq = ctx->ifc_txqs;
2433 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2434 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2435 txq->ift_timer.c_cpu);
2439 iflib_media_change(if_t ifp)
2441 if_ctx_t ctx = if_getsoftc(ifp);
2445 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2446 iflib_init_locked(ctx);
2452 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2454 if_ctx_t ctx = if_getsoftc(ifp);
2457 IFDI_UPDATE_ADMIN_STATUS(ctx);
2458 IFDI_MEDIA_STATUS(ctx, ifmr);
2463 iflib_stop(if_ctx_t ctx)
2465 iflib_txq_t txq = ctx->ifc_txqs;
2466 iflib_rxq_t rxq = ctx->ifc_rxqs;
2467 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2468 if_shared_ctx_t sctx = ctx->ifc_sctx;
2469 iflib_dma_info_t di;
2473 /* Tell the stack that the interface is no longer active */
2474 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2476 IFDI_INTR_DISABLE(ctx);
2481 iflib_debug_reset();
2482 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2483 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2484 /* make sure all transmitters have completed before proceeding XXX */
2487 callout_stop(&txq->ift_timer);
2488 CALLOUT_UNLOCK(txq);
2490 /* clean any enqueued buffers */
2491 iflib_ifmp_purge(txq);
2492 /* Free any existing tx buffers. */
2493 for (j = 0; j < txq->ift_size; j++) {
2494 iflib_txsd_free(ctx, txq, j);
2496 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2497 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2498 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2499 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2500 txq->ift_pullups = 0;
2501 ifmp_ring_reset_stats(txq->ift_br);
2502 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2503 bzero((void *)di->idi_vaddr, di->idi_size);
2505 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2506 /* make sure all transmitters have completed before proceeding XXX */
2508 rxq->ifr_cq_cidx = 0;
2509 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2510 bzero((void *)di->idi_vaddr, di->idi_size);
2511 /* also resets the free lists pidx/cidx */
2512 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2513 iflib_fl_bufs_free(fl);
2517 static inline caddr_t
2518 calc_next_rxd(iflib_fl_t fl, int cidx)
2522 caddr_t start, end, cur, next;
2524 nrxd = fl->ifl_size;
2525 size = fl->ifl_rxd_size;
2526 start = fl->ifl_ifdi->idi_vaddr;
2528 if (__predict_false(size == 0))
2530 cur = start + size*cidx;
2531 end = start + size*nrxd;
2532 next = CACHE_PTR_NEXT(cur);
2533 return (next < end ? next : start);
2537 prefetch_pkts(iflib_fl_t fl, int cidx)
2540 int nrxd = fl->ifl_size;
2543 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2544 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2545 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2546 next_rxd = calc_next_rxd(fl, cidx);
2548 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2549 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2550 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2551 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2552 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2553 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2554 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2555 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2558 static struct mbuf *
2559 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2560 int *pf_rv, if_rxd_info_t ri)
2566 int flid, cidx, len, next;
2569 flid = irf->irf_flid;
2570 cidx = irf->irf_idx;
2571 fl = &rxq->ifr_fl[flid];
2573 m = fl->ifl_sds.ifsd_m[cidx];
2574 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2577 fl->ifl_m_dequeued++;
2579 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2580 prefetch_pkts(fl, cidx);
2581 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2582 prefetch(&fl->ifl_sds.ifsd_map[next]);
2583 map = fl->ifl_sds.ifsd_map[cidx];
2585 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2587 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2588 irf->irf_len != 0) {
2589 payload = *sd->ifsd_cl;
2590 payload += ri->iri_pad;
2591 len = ri->iri_len - ri->iri_pad;
2592 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2593 len | PFIL_MEMPTR | PFIL_IN, NULL);
2598 * The filter ate it. Everything is recycled.
2603 case PFIL_REALLOCED:
2605 * The filter copied it. Everything is recycled.
2607 m = pfil_mem2mbuf(payload);
2612 * Filter said it was OK, so receive like
2615 fl->ifl_sds.ifsd_m[cidx] = NULL;
2621 fl->ifl_sds.ifsd_m[cidx] = NULL;
2625 if (unload && irf->irf_len != 0)
2626 bus_dmamap_unload(fl->ifl_buf_tag, map);
2627 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2628 if (__predict_false(fl->ifl_cidx == 0))
2630 bit_clear(fl->ifl_rx_bitmap, cidx);
2634 static struct mbuf *
2635 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2637 struct mbuf *m, *mh, *mt;
2639 int *pf_rv_ptr, flags, i, padlen;
2648 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2651 MPASS(*sd->ifsd_cl != NULL);
2654 * Exclude zero-length frags & frags from
2655 * packets the filter has consumed or dropped
2657 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2658 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2660 /* everything saved here */
2665 /* XXX we can save the cluster here, but not the mbuf */
2666 m_init(m, M_NOWAIT, MT_DATA, 0);
2671 flags = M_PKTHDR|M_EXT;
2673 padlen = ri->iri_pad;
2678 /* assuming padding is only on the first fragment */
2682 *sd->ifsd_cl = NULL;
2684 /* Can these two be made one ? */
2685 m_init(m, M_NOWAIT, MT_DATA, flags);
2686 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2688 * These must follow m_init and m_cljset
2690 m->m_data += padlen;
2691 ri->iri_len -= padlen;
2692 m->m_len = ri->iri_frags[i].irf_len;
2693 } while (++i < ri->iri_nfrags);
2699 * Process one software descriptor
2701 static struct mbuf *
2702 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2708 /* should I merge this back in now that the two paths are basically duplicated? */
2709 if (ri->iri_nfrags == 1 &&
2710 ri->iri_frags[0].irf_len != 0 &&
2711 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2712 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2714 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2716 if (pf_rv == PFIL_PASS) {
2717 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2718 #ifndef __NO_STRICT_ALIGNMENT
2722 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2723 m->m_len = ri->iri_frags[0].irf_len;
2726 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2729 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2732 m->m_pkthdr.len = ri->iri_len;
2733 m->m_pkthdr.rcvif = ri->iri_ifp;
2734 m->m_flags |= ri->iri_flags;
2735 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2736 m->m_pkthdr.flowid = ri->iri_flowid;
2737 M_HASHTYPE_SET(m, ri->iri_rsstype);
2738 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2739 m->m_pkthdr.csum_data = ri->iri_csum_data;
2743 #if defined(INET6) || defined(INET)
2745 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2747 CURVNET_SET(lc->ifp->if_vnet);
2749 *v6 = V_ip6_forwarding;
2752 *v4 = V_ipforwarding;
2758 * Returns true if it's possible this packet could be LROed.
2759 * if it returns false, it is guaranteed that tcp_lro_rx()
2760 * would not return zero.
2763 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2765 struct ether_header *eh;
2767 eh = mtod(m, struct ether_header *);
2768 switch (eh->ether_type) {
2770 case htons(ETHERTYPE_IPV6):
2771 return (!v6_forwarding);
2774 case htons(ETHERTYPE_IP):
2775 return (!v4_forwarding);
2783 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2789 _task_fn_rx_watchdog(void *context)
2791 iflib_rxq_t rxq = context;
2793 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2797 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2800 if_ctx_t ctx = rxq->ifr_ctx;
2801 if_shared_ctx_t sctx = ctx->ifc_sctx;
2802 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2805 struct if_rxd_info ri;
2806 int err, budget_left, rx_bytes, rx_pkts;
2809 bool v4_forwarding, v6_forwarding, lro_possible;
2813 * XXX early demux data packets so that if_input processing only handles
2814 * acks in interrupt context
2816 struct mbuf *m, *mh, *mt, *mf;
2820 lro_possible = v4_forwarding = v6_forwarding = false;
2824 rx_pkts = rx_bytes = 0;
2825 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2826 cidxp = &rxq->ifr_cq_cidx;
2828 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2829 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2830 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2831 retval |= iflib_fl_refill_all(ctx, fl);
2832 DBG_COUNTER_INC(rx_unavail);
2836 /* pfil needs the vnet to be set */
2837 CURVNET_SET_QUIET(ifp->if_vnet);
2838 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2839 if (__predict_false(!CTX_ACTIVE(ctx))) {
2840 DBG_COUNTER_INC(rx_ctx_inactive);
2844 * Reset client set fields to their default values
2847 ri.iri_qsidx = rxq->ifr_id;
2848 ri.iri_cidx = *cidxp;
2850 ri.iri_frags = rxq->ifr_frags;
2851 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2856 rx_bytes += ri.iri_len;
2857 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2858 *cidxp = ri.iri_cidx;
2859 /* Update our consumer index */
2860 /* XXX NB: shurd - check if this is still safe */
2861 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2862 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2863 /* was this only a completion queue message? */
2864 if (__predict_false(ri.iri_nfrags == 0))
2867 MPASS(ri.iri_nfrags != 0);
2868 MPASS(ri.iri_len != 0);
2870 /* will advance the cidx on the corresponding free lists */
2871 m = iflib_rxd_pkt_get(rxq, &ri);
2874 if (avail == 0 && budget_left)
2875 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2877 if (__predict_false(m == NULL))
2880 /* imm_pkt: -- cxgb */
2889 /* make sure that we can refill faster than drain */
2890 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2891 retval |= iflib_fl_refill_all(ctx, fl);
2893 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2895 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2897 while (mh != NULL) {
2900 m->m_nextpkt = NULL;
2901 #ifndef __NO_STRICT_ALIGNMENT
2902 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2905 rx_bytes += m->m_pkthdr.len;
2907 #if defined(INET6) || defined(INET)
2909 if (!lro_possible) {
2910 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2911 if (lro_possible && mf != NULL) {
2912 ifp->if_input(ifp, mf);
2913 DBG_COUNTER_INC(rx_if_input);
2917 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2918 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2919 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2925 ifp->if_input(ifp, m);
2926 DBG_COUNTER_INC(rx_if_input);
2937 ifp->if_input(ifp, mf);
2938 DBG_COUNTER_INC(rx_if_input);
2941 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2942 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2945 * Flush any outstanding LRO work
2947 #if defined(INET6) || defined(INET)
2948 tcp_lro_flush_all(&rxq->ifr_lc);
2950 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2951 retval |= IFLIB_RXEOF_MORE;
2955 ctx->ifc_flags |= IFC_DO_RESET;
2956 iflib_admin_intr_deferred(ctx);
2961 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2962 static inline qidx_t
2963 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2965 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2966 qidx_t minthresh = txq->ift_size / 8;
2967 if (in_use > 4*minthresh)
2968 return (notify_count);
2969 if (in_use > 2*minthresh)
2970 return (notify_count >> 1);
2971 if (in_use > minthresh)
2972 return (notify_count >> 3);
2976 static inline qidx_t
2977 txq_max_rs_deferred(iflib_txq_t txq)
2979 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2980 qidx_t minthresh = txq->ift_size / 8;
2981 if (txq->ift_in_use > 4*minthresh)
2982 return (notify_count);
2983 if (txq->ift_in_use > 2*minthresh)
2984 return (notify_count >> 1);
2985 if (txq->ift_in_use > minthresh)
2986 return (notify_count >> 2);
2990 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2991 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2993 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2994 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2995 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2997 /* forward compatibility for cxgb */
2998 #define FIRST_QSET(ctx) 0
2999 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3000 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3001 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3002 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3004 /* XXX we should be setting this to something other than zero */
3005 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3006 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3007 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3010 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
3016 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
3017 if (ring || txq->ift_db_pending >= max) {
3018 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3019 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3021 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3022 txq->ift_db_pending = txq->ift_npending = 0;
3030 print_pkt(if_pkt_info_t pi)
3032 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3033 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3034 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3035 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3036 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3037 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3041 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3042 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3043 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3044 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3047 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3049 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3050 struct ether_vlan_header *eh;
3054 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3055 M_WRITABLE(m) == 0) {
3056 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3060 DBG_COUNTER_INC(tx_frees);
3066 * Determine where frame payload starts.
3067 * Jump over vlan headers if already present,
3068 * helpful for QinQ too.
3070 if (__predict_false(m->m_len < sizeof(*eh))) {
3072 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3075 eh = mtod(m, struct ether_vlan_header *);
3076 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3077 pi->ipi_etype = ntohs(eh->evl_proto);
3078 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3080 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3081 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3084 switch (pi->ipi_etype) {
3089 struct ip *ip = NULL;
3090 struct tcphdr *th = NULL;
3093 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3094 if (__predict_false(m->m_len < minthlen)) {
3096 * if this code bloat is causing too much of a hit
3097 * move it to a separate function and mark it noinline
3099 if (m->m_len == pi->ipi_ehdrlen) {
3102 if (n->m_len >= sizeof(*ip)) {
3103 ip = (struct ip *)n->m_data;
3104 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3105 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3108 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3110 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3114 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3116 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3117 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3118 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3121 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3122 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3123 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3125 pi->ipi_ip_hlen = ip->ip_hl << 2;
3126 pi->ipi_ipproto = ip->ip_p;
3127 pi->ipi_flags |= IPI_TX_IPV4;
3129 /* TCP checksum offload may require TCP header length */
3130 if (IS_TX_OFFLOAD4(pi)) {
3131 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3132 if (__predict_false(th == NULL)) {
3134 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3136 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3138 pi->ipi_tcp_hflags = th->th_flags;
3139 pi->ipi_tcp_hlen = th->th_off << 2;
3140 pi->ipi_tcp_seq = th->th_seq;
3143 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3146 * TSO always requires hardware checksum offload.
3148 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3149 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3150 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3151 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3152 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3154 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3158 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3165 case ETHERTYPE_IPV6:
3167 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3169 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3171 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3173 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3176 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3178 /* XXX-BZ this will go badly in case of ext hdrs. */
3179 pi->ipi_ipproto = ip6->ip6_nxt;
3180 pi->ipi_flags |= IPI_TX_IPV6;
3182 /* TCP checksum offload may require TCP header length */
3183 if (IS_TX_OFFLOAD6(pi)) {
3184 if (pi->ipi_ipproto == IPPROTO_TCP) {
3185 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3187 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3190 pi->ipi_tcp_hflags = th->th_flags;
3191 pi->ipi_tcp_hlen = th->th_off << 2;
3192 pi->ipi_tcp_seq = th->th_seq;
3195 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3198 * TSO always requires hardware checksum offload.
3200 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3201 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3202 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3209 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3210 pi->ipi_ip_hlen = 0;
3219 * If dodgy hardware rejects the scatter gather chain we've handed it
3220 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3223 static __noinline struct mbuf *
3224 iflib_remove_mbuf(iflib_txq_t txq)
3227 struct mbuf *m, **ifsd_m;
3229 ifsd_m = txq->ift_sds.ifsd_m;
3230 ntxd = txq->ift_size;
3231 pidx = txq->ift_pidx & (ntxd - 1);
3232 ifsd_m = txq->ift_sds.ifsd_m;
3234 ifsd_m[pidx] = NULL;
3235 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3236 if (txq->ift_sds.ifsd_tso_map != NULL)
3237 bus_dmamap_unload(txq->ift_tso_buf_tag,
3238 txq->ift_sds.ifsd_tso_map[pidx]);
3240 txq->ift_dequeued++;
3245 static inline caddr_t
3246 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3250 caddr_t start, end, cur, next;
3252 ntxd = txq->ift_size;
3253 size = txq->ift_txd_size[qid];
3254 start = txq->ift_ifdi[qid].idi_vaddr;
3256 if (__predict_false(size == 0))
3258 cur = start + size*cidx;
3259 end = start + size*ntxd;
3260 next = CACHE_PTR_NEXT(cur);
3261 return (next < end ? next : start);
3265 * Pad an mbuf to ensure a minimum ethernet frame size.
3266 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3268 static __noinline int
3269 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3272 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3273 * and ARP message is the smallest common payload I can think of
3275 static char pad[18]; /* just zeros */
3277 struct mbuf *new_head;
3279 if (!M_WRITABLE(*m_head)) {
3280 new_head = m_dup(*m_head, M_NOWAIT);
3281 if (new_head == NULL) {
3283 device_printf(dev, "cannot pad short frame, m_dup() failed");
3284 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3285 DBG_COUNTER_INC(tx_frees);
3292 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3293 n > 0; n -= sizeof(pad))
3294 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3299 device_printf(dev, "cannot pad short frame\n");
3300 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3301 DBG_COUNTER_INC(tx_frees);
3309 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3312 if_shared_ctx_t sctx;
3313 if_softc_ctx_t scctx;
3314 bus_dma_tag_t buf_tag;
3315 bus_dma_segment_t *segs;
3316 struct mbuf *m_head, **ifsd_m;
3319 struct if_pkt_info pi;
3321 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3324 sctx = ctx->ifc_sctx;
3325 scctx = &ctx->ifc_softc_ctx;
3326 segs = txq->ift_segs;
3327 ntxd = txq->ift_size;
3332 * If we're doing TSO the next descriptor to clean may be quite far ahead
3334 cidx = txq->ift_cidx;
3335 pidx = txq->ift_pidx;
3336 if (ctx->ifc_flags & IFC_PREFETCH) {
3337 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3338 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3339 next_txd = calc_next_txd(txq, cidx, 0);
3343 /* prefetch the next cache line of mbuf pointers and flags */
3344 prefetch(&txq->ift_sds.ifsd_m[next]);
3345 prefetch(&txq->ift_sds.ifsd_map[next]);
3346 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3348 map = txq->ift_sds.ifsd_map[pidx];
3349 ifsd_m = txq->ift_sds.ifsd_m;
3351 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3352 buf_tag = txq->ift_tso_buf_tag;
3353 max_segs = scctx->isc_tx_tso_segments_max;
3354 map = txq->ift_sds.ifsd_tso_map[pidx];
3355 MPASS(buf_tag != NULL);
3356 MPASS(max_segs > 0);
3358 buf_tag = txq->ift_buf_tag;
3359 max_segs = scctx->isc_tx_nsegments;
3360 map = txq->ift_sds.ifsd_map[pidx];
3362 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3363 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3364 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3366 DBG_COUNTER_INC(encap_txd_encap_fail);
3373 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3375 pi.ipi_qsidx = txq->ift_id;
3376 pi.ipi_len = m_head->m_pkthdr.len;
3377 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3378 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3380 /* deliberate bitwise OR to make one condition */
3381 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3382 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3383 DBG_COUNTER_INC(encap_txd_encap_fail);
3390 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3393 if (__predict_false(err)) {
3396 /* try collapse once and defrag once */
3398 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3399 /* try defrag if collapsing fails */
3404 txq->ift_mbuf_defrag++;
3405 m_head = m_defrag(*m_headp, M_NOWAIT);
3408 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3409 * failed to map an mbuf that was run through m_defrag
3412 if (__predict_false(m_head == NULL || remap > 1))
3419 txq->ift_no_tx_dma_setup++;
3422 txq->ift_no_tx_dma_setup++;
3424 DBG_COUNTER_INC(tx_frees);
3428 txq->ift_map_failed++;
3429 DBG_COUNTER_INC(encap_load_mbuf_fail);
3430 DBG_COUNTER_INC(encap_txd_encap_fail);
3433 ifsd_m[pidx] = m_head;
3435 * XXX assumes a 1 to 1 relationship between segments and
3436 * descriptors - this does not hold true on all drivers, e.g.
3439 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3440 txq->ift_no_desc_avail++;
3441 bus_dmamap_unload(buf_tag, map);
3442 DBG_COUNTER_INC(encap_txq_avail_fail);
3443 DBG_COUNTER_INC(encap_txd_encap_fail);
3444 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3445 GROUPTASK_ENQUEUE(&txq->ift_task);
3449 * On Intel cards we can greatly reduce the number of TX interrupts
3450 * we see by only setting report status on every Nth descriptor.
3451 * However, this also means that the driver will need to keep track
3452 * of the descriptors that RS was set on to check them for the DD bit.
3454 txq->ift_rs_pending += nsegs + 1;
3455 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3456 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3457 pi.ipi_flags |= IPI_TX_INTR;
3458 txq->ift_rs_pending = 0;
3462 pi.ipi_nsegs = nsegs;
3464 MPASS(pidx >= 0 && pidx < txq->ift_size);
3468 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3469 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3470 DBG_COUNTER_INC(tx_encap);
3471 MPASS(pi.ipi_new_pidx < txq->ift_size);
3473 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3474 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3475 ndesc += txq->ift_size;
3479 * drivers can need as many as
3482 MPASS(ndesc <= pi.ipi_nsegs + 2);
3483 MPASS(pi.ipi_new_pidx != pidx);
3485 txq->ift_in_use += ndesc;
3488 * We update the last software descriptor again here because there may
3489 * be a sentinel and/or there may be more mbufs than segments
3491 txq->ift_pidx = pi.ipi_new_pidx;
3492 txq->ift_npending += pi.ipi_ndescs;
3494 *m_headp = m_head = iflib_remove_mbuf(txq);
3496 txq->ift_txd_encap_efbig++;
3505 * err can't possibly be non-zero here, so we don't neet to test it
3506 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3511 txq->ift_mbuf_defrag_failed++;
3512 txq->ift_map_failed++;
3514 DBG_COUNTER_INC(tx_frees);
3516 DBG_COUNTER_INC(encap_txd_encap_fail);
3521 iflib_tx_desc_free(iflib_txq_t txq, int n)
3523 uint32_t qsize, cidx, mask, gen;
3524 struct mbuf *m, **ifsd_m;
3527 cidx = txq->ift_cidx;
3529 qsize = txq->ift_size;
3531 ifsd_m = txq->ift_sds.ifsd_m;
3532 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3536 prefetch(ifsd_m[(cidx + 3) & mask]);
3537 prefetch(ifsd_m[(cidx + 4) & mask]);
3539 if ((m = ifsd_m[cidx]) != NULL) {
3540 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3541 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3542 bus_dmamap_sync(txq->ift_tso_buf_tag,
3543 txq->ift_sds.ifsd_tso_map[cidx],
3544 BUS_DMASYNC_POSTWRITE);
3545 bus_dmamap_unload(txq->ift_tso_buf_tag,
3546 txq->ift_sds.ifsd_tso_map[cidx]);
3548 bus_dmamap_sync(txq->ift_buf_tag,
3549 txq->ift_sds.ifsd_map[cidx],
3550 BUS_DMASYNC_POSTWRITE);
3551 bus_dmamap_unload(txq->ift_buf_tag,
3552 txq->ift_sds.ifsd_map[cidx]);
3554 /* XXX we don't support any drivers that batch packets yet */
3555 MPASS(m->m_nextpkt == NULL);
3557 ifsd_m[cidx] = NULL;
3559 txq->ift_dequeued++;
3561 DBG_COUNTER_INC(tx_frees);
3563 if (__predict_false(++cidx == qsize)) {
3568 txq->ift_cidx = cidx;
3573 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3576 if_ctx_t ctx = txq->ift_ctx;
3578 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3579 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3582 * Need a rate-limiting check so that this isn't called every time
3584 iflib_tx_credits_update(ctx, txq);
3585 reclaim = DESC_RECLAIMABLE(txq);
3587 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3589 if (iflib_verbose_debug) {
3590 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3591 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3597 iflib_tx_desc_free(txq, reclaim);
3598 txq->ift_cleaned += reclaim;
3599 txq->ift_in_use -= reclaim;
3604 static struct mbuf **
3605 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3608 struct mbuf **items;
3611 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3612 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3614 prefetch(items[(cidx + offset) & (size-1)]);
3615 if (remaining > 1) {
3616 prefetch2cachelines(&items[next]);
3617 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3618 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3619 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3621 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3625 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3628 ifmp_ring_check_drainage(txq->ift_br, budget);
3632 iflib_txq_can_drain(struct ifmp_ring *r)
3634 iflib_txq_t txq = r->cookie;
3635 if_ctx_t ctx = txq->ift_ctx;
3637 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3639 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3640 BUS_DMASYNC_POSTREAD);
3641 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3646 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3648 iflib_txq_t txq = r->cookie;
3649 if_ctx_t ctx = txq->ift_ctx;
3650 if_t ifp = ctx->ifc_ifp;
3651 struct mbuf *m, **mp;
3652 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3653 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3654 bool do_prefetch, rang, ring;
3656 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3657 !LINK_ACTIVE(ctx))) {
3658 DBG_COUNTER_INC(txq_drain_notready);
3661 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3662 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3663 avail = IDXDIFF(pidx, cidx, r->size);
3664 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3665 DBG_COUNTER_INC(txq_drain_flushing);
3666 for (i = 0; i < avail; i++) {
3667 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3668 m_free(r->items[(cidx + i) & (r->size-1)]);
3669 r->items[(cidx + i) & (r->size-1)] = NULL;
3674 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3675 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3677 callout_stop(&txq->ift_timer);
3678 CALLOUT_UNLOCK(txq);
3679 DBG_COUNTER_INC(txq_drain_oactive);
3683 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3684 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3685 count = MIN(avail, TX_BATCH_SIZE);
3687 if (iflib_verbose_debug)
3688 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3689 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3691 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3692 txq_avail = TXQ_AVAIL(txq);
3694 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3695 int rem = do_prefetch ? count - i : 0;
3697 mp = _ring_peek_one(r, cidx, i, rem);
3698 MPASS(mp != NULL && *mp != NULL);
3699 if (__predict_false(*mp == (struct mbuf *)txq)) {
3703 in_use_prev = txq->ift_in_use;
3704 err = iflib_encap(txq, mp);
3705 if (__predict_false(err)) {
3706 /* no room - bail out */
3710 /* we can't send this packet - skip it */
3716 DBG_COUNTER_INC(tx_sent);
3717 bytes_sent += m->m_pkthdr.len;
3718 mcast_sent += !!(m->m_flags & M_MCAST);
3719 txq_avail = TXQ_AVAIL(txq);
3721 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3722 ETHER_BPF_MTAP(ifp, m);
3723 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3725 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3728 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3729 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3730 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3731 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3732 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3734 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3736 if (iflib_verbose_debug)
3737 printf("consumed=%d\n", consumed);
3743 iflib_txq_drain_always(struct ifmp_ring *r)
3749 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3757 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3759 callout_stop(&txq->ift_timer);
3760 CALLOUT_UNLOCK(txq);
3762 avail = IDXDIFF(pidx, cidx, r->size);
3763 for (i = 0; i < avail; i++) {
3764 mp = _ring_peek_one(r, cidx, i, avail - i);
3765 if (__predict_false(*mp == (struct mbuf *)txq))
3768 DBG_COUNTER_INC(tx_frees);
3770 MPASS(ifmp_ring_is_stalled(r) == 0);
3775 iflib_ifmp_purge(iflib_txq_t txq)
3777 struct ifmp_ring *r;
3780 r->drain = iflib_txq_drain_free;
3781 r->can_drain = iflib_txq_drain_always;
3783 ifmp_ring_check_drainage(r, r->size);
3785 r->drain = iflib_txq_drain;
3786 r->can_drain = iflib_txq_can_drain;
3790 _task_fn_tx(void *context)
3792 iflib_txq_t txq = context;
3793 if_ctx_t ctx = txq->ift_ctx;
3794 if_t ifp = ctx->ifc_ifp;
3795 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3797 #ifdef IFLIB_DIAGNOSTICS
3798 txq->ift_cpu_exec_count[curcpu]++;
3800 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3803 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3804 netmap_tx_irq(ifp, txq->ift_id))
3808 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3809 iflib_altq_if_start(ifp);
3811 if (txq->ift_db_pending)
3812 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3814 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3816 * When abdicating, we always need to check drainage, not just when we don't enqueue
3819 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3823 if (ctx->ifc_flags & IFC_LEGACY)
3824 IFDI_INTR_ENABLE(ctx);
3826 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3830 _task_fn_rx(void *context)
3832 iflib_rxq_t rxq = context;
3833 if_ctx_t ctx = rxq->ifr_ctx;
3841 #ifdef IFLIB_DIAGNOSTICS
3842 rxq->ifr_cpu_exec_count[curcpu]++;
3844 DBG_COUNTER_INC(task_fn_rxs);
3845 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3848 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3849 if (nmirq != NM_IRQ_PASS) {
3850 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3854 budget = ctx->ifc_sysctl_rx_budget;
3856 budget = 16; /* XXX */
3857 more = iflib_rxeof(rxq, budget);
3861 if ((more & IFLIB_RXEOF_MORE) == 0) {
3862 if (ctx->ifc_flags & IFC_LEGACY)
3863 IFDI_INTR_ENABLE(ctx);
3865 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3866 DBG_COUNTER_INC(rx_intr_enables);
3868 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3871 if (more & IFLIB_RXEOF_MORE)
3872 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3873 else if (more & IFLIB_RXEOF_EMPTY)
3874 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3878 _task_fn_admin(void *context)
3880 if_ctx_t ctx = context;
3881 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3884 bool oactive, running, do_reset, do_watchdog, in_detach;
3885 uint32_t reset_on = hz / 2;
3888 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3889 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3890 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3891 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3892 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3893 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3896 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3902 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3904 callout_stop(&txq->ift_timer);
3905 CALLOUT_UNLOCK(txq);
3908 ctx->ifc_watchdog_events++;
3909 IFDI_WATCHDOG_RESET(ctx);
3911 IFDI_UPDATE_ADMIN_STATUS(ctx);
3912 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3915 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3916 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3918 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3920 IFDI_LINK_INTR_ENABLE(ctx);
3922 iflib_if_init_locked(ctx);
3925 if (LINK_ACTIVE(ctx) == 0)
3927 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3928 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3932 _task_fn_iov(void *context)
3934 if_ctx_t ctx = context;
3936 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3937 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3941 IFDI_VFLR_HANDLE(ctx);
3946 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3949 if_int_delay_info_t info;
3952 info = (if_int_delay_info_t)arg1;
3953 ctx = info->iidi_ctx;
3954 info->iidi_req = req;
3955 info->iidi_oidp = oidp;
3957 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3962 /*********************************************************************
3966 **********************************************************************/
3969 iflib_if_init_locked(if_ctx_t ctx)
3972 iflib_init_locked(ctx);
3976 iflib_if_init(void *arg)
3981 iflib_if_init_locked(ctx);
3986 iflib_if_transmit(if_t ifp, struct mbuf *m)
3988 if_ctx_t ctx = if_getsoftc(ifp);
3992 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3994 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3995 DBG_COUNTER_INC(tx_frees);
4000 MPASS(m->m_nextpkt == NULL);
4001 /* ALTQ-enabled interfaces always use queue 0. */
4003 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
4004 qidx = QIDX(ctx, m);
4006 * XXX calculate buf_ring based on flowid (divvy up bits?)
4008 txq = &ctx->ifc_txqs[qidx];
4010 #ifdef DRIVER_BACKPRESSURE
4011 if (txq->ift_closed) {
4013 next = m->m_nextpkt;
4014 m->m_nextpkt = NULL;
4016 DBG_COUNTER_INC(tx_frees);
4028 next = next->m_nextpkt;
4029 } while (next != NULL);
4031 if (count > nitems(marr))
4032 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4033 /* XXX check nextpkt */
4035 /* XXX simplify for now */
4036 DBG_COUNTER_INC(tx_frees);
4039 for (next = m, i = 0; next != NULL; i++) {
4041 next = next->m_nextpkt;
4042 mp[i]->m_nextpkt = NULL;
4045 DBG_COUNTER_INC(tx_seen);
4046 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4049 GROUPTASK_ENQUEUE(&txq->ift_task);
4052 GROUPTASK_ENQUEUE(&txq->ift_task);
4053 /* support forthcoming later */
4054 #ifdef DRIVER_BACKPRESSURE
4055 txq->ift_closed = TRUE;
4057 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4059 DBG_COUNTER_INC(tx_frees);
4067 * The overall approach to integrating iflib with ALTQ is to continue to use
4068 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4069 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4070 * is redundant/unnecessary, but doing so minimizes the amount of
4071 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4072 * redundantly queueing to an intermediate mp_ring is swamped by the
4073 * performance limitations inherent in using ALTQ.
4075 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4076 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4077 * given interface. If ALTQ is enabled for an interface, then all
4078 * transmitted packets for that interface will be submitted to the ALTQ
4079 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4080 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4081 * update stats that the iflib machinery handles, and which is sensitve to
4082 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4083 * will be installed as the start routine for use by ALTQ facilities that
4084 * need to trigger queue drains on a scheduled basis.
4088 iflib_altq_if_start(if_t ifp)
4090 struct ifaltq *ifq = &ifp->if_snd;
4094 IFQ_DEQUEUE_NOLOCK(ifq, m);
4096 iflib_if_transmit(ifp, m);
4097 IFQ_DEQUEUE_NOLOCK(ifq, m);
4103 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4107 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4108 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4110 iflib_altq_if_start(ifp);
4112 err = iflib_if_transmit(ifp, m);
4119 iflib_if_qflush(if_t ifp)
4121 if_ctx_t ctx = if_getsoftc(ifp);
4122 iflib_txq_t txq = ctx->ifc_txqs;
4126 ctx->ifc_flags |= IFC_QFLUSH;
4128 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4129 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4130 iflib_txq_check_drain(txq, 0);
4132 ctx->ifc_flags &= ~IFC_QFLUSH;
4136 * When ALTQ is enabled, this will also take care of purging the
4142 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4143 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4144 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4145 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4148 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4150 if_ctx_t ctx = if_getsoftc(ifp);
4151 struct ifreq *ifr = (struct ifreq *)data;
4152 #if defined(INET) || defined(INET6)
4153 struct ifaddr *ifa = (struct ifaddr *)data;
4155 bool avoid_reset = false;
4156 int err = 0, reinit = 0, bits;
4161 if (ifa->ifa_addr->sa_family == AF_INET)
4165 if (ifa->ifa_addr->sa_family == AF_INET6)
4169 ** Calling init results in link renegotiation,
4170 ** so we avoid doing it when possible.
4173 if_setflagbits(ifp, IFF_UP,0);
4174 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4177 if (!(if_getflags(ifp) & IFF_NOARP))
4178 arp_ifinit(ifp, ifa);
4181 err = ether_ioctl(ifp, command, data);
4185 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4189 bits = if_getdrvflags(ifp);
4190 /* stop the driver and free any clusters before proceeding */
4193 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4195 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4196 ctx->ifc_flags |= IFC_MULTISEG;
4198 ctx->ifc_flags &= ~IFC_MULTISEG;
4200 err = if_setmtu(ifp, ifr->ifr_mtu);
4202 iflib_init_locked(ctx);
4204 if_setdrvflags(ifp, bits);
4210 if (if_getflags(ifp) & IFF_UP) {
4211 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4212 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4213 (IFF_PROMISC | IFF_ALLMULTI)) {
4215 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4220 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4223 ctx->ifc_if_flags = if_getflags(ifp);
4228 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4230 IFDI_INTR_DISABLE(ctx);
4231 IFDI_MULTI_SET(ctx);
4232 IFDI_INTR_ENABLE(ctx);
4238 IFDI_MEDIA_SET(ctx);
4243 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4247 struct ifi2creq i2c;
4249 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4252 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4256 if (i2c.len > sizeof(i2c.data)) {
4261 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4262 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4268 int mask, setmask, oldmask;
4270 oldmask = if_getcapenable(ifp);
4271 mask = ifr->ifr_reqcap ^ oldmask;
4272 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4275 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4277 setmask |= (mask & IFCAP_FLAGS);
4278 setmask |= (mask & IFCAP_WOL);
4281 * If any RX csum has changed, change all the ones that
4282 * are supported by the driver.
4284 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4285 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4286 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4290 * want to ensure that traffic has stopped before we change any of the flags
4294 bits = if_getdrvflags(ifp);
4295 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4298 if_togglecapenable(ifp, setmask);
4300 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4301 iflib_init_locked(ctx);
4303 if_setdrvflags(ifp, bits);
4310 case SIOCGPRIVATE_0:
4314 err = IFDI_PRIV_IOCTL(ctx, command, data);
4318 err = ether_ioctl(ifp, command, data);
4327 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4329 if_ctx_t ctx = if_getsoftc(ifp);
4331 return (IFDI_GET_COUNTER(ctx, cnt));
4334 /*********************************************************************
4336 * OTHER FUNCTIONS EXPORTED TO THE STACK
4338 **********************************************************************/
4341 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4343 if_ctx_t ctx = if_getsoftc(ifp);
4345 if ((void *)ctx != arg)
4348 if ((vtag == 0) || (vtag > 4095))
4351 if (iflib_in_detach(ctx))
4355 /* Driver may need all untagged packets to be flushed */
4356 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4358 IFDI_VLAN_REGISTER(ctx, vtag);
4359 /* Re-init to load the changes, if required */
4360 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4361 iflib_init_locked(ctx);
4366 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4368 if_ctx_t ctx = if_getsoftc(ifp);
4370 if ((void *)ctx != arg)
4373 if ((vtag == 0) || (vtag > 4095))
4377 /* Driver may need all tagged packets to be flushed */
4378 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4380 IFDI_VLAN_UNREGISTER(ctx, vtag);
4381 /* Re-init to load the changes, if required */
4382 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4383 iflib_init_locked(ctx);
4388 iflib_led_func(void *arg, int onoff)
4393 IFDI_LED_FUNC(ctx, onoff);
4397 /*********************************************************************
4399 * BUS FUNCTION DEFINITIONS
4401 **********************************************************************/
4404 iflib_device_probe(device_t dev)
4406 const pci_vendor_info_t *ent;
4407 if_shared_ctx_t sctx;
4408 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4409 uint16_t pci_vendor_id;
4411 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4414 pci_vendor_id = pci_get_vendor(dev);
4415 pci_device_id = pci_get_device(dev);
4416 pci_subvendor_id = pci_get_subvendor(dev);
4417 pci_subdevice_id = pci_get_subdevice(dev);
4418 pci_rev_id = pci_get_revid(dev);
4419 if (sctx->isc_parse_devinfo != NULL)
4420 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4422 ent = sctx->isc_vendor_info;
4423 while (ent->pvi_vendor_id != 0) {
4424 if (pci_vendor_id != ent->pvi_vendor_id) {
4428 if ((pci_device_id == ent->pvi_device_id) &&
4429 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4430 (ent->pvi_subvendor_id == 0)) &&
4431 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4432 (ent->pvi_subdevice_id == 0)) &&
4433 ((pci_rev_id == ent->pvi_rev_id) ||
4434 (ent->pvi_rev_id == 0))) {
4435 device_set_desc_copy(dev, ent->pvi_name);
4436 /* this needs to be changed to zero if the bus probing code
4437 * ever stops re-probing on best match because the sctx
4438 * may have its values over written by register calls
4439 * in subsequent probes
4441 return (BUS_PROBE_DEFAULT);
4449 iflib_device_probe_vendor(device_t dev)
4453 probe = iflib_device_probe(dev);
4454 if (probe == BUS_PROBE_DEFAULT)
4455 return (BUS_PROBE_VENDOR);
4461 iflib_reset_qvalues(if_ctx_t ctx)
4463 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4464 if_shared_ctx_t sctx = ctx->ifc_sctx;
4465 device_t dev = ctx->ifc_dev;
4468 if (ctx->ifc_sysctl_ntxqs != 0)
4469 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4470 if (ctx->ifc_sysctl_nrxqs != 0)
4471 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4473 for (i = 0; i < sctx->isc_ntxqs; i++) {
4474 if (ctx->ifc_sysctl_ntxds[i] != 0)
4475 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4477 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4480 for (i = 0; i < sctx->isc_nrxqs; i++) {
4481 if (ctx->ifc_sysctl_nrxds[i] != 0)
4482 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4484 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4487 for (i = 0; i < sctx->isc_nrxqs; i++) {
4488 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4489 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4490 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4491 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4493 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4494 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4495 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4496 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4498 if (!powerof2(scctx->isc_nrxd[i])) {
4499 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4500 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4501 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4505 for (i = 0; i < sctx->isc_ntxqs; i++) {
4506 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4507 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4508 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4509 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4511 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4512 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4513 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4514 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4516 if (!powerof2(scctx->isc_ntxd[i])) {
4517 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4518 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4519 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4525 iflib_add_pfil(if_ctx_t ctx)
4527 struct pfil_head *pfil;
4528 struct pfil_head_args pa;
4532 pa.pa_version = PFIL_VERSION;
4533 pa.pa_flags = PFIL_IN;
4534 pa.pa_type = PFIL_TYPE_ETHERNET;
4535 pa.pa_headname = ctx->ifc_ifp->if_xname;
4536 pfil = pfil_head_register(&pa);
4538 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4544 iflib_rem_pfil(if_ctx_t ctx)
4546 struct pfil_head *pfil;
4550 rxq = ctx->ifc_rxqs;
4552 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4555 pfil_head_unregister(pfil);
4559 get_ctx_core_offset(if_ctx_t ctx)
4561 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4562 struct cpu_offset *op;
4564 uint16_t ret = ctx->ifc_sysctl_core_offset;
4566 if (ret != CORE_OFFSET_UNSPECIFIED)
4569 if (ctx->ifc_sysctl_separate_txrx)
4570 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4572 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4574 mtx_lock(&cpu_offset_mtx);
4575 SLIST_FOREACH(op, &cpu_offsets, entries) {
4576 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4579 MPASS(op->refcount < UINT_MAX);
4584 if (ret == CORE_OFFSET_UNSPECIFIED) {
4586 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4589 device_printf(ctx->ifc_dev,
4590 "allocation for cpu offset failed.\n");
4594 CPU_COPY(&ctx->ifc_cpus, &op->set);
4595 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4598 mtx_unlock(&cpu_offset_mtx);
4604 unref_ctx_core_offset(if_ctx_t ctx)
4606 struct cpu_offset *op, *top;
4608 mtx_lock(&cpu_offset_mtx);
4609 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4610 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4611 MPASS(op->refcount > 0);
4613 if (op->refcount == 0) {
4614 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4620 mtx_unlock(&cpu_offset_mtx);
4624 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4628 if_softc_ctx_t scctx;
4629 kobjop_desc_t kobj_desc;
4630 kobj_method_t *kobj_method;
4632 int num_txd, num_rxd;
4634 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4637 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4638 device_set_softc(dev, ctx);
4639 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4642 ctx->ifc_sctx = sctx;
4644 ctx->ifc_softc = sc;
4646 if ((err = iflib_register(ctx)) != 0) {
4647 device_printf(dev, "iflib_register failed %d\n", err);
4650 iflib_add_device_sysctl_pre(ctx);
4652 scctx = &ctx->ifc_softc_ctx;
4655 iflib_reset_qvalues(ctx);
4657 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4658 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4661 _iflib_pre_assert(scctx);
4662 ctx->ifc_txrx = *scctx->isc_txrx;
4664 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4665 ctx->ifc_mediap = scctx->isc_media;
4668 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4669 MPASS(scctx->isc_tx_csum_flags);
4672 if_setcapabilities(ifp,
4673 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4674 if_setcapenable(ifp,
4675 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4677 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4678 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4679 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4680 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4682 num_txd = iflib_num_tx_descs(ctx);
4683 num_rxd = iflib_num_rx_descs(ctx);
4685 /* XXX change for per-queue sizes */
4686 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4689 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4690 scctx->isc_tx_nsegments = max(1, num_txd /
4691 MAX_SINGLE_PACKET_FRACTION);
4692 if (scctx->isc_tx_tso_segments_max > num_txd /
4693 MAX_SINGLE_PACKET_FRACTION)
4694 scctx->isc_tx_tso_segments_max = max(1,
4695 num_txd / MAX_SINGLE_PACKET_FRACTION);
4697 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4698 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4700 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4703 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4706 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4707 * into account. In the worst case, each of these calls will
4708 * add another mbuf and, thus, the requirement for another DMA
4709 * segment. So for best performance, it doesn't make sense to
4710 * advertize a maximum of TSO segments that typically will
4711 * require defragmentation in iflib_encap().
4713 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4714 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4716 if (scctx->isc_rss_table_size == 0)
4717 scctx->isc_rss_table_size = 64;
4718 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4720 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4721 /* XXX format name */
4722 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4723 NULL, NULL, "admin");
4725 /* Set up cpu set. If it fails, use the set of all CPUs. */
4726 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4727 device_printf(dev, "Unable to fetch CPU list\n");
4728 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4730 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4733 ** Now set up MSI or MSI-X, should return us the number of supported
4734 ** vectors (will be 1 for a legacy interrupt and MSI).
4736 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4737 msix = scctx->isc_vectors;
4738 } else if (scctx->isc_msix_bar != 0)
4740 * The simple fact that isc_msix_bar is not 0 does not mean we
4741 * we have a good value there that is known to work.
4743 msix = iflib_msix_init(ctx);
4745 scctx->isc_vectors = 1;
4746 scctx->isc_ntxqsets = 1;
4747 scctx->isc_nrxqsets = 1;
4748 scctx->isc_intr = IFLIB_INTR_LEGACY;
4751 /* Get memory for the station queues */
4752 if ((err = iflib_queues_alloc(ctx))) {
4753 device_printf(dev, "Unable to allocate queue memory\n");
4754 goto fail_intr_free;
4757 if ((err = iflib_qset_structures_setup(ctx)))
4761 * Now that we know how many queues there are, get the core offset.
4763 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4767 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4768 * aren't the default NULL implementation.
4770 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4771 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4773 if (kobj_method == &kobj_desc->deflt) {
4775 "MSI-X requires ifdi_rx_queue_intr_enable method");
4779 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4780 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4782 if (kobj_method == &kobj_desc->deflt) {
4784 "MSI-X requires ifdi_tx_queue_intr_enable method");
4790 * Assign the MSI-X vectors.
4791 * Note that the default NULL ifdi_msix_intr_assign method will
4794 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4796 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4800 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4802 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4806 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4807 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4812 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4814 goto fail_intr_free;
4817 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4819 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4820 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4825 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4826 * This must appear after the call to ether_ifattach() because
4827 * ether_ifattach() sets if_hdrlen to the default value.
4829 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4830 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4832 if ((err = iflib_netmap_attach(ctx))) {
4833 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4838 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4840 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4841 iflib_add_device_sysctl_post(ctx);
4842 iflib_add_pfil(ctx);
4843 ctx->ifc_flags |= IFC_INIT_DONE;
4849 ether_ifdetach(ctx->ifc_ifp);
4851 iflib_free_intr_mem(ctx);
4853 iflib_tx_structures_free(ctx);
4854 iflib_rx_structures_free(ctx);
4855 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4859 iflib_deregister(ctx);
4861 device_set_softc(ctx->ifc_dev, NULL);
4862 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4863 free(ctx->ifc_softc, M_IFLIB);
4869 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4870 struct iflib_cloneattach_ctx *clctx)
4872 int num_txd, num_rxd;
4876 if_softc_ctx_t scctx;
4880 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4881 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4882 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4883 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4884 ctx->ifc_flags |= IFC_PSEUDO;
4886 ctx->ifc_sctx = sctx;
4887 ctx->ifc_softc = sc;
4890 if ((err = iflib_register(ctx)) != 0) {
4891 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4894 iflib_add_device_sysctl_pre(ctx);
4896 scctx = &ctx->ifc_softc_ctx;
4899 iflib_reset_qvalues(ctx);
4901 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4902 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4905 if (sctx->isc_flags & IFLIB_GEN_MAC)
4906 ether_gen_addr(ifp, &ctx->ifc_mac);
4907 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4908 clctx->cc_params)) != 0) {
4909 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4913 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4914 MPASS(scctx->isc_tx_csum_flags);
4917 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4918 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4920 ifp->if_flags |= IFF_NOGROUP;
4921 if (sctx->isc_flags & IFLIB_PSEUDO) {
4922 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4923 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4924 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4925 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4927 if_attach(ctx->ifc_ifp);
4928 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4931 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4932 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4938 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4939 * This must appear after the call to ether_ifattach() because
4940 * ether_ifattach() sets if_hdrlen to the default value.
4942 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4943 if_setifheaderlen(ifp,
4944 sizeof(struct ether_vlan_header));
4946 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4947 iflib_add_device_sysctl_post(ctx);
4948 ctx->ifc_flags |= IFC_INIT_DONE;
4952 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4953 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4954 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4956 _iflib_pre_assert(scctx);
4957 ctx->ifc_txrx = *scctx->isc_txrx;
4959 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4960 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4961 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4962 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4964 num_txd = iflib_num_tx_descs(ctx);
4965 num_rxd = iflib_num_rx_descs(ctx);
4967 /* XXX change for per-queue sizes */
4968 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4971 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4972 scctx->isc_tx_nsegments = max(1, num_txd /
4973 MAX_SINGLE_PACKET_FRACTION);
4974 if (scctx->isc_tx_tso_segments_max > num_txd /
4975 MAX_SINGLE_PACKET_FRACTION)
4976 scctx->isc_tx_tso_segments_max = max(1,
4977 num_txd / MAX_SINGLE_PACKET_FRACTION);
4979 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4980 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4982 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4985 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4988 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4989 * into account. In the worst case, each of these calls will
4990 * add another mbuf and, thus, the requirement for another DMA
4991 * segment. So for best performance, it doesn't make sense to
4992 * advertize a maximum of TSO segments that typically will
4993 * require defragmentation in iflib_encap().
4995 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4996 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4998 if (scctx->isc_rss_table_size == 0)
4999 scctx->isc_rss_table_size = 64;
5000 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5002 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5003 /* XXX format name */
5004 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5005 NULL, NULL, "admin");
5007 /* XXX --- can support > 1 -- but keep it simple for now */
5008 scctx->isc_intr = IFLIB_INTR_LEGACY;
5010 /* Get memory for the station queues */
5011 if ((err = iflib_queues_alloc(ctx))) {
5012 device_printf(dev, "Unable to allocate queue memory\n");
5013 goto fail_iflib_detach;
5016 if ((err = iflib_qset_structures_setup(ctx))) {
5017 device_printf(dev, "qset structure setup failed %d\n", err);
5022 * XXX What if anything do we want to do about interrupts?
5024 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5025 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5026 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5031 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5032 * This must appear after the call to ether_ifattach() because
5033 * ether_ifattach() sets if_hdrlen to the default value.
5035 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5036 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5038 /* XXX handle more than one queue */
5039 for (i = 0; i < scctx->isc_nrxqsets; i++)
5040 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5044 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5045 iflib_add_device_sysctl_post(ctx);
5046 ctx->ifc_flags |= IFC_INIT_DONE;
5051 ether_ifdetach(ctx->ifc_ifp);
5053 iflib_tx_structures_free(ctx);
5054 iflib_rx_structures_free(ctx);
5059 iflib_deregister(ctx);
5061 free(ctx->ifc_softc, M_IFLIB);
5067 iflib_pseudo_deregister(if_ctx_t ctx)
5069 if_t ifp = ctx->ifc_ifp;
5070 if_shared_ctx_t sctx = ctx->ifc_sctx;
5074 struct taskqgroup *tqg;
5077 /* Unregister VLAN event handlers early */
5078 iflib_unregister_vlan_handlers(ctx);
5080 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5081 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5085 ether_ifdetach(ifp);
5087 /* XXX drain any dependent tasks */
5088 tqg = qgroup_if_io_tqg;
5089 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5090 callout_drain(&txq->ift_timer);
5091 if (txq->ift_task.gt_uniq != NULL)
5092 taskqgroup_detach(tqg, &txq->ift_task);
5094 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5095 callout_drain(&rxq->ifr_watchdog);
5096 if (rxq->ifr_task.gt_uniq != NULL)
5097 taskqgroup_detach(tqg, &rxq->ifr_task);
5099 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5100 free(fl->ifl_rx_bitmap, M_IFLIB);
5102 tqg = qgroup_if_config_tqg;
5103 if (ctx->ifc_admin_task.gt_uniq != NULL)
5104 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5105 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5106 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5108 iflib_tx_structures_free(ctx);
5109 iflib_rx_structures_free(ctx);
5111 iflib_deregister(ctx);
5113 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5114 free(ctx->ifc_softc, M_IFLIB);
5120 iflib_device_attach(device_t dev)
5123 if_shared_ctx_t sctx;
5125 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5128 pci_enable_busmaster(dev);
5130 return (iflib_device_register(dev, NULL, sctx, &ctx));
5134 iflib_device_deregister(if_ctx_t ctx)
5136 if_t ifp = ctx->ifc_ifp;
5139 device_t dev = ctx->ifc_dev;
5141 struct taskqgroup *tqg;
5144 /* Make sure VLANS are not using driver */
5145 if (if_vlantrunkinuse(ifp)) {
5146 device_printf(dev, "Vlan in use, detach first\n");
5150 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5151 device_printf(dev, "SR-IOV in use; detach first.\n");
5157 ctx->ifc_flags |= IFC_IN_DETACH;
5160 /* Unregister VLAN handlers before calling iflib_stop() */
5161 iflib_unregister_vlan_handlers(ctx);
5163 iflib_netmap_detach(ifp);
5164 ether_ifdetach(ifp);
5170 iflib_rem_pfil(ctx);
5171 if (ctx->ifc_led_dev != NULL)
5172 led_destroy(ctx->ifc_led_dev);
5173 /* XXX drain any dependent tasks */
5174 tqg = qgroup_if_io_tqg;
5175 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5176 callout_drain(&txq->ift_timer);
5177 if (txq->ift_task.gt_uniq != NULL)
5178 taskqgroup_detach(tqg, &txq->ift_task);
5180 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5181 if (rxq->ifr_task.gt_uniq != NULL)
5182 taskqgroup_detach(tqg, &rxq->ifr_task);
5184 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5185 free(fl->ifl_rx_bitmap, M_IFLIB);
5187 tqg = qgroup_if_config_tqg;
5188 if (ctx->ifc_admin_task.gt_uniq != NULL)
5189 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5190 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5191 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5196 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5197 iflib_free_intr_mem(ctx);
5199 bus_generic_detach(dev);
5201 iflib_tx_structures_free(ctx);
5202 iflib_rx_structures_free(ctx);
5204 iflib_deregister(ctx);
5206 device_set_softc(ctx->ifc_dev, NULL);
5207 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5208 free(ctx->ifc_softc, M_IFLIB);
5209 unref_ctx_core_offset(ctx);
5215 iflib_free_intr_mem(if_ctx_t ctx)
5218 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5219 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5221 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5222 pci_release_msi(ctx->ifc_dev);
5224 if (ctx->ifc_msix_mem != NULL) {
5225 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5226 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5227 ctx->ifc_msix_mem = NULL;
5232 iflib_device_detach(device_t dev)
5234 if_ctx_t ctx = device_get_softc(dev);
5236 return (iflib_device_deregister(ctx));
5240 iflib_device_suspend(device_t dev)
5242 if_ctx_t ctx = device_get_softc(dev);
5248 return bus_generic_suspend(dev);
5251 iflib_device_shutdown(device_t dev)
5253 if_ctx_t ctx = device_get_softc(dev);
5259 return bus_generic_suspend(dev);
5263 iflib_device_resume(device_t dev)
5265 if_ctx_t ctx = device_get_softc(dev);
5266 iflib_txq_t txq = ctx->ifc_txqs;
5270 iflib_if_init_locked(ctx);
5272 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5273 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5275 return (bus_generic_resume(dev));
5279 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5282 if_ctx_t ctx = device_get_softc(dev);
5285 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5292 iflib_device_iov_uninit(device_t dev)
5294 if_ctx_t ctx = device_get_softc(dev);
5297 IFDI_IOV_UNINIT(ctx);
5302 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5305 if_ctx_t ctx = device_get_softc(dev);
5308 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5314 /*********************************************************************
5316 * MODULE FUNCTION DEFINITIONS
5318 **********************************************************************/
5321 * - Start a fast taskqueue thread for each core
5322 * - Start a taskqueue for control operations
5325 iflib_module_init(void)
5331 iflib_module_event_handler(module_t mod, int what, void *arg)
5337 if ((err = iflib_module_init()) != 0)
5343 return (EOPNOTSUPP);
5349 /*********************************************************************
5351 * PUBLIC FUNCTION DEFINITIONS
5352 * ordered as in iflib.h
5354 **********************************************************************/
5357 _iflib_assert(if_shared_ctx_t sctx)
5361 MPASS(sctx->isc_tx_maxsize);
5362 MPASS(sctx->isc_tx_maxsegsize);
5364 MPASS(sctx->isc_rx_maxsize);
5365 MPASS(sctx->isc_rx_nsegments);
5366 MPASS(sctx->isc_rx_maxsegsize);
5368 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5369 for (i = 0; i < sctx->isc_nrxqs; i++) {
5370 MPASS(sctx->isc_nrxd_min[i]);
5371 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5372 MPASS(sctx->isc_nrxd_max[i]);
5373 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5374 MPASS(sctx->isc_nrxd_default[i]);
5375 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5378 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5379 for (i = 0; i < sctx->isc_ntxqs; i++) {
5380 MPASS(sctx->isc_ntxd_min[i]);
5381 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5382 MPASS(sctx->isc_ntxd_max[i]);
5383 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5384 MPASS(sctx->isc_ntxd_default[i]);
5385 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5390 _iflib_pre_assert(if_softc_ctx_t scctx)
5393 MPASS(scctx->isc_txrx->ift_txd_encap);
5394 MPASS(scctx->isc_txrx->ift_txd_flush);
5395 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5396 MPASS(scctx->isc_txrx->ift_rxd_available);
5397 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5398 MPASS(scctx->isc_txrx->ift_rxd_refill);
5399 MPASS(scctx->isc_txrx->ift_rxd_flush);
5403 iflib_register(if_ctx_t ctx)
5405 if_shared_ctx_t sctx = ctx->ifc_sctx;
5406 driver_t *driver = sctx->isc_driver;
5407 device_t dev = ctx->ifc_dev;
5412 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5413 _iflib_assert(sctx);
5416 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5417 if (sctx->isc_flags & IFLIB_PSEUDO) {
5418 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5424 ifp = ctx->ifc_ifp = if_alloc(type);
5426 device_printf(dev, "can not allocate ifnet structure\n");
5431 * Initialize our context's device specific methods
5433 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5434 kobj_class_compile((kobj_class_t) driver);
5436 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5437 if_setsoftc(ifp, ctx);
5438 if_setdev(ifp, dev);
5439 if_setinitfn(ifp, iflib_if_init);
5440 if_setioctlfn(ifp, iflib_if_ioctl);
5442 if_setstartfn(ifp, iflib_altq_if_start);
5443 if_settransmitfn(ifp, iflib_altq_if_transmit);
5444 if_setsendqready(ifp);
5446 if_settransmitfn(ifp, iflib_if_transmit);
5448 if_setqflushfn(ifp, iflib_if_qflush);
5449 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5451 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5452 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5453 iflags |= IFF_POINTOPOINT;
5455 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5456 if_setflags(ifp, iflags);
5457 ctx->ifc_vlan_attach_event =
5458 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5459 EVENTHANDLER_PRI_FIRST);
5460 ctx->ifc_vlan_detach_event =
5461 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5462 EVENTHANDLER_PRI_FIRST);
5464 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5465 ctx->ifc_mediap = &ctx->ifc_media;
5466 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5467 iflib_media_change, iflib_media_status);
5473 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5475 /* Unregister VLAN events */
5476 if (ctx->ifc_vlan_attach_event != NULL) {
5477 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5478 ctx->ifc_vlan_attach_event = NULL;
5480 if (ctx->ifc_vlan_detach_event != NULL) {
5481 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5482 ctx->ifc_vlan_detach_event = NULL;
5488 iflib_deregister(if_ctx_t ctx)
5490 if_t ifp = ctx->ifc_ifp;
5492 /* Remove all media */
5493 ifmedia_removeall(&ctx->ifc_media);
5495 /* Ensure that VLAN event handlers are unregistered */
5496 iflib_unregister_vlan_handlers(ctx);
5498 /* Release kobject reference */
5499 kobj_delete((kobj_t) ctx, NULL);
5501 /* Free the ifnet structure */
5504 STATE_LOCK_DESTROY(ctx);
5506 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5507 CTX_LOCK_DESTROY(ctx);
5511 iflib_queues_alloc(if_ctx_t ctx)
5513 if_shared_ctx_t sctx = ctx->ifc_sctx;
5514 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5515 device_t dev = ctx->ifc_dev;
5516 int nrxqsets = scctx->isc_nrxqsets;
5517 int ntxqsets = scctx->isc_ntxqsets;
5520 iflib_fl_t fl = NULL;
5521 int i, j, cpu, err, txconf, rxconf;
5522 iflib_dma_info_t ifdip;
5523 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5524 uint32_t *txqsizes = scctx->isc_txqsizes;
5525 uint8_t nrxqs = sctx->isc_nrxqs;
5526 uint8_t ntxqs = sctx->isc_ntxqs;
5527 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5531 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5532 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5534 /* Allocate the TX ring struct memory */
5535 if (!(ctx->ifc_txqs =
5536 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5537 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5538 device_printf(dev, "Unable to allocate TX ring memory\n");
5543 /* Now allocate the RX */
5544 if (!(ctx->ifc_rxqs =
5545 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5546 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5547 device_printf(dev, "Unable to allocate RX ring memory\n");
5552 txq = ctx->ifc_txqs;
5553 rxq = ctx->ifc_rxqs;
5556 * XXX handle allocation failure
5558 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5559 /* Set up some basics */
5561 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5562 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5564 "Unable to allocate TX DMA info memory\n");
5568 txq->ift_ifdi = ifdip;
5569 for (j = 0; j < ntxqs; j++, ifdip++) {
5570 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5572 "Unable to allocate TX descriptors\n");
5576 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5577 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5581 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5582 txq->ift_br_offset = 1;
5584 txq->ift_br_offset = 0;
5587 txq->ift_timer.c_cpu = cpu;
5589 if (iflib_txsd_alloc(txq)) {
5590 device_printf(dev, "Critical Failure setting up TX buffers\n");
5595 /* Initialize the TX lock */
5596 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5597 device_get_nameunit(dev), txq->ift_id);
5598 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5599 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5601 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5602 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5604 /* XXX free any allocated rings */
5605 device_printf(dev, "Unable to allocate buf_ring\n");
5610 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5611 /* Set up some basics */
5612 callout_init(&rxq->ifr_watchdog, 1);
5614 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5615 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5617 "Unable to allocate RX DMA info memory\n");
5622 rxq->ifr_ifdi = ifdip;
5623 /* XXX this needs to be changed if #rx queues != #tx queues */
5624 rxq->ifr_ntxqirq = 1;
5625 rxq->ifr_txqid[0] = i;
5626 for (j = 0; j < nrxqs; j++, ifdip++) {
5627 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5629 "Unable to allocate RX descriptors\n");
5633 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5637 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5638 rxq->ifr_fl_offset = 1;
5640 rxq->ifr_fl_offset = 0;
5642 rxq->ifr_nfl = nfree_lists;
5644 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5645 device_printf(dev, "Unable to allocate free list memory\n");
5650 for (j = 0; j < nfree_lists; j++) {
5651 fl[j].ifl_rxq = rxq;
5653 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5654 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5656 /* Allocate receive buffers for the ring */
5657 if (iflib_rxsd_alloc(rxq)) {
5659 "Critical Failure setting up receive buffers\n");
5664 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5665 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5670 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5671 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5672 for (i = 0; i < ntxqsets; i++) {
5673 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5675 for (j = 0; j < ntxqs; j++, di++) {
5676 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5677 paddrs[i*ntxqs + j] = di->idi_paddr;
5680 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5681 device_printf(ctx->ifc_dev,
5682 "Unable to allocate device TX queue\n");
5683 iflib_tx_structures_free(ctx);
5684 free(vaddrs, M_IFLIB);
5685 free(paddrs, M_IFLIB);
5688 free(vaddrs, M_IFLIB);
5689 free(paddrs, M_IFLIB);
5692 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5693 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5694 for (i = 0; i < nrxqsets; i++) {
5695 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5697 for (j = 0; j < nrxqs; j++, di++) {
5698 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5699 paddrs[i*nrxqs + j] = di->idi_paddr;
5702 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5703 device_printf(ctx->ifc_dev,
5704 "Unable to allocate device RX queue\n");
5705 iflib_tx_structures_free(ctx);
5706 free(vaddrs, M_IFLIB);
5707 free(paddrs, M_IFLIB);
5710 free(vaddrs, M_IFLIB);
5711 free(paddrs, M_IFLIB);
5715 /* XXX handle allocation failure changes */
5719 if (ctx->ifc_rxqs != NULL)
5720 free(ctx->ifc_rxqs, M_IFLIB);
5721 ctx->ifc_rxqs = NULL;
5722 if (ctx->ifc_txqs != NULL)
5723 free(ctx->ifc_txqs, M_IFLIB);
5724 ctx->ifc_txqs = NULL;
5730 iflib_tx_structures_setup(if_ctx_t ctx)
5732 iflib_txq_t txq = ctx->ifc_txqs;
5735 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5736 iflib_txq_setup(txq);
5742 iflib_tx_structures_free(if_ctx_t ctx)
5744 iflib_txq_t txq = ctx->ifc_txqs;
5745 if_shared_ctx_t sctx = ctx->ifc_sctx;
5748 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5749 for (j = 0; j < sctx->isc_ntxqs; j++)
5750 iflib_dma_free(&txq->ift_ifdi[j]);
5751 iflib_txq_destroy(txq);
5753 free(ctx->ifc_txqs, M_IFLIB);
5754 ctx->ifc_txqs = NULL;
5755 IFDI_QUEUES_FREE(ctx);
5758 /*********************************************************************
5760 * Initialize all receive rings.
5762 **********************************************************************/
5764 iflib_rx_structures_setup(if_ctx_t ctx)
5766 iflib_rxq_t rxq = ctx->ifc_rxqs;
5768 #if defined(INET6) || defined(INET)
5772 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5773 #if defined(INET6) || defined(INET)
5774 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5775 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5776 TCP_LRO_ENTRIES, min(1024,
5777 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5779 device_printf(ctx->ifc_dev,
5780 "LRO Initialization failed!\n");
5785 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5788 #if defined(INET6) || defined(INET)
5791 * Free LRO resources allocated so far, we will only handle
5792 * the rings that completed, the failing case will have
5793 * cleaned up for itself. 'q' failed, so its the terminus.
5795 rxq = ctx->ifc_rxqs;
5796 for (i = 0; i < q; ++i, rxq++) {
5797 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5798 tcp_lro_free(&rxq->ifr_lc);
5804 /*********************************************************************
5806 * Free all receive rings.
5808 **********************************************************************/
5810 iflib_rx_structures_free(if_ctx_t ctx)
5812 iflib_rxq_t rxq = ctx->ifc_rxqs;
5813 if_shared_ctx_t sctx = ctx->ifc_sctx;
5816 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5817 for (j = 0; j < sctx->isc_nrxqs; j++)
5818 iflib_dma_free(&rxq->ifr_ifdi[j]);
5819 iflib_rx_sds_free(rxq);
5820 #if defined(INET6) || defined(INET)
5821 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5822 tcp_lro_free(&rxq->ifr_lc);
5825 free(ctx->ifc_rxqs, M_IFLIB);
5826 ctx->ifc_rxqs = NULL;
5830 iflib_qset_structures_setup(if_ctx_t ctx)
5835 * It is expected that the caller takes care of freeing queues if this
5838 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5839 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5843 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5844 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5850 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5851 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5854 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5859 find_nth(if_ctx_t ctx, int qid)
5862 int i, cpuid, eqid, count;
5864 CPU_COPY(&ctx->ifc_cpus, &cpus);
5865 count = CPU_COUNT(&cpus);
5867 /* clear up to the qid'th bit */
5868 for (i = 0; i < eqid; i++) {
5869 cpuid = CPU_FFS(&cpus);
5871 CPU_CLR(cpuid-1, &cpus);
5873 cpuid = CPU_FFS(&cpus);
5879 extern struct cpu_group *cpu_top; /* CPU topology */
5882 find_child_with_core(int cpu, struct cpu_group *grp)
5886 if (grp->cg_children == 0)
5889 MPASS(grp->cg_child);
5890 for (i = 0; i < grp->cg_children; i++) {
5891 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5899 * Find the nth "close" core to the specified core
5900 * "close" is defined as the deepest level that shares
5901 * at least an L2 cache. With threads, this will be
5902 * threads on the same core. If the shared cache is L3
5903 * or higher, simply returns the same core.
5906 find_close_core(int cpu, int core_offset)
5908 struct cpu_group *grp;
5917 while ((i = find_child_with_core(cpu, grp)) != -1) {
5918 /* If the child only has one cpu, don't descend */
5919 if (grp->cg_child[i].cg_count <= 1)
5921 grp = &grp->cg_child[i];
5924 /* If they don't share at least an L2 cache, use the same CPU */
5925 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5929 CPU_COPY(&grp->cg_mask, &cs);
5931 /* Add the selected CPU offset to core offset. */
5932 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5933 if (fcpu - 1 == cpu)
5935 CPU_CLR(fcpu - 1, &cs);
5941 CPU_COPY(&grp->cg_mask, &cs);
5942 for (i = core_offset % grp->cg_count; i > 0; i--) {
5943 MPASS(CPU_FFS(&cs));
5944 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5946 MPASS(CPU_FFS(&cs));
5947 return CPU_FFS(&cs) - 1;
5951 find_close_core(int cpu, int core_offset __unused)
5958 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5962 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5963 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5964 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5966 case IFLIB_INTR_RXTX:
5967 /* RX queues get the specified core */
5968 return qid / CPU_COUNT(&ctx->ifc_cpus);
5974 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5975 #define find_close_core(cpuid, tid) CPU_FIRST()
5976 #define find_nth(ctx, gid) CPU_FIRST()
5979 /* Just to avoid copy/paste */
5981 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5982 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5986 int co, cpuid, err, tid;
5989 co = ctx->ifc_sysctl_core_offset;
5990 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5991 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5992 cpuid = find_nth(ctx, qid + co);
5993 tid = get_core_offset(ctx, type, qid);
5995 device_printf(dev, "get_core_offset failed\n");
5996 return (EOPNOTSUPP);
5998 cpuid = find_close_core(cpuid, tid);
5999 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
6002 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6006 if (cpuid > ctx->ifc_cpuid_highest)
6007 ctx->ifc_cpuid_highest = cpuid;
6013 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6014 iflib_intr_type_t type, driver_filter_t *filter,
6015 void *filter_arg, int qid, const char *name)
6018 struct grouptask *gtask;
6019 struct taskqgroup *tqg;
6020 iflib_filter_info_t info;
6023 driver_filter_t *intr_fast;
6026 info = &ctx->ifc_filter_info;
6030 /* XXX merge tx/rx for netmap? */
6032 q = &ctx->ifc_txqs[qid];
6033 info = &ctx->ifc_txqs[qid].ift_filter_info;
6034 gtask = &ctx->ifc_txqs[qid].ift_task;
6035 tqg = qgroup_if_io_tqg;
6037 intr_fast = iflib_fast_intr;
6038 GROUPTASK_INIT(gtask, 0, fn, q);
6039 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6042 q = &ctx->ifc_rxqs[qid];
6043 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6044 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6045 tqg = qgroup_if_io_tqg;
6047 intr_fast = iflib_fast_intr;
6048 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6050 case IFLIB_INTR_RXTX:
6051 q = &ctx->ifc_rxqs[qid];
6052 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6053 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6054 tqg = qgroup_if_io_tqg;
6056 intr_fast = iflib_fast_intr_rxtx;
6057 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6059 case IFLIB_INTR_ADMIN:
6062 info = &ctx->ifc_filter_info;
6063 gtask = &ctx->ifc_admin_task;
6064 tqg = qgroup_if_config_tqg;
6065 fn = _task_fn_admin;
6066 intr_fast = iflib_fast_intr_ctx;
6069 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6074 info->ifi_filter = filter;
6075 info->ifi_filter_arg = filter_arg;
6076 info->ifi_task = gtask;
6080 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6082 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6085 if (type == IFLIB_INTR_ADMIN)
6089 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6094 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6101 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6103 struct grouptask *gtask;
6104 struct taskqgroup *tqg;
6111 q = &ctx->ifc_txqs[qid];
6112 gtask = &ctx->ifc_txqs[qid].ift_task;
6113 tqg = qgroup_if_io_tqg;
6115 GROUPTASK_INIT(gtask, 0, fn, q);
6118 q = &ctx->ifc_rxqs[qid];
6119 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6120 tqg = qgroup_if_io_tqg;
6122 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6124 case IFLIB_INTR_IOV:
6126 gtask = &ctx->ifc_vflr_task;
6127 tqg = qgroup_if_config_tqg;
6129 GROUPTASK_INIT(gtask, 0, fn, q);
6132 panic("unknown net intr type");
6135 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6138 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6141 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6146 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6150 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6153 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6154 rman_get_rid(irq->ii_res), irq->ii_res);
6158 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6160 iflib_txq_t txq = ctx->ifc_txqs;
6161 iflib_rxq_t rxq = ctx->ifc_rxqs;
6162 if_irq_t irq = &ctx->ifc_legacy_irq;
6163 iflib_filter_info_t info;
6165 struct grouptask *gtask;
6166 struct resource *res;
6167 struct taskqgroup *tqg;
6172 q = &ctx->ifc_rxqs[0];
6173 info = &rxq[0].ifr_filter_info;
6174 gtask = &rxq[0].ifr_task;
6175 tqg = qgroup_if_io_tqg;
6177 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6179 ctx->ifc_flags |= IFC_LEGACY;
6180 info->ifi_filter = filter;
6181 info->ifi_filter_arg = filter_arg;
6182 info->ifi_task = gtask;
6183 info->ifi_ctx = rx_only ? ctx : q;
6186 /* We allocate a single interrupt resource */
6187 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6188 iflib_fast_intr_rxtx, NULL, info, name);
6191 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6193 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6195 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6196 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6202 iflib_led_create(if_ctx_t ctx)
6205 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6206 device_get_nameunit(ctx->ifc_dev));
6210 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6213 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6217 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6220 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6224 iflib_admin_intr_deferred(if_ctx_t ctx)
6227 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6228 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6232 iflib_iov_intr_deferred(if_ctx_t ctx)
6235 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6239 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6242 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6247 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6251 GROUPTASK_INIT(gtask, 0, fn, ctx);
6252 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6257 iflib_config_gtask_deinit(struct grouptask *gtask)
6260 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6264 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6266 if_t ifp = ctx->ifc_ifp;
6267 iflib_txq_t txq = ctx->ifc_txqs;
6269 if_setbaudrate(ifp, baudrate);
6270 if (baudrate >= IF_Gbps(10)) {
6272 ctx->ifc_flags |= IFC_PREFETCH;
6275 /* If link down, disable watchdog */
6276 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6277 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6278 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6280 ctx->ifc_link_state = link_state;
6281 if_link_state_change(ifp, link_state);
6285 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6289 int credits_pre = txq->ift_cidx_processed;
6292 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6293 BUS_DMASYNC_POSTREAD);
6294 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6297 txq->ift_processed += credits;
6298 txq->ift_cidx_processed += credits;
6300 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6301 if (txq->ift_cidx_processed >= txq->ift_size)
6302 txq->ift_cidx_processed -= txq->ift_size;
6307 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6312 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6313 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6314 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6315 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6320 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6321 const char *description, if_int_delay_info_t info,
6322 int offset, int value)
6324 info->iidi_ctx = ctx;
6325 info->iidi_offset = offset;
6326 info->iidi_value = value;
6327 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6328 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6329 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6330 info, 0, iflib_sysctl_int_delay, "I", description);
6334 iflib_ctx_lock_get(if_ctx_t ctx)
6337 return (&ctx->ifc_ctx_sx);
6341 iflib_msix_init(if_ctx_t ctx)
6343 device_t dev = ctx->ifc_dev;
6344 if_shared_ctx_t sctx = ctx->ifc_sctx;
6345 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6346 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6347 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6349 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6350 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6353 device_printf(dev, "msix_init qsets capped at %d\n",
6354 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6356 /* Override by tuneable */
6357 if (scctx->isc_disable_msix)
6360 /* First try MSI-X */
6361 if ((msgs = pci_msix_count(dev)) == 0) {
6363 device_printf(dev, "MSI-X not supported or disabled\n");
6367 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6369 * bar == -1 => "trust me I know what I'm doing"
6370 * Some drivers are for hardware that is so shoddily
6371 * documented that no one knows which bars are which
6372 * so the developer has to map all bars. This hack
6373 * allows shoddy garbage to use MSI-X in this framework.
6376 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6377 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6378 if (ctx->ifc_msix_mem == NULL) {
6379 device_printf(dev, "Unable to map MSI-X table\n");
6384 admincnt = sctx->isc_admin_intrcnt;
6386 /* use only 1 qset in debug mode */
6387 queuemsgs = min(msgs - admincnt, 1);
6389 queuemsgs = msgs - admincnt;
6392 queues = imin(queuemsgs, rss_getnumbuckets());
6396 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6399 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6400 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6402 /* If we're doing RSS, clamp at the number of RSS buckets */
6403 if (queues > rss_getnumbuckets())
6404 queues = rss_getnumbuckets();
6406 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6407 rx_queues = iflib_num_rx_queues;
6411 if (rx_queues > scctx->isc_nrxqsets)
6412 rx_queues = scctx->isc_nrxqsets;
6415 * We want this to be all logical CPUs by default
6417 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6418 tx_queues = iflib_num_tx_queues;
6420 tx_queues = mp_ncpus;
6422 if (tx_queues > scctx->isc_ntxqsets)
6423 tx_queues = scctx->isc_ntxqsets;
6425 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6427 if (tx_queues != rx_queues)
6429 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6430 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6432 tx_queues = min(rx_queues, tx_queues);
6433 rx_queues = min(rx_queues, tx_queues);
6436 vectors = rx_queues + admincnt;
6437 if (msgs < vectors) {
6439 "insufficient number of MSI-X vectors "
6440 "(supported %d, need %d)\n", msgs, vectors);
6444 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6447 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6448 if (vectors != msgs) {
6450 "Unable to allocate sufficient MSI-X vectors "
6451 "(got %d, need %d)\n", vectors, msgs);
6452 pci_release_msi(dev);
6454 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6456 ctx->ifc_msix_mem = NULL;
6460 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6462 scctx->isc_vectors = vectors;
6463 scctx->isc_nrxqsets = rx_queues;
6464 scctx->isc_ntxqsets = tx_queues;
6465 scctx->isc_intr = IFLIB_INTR_MSIX;
6470 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6473 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6475 ctx->ifc_msix_mem = NULL;
6480 vectors = pci_msi_count(dev);
6481 scctx->isc_nrxqsets = 1;
6482 scctx->isc_ntxqsets = 1;
6483 scctx->isc_vectors = vectors;
6484 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6485 device_printf(dev,"Using an MSI interrupt\n");
6486 scctx->isc_intr = IFLIB_INTR_MSI;
6488 scctx->isc_vectors = 1;
6489 device_printf(dev,"Using a Legacy interrupt\n");
6490 scctx->isc_intr = IFLIB_INTR_LEGACY;
6496 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6499 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6502 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6504 const char *ring_state = "UNKNOWN";
6507 rc = sysctl_wire_old_buffer(req, 0);
6511 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6516 ring_state = ring_states[state[3]];
6518 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6519 state[0], state[1], state[2], ring_state);
6520 rc = sbuf_finish(sb);
6525 enum iflib_ndesc_handler {
6531 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6533 if_ctx_t ctx = (void *)arg1;
6534 enum iflib_ndesc_handler type = arg2;
6535 char buf[256] = {0};
6542 case IFLIB_NTXD_HANDLER:
6543 ndesc = ctx->ifc_sysctl_ntxds;
6545 nqs = ctx->ifc_sctx->isc_ntxqs;
6547 case IFLIB_NRXD_HANDLER:
6548 ndesc = ctx->ifc_sysctl_nrxds;
6550 nqs = ctx->ifc_sctx->isc_nrxqs;
6553 printf("%s: unhandled type\n", __func__);
6559 for (i=0; i<8; i++) {
6564 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6567 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6568 if (rc || req->newptr == NULL)
6571 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6572 i++, p = strsep(&next, " ,")) {
6573 ndesc[i] = strtoul(p, NULL, 10);
6579 #define NAME_BUFLEN 32
6581 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6583 device_t dev = iflib_get_dev(ctx);
6584 struct sysctl_oid_list *child, *oid_list;
6585 struct sysctl_ctx_list *ctx_list;
6586 struct sysctl_oid *node;
6588 ctx_list = device_get_sysctl_ctx(dev);
6589 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6590 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6591 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6592 oid_list = SYSCTL_CHILDREN(node);
6594 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6595 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6598 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6599 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6600 "# of txqs to use, 0 => use default #");
6601 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6602 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6603 "# of rxqs to use, 0 => use default #");
6604 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6605 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6606 "permit #txq != #rxq");
6607 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6608 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6609 "disable MSI-X (default 0)");
6610 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6611 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6612 "set the RX budget");
6613 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6614 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6615 "cause TX to abdicate instead of running to completion");
6616 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6617 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6618 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6619 "offset to start using cores at");
6620 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6621 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6622 "use separate cores for TX and RX");
6624 /* XXX change for per-queue sizes */
6625 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6626 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6627 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6628 "list of # of TX descriptors to use, 0 = use default #");
6629 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6630 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6631 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6632 "list of # of RX descriptors to use, 0 = use default #");
6636 iflib_add_device_sysctl_post(if_ctx_t ctx)
6638 if_shared_ctx_t sctx = ctx->ifc_sctx;
6639 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6640 device_t dev = iflib_get_dev(ctx);
6641 struct sysctl_oid_list *child;
6642 struct sysctl_ctx_list *ctx_list;
6647 char namebuf[NAME_BUFLEN];
6649 struct sysctl_oid *queue_node, *fl_node, *node;
6650 struct sysctl_oid_list *queue_list, *fl_list;
6651 ctx_list = device_get_sysctl_ctx(dev);
6653 node = ctx->ifc_sysctl_node;
6654 child = SYSCTL_CHILDREN(node);
6656 if (scctx->isc_ntxqsets > 100)
6658 else if (scctx->isc_ntxqsets > 10)
6662 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6663 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6664 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6665 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6666 queue_list = SYSCTL_CHILDREN(queue_node);
6668 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6670 &txq->ift_dequeued, "total mbufs freed");
6671 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6673 &txq->ift_enqueued, "total mbufs enqueued");
6675 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6677 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6678 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6680 &txq->ift_pullups, "# of times m_pullup was called");
6681 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6683 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6684 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6686 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6687 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6689 &txq->ift_map_failed, "# of times DMA map failed");
6690 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6692 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6693 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6695 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6696 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6698 &txq->ift_pidx, 1, "Producer Index");
6699 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6701 &txq->ift_cidx, 1, "Consumer Index");
6702 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6704 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6705 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6707 &txq->ift_in_use, 1, "descriptors in use");
6708 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6710 &txq->ift_processed, "descriptors procesed for clean");
6711 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6713 &txq->ift_cleaned, "total cleaned");
6714 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6715 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6716 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6717 mp_ring_state_handler, "A", "soft ring state");
6718 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6719 CTLFLAG_RD, &txq->ift_br->enqueues,
6720 "# of enqueues to the mp_ring for this queue");
6721 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6722 CTLFLAG_RD, &txq->ift_br->drops,
6723 "# of drops in the mp_ring for this queue");
6724 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6725 CTLFLAG_RD, &txq->ift_br->starts,
6726 "# of normal consumer starts in the mp_ring for this queue");
6727 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6728 CTLFLAG_RD, &txq->ift_br->stalls,
6729 "# of consumer stalls in the mp_ring for this queue");
6730 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6731 CTLFLAG_RD, &txq->ift_br->restarts,
6732 "# of consumer restarts in the mp_ring for this queue");
6733 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6734 CTLFLAG_RD, &txq->ift_br->abdications,
6735 "# of consumer abdications in the mp_ring for this queue");
6738 if (scctx->isc_nrxqsets > 100)
6740 else if (scctx->isc_nrxqsets > 10)
6744 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6745 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6746 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6747 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6748 queue_list = SYSCTL_CHILDREN(queue_node);
6749 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6750 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6752 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6755 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6756 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6757 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6758 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6759 fl_list = SYSCTL_CHILDREN(fl_node);
6760 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6762 &fl->ifl_pidx, 1, "Producer Index");
6763 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6765 &fl->ifl_cidx, 1, "Consumer Index");
6766 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6768 &fl->ifl_credits, 1, "credits available");
6769 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6771 &fl->ifl_buf_size, 1, "buffer size");
6773 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6775 &fl->ifl_m_enqueued, "mbufs allocated");
6776 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6778 &fl->ifl_m_dequeued, "mbufs freed");
6779 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6781 &fl->ifl_cl_enqueued, "clusters allocated");
6782 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6784 &fl->ifl_cl_dequeued, "clusters freed");
6792 iflib_request_reset(if_ctx_t ctx)
6796 ctx->ifc_flags |= IFC_DO_RESET;
6800 #ifndef __NO_STRICT_ALIGNMENT
6801 static struct mbuf *
6802 iflib_fixup_rx(struct mbuf *m)
6806 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6807 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6808 m->m_data += ETHER_HDR_LEN;
6811 MGETHDR(n, M_NOWAIT, MT_DATA);
6816 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6817 m->m_data += ETHER_HDR_LEN;
6818 m->m_len -= ETHER_HDR_LEN;
6819 n->m_len = ETHER_HDR_LEN;
6820 M_MOVE_PKTHDR(n, m);
6829 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6833 ctx = if_getsoftc(ifp);
6835 *nrxr = NRXQSETS(ctx);
6836 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6837 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6842 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6845 if_softc_ctx_t scctx;
6850 ctx = if_getsoftc(ifp);
6851 scctx = &ctx->ifc_softc_ctx;
6854 case DEBUGNET_START:
6855 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6856 rxq = &ctx->ifc_rxqs[i];
6857 for (j = 0; j < rxq->ifr_nfl; j++) {
6859 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6862 iflib_no_tx_batch = 1;
6870 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6876 ctx = if_getsoftc(ifp);
6877 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6881 txq = &ctx->ifc_txqs[0];
6882 error = iflib_encap(txq, &m);
6884 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6889 iflib_debugnet_poll(if_t ifp, int count)
6891 struct epoch_tracker et;
6893 if_softc_ctx_t scctx;
6897 ctx = if_getsoftc(ifp);
6898 scctx = &ctx->ifc_softc_ctx;
6900 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6904 txq = &ctx->ifc_txqs[0];
6905 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6907 NET_EPOCH_ENTER(et);
6908 for (i = 0; i < scctx->isc_nrxqsets; i++)
6909 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6913 #endif /* DEBUGNET */