2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 #define IFLIB_RXEOF_MORE (1U << 0)
132 #define IFLIB_RXEOF_EMPTY (2U << 0)
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
145 static void iflib_tqg_detach(if_ctx_t ctx);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
198 uint8_t ifc_sysctl_use_logical_cores;
199 bool ifc_cpus_are_physical_cores;
201 qidx_t ifc_sysctl_ntxds[8];
202 qidx_t ifc_sysctl_nrxds[8];
203 struct if_txrx ifc_txrx;
204 #define isc_txd_encap ifc_txrx.ift_txd_encap
205 #define isc_txd_flush ifc_txrx.ift_txd_flush
206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
207 #define isc_rxd_available ifc_txrx.ift_rxd_available
208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
212 eventhandler_tag ifc_vlan_attach_event;
213 eventhandler_tag ifc_vlan_detach_event;
214 struct ether_addr ifc_mac;
218 iflib_get_softc(if_ctx_t ctx)
221 return (ctx->ifc_softc);
225 iflib_get_dev(if_ctx_t ctx)
228 return (ctx->ifc_dev);
232 iflib_get_ifp(if_ctx_t ctx)
235 return (ctx->ifc_ifp);
239 iflib_get_media(if_ctx_t ctx)
242 return (ctx->ifc_mediap);
246 iflib_get_flags(if_ctx_t ctx)
248 return (ctx->ifc_flags);
252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
259 iflib_get_softc_ctx(if_ctx_t ctx)
262 return (&ctx->ifc_softc_ctx);
266 iflib_get_sctx(if_ctx_t ctx)
269 return (ctx->ifc_sctx);
272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
289 struct mbuf **ifsd_m; /* pkthdr mbufs */
292 /* magic number that should be high enough for any hardware */
293 #define IFLIB_MAX_TX_SEGS 128
294 #define IFLIB_RX_COPY_THRESH 128
295 #define IFLIB_MAX_RX_REFRESH 32
296 /* The minimum descriptors per second before we start coalescing */
297 #define IFLIB_MIN_DESC_SEC 16384
298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
299 #define IFLIB_QUEUE_IDLE 0
300 #define IFLIB_QUEUE_HUNG 1
301 #define IFLIB_QUEUE_WORKING 2
302 /* maximum number of txqs that can share an rx interrupt */
303 #define IFLIB_MAX_TX_SHARED_INTR 4
305 /* this should really scale with ring size - this is a fairly arbitrary value */
306 #define TX_BATCH_SIZE 32
308 #define IFLIB_RESTART_BUDGET 8
310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
317 qidx_t ift_cidx_processed;
320 uint8_t ift_br_offset;
321 uint16_t ift_npending;
322 uint16_t ift_db_pending;
323 uint16_t ift_rs_pending;
325 uint8_t ift_txd_size[8];
326 uint64_t ift_processed;
327 uint64_t ift_cleaned;
328 uint64_t ift_cleaned_prev;
330 uint64_t ift_enqueued;
331 uint64_t ift_dequeued;
333 uint64_t ift_no_tx_dma_setup;
334 uint64_t ift_no_desc_avail;
335 uint64_t ift_mbuf_defrag_failed;
336 uint64_t ift_mbuf_defrag;
337 uint64_t ift_map_failed;
338 uint64_t ift_txd_encap_efbig;
339 uint64_t ift_pullups;
340 uint64_t ift_last_timer_tick;
343 struct mtx ift_db_mtx;
345 /* constant values */
347 struct ifmp_ring *ift_br;
348 struct grouptask ift_task;
351 struct callout ift_timer;
353 struct callout ift_netmap_timer;
354 #endif /* DEV_NETMAP */
356 if_txsd_vec_t ift_sds;
359 uint8_t ift_update_freq;
360 struct iflib_filter_info ift_filter_info;
361 bus_dma_tag_t ift_buf_tag;
362 bus_dma_tag_t ift_tso_buf_tag;
363 iflib_dma_info_t ift_ifdi;
364 #define MTX_NAME_LEN 32
365 char ift_mtx_name[MTX_NAME_LEN];
366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
367 #ifdef IFLIB_DIAGNOSTICS
368 uint64_t ift_cpu_exec_count[256];
370 } __aligned(CACHE_LINE_SIZE);
377 uint8_t ifl_rxd_size;
379 uint64_t ifl_m_enqueued;
380 uint64_t ifl_m_dequeued;
381 uint64_t ifl_cl_enqueued;
382 uint64_t ifl_cl_dequeued;
385 bitstr_t *ifl_rx_bitmap;
389 uint16_t ifl_buf_size;
392 iflib_rxsd_array_t ifl_sds;
395 bus_dma_tag_t ifl_buf_tag;
396 iflib_dma_info_t ifl_ifdi;
397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
399 } __aligned(CACHE_LINE_SIZE);
402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
408 else if (pidx < cidx)
409 used = size - cidx + pidx;
410 else if (gen == 0 && pidx == cidx)
412 else if (gen == 1 && pidx == cidx)
420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
422 #define IDXDIFF(head, tail, wrap) \
423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
429 struct pfil_head *pfil;
431 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
432 * the completion queue consumer index. Otherwise it's unused.
438 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
439 uint8_t ifr_fl_offset;
440 struct lro_ctrl ifr_lc;
441 struct grouptask ifr_task;
442 struct callout ifr_watchdog;
443 struct iflib_filter_info ifr_filter_info;
444 iflib_dma_info_t ifr_ifdi;
446 /* dynamically allocate if any drivers need a value substantially larger than this */
447 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
448 #ifdef IFLIB_DIAGNOSTICS
449 uint64_t ifr_cpu_exec_count[256];
451 } __aligned(CACHE_LINE_SIZE);
453 typedef struct if_rxsd {
458 /* multiple of word size */
460 #define PKT_INFO_SIZE 6
461 #define RXD_INFO_SIZE 5
462 #define PKT_TYPE uint64_t
464 #define PKT_INFO_SIZE 11
465 #define RXD_INFO_SIZE 8
466 #define PKT_TYPE uint32_t
468 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
469 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
471 typedef struct if_pkt_info_pad {
472 PKT_TYPE pkt_val[PKT_INFO_SIZE];
473 } *if_pkt_info_pad_t;
474 typedef struct if_rxd_info_pad {
475 PKT_TYPE rxd_val[RXD_INFO_SIZE];
476 } *if_rxd_info_pad_t;
478 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
479 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
482 pkt_info_zero(if_pkt_info_t pi)
484 if_pkt_info_pad_t pi_pad;
486 pi_pad = (if_pkt_info_pad_t)pi;
487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
495 static device_method_t iflib_pseudo_methods[] = {
496 DEVMETHOD(device_attach, noop_attach),
497 DEVMETHOD(device_detach, iflib_pseudo_detach),
501 driver_t iflib_pseudodriver = {
502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
506 rxd_info_zero(if_rxd_info_t ri)
508 if_rxd_info_pad_t ri_pad;
511 ri_pad = (if_rxd_info_pad_t)ri;
512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
513 ri_pad->rxd_val[i] = 0;
514 ri_pad->rxd_val[i+1] = 0;
515 ri_pad->rxd_val[i+2] = 0;
516 ri_pad->rxd_val[i+3] = 0;
519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
524 * Only allow a single packet to take up most 1/nth of the tx ring
526 #define MAX_SINGLE_PACKET_FRACTION 12
527 #define IF_BAD_DMA (bus_addr_t)-1
529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
545 iflib_set_detach(if_ctx_t ctx)
548 ctx->ifc_flags |= IFC_IN_DETACH;
552 /* Our boot-time initialization hook */
553 static int iflib_module_event_handler(module_t, int, void *);
555 static moduledata_t iflib_moduledata = {
557 iflib_module_event_handler,
561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
562 MODULE_VERSION(iflib, 1);
564 MODULE_DEPEND(iflib, pci, 1, 1, 1);
565 MODULE_DEPEND(iflib, ether, 1, 1, 1);
567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
570 #ifndef IFLIB_DEBUG_COUNTERS
572 #define IFLIB_DEBUG_COUNTERS 1
574 #define IFLIB_DEBUG_COUNTERS 0
575 #endif /* !INVARIANTS */
578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
579 "iflib driver parameters");
582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
584 static int iflib_min_tx_latency = 0;
585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
587 static int iflib_no_tx_batch = 0;
588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
590 static int iflib_timer_default = 1000;
591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
595 #if IFLIB_DEBUG_COUNTERS
597 static int iflib_tx_seen;
598 static int iflib_tx_sent;
599 static int iflib_tx_encap;
600 static int iflib_rx_allocs;
601 static int iflib_fl_refills;
602 static int iflib_fl_refills_large;
603 static int iflib_tx_frees;
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
606 &iflib_tx_seen, 0, "# TX mbufs seen");
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
608 &iflib_tx_sent, 0, "# TX mbufs sent");
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
610 &iflib_tx_encap, 0, "# TX mbufs encapped");
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
612 &iflib_tx_frees, 0, "# TX frees");
613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
614 &iflib_rx_allocs, 0, "# RX allocations");
615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
616 &iflib_fl_refills, 0, "# refills");
617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
618 &iflib_fl_refills_large, 0, "# large refills");
620 static int iflib_txq_drain_flushing;
621 static int iflib_txq_drain_oactive;
622 static int iflib_txq_drain_notready;
624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
625 &iflib_txq_drain_flushing, 0, "# drain flushes");
626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
627 &iflib_txq_drain_oactive, 0, "# drain oactives");
628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
629 &iflib_txq_drain_notready, 0, "# drain notready");
631 static int iflib_encap_load_mbuf_fail;
632 static int iflib_encap_pad_mbuf_fail;
633 static int iflib_encap_txq_avail_fail;
634 static int iflib_encap_txd_encap_fail;
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
645 static int iflib_task_fn_rxs;
646 static int iflib_rx_intr_enables;
647 static int iflib_fast_intrs;
648 static int iflib_rx_unavail;
649 static int iflib_rx_ctx_inactive;
650 static int iflib_rx_if_input;
651 static int iflib_rxd_flush;
653 static int iflib_verbose_debug;
655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
658 &iflib_rx_intr_enables, 0, "# RX intr enables");
659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
660 &iflib_fast_intrs, 0, "# fast_intr calls");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
662 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
666 &iflib_rx_if_input, 0, "# times rxeof called if_input");
667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
668 &iflib_rxd_flush, 0, "# times rxd_flush called");
669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
670 &iflib_verbose_debug, 0, "enable verbose debugging");
672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
674 iflib_debug_reset(void)
676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
678 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
679 iflib_txq_drain_notready =
680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
684 iflib_rx_ctx_inactive = iflib_rx_if_input =
689 #define DBG_COUNTER_INC(name)
690 static void iflib_debug_reset(void) {}
693 #define IFLIB_DEBUG 0
695 static void iflib_tx_structures_free(if_ctx_t ctx);
696 static void iflib_rx_structures_free(if_ctx_t ctx);
697 static int iflib_queues_alloc(if_ctx_t ctx);
698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
700 static int iflib_qset_structures_setup(if_ctx_t ctx);
701 static int iflib_msix_init(if_ctx_t ctx);
702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
706 static void iflib_altq_if_start(if_t ifp);
707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
709 static int iflib_register(if_ctx_t);
710 static void iflib_deregister(if_ctx_t);
711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
712 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
713 static void iflib_init_locked(if_ctx_t ctx);
714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
715 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
716 static void iflib_ifmp_purge(iflib_txq_t txq);
717 static void _iflib_pre_assert(if_softc_ctx_t scctx);
718 static void iflib_if_init_locked(if_ctx_t ctx);
719 static void iflib_free_intr_mem(if_ctx_t ctx);
720 #ifndef __NO_STRICT_ALIGNMENT
721 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
724 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
725 SLIST_HEAD_INITIALIZER(cpu_offsets);
727 SLIST_ENTRY(cpu_offset) entries;
729 unsigned int refcount;
732 static struct mtx cpu_offset_mtx;
733 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
736 DEBUGNET_DEFINE(iflib);
739 iflib_num_rx_descs(if_ctx_t ctx)
741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
742 if_shared_ctx_t sctx = ctx->ifc_sctx;
743 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
745 return scctx->isc_nrxd[first_rxq];
749 iflib_num_tx_descs(if_ctx_t ctx)
751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
752 if_shared_ctx_t sctx = ctx->ifc_sctx;
753 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
755 return scctx->isc_ntxd[first_txq];
759 #include <sys/selinfo.h>
760 #include <net/netmap.h>
761 #include <dev/netmap/netmap_kern.h>
763 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
765 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
766 static void iflib_netmap_timer(void *arg);
769 * device-specific sysctl variables:
771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
772 * During regular operations the CRC is stripped, but on some
773 * hardware reception of frames not multiple of 64 is slower,
774 * so using crcstrip=0 helps in benchmarks.
776 * iflib_rx_miss, iflib_rx_miss_bufs:
777 * count packets that might be missed due to lost interrupts.
779 SYSCTL_DECL(_dev_netmap);
781 * The xl driver by default strips CRCs and we do not override it.
784 int iflib_crcstrip = 1;
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
788 int iflib_rx_miss, iflib_rx_miss_bufs;
789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
795 * Register/unregister. We are already under netmap lock.
796 * Only called on the first register or the last unregister.
799 iflib_netmap_register(struct netmap_adapter *na, int onoff)
802 if_ctx_t ctx = ifp->if_softc;
807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
812 * Enable (or disable) netmap flags, and intercept (or restore)
813 * ifp->if_transmit. This is done once the device has been stopped
814 * to prevent race conditions. Also, this must be done after
815 * calling netmap_disable_all_rings() and before calling
816 * netmap_enable_all_rings(), so that these two functions see the
817 * updated state of the NAF_NETMAP_ON bit.
820 nm_set_native_flags(na);
822 nm_clear_native_flags(na);
825 iflib_init_locked(ctx);
826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
829 nm_clear_native_flags(na);
835 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
838 if_ctx_t ctx = ifp->if_softc;
839 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
840 iflib_fl_t fl = &rxq->ifr_fl[0];
842 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
843 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
844 info->num_tx_descs = iflib_num_tx_descs(ctx);
845 info->num_rx_descs = iflib_num_rx_descs(ctx);
846 info->rx_buf_maxsize = fl->ifl_buf_size;
847 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
848 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
849 info->num_rx_descs, info->rx_buf_maxsize);
855 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
857 struct netmap_adapter *na = kring->na;
858 u_int const lim = kring->nkr_num_slots - 1;
859 struct netmap_ring *ring = kring->ring;
861 struct if_rxd_update iru;
862 if_ctx_t ctx = rxq->ifr_ctx;
863 iflib_fl_t fl = &rxq->ifr_fl[0];
864 u_int nic_i_first, nic_i;
867 #if IFLIB_DEBUG_COUNTERS
872 * This function is used both at initialization and in rxsync.
873 * At initialization we need to prepare (with isc_rxd_refill())
874 * all the netmap buffers currently owned by the kernel, in
875 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
876 * (except for kring->nkr_hwofs). These may be less than
877 * kring->nkr_num_slots if netmap_reset() was called while
878 * an application using the kring that still owned some
880 * At rxsync time, both indexes point to the next buffer to be
882 * In any case we publish (with isc_rxd_flush()) up to
883 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
884 * pointer to overrun the head/cons pointer, although this is
885 * not necessary for some NICs (e.g. vmx).
887 if (__predict_false(init)) {
888 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
890 n = kring->rhead - kring->nr_hwcur;
892 return (0); /* Nothing to do. */
894 n += kring->nkr_num_slots;
897 iru_init(&iru, rxq, 0 /* flid */);
898 map = fl->ifl_sds.ifsd_map;
899 nic_i = fl->ifl_pidx;
900 nm_i = netmap_idx_n2k(kring, nic_i);
901 if (__predict_false(init)) {
903 * On init/reset, nic_i must be 0, and we must
904 * start to refill from hwtail (see netmap_reset()).
907 MPASS(nm_i == kring->nr_hwtail);
909 MPASS(nm_i == kring->nr_hwcur);
910 DBG_COUNTER_INC(fl_refills);
912 #if IFLIB_DEBUG_COUNTERS
914 DBG_COUNTER_INC(fl_refills_large);
917 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
918 struct netmap_slot *slot = &ring->slot[nm_i];
920 void *addr = PNMB(na, slot, &paddr);
922 MPASS(i < IFLIB_MAX_RX_REFRESH);
924 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
925 return netmap_ring_reinit(kring);
927 fl->ifl_bus_addrs[i] = paddr +
928 nm_get_offset(kring, slot);
929 fl->ifl_rxd_idxs[i] = nic_i;
931 if (__predict_false(init)) {
932 netmap_load_map(na, fl->ifl_buf_tag,
934 } else if (slot->flags & NS_BUF_CHANGED) {
935 /* buffer has changed, reload map */
936 netmap_reload_map(na, fl->ifl_buf_tag,
939 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
940 BUS_DMASYNC_PREREAD);
941 slot->flags &= ~NS_BUF_CHANGED;
943 nm_i = nm_next(nm_i, lim);
944 nic_i = nm_next(nic_i, lim);
947 iru.iru_pidx = nic_i_first;
949 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
951 fl->ifl_pidx = nic_i;
953 * At the end of the loop we must have refilled everything
954 * we could possibly refill.
956 MPASS(nm_i == kring->rhead);
957 kring->nr_hwcur = nm_i;
959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
961 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
962 nm_prev(nic_i, lim));
963 DBG_COUNTER_INC(rxd_flush);
968 #define NETMAP_TX_TIMER_US 90
971 * Reconcile kernel and user view of the transmit ring.
973 * All information is in the kring.
974 * Userspace wants to send packets up to the one before kring->rhead,
975 * kernel knows kring->nr_hwcur is the first unsent packet.
977 * Here we push packets out (as many as possible), and possibly
978 * reclaim buffers from previously completed transmission.
980 * The caller (netmap) guarantees that there is only one instance
981 * running at any time. Any interference with other driver
982 * methods should be handled by the individual drivers.
985 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
987 struct netmap_adapter *na = kring->na;
989 struct netmap_ring *ring = kring->ring;
990 u_int nm_i; /* index into the netmap kring */
991 u_int nic_i; /* index into the NIC ring */
993 u_int const lim = kring->nkr_num_slots - 1;
994 u_int const head = kring->rhead;
995 struct if_pkt_info pi;
998 * interrupts on every tx packet are expensive so request
999 * them every half ring, or where NS_REPORT is set
1001 u_int report_frequency = kring->nkr_num_slots >> 1;
1002 /* device-specific */
1003 if_ctx_t ctx = ifp->if_softc;
1004 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
1006 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1007 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1010 * First part: process new packets to send.
1011 * nm_i is the current index in the netmap kring,
1012 * nic_i is the corresponding index in the NIC ring.
1014 * If we have packets to send (nm_i != head)
1015 * iterate over the netmap ring, fetch length and update
1016 * the corresponding slot in the NIC ring. Some drivers also
1017 * need to update the buffer's physical address in the NIC slot
1018 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1020 * The netmap_reload_map() calls is especially expensive,
1021 * even when (as in this case) the tag is 0, so do only
1022 * when the buffer has actually changed.
1024 * If possible do not set the report/intr bit on all slots,
1025 * but only a few times per ring or when NS_REPORT is set.
1027 * Finally, on 10G and faster drivers, it might be useful
1028 * to prefetch the next slot and txr entry.
1031 nm_i = kring->nr_hwcur;
1032 if (nm_i != head) { /* we have new packets to send */
1033 uint32_t pkt_len = 0, seg_idx = 0;
1034 int nic_i_start = -1, flags = 0;
1036 pi.ipi_segs = txq->ift_segs;
1037 pi.ipi_qsidx = kring->ring_id;
1038 nic_i = netmap_idx_k2n(kring, nm_i);
1040 __builtin_prefetch(&ring->slot[nm_i]);
1041 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1042 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1044 for (n = 0; nm_i != head; n++) {
1045 struct netmap_slot *slot = &ring->slot[nm_i];
1046 uint64_t offset = nm_get_offset(kring, slot);
1047 u_int len = slot->len;
1049 void *addr = PNMB(na, slot, &paddr);
1051 flags |= (slot->flags & NS_REPORT ||
1052 nic_i == 0 || nic_i == report_frequency) ?
1056 * If this is the first packet fragment, save the
1057 * index of the first NIC slot for later.
1059 if (nic_i_start < 0)
1060 nic_i_start = nic_i;
1062 pi.ipi_segs[seg_idx].ds_addr = paddr + offset;
1063 pi.ipi_segs[seg_idx].ds_len = len;
1069 if (!(slot->flags & NS_MOREFRAG)) {
1070 pi.ipi_len = pkt_len;
1071 pi.ipi_nsegs = seg_idx;
1072 pi.ipi_pidx = nic_i_start;
1074 pi.ipi_flags = flags;
1076 /* Prepare the NIC TX ring. */
1077 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1078 DBG_COUNTER_INC(tx_encap);
1080 /* Reinit per-packet info for the next one. */
1081 flags = seg_idx = pkt_len = 0;
1085 /* prefetch for next round */
1086 __builtin_prefetch(&ring->slot[nm_i + 1]);
1087 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1088 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1090 NM_CHECK_ADDR_LEN_OFF(na, len, offset);
1092 if (slot->flags & NS_BUF_CHANGED) {
1093 /* buffer has changed, reload map */
1094 netmap_reload_map(na, txq->ift_buf_tag,
1095 txq->ift_sds.ifsd_map[nic_i], addr);
1097 /* make sure changes to the buffer are synced */
1098 bus_dmamap_sync(txq->ift_buf_tag,
1099 txq->ift_sds.ifsd_map[nic_i],
1100 BUS_DMASYNC_PREWRITE);
1102 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1103 nm_i = nm_next(nm_i, lim);
1104 nic_i = nm_next(nic_i, lim);
1106 kring->nr_hwcur = nm_i;
1108 /* synchronize the NIC ring */
1109 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1110 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1112 /* (re)start the tx unit up to slot nic_i (excluded) */
1113 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1117 * Second part: reclaim buffers for completed transmissions.
1119 * If there are unclaimed buffers, attempt to reclaim them.
1120 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1121 * trigger a per-tx-queue timer to try again later.
1123 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1124 if (iflib_tx_credits_update(ctx, txq)) {
1125 /* some tx completed, increment avail */
1126 nic_i = txq->ift_cidx_processed;
1127 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1131 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1132 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1133 callout_reset_sbt_on(&txq->ift_netmap_timer,
1134 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1135 iflib_netmap_timer, txq,
1136 txq->ift_netmap_timer.c_cpu, 0);
1142 * Reconcile kernel and user view of the receive ring.
1143 * Same as for the txsync, this routine must be efficient.
1144 * The caller guarantees a single invocations, but races against
1145 * the rest of the driver should be handled here.
1147 * On call, kring->rhead is the first packet that userspace wants
1148 * to keep, and kring->rcur is the wakeup point.
1149 * The kernel has previously reported packets up to kring->rtail.
1151 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1152 * of whether or not we received an interrupt.
1155 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1157 struct netmap_adapter *na = kring->na;
1158 struct netmap_ring *ring = kring->ring;
1160 uint32_t nm_i; /* index into the netmap ring */
1161 uint32_t nic_i; /* index into the NIC ring */
1163 u_int const lim = kring->nkr_num_slots - 1;
1164 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1167 if_ctx_t ctx = ifp->if_softc;
1168 if_shared_ctx_t sctx = ctx->ifc_sctx;
1169 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1170 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1171 iflib_fl_t fl = &rxq->ifr_fl[0];
1172 struct if_rxd_info ri;
1176 * netmap only uses free list 0, to avoid out of order consumption
1177 * of receive buffers
1180 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1181 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1184 * First part: import newly received packets.
1186 * nm_i is the index of the next free slot in the netmap ring,
1187 * nic_i is the index of the next received packet in the NIC ring
1188 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1189 * differ in case if_init() has been called while
1190 * in netmap mode. For the receive ring we have
1192 * nic_i = fl->ifl_cidx;
1193 * nm_i = kring->nr_hwtail (previous)
1195 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1197 * fl->ifl_cidx is set to 0 on a ring reinit
1199 if (netmap_no_pendintr || force_update) {
1200 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1201 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1202 int crclen = iflib_crcstrip ? 0 : 4;
1206 * For the free list consumer index, we use the same
1207 * logic as in iflib_rxeof().
1210 cidxp = &rxq->ifr_cq_cidx;
1212 cidxp = &fl->ifl_cidx;
1213 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1214 rxq->ifr_id, *cidxp, USHRT_MAX);
1216 nic_i = fl->ifl_cidx;
1217 nm_i = netmap_idx_n2k(kring, nic_i);
1218 MPASS(nm_i == kring->nr_hwtail);
1219 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1221 ri.iri_frags = rxq->ifr_frags;
1222 ri.iri_qsidx = kring->ring_id;
1223 ri.iri_ifp = ctx->ifc_ifp;
1224 ri.iri_cidx = *cidxp;
1226 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1227 for (i = 0; i < ri.iri_nfrags; i++) {
1229 ring->slot[nm_i].len = 0;
1230 ring->slot[nm_i].flags = 0;
1232 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1233 if (i == (ri.iri_nfrags - 1)) {
1234 ring->slot[nm_i].len -= crclen;
1235 ring->slot[nm_i].flags = 0;
1237 ring->slot[nm_i].flags = NS_MOREFRAG;
1240 bus_dmamap_sync(fl->ifl_buf_tag,
1241 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1242 nm_i = nm_next(nm_i, lim);
1243 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1247 *cidxp = ri.iri_cidx;
1248 while (*cidxp >= scctx->isc_nrxd[0])
1249 *cidxp -= scctx->isc_nrxd[0];
1253 if (n) { /* update the state variables */
1254 if (netmap_no_pendintr && !force_update) {
1257 iflib_rx_miss_bufs += n;
1259 kring->nr_hwtail = nm_i;
1261 kring->nr_kflags &= ~NKR_PENDINTR;
1264 * Second part: skip past packets that userspace has released.
1265 * (kring->nr_hwcur to head excluded),
1266 * and make the buffers available for reception.
1267 * As usual nm_i is the index in the netmap ring,
1268 * nic_i is the index in the NIC ring, and
1269 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1271 netmap_fl_refill(rxq, kring, false);
1277 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1279 if_ctx_t ctx = na->ifp->if_softc;
1283 IFDI_INTR_ENABLE(ctx);
1285 IFDI_INTR_DISABLE(ctx);
1291 iflib_netmap_attach(if_ctx_t ctx)
1293 struct netmap_adapter na;
1295 bzero(&na, sizeof(na));
1297 na.ifp = ctx->ifc_ifp;
1298 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS;
1299 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1300 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1302 na.num_tx_desc = iflib_num_tx_descs(ctx);
1303 na.num_rx_desc = iflib_num_rx_descs(ctx);
1304 na.nm_txsync = iflib_netmap_txsync;
1305 na.nm_rxsync = iflib_netmap_rxsync;
1306 na.nm_register = iflib_netmap_register;
1307 na.nm_intr = iflib_netmap_intr;
1308 na.nm_config = iflib_netmap_config;
1309 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1310 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1311 return (netmap_attach(&na));
1315 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1317 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1318 struct netmap_slot *slot;
1320 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1323 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1325 * In netmap mode, set the map for the packet buffer.
1326 * NOTE: Some drivers (not this one) also need to set
1327 * the physical buffer address in the NIC ring.
1328 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1329 * netmap slot index, si
1331 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1332 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1333 NMB(na, slot + si));
1339 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1341 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1342 struct netmap_kring *kring;
1343 struct netmap_slot *slot;
1345 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1348 kring = na->rx_rings[rxq->ifr_id];
1349 netmap_fl_refill(rxq, kring, true);
1354 iflib_netmap_timer(void *arg)
1356 iflib_txq_t txq = arg;
1357 if_ctx_t ctx = txq->ift_ctx;
1360 * Wake up the netmap application, to give it a chance to
1361 * call txsync and reclaim more completed TX buffers.
1363 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1366 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1369 #define iflib_netmap_txq_init(ctx, txq) (0)
1370 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1371 #define iflib_netmap_detach(ifp)
1372 #define netmap_enable_all_rings(ifp)
1373 #define netmap_disable_all_rings(ifp)
1375 #define iflib_netmap_attach(ctx) (0)
1376 #define netmap_rx_irq(ifp, qid, budget) (0)
1379 #if defined(__i386__) || defined(__amd64__)
1380 static __inline void
1383 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1385 static __inline void
1386 prefetch2cachelines(void *x)
1388 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1389 #if (CACHE_LINE_SIZE < 128)
1390 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1395 #define prefetch2cachelines(x)
1399 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1403 fl = &rxq->ifr_fl[flid];
1404 iru->iru_paddrs = fl->ifl_bus_addrs;
1405 iru->iru_idxs = fl->ifl_rxd_idxs;
1406 iru->iru_qsidx = rxq->ifr_id;
1407 iru->iru_buf_size = fl->ifl_buf_size;
1408 iru->iru_flidx = fl->ifl_id;
1412 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1416 *(bus_addr_t *) arg = segs[0].ds_addr;
1419 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \
1420 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \
1421 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL)
1424 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1427 device_t dev = ctx->ifc_dev;
1430 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width);
1432 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1433 align, 0, /* alignment, bounds */
1434 lowaddr, /* lowaddr */
1435 BUS_SPACE_MAXADDR, /* highaddr */
1436 NULL, NULL, /* filter, filterarg */
1439 size, /* maxsegsize */
1440 BUS_DMA_ALLOCNOW, /* flags */
1441 NULL, /* lockfunc */
1446 "%s: bus_dma_tag_create failed: %d\n",
1451 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1452 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1455 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1456 __func__, (uintmax_t)size, err);
1460 dma->idi_paddr = IF_BAD_DMA;
1461 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1462 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1463 if (err || dma->idi_paddr == IF_BAD_DMA) {
1465 "%s: bus_dmamap_load failed: %d\n",
1470 dma->idi_size = size;
1474 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1476 bus_dma_tag_destroy(dma->idi_tag);
1478 dma->idi_tag = NULL;
1484 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1486 if_shared_ctx_t sctx = ctx->ifc_sctx;
1488 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1490 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1494 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1497 iflib_dma_info_t *dmaiter;
1500 for (i = 0; i < count; i++, dmaiter++) {
1501 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1505 iflib_dma_free_multi(dmalist, i);
1510 iflib_dma_free(iflib_dma_info_t dma)
1512 if (dma->idi_tag == NULL)
1514 if (dma->idi_paddr != IF_BAD_DMA) {
1515 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1516 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1517 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1518 dma->idi_paddr = IF_BAD_DMA;
1520 if (dma->idi_vaddr != NULL) {
1521 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1522 dma->idi_vaddr = NULL;
1524 bus_dma_tag_destroy(dma->idi_tag);
1525 dma->idi_tag = NULL;
1529 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1532 iflib_dma_info_t *dmaiter = dmalist;
1534 for (i = 0; i < count; i++, dmaiter++)
1535 iflib_dma_free(*dmaiter);
1539 iflib_fast_intr(void *arg)
1541 iflib_filter_info_t info = arg;
1542 struct grouptask *gtask = info->ifi_task;
1545 DBG_COUNTER_INC(fast_intrs);
1546 if (info->ifi_filter != NULL) {
1547 result = info->ifi_filter(info->ifi_filter_arg);
1548 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1552 GROUPTASK_ENQUEUE(gtask);
1553 return (FILTER_HANDLED);
1557 iflib_fast_intr_rxtx(void *arg)
1559 iflib_filter_info_t info = arg;
1560 struct grouptask *gtask = info->ifi_task;
1562 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1565 int i, cidx, result;
1567 bool intr_enable, intr_legacy;
1569 DBG_COUNTER_INC(fast_intrs);
1570 if (info->ifi_filter != NULL) {
1571 result = info->ifi_filter(info->ifi_filter_arg);
1572 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1577 sc = ctx->ifc_softc;
1578 intr_enable = false;
1579 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1580 MPASS(rxq->ifr_ntxqirq);
1581 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1582 txqid = rxq->ifr_txqid[i];
1583 txq = &ctx->ifc_txqs[txqid];
1584 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1585 BUS_DMASYNC_POSTREAD);
1586 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1590 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1593 GROUPTASK_ENQUEUE(&txq->ift_task);
1595 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1596 cidx = rxq->ifr_cq_cidx;
1598 cidx = rxq->ifr_fl[0].ifl_cidx;
1599 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1600 GROUPTASK_ENQUEUE(gtask);
1605 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1606 DBG_COUNTER_INC(rx_intr_enables);
1609 IFDI_INTR_ENABLE(ctx);
1610 return (FILTER_HANDLED);
1614 iflib_fast_intr_ctx(void *arg)
1616 iflib_filter_info_t info = arg;
1617 struct grouptask *gtask = info->ifi_task;
1620 DBG_COUNTER_INC(fast_intrs);
1621 if (info->ifi_filter != NULL) {
1622 result = info->ifi_filter(info->ifi_filter_arg);
1623 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1627 GROUPTASK_ENQUEUE(gtask);
1628 return (FILTER_HANDLED);
1632 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1633 driver_filter_t filter, driver_intr_t handler, void *arg,
1636 struct resource *res;
1638 device_t dev = ctx->ifc_dev;
1642 if (ctx->ifc_flags & IFC_LEGACY)
1643 flags |= RF_SHAREABLE;
1646 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1649 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1653 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1654 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1655 filter, handler, arg, &tag);
1658 "failed to setup interrupt for rid %d, name %s: %d\n",
1659 rid, name ? name : "unknown", rc);
1662 bus_describe_intr(dev, res, tag, "%s", name);
1668 /*********************************************************************
1670 * Allocate DMA resources for TX buffers as well as memory for the TX
1671 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1672 * iflib_sw_tx_desc_array structure, storing all the information that
1673 * is needed to transmit a packet on the wire. This is called only
1674 * once at attach, setup is done every reset.
1676 **********************************************************************/
1678 iflib_txsd_alloc(iflib_txq_t txq)
1680 if_ctx_t ctx = txq->ift_ctx;
1681 if_shared_ctx_t sctx = ctx->ifc_sctx;
1682 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1683 device_t dev = ctx->ifc_dev;
1684 bus_size_t tsomaxsize;
1686 int err, nsegments, ntsosegments;
1689 nsegments = scctx->isc_tx_nsegments;
1690 ntsosegments = scctx->isc_tx_tso_segments_max;
1691 tsomaxsize = scctx->isc_tx_tso_size_max;
1692 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1693 tsomaxsize += sizeof(struct ether_vlan_header);
1694 MPASS(scctx->isc_ntxd[0] > 0);
1695 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1696 MPASS(nsegments > 0);
1697 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1698 MPASS(ntsosegments > 0);
1699 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1702 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1705 * Set up DMA tags for TX buffers.
1707 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1708 1, 0, /* alignment, bounds */
1709 lowaddr, /* lowaddr */
1710 BUS_SPACE_MAXADDR, /* highaddr */
1711 NULL, NULL, /* filter, filterarg */
1712 sctx->isc_tx_maxsize, /* maxsize */
1713 nsegments, /* nsegments */
1714 sctx->isc_tx_maxsegsize, /* maxsegsize */
1716 NULL, /* lockfunc */
1717 NULL, /* lockfuncarg */
1718 &txq->ift_buf_tag))) {
1719 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1720 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1721 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1724 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1725 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1726 1, 0, /* alignment, bounds */
1727 lowaddr, /* lowaddr */
1728 BUS_SPACE_MAXADDR, /* highaddr */
1729 NULL, NULL, /* filter, filterarg */
1730 tsomaxsize, /* maxsize */
1731 ntsosegments, /* nsegments */
1732 sctx->isc_tso_maxsegsize,/* maxsegsize */
1734 NULL, /* lockfunc */
1735 NULL, /* lockfuncarg */
1736 &txq->ift_tso_buf_tag))) {
1737 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1742 /* Allocate memory for the TX mbuf map. */
1743 if (!(txq->ift_sds.ifsd_m =
1744 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1745 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1746 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1752 * Create the DMA maps for TX buffers.
1754 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1755 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1756 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1758 "Unable to allocate TX buffer DMA map memory\n");
1762 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1763 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1764 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1766 "Unable to allocate TSO TX buffer map memory\n");
1770 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1771 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1772 &txq->ift_sds.ifsd_map[i]);
1774 device_printf(dev, "Unable to create TX DMA map\n");
1779 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1780 &txq->ift_sds.ifsd_tso_map[i]);
1782 device_printf(dev, "Unable to create TSO TX DMA map\n");
1788 /* We free all, it handles case where we are in the middle */
1789 iflib_tx_structures_free(ctx);
1794 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1798 if (txq->ift_sds.ifsd_map != NULL) {
1799 map = txq->ift_sds.ifsd_map[i];
1800 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1801 bus_dmamap_unload(txq->ift_buf_tag, map);
1802 bus_dmamap_destroy(txq->ift_buf_tag, map);
1803 txq->ift_sds.ifsd_map[i] = NULL;
1806 if (txq->ift_sds.ifsd_tso_map != NULL) {
1807 map = txq->ift_sds.ifsd_tso_map[i];
1808 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1809 BUS_DMASYNC_POSTWRITE);
1810 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1811 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1812 txq->ift_sds.ifsd_tso_map[i] = NULL;
1817 iflib_txq_destroy(iflib_txq_t txq)
1819 if_ctx_t ctx = txq->ift_ctx;
1821 for (int i = 0; i < txq->ift_size; i++)
1822 iflib_txsd_destroy(ctx, txq, i);
1824 if (txq->ift_br != NULL) {
1825 ifmp_ring_free(txq->ift_br);
1829 mtx_destroy(&txq->ift_mtx);
1831 if (txq->ift_sds.ifsd_map != NULL) {
1832 free(txq->ift_sds.ifsd_map, M_IFLIB);
1833 txq->ift_sds.ifsd_map = NULL;
1835 if (txq->ift_sds.ifsd_tso_map != NULL) {
1836 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1837 txq->ift_sds.ifsd_tso_map = NULL;
1839 if (txq->ift_sds.ifsd_m != NULL) {
1840 free(txq->ift_sds.ifsd_m, M_IFLIB);
1841 txq->ift_sds.ifsd_m = NULL;
1843 if (txq->ift_buf_tag != NULL) {
1844 bus_dma_tag_destroy(txq->ift_buf_tag);
1845 txq->ift_buf_tag = NULL;
1847 if (txq->ift_tso_buf_tag != NULL) {
1848 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1849 txq->ift_tso_buf_tag = NULL;
1851 if (txq->ift_ifdi != NULL) {
1852 free(txq->ift_ifdi, M_IFLIB);
1857 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1861 mp = &txq->ift_sds.ifsd_m[i];
1865 if (txq->ift_sds.ifsd_map != NULL) {
1866 bus_dmamap_sync(txq->ift_buf_tag,
1867 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1868 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1870 if (txq->ift_sds.ifsd_tso_map != NULL) {
1871 bus_dmamap_sync(txq->ift_tso_buf_tag,
1872 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1873 bus_dmamap_unload(txq->ift_tso_buf_tag,
1874 txq->ift_sds.ifsd_tso_map[i]);
1877 DBG_COUNTER_INC(tx_frees);
1882 iflib_txq_setup(iflib_txq_t txq)
1884 if_ctx_t ctx = txq->ift_ctx;
1885 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1886 if_shared_ctx_t sctx = ctx->ifc_sctx;
1887 iflib_dma_info_t di;
1890 /* Set number of descriptors available */
1891 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1892 /* XXX make configurable */
1893 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1896 txq->ift_cidx_processed = 0;
1897 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1898 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1900 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1901 bzero((void *)di->idi_vaddr, di->idi_size);
1903 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1904 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1905 bus_dmamap_sync(di->idi_tag, di->idi_map,
1906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1910 /*********************************************************************
1912 * Allocate DMA resources for RX buffers as well as memory for the RX
1913 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1914 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1915 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1916 * Since we use use one entry in iflib_sw_rx_desc_array per received
1917 * packet, the maximum number of entries we'll need is equal to the
1918 * number of hardware receive descriptors that we've allocated.
1920 **********************************************************************/
1922 iflib_rxsd_alloc(iflib_rxq_t rxq)
1924 if_ctx_t ctx = rxq->ifr_ctx;
1925 if_shared_ctx_t sctx = ctx->ifc_sctx;
1926 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1927 device_t dev = ctx->ifc_dev;
1932 MPASS(scctx->isc_nrxd[0] > 0);
1933 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1935 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1938 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1939 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1940 /* Set up DMA tag for RX buffers. */
1941 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1942 1, 0, /* alignment, bounds */
1943 lowaddr, /* lowaddr */
1944 BUS_SPACE_MAXADDR, /* highaddr */
1945 NULL, NULL, /* filter, filterarg */
1946 sctx->isc_rx_maxsize, /* maxsize */
1947 sctx->isc_rx_nsegments, /* nsegments */
1948 sctx->isc_rx_maxsegsize, /* maxsegsize */
1950 NULL, /* lockfunc */
1955 "Unable to allocate RX DMA tag: %d\n", err);
1959 /* Allocate memory for the RX mbuf map. */
1960 if (!(fl->ifl_sds.ifsd_m =
1961 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1962 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1964 "Unable to allocate RX mbuf map memory\n");
1969 /* Allocate memory for the direct RX cluster pointer map. */
1970 if (!(fl->ifl_sds.ifsd_cl =
1971 (caddr_t *) malloc(sizeof(caddr_t) *
1972 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1974 "Unable to allocate RX cluster map memory\n");
1979 /* Allocate memory for the RX cluster bus address map. */
1980 if (!(fl->ifl_sds.ifsd_ba =
1981 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1982 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1984 "Unable to allocate RX bus address map memory\n");
1990 * Create the DMA maps for RX buffers.
1992 if (!(fl->ifl_sds.ifsd_map =
1993 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1995 "Unable to allocate RX buffer DMA map memory\n");
1999 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
2000 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
2001 &fl->ifl_sds.ifsd_map[i]);
2003 device_printf(dev, "Unable to create RX buffer DMA map\n");
2011 iflib_rx_structures_free(ctx);
2016 * Internal service routines
2019 struct rxq_refill_cb_arg {
2021 bus_dma_segment_t seg;
2026 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2028 struct rxq_refill_cb_arg *cb_arg = arg;
2030 cb_arg->error = error;
2031 cb_arg->seg = segs[0];
2032 cb_arg->nseg = nseg;
2036 * iflib_fl_refill - refill an rxq free-buffer list
2037 * @ctx: the iflib context
2038 * @fl: the free list to refill
2039 * @count: the number of new buffers to allocate
2041 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2042 * The caller must assure that @count does not exceed the queue's capacity
2043 * minus one (since we always leave a descriptor unavailable).
2046 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2048 struct if_rxd_update iru;
2049 struct rxq_refill_cb_arg cb_arg;
2053 bus_dmamap_t *sd_map;
2054 bus_addr_t bus_addr, *sd_ba;
2055 int err, frag_idx, i, idx, n, pidx;
2058 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2060 sd_m = fl->ifl_sds.ifsd_m;
2061 sd_map = fl->ifl_sds.ifsd_map;
2062 sd_cl = fl->ifl_sds.ifsd_cl;
2063 sd_ba = fl->ifl_sds.ifsd_ba;
2064 pidx = fl->ifl_pidx;
2066 frag_idx = fl->ifl_fragidx;
2067 credits = fl->ifl_credits;
2072 MPASS(credits + n <= fl->ifl_size);
2074 if (pidx < fl->ifl_cidx)
2075 MPASS(pidx + n <= fl->ifl_cidx);
2076 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2077 MPASS(fl->ifl_gen == 0);
2078 if (pidx > fl->ifl_cidx)
2079 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2081 DBG_COUNTER_INC(fl_refills);
2083 DBG_COUNTER_INC(fl_refills_large);
2084 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2087 * We allocate an uninitialized mbuf + cluster, mbuf is
2088 * initialized after rx.
2090 * If the cluster is still set then we know a minimum sized
2091 * packet was received
2093 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2096 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2097 MPASS(frag_idx >= 0);
2098 if ((cl = sd_cl[frag_idx]) == NULL) {
2099 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2100 if (__predict_false(cl == NULL))
2104 MPASS(sd_map != NULL);
2105 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2106 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2108 if (__predict_false(err != 0 || cb_arg.error)) {
2109 uma_zfree(fl->ifl_zone, cl);
2113 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2114 sd_cl[frag_idx] = cl;
2116 fl->ifl_cl_enqueued++;
2119 bus_addr = sd_ba[frag_idx];
2121 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2122 BUS_DMASYNC_PREREAD);
2124 if (sd_m[frag_idx] == NULL) {
2125 m = m_gethdr_raw(M_NOWAIT, 0);
2126 if (__predict_false(m == NULL))
2130 bit_set(fl->ifl_rx_bitmap, frag_idx);
2132 fl->ifl_m_enqueued++;
2135 DBG_COUNTER_INC(rx_allocs);
2136 fl->ifl_rxd_idxs[i] = frag_idx;
2137 fl->ifl_bus_addrs[i] = bus_addr;
2140 MPASS(credits <= fl->ifl_size);
2141 if (++idx == fl->ifl_size) {
2147 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2148 iru.iru_pidx = pidx;
2150 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2152 fl->ifl_credits = credits;
2158 if (n < count - 1) {
2160 iru.iru_pidx = pidx;
2162 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2164 fl->ifl_credits = credits;
2166 DBG_COUNTER_INC(rxd_flush);
2167 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2169 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2170 fl->ifl_id, fl->ifl_pidx);
2171 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2172 fl->ifl_fragidx = frag_idx + 1;
2173 if (fl->ifl_fragidx == fl->ifl_size)
2174 fl->ifl_fragidx = 0;
2176 fl->ifl_fragidx = frag_idx;
2180 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2183 static inline uint8_t
2184 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2187 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2188 * This is important as it confuses most NICs. For instance,
2189 * Intel NICs have (per receive ring) RDH and RDT registers, where
2190 * RDH points to the next receive descriptor to be used by the NIC,
2191 * and RDT for the next receive descriptor to be published by the
2192 * driver to the NIC (RDT - 1 is thus the last valid one).
2193 * The condition RDH == RDT means no descriptors are available to
2194 * the NIC, and thus it would be ambiguous if it also meant that
2195 * all the descriptors are available to the NIC.
2197 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2199 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2202 MPASS(fl->ifl_credits <= fl->ifl_size);
2203 MPASS(reclaimable == delta);
2205 if (reclaimable > 0)
2206 return (iflib_fl_refill(ctx, fl, reclaimable));
2211 iflib_in_detach(if_ctx_t ctx)
2216 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2222 iflib_fl_bufs_free(iflib_fl_t fl)
2224 iflib_dma_info_t idi = fl->ifl_ifdi;
2225 bus_dmamap_t sd_map;
2228 for (i = 0; i < fl->ifl_size; i++) {
2229 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2230 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2232 if (*sd_cl != NULL) {
2233 sd_map = fl->ifl_sds.ifsd_map[i];
2234 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2235 BUS_DMASYNC_POSTREAD);
2236 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2237 uma_zfree(fl->ifl_zone, *sd_cl);
2239 if (*sd_m != NULL) {
2240 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2245 MPASS(*sd_m == NULL);
2248 fl->ifl_m_dequeued++;
2249 fl->ifl_cl_dequeued++;
2253 for (i = 0; i < fl->ifl_size; i++) {
2254 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2255 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2259 * Reset free list values
2261 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2262 bzero(idi->idi_vaddr, idi->idi_size);
2265 /*********************************************************************
2267 * Initialize a free list and its buffers.
2269 **********************************************************************/
2271 iflib_fl_setup(iflib_fl_t fl)
2273 iflib_rxq_t rxq = fl->ifl_rxq;
2274 if_ctx_t ctx = rxq->ifr_ctx;
2275 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2278 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2280 ** Free current RX buffer structs and their mbufs
2282 iflib_fl_bufs_free(fl);
2283 /* Now replenish the mbufs */
2284 MPASS(fl->ifl_credits == 0);
2285 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2286 if (scctx->isc_rxd_buf_size[qidx] != 0)
2287 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2289 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2291 * ifl_buf_size may be a driver-supplied value, so pull it up
2292 * to the selected mbuf size.
2294 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2295 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2296 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2297 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2298 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2301 * Avoid pre-allocating zillions of clusters to an idle card
2302 * potentially speeding up attach. In any case make sure
2303 * to leave a descriptor unavailable. See the comment in
2304 * iflib_fl_refill_all().
2306 MPASS(fl->ifl_size > 0);
2307 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2308 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2314 MPASS(fl->ifl_ifdi != NULL);
2315 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2320 /*********************************************************************
2322 * Free receive ring data structures
2324 **********************************************************************/
2326 iflib_rx_sds_free(iflib_rxq_t rxq)
2331 if (rxq->ifr_fl != NULL) {
2332 for (i = 0; i < rxq->ifr_nfl; i++) {
2333 fl = &rxq->ifr_fl[i];
2334 if (fl->ifl_buf_tag != NULL) {
2335 if (fl->ifl_sds.ifsd_map != NULL) {
2336 for (j = 0; j < fl->ifl_size; j++) {
2339 fl->ifl_sds.ifsd_map[j],
2340 BUS_DMASYNC_POSTREAD);
2343 fl->ifl_sds.ifsd_map[j]);
2346 fl->ifl_sds.ifsd_map[j]);
2349 bus_dma_tag_destroy(fl->ifl_buf_tag);
2350 fl->ifl_buf_tag = NULL;
2352 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2353 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2354 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2355 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2356 free(fl->ifl_rx_bitmap, M_IFLIB);
2357 fl->ifl_sds.ifsd_m = NULL;
2358 fl->ifl_sds.ifsd_cl = NULL;
2359 fl->ifl_sds.ifsd_ba = NULL;
2360 fl->ifl_sds.ifsd_map = NULL;
2361 fl->ifl_rx_bitmap = NULL;
2363 free(rxq->ifr_fl, M_IFLIB);
2365 free(rxq->ifr_ifdi, M_IFLIB);
2366 rxq->ifr_ifdi = NULL;
2367 rxq->ifr_cq_cidx = 0;
2375 iflib_timer(void *arg)
2377 iflib_txq_t txq = arg;
2378 if_ctx_t ctx = txq->ift_ctx;
2379 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2380 uint64_t this_tick = ticks;
2382 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2386 ** Check on the state of the TX queue(s), this
2387 ** can be done without the lock because its RO
2388 ** and the HUNG state will be static if set.
2390 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2391 txq->ift_last_timer_tick = this_tick;
2392 IFDI_TIMER(ctx, txq->ift_id);
2393 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2394 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2395 (sctx->isc_pause_frames == 0)))
2398 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2399 ifmp_ring_is_stalled(txq->ift_br)) {
2400 KASSERT(ctx->ifc_link_state == LINK_STATE_UP,
2401 ("queue can't be marked as hung if interface is down"));
2402 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2404 txq->ift_cleaned_prev = txq->ift_cleaned;
2406 /* handle any laggards */
2407 if (txq->ift_db_pending)
2408 GROUPTASK_ENQUEUE(&txq->ift_task);
2410 sctx->isc_pause_frames = 0;
2411 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2412 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2413 txq, txq->ift_timer.c_cpu);
2417 device_printf(ctx->ifc_dev,
2418 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2419 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2421 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2422 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2423 iflib_admin_intr_deferred(ctx);
2428 iflib_get_mbuf_size_for(unsigned int size)
2431 if (size <= MCLBYTES)
2434 return (MJUMPAGESIZE);
2438 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2440 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2443 * XXX don't set the max_frame_size to larger
2444 * than the hardware can handle
2446 ctx->ifc_rx_mbuf_sz =
2447 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2451 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2454 return (ctx->ifc_rx_mbuf_sz);
2458 iflib_init_locked(if_ctx_t ctx)
2460 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2462 if_t ifp = ctx->ifc_ifp;
2466 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2468 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2469 IFDI_INTR_DISABLE(ctx);
2472 * See iflib_stop(). Useful in case iflib_init_locked() is
2473 * called without first calling iflib_stop().
2475 netmap_disable_all_rings(ifp);
2477 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2478 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2479 /* Set hardware offload abilities */
2480 if_clearhwassist(ifp);
2481 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2482 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2483 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2484 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2485 if (if_getcapenable(ifp) & IFCAP_TSO4)
2486 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2487 if (if_getcapenable(ifp) & IFCAP_TSO6)
2488 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2490 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2492 callout_stop(&txq->ift_timer);
2494 callout_stop(&txq->ift_netmap_timer);
2495 #endif /* DEV_NETMAP */
2496 CALLOUT_UNLOCK(txq);
2497 (void)iflib_netmap_txq_init(ctx, txq);
2501 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2502 * that drivers can use the value when setting up the hardware receive
2505 iflib_calc_rx_mbuf_sz(ctx);
2508 i = if_getdrvflags(ifp);
2511 MPASS(if_getdrvflags(ifp) == i);
2512 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2513 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2514 /* This rxq is in netmap mode. Skip normal init. */
2517 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2518 if (iflib_fl_setup(fl)) {
2519 device_printf(ctx->ifc_dev,
2520 "setting up free list %d failed - "
2521 "check cluster settings\n", j);
2527 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2528 IFDI_INTR_ENABLE(ctx);
2529 txq = ctx->ifc_txqs;
2530 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2531 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2532 txq->ift_timer.c_cpu);
2534 /* Re-enable txsync/rxsync. */
2535 netmap_enable_all_rings(ifp);
2539 iflib_media_change(if_t ifp)
2541 if_ctx_t ctx = if_getsoftc(ifp);
2545 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2546 iflib_if_init_locked(ctx);
2552 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2554 if_ctx_t ctx = if_getsoftc(ifp);
2557 IFDI_UPDATE_ADMIN_STATUS(ctx);
2558 IFDI_MEDIA_STATUS(ctx, ifmr);
2563 iflib_stop(if_ctx_t ctx)
2565 iflib_txq_t txq = ctx->ifc_txqs;
2566 iflib_rxq_t rxq = ctx->ifc_rxqs;
2567 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2568 if_shared_ctx_t sctx = ctx->ifc_sctx;
2569 iflib_dma_info_t di;
2573 /* Tell the stack that the interface is no longer active */
2574 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2576 IFDI_INTR_DISABLE(ctx);
2582 * Stop any pending txsync/rxsync and prevent new ones
2583 * form starting. Processes blocked in poll() will get
2586 netmap_disable_all_rings(ctx->ifc_ifp);
2588 iflib_debug_reset();
2589 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2590 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2591 /* make sure all transmitters have completed before proceeding XXX */
2594 callout_stop(&txq->ift_timer);
2596 callout_stop(&txq->ift_netmap_timer);
2597 #endif /* DEV_NETMAP */
2598 CALLOUT_UNLOCK(txq);
2600 /* clean any enqueued buffers */
2601 iflib_ifmp_purge(txq);
2602 /* Free any existing tx buffers. */
2603 for (j = 0; j < txq->ift_size; j++) {
2604 iflib_txsd_free(ctx, txq, j);
2606 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2607 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0;
2608 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES)
2609 txq->ift_cidx = txq->ift_pidx;
2611 txq->ift_cidx = txq->ift_pidx = 0;
2613 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2614 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2615 txq->ift_pullups = 0;
2616 ifmp_ring_reset_stats(txq->ift_br);
2617 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2618 bzero((void *)di->idi_vaddr, di->idi_size);
2620 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2621 /* make sure all transmitters have completed before proceeding XXX */
2623 rxq->ifr_cq_cidx = 0;
2624 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2625 bzero((void *)di->idi_vaddr, di->idi_size);
2626 /* also resets the free lists pidx/cidx */
2627 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2628 iflib_fl_bufs_free(fl);
2632 static inline caddr_t
2633 calc_next_rxd(iflib_fl_t fl, int cidx)
2637 caddr_t start, end, cur, next;
2639 nrxd = fl->ifl_size;
2640 size = fl->ifl_rxd_size;
2641 start = fl->ifl_ifdi->idi_vaddr;
2643 if (__predict_false(size == 0))
2645 cur = start + size*cidx;
2646 end = start + size*nrxd;
2647 next = CACHE_PTR_NEXT(cur);
2648 return (next < end ? next : start);
2652 prefetch_pkts(iflib_fl_t fl, int cidx)
2655 int nrxd = fl->ifl_size;
2658 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2659 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2660 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2661 next_rxd = calc_next_rxd(fl, cidx);
2663 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2664 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2665 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2666 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2667 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2668 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2669 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2670 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2673 static struct mbuf *
2674 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2675 int *pf_rv, if_rxd_info_t ri)
2681 int flid, cidx, len, next;
2684 flid = irf->irf_flid;
2685 cidx = irf->irf_idx;
2686 fl = &rxq->ifr_fl[flid];
2688 m = fl->ifl_sds.ifsd_m[cidx];
2689 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2692 fl->ifl_m_dequeued++;
2694 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2695 prefetch_pkts(fl, cidx);
2696 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2697 prefetch(&fl->ifl_sds.ifsd_map[next]);
2698 map = fl->ifl_sds.ifsd_map[cidx];
2700 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2702 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2703 irf->irf_len != 0) {
2704 payload = *sd->ifsd_cl;
2705 payload += ri->iri_pad;
2706 len = ri->iri_len - ri->iri_pad;
2707 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2708 len | PFIL_MEMPTR | PFIL_IN, NULL);
2713 * The filter ate it. Everything is recycled.
2718 case PFIL_REALLOCED:
2720 * The filter copied it. Everything is recycled.
2722 m = pfil_mem2mbuf(payload);
2727 * Filter said it was OK, so receive like
2730 fl->ifl_sds.ifsd_m[cidx] = NULL;
2736 fl->ifl_sds.ifsd_m[cidx] = NULL;
2741 if (unload && irf->irf_len != 0)
2742 bus_dmamap_unload(fl->ifl_buf_tag, map);
2743 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2744 if (__predict_false(fl->ifl_cidx == 0))
2746 bit_clear(fl->ifl_rx_bitmap, cidx);
2750 static struct mbuf *
2751 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2753 struct mbuf *m, *mh, *mt;
2755 int *pf_rv_ptr, flags, i, padlen;
2764 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2767 MPASS(*sd->ifsd_cl != NULL);
2770 * Exclude zero-length frags & frags from
2771 * packets the filter has consumed or dropped
2773 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2774 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2776 /* everything saved here */
2781 /* XXX we can save the cluster here, but not the mbuf */
2782 m_init(m, M_NOWAIT, MT_DATA, 0);
2787 flags = M_PKTHDR|M_EXT;
2789 padlen = ri->iri_pad;
2794 /* assuming padding is only on the first fragment */
2798 *sd->ifsd_cl = NULL;
2800 /* Can these two be made one ? */
2801 m_init(m, M_NOWAIT, MT_DATA, flags);
2802 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2804 * These must follow m_init and m_cljset
2806 m->m_data += padlen;
2807 ri->iri_len -= padlen;
2808 m->m_len = ri->iri_frags[i].irf_len;
2809 } while (++i < ri->iri_nfrags);
2815 * Process one software descriptor
2817 static struct mbuf *
2818 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2824 /* should I merge this back in now that the two paths are basically duplicated? */
2825 if (ri->iri_nfrags == 1 &&
2826 ri->iri_frags[0].irf_len != 0 &&
2827 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2828 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2830 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2832 if (pf_rv == PFIL_PASS) {
2833 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2834 #ifndef __NO_STRICT_ALIGNMENT
2835 if (!IP_ALIGNED(m) && ri->iri_pad == 0)
2838 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2839 m->m_len = ri->iri_frags[0].irf_len;
2840 m->m_data += ri->iri_pad;
2841 ri->iri_len -= ri->iri_pad;
2844 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2847 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2850 m->m_pkthdr.len = ri->iri_len;
2851 m->m_pkthdr.rcvif = ri->iri_ifp;
2852 m->m_flags |= ri->iri_flags;
2853 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2854 m->m_pkthdr.flowid = ri->iri_flowid;
2855 M_HASHTYPE_SET(m, ri->iri_rsstype);
2856 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2857 m->m_pkthdr.csum_data = ri->iri_csum_data;
2861 #if defined(INET6) || defined(INET)
2863 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2865 CURVNET_SET(lc->ifp->if_vnet);
2867 *v6 = V_ip6_forwarding;
2870 *v4 = V_ipforwarding;
2876 * Returns true if it's possible this packet could be LROed.
2877 * if it returns false, it is guaranteed that tcp_lro_rx()
2878 * would not return zero.
2881 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2883 struct ether_header *eh;
2885 eh = mtod(m, struct ether_header *);
2886 switch (eh->ether_type) {
2888 case htons(ETHERTYPE_IPV6):
2889 return (!v6_forwarding);
2892 case htons(ETHERTYPE_IP):
2893 return (!v4_forwarding);
2901 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2907 _task_fn_rx_watchdog(void *context)
2909 iflib_rxq_t rxq = context;
2911 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2915 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2918 if_ctx_t ctx = rxq->ifr_ctx;
2919 if_shared_ctx_t sctx = ctx->ifc_sctx;
2920 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2923 struct if_rxd_info ri;
2924 int err, budget_left, rx_bytes, rx_pkts;
2927 bool v4_forwarding, v6_forwarding, lro_possible;
2931 * XXX early demux data packets so that if_input processing only handles
2932 * acks in interrupt context
2934 struct mbuf *m, *mh, *mt, *mf;
2938 lro_possible = v4_forwarding = v6_forwarding = false;
2942 rx_pkts = rx_bytes = 0;
2943 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2944 cidxp = &rxq->ifr_cq_cidx;
2946 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2947 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2948 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2949 retval |= iflib_fl_refill_all(ctx, fl);
2950 DBG_COUNTER_INC(rx_unavail);
2954 /* pfil needs the vnet to be set */
2955 CURVNET_SET_QUIET(ifp->if_vnet);
2956 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2957 if (__predict_false(!CTX_ACTIVE(ctx))) {
2958 DBG_COUNTER_INC(rx_ctx_inactive);
2962 * Reset client set fields to their default values
2965 ri.iri_qsidx = rxq->ifr_id;
2966 ri.iri_cidx = *cidxp;
2968 ri.iri_frags = rxq->ifr_frags;
2969 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2974 rx_bytes += ri.iri_len;
2975 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2976 *cidxp = ri.iri_cidx;
2977 /* Update our consumer index */
2978 /* XXX NB: shurd - check if this is still safe */
2979 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2980 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2981 /* was this only a completion queue message? */
2982 if (__predict_false(ri.iri_nfrags == 0))
2985 MPASS(ri.iri_nfrags != 0);
2986 MPASS(ri.iri_len != 0);
2988 /* will advance the cidx on the corresponding free lists */
2989 m = iflib_rxd_pkt_get(rxq, &ri);
2992 if (avail == 0 && budget_left)
2993 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2995 if (__predict_false(m == NULL))
2998 /* imm_pkt: -- cxgb */
3007 /* make sure that we can refill faster than drain */
3008 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3009 retval |= iflib_fl_refill_all(ctx, fl);
3011 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
3013 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
3015 while (mh != NULL) {
3018 m->m_nextpkt = NULL;
3019 #ifndef __NO_STRICT_ALIGNMENT
3020 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
3023 #if defined(INET6) || defined(INET)
3025 if (!lro_possible) {
3026 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
3027 if (lro_possible && mf != NULL) {
3028 ifp->if_input(ifp, mf);
3029 DBG_COUNTER_INC(rx_if_input);
3033 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
3034 (CSUM_L4_CALC|CSUM_L4_VALID)) {
3035 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
3041 ifp->if_input(ifp, m);
3042 DBG_COUNTER_INC(rx_if_input);
3053 ifp->if_input(ifp, mf);
3054 DBG_COUNTER_INC(rx_if_input);
3057 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3058 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3061 * Flush any outstanding LRO work
3063 #if defined(INET6) || defined(INET)
3064 tcp_lro_flush_all(&rxq->ifr_lc);
3066 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3067 retval |= IFLIB_RXEOF_MORE;
3071 ctx->ifc_flags |= IFC_DO_RESET;
3072 iflib_admin_intr_deferred(ctx);
3077 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
3078 static inline qidx_t
3079 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3081 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3082 qidx_t minthresh = txq->ift_size / 8;
3083 if (in_use > 4*minthresh)
3084 return (notify_count);
3085 if (in_use > 2*minthresh)
3086 return (notify_count >> 1);
3087 if (in_use > minthresh)
3088 return (notify_count >> 3);
3092 static inline qidx_t
3093 txq_max_rs_deferred(iflib_txq_t txq)
3095 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3096 qidx_t minthresh = txq->ift_size / 8;
3097 if (txq->ift_in_use > 4*minthresh)
3098 return (notify_count);
3099 if (txq->ift_in_use > 2*minthresh)
3100 return (notify_count >> 1);
3101 if (txq->ift_in_use > minthresh)
3102 return (notify_count >> 2);
3106 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3107 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3109 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3110 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3111 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3113 /* forward compatibility for cxgb */
3114 #define FIRST_QSET(ctx) 0
3115 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3116 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3117 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3118 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3120 /* XXX we should be setting this to something other than zero */
3121 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3122 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3123 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3126 iflib_txd_db_check(iflib_txq_t txq, int ring)
3128 if_ctx_t ctx = txq->ift_ctx;
3131 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3133 /* force || threshold exceeded || at the edge of the ring */
3134 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) {
3137 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3138 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3139 * producer index explicitly (INTC).
3141 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3142 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3143 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3144 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3147 * Absent bugs there are zero packets pending so reset pending counts to zero.
3149 txq->ift_db_pending = txq->ift_npending = 0;
3157 print_pkt(if_pkt_info_t pi)
3159 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3160 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3161 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3162 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3163 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3164 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3168 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3169 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3170 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3171 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3174 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3176 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3177 struct ether_vlan_header *eh;
3181 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3182 M_WRITABLE(m) == 0) {
3183 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3187 DBG_COUNTER_INC(tx_frees);
3193 * Determine where frame payload starts.
3194 * Jump over vlan headers if already present,
3195 * helpful for QinQ too.
3197 if (__predict_false(m->m_len < sizeof(*eh))) {
3199 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3202 eh = mtod(m, struct ether_vlan_header *);
3203 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3204 pi->ipi_etype = ntohs(eh->evl_proto);
3205 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3207 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3208 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3211 switch (pi->ipi_etype) {
3216 struct ip *ip = NULL;
3217 struct tcphdr *th = NULL;
3220 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3221 if (__predict_false(m->m_len < minthlen)) {
3223 * if this code bloat is causing too much of a hit
3224 * move it to a separate function and mark it noinline
3226 if (m->m_len == pi->ipi_ehdrlen) {
3229 if (n->m_len >= sizeof(*ip)) {
3230 ip = (struct ip *)n->m_data;
3231 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3232 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3235 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3237 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3241 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3243 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3244 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3245 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3248 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3249 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3250 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3252 pi->ipi_ip_hlen = ip->ip_hl << 2;
3253 pi->ipi_ipproto = ip->ip_p;
3254 pi->ipi_flags |= IPI_TX_IPV4;
3256 /* TCP checksum offload may require TCP header length */
3257 if (IS_TX_OFFLOAD4(pi)) {
3258 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3259 if (__predict_false(th == NULL)) {
3261 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3263 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3265 pi->ipi_tcp_hflags = th->th_flags;
3266 pi->ipi_tcp_hlen = th->th_off << 2;
3267 pi->ipi_tcp_seq = th->th_seq;
3270 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3273 * TSO always requires hardware checksum offload.
3275 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3276 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3277 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3278 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3279 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3281 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3285 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3292 case ETHERTYPE_IPV6:
3294 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3296 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3298 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3300 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3303 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3305 /* XXX-BZ this will go badly in case of ext hdrs. */
3306 pi->ipi_ipproto = ip6->ip6_nxt;
3307 pi->ipi_flags |= IPI_TX_IPV6;
3309 /* TCP checksum offload may require TCP header length */
3310 if (IS_TX_OFFLOAD6(pi)) {
3311 if (pi->ipi_ipproto == IPPROTO_TCP) {
3312 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3314 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3317 pi->ipi_tcp_hflags = th->th_flags;
3318 pi->ipi_tcp_hlen = th->th_off << 2;
3319 pi->ipi_tcp_seq = th->th_seq;
3322 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3325 * TSO always requires hardware checksum offload.
3327 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3328 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3329 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3336 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3337 pi->ipi_ip_hlen = 0;
3346 * If dodgy hardware rejects the scatter gather chain we've handed it
3347 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3350 static __noinline struct mbuf *
3351 iflib_remove_mbuf(iflib_txq_t txq)
3354 struct mbuf *m, **ifsd_m;
3356 ifsd_m = txq->ift_sds.ifsd_m;
3357 ntxd = txq->ift_size;
3358 pidx = txq->ift_pidx & (ntxd - 1);
3359 ifsd_m = txq->ift_sds.ifsd_m;
3361 ifsd_m[pidx] = NULL;
3362 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3363 if (txq->ift_sds.ifsd_tso_map != NULL)
3364 bus_dmamap_unload(txq->ift_tso_buf_tag,
3365 txq->ift_sds.ifsd_tso_map[pidx]);
3367 txq->ift_dequeued++;
3372 static inline caddr_t
3373 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3377 caddr_t start, end, cur, next;
3379 ntxd = txq->ift_size;
3380 size = txq->ift_txd_size[qid];
3381 start = txq->ift_ifdi[qid].idi_vaddr;
3383 if (__predict_false(size == 0))
3385 cur = start + size*cidx;
3386 end = start + size*ntxd;
3387 next = CACHE_PTR_NEXT(cur);
3388 return (next < end ? next : start);
3392 * Pad an mbuf to ensure a minimum ethernet frame size.
3393 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3395 static __noinline int
3396 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3399 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3400 * and ARP message is the smallest common payload I can think of
3402 static char pad[18]; /* just zeros */
3404 struct mbuf *new_head;
3406 if (!M_WRITABLE(*m_head)) {
3407 new_head = m_dup(*m_head, M_NOWAIT);
3408 if (new_head == NULL) {
3410 device_printf(dev, "cannot pad short frame, m_dup() failed");
3411 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3412 DBG_COUNTER_INC(tx_frees);
3419 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3420 n > 0; n -= sizeof(pad))
3421 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3426 device_printf(dev, "cannot pad short frame\n");
3427 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3428 DBG_COUNTER_INC(tx_frees);
3436 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3439 if_shared_ctx_t sctx;
3440 if_softc_ctx_t scctx;
3441 bus_dma_tag_t buf_tag;
3442 bus_dma_segment_t *segs;
3443 struct mbuf *m_head, **ifsd_m;
3446 struct if_pkt_info pi;
3448 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3451 sctx = ctx->ifc_sctx;
3452 scctx = &ctx->ifc_softc_ctx;
3453 segs = txq->ift_segs;
3454 ntxd = txq->ift_size;
3459 * If we're doing TSO the next descriptor to clean may be quite far ahead
3461 cidx = txq->ift_cidx;
3462 pidx = txq->ift_pidx;
3463 if (ctx->ifc_flags & IFC_PREFETCH) {
3464 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3465 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3466 next_txd = calc_next_txd(txq, cidx, 0);
3470 /* prefetch the next cache line of mbuf pointers and flags */
3471 prefetch(&txq->ift_sds.ifsd_m[next]);
3472 prefetch(&txq->ift_sds.ifsd_map[next]);
3473 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3475 map = txq->ift_sds.ifsd_map[pidx];
3476 ifsd_m = txq->ift_sds.ifsd_m;
3478 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3479 buf_tag = txq->ift_tso_buf_tag;
3480 max_segs = scctx->isc_tx_tso_segments_max;
3481 map = txq->ift_sds.ifsd_tso_map[pidx];
3482 MPASS(buf_tag != NULL);
3483 MPASS(max_segs > 0);
3485 buf_tag = txq->ift_buf_tag;
3486 max_segs = scctx->isc_tx_nsegments;
3487 map = txq->ift_sds.ifsd_map[pidx];
3489 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3490 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3491 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3493 DBG_COUNTER_INC(encap_txd_encap_fail);
3500 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3502 pi.ipi_qsidx = txq->ift_id;
3503 pi.ipi_len = m_head->m_pkthdr.len;
3504 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3505 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3507 /* deliberate bitwise OR to make one condition */
3508 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3509 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3510 DBG_COUNTER_INC(encap_txd_encap_fail);
3517 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3520 if (__predict_false(err)) {
3523 /* try collapse once and defrag once */
3525 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3526 /* try defrag if collapsing fails */
3531 txq->ift_mbuf_defrag++;
3532 m_head = m_defrag(*m_headp, M_NOWAIT);
3535 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3536 * failed to map an mbuf that was run through m_defrag
3539 if (__predict_false(m_head == NULL || remap > 1))
3546 txq->ift_no_tx_dma_setup++;
3549 txq->ift_no_tx_dma_setup++;
3551 DBG_COUNTER_INC(tx_frees);
3555 txq->ift_map_failed++;
3556 DBG_COUNTER_INC(encap_load_mbuf_fail);
3557 DBG_COUNTER_INC(encap_txd_encap_fail);
3560 ifsd_m[pidx] = m_head;
3562 * XXX assumes a 1 to 1 relationship between segments and
3563 * descriptors - this does not hold true on all drivers, e.g.
3566 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3567 txq->ift_no_desc_avail++;
3568 bus_dmamap_unload(buf_tag, map);
3569 DBG_COUNTER_INC(encap_txq_avail_fail);
3570 DBG_COUNTER_INC(encap_txd_encap_fail);
3571 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3572 GROUPTASK_ENQUEUE(&txq->ift_task);
3576 * On Intel cards we can greatly reduce the number of TX interrupts
3577 * we see by only setting report status on every Nth descriptor.
3578 * However, this also means that the driver will need to keep track
3579 * of the descriptors that RS was set on to check them for the DD bit.
3581 txq->ift_rs_pending += nsegs + 1;
3582 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3583 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3584 pi.ipi_flags |= IPI_TX_INTR;
3585 txq->ift_rs_pending = 0;
3589 pi.ipi_nsegs = nsegs;
3591 MPASS(pidx >= 0 && pidx < txq->ift_size);
3595 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3596 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3597 DBG_COUNTER_INC(tx_encap);
3598 MPASS(pi.ipi_new_pidx < txq->ift_size);
3600 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3601 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3602 ndesc += txq->ift_size;
3606 * drivers can need as many as
3609 MPASS(ndesc <= pi.ipi_nsegs + 2);
3610 MPASS(pi.ipi_new_pidx != pidx);
3612 txq->ift_in_use += ndesc;
3613 txq->ift_db_pending += ndesc;
3616 * We update the last software descriptor again here because there may
3617 * be a sentinel and/or there may be more mbufs than segments
3619 txq->ift_pidx = pi.ipi_new_pidx;
3620 txq->ift_npending += pi.ipi_ndescs;
3622 *m_headp = m_head = iflib_remove_mbuf(txq);
3624 txq->ift_txd_encap_efbig++;
3633 * err can't possibly be non-zero here, so we don't neet to test it
3634 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3639 txq->ift_mbuf_defrag_failed++;
3640 txq->ift_map_failed++;
3642 DBG_COUNTER_INC(tx_frees);
3644 DBG_COUNTER_INC(encap_txd_encap_fail);
3649 iflib_tx_desc_free(iflib_txq_t txq, int n)
3651 uint32_t qsize, cidx, mask, gen;
3652 struct mbuf *m, **ifsd_m;
3655 cidx = txq->ift_cidx;
3657 qsize = txq->ift_size;
3659 ifsd_m = txq->ift_sds.ifsd_m;
3660 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3664 prefetch(ifsd_m[(cidx + 3) & mask]);
3665 prefetch(ifsd_m[(cidx + 4) & mask]);
3667 if ((m = ifsd_m[cidx]) != NULL) {
3668 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3669 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3670 bus_dmamap_sync(txq->ift_tso_buf_tag,
3671 txq->ift_sds.ifsd_tso_map[cidx],
3672 BUS_DMASYNC_POSTWRITE);
3673 bus_dmamap_unload(txq->ift_tso_buf_tag,
3674 txq->ift_sds.ifsd_tso_map[cidx]);
3676 bus_dmamap_sync(txq->ift_buf_tag,
3677 txq->ift_sds.ifsd_map[cidx],
3678 BUS_DMASYNC_POSTWRITE);
3679 bus_dmamap_unload(txq->ift_buf_tag,
3680 txq->ift_sds.ifsd_map[cidx]);
3682 /* XXX we don't support any drivers that batch packets yet */
3683 MPASS(m->m_nextpkt == NULL);
3685 ifsd_m[cidx] = NULL;
3687 txq->ift_dequeued++;
3689 DBG_COUNTER_INC(tx_frees);
3691 if (__predict_false(++cidx == qsize)) {
3696 txq->ift_cidx = cidx;
3701 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3704 if_ctx_t ctx = txq->ift_ctx;
3706 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3707 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3710 * Need a rate-limiting check so that this isn't called every time
3712 iflib_tx_credits_update(ctx, txq);
3713 reclaim = DESC_RECLAIMABLE(txq);
3715 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3717 if (iflib_verbose_debug) {
3718 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3719 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3725 iflib_tx_desc_free(txq, reclaim);
3726 txq->ift_cleaned += reclaim;
3727 txq->ift_in_use -= reclaim;
3732 static struct mbuf **
3733 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3736 struct mbuf **items;
3739 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3740 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3742 prefetch(items[(cidx + offset) & (size-1)]);
3743 if (remaining > 1) {
3744 prefetch2cachelines(&items[next]);
3745 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3746 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3747 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3749 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3753 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3756 ifmp_ring_check_drainage(txq->ift_br, budget);
3760 iflib_txq_can_drain(struct ifmp_ring *r)
3762 iflib_txq_t txq = r->cookie;
3763 if_ctx_t ctx = txq->ift_ctx;
3765 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3767 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3768 BUS_DMASYNC_POSTREAD);
3769 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3774 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3776 iflib_txq_t txq = r->cookie;
3777 if_ctx_t ctx = txq->ift_ctx;
3778 if_t ifp = ctx->ifc_ifp;
3779 struct mbuf *m, **mp;
3780 int avail, bytes_sent, skipped, count, err, i;
3781 int mcast_sent, pkt_sent, reclaimed;
3782 bool do_prefetch, rang, ring;
3784 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3785 !LINK_ACTIVE(ctx))) {
3786 DBG_COUNTER_INC(txq_drain_notready);
3789 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3790 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3791 avail = IDXDIFF(pidx, cidx, r->size);
3793 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3795 * The driver is unloading so we need to free all pending packets.
3797 DBG_COUNTER_INC(txq_drain_flushing);
3798 for (i = 0; i < avail; i++) {
3799 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3800 m_freem(r->items[(cidx + i) & (r->size-1)]);
3801 r->items[(cidx + i) & (r->size-1)] = NULL;
3806 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3807 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3809 callout_stop(&txq->ift_timer);
3810 CALLOUT_UNLOCK(txq);
3811 DBG_COUNTER_INC(txq_drain_oactive);
3816 * If we've reclaimed any packets this queue cannot be hung.
3819 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3820 skipped = mcast_sent = bytes_sent = pkt_sent = 0;
3821 count = MIN(avail, TX_BATCH_SIZE);
3823 if (iflib_verbose_debug)
3824 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3825 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3827 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3829 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) {
3830 int rem = do_prefetch ? count - i : 0;
3832 mp = _ring_peek_one(r, cidx, i, rem);
3833 MPASS(mp != NULL && *mp != NULL);
3836 * Completion interrupts will use the address of the txq
3837 * as a sentinel to enqueue _something_ in order to acquire
3838 * the lock on the mp_ring (there's no direct lock call).
3839 * We obviously whave to check for these sentinel cases
3842 if (__predict_false(*mp == (struct mbuf *)txq)) {
3846 err = iflib_encap(txq, mp);
3847 if (__predict_false(err)) {
3848 /* no room - bail out */
3852 /* we can't send this packet - skip it */
3857 DBG_COUNTER_INC(tx_sent);
3858 bytes_sent += m->m_pkthdr.len;
3859 mcast_sent += !!(m->m_flags & M_MCAST);
3861 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3863 ETHER_BPF_MTAP(ifp, m);
3864 rang = iflib_txd_db_check(txq, false);
3867 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3868 ring = rang ? false : (iflib_min_tx_latency | err);
3869 iflib_txd_db_check(txq, ring);
3870 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3871 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3873 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3875 if (iflib_verbose_debug)
3876 printf("consumed=%d\n", skipped + pkt_sent);
3878 return (skipped + pkt_sent);
3882 iflib_txq_drain_always(struct ifmp_ring *r)
3888 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3896 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3898 callout_stop(&txq->ift_timer);
3899 CALLOUT_UNLOCK(txq);
3901 avail = IDXDIFF(pidx, cidx, r->size);
3902 for (i = 0; i < avail; i++) {
3903 mp = _ring_peek_one(r, cidx, i, avail - i);
3904 if (__predict_false(*mp == (struct mbuf *)txq))
3907 DBG_COUNTER_INC(tx_frees);
3909 MPASS(ifmp_ring_is_stalled(r) == 0);
3914 iflib_ifmp_purge(iflib_txq_t txq)
3916 struct ifmp_ring *r;
3919 r->drain = iflib_txq_drain_free;
3920 r->can_drain = iflib_txq_drain_always;
3922 ifmp_ring_check_drainage(r, r->size);
3924 r->drain = iflib_txq_drain;
3925 r->can_drain = iflib_txq_can_drain;
3929 _task_fn_tx(void *context)
3931 iflib_txq_t txq = context;
3932 if_ctx_t ctx = txq->ift_ctx;
3933 if_t ifp = ctx->ifc_ifp;
3934 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3936 #ifdef IFLIB_DIAGNOSTICS
3937 txq->ift_cpu_exec_count[curcpu]++;
3939 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3942 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3943 netmap_tx_irq(ifp, txq->ift_id))
3947 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3948 iflib_altq_if_start(ifp);
3950 if (txq->ift_db_pending)
3951 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3953 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3955 * When abdicating, we always need to check drainage, not just when we don't enqueue
3958 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3962 if (ctx->ifc_flags & IFC_LEGACY)
3963 IFDI_INTR_ENABLE(ctx);
3965 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3969 _task_fn_rx(void *context)
3971 iflib_rxq_t rxq = context;
3972 if_ctx_t ctx = rxq->ifr_ctx;
3980 #ifdef IFLIB_DIAGNOSTICS
3981 rxq->ifr_cpu_exec_count[curcpu]++;
3983 DBG_COUNTER_INC(task_fn_rxs);
3984 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3987 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3988 if (nmirq != NM_IRQ_PASS) {
3989 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3993 budget = ctx->ifc_sysctl_rx_budget;
3995 budget = 16; /* XXX */
3996 more = iflib_rxeof(rxq, budget);
4000 if ((more & IFLIB_RXEOF_MORE) == 0) {
4001 if (ctx->ifc_flags & IFC_LEGACY)
4002 IFDI_INTR_ENABLE(ctx);
4004 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
4005 DBG_COUNTER_INC(rx_intr_enables);
4007 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4010 if (more & IFLIB_RXEOF_MORE)
4011 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4012 else if (more & IFLIB_RXEOF_EMPTY)
4013 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4017 _task_fn_admin(void *context)
4019 if_ctx_t ctx = context;
4020 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4023 bool oactive, running, do_reset, do_watchdog, in_detach;
4026 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4027 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4028 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4029 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4030 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4031 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
4034 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4040 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4042 callout_stop(&txq->ift_timer);
4043 CALLOUT_UNLOCK(txq);
4045 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ)
4046 IFDI_ADMIN_COMPLETION_HANDLE(ctx);
4048 ctx->ifc_watchdog_events++;
4049 IFDI_WATCHDOG_RESET(ctx);
4051 IFDI_UPDATE_ADMIN_STATUS(ctx);
4052 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4053 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4054 txq->ift_timer.c_cpu);
4056 IFDI_LINK_INTR_ENABLE(ctx);
4058 iflib_if_init_locked(ctx);
4061 if (LINK_ACTIVE(ctx) == 0)
4063 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4064 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4068 _task_fn_iov(void *context)
4070 if_ctx_t ctx = context;
4072 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4073 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4077 IFDI_VFLR_HANDLE(ctx);
4082 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4085 if_int_delay_info_t info;
4088 info = (if_int_delay_info_t)arg1;
4089 ctx = info->iidi_ctx;
4090 info->iidi_req = req;
4091 info->iidi_oidp = oidp;
4093 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4098 /*********************************************************************
4102 **********************************************************************/
4105 iflib_if_init_locked(if_ctx_t ctx)
4108 iflib_init_locked(ctx);
4112 iflib_if_init(void *arg)
4117 iflib_if_init_locked(ctx);
4122 iflib_if_transmit(if_t ifp, struct mbuf *m)
4124 if_ctx_t ctx = if_getsoftc(ifp);
4128 int abdicate = ctx->ifc_sysctl_tx_abdicate;
4130 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4131 DBG_COUNTER_INC(tx_frees);
4136 MPASS(m->m_nextpkt == NULL);
4137 /* ALTQ-enabled interfaces always use queue 0. */
4139 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
4140 qidx = QIDX(ctx, m);
4142 * XXX calculate buf_ring based on flowid (divvy up bits?)
4144 txq = &ctx->ifc_txqs[qidx];
4146 #ifdef DRIVER_BACKPRESSURE
4147 if (txq->ift_closed) {
4149 next = m->m_nextpkt;
4150 m->m_nextpkt = NULL;
4152 DBG_COUNTER_INC(tx_frees);
4164 next = next->m_nextpkt;
4165 } while (next != NULL);
4167 if (count > nitems(marr))
4168 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4169 /* XXX check nextpkt */
4171 /* XXX simplify for now */
4172 DBG_COUNTER_INC(tx_frees);
4175 for (next = m, i = 0; next != NULL; i++) {
4177 next = next->m_nextpkt;
4178 mp[i]->m_nextpkt = NULL;
4181 DBG_COUNTER_INC(tx_seen);
4182 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4185 GROUPTASK_ENQUEUE(&txq->ift_task);
4188 GROUPTASK_ENQUEUE(&txq->ift_task);
4189 /* support forthcoming later */
4190 #ifdef DRIVER_BACKPRESSURE
4191 txq->ift_closed = TRUE;
4193 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4195 DBG_COUNTER_INC(tx_frees);
4203 * The overall approach to integrating iflib with ALTQ is to continue to use
4204 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4205 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4206 * is redundant/unnecessary, but doing so minimizes the amount of
4207 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4208 * redundantly queueing to an intermediate mp_ring is swamped by the
4209 * performance limitations inherent in using ALTQ.
4211 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4212 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4213 * given interface. If ALTQ is enabled for an interface, then all
4214 * transmitted packets for that interface will be submitted to the ALTQ
4215 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4216 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4217 * update stats that the iflib machinery handles, and which is sensitve to
4218 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4219 * will be installed as the start routine for use by ALTQ facilities that
4220 * need to trigger queue drains on a scheduled basis.
4224 iflib_altq_if_start(if_t ifp)
4226 struct ifaltq *ifq = &ifp->if_snd;
4230 IFQ_DEQUEUE_NOLOCK(ifq, m);
4232 iflib_if_transmit(ifp, m);
4233 IFQ_DEQUEUE_NOLOCK(ifq, m);
4239 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4243 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4244 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4246 iflib_altq_if_start(ifp);
4248 err = iflib_if_transmit(ifp, m);
4255 iflib_if_qflush(if_t ifp)
4257 if_ctx_t ctx = if_getsoftc(ifp);
4258 iflib_txq_t txq = ctx->ifc_txqs;
4262 ctx->ifc_flags |= IFC_QFLUSH;
4264 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4265 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4266 iflib_txq_check_drain(txq, 0);
4268 ctx->ifc_flags &= ~IFC_QFLUSH;
4272 * When ALTQ is enabled, this will also take care of purging the
4278 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4279 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4280 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4281 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4284 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4286 if_ctx_t ctx = if_getsoftc(ifp);
4287 struct ifreq *ifr = (struct ifreq *)data;
4288 #if defined(INET) || defined(INET6)
4289 struct ifaddr *ifa = (struct ifaddr *)data;
4291 bool avoid_reset = false;
4292 int err = 0, reinit = 0, bits;
4297 if (ifa->ifa_addr->sa_family == AF_INET)
4301 if (ifa->ifa_addr->sa_family == AF_INET6)
4305 ** Calling init results in link renegotiation,
4306 ** so we avoid doing it when possible.
4309 if_setflagbits(ifp, IFF_UP,0);
4310 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4313 if (!(if_getflags(ifp) & IFF_NOARP))
4314 arp_ifinit(ifp, ifa);
4317 err = ether_ioctl(ifp, command, data);
4321 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4325 bits = if_getdrvflags(ifp);
4326 /* stop the driver and free any clusters before proceeding */
4329 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4331 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4332 ctx->ifc_flags |= IFC_MULTISEG;
4334 ctx->ifc_flags &= ~IFC_MULTISEG;
4336 err = if_setmtu(ifp, ifr->ifr_mtu);
4338 iflib_init_locked(ctx);
4340 if_setdrvflags(ifp, bits);
4346 if (if_getflags(ifp) & IFF_UP) {
4347 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4348 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4349 (IFF_PROMISC | IFF_ALLMULTI)) {
4351 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4356 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4359 ctx->ifc_if_flags = if_getflags(ifp);
4364 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4366 IFDI_INTR_DISABLE(ctx);
4367 IFDI_MULTI_SET(ctx);
4368 IFDI_INTR_ENABLE(ctx);
4374 IFDI_MEDIA_SET(ctx);
4379 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4383 struct ifi2creq i2c;
4385 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4388 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4392 if (i2c.len > sizeof(i2c.data)) {
4397 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4398 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4404 int mask, setmask, oldmask;
4406 oldmask = if_getcapenable(ifp);
4407 mask = ifr->ifr_reqcap ^ oldmask;
4408 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4411 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4413 setmask |= (mask & IFCAP_FLAGS);
4414 setmask |= (mask & IFCAP_WOL);
4417 * If any RX csum has changed, change all the ones that
4418 * are supported by the driver.
4420 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4421 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4422 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4426 * want to ensure that traffic has stopped before we change any of the flags
4430 bits = if_getdrvflags(ifp);
4431 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4434 if_togglecapenable(ifp, setmask);
4436 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4437 iflib_init_locked(ctx);
4439 if_setdrvflags(ifp, bits);
4446 case SIOCGPRIVATE_0:
4450 err = IFDI_PRIV_IOCTL(ctx, command, data);
4454 err = ether_ioctl(ifp, command, data);
4463 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4465 if_ctx_t ctx = if_getsoftc(ifp);
4467 return (IFDI_GET_COUNTER(ctx, cnt));
4470 /*********************************************************************
4472 * OTHER FUNCTIONS EXPORTED TO THE STACK
4474 **********************************************************************/
4477 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4479 if_ctx_t ctx = if_getsoftc(ifp);
4481 if ((void *)ctx != arg)
4484 if ((vtag == 0) || (vtag > 4095))
4487 if (iflib_in_detach(ctx))
4491 /* Driver may need all untagged packets to be flushed */
4492 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4494 IFDI_VLAN_REGISTER(ctx, vtag);
4495 /* Re-init to load the changes, if required */
4496 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4497 iflib_init_locked(ctx);
4502 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4504 if_ctx_t ctx = if_getsoftc(ifp);
4506 if ((void *)ctx != arg)
4509 if ((vtag == 0) || (vtag > 4095))
4513 /* Driver may need all tagged packets to be flushed */
4514 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4516 IFDI_VLAN_UNREGISTER(ctx, vtag);
4517 /* Re-init to load the changes, if required */
4518 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4519 iflib_init_locked(ctx);
4524 iflib_led_func(void *arg, int onoff)
4529 IFDI_LED_FUNC(ctx, onoff);
4533 /*********************************************************************
4535 * BUS FUNCTION DEFINITIONS
4537 **********************************************************************/
4540 iflib_device_probe(device_t dev)
4542 const pci_vendor_info_t *ent;
4543 if_shared_ctx_t sctx;
4544 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4545 uint16_t pci_vendor_id;
4547 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4550 pci_vendor_id = pci_get_vendor(dev);
4551 pci_device_id = pci_get_device(dev);
4552 pci_subvendor_id = pci_get_subvendor(dev);
4553 pci_subdevice_id = pci_get_subdevice(dev);
4554 pci_rev_id = pci_get_revid(dev);
4555 if (sctx->isc_parse_devinfo != NULL)
4556 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4558 ent = sctx->isc_vendor_info;
4559 while (ent->pvi_vendor_id != 0) {
4560 if (pci_vendor_id != ent->pvi_vendor_id) {
4564 if ((pci_device_id == ent->pvi_device_id) &&
4565 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4566 (ent->pvi_subvendor_id == 0)) &&
4567 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4568 (ent->pvi_subdevice_id == 0)) &&
4569 ((pci_rev_id == ent->pvi_rev_id) ||
4570 (ent->pvi_rev_id == 0))) {
4571 device_set_desc_copy(dev, ent->pvi_name);
4572 /* this needs to be changed to zero if the bus probing code
4573 * ever stops re-probing on best match because the sctx
4574 * may have its values over written by register calls
4575 * in subsequent probes
4577 return (BUS_PROBE_DEFAULT);
4585 iflib_device_probe_vendor(device_t dev)
4589 probe = iflib_device_probe(dev);
4590 if (probe == BUS_PROBE_DEFAULT)
4591 return (BUS_PROBE_VENDOR);
4597 iflib_reset_qvalues(if_ctx_t ctx)
4599 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4600 if_shared_ctx_t sctx = ctx->ifc_sctx;
4601 device_t dev = ctx->ifc_dev;
4604 if (ctx->ifc_sysctl_ntxqs != 0)
4605 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4606 if (ctx->ifc_sysctl_nrxqs != 0)
4607 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4609 for (i = 0; i < sctx->isc_ntxqs; i++) {
4610 if (ctx->ifc_sysctl_ntxds[i] != 0)
4611 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4613 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4616 for (i = 0; i < sctx->isc_nrxqs; i++) {
4617 if (ctx->ifc_sysctl_nrxds[i] != 0)
4618 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4620 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4623 for (i = 0; i < sctx->isc_nrxqs; i++) {
4624 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4625 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4626 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4627 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4629 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4630 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4631 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4632 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4634 if (!powerof2(scctx->isc_nrxd[i])) {
4635 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4636 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4637 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4641 for (i = 0; i < sctx->isc_ntxqs; i++) {
4642 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4643 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4644 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4645 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4647 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4648 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4649 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4650 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4652 if (!powerof2(scctx->isc_ntxd[i])) {
4653 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4654 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4655 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4661 iflib_add_pfil(if_ctx_t ctx)
4663 struct pfil_head *pfil;
4664 struct pfil_head_args pa;
4668 pa.pa_version = PFIL_VERSION;
4669 pa.pa_flags = PFIL_IN;
4670 pa.pa_type = PFIL_TYPE_ETHERNET;
4671 pa.pa_headname = ctx->ifc_ifp->if_xname;
4672 pfil = pfil_head_register(&pa);
4674 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4680 iflib_rem_pfil(if_ctx_t ctx)
4682 struct pfil_head *pfil;
4686 rxq = ctx->ifc_rxqs;
4688 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4691 pfil_head_unregister(pfil);
4696 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from
4697 * cpuid and wrapping as necessary.
4700 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n)
4702 unsigned int first_valid;
4703 unsigned int last_valid;
4705 /* cpuid should always be in the valid set */
4706 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus));
4708 /* valid set should never be empty */
4709 MPASS(!CPU_EMPTY(&ctx->ifc_cpus));
4711 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4712 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4713 n = n % CPU_COUNT(&ctx->ifc_cpus);
4717 if (cpuid > last_valid)
4718 cpuid = first_valid;
4719 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus));
4726 #if defined(SMP) && defined(SCHED_ULE)
4727 extern struct cpu_group *cpu_top; /* CPU topology */
4730 find_child_with_core(int cpu, struct cpu_group *grp)
4734 if (grp->cg_children == 0)
4737 MPASS(grp->cg_child);
4738 for (i = 0; i < grp->cg_children; i++) {
4739 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
4748 * Find an L2 neighbor of the given CPU or return -1 if none found. This
4749 * does not distinguish among multiple L2 neighbors if the given CPU has
4750 * more than one (it will always return the same result in that case).
4753 find_l2_neighbor(int cpu)
4755 struct cpu_group *grp;
4763 * Find the smallest CPU group that contains the given core.
4766 while ((i = find_child_with_core(cpu, grp)) != -1) {
4768 * If the smallest group containing the given CPU has less
4769 * than two members, we conclude the given CPU has no
4772 if (grp->cg_child[i].cg_count <= 1)
4774 grp = &grp->cg_child[i];
4777 /* Must share L2. */
4778 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
4782 * Select the first member of the set that isn't the reference
4783 * CPU, which at this point is guaranteed to exist.
4785 for (i = 0; i < CPU_SETSIZE; i++) {
4786 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu)
4790 /* Should never be reached */
4796 find_l2_neighbor(int cpu)
4804 * CPU mapping behaviors
4805 * ---------------------
4806 * 'separate txrx' refers to the separate_txrx sysctl
4807 * 'use logical' refers to the use_logical_cores sysctl
4808 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded
4811 * txrx logical CPUS result
4812 * ---------- --------- ------ ------------------------------------------------
4813 * - - X RX and TX queues mapped to consecutive physical
4814 * cores with RX/TX pairs on same core and excess
4815 * of either following
4816 * - X X RX and TX queues mapped to consecutive cores
4817 * of any type with RX/TX pairs on same core and
4818 * excess of either following
4819 * X - X RX and TX queues mapped to consecutive physical
4820 * cores; all RX then all TX
4821 * X X X RX queues mapped to consecutive physical cores
4822 * first, then TX queues mapped to L2 neighbor of
4823 * the corresponding RX queue if one exists,
4824 * otherwise to consecutive physical cores
4825 * - n/a - RX and TX queues mapped to consecutive cores of
4826 * any type with RX/TX pairs on same core and excess
4827 * of either following
4828 * X n/a - RX and TX queues mapped to consecutive cores of
4829 * any type; all RX then all TX
4832 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid,
4835 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4836 unsigned int core_index;
4838 if (ctx->ifc_sysctl_separate_txrx) {
4840 * When using separate CPUs for TX and RX, the assignment
4841 * will always be of a consecutive CPU out of the set of
4842 * context CPUs, except for the specific case where the
4843 * context CPUs are phsyical cores, the use of logical cores
4844 * has been enabled, the assignment is for TX, the TX qid
4845 * corresponds to an RX qid, and the CPU assigned to the
4846 * corresponding RX queue has an L2 neighbor.
4848 if (ctx->ifc_sysctl_use_logical_cores &&
4849 ctx->ifc_cpus_are_physical_cores &&
4850 is_tx && qid < scctx->isc_nrxqsets) {
4852 unsigned int rx_cpuid;
4854 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid);
4855 l2_neighbor = find_l2_neighbor(rx_cpuid);
4856 if (l2_neighbor != -1) {
4857 return (l2_neighbor);
4860 * ... else fall through to the normal
4861 * consecutive-after-RX assignment scheme.
4863 * Note that we are assuming that all RX queue CPUs
4864 * have an L2 neighbor, or all do not. If a mixed
4865 * scenario is possible, we will have to keep track
4866 * separately of how many queues prior to this one
4867 * were not able to be assigned to an L2 neighbor.
4871 core_index = scctx->isc_nrxqsets + qid;
4878 return (cpuid_advance(ctx, base_cpuid, core_index));
4882 get_ctx_core_offset(if_ctx_t ctx)
4884 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4885 struct cpu_offset *op;
4886 cpuset_t assigned_cpus;
4887 unsigned int cores_consumed;
4888 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset;
4889 unsigned int first_valid;
4890 unsigned int last_valid;
4893 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4894 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4896 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) {
4898 * Align the user-chosen base CPU ID to the next valid CPU
4899 * for this device. If the chosen base CPU ID is smaller
4900 * than the first valid CPU or larger than the last valid
4901 * CPU, we assume the user does not know what the valid
4902 * range is for this device and is thinking in terms of a
4903 * zero-based reference frame, and so we shift the given
4904 * value into the valid range (and wrap accordingly) so the
4905 * intent is translated to the proper frame of reference.
4906 * If the base CPU ID is within the valid first/last, but
4907 * does not correspond to a valid CPU, it is advanced to the
4908 * next valid CPU (wrapping if necessary).
4910 if (base_cpuid < first_valid || base_cpuid > last_valid) {
4911 /* shift from zero-based to first_valid-based */
4912 base_cpuid += first_valid;
4913 /* wrap to range [first_valid, last_valid] */
4914 base_cpuid = (base_cpuid - first_valid) %
4915 (last_valid - first_valid + 1);
4917 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) {
4919 * base_cpuid is in [first_valid, last_valid], but
4920 * not a member of the valid set. In this case,
4921 * there will always be a member of the valid set
4922 * with a CPU ID that is greater than base_cpuid,
4923 * and we simply advance to it.
4925 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus))
4928 return (base_cpuid);
4932 * Determine how many cores will be consumed by performing the CPU
4933 * assignments and counting how many of the assigned CPUs correspond
4934 * to CPUs in the set of context CPUs. This is done using the CPU
4935 * ID first_valid as the base CPU ID, as the base CPU must be within
4936 * the set of context CPUs.
4938 * Note not all assigned CPUs will be in the set of context CPUs
4939 * when separate CPUs are being allocated to TX and RX queues,
4940 * assignment to logical cores has been enabled, the set of context
4941 * CPUs contains only physical CPUs, and TX queues are mapped to L2
4942 * neighbors of CPUs that RX queues have been mapped to - in this
4943 * case we do only want to count how many CPUs in the set of context
4944 * CPUs have been consumed, as that determines the next CPU in that
4945 * set to start allocating at for the next device for which
4946 * core_offset is not set.
4948 CPU_ZERO(&assigned_cpus);
4949 for (i = 0; i < scctx->isc_ntxqsets; i++)
4950 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true),
4952 for (i = 0; i < scctx->isc_nrxqsets; i++)
4953 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false),
4955 CPU_AND(&assigned_cpus, &ctx->ifc_cpus);
4956 cores_consumed = CPU_COUNT(&assigned_cpus);
4958 mtx_lock(&cpu_offset_mtx);
4959 SLIST_FOREACH(op, &cpu_offsets, entries) {
4960 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4961 base_cpuid = op->next_cpuid;
4962 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid,
4964 MPASS(op->refcount < UINT_MAX);
4969 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) {
4970 base_cpuid = first_valid;
4971 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4974 device_printf(ctx->ifc_dev,
4975 "allocation for cpu offset failed.\n");
4977 op->next_cpuid = cpuid_advance(ctx, base_cpuid,
4980 CPU_COPY(&ctx->ifc_cpus, &op->set);
4981 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4984 mtx_unlock(&cpu_offset_mtx);
4986 return (base_cpuid);
4990 unref_ctx_core_offset(if_ctx_t ctx)
4992 struct cpu_offset *op, *top;
4994 mtx_lock(&cpu_offset_mtx);
4995 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4996 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4997 MPASS(op->refcount > 0);
4999 if (op->refcount == 0) {
5000 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
5006 mtx_unlock(&cpu_offset_mtx);
5010 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
5014 if_softc_ctx_t scctx;
5015 kobjop_desc_t kobj_desc;
5016 kobj_method_t *kobj_method;
5018 int num_txd, num_rxd;
5020 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
5023 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5024 device_set_softc(dev, ctx);
5025 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5028 ctx->ifc_sctx = sctx;
5030 ctx->ifc_softc = sc;
5032 if ((err = iflib_register(ctx)) != 0) {
5033 device_printf(dev, "iflib_register failed %d\n", err);
5036 iflib_add_device_sysctl_pre(ctx);
5038 scctx = &ctx->ifc_softc_ctx;
5041 iflib_reset_qvalues(ctx);
5043 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5044 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5047 _iflib_pre_assert(scctx);
5048 ctx->ifc_txrx = *scctx->isc_txrx;
5050 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR));
5052 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
5053 ctx->ifc_mediap = scctx->isc_media;
5056 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5057 MPASS(scctx->isc_tx_csum_flags);
5060 if_setcapabilities(ifp,
5061 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
5062 if_setcapenable(ifp,
5063 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
5065 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5066 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5067 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5068 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5070 num_txd = iflib_num_tx_descs(ctx);
5071 num_rxd = iflib_num_rx_descs(ctx);
5073 /* XXX change for per-queue sizes */
5074 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5077 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5078 scctx->isc_tx_nsegments = max(1, num_txd /
5079 MAX_SINGLE_PACKET_FRACTION);
5080 if (scctx->isc_tx_tso_segments_max > num_txd /
5081 MAX_SINGLE_PACKET_FRACTION)
5082 scctx->isc_tx_tso_segments_max = max(1,
5083 num_txd / MAX_SINGLE_PACKET_FRACTION);
5085 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5086 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5088 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5091 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5094 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5095 * into account. In the worst case, each of these calls will
5096 * add another mbuf and, thus, the requirement for another DMA
5097 * segment. So for best performance, it doesn't make sense to
5098 * advertize a maximum of TSO segments that typically will
5099 * require defragmentation in iflib_encap().
5101 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5102 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5104 if (scctx->isc_rss_table_size == 0)
5105 scctx->isc_rss_table_size = 64;
5106 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5108 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5109 /* XXX format name */
5110 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5111 NULL, NULL, "admin");
5113 /* Set up cpu set. If it fails, use the set of all CPUs. */
5114 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
5115 device_printf(dev, "Unable to fetch CPU list\n");
5116 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
5117 ctx->ifc_cpus_are_physical_cores = false;
5119 ctx->ifc_cpus_are_physical_cores = true;
5120 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
5123 ** Now set up MSI or MSI-X, should return us the number of supported
5124 ** vectors (will be 1 for a legacy interrupt and MSI).
5126 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
5127 msix = scctx->isc_vectors;
5128 } else if (scctx->isc_msix_bar != 0)
5130 * The simple fact that isc_msix_bar is not 0 does not mean we
5131 * we have a good value there that is known to work.
5133 msix = iflib_msix_init(ctx);
5135 scctx->isc_vectors = 1;
5136 scctx->isc_ntxqsets = 1;
5137 scctx->isc_nrxqsets = 1;
5138 scctx->isc_intr = IFLIB_INTR_LEGACY;
5141 /* Get memory for the station queues */
5142 if ((err = iflib_queues_alloc(ctx))) {
5143 device_printf(dev, "Unable to allocate queue memory\n");
5144 goto fail_intr_free;
5147 if ((err = iflib_qset_structures_setup(ctx)))
5151 * Now that we know how many queues there are, get the core offset.
5153 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
5157 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
5158 * aren't the default NULL implementation.
5160 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
5161 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5163 if (kobj_method == &kobj_desc->deflt) {
5165 "MSI-X requires ifdi_rx_queue_intr_enable method");
5169 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
5170 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5172 if (kobj_method == &kobj_desc->deflt) {
5174 "MSI-X requires ifdi_tx_queue_intr_enable method");
5180 * Assign the MSI-X vectors.
5181 * Note that the default NULL ifdi_msix_intr_assign method will
5184 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
5186 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
5190 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
5192 if (scctx->isc_intr == IFLIB_INTR_MSI) {
5196 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
5197 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
5202 "Cannot use iflib with only 1 MSI-X interrupt!\n");
5207 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5209 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5210 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5215 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5216 * This must appear after the call to ether_ifattach() because
5217 * ether_ifattach() sets if_hdrlen to the default value.
5219 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5220 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5222 if ((err = iflib_netmap_attach(ctx))) {
5223 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
5228 DEBUGNET_SET(ctx->ifc_ifp, iflib);
5230 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5231 iflib_add_device_sysctl_post(ctx);
5232 iflib_add_pfil(ctx);
5233 ctx->ifc_flags |= IFC_INIT_DONE;
5239 ether_ifdetach(ctx->ifc_ifp);
5241 iflib_tqg_detach(ctx);
5242 iflib_tx_structures_free(ctx);
5243 iflib_rx_structures_free(ctx);
5245 IFDI_QUEUES_FREE(ctx);
5247 iflib_free_intr_mem(ctx);
5250 iflib_deregister(ctx);
5252 device_set_softc(ctx->ifc_dev, NULL);
5253 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5254 free(ctx->ifc_softc, M_IFLIB);
5260 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
5261 struct iflib_cloneattach_ctx *clctx)
5263 int num_txd, num_rxd;
5267 if_softc_ctx_t scctx;
5271 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
5272 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5273 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5274 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
5275 ctx->ifc_flags |= IFC_PSEUDO;
5277 ctx->ifc_sctx = sctx;
5278 ctx->ifc_softc = sc;
5281 if ((err = iflib_register(ctx)) != 0) {
5282 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
5285 iflib_add_device_sysctl_pre(ctx);
5287 scctx = &ctx->ifc_softc_ctx;
5290 iflib_reset_qvalues(ctx);
5292 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5293 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5296 if (sctx->isc_flags & IFLIB_GEN_MAC)
5297 ether_gen_addr(ifp, &ctx->ifc_mac);
5298 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
5299 clctx->cc_params)) != 0) {
5300 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
5304 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5305 MPASS(scctx->isc_tx_csum_flags);
5308 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5309 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5311 ifp->if_flags |= IFF_NOGROUP;
5312 if (sctx->isc_flags & IFLIB_PSEUDO) {
5313 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5314 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5315 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
5316 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5318 if_attach(ctx->ifc_ifp);
5319 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
5322 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5323 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5329 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5330 * This must appear after the call to ether_ifattach() because
5331 * ether_ifattach() sets if_hdrlen to the default value.
5333 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5334 if_setifheaderlen(ifp,
5335 sizeof(struct ether_vlan_header));
5337 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5338 iflib_add_device_sysctl_post(ctx);
5339 ctx->ifc_flags |= IFC_INIT_DONE;
5343 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
5344 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5345 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5347 _iflib_pre_assert(scctx);
5348 ctx->ifc_txrx = *scctx->isc_txrx;
5350 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5351 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5352 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5353 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5355 num_txd = iflib_num_tx_descs(ctx);
5356 num_rxd = iflib_num_rx_descs(ctx);
5358 /* XXX change for per-queue sizes */
5359 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5362 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5363 scctx->isc_tx_nsegments = max(1, num_txd /
5364 MAX_SINGLE_PACKET_FRACTION);
5365 if (scctx->isc_tx_tso_segments_max > num_txd /
5366 MAX_SINGLE_PACKET_FRACTION)
5367 scctx->isc_tx_tso_segments_max = max(1,
5368 num_txd / MAX_SINGLE_PACKET_FRACTION);
5370 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5371 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5373 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5376 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5379 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5380 * into account. In the worst case, each of these calls will
5381 * add another mbuf and, thus, the requirement for another DMA
5382 * segment. So for best performance, it doesn't make sense to
5383 * advertize a maximum of TSO segments that typically will
5384 * require defragmentation in iflib_encap().
5386 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5387 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5389 if (scctx->isc_rss_table_size == 0)
5390 scctx->isc_rss_table_size = 64;
5391 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5393 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5394 /* XXX format name */
5395 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5396 NULL, NULL, "admin");
5398 /* XXX --- can support > 1 -- but keep it simple for now */
5399 scctx->isc_intr = IFLIB_INTR_LEGACY;
5401 /* Get memory for the station queues */
5402 if ((err = iflib_queues_alloc(ctx))) {
5403 device_printf(dev, "Unable to allocate queue memory\n");
5404 goto fail_iflib_detach;
5407 if ((err = iflib_qset_structures_setup(ctx))) {
5408 device_printf(dev, "qset structure setup failed %d\n", err);
5413 * XXX What if anything do we want to do about interrupts?
5415 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5416 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5417 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5422 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5423 * This must appear after the call to ether_ifattach() because
5424 * ether_ifattach() sets if_hdrlen to the default value.
5426 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5427 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5429 /* XXX handle more than one queue */
5430 for (i = 0; i < scctx->isc_nrxqsets; i++)
5431 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5435 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5436 iflib_add_device_sysctl_post(ctx);
5437 ctx->ifc_flags |= IFC_INIT_DONE;
5442 ether_ifdetach(ctx->ifc_ifp);
5444 iflib_tqg_detach(ctx);
5445 iflib_tx_structures_free(ctx);
5446 iflib_rx_structures_free(ctx);
5449 IFDI_QUEUES_FREE(ctx);
5452 iflib_deregister(ctx);
5454 free(ctx->ifc_softc, M_IFLIB);
5460 iflib_pseudo_deregister(if_ctx_t ctx)
5462 if_t ifp = ctx->ifc_ifp;
5463 if_shared_ctx_t sctx = ctx->ifc_sctx;
5465 /* Unregister VLAN event handlers early */
5466 iflib_unregister_vlan_handlers(ctx);
5468 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5469 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5473 ether_ifdetach(ifp);
5476 iflib_tqg_detach(ctx);
5477 iflib_tx_structures_free(ctx);
5478 iflib_rx_structures_free(ctx);
5480 IFDI_QUEUES_FREE(ctx);
5482 iflib_deregister(ctx);
5484 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5485 free(ctx->ifc_softc, M_IFLIB);
5491 iflib_device_attach(device_t dev)
5494 if_shared_ctx_t sctx;
5496 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5499 pci_enable_busmaster(dev);
5501 return (iflib_device_register(dev, NULL, sctx, &ctx));
5505 iflib_device_deregister(if_ctx_t ctx)
5507 if_t ifp = ctx->ifc_ifp;
5508 device_t dev = ctx->ifc_dev;
5510 /* Make sure VLANS are not using driver */
5511 if (if_vlantrunkinuse(ifp)) {
5512 device_printf(dev, "Vlan in use, detach first\n");
5516 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5517 device_printf(dev, "SR-IOV in use; detach first.\n");
5523 ctx->ifc_flags |= IFC_IN_DETACH;
5526 /* Unregister VLAN handlers before calling iflib_stop() */
5527 iflib_unregister_vlan_handlers(ctx);
5529 iflib_netmap_detach(ifp);
5530 ether_ifdetach(ifp);
5536 iflib_rem_pfil(ctx);
5537 if (ctx->ifc_led_dev != NULL)
5538 led_destroy(ctx->ifc_led_dev);
5540 iflib_tqg_detach(ctx);
5541 iflib_tx_structures_free(ctx);
5542 iflib_rx_structures_free(ctx);
5546 IFDI_QUEUES_FREE(ctx);
5549 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5550 iflib_free_intr_mem(ctx);
5552 bus_generic_detach(dev);
5554 iflib_deregister(ctx);
5556 device_set_softc(ctx->ifc_dev, NULL);
5557 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5558 free(ctx->ifc_softc, M_IFLIB);
5559 unref_ctx_core_offset(ctx);
5565 iflib_tqg_detach(if_ctx_t ctx)
5570 struct taskqgroup *tqg;
5572 /* XXX drain any dependent tasks */
5573 tqg = qgroup_if_io_tqg;
5574 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5575 callout_drain(&txq->ift_timer);
5577 callout_drain(&txq->ift_netmap_timer);
5578 #endif /* DEV_NETMAP */
5579 if (txq->ift_task.gt_uniq != NULL)
5580 taskqgroup_detach(tqg, &txq->ift_task);
5582 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5583 if (rxq->ifr_task.gt_uniq != NULL)
5584 taskqgroup_detach(tqg, &rxq->ifr_task);
5586 tqg = qgroup_if_config_tqg;
5587 if (ctx->ifc_admin_task.gt_uniq != NULL)
5588 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5589 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5590 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5594 iflib_free_intr_mem(if_ctx_t ctx)
5597 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5598 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5600 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5601 pci_release_msi(ctx->ifc_dev);
5603 if (ctx->ifc_msix_mem != NULL) {
5604 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5605 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5606 ctx->ifc_msix_mem = NULL;
5611 iflib_device_detach(device_t dev)
5613 if_ctx_t ctx = device_get_softc(dev);
5615 return (iflib_device_deregister(ctx));
5619 iflib_device_suspend(device_t dev)
5621 if_ctx_t ctx = device_get_softc(dev);
5627 return bus_generic_suspend(dev);
5630 iflib_device_shutdown(device_t dev)
5632 if_ctx_t ctx = device_get_softc(dev);
5638 return bus_generic_suspend(dev);
5642 iflib_device_resume(device_t dev)
5644 if_ctx_t ctx = device_get_softc(dev);
5645 iflib_txq_t txq = ctx->ifc_txqs;
5649 iflib_if_init_locked(ctx);
5651 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5652 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5654 return (bus_generic_resume(dev));
5658 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5661 if_ctx_t ctx = device_get_softc(dev);
5664 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5671 iflib_device_iov_uninit(device_t dev)
5673 if_ctx_t ctx = device_get_softc(dev);
5676 IFDI_IOV_UNINIT(ctx);
5681 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5684 if_ctx_t ctx = device_get_softc(dev);
5687 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5693 /*********************************************************************
5695 * MODULE FUNCTION DEFINITIONS
5697 **********************************************************************/
5700 * - Start a fast taskqueue thread for each core
5701 * - Start a taskqueue for control operations
5704 iflib_module_init(void)
5706 iflib_timer_default = hz / 2;
5711 iflib_module_event_handler(module_t mod, int what, void *arg)
5717 if ((err = iflib_module_init()) != 0)
5723 return (EOPNOTSUPP);
5729 /*********************************************************************
5731 * PUBLIC FUNCTION DEFINITIONS
5732 * ordered as in iflib.h
5734 **********************************************************************/
5737 _iflib_assert(if_shared_ctx_t sctx)
5741 MPASS(sctx->isc_tx_maxsize);
5742 MPASS(sctx->isc_tx_maxsegsize);
5744 MPASS(sctx->isc_rx_maxsize);
5745 MPASS(sctx->isc_rx_nsegments);
5746 MPASS(sctx->isc_rx_maxsegsize);
5748 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5749 for (i = 0; i < sctx->isc_nrxqs; i++) {
5750 MPASS(sctx->isc_nrxd_min[i]);
5751 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5752 MPASS(sctx->isc_nrxd_max[i]);
5753 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5754 MPASS(sctx->isc_nrxd_default[i]);
5755 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5758 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5759 for (i = 0; i < sctx->isc_ntxqs; i++) {
5760 MPASS(sctx->isc_ntxd_min[i]);
5761 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5762 MPASS(sctx->isc_ntxd_max[i]);
5763 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5764 MPASS(sctx->isc_ntxd_default[i]);
5765 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5770 _iflib_pre_assert(if_softc_ctx_t scctx)
5773 MPASS(scctx->isc_txrx->ift_txd_encap);
5774 MPASS(scctx->isc_txrx->ift_txd_flush);
5775 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5776 MPASS(scctx->isc_txrx->ift_rxd_available);
5777 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5778 MPASS(scctx->isc_txrx->ift_rxd_refill);
5779 MPASS(scctx->isc_txrx->ift_rxd_flush);
5783 iflib_register(if_ctx_t ctx)
5785 if_shared_ctx_t sctx = ctx->ifc_sctx;
5786 driver_t *driver = sctx->isc_driver;
5787 device_t dev = ctx->ifc_dev;
5792 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5793 _iflib_assert(sctx);
5796 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5797 if (sctx->isc_flags & IFLIB_PSEUDO) {
5798 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5804 ifp = ctx->ifc_ifp = if_alloc(type);
5806 device_printf(dev, "can not allocate ifnet structure\n");
5811 * Initialize our context's device specific methods
5813 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5814 kobj_class_compile((kobj_class_t) driver);
5816 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5817 if_setsoftc(ifp, ctx);
5818 if_setdev(ifp, dev);
5819 if_setinitfn(ifp, iflib_if_init);
5820 if_setioctlfn(ifp, iflib_if_ioctl);
5822 if_setstartfn(ifp, iflib_altq_if_start);
5823 if_settransmitfn(ifp, iflib_altq_if_transmit);
5824 if_setsendqready(ifp);
5826 if_settransmitfn(ifp, iflib_if_transmit);
5828 if_setqflushfn(ifp, iflib_if_qflush);
5829 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5831 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5832 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5833 iflags |= IFF_POINTOPOINT;
5835 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5836 if_setflags(ifp, iflags);
5837 ctx->ifc_vlan_attach_event =
5838 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5839 EVENTHANDLER_PRI_FIRST);
5840 ctx->ifc_vlan_detach_event =
5841 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5842 EVENTHANDLER_PRI_FIRST);
5844 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5845 ctx->ifc_mediap = &ctx->ifc_media;
5846 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5847 iflib_media_change, iflib_media_status);
5853 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5855 /* Unregister VLAN events */
5856 if (ctx->ifc_vlan_attach_event != NULL) {
5857 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5858 ctx->ifc_vlan_attach_event = NULL;
5860 if (ctx->ifc_vlan_detach_event != NULL) {
5861 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5862 ctx->ifc_vlan_detach_event = NULL;
5868 iflib_deregister(if_ctx_t ctx)
5870 if_t ifp = ctx->ifc_ifp;
5872 /* Remove all media */
5873 ifmedia_removeall(&ctx->ifc_media);
5875 /* Ensure that VLAN event handlers are unregistered */
5876 iflib_unregister_vlan_handlers(ctx);
5878 /* Release kobject reference */
5879 kobj_delete((kobj_t) ctx, NULL);
5881 /* Free the ifnet structure */
5884 STATE_LOCK_DESTROY(ctx);
5886 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5887 CTX_LOCK_DESTROY(ctx);
5891 iflib_queues_alloc(if_ctx_t ctx)
5893 if_shared_ctx_t sctx = ctx->ifc_sctx;
5894 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5895 device_t dev = ctx->ifc_dev;
5896 int nrxqsets = scctx->isc_nrxqsets;
5897 int ntxqsets = scctx->isc_ntxqsets;
5900 iflib_fl_t fl = NULL;
5901 int i, j, cpu, err, txconf, rxconf;
5902 iflib_dma_info_t ifdip;
5903 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5904 uint32_t *txqsizes = scctx->isc_txqsizes;
5905 uint8_t nrxqs = sctx->isc_nrxqs;
5906 uint8_t ntxqs = sctx->isc_ntxqs;
5907 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5908 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
5912 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5913 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5914 KASSERT(nrxqs >= fl_offset + nfree_lists,
5915 ("there must be at least a rxq for each free list"));
5917 /* Allocate the TX ring struct memory */
5918 if (!(ctx->ifc_txqs =
5919 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5920 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5921 device_printf(dev, "Unable to allocate TX ring memory\n");
5926 /* Now allocate the RX */
5927 if (!(ctx->ifc_rxqs =
5928 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5929 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5930 device_printf(dev, "Unable to allocate RX ring memory\n");
5935 txq = ctx->ifc_txqs;
5936 rxq = ctx->ifc_rxqs;
5939 * XXX handle allocation failure
5941 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5942 /* Set up some basics */
5944 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5945 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5947 "Unable to allocate TX DMA info memory\n");
5951 txq->ift_ifdi = ifdip;
5952 for (j = 0; j < ntxqs; j++, ifdip++) {
5953 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5955 "Unable to allocate TX descriptors\n");
5959 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5960 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5964 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5965 txq->ift_br_offset = 1;
5967 txq->ift_br_offset = 0;
5970 if (iflib_txsd_alloc(txq)) {
5971 device_printf(dev, "Critical Failure setting up TX buffers\n");
5976 /* Initialize the TX lock */
5977 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5978 device_get_nameunit(dev), txq->ift_id);
5979 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5980 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5981 txq->ift_timer.c_cpu = cpu;
5983 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
5984 txq->ift_netmap_timer.c_cpu = cpu;
5985 #endif /* DEV_NETMAP */
5987 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5988 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5990 /* XXX free any allocated rings */
5991 device_printf(dev, "Unable to allocate buf_ring\n");
5996 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5997 /* Set up some basics */
5998 callout_init(&rxq->ifr_watchdog, 1);
6000 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
6001 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
6003 "Unable to allocate RX DMA info memory\n");
6008 rxq->ifr_ifdi = ifdip;
6009 /* XXX this needs to be changed if #rx queues != #tx queues */
6010 rxq->ifr_ntxqirq = 1;
6011 rxq->ifr_txqid[0] = i;
6012 for (j = 0; j < nrxqs; j++, ifdip++) {
6013 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
6015 "Unable to allocate RX descriptors\n");
6019 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
6023 rxq->ifr_fl_offset = fl_offset;
6024 rxq->ifr_nfl = nfree_lists;
6026 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
6027 device_printf(dev, "Unable to allocate free list memory\n");
6032 for (j = 0; j < nfree_lists; j++) {
6033 fl[j].ifl_rxq = rxq;
6035 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
6036 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
6038 /* Allocate receive buffers for the ring */
6039 if (iflib_rxsd_alloc(rxq)) {
6041 "Critical Failure setting up receive buffers\n");
6046 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
6047 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
6052 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
6053 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
6054 for (i = 0; i < ntxqsets; i++) {
6055 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
6057 for (j = 0; j < ntxqs; j++, di++) {
6058 vaddrs[i*ntxqs + j] = di->idi_vaddr;
6059 paddrs[i*ntxqs + j] = di->idi_paddr;
6062 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
6063 device_printf(ctx->ifc_dev,
6064 "Unable to allocate device TX queue\n");
6065 iflib_tx_structures_free(ctx);
6066 free(vaddrs, M_IFLIB);
6067 free(paddrs, M_IFLIB);
6070 free(vaddrs, M_IFLIB);
6071 free(paddrs, M_IFLIB);
6074 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6075 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6076 for (i = 0; i < nrxqsets; i++) {
6077 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
6079 for (j = 0; j < nrxqs; j++, di++) {
6080 vaddrs[i*nrxqs + j] = di->idi_vaddr;
6081 paddrs[i*nrxqs + j] = di->idi_paddr;
6084 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
6085 device_printf(ctx->ifc_dev,
6086 "Unable to allocate device RX queue\n");
6087 iflib_tx_structures_free(ctx);
6088 free(vaddrs, M_IFLIB);
6089 free(paddrs, M_IFLIB);
6092 free(vaddrs, M_IFLIB);
6093 free(paddrs, M_IFLIB);
6097 /* XXX handle allocation failure changes */
6101 if (ctx->ifc_rxqs != NULL)
6102 free(ctx->ifc_rxqs, M_IFLIB);
6103 ctx->ifc_rxqs = NULL;
6104 if (ctx->ifc_txqs != NULL)
6105 free(ctx->ifc_txqs, M_IFLIB);
6106 ctx->ifc_txqs = NULL;
6112 iflib_tx_structures_setup(if_ctx_t ctx)
6114 iflib_txq_t txq = ctx->ifc_txqs;
6117 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
6118 iflib_txq_setup(txq);
6124 iflib_tx_structures_free(if_ctx_t ctx)
6126 iflib_txq_t txq = ctx->ifc_txqs;
6127 if_shared_ctx_t sctx = ctx->ifc_sctx;
6130 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6131 for (j = 0; j < sctx->isc_ntxqs; j++)
6132 iflib_dma_free(&txq->ift_ifdi[j]);
6133 iflib_txq_destroy(txq);
6135 free(ctx->ifc_txqs, M_IFLIB);
6136 ctx->ifc_txqs = NULL;
6139 /*********************************************************************
6141 * Initialize all receive rings.
6143 **********************************************************************/
6145 iflib_rx_structures_setup(if_ctx_t ctx)
6147 iflib_rxq_t rxq = ctx->ifc_rxqs;
6149 #if defined(INET6) || defined(INET)
6153 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
6154 #if defined(INET6) || defined(INET)
6155 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
6156 TCP_LRO_ENTRIES, min(1024,
6157 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
6159 device_printf(ctx->ifc_dev,
6160 "LRO Initialization failed!\n");
6164 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
6167 #if defined(INET6) || defined(INET)
6170 * Free LRO resources allocated so far, we will only handle
6171 * the rings that completed, the failing case will have
6172 * cleaned up for itself. 'q' failed, so its the terminus.
6174 rxq = ctx->ifc_rxqs;
6175 for (i = 0; i < q; ++i, rxq++) {
6176 tcp_lro_free(&rxq->ifr_lc);
6182 /*********************************************************************
6184 * Free all receive rings.
6186 **********************************************************************/
6188 iflib_rx_structures_free(if_ctx_t ctx)
6190 iflib_rxq_t rxq = ctx->ifc_rxqs;
6191 if_shared_ctx_t sctx = ctx->ifc_sctx;
6194 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
6195 for (j = 0; j < sctx->isc_nrxqs; j++)
6196 iflib_dma_free(&rxq->ifr_ifdi[j]);
6197 iflib_rx_sds_free(rxq);
6198 #if defined(INET6) || defined(INET)
6199 tcp_lro_free(&rxq->ifr_lc);
6202 free(ctx->ifc_rxqs, M_IFLIB);
6203 ctx->ifc_rxqs = NULL;
6207 iflib_qset_structures_setup(if_ctx_t ctx)
6212 * It is expected that the caller takes care of freeing queues if this
6215 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
6216 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
6220 if ((err = iflib_rx_structures_setup(ctx)) != 0)
6221 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
6227 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
6228 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
6231 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
6234 /* Just to avoid copy/paste */
6236 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6237 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6241 unsigned int base_cpuid, cpuid;
6245 base_cpuid = ctx->ifc_sysctl_core_offset;
6246 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX);
6247 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev,
6248 irq ? irq->ii_res : NULL, name);
6250 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6254 if (cpuid > ctx->ifc_cpuid_highest)
6255 ctx->ifc_cpuid_highest = cpuid;
6261 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6262 iflib_intr_type_t type, driver_filter_t *filter,
6263 void *filter_arg, int qid, const char *name)
6266 struct grouptask *gtask;
6267 struct taskqgroup *tqg;
6268 iflib_filter_info_t info;
6271 driver_filter_t *intr_fast;
6274 info = &ctx->ifc_filter_info;
6278 /* XXX merge tx/rx for netmap? */
6280 q = &ctx->ifc_txqs[qid];
6281 info = &ctx->ifc_txqs[qid].ift_filter_info;
6282 gtask = &ctx->ifc_txqs[qid].ift_task;
6283 tqg = qgroup_if_io_tqg;
6285 intr_fast = iflib_fast_intr;
6286 GROUPTASK_INIT(gtask, 0, fn, q);
6287 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6290 q = &ctx->ifc_rxqs[qid];
6291 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6292 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6293 tqg = qgroup_if_io_tqg;
6295 intr_fast = iflib_fast_intr;
6296 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6298 case IFLIB_INTR_RXTX:
6299 q = &ctx->ifc_rxqs[qid];
6300 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6301 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6302 tqg = qgroup_if_io_tqg;
6304 intr_fast = iflib_fast_intr_rxtx;
6305 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6307 case IFLIB_INTR_ADMIN:
6310 info = &ctx->ifc_filter_info;
6311 gtask = &ctx->ifc_admin_task;
6312 tqg = qgroup_if_config_tqg;
6313 fn = _task_fn_admin;
6314 intr_fast = iflib_fast_intr_ctx;
6317 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6322 info->ifi_filter = filter;
6323 info->ifi_filter_arg = filter_arg;
6324 info->ifi_task = gtask;
6328 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6330 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6333 if (type == IFLIB_INTR_ADMIN)
6337 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6342 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6349 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6352 struct grouptask *gtask;
6353 struct taskqgroup *tqg;
6360 q = &ctx->ifc_txqs[qid];
6361 gtask = &ctx->ifc_txqs[qid].ift_task;
6362 tqg = qgroup_if_io_tqg;
6364 GROUPTASK_INIT(gtask, 0, fn, q);
6367 q = &ctx->ifc_rxqs[qid];
6368 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6369 tqg = qgroup_if_io_tqg;
6371 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6373 case IFLIB_INTR_IOV:
6375 gtask = &ctx->ifc_vflr_task;
6376 tqg = qgroup_if_config_tqg;
6378 GROUPTASK_INIT(gtask, 0, fn, q);
6381 panic("unknown net intr type");
6383 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name);
6386 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL,
6392 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6396 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6399 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6400 rman_get_rid(irq->ii_res), irq->ii_res);
6404 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6406 iflib_txq_t txq = ctx->ifc_txqs;
6407 iflib_rxq_t rxq = ctx->ifc_rxqs;
6408 if_irq_t irq = &ctx->ifc_legacy_irq;
6409 iflib_filter_info_t info;
6411 struct grouptask *gtask;
6412 struct resource *res;
6413 struct taskqgroup *tqg;
6418 q = &ctx->ifc_rxqs[0];
6419 info = &rxq[0].ifr_filter_info;
6420 gtask = &rxq[0].ifr_task;
6421 tqg = qgroup_if_io_tqg;
6423 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6425 ctx->ifc_flags |= IFC_LEGACY;
6426 info->ifi_filter = filter;
6427 info->ifi_filter_arg = filter_arg;
6428 info->ifi_task = gtask;
6429 info->ifi_ctx = rx_only ? ctx : q;
6432 /* We allocate a single interrupt resource */
6433 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6434 iflib_fast_intr_rxtx, NULL, info, name);
6437 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6439 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6441 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6442 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6448 iflib_led_create(if_ctx_t ctx)
6451 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6452 device_get_nameunit(ctx->ifc_dev));
6456 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6459 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6463 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6466 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6470 iflib_admin_intr_deferred(if_ctx_t ctx)
6473 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6474 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6478 iflib_iov_intr_deferred(if_ctx_t ctx)
6481 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6485 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6488 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6493 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6497 GROUPTASK_INIT(gtask, 0, fn, ctx);
6498 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6503 iflib_config_gtask_deinit(struct grouptask *gtask)
6506 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6510 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6512 if_t ifp = ctx->ifc_ifp;
6513 iflib_txq_t txq = ctx->ifc_txqs;
6515 if_setbaudrate(ifp, baudrate);
6516 if (baudrate >= IF_Gbps(10)) {
6518 ctx->ifc_flags |= IFC_PREFETCH;
6521 /* If link down, disable watchdog */
6522 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6523 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6524 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6526 ctx->ifc_link_state = link_state;
6527 if_link_state_change(ifp, link_state);
6531 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6535 int credits_pre = txq->ift_cidx_processed;
6538 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6539 BUS_DMASYNC_POSTREAD);
6540 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6543 txq->ift_processed += credits;
6544 txq->ift_cidx_processed += credits;
6546 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6547 if (txq->ift_cidx_processed >= txq->ift_size)
6548 txq->ift_cidx_processed -= txq->ift_size;
6553 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6558 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6559 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6560 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6561 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6566 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6567 const char *description, if_int_delay_info_t info,
6568 int offset, int value)
6570 info->iidi_ctx = ctx;
6571 info->iidi_offset = offset;
6572 info->iidi_value = value;
6573 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6574 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6575 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6576 info, 0, iflib_sysctl_int_delay, "I", description);
6580 iflib_ctx_lock_get(if_ctx_t ctx)
6583 return (&ctx->ifc_ctx_sx);
6587 iflib_msix_init(if_ctx_t ctx)
6589 device_t dev = ctx->ifc_dev;
6590 if_shared_ctx_t sctx = ctx->ifc_sctx;
6591 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6592 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6593 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6595 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6596 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6599 device_printf(dev, "msix_init qsets capped at %d\n",
6600 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6602 /* Override by tuneable */
6603 if (scctx->isc_disable_msix)
6606 /* First try MSI-X */
6607 if ((msgs = pci_msix_count(dev)) == 0) {
6609 device_printf(dev, "MSI-X not supported or disabled\n");
6613 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6615 * bar == -1 => "trust me I know what I'm doing"
6616 * Some drivers are for hardware that is so shoddily
6617 * documented that no one knows which bars are which
6618 * so the developer has to map all bars. This hack
6619 * allows shoddy garbage to use MSI-X in this framework.
6622 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6623 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6624 if (ctx->ifc_msix_mem == NULL) {
6625 device_printf(dev, "Unable to map MSI-X table\n");
6630 admincnt = sctx->isc_admin_intrcnt;
6632 /* use only 1 qset in debug mode */
6633 queuemsgs = min(msgs - admincnt, 1);
6635 queuemsgs = msgs - admincnt;
6638 queues = imin(queuemsgs, rss_getnumbuckets());
6642 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6645 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6646 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6648 /* If we're doing RSS, clamp at the number of RSS buckets */
6649 if (queues > rss_getnumbuckets())
6650 queues = rss_getnumbuckets();
6652 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6653 rx_queues = iflib_num_rx_queues;
6657 if (rx_queues > scctx->isc_nrxqsets)
6658 rx_queues = scctx->isc_nrxqsets;
6661 * We want this to be all logical CPUs by default
6663 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6664 tx_queues = iflib_num_tx_queues;
6666 tx_queues = mp_ncpus;
6668 if (tx_queues > scctx->isc_ntxqsets)
6669 tx_queues = scctx->isc_ntxqsets;
6671 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6673 if (tx_queues != rx_queues)
6675 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6676 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6678 tx_queues = min(rx_queues, tx_queues);
6679 rx_queues = min(rx_queues, tx_queues);
6682 vectors = rx_queues + admincnt;
6683 if (msgs < vectors) {
6685 "insufficient number of MSI-X vectors "
6686 "(supported %d, need %d)\n", msgs, vectors);
6690 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6693 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6694 if (vectors != msgs) {
6696 "Unable to allocate sufficient MSI-X vectors "
6697 "(got %d, need %d)\n", vectors, msgs);
6698 pci_release_msi(dev);
6700 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6702 ctx->ifc_msix_mem = NULL;
6706 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6708 scctx->isc_vectors = vectors;
6709 scctx->isc_nrxqsets = rx_queues;
6710 scctx->isc_ntxqsets = tx_queues;
6711 scctx->isc_intr = IFLIB_INTR_MSIX;
6716 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6719 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6721 ctx->ifc_msix_mem = NULL;
6726 vectors = pci_msi_count(dev);
6727 scctx->isc_nrxqsets = 1;
6728 scctx->isc_ntxqsets = 1;
6729 scctx->isc_vectors = vectors;
6730 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6731 device_printf(dev,"Using an MSI interrupt\n");
6732 scctx->isc_intr = IFLIB_INTR_MSI;
6734 scctx->isc_vectors = 1;
6735 device_printf(dev,"Using a Legacy interrupt\n");
6736 scctx->isc_intr = IFLIB_INTR_LEGACY;
6742 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6745 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6748 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6750 const char *ring_state = "UNKNOWN";
6753 rc = sysctl_wire_old_buffer(req, 0);
6757 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6762 ring_state = ring_states[state[3]];
6764 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6765 state[0], state[1], state[2], ring_state);
6766 rc = sbuf_finish(sb);
6771 enum iflib_ndesc_handler {
6777 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6779 if_ctx_t ctx = (void *)arg1;
6780 enum iflib_ndesc_handler type = arg2;
6781 char buf[256] = {0};
6788 case IFLIB_NTXD_HANDLER:
6789 ndesc = ctx->ifc_sysctl_ntxds;
6791 nqs = ctx->ifc_sctx->isc_ntxqs;
6793 case IFLIB_NRXD_HANDLER:
6794 ndesc = ctx->ifc_sysctl_nrxds;
6796 nqs = ctx->ifc_sctx->isc_nrxqs;
6799 printf("%s: unhandled type\n", __func__);
6805 for (i=0; i<8; i++) {
6810 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6813 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6814 if (rc || req->newptr == NULL)
6817 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6818 i++, p = strsep(&next, " ,")) {
6819 ndesc[i] = strtoul(p, NULL, 10);
6825 #define NAME_BUFLEN 32
6827 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6829 device_t dev = iflib_get_dev(ctx);
6830 struct sysctl_oid_list *child, *oid_list;
6831 struct sysctl_ctx_list *ctx_list;
6832 struct sysctl_oid *node;
6834 ctx_list = device_get_sysctl_ctx(dev);
6835 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6836 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6837 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6838 oid_list = SYSCTL_CHILDREN(node);
6840 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6841 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6844 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6845 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6846 "# of txqs to use, 0 => use default #");
6847 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6848 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6849 "# of rxqs to use, 0 => use default #");
6850 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6851 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6852 "permit #txq != #rxq");
6853 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6854 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6855 "disable MSI-X (default 0)");
6856 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6857 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6858 "set the RX budget");
6859 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6860 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6861 "cause TX to abdicate instead of running to completion");
6862 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6863 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6864 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6865 "offset to start using cores at");
6866 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6867 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6868 "use separate cores for TX and RX");
6869 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores",
6870 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0,
6871 "try to make use of logical cores for TX and RX");
6873 /* XXX change for per-queue sizes */
6874 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6875 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6876 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6877 "list of # of TX descriptors to use, 0 = use default #");
6878 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6879 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6880 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6881 "list of # of RX descriptors to use, 0 = use default #");
6885 iflib_add_device_sysctl_post(if_ctx_t ctx)
6887 if_shared_ctx_t sctx = ctx->ifc_sctx;
6888 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6889 device_t dev = iflib_get_dev(ctx);
6890 struct sysctl_oid_list *child;
6891 struct sysctl_ctx_list *ctx_list;
6896 char namebuf[NAME_BUFLEN];
6898 struct sysctl_oid *queue_node, *fl_node, *node;
6899 struct sysctl_oid_list *queue_list, *fl_list;
6900 ctx_list = device_get_sysctl_ctx(dev);
6902 node = ctx->ifc_sysctl_node;
6903 child = SYSCTL_CHILDREN(node);
6905 if (scctx->isc_ntxqsets > 100)
6907 else if (scctx->isc_ntxqsets > 10)
6911 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6912 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6913 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6914 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6915 queue_list = SYSCTL_CHILDREN(queue_node);
6916 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6918 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to");
6920 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6922 &txq->ift_dequeued, "total mbufs freed");
6923 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6925 &txq->ift_enqueued, "total mbufs enqueued");
6927 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6929 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6930 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6932 &txq->ift_pullups, "# of times m_pullup was called");
6933 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6935 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6936 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6938 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6939 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6941 &txq->ift_map_failed, "# of times DMA map failed");
6942 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6944 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6945 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6947 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6948 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6950 &txq->ift_pidx, 1, "Producer Index");
6951 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6953 &txq->ift_cidx, 1, "Consumer Index");
6954 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6956 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6957 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6959 &txq->ift_in_use, 1, "descriptors in use");
6960 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6962 &txq->ift_processed, "descriptors procesed for clean");
6963 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6965 &txq->ift_cleaned, "total cleaned");
6966 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6967 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6968 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6969 mp_ring_state_handler, "A", "soft ring state");
6970 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6971 CTLFLAG_RD, &txq->ift_br->enqueues,
6972 "# of enqueues to the mp_ring for this queue");
6973 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6974 CTLFLAG_RD, &txq->ift_br->drops,
6975 "# of drops in the mp_ring for this queue");
6976 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6977 CTLFLAG_RD, &txq->ift_br->starts,
6978 "# of normal consumer starts in the mp_ring for this queue");
6979 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6980 CTLFLAG_RD, &txq->ift_br->stalls,
6981 "# of consumer stalls in the mp_ring for this queue");
6982 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6983 CTLFLAG_RD, &txq->ift_br->restarts,
6984 "# of consumer restarts in the mp_ring for this queue");
6985 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6986 CTLFLAG_RD, &txq->ift_br->abdications,
6987 "# of consumer abdications in the mp_ring for this queue");
6990 if (scctx->isc_nrxqsets > 100)
6992 else if (scctx->isc_nrxqsets > 10)
6996 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6997 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6998 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6999 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
7000 queue_list = SYSCTL_CHILDREN(queue_node);
7001 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
7003 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to");
7004 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
7005 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
7007 &rxq->ifr_cq_cidx, 1, "Consumer Index");
7010 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
7011 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
7012 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
7013 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
7014 fl_list = SYSCTL_CHILDREN(fl_node);
7015 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
7017 &fl->ifl_pidx, 1, "Producer Index");
7018 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
7020 &fl->ifl_cidx, 1, "Consumer Index");
7021 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
7023 &fl->ifl_credits, 1, "credits available");
7024 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
7026 &fl->ifl_buf_size, 1, "buffer size");
7028 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
7030 &fl->ifl_m_enqueued, "mbufs allocated");
7031 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
7033 &fl->ifl_m_dequeued, "mbufs freed");
7034 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
7036 &fl->ifl_cl_enqueued, "clusters allocated");
7037 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
7039 &fl->ifl_cl_dequeued, "clusters freed");
7047 iflib_request_reset(if_ctx_t ctx)
7051 ctx->ifc_flags |= IFC_DO_RESET;
7055 #ifndef __NO_STRICT_ALIGNMENT
7056 static struct mbuf *
7057 iflib_fixup_rx(struct mbuf *m)
7061 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
7062 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
7063 m->m_data += ETHER_HDR_LEN;
7066 MGETHDR(n, M_NOWAIT, MT_DATA);
7071 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
7072 m->m_data += ETHER_HDR_LEN;
7073 m->m_len -= ETHER_HDR_LEN;
7074 n->m_len = ETHER_HDR_LEN;
7075 M_MOVE_PKTHDR(n, m);
7084 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
7088 ctx = if_getsoftc(ifp);
7090 *nrxr = NRXQSETS(ctx);
7091 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
7092 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
7097 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
7100 if_softc_ctx_t scctx;
7105 ctx = if_getsoftc(ifp);
7106 scctx = &ctx->ifc_softc_ctx;
7109 case DEBUGNET_START:
7110 for (i = 0; i < scctx->isc_nrxqsets; i++) {
7111 rxq = &ctx->ifc_rxqs[i];
7112 for (j = 0; j < rxq->ifr_nfl; j++) {
7114 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
7117 iflib_no_tx_batch = 1;
7125 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
7131 ctx = if_getsoftc(ifp);
7132 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7136 txq = &ctx->ifc_txqs[0];
7137 error = iflib_encap(txq, &m);
7139 (void)iflib_txd_db_check(txq, true);
7144 iflib_debugnet_poll(if_t ifp, int count)
7146 struct epoch_tracker et;
7148 if_softc_ctx_t scctx;
7152 ctx = if_getsoftc(ifp);
7153 scctx = &ctx->ifc_softc_ctx;
7155 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7159 txq = &ctx->ifc_txqs[0];
7160 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
7162 NET_EPOCH_ENTER(et);
7163 for (i = 0; i < scctx->isc_nrxqsets; i++)
7164 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7168 #endif /* DEBUGNET */