2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
95 #if defined(__i386__) || defined(__amd64__)
96 #include <sys/memdesc.h>
97 #include <machine/bus.h>
98 #include <machine/md_var.h>
99 #include <machine/specialreg.h>
100 #include <x86/include/busdma_impl.h>
101 #include <x86/iommu/busdma_dmar.h>
104 #include <sys/bitstring.h>
106 * enable accounting of every mbuf as it comes in to and goes out of
107 * iflib's software descriptor references
109 #define MEMORY_LOGGING 0
111 * Enable mbuf vectors for compressing long mbuf chains
116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
117 * we prefetch needs to be determined by the time spent in m_free vis a vis
118 * the cost of a prefetch. This will of course vary based on the workload:
119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
120 * is quite expensive, thus suggesting very little prefetch.
121 * - small packet forwarding which is just returning a single mbuf to
122 * UMA will typically be very fast vis a vis the cost of a memory
129 * - private structures
130 * - iflib private utility functions
132 * - vlan registry and other exported functions
133 * - iflib public core functions
137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
140 typedef struct iflib_txq *iflib_txq_t;
142 typedef struct iflib_rxq *iflib_rxq_t;
144 typedef struct iflib_fl *iflib_fl_t;
148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
150 typedef struct iflib_filter_info {
151 driver_filter_t *ifi_filter;
152 void *ifi_filter_arg;
153 struct grouptask *ifi_task;
155 } *iflib_filter_info_t;
160 * Pointer to hardware driver's softc
167 if_shared_ctx_t ifc_sctx;
168 struct if_softc_ctx ifc_softc_ctx;
170 struct sx ifc_ctx_sx;
171 struct mtx ifc_state_mtx;
173 uint16_t ifc_nhwtxqs;
175 iflib_txq_t ifc_txqs;
176 iflib_rxq_t ifc_rxqs;
177 uint32_t ifc_if_flags;
179 uint32_t ifc_max_fl_buf_size;
184 int ifc_watchdog_events;
185 struct cdev *ifc_led_dev;
186 struct resource *ifc_msix_mem;
188 struct if_irq ifc_legacy_irq;
189 struct grouptask ifc_admin_task;
190 struct grouptask ifc_vflr_task;
191 struct iflib_filter_info ifc_filter_info;
192 struct ifmedia ifc_media;
194 struct sysctl_oid *ifc_sysctl_node;
195 uint16_t ifc_sysctl_ntxqs;
196 uint16_t ifc_sysctl_nrxqs;
197 uint16_t ifc_sysctl_qs_eq_override;
198 uint16_t ifc_sysctl_rx_budget;
200 qidx_t ifc_sysctl_ntxds[8];
201 qidx_t ifc_sysctl_nrxds[8];
202 struct if_txrx ifc_txrx;
203 #define isc_txd_encap ifc_txrx.ift_txd_encap
204 #define isc_txd_flush ifc_txrx.ift_txd_flush
205 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
206 #define isc_rxd_available ifc_txrx.ift_rxd_available
207 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
209 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
213 eventhandler_tag ifc_vlan_attach_event;
214 eventhandler_tag ifc_vlan_detach_event;
215 uint8_t ifc_mac[ETHER_ADDR_LEN];
216 char ifc_mtx_name[16];
221 iflib_get_softc(if_ctx_t ctx)
224 return (ctx->ifc_softc);
228 iflib_get_dev(if_ctx_t ctx)
231 return (ctx->ifc_dev);
235 iflib_get_ifp(if_ctx_t ctx)
238 return (ctx->ifc_ifp);
242 iflib_get_media(if_ctx_t ctx)
245 return (&ctx->ifc_media);
249 iflib_get_flags(if_ctx_t ctx)
251 return (ctx->ifc_flags);
255 iflib_set_detach(if_ctx_t ctx)
257 ctx->ifc_in_detach = 1;
261 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
264 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
268 iflib_get_softc_ctx(if_ctx_t ctx)
271 return (&ctx->ifc_softc_ctx);
275 iflib_get_sctx(if_ctx_t ctx)
278 return (ctx->ifc_sctx);
281 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
282 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
283 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
285 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
286 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
288 #define RX_SW_DESC_MAP_CREATED (1 << 0)
289 #define TX_SW_DESC_MAP_CREATED (1 << 1)
290 #define RX_SW_DESC_INUSE (1 << 3)
291 #define TX_SW_DESC_MAPPED (1 << 4)
293 #define M_TOOBIG M_PROTO1
295 typedef struct iflib_sw_rx_desc_array {
296 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
297 struct mbuf **ifsd_m; /* pkthdr mbufs */
298 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
300 } iflib_rxsd_array_t;
302 typedef struct iflib_sw_tx_desc_array {
303 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
304 struct mbuf **ifsd_m; /* pkthdr mbufs */
309 /* magic number that should be high enough for any hardware */
310 #define IFLIB_MAX_TX_SEGS 128
311 /* bnxt supports 64 with hardware LRO enabled */
312 #define IFLIB_MAX_RX_SEGS 64
313 #define IFLIB_RX_COPY_THRESH 128
314 #define IFLIB_MAX_RX_REFRESH 32
315 /* The minimum descriptors per second before we start coalescing */
316 #define IFLIB_MIN_DESC_SEC 16384
317 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
318 #define IFLIB_QUEUE_IDLE 0
319 #define IFLIB_QUEUE_HUNG 1
320 #define IFLIB_QUEUE_WORKING 2
321 /* maximum number of txqs that can share an rx interrupt */
322 #define IFLIB_MAX_TX_SHARED_INTR 4
324 /* this should really scale with ring size - this is a fairly arbitrary value */
325 #define TX_BATCH_SIZE 32
327 #define IFLIB_RESTART_BUDGET 8
330 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
331 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
332 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
336 qidx_t ift_cidx_processed;
339 uint8_t ift_br_offset;
340 uint16_t ift_npending;
341 uint16_t ift_db_pending;
342 uint16_t ift_rs_pending;
344 uint8_t ift_txd_size[8];
345 uint64_t ift_processed;
346 uint64_t ift_cleaned;
347 uint64_t ift_cleaned_prev;
349 uint64_t ift_enqueued;
350 uint64_t ift_dequeued;
352 uint64_t ift_no_tx_dma_setup;
353 uint64_t ift_no_desc_avail;
354 uint64_t ift_mbuf_defrag_failed;
355 uint64_t ift_mbuf_defrag;
356 uint64_t ift_map_failed;
357 uint64_t ift_txd_encap_efbig;
358 uint64_t ift_pullups;
361 struct mtx ift_db_mtx;
363 /* constant values */
365 struct ifmp_ring *ift_br;
366 struct grouptask ift_task;
369 struct callout ift_timer;
371 if_txsd_vec_t ift_sds;
374 uint8_t ift_update_freq;
375 struct iflib_filter_info ift_filter_info;
376 bus_dma_tag_t ift_desc_tag;
377 bus_dma_tag_t ift_tso_desc_tag;
378 iflib_dma_info_t ift_ifdi;
379 #define MTX_NAME_LEN 16
380 char ift_mtx_name[MTX_NAME_LEN];
381 char ift_db_mtx_name[MTX_NAME_LEN];
382 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
383 #ifdef IFLIB_DIAGNOSTICS
384 uint64_t ift_cpu_exec_count[256];
386 } __aligned(CACHE_LINE_SIZE);
393 uint8_t ifl_rxd_size;
395 uint64_t ifl_m_enqueued;
396 uint64_t ifl_m_dequeued;
397 uint64_t ifl_cl_enqueued;
398 uint64_t ifl_cl_dequeued;
402 bitstr_t *ifl_rx_bitmap;
406 uint16_t ifl_buf_size;
409 iflib_rxsd_array_t ifl_sds;
412 bus_dma_tag_t ifl_desc_tag;
413 iflib_dma_info_t ifl_ifdi;
414 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
415 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
417 } __aligned(CACHE_LINE_SIZE);
420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
426 else if (pidx < cidx)
427 used = size - cidx + pidx;
428 else if (gen == 0 && pidx == cidx)
430 else if (gen == 1 && pidx == cidx)
438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
440 #define IDXDIFF(head, tail, wrap) \
441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
444 /* If there is a separate completion queue -
445 * these are the cq cidx and pidx. Otherwise
452 uint8_t ifr_fl_offset;
458 uint8_t ifr_lro_enabled;
461 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
462 struct lro_ctrl ifr_lc;
463 struct grouptask ifr_task;
464 struct iflib_filter_info ifr_filter_info;
465 iflib_dma_info_t ifr_ifdi;
467 /* dynamically allocate if any drivers need a value substantially larger than this */
468 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
469 #ifdef IFLIB_DIAGNOSTICS
470 uint64_t ifr_cpu_exec_count[256];
472 } __aligned(CACHE_LINE_SIZE);
474 typedef struct if_rxsd {
476 struct mbuf **ifsd_m;
481 /* multiple of word size */
483 #define PKT_INFO_SIZE 6
484 #define RXD_INFO_SIZE 5
485 #define PKT_TYPE uint64_t
487 #define PKT_INFO_SIZE 11
488 #define RXD_INFO_SIZE 8
489 #define PKT_TYPE uint32_t
491 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
492 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
494 typedef struct if_pkt_info_pad {
495 PKT_TYPE pkt_val[PKT_INFO_SIZE];
496 } *if_pkt_info_pad_t;
497 typedef struct if_rxd_info_pad {
498 PKT_TYPE rxd_val[RXD_INFO_SIZE];
499 } *if_rxd_info_pad_t;
501 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
502 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
506 pkt_info_zero(if_pkt_info_t pi)
508 if_pkt_info_pad_t pi_pad;
510 pi_pad = (if_pkt_info_pad_t)pi;
511 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
512 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
514 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
515 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
519 static device_method_t iflib_pseudo_methods[] = {
520 DEVMETHOD(device_attach, noop_attach),
521 DEVMETHOD(device_detach, iflib_pseudo_detach),
525 driver_t iflib_pseudodriver = {
526 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
530 rxd_info_zero(if_rxd_info_t ri)
532 if_rxd_info_pad_t ri_pad;
535 ri_pad = (if_rxd_info_pad_t)ri;
536 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
537 ri_pad->rxd_val[i] = 0;
538 ri_pad->rxd_val[i+1] = 0;
539 ri_pad->rxd_val[i+2] = 0;
540 ri_pad->rxd_val[i+3] = 0;
543 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
548 * Only allow a single packet to take up most 1/nth of the tx ring
550 #define MAX_SINGLE_PACKET_FRACTION 12
551 #define IF_BAD_DMA (bus_addr_t)-1
553 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
555 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
556 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
557 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
558 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
561 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
562 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
563 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
564 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
568 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
569 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
572 /* Our boot-time initialization hook */
573 static int iflib_module_event_handler(module_t, int, void *);
575 static moduledata_t iflib_moduledata = {
577 iflib_module_event_handler,
581 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
582 MODULE_VERSION(iflib, 1);
584 MODULE_DEPEND(iflib, pci, 1, 1, 1);
585 MODULE_DEPEND(iflib, ether, 1, 1, 1);
587 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
588 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
590 #ifndef IFLIB_DEBUG_COUNTERS
592 #define IFLIB_DEBUG_COUNTERS 1
594 #define IFLIB_DEBUG_COUNTERS 0
595 #endif /* !INVARIANTS */
598 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
599 "iflib driver parameters");
602 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
604 static int iflib_min_tx_latency = 0;
605 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
606 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
607 static int iflib_no_tx_batch = 0;
608 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
609 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
612 #if IFLIB_DEBUG_COUNTERS
614 static int iflib_tx_seen;
615 static int iflib_tx_sent;
616 static int iflib_tx_encap;
617 static int iflib_rx_allocs;
618 static int iflib_fl_refills;
619 static int iflib_fl_refills_large;
620 static int iflib_tx_frees;
622 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
623 &iflib_tx_seen, 0, "# tx mbufs seen");
624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
625 &iflib_tx_sent, 0, "# tx mbufs sent");
626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
627 &iflib_tx_encap, 0, "# tx mbufs encapped");
628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
629 &iflib_tx_frees, 0, "# tx frees");
630 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
631 &iflib_rx_allocs, 0, "# rx allocations");
632 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
633 &iflib_fl_refills, 0, "# refills");
634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
635 &iflib_fl_refills_large, 0, "# large refills");
638 static int iflib_txq_drain_flushing;
639 static int iflib_txq_drain_oactive;
640 static int iflib_txq_drain_notready;
641 static int iflib_txq_drain_encapfail;
643 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
644 &iflib_txq_drain_flushing, 0, "# drain flushes");
645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
646 &iflib_txq_drain_oactive, 0, "# drain oactives");
647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
648 &iflib_txq_drain_notready, 0, "# drain notready");
649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
650 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
653 static int iflib_encap_load_mbuf_fail;
654 static int iflib_encap_pad_mbuf_fail;
655 static int iflib_encap_txq_avail_fail;
656 static int iflib_encap_txd_encap_fail;
658 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
659 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
661 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
663 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
665 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
667 static int iflib_task_fn_rxs;
668 static int iflib_rx_intr_enables;
669 static int iflib_fast_intrs;
670 static int iflib_intr_link;
671 static int iflib_intr_msix;
672 static int iflib_rx_unavail;
673 static int iflib_rx_ctx_inactive;
674 static int iflib_rx_zero_len;
675 static int iflib_rx_if_input;
676 static int iflib_rx_mbuf_null;
677 static int iflib_rxd_flush;
679 static int iflib_verbose_debug;
681 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
682 &iflib_intr_link, 0, "# intr link calls");
683 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
684 &iflib_intr_msix, 0, "# intr msix calls");
685 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
686 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
687 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
688 &iflib_rx_intr_enables, 0, "# rx intr enables");
689 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
690 &iflib_fast_intrs, 0, "# fast_intr calls");
691 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
692 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
693 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
694 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
695 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
696 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
697 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
698 &iflib_rx_if_input, 0, "# times rxeof called if_input");
699 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
700 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
701 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
702 &iflib_rxd_flush, 0, "# times rxd_flush called");
703 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
704 &iflib_verbose_debug, 0, "enable verbose debugging");
706 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
708 iflib_debug_reset(void)
710 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
711 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
712 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
713 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
714 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
715 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
716 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
717 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
718 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
719 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
723 #define DBG_COUNTER_INC(name)
724 static void iflib_debug_reset(void) {}
727 #define IFLIB_DEBUG 0
729 static void iflib_tx_structures_free(if_ctx_t ctx);
730 static void iflib_rx_structures_free(if_ctx_t ctx);
731 static int iflib_queues_alloc(if_ctx_t ctx);
732 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
733 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
734 static int iflib_qset_structures_setup(if_ctx_t ctx);
735 static int iflib_msix_init(if_ctx_t ctx);
736 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
737 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
738 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
739 static int iflib_register(if_ctx_t);
740 static void iflib_init_locked(if_ctx_t ctx);
741 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
742 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
743 static void iflib_ifmp_purge(iflib_txq_t txq);
744 static void _iflib_pre_assert(if_softc_ctx_t scctx);
745 static void iflib_if_init_locked(if_ctx_t ctx);
746 #ifndef __NO_STRICT_ALIGNMENT
747 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
750 NETDUMP_DEFINE(iflib);
753 #include <sys/selinfo.h>
754 #include <net/netmap.h>
755 #include <dev/netmap/netmap_kern.h>
757 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
762 * device-specific sysctl variables:
764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
765 * During regular operations the CRC is stripped, but on some
766 * hardware reception of frames not multiple of 64 is slower,
767 * so using crcstrip=0 helps in benchmarks.
769 * iflib_rx_miss, iflib_rx_miss_bufs:
770 * count packets that might be missed due to lost interrupts.
772 SYSCTL_DECL(_dev_netmap);
774 * The xl driver by default strips CRCs and we do not override it.
777 int iflib_crcstrip = 1;
778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
781 int iflib_rx_miss, iflib_rx_miss_bufs;
782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
788 * Register/unregister. We are already under netmap lock.
789 * Only called on the first register or the last unregister.
792 iflib_netmap_register(struct netmap_adapter *na, int onoff)
794 struct ifnet *ifp = na->ifp;
795 if_ctx_t ctx = ifp->if_softc;
799 IFDI_INTR_DISABLE(ctx);
801 /* Tell the stack that the interface is no longer active */
802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
807 /* enable or disable flags and callbacks in na and ifp */
809 nm_set_native_flags(na);
811 nm_clear_native_flags(na);
814 iflib_init_locked(ctx);
815 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
816 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
818 nm_clear_native_flags(na);
824 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
826 struct netmap_adapter *na = kring->na;
827 u_int const lim = kring->nkr_num_slots - 1;
828 u_int head = kring->rhead;
829 struct netmap_ring *ring = kring->ring;
831 struct if_rxd_update iru;
832 if_ctx_t ctx = rxq->ifr_ctx;
833 iflib_fl_t fl = &rxq->ifr_fl[0];
834 uint32_t refill_pidx, nic_i;
836 if (nm_i == head && __predict_true(!init))
838 iru_init(&iru, rxq, 0 /* flid */);
839 map = fl->ifl_sds.ifsd_map;
840 refill_pidx = netmap_idx_k2n(kring, nm_i);
842 * IMPORTANT: we must leave one free slot in the ring,
843 * so move head back by one unit
845 head = nm_prev(head, lim);
847 while (nm_i != head) {
848 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
849 struct netmap_slot *slot = &ring->slot[nm_i];
850 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
851 uint32_t nic_i_dma = refill_pidx;
852 nic_i = netmap_idx_k2n(kring, nm_i);
854 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
856 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
857 return netmap_ring_reinit(kring);
859 fl->ifl_vm_addrs[tmp_pidx] = addr;
860 if (__predict_false(init) && map) {
861 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
862 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
863 /* buffer has changed, reload map */
864 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
866 slot->flags &= ~NS_BUF_CHANGED;
868 nm_i = nm_next(nm_i, lim);
869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
873 iru.iru_pidx = refill_pidx;
874 iru.iru_count = tmp_pidx+1;
875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
881 for (int n = 0; n < iru.iru_count; n++) {
882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
883 BUS_DMASYNC_PREREAD);
884 /* XXX - change this to not use the netmap func*/
885 nic_i_dma = nm_next(nic_i_dma, lim);
889 kring->nr_hwcur = head;
892 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
894 if (__predict_true(nic_i != UINT_MAX))
895 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
900 * Reconcile kernel and user view of the transmit ring.
902 * All information is in the kring.
903 * Userspace wants to send packets up to the one before kring->rhead,
904 * kernel knows kring->nr_hwcur is the first unsent packet.
906 * Here we push packets out (as many as possible), and possibly
907 * reclaim buffers from previously completed transmission.
909 * The caller (netmap) guarantees that there is only one instance
910 * running at any time. Any interference with other driver
911 * methods should be handled by the individual drivers.
914 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
916 struct netmap_adapter *na = kring->na;
917 struct ifnet *ifp = na->ifp;
918 struct netmap_ring *ring = kring->ring;
919 u_int nm_i; /* index into the netmap ring */
920 u_int nic_i; /* index into the NIC ring */
922 u_int const lim = kring->nkr_num_slots - 1;
923 u_int const head = kring->rhead;
924 struct if_pkt_info pi;
927 * interrupts on every tx packet are expensive so request
928 * them every half ring, or where NS_REPORT is set
930 u_int report_frequency = kring->nkr_num_slots >> 1;
931 /* device-specific */
932 if_ctx_t ctx = ifp->if_softc;
933 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
935 if (txq->ift_sds.ifsd_map)
936 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
937 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
941 * First part: process new packets to send.
942 * nm_i is the current index in the netmap ring,
943 * nic_i is the corresponding index in the NIC ring.
945 * If we have packets to send (nm_i != head)
946 * iterate over the netmap ring, fetch length and update
947 * the corresponding slot in the NIC ring. Some drivers also
948 * need to update the buffer's physical address in the NIC slot
949 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
951 * The netmap_reload_map() calls is especially expensive,
952 * even when (as in this case) the tag is 0, so do only
953 * when the buffer has actually changed.
955 * If possible do not set the report/intr bit on all slots,
956 * but only a few times per ring or when NS_REPORT is set.
958 * Finally, on 10G and faster drivers, it might be useful
959 * to prefetch the next slot and txr entry.
962 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
963 if (nm_i != head) { /* we have new packets to send */
965 pi.ipi_segs = txq->ift_segs;
966 pi.ipi_qsidx = kring->ring_id;
967 nic_i = netmap_idx_k2n(kring, nm_i);
969 __builtin_prefetch(&ring->slot[nm_i]);
970 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
971 if (txq->ift_sds.ifsd_map)
972 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
974 for (n = 0; nm_i != head; n++) {
975 struct netmap_slot *slot = &ring->slot[nm_i];
976 u_int len = slot->len;
978 void *addr = PNMB(na, slot, &paddr);
979 int flags = (slot->flags & NS_REPORT ||
980 nic_i == 0 || nic_i == report_frequency) ?
983 /* device-specific */
985 pi.ipi_segs[0].ds_addr = paddr;
986 pi.ipi_segs[0].ds_len = len;
990 pi.ipi_flags = flags;
992 /* Fill the slot in the NIC ring. */
993 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
995 /* prefetch for next round */
996 __builtin_prefetch(&ring->slot[nm_i + 1]);
997 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
998 if (txq->ift_sds.ifsd_map) {
999 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1001 NM_CHECK_ADDR_LEN(na, addr, len);
1003 if (slot->flags & NS_BUF_CHANGED) {
1004 /* buffer has changed, reload map */
1005 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
1007 /* make sure changes to the buffer are synced */
1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1009 BUS_DMASYNC_PREWRITE);
1011 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1012 nm_i = nm_next(nm_i, lim);
1013 nic_i = nm_next(nic_i, lim);
1015 kring->nr_hwcur = head;
1017 /* synchronize the NIC ring */
1018 if (txq->ift_sds.ifsd_map)
1019 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1022 /* (re)start the tx unit up to slot nic_i (excluded) */
1023 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1027 * Second part: reclaim buffers for completed transmissions.
1029 * If there are unclaimed buffers, attempt to reclaim them.
1030 * If none are reclaimed, and TX IRQs are not in use, do an initial
1031 * minimal delay, then trigger the tx handler which will spin in the
1034 if (kring->nr_hwtail != nm_prev(head, lim)) {
1035 if (iflib_tx_credits_update(ctx, txq)) {
1036 /* some tx completed, increment avail */
1037 nic_i = txq->ift_cidx_processed;
1038 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1041 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1043 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txq->ift_id].ift_task);
1051 * Reconcile kernel and user view of the receive ring.
1052 * Same as for the txsync, this routine must be efficient.
1053 * The caller guarantees a single invocations, but races against
1054 * the rest of the driver should be handled here.
1056 * On call, kring->rhead is the first packet that userspace wants
1057 * to keep, and kring->rcur is the wakeup point.
1058 * The kernel has previously reported packets up to kring->rtail.
1060 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1061 * of whether or not we received an interrupt.
1064 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1066 struct netmap_adapter *na = kring->na;
1067 struct netmap_ring *ring = kring->ring;
1068 uint32_t nm_i; /* index into the netmap ring */
1069 uint32_t nic_i; /* index into the NIC ring */
1071 u_int const lim = kring->nkr_num_slots - 1;
1072 u_int const head = netmap_idx_n2k(kring, kring->rhead);
1073 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1074 struct if_rxd_info ri;
1076 struct ifnet *ifp = na->ifp;
1077 if_ctx_t ctx = ifp->if_softc;
1078 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1079 iflib_fl_t fl = rxq->ifr_fl;
1081 return netmap_ring_reinit(kring);
1083 /* XXX check sync modes */
1084 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1085 if (fl->ifl_sds.ifsd_map == NULL)
1087 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1088 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1091 * First part: import newly received packets.
1093 * nm_i is the index of the next free slot in the netmap ring,
1094 * nic_i is the index of the next received packet in the NIC ring,
1095 * and they may differ in case if_init() has been called while
1096 * in netmap mode. For the receive ring we have
1098 * nic_i = rxr->next_check;
1099 * nm_i = kring->nr_hwtail (previous)
1101 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1103 * rxr->next_check is set to 0 on a ring reinit
1105 if (netmap_no_pendintr || force_update) {
1106 int crclen = iflib_crcstrip ? 0 : 4;
1109 for (i = 0; i < rxq->ifr_nfl; i++) {
1110 fl = &rxq->ifr_fl[i];
1111 nic_i = fl->ifl_cidx;
1112 nm_i = netmap_idx_n2k(kring, nic_i);
1113 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1114 for (n = 0; avail > 0; n++, avail--) {
1116 ri.iri_frags = rxq->ifr_frags;
1117 ri.iri_qsidx = kring->ring_id;
1118 ri.iri_ifp = ctx->ifc_ifp;
1119 ri.iri_cidx = nic_i;
1121 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1122 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1123 ring->slot[nm_i].flags = 0;
1124 if (fl->ifl_sds.ifsd_map)
1125 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1126 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1127 nm_i = nm_next(nm_i, lim);
1128 nic_i = nm_next(nic_i, lim);
1130 if (n) { /* update the state variables */
1131 if (netmap_no_pendintr && !force_update) {
1134 iflib_rx_miss_bufs += n;
1136 fl->ifl_cidx = nic_i;
1137 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i);
1139 kring->nr_kflags &= ~NKR_PENDINTR;
1143 * Second part: skip past packets that userspace has released.
1144 * (kring->nr_hwcur to head excluded),
1145 * and make the buffers available for reception.
1146 * As usual nm_i is the index in the netmap ring,
1147 * nic_i is the index in the NIC ring, and
1148 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1150 /* XXX not sure how this will work with multiple free lists */
1151 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
1153 return (netmap_fl_refill(rxq, kring, nm_i, false));
1157 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1159 struct ifnet *ifp = na->ifp;
1160 if_ctx_t ctx = ifp->if_softc;
1164 IFDI_INTR_ENABLE(ctx);
1166 IFDI_INTR_DISABLE(ctx);
1173 iflib_netmap_attach(if_ctx_t ctx)
1175 struct netmap_adapter na;
1176 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1178 bzero(&na, sizeof(na));
1180 na.ifp = ctx->ifc_ifp;
1181 na.na_flags = NAF_BDG_MAYSLEEP;
1182 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1183 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1185 na.num_tx_desc = scctx->isc_ntxd[0];
1186 na.num_rx_desc = scctx->isc_nrxd[0];
1187 na.nm_txsync = iflib_netmap_txsync;
1188 na.nm_rxsync = iflib_netmap_rxsync;
1189 na.nm_register = iflib_netmap_register;
1190 na.nm_intr = iflib_netmap_intr;
1191 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1192 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1193 return (netmap_attach(&na));
1197 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1199 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1200 struct netmap_slot *slot;
1202 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1205 if (txq->ift_sds.ifsd_map == NULL)
1208 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1211 * In netmap mode, set the map for the packet buffer.
1212 * NOTE: Some drivers (not this one) also need to set
1213 * the physical buffer address in the NIC ring.
1214 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1215 * netmap slot index, si
1217 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1218 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1223 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1225 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1226 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1227 struct netmap_slot *slot;
1230 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1233 nm_i = netmap_idx_n2k(kring, 0);
1234 netmap_fl_refill(rxq, kring, nm_i, true);
1237 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1240 #define iflib_netmap_txq_init(ctx, txq)
1241 #define iflib_netmap_rxq_init(ctx, rxq)
1242 #define iflib_netmap_detach(ifp)
1244 #define iflib_netmap_attach(ctx) (0)
1245 #define netmap_rx_irq(ifp, qid, budget) (0)
1246 #define netmap_tx_irq(ifp, qid) do {} while (0)
1250 #if defined(__i386__) || defined(__amd64__)
1251 static __inline void
1254 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1256 static __inline void
1257 prefetch2cachelines(void *x)
1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1260 #if (CACHE_LINE_SIZE < 128)
1261 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1266 #define prefetch2cachelines(x)
1270 iflib_gen_mac(if_ctx_t ctx)
1274 char uuid[HOSTUUIDLEN+1];
1275 char buf[HOSTUUIDLEN+16];
1277 unsigned char digest[16];
1281 uuid[HOSTUUIDLEN] = 0;
1282 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1283 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1285 * Generate a pseudo-random, deterministic MAC
1286 * address based on the UUID and unit number.
1287 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1290 MD5Update(&mdctx, buf, strlen(buf));
1291 MD5Final(digest, &mdctx);
1302 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1306 fl = &rxq->ifr_fl[flid];
1307 iru->iru_paddrs = fl->ifl_bus_addrs;
1308 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1309 iru->iru_idxs = fl->ifl_rxd_idxs;
1310 iru->iru_qsidx = rxq->ifr_id;
1311 iru->iru_buf_size = fl->ifl_buf_size;
1312 iru->iru_flidx = fl->ifl_id;
1316 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1320 *(bus_addr_t *) arg = segs[0].ds_addr;
1324 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1327 if_shared_ctx_t sctx = ctx->ifc_sctx;
1328 device_t dev = ctx->ifc_dev;
1330 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1332 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1333 sctx->isc_q_align, 0, /* alignment, bounds */
1334 BUS_SPACE_MAXADDR, /* lowaddr */
1335 BUS_SPACE_MAXADDR, /* highaddr */
1336 NULL, NULL, /* filter, filterarg */
1339 size, /* maxsegsize */
1340 BUS_DMA_ALLOCNOW, /* flags */
1341 NULL, /* lockfunc */
1346 "%s: bus_dma_tag_create failed: %d\n",
1351 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1352 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1355 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1356 __func__, (uintmax_t)size, err);
1360 dma->idi_paddr = IF_BAD_DMA;
1361 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1362 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1363 if (err || dma->idi_paddr == IF_BAD_DMA) {
1365 "%s: bus_dmamap_load failed: %d\n",
1370 dma->idi_size = size;
1374 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1376 bus_dma_tag_destroy(dma->idi_tag);
1378 dma->idi_tag = NULL;
1384 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1387 iflib_dma_info_t *dmaiter;
1390 for (i = 0; i < count; i++, dmaiter++) {
1391 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1395 iflib_dma_free_multi(dmalist, i);
1400 iflib_dma_free(iflib_dma_info_t dma)
1402 if (dma->idi_tag == NULL)
1404 if (dma->idi_paddr != IF_BAD_DMA) {
1405 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1406 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1407 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1408 dma->idi_paddr = IF_BAD_DMA;
1410 if (dma->idi_vaddr != NULL) {
1411 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1412 dma->idi_vaddr = NULL;
1414 bus_dma_tag_destroy(dma->idi_tag);
1415 dma->idi_tag = NULL;
1419 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1422 iflib_dma_info_t *dmaiter = dmalist;
1424 for (i = 0; i < count; i++, dmaiter++)
1425 iflib_dma_free(*dmaiter);
1428 #ifdef EARLY_AP_STARTUP
1429 static const int iflib_started = 1;
1432 * We used to abuse the smp_started flag to decide if the queues have been
1433 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1434 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1435 * is set. Run a SYSINIT() strictly after that to just set a usable
1439 static int iflib_started;
1442 iflib_record_started(void *arg)
1447 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1448 iflib_record_started, NULL);
1452 iflib_fast_intr(void *arg)
1454 iflib_filter_info_t info = arg;
1455 struct grouptask *gtask = info->ifi_task;
1457 return (FILTER_HANDLED);
1459 DBG_COUNTER_INC(fast_intrs);
1460 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1461 return (FILTER_HANDLED);
1463 GROUPTASK_ENQUEUE(gtask);
1464 return (FILTER_HANDLED);
1468 iflib_fast_intr_rxtx(void *arg)
1470 iflib_filter_info_t info = arg;
1471 struct grouptask *gtask = info->ifi_task;
1472 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1473 if_ctx_t ctx = NULL;;
1477 return (FILTER_HANDLED);
1479 DBG_COUNTER_INC(fast_intrs);
1480 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1481 return (FILTER_HANDLED);
1483 MPASS(rxq->ifr_ntxqirq);
1484 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1485 qidx_t txqid = rxq->ifr_txqid[i];
1489 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1493 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1496 cidx = rxq->ifr_cq_cidx;
1498 cidx = rxq->ifr_fl[0].ifl_cidx;
1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1500 GROUPTASK_ENQUEUE(gtask);
1502 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1503 return (FILTER_HANDLED);
1508 iflib_fast_intr_ctx(void *arg)
1510 iflib_filter_info_t info = arg;
1511 struct grouptask *gtask = info->ifi_task;
1514 return (FILTER_HANDLED);
1516 DBG_COUNTER_INC(fast_intrs);
1517 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1518 return (FILTER_HANDLED);
1520 GROUPTASK_ENQUEUE(gtask);
1521 return (FILTER_HANDLED);
1525 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1526 driver_filter_t filter, driver_intr_t handler, void *arg,
1530 struct resource *res;
1532 device_t dev = ctx->ifc_dev;
1535 if (ctx->ifc_flags & IFC_LEGACY)
1536 flags |= RF_SHAREABLE;
1539 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1542 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1546 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1547 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1548 filter, handler, arg, &tag);
1551 "failed to setup interrupt for rid %d, name %s: %d\n",
1552 rid, name ? name : "unknown", rc);
1555 bus_describe_intr(dev, res, tag, "%s", name);
1562 /*********************************************************************
1564 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1565 * the information needed to transmit a packet on the wire. This is
1566 * called only once at attach, setup is done every reset.
1568 **********************************************************************/
1571 iflib_txsd_alloc(iflib_txq_t txq)
1573 if_ctx_t ctx = txq->ift_ctx;
1574 if_shared_ctx_t sctx = ctx->ifc_sctx;
1575 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1576 device_t dev = ctx->ifc_dev;
1577 int err, nsegments, ntsosegments;
1579 nsegments = scctx->isc_tx_nsegments;
1580 ntsosegments = scctx->isc_tx_tso_segments_max;
1581 MPASS(scctx->isc_ntxd[0] > 0);
1582 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1583 MPASS(nsegments > 0);
1584 MPASS(ntsosegments > 0);
1586 * Setup DMA descriptor areas.
1588 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1589 1, 0, /* alignment, bounds */
1590 BUS_SPACE_MAXADDR, /* lowaddr */
1591 BUS_SPACE_MAXADDR, /* highaddr */
1592 NULL, NULL, /* filter, filterarg */
1593 sctx->isc_tx_maxsize, /* maxsize */
1594 nsegments, /* nsegments */
1595 sctx->isc_tx_maxsegsize, /* maxsegsize */
1597 NULL, /* lockfunc */
1598 NULL, /* lockfuncarg */
1599 &txq->ift_desc_tag))) {
1600 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1601 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1602 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1605 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1606 1, 0, /* alignment, bounds */
1607 BUS_SPACE_MAXADDR, /* lowaddr */
1608 BUS_SPACE_MAXADDR, /* highaddr */
1609 NULL, NULL, /* filter, filterarg */
1610 scctx->isc_tx_tso_size_max, /* maxsize */
1611 ntsosegments, /* nsegments */
1612 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1614 NULL, /* lockfunc */
1615 NULL, /* lockfuncarg */
1616 &txq->ift_tso_desc_tag))) {
1617 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1621 if (!(txq->ift_sds.ifsd_flags =
1622 (uint8_t *) malloc(sizeof(uint8_t) *
1623 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1624 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1628 if (!(txq->ift_sds.ifsd_m =
1629 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1630 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1631 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1636 /* Create the descriptor buffer dma maps */
1637 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1638 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1641 if (!(txq->ift_sds.ifsd_map =
1642 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1643 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1648 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1649 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1651 device_printf(dev, "Unable to create TX DMA map\n");
1658 /* We free all, it handles case where we are in the middle */
1659 iflib_tx_structures_free(ctx);
1664 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1669 if (txq->ift_sds.ifsd_map != NULL)
1670 map = txq->ift_sds.ifsd_map[i];
1672 bus_dmamap_unload(txq->ift_desc_tag, map);
1673 bus_dmamap_destroy(txq->ift_desc_tag, map);
1674 txq->ift_sds.ifsd_map[i] = NULL;
1679 iflib_txq_destroy(iflib_txq_t txq)
1681 if_ctx_t ctx = txq->ift_ctx;
1683 for (int i = 0; i < txq->ift_size; i++)
1684 iflib_txsd_destroy(ctx, txq, i);
1685 if (txq->ift_sds.ifsd_map != NULL) {
1686 free(txq->ift_sds.ifsd_map, M_IFLIB);
1687 txq->ift_sds.ifsd_map = NULL;
1689 if (txq->ift_sds.ifsd_m != NULL) {
1690 free(txq->ift_sds.ifsd_m, M_IFLIB);
1691 txq->ift_sds.ifsd_m = NULL;
1693 if (txq->ift_sds.ifsd_flags != NULL) {
1694 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1695 txq->ift_sds.ifsd_flags = NULL;
1697 if (txq->ift_desc_tag != NULL) {
1698 bus_dma_tag_destroy(txq->ift_desc_tag);
1699 txq->ift_desc_tag = NULL;
1701 if (txq->ift_tso_desc_tag != NULL) {
1702 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1703 txq->ift_tso_desc_tag = NULL;
1708 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1712 mp = &txq->ift_sds.ifsd_m[i];
1716 if (txq->ift_sds.ifsd_map != NULL) {
1717 bus_dmamap_sync(txq->ift_desc_tag,
1718 txq->ift_sds.ifsd_map[i],
1719 BUS_DMASYNC_POSTWRITE);
1720 bus_dmamap_unload(txq->ift_desc_tag,
1721 txq->ift_sds.ifsd_map[i]);
1724 DBG_COUNTER_INC(tx_frees);
1729 iflib_txq_setup(iflib_txq_t txq)
1731 if_ctx_t ctx = txq->ift_ctx;
1732 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1733 iflib_dma_info_t di;
1736 /* Set number of descriptors available */
1737 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1738 /* XXX make configurable */
1739 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1742 txq->ift_cidx_processed = 0;
1743 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1744 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1746 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1747 bzero((void *)di->idi_vaddr, di->idi_size);
1749 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1750 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1751 bus_dmamap_sync(di->idi_tag, di->idi_map,
1752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1756 /*********************************************************************
1758 * Allocate memory for rx_buffer structures. Since we use one
1759 * rx_buffer per received packet, the maximum number of rx_buffer's
1760 * that we'll need is equal to the number of receive descriptors
1761 * that we've allocated.
1763 **********************************************************************/
1765 iflib_rxsd_alloc(iflib_rxq_t rxq)
1767 if_ctx_t ctx = rxq->ifr_ctx;
1768 if_shared_ctx_t sctx = ctx->ifc_sctx;
1769 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1770 device_t dev = ctx->ifc_dev;
1774 MPASS(scctx->isc_nrxd[0] > 0);
1775 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1778 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1779 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1780 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1781 1, 0, /* alignment, bounds */
1782 BUS_SPACE_MAXADDR, /* lowaddr */
1783 BUS_SPACE_MAXADDR, /* highaddr */
1784 NULL, NULL, /* filter, filterarg */
1785 sctx->isc_rx_maxsize, /* maxsize */
1786 sctx->isc_rx_nsegments, /* nsegments */
1787 sctx->isc_rx_maxsegsize, /* maxsegsize */
1789 NULL, /* lockfunc */
1793 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1797 if (!(fl->ifl_sds.ifsd_flags =
1798 (uint8_t *) malloc(sizeof(uint8_t) *
1799 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1800 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1804 if (!(fl->ifl_sds.ifsd_m =
1805 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1806 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1807 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1811 if (!(fl->ifl_sds.ifsd_cl =
1812 (caddr_t *) malloc(sizeof(caddr_t) *
1813 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1814 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1819 /* Create the descriptor buffer dma maps */
1820 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1821 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1824 if (!(fl->ifl_sds.ifsd_map =
1825 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1826 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1831 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1832 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1834 device_printf(dev, "Unable to create RX buffer DMA map\n");
1843 iflib_rx_structures_free(ctx);
1849 * Internal service routines
1852 struct rxq_refill_cb_arg {
1854 bus_dma_segment_t seg;
1859 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1861 struct rxq_refill_cb_arg *cb_arg = arg;
1863 cb_arg->error = error;
1864 cb_arg->seg = segs[0];
1865 cb_arg->nseg = nseg;
1870 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1872 #define IS_DMAR(ctx) (0)
1876 * rxq_refill - refill an rxq free-buffer list
1877 * @ctx: the iflib context
1878 * @rxq: the free-list to refill
1879 * @n: the number of new buffers to allocate
1881 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1882 * The caller must assure that @n does not exceed the queue's capacity.
1885 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1888 int idx, frag_idx = fl->ifl_fragidx;
1889 int pidx = fl->ifl_pidx;
1893 struct if_rxd_update iru;
1894 bus_dmamap_t *sd_map;
1900 sd_m = fl->ifl_sds.ifsd_m;
1901 sd_map = fl->ifl_sds.ifsd_map;
1902 sd_cl = fl->ifl_sds.ifsd_cl;
1903 sd_flags = fl->ifl_sds.ifsd_flags;
1905 credits = fl->ifl_credits;
1909 MPASS(credits + n <= fl->ifl_size);
1911 if (pidx < fl->ifl_cidx)
1912 MPASS(pidx + n <= fl->ifl_cidx);
1913 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1914 MPASS(fl->ifl_gen == 0);
1915 if (pidx > fl->ifl_cidx)
1916 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1918 DBG_COUNTER_INC(fl_refills);
1920 DBG_COUNTER_INC(fl_refills_large);
1921 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1924 * We allocate an uninitialized mbuf + cluster, mbuf is
1925 * initialized after rx.
1927 * If the cluster is still set then we know a minimum sized packet was received
1929 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1930 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1931 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1932 if ((cl = sd_cl[frag_idx]) == NULL) {
1933 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1936 fl->ifl_cl_enqueued++;
1939 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1943 fl->ifl_m_enqueued++;
1946 DBG_COUNTER_INC(rx_allocs);
1947 #if defined(__i386__) || defined(__amd64__)
1948 if (!IS_DMAR(ctx)) {
1949 bus_addr = pmap_kextract((vm_offset_t)cl);
1953 struct rxq_refill_cb_arg cb_arg;
1956 MPASS(sd_map != NULL);
1957 MPASS(sd_map[frag_idx] != NULL);
1958 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1959 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1960 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1961 BUS_DMASYNC_PREREAD);
1963 if (err != 0 || cb_arg.error) {
1967 if (fl->ifl_zone == zone_pack)
1968 uma_zfree(fl->ifl_zone, cl);
1973 bus_addr = cb_arg.seg.ds_addr;
1975 bit_set(fl->ifl_rx_bitmap, frag_idx);
1976 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1978 MPASS(sd_m[frag_idx] == NULL);
1979 sd_cl[frag_idx] = cl;
1981 fl->ifl_rxd_idxs[i] = frag_idx;
1982 fl->ifl_bus_addrs[i] = bus_addr;
1983 fl->ifl_vm_addrs[i] = cl;
1986 MPASS(credits <= fl->ifl_size);
1987 if (++idx == fl->ifl_size) {
1991 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1992 iru.iru_pidx = pidx;
1994 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1998 fl->ifl_credits = credits;
2004 iru.iru_pidx = pidx;
2006 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2008 fl->ifl_credits = credits;
2010 DBG_COUNTER_INC(rxd_flush);
2011 if (fl->ifl_pidx == 0)
2012 pidx = fl->ifl_size - 1;
2014 pidx = fl->ifl_pidx - 1;
2017 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2019 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2020 fl->ifl_fragidx = frag_idx;
2023 static __inline void
2024 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2026 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2027 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2029 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2032 MPASS(fl->ifl_credits <= fl->ifl_size);
2033 MPASS(reclaimable == delta);
2035 if (reclaimable > 0)
2036 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2040 iflib_fl_bufs_free(iflib_fl_t fl)
2042 iflib_dma_info_t idi = fl->ifl_ifdi;
2045 for (i = 0; i < fl->ifl_size; i++) {
2046 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2047 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
2048 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2050 if (*sd_flags & RX_SW_DESC_INUSE) {
2051 if (fl->ifl_sds.ifsd_map != NULL) {
2052 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
2053 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2054 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
2055 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2057 if (*sd_m != NULL) {
2058 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2059 uma_zfree(zone_mbuf, *sd_m);
2062 uma_zfree(fl->ifl_zone, *sd_cl);
2065 MPASS(*sd_cl == NULL);
2066 MPASS(*sd_m == NULL);
2069 fl->ifl_m_dequeued++;
2070 fl->ifl_cl_dequeued++;
2076 for (i = 0; i < fl->ifl_size; i++) {
2077 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2078 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2079 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2083 * Reset free list values
2085 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2086 bzero(idi->idi_vaddr, idi->idi_size);
2089 /*********************************************************************
2091 * Initialize a receive ring and its buffers.
2093 **********************************************************************/
2095 iflib_fl_setup(iflib_fl_t fl)
2097 iflib_rxq_t rxq = fl->ifl_rxq;
2098 if_ctx_t ctx = rxq->ifr_ctx;
2099 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2101 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2103 ** Free current RX buffer structs and their mbufs
2105 iflib_fl_bufs_free(fl);
2106 /* Now replenish the mbufs */
2107 MPASS(fl->ifl_credits == 0);
2109 * XXX don't set the max_frame_size to larger
2110 * than the hardware can handle
2112 if (sctx->isc_max_frame_size <= 2048)
2113 fl->ifl_buf_size = MCLBYTES;
2114 #ifndef CONTIGMALLOC_WORKS
2116 fl->ifl_buf_size = MJUMPAGESIZE;
2118 else if (sctx->isc_max_frame_size <= 4096)
2119 fl->ifl_buf_size = MJUMPAGESIZE;
2120 else if (sctx->isc_max_frame_size <= 9216)
2121 fl->ifl_buf_size = MJUM9BYTES;
2123 fl->ifl_buf_size = MJUM16BYTES;
2125 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2126 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2127 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2128 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2131 /* avoid pre-allocating zillions of clusters to an idle card
2132 * potentially speeding up attach
2134 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2135 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2136 if (min(128, fl->ifl_size) != fl->ifl_credits)
2142 MPASS(fl->ifl_ifdi != NULL);
2143 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2144 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2148 /*********************************************************************
2150 * Free receive ring data structures
2152 **********************************************************************/
2154 iflib_rx_sds_free(iflib_rxq_t rxq)
2159 if (rxq->ifr_fl != NULL) {
2160 for (i = 0; i < rxq->ifr_nfl; i++) {
2161 fl = &rxq->ifr_fl[i];
2162 if (fl->ifl_desc_tag != NULL) {
2163 bus_dma_tag_destroy(fl->ifl_desc_tag);
2164 fl->ifl_desc_tag = NULL;
2166 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2167 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2168 /* XXX destroy maps first */
2169 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2170 fl->ifl_sds.ifsd_m = NULL;
2171 fl->ifl_sds.ifsd_cl = NULL;
2172 fl->ifl_sds.ifsd_map = NULL;
2174 free(rxq->ifr_fl, M_IFLIB);
2176 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2181 * MI independent logic
2185 iflib_timer(void *arg)
2187 iflib_txq_t txq = arg;
2188 if_ctx_t ctx = txq->ift_ctx;
2189 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2191 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2194 ** Check on the state of the TX queue(s), this
2195 ** can be done without the lock because its RO
2196 ** and the HUNG state will be static if set.
2198 IFDI_TIMER(ctx, txq->ift_id);
2199 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2200 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2201 (sctx->isc_pause_frames == 0)))
2204 if (ifmp_ring_is_stalled(txq->ift_br))
2205 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2206 txq->ift_cleaned_prev = txq->ift_cleaned;
2207 /* handle any laggards */
2208 if (txq->ift_db_pending)
2209 GROUPTASK_ENQUEUE(&txq->ift_task);
2211 sctx->isc_pause_frames = 0;
2212 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2213 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2216 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2217 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2219 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2220 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2221 iflib_admin_intr_deferred(ctx);
2226 iflib_init_locked(if_ctx_t ctx)
2228 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2229 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2230 if_t ifp = ctx->ifc_ifp;
2234 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2237 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2238 IFDI_INTR_DISABLE(ctx);
2240 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2241 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2242 /* Set hardware offload abilities */
2243 if_clearhwassist(ifp);
2244 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2245 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2246 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2247 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2248 if (if_getcapenable(ifp) & IFCAP_TSO4)
2249 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2250 if (if_getcapenable(ifp) & IFCAP_TSO6)
2251 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2253 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2255 callout_stop(&txq->ift_timer);
2256 CALLOUT_UNLOCK(txq);
2257 iflib_netmap_txq_init(ctx, txq);
2260 i = if_getdrvflags(ifp);
2263 MPASS(if_getdrvflags(ifp) == i);
2264 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2265 /* XXX this should really be done on a per-queue basis */
2266 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2267 MPASS(rxq->ifr_id == i);
2268 iflib_netmap_rxq_init(ctx, rxq);
2271 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2272 if (iflib_fl_setup(fl)) {
2273 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2280 IFDI_INTR_ENABLE(ctx);
2281 txq = ctx->ifc_txqs;
2282 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2283 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2284 txq->ift_timer.c_cpu);
2288 iflib_media_change(if_t ifp)
2290 if_ctx_t ctx = if_getsoftc(ifp);
2294 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2295 iflib_init_locked(ctx);
2301 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2303 if_ctx_t ctx = if_getsoftc(ifp);
2306 IFDI_UPDATE_ADMIN_STATUS(ctx);
2307 IFDI_MEDIA_STATUS(ctx, ifmr);
2312 iflib_stop(if_ctx_t ctx)
2314 iflib_txq_t txq = ctx->ifc_txqs;
2315 iflib_rxq_t rxq = ctx->ifc_rxqs;
2316 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2317 iflib_dma_info_t di;
2321 /* Tell the stack that the interface is no longer active */
2322 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2324 IFDI_INTR_DISABLE(ctx);
2329 iflib_debug_reset();
2330 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2331 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2332 /* make sure all transmitters have completed before proceeding XXX */
2335 callout_stop(&txq->ift_timer);
2336 CALLOUT_UNLOCK(txq);
2338 /* clean any enqueued buffers */
2339 iflib_ifmp_purge(txq);
2340 /* Free any existing tx buffers. */
2341 for (j = 0; j < txq->ift_size; j++) {
2342 iflib_txsd_free(ctx, txq, j);
2344 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2345 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2346 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2347 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2348 txq->ift_pullups = 0;
2349 ifmp_ring_reset_stats(txq->ift_br);
2350 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2351 bzero((void *)di->idi_vaddr, di->idi_size);
2353 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2354 /* make sure all transmitters have completed before proceeding XXX */
2356 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++)
2357 bzero((void *)di->idi_vaddr, di->idi_size);
2358 /* also resets the free lists pidx/cidx */
2359 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2360 iflib_fl_bufs_free(fl);
2364 static inline caddr_t
2365 calc_next_rxd(iflib_fl_t fl, int cidx)
2369 caddr_t start, end, cur, next;
2371 nrxd = fl->ifl_size;
2372 size = fl->ifl_rxd_size;
2373 start = fl->ifl_ifdi->idi_vaddr;
2375 if (__predict_false(size == 0))
2377 cur = start + size*cidx;
2378 end = start + size*nrxd;
2379 next = CACHE_PTR_NEXT(cur);
2380 return (next < end ? next : start);
2384 prefetch_pkts(iflib_fl_t fl, int cidx)
2387 int nrxd = fl->ifl_size;
2391 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2392 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2393 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2394 next_rxd = calc_next_rxd(fl, cidx);
2396 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2397 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2398 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2399 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2400 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2401 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2402 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2403 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2407 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2412 iflib_dma_info_t di;
2416 flid = irf->irf_flid;
2417 cidx = irf->irf_idx;
2418 fl = &rxq->ifr_fl[flid];
2420 sd->ifsd_cidx = cidx;
2421 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2422 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2425 fl->ifl_m_dequeued++;
2427 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2428 prefetch_pkts(fl, cidx);
2429 if (fl->ifl_sds.ifsd_map != NULL) {
2430 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2431 prefetch(&fl->ifl_sds.ifsd_map[next]);
2432 map = fl->ifl_sds.ifsd_map[cidx];
2434 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2435 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2436 bus_dmamap_sync(di->idi_tag, di->idi_map,
2437 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2439 /* not valid assert if bxe really does SGE from non-contiguous elements */
2440 MPASS(fl->ifl_cidx == cidx);
2442 bus_dmamap_unload(fl->ifl_desc_tag, map);
2444 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2445 if (__predict_false(fl->ifl_cidx == 0))
2448 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2449 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2450 bit_clear(fl->ifl_rx_bitmap, cidx);
2453 static struct mbuf *
2454 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2456 int i, padlen , flags;
2457 struct mbuf *m, *mh, *mt;
2463 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2465 MPASS(*sd->ifsd_cl != NULL);
2466 MPASS(*sd->ifsd_m != NULL);
2468 /* Don't include zero-length frags */
2469 if (ri->iri_frags[i].irf_len == 0) {
2470 /* XXX we can save the cluster here, but not the mbuf */
2471 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2472 m_free(*sd->ifsd_m);
2479 flags = M_PKTHDR|M_EXT;
2481 padlen = ri->iri_pad;
2486 /* assuming padding is only on the first fragment */
2490 *sd->ifsd_cl = NULL;
2492 /* Can these two be made one ? */
2493 m_init(m, M_NOWAIT, MT_DATA, flags);
2494 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2496 * These must follow m_init and m_cljset
2498 m->m_data += padlen;
2499 ri->iri_len -= padlen;
2500 m->m_len = ri->iri_frags[i].irf_len;
2501 } while (++i < ri->iri_nfrags);
2507 * Process one software descriptor
2509 static struct mbuf *
2510 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2515 /* should I merge this back in now that the two paths are basically duplicated? */
2516 if (ri->iri_nfrags == 1 &&
2517 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2518 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2521 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2522 #ifndef __NO_STRICT_ALIGNMENT
2526 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2527 m->m_len = ri->iri_frags[0].irf_len;
2529 m = assemble_segments(rxq, ri, &sd);
2531 m->m_pkthdr.len = ri->iri_len;
2532 m->m_pkthdr.rcvif = ri->iri_ifp;
2533 m->m_flags |= ri->iri_flags;
2534 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2535 m->m_pkthdr.flowid = ri->iri_flowid;
2536 M_HASHTYPE_SET(m, ri->iri_rsstype);
2537 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2538 m->m_pkthdr.csum_data = ri->iri_csum_data;
2542 #if defined(INET6) || defined(INET)
2544 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2546 CURVNET_SET(lc->ifp->if_vnet);
2548 *v6 = VNET(ip6_forwarding);
2551 *v4 = VNET(ipforwarding);
2557 * Returns true if it's possible this packet could be LROed.
2558 * if it returns false, it is guaranteed that tcp_lro_rx()
2559 * would not return zero.
2562 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2564 struct ether_header *eh;
2567 eh = mtod(m, struct ether_header *);
2568 eh_type = ntohs(eh->ether_type);
2571 case ETHERTYPE_IPV6:
2572 return !v6_forwarding;
2576 return !v4_forwarding;
2584 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2590 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2592 if_ctx_t ctx = rxq->ifr_ctx;
2593 if_shared_ctx_t sctx = ctx->ifc_sctx;
2594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2597 struct if_rxd_info ri;
2598 int err, budget_left, rx_bytes, rx_pkts;
2602 bool v4_forwarding, v6_forwarding, lro_possible;
2605 * XXX early demux data packets so that if_input processing only handles
2606 * acks in interrupt context
2608 struct mbuf *m, *mh, *mt, *mf;
2610 lro_possible = v4_forwarding = v6_forwarding = false;
2614 rx_pkts = rx_bytes = 0;
2615 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2616 cidxp = &rxq->ifr_cq_cidx;
2618 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2619 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2620 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2621 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2622 DBG_COUNTER_INC(rx_unavail);
2626 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2627 if (__predict_false(!CTX_ACTIVE(ctx))) {
2628 DBG_COUNTER_INC(rx_ctx_inactive);
2632 * Reset client set fields to their default values
2635 ri.iri_qsidx = rxq->ifr_id;
2636 ri.iri_cidx = *cidxp;
2638 ri.iri_frags = rxq->ifr_frags;
2639 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2643 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2644 *cidxp = ri.iri_cidx;
2645 /* Update our consumer index */
2646 /* XXX NB: shurd - check if this is still safe */
2647 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2648 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2649 rxq->ifr_cq_gen = 0;
2651 /* was this only a completion queue message? */
2652 if (__predict_false(ri.iri_nfrags == 0))
2655 MPASS(ri.iri_nfrags != 0);
2656 MPASS(ri.iri_len != 0);
2658 /* will advance the cidx on the corresponding free lists */
2659 m = iflib_rxd_pkt_get(rxq, &ri);
2660 if (avail == 0 && budget_left)
2661 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2663 if (__predict_false(m == NULL)) {
2664 DBG_COUNTER_INC(rx_mbuf_null);
2667 /* imm_pkt: -- cxgb */
2675 /* make sure that we can refill faster than drain */
2676 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2677 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2679 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2681 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2683 while (mh != NULL) {
2686 m->m_nextpkt = NULL;
2687 #ifndef __NO_STRICT_ALIGNMENT
2688 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2691 rx_bytes += m->m_pkthdr.len;
2693 #if defined(INET6) || defined(INET)
2695 if (!lro_possible) {
2696 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2697 if (lro_possible && mf != NULL) {
2698 ifp->if_input(ifp, mf);
2699 DBG_COUNTER_INC(rx_if_input);
2703 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2704 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2705 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2711 ifp->if_input(ifp, m);
2712 DBG_COUNTER_INC(rx_if_input);
2723 ifp->if_input(ifp, mf);
2724 DBG_COUNTER_INC(rx_if_input);
2727 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2728 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2731 * Flush any outstanding LRO work
2733 #if defined(INET6) || defined(INET)
2734 tcp_lro_flush_all(&rxq->ifr_lc);
2738 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2741 ctx->ifc_flags |= IFC_DO_RESET;
2742 iflib_admin_intr_deferred(ctx);
2747 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2748 static inline qidx_t
2749 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2751 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2752 qidx_t minthresh = txq->ift_size / 8;
2753 if (in_use > 4*minthresh)
2754 return (notify_count);
2755 if (in_use > 2*minthresh)
2756 return (notify_count >> 1);
2757 if (in_use > minthresh)
2758 return (notify_count >> 3);
2762 static inline qidx_t
2763 txq_max_rs_deferred(iflib_txq_t txq)
2765 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2766 qidx_t minthresh = txq->ift_size / 8;
2767 if (txq->ift_in_use > 4*minthresh)
2768 return (notify_count);
2769 if (txq->ift_in_use > 2*minthresh)
2770 return (notify_count >> 1);
2771 if (txq->ift_in_use > minthresh)
2772 return (notify_count >> 2);
2776 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2777 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2779 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2780 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2781 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2783 /* forward compatibility for cxgb */
2784 #define FIRST_QSET(ctx) 0
2785 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2786 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2787 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2788 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2790 /* XXX we should be setting this to something other than zero */
2791 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2792 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2795 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2801 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2802 if (ring || txq->ift_db_pending >= max) {
2803 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2804 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2805 txq->ift_db_pending = txq->ift_npending = 0;
2813 print_pkt(if_pkt_info_t pi)
2815 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2816 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2817 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2818 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2819 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2820 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2824 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2825 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2826 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2827 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2830 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2832 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2833 struct ether_vlan_header *eh;
2837 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2838 M_WRITABLE(m) == 0) {
2839 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2848 * Determine where frame payload starts.
2849 * Jump over vlan headers if already present,
2850 * helpful for QinQ too.
2852 if (__predict_false(m->m_len < sizeof(*eh))) {
2854 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2857 eh = mtod(m, struct ether_vlan_header *);
2858 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2859 pi->ipi_etype = ntohs(eh->evl_proto);
2860 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2862 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2863 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2866 switch (pi->ipi_etype) {
2870 struct ip *ip = NULL;
2871 struct tcphdr *th = NULL;
2874 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2875 if (__predict_false(m->m_len < minthlen)) {
2877 * if this code bloat is causing too much of a hit
2878 * move it to a separate function and mark it noinline
2880 if (m->m_len == pi->ipi_ehdrlen) {
2883 if (n->m_len >= sizeof(*ip)) {
2884 ip = (struct ip *)n->m_data;
2885 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2886 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2889 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2891 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2895 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2897 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2898 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2899 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2902 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2903 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2904 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2906 pi->ipi_ip_hlen = ip->ip_hl << 2;
2907 pi->ipi_ipproto = ip->ip_p;
2908 pi->ipi_flags |= IPI_TX_IPV4;
2910 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2913 /* TCP checksum offload may require TCP header length */
2914 if (IS_TX_OFFLOAD4(pi)) {
2915 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2916 if (__predict_false(th == NULL)) {
2918 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2920 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2922 pi->ipi_tcp_hflags = th->th_flags;
2923 pi->ipi_tcp_hlen = th->th_off << 2;
2924 pi->ipi_tcp_seq = th->th_seq;
2927 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2929 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2930 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2931 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2932 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2934 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2942 case ETHERTYPE_IPV6:
2944 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2946 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2948 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2949 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2952 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2954 /* XXX-BZ this will go badly in case of ext hdrs. */
2955 pi->ipi_ipproto = ip6->ip6_nxt;
2956 pi->ipi_flags |= IPI_TX_IPV6;
2958 /* TCP checksum offload may require TCP header length */
2959 if (IS_TX_OFFLOAD6(pi)) {
2960 if (pi->ipi_ipproto == IPPROTO_TCP) {
2961 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2963 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2966 pi->ipi_tcp_hflags = th->th_flags;
2967 pi->ipi_tcp_hlen = th->th_off << 2;
2968 pi->ipi_tcp_seq = th->th_seq;
2971 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2974 * The corresponding flag is set by the stack in the IPv4
2975 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2976 * So, set it here because the rest of the flow requires it.
2978 pi->ipi_csum_flags |= CSUM_IP6_TCP;
2979 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2980 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2987 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2988 pi->ipi_ip_hlen = 0;
2996 static __noinline struct mbuf *
2997 collapse_pkthdr(struct mbuf *m0)
2999 struct mbuf *m, *m_next, *tmp;
3003 while (m_next != NULL && m_next->m_len == 0) {
3007 m_next = m_next->m_next;
3011 if ((m_next->m_flags & M_EXT) == 0) {
3012 m = m_defrag(m, M_NOWAIT);
3014 tmp = m_next->m_next;
3015 memcpy(m_next, m, MPKTHSIZE);
3023 * If dodgy hardware rejects the scatter gather chain we've handed it
3024 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3027 static __noinline struct mbuf *
3028 iflib_remove_mbuf(iflib_txq_t txq)
3031 struct mbuf *m, *mh, **ifsd_m;
3033 pidx = txq->ift_pidx;
3034 ifsd_m = txq->ift_sds.ifsd_m;
3035 ntxd = txq->ift_size;
3036 mh = m = ifsd_m[pidx];
3037 ifsd_m[pidx] = NULL;
3039 txq->ift_dequeued++;
3044 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
3046 txq->ift_dequeued++;
3055 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
3056 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
3057 int max_segs, int flags)
3060 if_shared_ctx_t sctx;
3061 if_softc_ctx_t scctx;
3062 int i, next, pidx, err, ntxd, count;
3063 struct mbuf *m, *tmp, **ifsd_m;
3068 * Please don't ever do this
3070 if (__predict_false(m->m_len == 0))
3071 *m0 = m = collapse_pkthdr(m);
3074 sctx = ctx->ifc_sctx;
3075 scctx = &ctx->ifc_softc_ctx;
3076 ifsd_m = txq->ift_sds.ifsd_m;
3077 ntxd = txq->ift_size;
3078 pidx = txq->ift_pidx;
3080 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3082 err = bus_dmamap_load_mbuf_sg(tag, map,
3083 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3086 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3090 if (__predict_false(m->m_len <= 0)) {
3099 } while (m != NULL);
3100 if (count > *nsegs) {
3102 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3108 next = (pidx + count) & (ntxd-1);
3109 MPASS(ifsd_m[next] == NULL);
3114 } while (m != NULL);
3116 int buflen, sgsize, maxsegsz, max_sgsize;
3122 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3123 maxsegsz = scctx->isc_tx_tso_segsize_max;
3125 maxsegsz = sctx->isc_tx_maxsegsize;
3128 if (__predict_false(m->m_len <= 0)) {
3136 vaddr = (vm_offset_t)m->m_data;
3138 * see if we can't be smarter about physically
3139 * contiguous mappings
3141 next = (pidx + count) & (ntxd-1);
3142 MPASS(ifsd_m[next] == NULL);
3144 txq->ift_enqueued++;
3147 while (buflen > 0) {
3150 max_sgsize = MIN(buflen, maxsegsz);
3151 curaddr = pmap_kextract(vaddr);
3152 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3153 sgsize = MIN(sgsize, max_sgsize);
3154 segs[i].ds_addr = curaddr;
3155 segs[i].ds_len = sgsize;
3163 } while (m != NULL);
3168 *m0 = iflib_remove_mbuf(txq);
3172 static inline caddr_t
3173 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3177 caddr_t start, end, cur, next;
3179 ntxd = txq->ift_size;
3180 size = txq->ift_txd_size[qid];
3181 start = txq->ift_ifdi[qid].idi_vaddr;
3183 if (__predict_false(size == 0))
3185 cur = start + size*cidx;
3186 end = start + size*ntxd;
3187 next = CACHE_PTR_NEXT(cur);
3188 return (next < end ? next : start);
3192 * Pad an mbuf to ensure a minimum ethernet frame size.
3193 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3195 static __noinline int
3196 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3199 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3200 * and ARP message is the smallest common payload I can think of
3202 static char pad[18]; /* just zeros */
3204 struct mbuf *new_head;
3206 if (!M_WRITABLE(*m_head)) {
3207 new_head = m_dup(*m_head, M_NOWAIT);
3208 if (new_head == NULL) {
3210 device_printf(dev, "cannot pad short frame, m_dup() failed");
3211 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3218 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3219 n > 0; n -= sizeof(pad))
3220 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3225 device_printf(dev, "cannot pad short frame\n");
3226 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3234 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3237 if_shared_ctx_t sctx;
3238 if_softc_ctx_t scctx;
3239 bus_dma_segment_t *segs;
3240 struct mbuf *m_head;
3243 struct if_pkt_info pi;
3245 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3246 bus_dma_tag_t desc_tag;
3248 segs = txq->ift_segs;
3250 sctx = ctx->ifc_sctx;
3251 scctx = &ctx->ifc_softc_ctx;
3252 segs = txq->ift_segs;
3253 ntxd = txq->ift_size;
3258 * If we're doing TSO the next descriptor to clean may be quite far ahead
3260 cidx = txq->ift_cidx;
3261 pidx = txq->ift_pidx;
3262 if (ctx->ifc_flags & IFC_PREFETCH) {
3263 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3264 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3265 next_txd = calc_next_txd(txq, cidx, 0);
3269 /* prefetch the next cache line of mbuf pointers and flags */
3270 prefetch(&txq->ift_sds.ifsd_m[next]);
3271 if (txq->ift_sds.ifsd_map != NULL) {
3272 prefetch(&txq->ift_sds.ifsd_map[next]);
3273 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3274 prefetch(&txq->ift_sds.ifsd_flags[next]);
3276 } else if (txq->ift_sds.ifsd_map != NULL)
3277 map = txq->ift_sds.ifsd_map[pidx];
3279 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3280 desc_tag = txq->ift_tso_desc_tag;
3281 max_segs = scctx->isc_tx_tso_segments_max;
3283 desc_tag = txq->ift_desc_tag;
3284 max_segs = scctx->isc_tx_nsegments;
3286 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3287 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3288 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3295 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3297 pi.ipi_qsidx = txq->ift_id;
3298 pi.ipi_len = m_head->m_pkthdr.len;
3299 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3300 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3302 /* deliberate bitwise OR to make one condition */
3303 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3304 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3310 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3312 if (__predict_false(err)) {
3315 /* try collapse once and defrag once */
3317 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3318 /* try defrag if collapsing fails */
3323 m_head = m_defrag(*m_headp, M_NOWAIT);
3325 if (__predict_false(m_head == NULL))
3327 txq->ift_mbuf_defrag++;
3332 txq->ift_no_tx_dma_setup++;
3335 txq->ift_no_tx_dma_setup++;
3337 DBG_COUNTER_INC(tx_frees);
3341 txq->ift_map_failed++;
3342 DBG_COUNTER_INC(encap_load_mbuf_fail);
3347 * XXX assumes a 1 to 1 relationship between segments and
3348 * descriptors - this does not hold true on all drivers, e.g.
3351 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3352 txq->ift_no_desc_avail++;
3354 bus_dmamap_unload(desc_tag, map);
3355 DBG_COUNTER_INC(encap_txq_avail_fail);
3356 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3357 GROUPTASK_ENQUEUE(&txq->ift_task);
3361 * On Intel cards we can greatly reduce the number of TX interrupts
3362 * we see by only setting report status on every Nth descriptor.
3363 * However, this also means that the driver will need to keep track
3364 * of the descriptors that RS was set on to check them for the DD bit.
3366 txq->ift_rs_pending += nsegs + 1;
3367 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3368 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3369 pi.ipi_flags |= IPI_TX_INTR;
3370 txq->ift_rs_pending = 0;
3374 pi.ipi_nsegs = nsegs;
3376 MPASS(pidx >= 0 && pidx < txq->ift_size);
3381 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3382 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3384 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3386 DBG_COUNTER_INC(tx_encap);
3387 MPASS(pi.ipi_new_pidx < txq->ift_size);
3389 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3390 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3391 ndesc += txq->ift_size;
3395 * drivers can need as many as
3398 MPASS(ndesc <= pi.ipi_nsegs + 2);
3399 MPASS(pi.ipi_new_pidx != pidx);
3401 txq->ift_in_use += ndesc;
3404 * We update the last software descriptor again here because there may
3405 * be a sentinel and/or there may be more mbufs than segments
3407 txq->ift_pidx = pi.ipi_new_pidx;
3408 txq->ift_npending += pi.ipi_ndescs;
3410 *m_headp = m_head = iflib_remove_mbuf(txq);
3412 txq->ift_txd_encap_efbig++;
3418 DBG_COUNTER_INC(encap_txd_encap_fail);
3424 txq->ift_mbuf_defrag_failed++;
3425 txq->ift_map_failed++;
3427 DBG_COUNTER_INC(tx_frees);
3433 iflib_tx_desc_free(iflib_txq_t txq, int n)
3436 uint32_t qsize, cidx, mask, gen;
3437 struct mbuf *m, **ifsd_m;
3438 uint8_t *ifsd_flags;
3439 bus_dmamap_t *ifsd_map;
3442 cidx = txq->ift_cidx;
3444 qsize = txq->ift_size;
3446 hasmap = txq->ift_sds.ifsd_map != NULL;
3447 ifsd_flags = txq->ift_sds.ifsd_flags;
3448 ifsd_m = txq->ift_sds.ifsd_m;
3449 ifsd_map = txq->ift_sds.ifsd_map;
3450 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3454 prefetch(ifsd_m[(cidx + 3) & mask]);
3455 prefetch(ifsd_m[(cidx + 4) & mask]);
3457 if (ifsd_m[cidx] != NULL) {
3458 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3459 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3460 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3462 * does it matter if it's not the TSO tag? If so we'll
3463 * have to add the type to flags
3465 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3466 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3468 if ((m = ifsd_m[cidx]) != NULL) {
3469 /* XXX we don't support any drivers that batch packets yet */
3470 MPASS(m->m_nextpkt == NULL);
3471 /* if the number of clusters exceeds the number of segments
3472 * there won't be space on the ring to save a pointer to each
3473 * cluster so we simply free the list here
3475 if (m->m_flags & M_TOOBIG) {
3480 ifsd_m[cidx] = NULL;
3482 txq->ift_dequeued++;
3484 DBG_COUNTER_INC(tx_frees);
3487 if (__predict_false(++cidx == qsize)) {
3492 txq->ift_cidx = cidx;
3497 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3500 if_ctx_t ctx = txq->ift_ctx;
3502 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3503 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3506 * Need a rate-limiting check so that this isn't called every time
3508 iflib_tx_credits_update(ctx, txq);
3509 reclaim = DESC_RECLAIMABLE(txq);
3511 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3513 if (iflib_verbose_debug) {
3514 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3515 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3522 iflib_tx_desc_free(txq, reclaim);
3523 txq->ift_cleaned += reclaim;
3524 txq->ift_in_use -= reclaim;
3529 static struct mbuf **
3530 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3533 struct mbuf **items;
3536 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3537 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3539 prefetch(items[(cidx + offset) & (size-1)]);
3540 if (remaining > 1) {
3541 prefetch2cachelines(&items[next]);
3542 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3543 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3544 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3546 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3550 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3553 ifmp_ring_check_drainage(txq->ift_br, budget);
3557 iflib_txq_can_drain(struct ifmp_ring *r)
3559 iflib_txq_t txq = r->cookie;
3560 if_ctx_t ctx = txq->ift_ctx;
3562 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3563 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3567 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3569 iflib_txq_t txq = r->cookie;
3570 if_ctx_t ctx = txq->ift_ctx;
3571 struct ifnet *ifp = ctx->ifc_ifp;
3572 struct mbuf **mp, *m;
3573 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3574 int reclaimed, err, in_use_prev, desc_used;
3575 bool do_prefetch, ring, rang;
3577 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3578 !LINK_ACTIVE(ctx))) {
3579 DBG_COUNTER_INC(txq_drain_notready);
3582 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3583 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3584 avail = IDXDIFF(pidx, cidx, r->size);
3585 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3586 DBG_COUNTER_INC(txq_drain_flushing);
3587 for (i = 0; i < avail; i++) {
3588 m_free(r->items[(cidx + i) & (r->size-1)]);
3589 r->items[(cidx + i) & (r->size-1)] = NULL;
3594 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3595 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3597 callout_stop(&txq->ift_timer);
3598 CALLOUT_UNLOCK(txq);
3599 DBG_COUNTER_INC(txq_drain_oactive);
3603 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3604 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3605 count = MIN(avail, TX_BATCH_SIZE);
3607 if (iflib_verbose_debug)
3608 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3609 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3611 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3612 avail = TXQ_AVAIL(txq);
3614 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3615 int rem = do_prefetch ? count - i : 0;
3617 mp = _ring_peek_one(r, cidx, i, rem);
3618 MPASS(mp != NULL && *mp != NULL);
3619 if (__predict_false(*mp == (struct mbuf *)txq)) {
3624 in_use_prev = txq->ift_in_use;
3625 err = iflib_encap(txq, mp);
3626 if (__predict_false(err)) {
3627 DBG_COUNTER_INC(txq_drain_encapfail);
3628 /* no room - bail out */
3632 DBG_COUNTER_INC(txq_drain_encapfail);
3633 /* we can't send this packet - skip it */
3639 DBG_COUNTER_INC(tx_sent);
3640 bytes_sent += m->m_pkthdr.len;
3641 mcast_sent += !!(m->m_flags & M_MCAST);
3642 avail = TXQ_AVAIL(txq);
3644 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3645 desc_used += (txq->ift_in_use - in_use_prev);
3646 ETHER_BPF_MTAP(ifp, m);
3647 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3649 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3652 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3653 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3654 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3655 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3656 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3658 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3660 if (iflib_verbose_debug)
3661 printf("consumed=%d\n", consumed);
3667 iflib_txq_drain_always(struct ifmp_ring *r)
3673 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3681 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3683 callout_stop(&txq->ift_timer);
3684 CALLOUT_UNLOCK(txq);
3686 avail = IDXDIFF(pidx, cidx, r->size);
3687 for (i = 0; i < avail; i++) {
3688 mp = _ring_peek_one(r, cidx, i, avail - i);
3689 if (__predict_false(*mp == (struct mbuf *)txq))
3693 MPASS(ifmp_ring_is_stalled(r) == 0);
3698 iflib_ifmp_purge(iflib_txq_t txq)
3700 struct ifmp_ring *r;
3703 r->drain = iflib_txq_drain_free;
3704 r->can_drain = iflib_txq_drain_always;
3706 ifmp_ring_check_drainage(r, r->size);
3708 r->drain = iflib_txq_drain;
3709 r->can_drain = iflib_txq_can_drain;
3713 _task_fn_tx(void *context)
3715 iflib_txq_t txq = context;
3716 if_ctx_t ctx = txq->ift_ctx;
3717 struct ifnet *ifp = ctx->ifc_ifp;
3719 #ifdef IFLIB_DIAGNOSTICS
3720 txq->ift_cpu_exec_count[curcpu]++;
3722 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3724 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3726 * If there are no available credits, and TX IRQs are not in use,
3727 * re-schedule the task immediately.
3729 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3730 netmap_tx_irq(ifp, txq->ift_id);
3731 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3734 if (txq->ift_db_pending)
3735 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3736 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3737 if (ctx->ifc_flags & IFC_LEGACY)
3738 IFDI_INTR_ENABLE(ctx);
3743 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3744 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3749 _task_fn_rx(void *context)
3751 iflib_rxq_t rxq = context;
3752 if_ctx_t ctx = rxq->ifr_ctx;
3756 #ifdef IFLIB_DIAGNOSTICS
3757 rxq->ifr_cpu_exec_count[curcpu]++;
3759 DBG_COUNTER_INC(task_fn_rxs);
3760 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3764 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3766 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3771 budget = ctx->ifc_sysctl_rx_budget;
3773 budget = 16; /* XXX */
3774 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3775 if (ctx->ifc_flags & IFC_LEGACY)
3776 IFDI_INTR_ENABLE(ctx);
3781 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3782 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3783 DBG_COUNTER_INC(rx_intr_enables);
3786 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3789 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3793 _task_fn_admin(void *context)
3795 if_ctx_t ctx = context;
3796 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3799 bool oactive, running, do_reset, do_watchdog;
3802 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3803 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3804 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3805 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3806 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3809 if ((!running & !oactive) &&
3810 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3814 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3816 callout_stop(&txq->ift_timer);
3817 CALLOUT_UNLOCK(txq);
3820 ctx->ifc_watchdog_events++;
3821 IFDI_WATCHDOG_RESET(ctx);
3823 IFDI_UPDATE_ADMIN_STATUS(ctx);
3824 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3825 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3826 IFDI_LINK_INTR_ENABLE(ctx);
3828 iflib_if_init_locked(ctx);
3831 if (LINK_ACTIVE(ctx) == 0)
3833 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3834 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3839 _task_fn_iov(void *context)
3841 if_ctx_t ctx = context;
3843 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3847 IFDI_VFLR_HANDLE(ctx);
3852 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3855 if_int_delay_info_t info;
3858 info = (if_int_delay_info_t)arg1;
3859 ctx = info->iidi_ctx;
3860 info->iidi_req = req;
3861 info->iidi_oidp = oidp;
3863 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3868 /*********************************************************************
3872 **********************************************************************/
3875 iflib_if_init_locked(if_ctx_t ctx)
3878 iflib_init_locked(ctx);
3883 iflib_if_init(void *arg)
3888 iflib_if_init_locked(ctx);
3893 iflib_if_transmit(if_t ifp, struct mbuf *m)
3895 if_ctx_t ctx = if_getsoftc(ifp);
3900 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3901 DBG_COUNTER_INC(tx_frees);
3906 MPASS(m->m_nextpkt == NULL);
3908 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3909 qidx = QIDX(ctx, m);
3911 * XXX calculate buf_ring based on flowid (divvy up bits?)
3913 txq = &ctx->ifc_txqs[qidx];
3915 #ifdef DRIVER_BACKPRESSURE
3916 if (txq->ift_closed) {
3918 next = m->m_nextpkt;
3919 m->m_nextpkt = NULL;
3932 next = next->m_nextpkt;
3933 } while (next != NULL);
3935 if (count > nitems(marr))
3936 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3937 /* XXX check nextpkt */
3939 /* XXX simplify for now */
3940 DBG_COUNTER_INC(tx_frees);
3943 for (next = m, i = 0; next != NULL; i++) {
3945 next = next->m_nextpkt;
3946 mp[i]->m_nextpkt = NULL;
3949 DBG_COUNTER_INC(tx_seen);
3950 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3952 GROUPTASK_ENQUEUE(&txq->ift_task);
3954 /* support forthcoming later */
3955 #ifdef DRIVER_BACKPRESSURE
3956 txq->ift_closed = TRUE;
3958 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3966 iflib_if_qflush(if_t ifp)
3968 if_ctx_t ctx = if_getsoftc(ifp);
3969 iflib_txq_t txq = ctx->ifc_txqs;
3973 ctx->ifc_flags |= IFC_QFLUSH;
3975 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3976 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3977 iflib_txq_check_drain(txq, 0);
3979 ctx->ifc_flags &= ~IFC_QFLUSH;
3986 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3987 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3988 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3991 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3993 if_ctx_t ctx = if_getsoftc(ifp);
3994 struct ifreq *ifr = (struct ifreq *)data;
3995 #if defined(INET) || defined(INET6)
3996 struct ifaddr *ifa = (struct ifaddr *)data;
3998 bool avoid_reset = FALSE;
3999 int err = 0, reinit = 0, bits;
4004 if (ifa->ifa_addr->sa_family == AF_INET)
4008 if (ifa->ifa_addr->sa_family == AF_INET6)
4012 ** Calling init results in link renegotiation,
4013 ** so we avoid doing it when possible.
4016 if_setflagbits(ifp, IFF_UP,0);
4017 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4020 if (!(if_getflags(ifp) & IFF_NOARP))
4021 arp_ifinit(ifp, ifa);
4024 err = ether_ioctl(ifp, command, data);
4028 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4032 bits = if_getdrvflags(ifp);
4033 /* stop the driver and free any clusters before proceeding */
4036 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4038 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4039 ctx->ifc_flags |= IFC_MULTISEG;
4041 ctx->ifc_flags &= ~IFC_MULTISEG;
4043 err = if_setmtu(ifp, ifr->ifr_mtu);
4045 iflib_init_locked(ctx);
4047 if_setdrvflags(ifp, bits);
4053 if (if_getflags(ifp) & IFF_UP) {
4054 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4055 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4056 (IFF_PROMISC | IFF_ALLMULTI)) {
4057 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4061 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4064 ctx->ifc_if_flags = if_getflags(ifp);
4069 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4071 IFDI_INTR_DISABLE(ctx);
4072 IFDI_MULTI_SET(ctx);
4073 IFDI_INTR_ENABLE(ctx);
4079 IFDI_MEDIA_SET(ctx);
4084 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4088 struct ifi2creq i2c;
4090 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4093 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4097 if (i2c.len > sizeof(i2c.data)) {
4102 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4103 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4111 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4114 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4116 setmask |= (mask & IFCAP_FLAGS);
4118 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4119 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4120 if ((mask & IFCAP_WOL) &&
4121 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4122 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4125 * want to ensure that traffic has stopped before we change any of the flags
4129 bits = if_getdrvflags(ifp);
4130 if (bits & IFF_DRV_RUNNING)
4133 if_togglecapenable(ifp, setmask);
4135 if (bits & IFF_DRV_RUNNING)
4136 iflib_init_locked(ctx);
4138 if_setdrvflags(ifp, bits);
4144 case SIOCGPRIVATE_0:
4148 err = IFDI_PRIV_IOCTL(ctx, command, data);
4152 err = ether_ioctl(ifp, command, data);
4161 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4163 if_ctx_t ctx = if_getsoftc(ifp);
4165 return (IFDI_GET_COUNTER(ctx, cnt));
4168 /*********************************************************************
4170 * OTHER FUNCTIONS EXPORTED TO THE STACK
4172 **********************************************************************/
4175 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4177 if_ctx_t ctx = if_getsoftc(ifp);
4179 if ((void *)ctx != arg)
4182 if ((vtag == 0) || (vtag > 4095))
4186 IFDI_VLAN_REGISTER(ctx, vtag);
4187 /* Re-init to load the changes */
4188 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4189 iflib_if_init_locked(ctx);
4194 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4196 if_ctx_t ctx = if_getsoftc(ifp);
4198 if ((void *)ctx != arg)
4201 if ((vtag == 0) || (vtag > 4095))
4205 IFDI_VLAN_UNREGISTER(ctx, vtag);
4206 /* Re-init to load the changes */
4207 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4208 iflib_if_init_locked(ctx);
4213 iflib_led_func(void *arg, int onoff)
4218 IFDI_LED_FUNC(ctx, onoff);
4222 /*********************************************************************
4224 * BUS FUNCTION DEFINITIONS
4226 **********************************************************************/
4229 iflib_device_probe(device_t dev)
4231 pci_vendor_info_t *ent;
4233 uint16_t pci_vendor_id, pci_device_id;
4234 uint16_t pci_subvendor_id, pci_subdevice_id;
4235 uint16_t pci_rev_id;
4236 if_shared_ctx_t sctx;
4238 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4241 pci_vendor_id = pci_get_vendor(dev);
4242 pci_device_id = pci_get_device(dev);
4243 pci_subvendor_id = pci_get_subvendor(dev);
4244 pci_subdevice_id = pci_get_subdevice(dev);
4245 pci_rev_id = pci_get_revid(dev);
4246 if (sctx->isc_parse_devinfo != NULL)
4247 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4249 ent = sctx->isc_vendor_info;
4250 while (ent->pvi_vendor_id != 0) {
4251 if (pci_vendor_id != ent->pvi_vendor_id) {
4255 if ((pci_device_id == ent->pvi_device_id) &&
4256 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4257 (ent->pvi_subvendor_id == 0)) &&
4258 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4259 (ent->pvi_subdevice_id == 0)) &&
4260 ((pci_rev_id == ent->pvi_rev_id) ||
4261 (ent->pvi_rev_id == 0))) {
4263 device_set_desc_copy(dev, ent->pvi_name);
4264 /* this needs to be changed to zero if the bus probing code
4265 * ever stops re-probing on best match because the sctx
4266 * may have its values over written by register calls
4267 * in subsequent probes
4269 return (BUS_PROBE_DEFAULT);
4277 iflib_reset_qvalues(if_ctx_t ctx)
4279 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4280 if_shared_ctx_t sctx = ctx->ifc_sctx;
4281 device_t dev = ctx->ifc_dev;
4284 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4285 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4287 * XXX sanity check that ntxd & nrxd are a power of 2
4289 if (ctx->ifc_sysctl_ntxqs != 0)
4290 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4291 if (ctx->ifc_sysctl_nrxqs != 0)
4292 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4294 for (i = 0; i < sctx->isc_ntxqs; i++) {
4295 if (ctx->ifc_sysctl_ntxds[i] != 0)
4296 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4298 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4301 for (i = 0; i < sctx->isc_nrxqs; i++) {
4302 if (ctx->ifc_sysctl_nrxds[i] != 0)
4303 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4305 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4308 for (i = 0; i < sctx->isc_nrxqs; i++) {
4309 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4310 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4311 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4312 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4314 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4315 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4316 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4317 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4321 for (i = 0; i < sctx->isc_ntxqs; i++) {
4322 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4323 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4324 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4325 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4327 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4328 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4329 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4330 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4336 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4341 if_softc_ctx_t scctx;
4347 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4350 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4351 device_set_softc(dev, ctx);
4352 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4355 ctx->ifc_sctx = sctx;
4357 ctx->ifc_softc = sc;
4359 if ((err = iflib_register(ctx)) != 0) {
4360 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4363 device_printf(dev, "iflib_register failed %d\n", err);
4366 iflib_add_device_sysctl_pre(ctx);
4368 scctx = &ctx->ifc_softc_ctx;
4371 iflib_reset_qvalues(ctx);
4373 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4375 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4378 _iflib_pre_assert(scctx);
4379 ctx->ifc_txrx = *scctx->isc_txrx;
4382 MPASS(scctx->isc_capenable);
4383 if (scctx->isc_capenable & IFCAP_TXCSUM)
4384 MPASS(scctx->isc_tx_csum_flags);
4387 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4388 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4390 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4391 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4392 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4393 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4396 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4397 ctx->ifc_flags |= IFC_DMAR;
4398 #elif !(defined(__i386__) || defined(__amd64__))
4399 /* set unconditionally for !x86 */
4400 ctx->ifc_flags |= IFC_DMAR;
4403 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4404 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4406 /* XXX change for per-queue sizes */
4407 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4408 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4409 for (i = 0; i < sctx->isc_nrxqs; i++) {
4410 if (!powerof2(scctx->isc_nrxd[i])) {
4411 /* round down instead? */
4412 device_printf(dev, "# rx descriptors must be a power of 2\n");
4417 for (i = 0; i < sctx->isc_ntxqs; i++) {
4418 if (!powerof2(scctx->isc_ntxd[i])) {
4420 "# tx descriptors must be a power of 2");
4426 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4427 MAX_SINGLE_PACKET_FRACTION)
4428 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4429 MAX_SINGLE_PACKET_FRACTION);
4430 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4431 MAX_SINGLE_PACKET_FRACTION)
4432 scctx->isc_tx_tso_segments_max = max(1,
4433 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4436 * Protect the stack against modern hardware
4438 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4439 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4441 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4442 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4443 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4444 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4445 if (scctx->isc_rss_table_size == 0)
4446 scctx->isc_rss_table_size = 64;
4447 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4449 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4450 /* XXX format name */
4451 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4453 /* Set up cpu set. If it fails, use the set of all CPUs. */
4454 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4455 device_printf(dev, "Unable to fetch CPU list\n");
4456 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4458 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4461 ** Now setup MSI or MSI/X, should
4462 ** return us the number of supported
4463 ** vectors. (Will be 1 for MSI)
4465 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4466 msix = scctx->isc_vectors;
4467 } else if (scctx->isc_msix_bar != 0)
4469 * The simple fact that isc_msix_bar is not 0 does not mean we
4470 * we have a good value there that is known to work.
4472 msix = iflib_msix_init(ctx);
4474 scctx->isc_vectors = 1;
4475 scctx->isc_ntxqsets = 1;
4476 scctx->isc_nrxqsets = 1;
4477 scctx->isc_intr = IFLIB_INTR_LEGACY;
4480 /* Get memory for the station queues */
4481 if ((err = iflib_queues_alloc(ctx))) {
4482 device_printf(dev, "Unable to allocate queue memory\n");
4486 if ((err = iflib_qset_structures_setup(ctx)))
4490 * Group taskqueues aren't properly set up until SMP is started,
4491 * so we disable interrupts until we can handle them post
4494 * XXX: disabling interrupts doesn't actually work, at least for
4495 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4496 * we do null handling and depend on this not causing too large an
4499 IFDI_INTR_DISABLE(ctx);
4500 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4501 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4502 goto fail_intr_free;
4506 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4510 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4511 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4512 goto fail_intr_free;
4515 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4516 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4517 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4520 if ((err = iflib_netmap_attach(ctx))) {
4521 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4526 NETDUMP_SET(ctx->ifc_ifp, iflib);
4528 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4529 iflib_add_device_sysctl_post(ctx);
4530 ctx->ifc_flags |= IFC_INIT_DONE;
4534 ether_ifdetach(ctx->ifc_ifp);
4536 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4537 pci_release_msi(ctx->ifc_dev);
4539 iflib_tx_structures_free(ctx);
4540 iflib_rx_structures_free(ctx);
4548 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4549 struct iflib_cloneattach_ctx *clctx)
4554 if_softc_ctx_t scctx;
4560 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4561 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4562 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4563 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4564 ctx->ifc_flags |= IFC_PSEUDO;
4566 ctx->ifc_sctx = sctx;
4567 ctx->ifc_softc = sc;
4570 if ((err = iflib_register(ctx)) != 0) {
4571 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4576 iflib_add_device_sysctl_pre(ctx);
4578 scctx = &ctx->ifc_softc_ctx;
4582 * XXX sanity check that ntxd & nrxd are a power of 2
4584 iflib_reset_qvalues(ctx);
4586 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4587 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4590 if (sctx->isc_flags & IFLIB_GEN_MAC)
4592 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4593 clctx->cc_params)) != 0) {
4594 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4597 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4598 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4599 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4602 MPASS(scctx->isc_capenable);
4603 if (scctx->isc_capenable & IFCAP_TXCSUM)
4604 MPASS(scctx->isc_tx_csum_flags);
4607 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4608 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4610 ifp->if_flags |= IFF_NOGROUP;
4611 if (sctx->isc_flags & IFLIB_PSEUDO) {
4612 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4614 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4615 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4620 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4621 iflib_add_device_sysctl_post(ctx);
4622 ctx->ifc_flags |= IFC_INIT_DONE;
4625 _iflib_pre_assert(scctx);
4626 ctx->ifc_txrx = *scctx->isc_txrx;
4628 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4629 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4630 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4631 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4633 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4634 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4636 /* XXX change for per-queue sizes */
4637 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4638 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4639 for (i = 0; i < sctx->isc_nrxqs; i++) {
4640 if (!powerof2(scctx->isc_nrxd[i])) {
4641 /* round down instead? */
4642 device_printf(dev, "# rx descriptors must be a power of 2\n");
4647 for (i = 0; i < sctx->isc_ntxqs; i++) {
4648 if (!powerof2(scctx->isc_ntxd[i])) {
4650 "# tx descriptors must be a power of 2");
4656 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4657 MAX_SINGLE_PACKET_FRACTION)
4658 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4659 MAX_SINGLE_PACKET_FRACTION);
4660 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4661 MAX_SINGLE_PACKET_FRACTION)
4662 scctx->isc_tx_tso_segments_max = max(1,
4663 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4666 * Protect the stack against modern hardware
4668 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4669 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4671 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4672 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4673 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4674 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4675 if (scctx->isc_rss_table_size == 0)
4676 scctx->isc_rss_table_size = 64;
4677 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4679 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4680 /* XXX format name */
4681 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4683 /* XXX --- can support > 1 -- but keep it simple for now */
4684 scctx->isc_intr = IFLIB_INTR_LEGACY;
4686 /* Get memory for the station queues */
4687 if ((err = iflib_queues_alloc(ctx))) {
4688 device_printf(dev, "Unable to allocate queue memory\n");
4692 if ((err = iflib_qset_structures_setup(ctx))) {
4693 device_printf(dev, "qset structure setup failed %d\n", err);
4697 * XXX What if anything do we want to do about interrupts?
4699 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4700 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4701 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4704 /* XXX handle more than one queue */
4705 for (i = 0; i < scctx->isc_nrxqsets; i++)
4706 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4710 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4711 iflib_add_device_sysctl_post(ctx);
4712 ctx->ifc_flags |= IFC_INIT_DONE;
4715 ether_ifdetach(ctx->ifc_ifp);
4717 iflib_tx_structures_free(ctx);
4718 iflib_rx_structures_free(ctx);
4725 iflib_pseudo_deregister(if_ctx_t ctx)
4727 if_t ifp = ctx->ifc_ifp;
4731 struct taskqgroup *tqg;
4734 /* Unregister VLAN events */
4735 if (ctx->ifc_vlan_attach_event != NULL)
4736 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4737 if (ctx->ifc_vlan_detach_event != NULL)
4738 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4740 ether_ifdetach(ifp);
4741 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4742 CTX_LOCK_DESTROY(ctx);
4743 /* XXX drain any dependent tasks */
4744 tqg = qgroup_if_io_tqg;
4745 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4746 callout_drain(&txq->ift_timer);
4747 if (txq->ift_task.gt_uniq != NULL)
4748 taskqgroup_detach(tqg, &txq->ift_task);
4750 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4751 if (rxq->ifr_task.gt_uniq != NULL)
4752 taskqgroup_detach(tqg, &rxq->ifr_task);
4754 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4755 free(fl->ifl_rx_bitmap, M_IFLIB);
4757 tqg = qgroup_if_config_tqg;
4758 if (ctx->ifc_admin_task.gt_uniq != NULL)
4759 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4760 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4761 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4765 iflib_tx_structures_free(ctx);
4766 iflib_rx_structures_free(ctx);
4767 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4768 free(ctx->ifc_softc, M_IFLIB);
4774 iflib_device_attach(device_t dev)
4777 if_shared_ctx_t sctx;
4779 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4782 pci_enable_busmaster(dev);
4784 return (iflib_device_register(dev, NULL, sctx, &ctx));
4788 iflib_device_deregister(if_ctx_t ctx)
4790 if_t ifp = ctx->ifc_ifp;
4793 device_t dev = ctx->ifc_dev;
4795 struct taskqgroup *tqg;
4798 /* Make sure VLANS are not using driver */
4799 if (if_vlantrunkinuse(ifp)) {
4800 device_printf(dev,"Vlan in use, detach first\n");
4805 ctx->ifc_in_detach = 1;
4809 /* Unregister VLAN events */
4810 if (ctx->ifc_vlan_attach_event != NULL)
4811 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4812 if (ctx->ifc_vlan_detach_event != NULL)
4813 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4815 iflib_netmap_detach(ifp);
4816 ether_ifdetach(ifp);
4817 if (ctx->ifc_led_dev != NULL)
4818 led_destroy(ctx->ifc_led_dev);
4819 /* XXX drain any dependent tasks */
4820 tqg = qgroup_if_io_tqg;
4821 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4822 callout_drain(&txq->ift_timer);
4823 if (txq->ift_task.gt_uniq != NULL)
4824 taskqgroup_detach(tqg, &txq->ift_task);
4826 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4827 if (rxq->ifr_task.gt_uniq != NULL)
4828 taskqgroup_detach(tqg, &rxq->ifr_task);
4830 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4831 free(fl->ifl_rx_bitmap, M_IFLIB);
4834 tqg = qgroup_if_config_tqg;
4835 if (ctx->ifc_admin_task.gt_uniq != NULL)
4836 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4837 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4838 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4843 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4844 CTX_LOCK_DESTROY(ctx);
4845 device_set_softc(ctx->ifc_dev, NULL);
4846 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4847 pci_release_msi(dev);
4849 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4850 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4852 if (ctx->ifc_msix_mem != NULL) {
4853 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4854 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4855 ctx->ifc_msix_mem = NULL;
4858 bus_generic_detach(dev);
4861 iflib_tx_structures_free(ctx);
4862 iflib_rx_structures_free(ctx);
4863 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4864 free(ctx->ifc_softc, M_IFLIB);
4871 iflib_device_detach(device_t dev)
4873 if_ctx_t ctx = device_get_softc(dev);
4875 return (iflib_device_deregister(ctx));
4879 iflib_device_suspend(device_t dev)
4881 if_ctx_t ctx = device_get_softc(dev);
4887 return bus_generic_suspend(dev);
4890 iflib_device_shutdown(device_t dev)
4892 if_ctx_t ctx = device_get_softc(dev);
4898 return bus_generic_suspend(dev);
4903 iflib_device_resume(device_t dev)
4905 if_ctx_t ctx = device_get_softc(dev);
4906 iflib_txq_t txq = ctx->ifc_txqs;
4910 iflib_init_locked(ctx);
4912 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4913 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4915 return (bus_generic_resume(dev));
4919 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4922 if_ctx_t ctx = device_get_softc(dev);
4925 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4932 iflib_device_iov_uninit(device_t dev)
4934 if_ctx_t ctx = device_get_softc(dev);
4937 IFDI_IOV_UNINIT(ctx);
4942 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4945 if_ctx_t ctx = device_get_softc(dev);
4948 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4954 /*********************************************************************
4956 * MODULE FUNCTION DEFINITIONS
4958 **********************************************************************/
4961 * - Start a fast taskqueue thread for each core
4962 * - Start a taskqueue for control operations
4965 iflib_module_init(void)
4971 iflib_module_event_handler(module_t mod, int what, void *arg)
4977 if ((err = iflib_module_init()) != 0)
4983 return (EOPNOTSUPP);
4989 /*********************************************************************
4991 * PUBLIC FUNCTION DEFINITIONS
4992 * ordered as in iflib.h
4994 **********************************************************************/
4998 _iflib_assert(if_shared_ctx_t sctx)
5000 MPASS(sctx->isc_tx_maxsize);
5001 MPASS(sctx->isc_tx_maxsegsize);
5003 MPASS(sctx->isc_rx_maxsize);
5004 MPASS(sctx->isc_rx_nsegments);
5005 MPASS(sctx->isc_rx_maxsegsize);
5007 MPASS(sctx->isc_nrxd_min[0]);
5008 MPASS(sctx->isc_nrxd_max[0]);
5009 MPASS(sctx->isc_nrxd_default[0]);
5010 MPASS(sctx->isc_ntxd_min[0]);
5011 MPASS(sctx->isc_ntxd_max[0]);
5012 MPASS(sctx->isc_ntxd_default[0]);
5016 _iflib_pre_assert(if_softc_ctx_t scctx)
5019 MPASS(scctx->isc_txrx->ift_txd_encap);
5020 MPASS(scctx->isc_txrx->ift_txd_flush);
5021 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5022 MPASS(scctx->isc_txrx->ift_rxd_available);
5023 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5024 MPASS(scctx->isc_txrx->ift_rxd_refill);
5025 MPASS(scctx->isc_txrx->ift_rxd_flush);
5029 iflib_register(if_ctx_t ctx)
5031 if_shared_ctx_t sctx = ctx->ifc_sctx;
5032 driver_t *driver = sctx->isc_driver;
5033 device_t dev = ctx->ifc_dev;
5036 _iflib_assert(sctx);
5039 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5040 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
5042 device_printf(dev, "can not allocate ifnet structure\n");
5047 * Initialize our context's device specific methods
5049 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5050 kobj_class_compile((kobj_class_t) driver);
5053 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5054 if_setsoftc(ifp, ctx);
5055 if_setdev(ifp, dev);
5056 if_setinitfn(ifp, iflib_if_init);
5057 if_setioctlfn(ifp, iflib_if_ioctl);
5058 if_settransmitfn(ifp, iflib_if_transmit);
5059 if_setqflushfn(ifp, iflib_if_qflush);
5060 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5062 ctx->ifc_vlan_attach_event =
5063 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5064 EVENTHANDLER_PRI_FIRST);
5065 ctx->ifc_vlan_detach_event =
5066 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5067 EVENTHANDLER_PRI_FIRST);
5069 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5070 iflib_media_change, iflib_media_status);
5077 iflib_queues_alloc(if_ctx_t ctx)
5079 if_shared_ctx_t sctx = ctx->ifc_sctx;
5080 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5081 device_t dev = ctx->ifc_dev;
5082 int nrxqsets = scctx->isc_nrxqsets;
5083 int ntxqsets = scctx->isc_ntxqsets;
5086 iflib_fl_t fl = NULL;
5087 int i, j, cpu, err, txconf, rxconf;
5088 iflib_dma_info_t ifdip;
5089 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5090 uint32_t *txqsizes = scctx->isc_txqsizes;
5091 uint8_t nrxqs = sctx->isc_nrxqs;
5092 uint8_t ntxqs = sctx->isc_ntxqs;
5093 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5097 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5098 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5100 /* Allocate the TX ring struct memory */
5101 if (!(ctx->ifc_txqs =
5102 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5103 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5104 device_printf(dev, "Unable to allocate TX ring memory\n");
5109 /* Now allocate the RX */
5110 if (!(ctx->ifc_rxqs =
5111 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5112 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5113 device_printf(dev, "Unable to allocate RX ring memory\n");
5118 txq = ctx->ifc_txqs;
5119 rxq = ctx->ifc_rxqs;
5122 * XXX handle allocation failure
5124 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5125 /* Set up some basics */
5127 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5128 device_printf(dev, "failed to allocate iflib_dma_info\n");
5132 txq->ift_ifdi = ifdip;
5133 for (j = 0; j < ntxqs; j++, ifdip++) {
5134 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5135 device_printf(dev, "Unable to allocate Descriptor memory\n");
5139 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5140 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5144 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5145 txq->ift_br_offset = 1;
5147 txq->ift_br_offset = 0;
5150 txq->ift_timer.c_cpu = cpu;
5152 if (iflib_txsd_alloc(txq)) {
5153 device_printf(dev, "Critical Failure setting up TX buffers\n");
5158 /* Initialize the TX lock */
5159 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5160 device_get_nameunit(dev), txq->ift_id);
5161 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5162 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5164 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5165 device_get_nameunit(dev), txq->ift_id);
5167 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5168 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5170 /* XXX free any allocated rings */
5171 device_printf(dev, "Unable to allocate buf_ring\n");
5176 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5177 /* Set up some basics */
5179 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5180 device_printf(dev, "failed to allocate iflib_dma_info\n");
5185 rxq->ifr_ifdi = ifdip;
5186 /* XXX this needs to be changed if #rx queues != #tx queues */
5187 rxq->ifr_ntxqirq = 1;
5188 rxq->ifr_txqid[0] = i;
5189 for (j = 0; j < nrxqs; j++, ifdip++) {
5190 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5191 device_printf(dev, "Unable to allocate Descriptor memory\n");
5195 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5199 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5200 rxq->ifr_fl_offset = 1;
5202 rxq->ifr_fl_offset = 0;
5204 rxq->ifr_nfl = nfree_lists;
5206 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5207 device_printf(dev, "Unable to allocate free list memory\n");
5212 for (j = 0; j < nfree_lists; j++) {
5213 fl[j].ifl_rxq = rxq;
5215 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5216 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5218 /* Allocate receive buffers for the ring*/
5219 if (iflib_rxsd_alloc(rxq)) {
5221 "Critical Failure setting up receive buffers\n");
5226 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5227 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
5231 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5232 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5233 for (i = 0; i < ntxqsets; i++) {
5234 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5236 for (j = 0; j < ntxqs; j++, di++) {
5237 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5238 paddrs[i*ntxqs + j] = di->idi_paddr;
5241 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5242 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5243 iflib_tx_structures_free(ctx);
5244 free(vaddrs, M_IFLIB);
5245 free(paddrs, M_IFLIB);
5248 free(vaddrs, M_IFLIB);
5249 free(paddrs, M_IFLIB);
5252 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5253 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5254 for (i = 0; i < nrxqsets; i++) {
5255 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5257 for (j = 0; j < nrxqs; j++, di++) {
5258 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5259 paddrs[i*nrxqs + j] = di->idi_paddr;
5262 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5263 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5264 iflib_tx_structures_free(ctx);
5265 free(vaddrs, M_IFLIB);
5266 free(paddrs, M_IFLIB);
5269 free(vaddrs, M_IFLIB);
5270 free(paddrs, M_IFLIB);
5274 /* XXX handle allocation failure changes */
5278 if (ctx->ifc_rxqs != NULL)
5279 free(ctx->ifc_rxqs, M_IFLIB);
5280 ctx->ifc_rxqs = NULL;
5281 if (ctx->ifc_txqs != NULL)
5282 free(ctx->ifc_txqs, M_IFLIB);
5283 ctx->ifc_txqs = NULL;
5289 iflib_tx_structures_setup(if_ctx_t ctx)
5291 iflib_txq_t txq = ctx->ifc_txqs;
5294 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5295 iflib_txq_setup(txq);
5301 iflib_tx_structures_free(if_ctx_t ctx)
5303 iflib_txq_t txq = ctx->ifc_txqs;
5306 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5307 iflib_txq_destroy(txq);
5308 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
5309 iflib_dma_free(&txq->ift_ifdi[j]);
5311 free(ctx->ifc_txqs, M_IFLIB);
5312 ctx->ifc_txqs = NULL;
5313 IFDI_QUEUES_FREE(ctx);
5316 /*********************************************************************
5318 * Initialize all receive rings.
5320 **********************************************************************/
5322 iflib_rx_structures_setup(if_ctx_t ctx)
5324 iflib_rxq_t rxq = ctx->ifc_rxqs;
5326 #if defined(INET6) || defined(INET)
5330 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5331 #if defined(INET6) || defined(INET)
5332 tcp_lro_free(&rxq->ifr_lc);
5333 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5334 TCP_LRO_ENTRIES, min(1024,
5335 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5336 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5339 rxq->ifr_lro_enabled = TRUE;
5341 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5344 #if defined(INET6) || defined(INET)
5347 * Free RX software descriptors allocated so far, we will only handle
5348 * the rings that completed, the failing case will have
5349 * cleaned up for itself. 'q' failed, so its the terminus.
5351 rxq = ctx->ifc_rxqs;
5352 for (i = 0; i < q; ++i, rxq++) {
5353 iflib_rx_sds_free(rxq);
5354 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5360 /*********************************************************************
5362 * Free all receive rings.
5364 **********************************************************************/
5366 iflib_rx_structures_free(if_ctx_t ctx)
5368 iflib_rxq_t rxq = ctx->ifc_rxqs;
5370 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5371 iflib_rx_sds_free(rxq);
5376 iflib_qset_structures_setup(if_ctx_t ctx)
5381 * It is expected that the caller takes care of freeing queues if this
5384 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5385 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5389 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5390 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5396 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5397 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5400 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5405 find_nth(if_ctx_t ctx, int qid)
5408 int i, cpuid, eqid, count;
5410 CPU_COPY(&ctx->ifc_cpus, &cpus);
5411 count = CPU_COUNT(&cpus);
5413 /* clear up to the qid'th bit */
5414 for (i = 0; i < eqid; i++) {
5415 cpuid = CPU_FFS(&cpus);
5417 CPU_CLR(cpuid-1, &cpus);
5419 cpuid = CPU_FFS(&cpus);
5425 extern struct cpu_group *cpu_top; /* CPU topology */
5428 find_child_with_core(int cpu, struct cpu_group *grp)
5432 if (grp->cg_children == 0)
5435 MPASS(grp->cg_child);
5436 for (i = 0; i < grp->cg_children; i++) {
5437 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5445 * Find the nth "close" core to the specified core
5446 * "close" is defined as the deepest level that shares
5447 * at least an L2 cache. With threads, this will be
5448 * threads on the same core. If the sahred cache is L3
5449 * or higher, simply returns the same core.
5452 find_close_core(int cpu, int core_offset)
5454 struct cpu_group *grp;
5463 while ((i = find_child_with_core(cpu, grp)) != -1) {
5464 /* If the child only has one cpu, don't descend */
5465 if (grp->cg_child[i].cg_count <= 1)
5467 grp = &grp->cg_child[i];
5470 /* If they don't share at least an L2 cache, use the same CPU */
5471 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5475 CPU_COPY(&grp->cg_mask, &cs);
5477 /* Add the selected CPU offset to core offset. */
5478 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5479 if (fcpu - 1 == cpu)
5481 CPU_CLR(fcpu - 1, &cs);
5487 CPU_COPY(&grp->cg_mask, &cs);
5488 for (i = core_offset % grp->cg_count; i > 0; i--) {
5489 MPASS(CPU_FFS(&cs));
5490 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5492 MPASS(CPU_FFS(&cs));
5493 return CPU_FFS(&cs) - 1;
5497 find_close_core(int cpu, int core_offset __unused)
5504 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5508 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5509 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5510 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5512 case IFLIB_INTR_RXTX:
5513 /* RX queues get the specified core */
5514 return qid / CPU_COUNT(&ctx->ifc_cpus);
5520 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5521 #define find_close_core(cpuid, tid) CPU_FIRST()
5522 #define find_nth(ctx, gid) CPU_FIRST()
5525 /* Just to avoid copy/paste */
5527 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5528 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5533 cpuid = find_nth(ctx, qid);
5534 tid = get_core_offset(ctx, type, qid);
5536 cpuid = find_close_core(cpuid, tid);
5537 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5539 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5543 if (cpuid > ctx->ifc_cpuid_highest)
5544 ctx->ifc_cpuid_highest = cpuid;
5550 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5551 iflib_intr_type_t type, driver_filter_t *filter,
5552 void *filter_arg, int qid, const char *name)
5554 struct grouptask *gtask;
5555 struct taskqgroup *tqg;
5556 iflib_filter_info_t info;
5559 driver_filter_t *intr_fast;
5562 info = &ctx->ifc_filter_info;
5566 /* XXX merge tx/rx for netmap? */
5568 q = &ctx->ifc_txqs[qid];
5569 info = &ctx->ifc_txqs[qid].ift_filter_info;
5570 gtask = &ctx->ifc_txqs[qid].ift_task;
5571 tqg = qgroup_if_io_tqg;
5573 intr_fast = iflib_fast_intr;
5574 GROUPTASK_INIT(gtask, 0, fn, q);
5575 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5578 q = &ctx->ifc_rxqs[qid];
5579 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5580 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5581 tqg = qgroup_if_io_tqg;
5583 intr_fast = iflib_fast_intr;
5584 GROUPTASK_INIT(gtask, 0, fn, q);
5586 case IFLIB_INTR_RXTX:
5587 q = &ctx->ifc_rxqs[qid];
5588 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5589 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5590 tqg = qgroup_if_io_tqg;
5592 intr_fast = iflib_fast_intr_rxtx;
5593 GROUPTASK_INIT(gtask, 0, fn, q);
5595 case IFLIB_INTR_ADMIN:
5598 info = &ctx->ifc_filter_info;
5599 gtask = &ctx->ifc_admin_task;
5600 tqg = qgroup_if_config_tqg;
5601 fn = _task_fn_admin;
5602 intr_fast = iflib_fast_intr_ctx;
5605 panic("unknown net intr type");
5608 info->ifi_filter = filter;
5609 info->ifi_filter_arg = filter_arg;
5610 info->ifi_task = gtask;
5613 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5615 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5618 if (type == IFLIB_INTR_ADMIN)
5622 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5626 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5633 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5635 struct grouptask *gtask;
5636 struct taskqgroup *tqg;
5644 q = &ctx->ifc_txqs[qid];
5645 gtask = &ctx->ifc_txqs[qid].ift_task;
5646 tqg = qgroup_if_io_tqg;
5649 irq_num = rman_get_start(irq->ii_res);
5652 q = &ctx->ifc_rxqs[qid];
5653 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5654 tqg = qgroup_if_io_tqg;
5657 irq_num = rman_get_start(irq->ii_res);
5659 case IFLIB_INTR_IOV:
5661 gtask = &ctx->ifc_vflr_task;
5662 tqg = qgroup_if_config_tqg;
5666 panic("unknown net intr type");
5668 GROUPTASK_INIT(gtask, 0, fn, q);
5669 if (irq_num != -1) {
5670 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5672 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5675 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5680 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5683 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5686 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5690 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5692 iflib_txq_t txq = ctx->ifc_txqs;
5693 iflib_rxq_t rxq = ctx->ifc_rxqs;
5694 if_irq_t irq = &ctx->ifc_legacy_irq;
5695 iflib_filter_info_t info;
5696 struct grouptask *gtask;
5697 struct taskqgroup *tqg;
5703 q = &ctx->ifc_rxqs[0];
5704 info = &rxq[0].ifr_filter_info;
5705 gtask = &rxq[0].ifr_task;
5706 tqg = qgroup_if_io_tqg;
5707 tqrid = irq->ii_rid = *rid;
5710 ctx->ifc_flags |= IFC_LEGACY;
5711 info->ifi_filter = filter;
5712 info->ifi_filter_arg = filter_arg;
5713 info->ifi_task = gtask;
5714 info->ifi_ctx = ctx;
5716 /* We allocate a single interrupt resource */
5717 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5719 GROUPTASK_INIT(gtask, 0, fn, q);
5720 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5722 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5723 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5728 iflib_led_create(if_ctx_t ctx)
5731 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5732 device_get_nameunit(ctx->ifc_dev));
5736 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5739 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5743 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5746 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5750 iflib_admin_intr_deferred(if_ctx_t ctx)
5753 struct grouptask *gtask;
5755 gtask = &ctx->ifc_admin_task;
5756 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5759 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5763 iflib_iov_intr_deferred(if_ctx_t ctx)
5766 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5770 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5773 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5777 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5781 GROUPTASK_INIT(gtask, 0, fn, ctx);
5782 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5786 iflib_config_gtask_deinit(struct grouptask *gtask)
5789 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5793 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5795 if_t ifp = ctx->ifc_ifp;
5796 iflib_txq_t txq = ctx->ifc_txqs;
5798 if_setbaudrate(ifp, baudrate);
5799 if (baudrate >= IF_Gbps(10)) {
5801 ctx->ifc_flags |= IFC_PREFETCH;
5804 /* If link down, disable watchdog */
5805 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5806 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5807 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5809 ctx->ifc_link_state = link_state;
5810 if_link_state_change(ifp, link_state);
5814 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5818 int credits_pre = txq->ift_cidx_processed;
5821 if (ctx->isc_txd_credits_update == NULL)
5824 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5827 txq->ift_processed += credits;
5828 txq->ift_cidx_processed += credits;
5830 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5831 if (txq->ift_cidx_processed >= txq->ift_size)
5832 txq->ift_cidx_processed -= txq->ift_size;
5837 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5840 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5845 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5846 const char *description, if_int_delay_info_t info,
5847 int offset, int value)
5849 info->iidi_ctx = ctx;
5850 info->iidi_offset = offset;
5851 info->iidi_value = value;
5852 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5853 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5854 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5855 info, 0, iflib_sysctl_int_delay, "I", description);
5859 iflib_ctx_lock_get(if_ctx_t ctx)
5862 return (&ctx->ifc_ctx_sx);
5866 iflib_msix_init(if_ctx_t ctx)
5868 device_t dev = ctx->ifc_dev;
5869 if_shared_ctx_t sctx = ctx->ifc_sctx;
5870 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5871 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5872 int iflib_num_tx_queues, iflib_num_rx_queues;
5873 int err, admincnt, bar;
5875 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5876 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5878 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5880 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5881 admincnt = sctx->isc_admin_intrcnt;
5882 /* Override by tuneable */
5883 if (scctx->isc_disable_msix)
5887 * bar == -1 => "trust me I know what I'm doing"
5888 * Some drivers are for hardware that is so shoddily
5889 * documented that no one knows which bars are which
5890 * so the developer has to map all bars. This hack
5891 * allows shoddy garbage to use msix in this framework.
5894 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5895 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5896 if (ctx->ifc_msix_mem == NULL) {
5897 /* May not be enabled */
5898 device_printf(dev, "Unable to map MSIX table \n");
5902 /* First try MSI/X */
5903 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5904 device_printf(dev, "System has MSIX disabled \n");
5905 bus_release_resource(dev, SYS_RES_MEMORY,
5906 bar, ctx->ifc_msix_mem);
5907 ctx->ifc_msix_mem = NULL;
5911 /* use only 1 qset in debug mode */
5912 queuemsgs = min(msgs - admincnt, 1);
5914 queuemsgs = msgs - admincnt;
5917 queues = imin(queuemsgs, rss_getnumbuckets());
5921 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5922 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5923 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5925 /* If we're doing RSS, clamp at the number of RSS buckets */
5926 if (queues > rss_getnumbuckets())
5927 queues = rss_getnumbuckets();
5929 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5930 rx_queues = iflib_num_rx_queues;
5934 if (rx_queues > scctx->isc_nrxqsets)
5935 rx_queues = scctx->isc_nrxqsets;
5938 * We want this to be all logical CPUs by default
5940 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5941 tx_queues = iflib_num_tx_queues;
5943 tx_queues = mp_ncpus;
5945 if (tx_queues > scctx->isc_ntxqsets)
5946 tx_queues = scctx->isc_ntxqsets;
5948 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5950 if (tx_queues != rx_queues)
5951 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5952 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5954 tx_queues = min(rx_queues, tx_queues);
5955 rx_queues = min(rx_queues, tx_queues);
5958 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5960 vectors = rx_queues + admincnt;
5961 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5963 "Using MSIX interrupts with %d vectors\n", vectors);
5964 scctx->isc_vectors = vectors;
5965 scctx->isc_nrxqsets = rx_queues;
5966 scctx->isc_ntxqsets = tx_queues;
5967 scctx->isc_intr = IFLIB_INTR_MSIX;
5971 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5972 bus_release_resource(dev, SYS_RES_MEMORY, bar,
5974 ctx->ifc_msix_mem = NULL;
5977 vectors = pci_msi_count(dev);
5978 scctx->isc_nrxqsets = 1;
5979 scctx->isc_ntxqsets = 1;
5980 scctx->isc_vectors = vectors;
5981 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5982 device_printf(dev,"Using an MSI interrupt\n");
5983 scctx->isc_intr = IFLIB_INTR_MSI;
5985 scctx->isc_vectors = 1;
5986 device_printf(dev,"Using a Legacy interrupt\n");
5987 scctx->isc_intr = IFLIB_INTR_LEGACY;
5993 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5996 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5999 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6001 const char *ring_state = "UNKNOWN";
6004 rc = sysctl_wire_old_buffer(req, 0);
6008 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6013 ring_state = ring_states[state[3]];
6015 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6016 state[0], state[1], state[2], ring_state);
6017 rc = sbuf_finish(sb);
6022 enum iflib_ndesc_handler {
6028 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6030 if_ctx_t ctx = (void *)arg1;
6031 enum iflib_ndesc_handler type = arg2;
6032 char buf[256] = {0};
6037 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6041 case IFLIB_NTXD_HANDLER:
6042 ndesc = ctx->ifc_sysctl_ntxds;
6044 nqs = ctx->ifc_sctx->isc_ntxqs;
6046 case IFLIB_NRXD_HANDLER:
6047 ndesc = ctx->ifc_sysctl_nrxds;
6049 nqs = ctx->ifc_sctx->isc_nrxqs;
6052 panic("unhandled type");
6057 for (i=0; i<8; i++) {
6062 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6065 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6066 if (rc || req->newptr == NULL)
6069 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6070 i++, p = strsep(&next, " ,")) {
6071 ndesc[i] = strtoul(p, NULL, 10);
6077 #define NAME_BUFLEN 32
6079 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6081 device_t dev = iflib_get_dev(ctx);
6082 struct sysctl_oid_list *child, *oid_list;
6083 struct sysctl_ctx_list *ctx_list;
6084 struct sysctl_oid *node;
6086 ctx_list = device_get_sysctl_ctx(dev);
6087 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6088 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6089 CTLFLAG_RD, NULL, "IFLIB fields");
6090 oid_list = SYSCTL_CHILDREN(node);
6092 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6093 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6096 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6097 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6098 "# of txqs to use, 0 => use default #");
6099 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6100 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6101 "# of rxqs to use, 0 => use default #");
6102 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6103 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6104 "permit #txq != #rxq");
6105 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6106 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6107 "disable MSIX (default 0)");
6108 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6109 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6110 "set the rx budget");
6112 /* XXX change for per-queue sizes */
6113 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6114 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6115 mp_ndesc_handler, "A",
6116 "list of # of tx descriptors to use, 0 = use default #");
6117 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6118 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6119 mp_ndesc_handler, "A",
6120 "list of # of rx descriptors to use, 0 = use default #");
6124 iflib_add_device_sysctl_post(if_ctx_t ctx)
6126 if_shared_ctx_t sctx = ctx->ifc_sctx;
6127 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6128 device_t dev = iflib_get_dev(ctx);
6129 struct sysctl_oid_list *child;
6130 struct sysctl_ctx_list *ctx_list;
6135 char namebuf[NAME_BUFLEN];
6137 struct sysctl_oid *queue_node, *fl_node, *node;
6138 struct sysctl_oid_list *queue_list, *fl_list;
6139 ctx_list = device_get_sysctl_ctx(dev);
6141 node = ctx->ifc_sysctl_node;
6142 child = SYSCTL_CHILDREN(node);
6144 if (scctx->isc_ntxqsets > 100)
6146 else if (scctx->isc_ntxqsets > 10)
6150 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6151 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6152 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6153 CTLFLAG_RD, NULL, "Queue Name");
6154 queue_list = SYSCTL_CHILDREN(queue_node);
6156 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6158 &txq->ift_dequeued, "total mbufs freed");
6159 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6161 &txq->ift_enqueued, "total mbufs enqueued");
6163 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6165 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6166 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6168 &txq->ift_pullups, "# of times m_pullup was called");
6169 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6171 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6172 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6174 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6175 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6177 &txq->ift_map_failed, "# of times dma map failed");
6178 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6180 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6181 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6183 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6184 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6186 &txq->ift_pidx, 1, "Producer Index");
6187 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6189 &txq->ift_cidx, 1, "Consumer Index");
6190 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6192 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6193 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6195 &txq->ift_in_use, 1, "descriptors in use");
6196 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6198 &txq->ift_processed, "descriptors procesed for clean");
6199 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6201 &txq->ift_cleaned, "total cleaned");
6202 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6203 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6204 0, mp_ring_state_handler, "A", "soft ring state");
6205 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6206 CTLFLAG_RD, &txq->ift_br->enqueues,
6207 "# of enqueues to the mp_ring for this queue");
6208 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6209 CTLFLAG_RD, &txq->ift_br->drops,
6210 "# of drops in the mp_ring for this queue");
6211 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6212 CTLFLAG_RD, &txq->ift_br->starts,
6213 "# of normal consumer starts in the mp_ring for this queue");
6214 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6215 CTLFLAG_RD, &txq->ift_br->stalls,
6216 "# of consumer stalls in the mp_ring for this queue");
6217 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6218 CTLFLAG_RD, &txq->ift_br->restarts,
6219 "# of consumer restarts in the mp_ring for this queue");
6220 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6221 CTLFLAG_RD, &txq->ift_br->abdications,
6222 "# of consumer abdications in the mp_ring for this queue");
6225 if (scctx->isc_nrxqsets > 100)
6227 else if (scctx->isc_nrxqsets > 10)
6231 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6232 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6233 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6234 CTLFLAG_RD, NULL, "Queue Name");
6235 queue_list = SYSCTL_CHILDREN(queue_node);
6236 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6237 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6239 &rxq->ifr_cq_pidx, 1, "Producer Index");
6240 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6242 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6245 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6246 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6247 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6248 CTLFLAG_RD, NULL, "freelist Name");
6249 fl_list = SYSCTL_CHILDREN(fl_node);
6250 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6252 &fl->ifl_pidx, 1, "Producer Index");
6253 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6255 &fl->ifl_cidx, 1, "Consumer Index");
6256 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6258 &fl->ifl_credits, 1, "credits available");
6260 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6262 &fl->ifl_m_enqueued, "mbufs allocated");
6263 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6265 &fl->ifl_m_dequeued, "mbufs freed");
6266 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6268 &fl->ifl_cl_enqueued, "clusters allocated");
6269 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6271 &fl->ifl_cl_dequeued, "clusters freed");
6279 #ifndef __NO_STRICT_ALIGNMENT
6280 static struct mbuf *
6281 iflib_fixup_rx(struct mbuf *m)
6285 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6286 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6287 m->m_data += ETHER_HDR_LEN;
6290 MGETHDR(n, M_NOWAIT, MT_DATA);
6295 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6296 m->m_data += ETHER_HDR_LEN;
6297 m->m_len -= ETHER_HDR_LEN;
6298 n->m_len = ETHER_HDR_LEN;
6299 M_MOVE_PKTHDR(n, m);
6308 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6312 ctx = if_getsoftc(ifp);
6314 *nrxr = NRXQSETS(ctx);
6315 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6316 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6321 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6324 if_softc_ctx_t scctx;
6329 ctx = if_getsoftc(ifp);
6330 scctx = &ctx->ifc_softc_ctx;
6334 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6335 rxq = &ctx->ifc_rxqs[i];
6336 for (j = 0; j < rxq->ifr_nfl; j++) {
6338 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6341 iflib_no_tx_batch = 1;
6349 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6355 ctx = if_getsoftc(ifp);
6356 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6360 txq = &ctx->ifc_txqs[0];
6361 error = iflib_encap(txq, &m);
6363 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6368 iflib_netdump_poll(struct ifnet *ifp, int count)
6371 if_softc_ctx_t scctx;
6375 ctx = if_getsoftc(ifp);
6376 scctx = &ctx->ifc_softc_ctx;
6378 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6382 txq = &ctx->ifc_txqs[0];
6383 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6385 for (i = 0; i < scctx->isc_nrxqsets; i++)
6386 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6389 #endif /* NETDUMP */