2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet/netdump/netdump.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
133 typedef struct iflib_txq *iflib_txq_t;
135 typedef struct iflib_rxq *iflib_rxq_t;
137 typedef struct iflib_fl *iflib_fl_t;
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
144 typedef struct iflib_filter_info {
145 driver_filter_t *ifi_filter;
146 void *ifi_filter_arg;
147 struct grouptask *ifi_task;
149 } *iflib_filter_info_t;
154 * Pointer to hardware driver's softc
161 if_shared_ctx_t ifc_sctx;
162 struct if_softc_ctx ifc_softc_ctx;
164 struct sx ifc_ctx_sx;
165 struct mtx ifc_state_mtx;
167 iflib_txq_t ifc_txqs;
168 iflib_rxq_t ifc_rxqs;
169 uint32_t ifc_if_flags;
171 uint32_t ifc_max_fl_buf_size;
172 uint32_t ifc_rx_mbuf_sz;
175 int ifc_watchdog_events;
176 struct cdev *ifc_led_dev;
177 struct resource *ifc_msix_mem;
179 struct if_irq ifc_legacy_irq;
180 struct grouptask ifc_admin_task;
181 struct grouptask ifc_vflr_task;
182 struct iflib_filter_info ifc_filter_info;
183 struct ifmedia ifc_media;
184 struct ifmedia *ifc_mediap;
186 struct sysctl_oid *ifc_sysctl_node;
187 uint16_t ifc_sysctl_ntxqs;
188 uint16_t ifc_sysctl_nrxqs;
189 uint16_t ifc_sysctl_qs_eq_override;
190 uint16_t ifc_sysctl_rx_budget;
191 uint16_t ifc_sysctl_tx_abdicate;
192 uint16_t ifc_sysctl_core_offset;
193 #define CORE_OFFSET_UNSPECIFIED 0xffff
194 uint8_t ifc_sysctl_separate_txrx;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 struct ether_addr ifc_mac;
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (ctx->ifc_mediap);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 #define IFLIB_RX_COPY_THRESH 128
292 #define IFLIB_MAX_RX_REFRESH 32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC 16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
296 #define IFLIB_QUEUE_IDLE 0
297 #define IFLIB_QUEUE_HUNG 1
298 #define IFLIB_QUEUE_WORKING 2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR 4
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE 32
305 #define IFLIB_RESTART_BUDGET 8
307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
314 qidx_t ift_cidx_processed;
317 uint8_t ift_br_offset;
318 uint16_t ift_npending;
319 uint16_t ift_db_pending;
320 uint16_t ift_rs_pending;
322 uint8_t ift_txd_size[8];
323 uint64_t ift_processed;
324 uint64_t ift_cleaned;
325 uint64_t ift_cleaned_prev;
327 uint64_t ift_enqueued;
328 uint64_t ift_dequeued;
330 uint64_t ift_no_tx_dma_setup;
331 uint64_t ift_no_desc_avail;
332 uint64_t ift_mbuf_defrag_failed;
333 uint64_t ift_mbuf_defrag;
334 uint64_t ift_map_failed;
335 uint64_t ift_txd_encap_efbig;
336 uint64_t ift_pullups;
337 uint64_t ift_last_timer_tick;
340 struct mtx ift_db_mtx;
342 /* constant values */
344 struct ifmp_ring *ift_br;
345 struct grouptask ift_task;
348 struct callout ift_timer;
350 if_txsd_vec_t ift_sds;
353 uint8_t ift_update_freq;
354 struct iflib_filter_info ift_filter_info;
355 bus_dma_tag_t ift_buf_tag;
356 bus_dma_tag_t ift_tso_buf_tag;
357 iflib_dma_info_t ift_ifdi;
358 #define MTX_NAME_LEN 16
359 char ift_mtx_name[MTX_NAME_LEN];
360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 uint64_t ift_cpu_exec_count[256];
364 } __aligned(CACHE_LINE_SIZE);
371 uint8_t ifl_rxd_size;
373 uint64_t ifl_m_enqueued;
374 uint64_t ifl_m_dequeued;
375 uint64_t ifl_cl_enqueued;
376 uint64_t ifl_cl_dequeued;
379 bitstr_t *ifl_rx_bitmap;
383 uint16_t ifl_buf_size;
386 iflib_rxsd_array_t ifl_sds;
389 bus_dma_tag_t ifl_buf_tag;
390 iflib_dma_info_t ifl_ifdi;
391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the command queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct iflib_filter_info ifr_filter_info;
438 iflib_dma_info_t ifr_ifdi;
440 /* dynamically allocate if any drivers need a value substantially larger than this */
441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
442 #ifdef IFLIB_DIAGNOSTICS
443 uint64_t ifr_cpu_exec_count[256];
445 } __aligned(CACHE_LINE_SIZE);
447 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_init_locked(if_ctx_t ctx);
706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
707 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
708 static void iflib_ifmp_purge(iflib_txq_t txq);
709 static void _iflib_pre_assert(if_softc_ctx_t scctx);
710 static void iflib_if_init_locked(if_ctx_t ctx);
711 static void iflib_free_intr_mem(if_ctx_t ctx);
712 #ifndef __NO_STRICT_ALIGNMENT
713 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
716 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
717 SLIST_HEAD_INITIALIZER(cpu_offsets);
719 SLIST_ENTRY(cpu_offset) entries;
721 unsigned int refcount;
724 static struct mtx cpu_offset_mtx;
725 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
728 NETDUMP_DEFINE(iflib);
731 #include <sys/selinfo.h>
732 #include <net/netmap.h>
733 #include <dev/netmap/netmap_kern.h>
735 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
740 * device-specific sysctl variables:
742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
743 * During regular operations the CRC is stripped, but on some
744 * hardware reception of frames not multiple of 64 is slower,
745 * so using crcstrip=0 helps in benchmarks.
747 * iflib_rx_miss, iflib_rx_miss_bufs:
748 * count packets that might be missed due to lost interrupts.
750 SYSCTL_DECL(_dev_netmap);
752 * The xl driver by default strips CRCs and we do not override it.
755 int iflib_crcstrip = 1;
756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
759 int iflib_rx_miss, iflib_rx_miss_bufs;
760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
766 * Register/unregister. We are already under netmap lock.
767 * Only called on the first register or the last unregister.
770 iflib_netmap_register(struct netmap_adapter *na, int onoff)
773 if_ctx_t ctx = ifp->if_softc;
777 IFDI_INTR_DISABLE(ctx);
779 /* Tell the stack that the interface is no longer active */
780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
785 /* enable or disable flags and callbacks in na and ifp */
787 nm_set_native_flags(na);
789 nm_clear_native_flags(na);
792 iflib_init_locked(ctx);
793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
796 nm_clear_native_flags(na);
802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
804 struct netmap_adapter *na = kring->na;
805 u_int const lim = kring->nkr_num_slots - 1;
806 u_int head = kring->rhead;
807 struct netmap_ring *ring = kring->ring;
809 struct if_rxd_update iru;
810 if_ctx_t ctx = rxq->ifr_ctx;
811 iflib_fl_t fl = &rxq->ifr_fl[0];
812 uint32_t refill_pidx, nic_i;
813 #if IFLIB_DEBUG_COUNTERS
817 if (nm_i == head && __predict_true(!init))
819 iru_init(&iru, rxq, 0 /* flid */);
820 map = fl->ifl_sds.ifsd_map;
821 refill_pidx = netmap_idx_k2n(kring, nm_i);
823 * IMPORTANT: we must leave one free slot in the ring,
824 * so move head back by one unit
826 head = nm_prev(head, lim);
828 DBG_COUNTER_INC(fl_refills);
829 while (nm_i != head) {
830 #if IFLIB_DEBUG_COUNTERS
832 DBG_COUNTER_INC(fl_refills_large);
834 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
835 struct netmap_slot *slot = &ring->slot[nm_i];
836 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
837 uint32_t nic_i_dma = refill_pidx;
838 nic_i = netmap_idx_k2n(kring, nm_i);
840 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
842 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
843 return netmap_ring_reinit(kring);
845 fl->ifl_vm_addrs[tmp_pidx] = addr;
846 if (__predict_false(init)) {
847 netmap_load_map(na, fl->ifl_buf_tag,
849 } else if (slot->flags & NS_BUF_CHANGED) {
850 /* buffer has changed, reload map */
851 netmap_reload_map(na, fl->ifl_buf_tag,
854 slot->flags &= ~NS_BUF_CHANGED;
856 nm_i = nm_next(nm_i, lim);
857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
861 iru.iru_pidx = refill_pidx;
862 iru.iru_count = tmp_pidx+1;
863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
865 for (int n = 0; n < iru.iru_count; n++) {
866 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
867 BUS_DMASYNC_PREREAD);
868 /* XXX - change this to not use the netmap func*/
869 nic_i_dma = nm_next(nic_i_dma, lim);
873 kring->nr_hwcur = head;
875 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
877 if (__predict_true(nic_i != UINT_MAX)) {
878 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
879 DBG_COUNTER_INC(rxd_flush);
885 * Reconcile kernel and user view of the transmit ring.
887 * All information is in the kring.
888 * Userspace wants to send packets up to the one before kring->rhead,
889 * kernel knows kring->nr_hwcur is the first unsent packet.
891 * Here we push packets out (as many as possible), and possibly
892 * reclaim buffers from previously completed transmission.
894 * The caller (netmap) guarantees that there is only one instance
895 * running at any time. Any interference with other driver
896 * methods should be handled by the individual drivers.
899 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
901 struct netmap_adapter *na = kring->na;
903 struct netmap_ring *ring = kring->ring;
904 u_int nm_i; /* index into the netmap kring */
905 u_int nic_i; /* index into the NIC ring */
907 u_int const lim = kring->nkr_num_slots - 1;
908 u_int const head = kring->rhead;
909 struct if_pkt_info pi;
912 * interrupts on every tx packet are expensive so request
913 * them every half ring, or where NS_REPORT is set
915 u_int report_frequency = kring->nkr_num_slots >> 1;
916 /* device-specific */
917 if_ctx_t ctx = ifp->if_softc;
918 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
920 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
924 * First part: process new packets to send.
925 * nm_i is the current index in the netmap kring,
926 * nic_i is the corresponding index in the NIC ring.
928 * If we have packets to send (nm_i != head)
929 * iterate over the netmap ring, fetch length and update
930 * the corresponding slot in the NIC ring. Some drivers also
931 * need to update the buffer's physical address in the NIC slot
932 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
934 * The netmap_reload_map() calls is especially expensive,
935 * even when (as in this case) the tag is 0, so do only
936 * when the buffer has actually changed.
938 * If possible do not set the report/intr bit on all slots,
939 * but only a few times per ring or when NS_REPORT is set.
941 * Finally, on 10G and faster drivers, it might be useful
942 * to prefetch the next slot and txr entry.
945 nm_i = kring->nr_hwcur;
946 if (nm_i != head) { /* we have new packets to send */
948 pi.ipi_segs = txq->ift_segs;
949 pi.ipi_qsidx = kring->ring_id;
950 nic_i = netmap_idx_k2n(kring, nm_i);
952 __builtin_prefetch(&ring->slot[nm_i]);
953 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
954 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
956 for (n = 0; nm_i != head; n++) {
957 struct netmap_slot *slot = &ring->slot[nm_i];
958 u_int len = slot->len;
960 void *addr = PNMB(na, slot, &paddr);
961 int flags = (slot->flags & NS_REPORT ||
962 nic_i == 0 || nic_i == report_frequency) ?
965 /* device-specific */
967 pi.ipi_segs[0].ds_addr = paddr;
968 pi.ipi_segs[0].ds_len = len;
972 pi.ipi_flags = flags;
974 /* Fill the slot in the NIC ring. */
975 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
976 DBG_COUNTER_INC(tx_encap);
978 /* prefetch for next round */
979 __builtin_prefetch(&ring->slot[nm_i + 1]);
980 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
981 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
983 NM_CHECK_ADDR_LEN(na, addr, len);
985 if (slot->flags & NS_BUF_CHANGED) {
986 /* buffer has changed, reload map */
987 netmap_reload_map(na, txq->ift_buf_tag,
988 txq->ift_sds.ifsd_map[nic_i], addr);
990 /* make sure changes to the buffer are synced */
991 bus_dmamap_sync(txq->ift_buf_tag,
992 txq->ift_sds.ifsd_map[nic_i],
993 BUS_DMASYNC_PREWRITE);
995 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
996 nm_i = nm_next(nm_i, lim);
997 nic_i = nm_next(nic_i, lim);
999 kring->nr_hwcur = nm_i;
1001 /* synchronize the NIC ring */
1002 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1003 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1005 /* (re)start the tx unit up to slot nic_i (excluded) */
1006 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1010 * Second part: reclaim buffers for completed transmissions.
1012 * If there are unclaimed buffers, attempt to reclaim them.
1013 * If none are reclaimed, and TX IRQs are not in use, do an initial
1014 * minimal delay, then trigger the tx handler which will spin in the
1017 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1018 if (iflib_tx_credits_update(ctx, txq)) {
1019 /* some tx completed, increment avail */
1020 nic_i = txq->ift_cidx_processed;
1021 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1024 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1026 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1027 iflib_timer, txq, txq->ift_timer.c_cpu);
1033 * Reconcile kernel and user view of the receive ring.
1034 * Same as for the txsync, this routine must be efficient.
1035 * The caller guarantees a single invocations, but races against
1036 * the rest of the driver should be handled here.
1038 * On call, kring->rhead is the first packet that userspace wants
1039 * to keep, and kring->rcur is the wakeup point.
1040 * The kernel has previously reported packets up to kring->rtail.
1042 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1043 * of whether or not we received an interrupt.
1046 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1048 struct netmap_adapter *na = kring->na;
1049 struct netmap_ring *ring = kring->ring;
1052 uint32_t nm_i; /* index into the netmap ring */
1053 uint32_t nic_i; /* index into the NIC ring */
1055 u_int const lim = kring->nkr_num_slots - 1;
1056 u_int const head = kring->rhead;
1057 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1058 struct if_rxd_info ri;
1060 if_ctx_t ctx = ifp->if_softc;
1061 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1063 return netmap_ring_reinit(kring);
1066 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1069 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1075 * First part: import newly received packets.
1077 * nm_i is the index of the next free slot in the netmap ring,
1078 * nic_i is the index of the next received packet in the NIC ring,
1079 * and they may differ in case if_init() has been called while
1080 * in netmap mode. For the receive ring we have
1082 * nic_i = rxr->next_check;
1083 * nm_i = kring->nr_hwtail (previous)
1085 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1087 * rxr->next_check is set to 0 on a ring reinit
1089 if (netmap_no_pendintr || force_update) {
1090 int crclen = iflib_crcstrip ? 0 : 4;
1093 for (i = 0; i < rxq->ifr_nfl; i++) {
1094 fl = &rxq->ifr_fl[i];
1095 nic_i = fl->ifl_cidx;
1096 nm_i = netmap_idx_n2k(kring, nic_i);
1097 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1098 rxq->ifr_id, nic_i, USHRT_MAX);
1099 for (n = 0; avail > 0; n++, avail--) {
1101 ri.iri_frags = rxq->ifr_frags;
1102 ri.iri_qsidx = kring->ring_id;
1103 ri.iri_ifp = ctx->ifc_ifp;
1104 ri.iri_cidx = nic_i;
1106 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1107 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1108 ring->slot[nm_i].flags = 0;
1109 bus_dmamap_sync(fl->ifl_buf_tag,
1110 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1111 nm_i = nm_next(nm_i, lim);
1112 nic_i = nm_next(nic_i, lim);
1114 if (n) { /* update the state variables */
1115 if (netmap_no_pendintr && !force_update) {
1118 iflib_rx_miss_bufs += n;
1120 fl->ifl_cidx = nic_i;
1121 kring->nr_hwtail = nm_i;
1123 kring->nr_kflags &= ~NKR_PENDINTR;
1127 * Second part: skip past packets that userspace has released.
1128 * (kring->nr_hwcur to head excluded),
1129 * and make the buffers available for reception.
1130 * As usual nm_i is the index in the netmap ring,
1131 * nic_i is the index in the NIC ring, and
1132 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1134 /* XXX not sure how this will work with multiple free lists */
1135 nm_i = kring->nr_hwcur;
1137 return (netmap_fl_refill(rxq, kring, nm_i, false));
1141 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1143 if_ctx_t ctx = na->ifp->if_softc;
1147 IFDI_INTR_ENABLE(ctx);
1149 IFDI_INTR_DISABLE(ctx);
1156 iflib_netmap_attach(if_ctx_t ctx)
1158 struct netmap_adapter na;
1159 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1161 bzero(&na, sizeof(na));
1163 na.ifp = ctx->ifc_ifp;
1164 na.na_flags = NAF_BDG_MAYSLEEP;
1165 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1166 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1168 na.num_tx_desc = scctx->isc_ntxd[0];
1169 na.num_rx_desc = scctx->isc_nrxd[0];
1170 na.nm_txsync = iflib_netmap_txsync;
1171 na.nm_rxsync = iflib_netmap_rxsync;
1172 na.nm_register = iflib_netmap_register;
1173 na.nm_intr = iflib_netmap_intr;
1174 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1175 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1176 return (netmap_attach(&na));
1180 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1182 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1183 struct netmap_slot *slot;
1185 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1188 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1191 * In netmap mode, set the map for the packet buffer.
1192 * NOTE: Some drivers (not this one) also need to set
1193 * the physical buffer address in the NIC ring.
1194 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1195 * netmap slot index, si
1197 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1198 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1199 NMB(na, slot + si));
1204 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1206 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1207 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1208 struct netmap_slot *slot;
1211 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1214 nm_i = netmap_idx_n2k(kring, 0);
1215 netmap_fl_refill(rxq, kring, nm_i, true);
1219 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1221 struct netmap_kring *kring;
1224 txqid = txq->ift_id;
1225 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1227 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1228 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1229 BUS_DMASYNC_POSTREAD);
1230 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1231 netmap_tx_irq(ctx->ifc_ifp, txqid);
1232 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1236 *reset_on = hz / 1000;
1241 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1244 #define iflib_netmap_txq_init(ctx, txq)
1245 #define iflib_netmap_rxq_init(ctx, rxq)
1246 #define iflib_netmap_detach(ifp)
1248 #define iflib_netmap_attach(ctx) (0)
1249 #define netmap_rx_irq(ifp, qid, budget) (0)
1250 #define netmap_tx_irq(ifp, qid) do {} while (0)
1251 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1254 #if defined(__i386__) || defined(__amd64__)
1255 static __inline void
1258 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1260 static __inline void
1261 prefetch2cachelines(void *x)
1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1264 #if (CACHE_LINE_SIZE < 128)
1265 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1270 #define prefetch2cachelines(x)
1274 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1278 fl = &rxq->ifr_fl[flid];
1279 iru->iru_paddrs = fl->ifl_bus_addrs;
1280 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1281 iru->iru_idxs = fl->ifl_rxd_idxs;
1282 iru->iru_qsidx = rxq->ifr_id;
1283 iru->iru_buf_size = fl->ifl_buf_size;
1284 iru->iru_flidx = fl->ifl_id;
1288 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1292 *(bus_addr_t *) arg = segs[0].ds_addr;
1296 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1299 device_t dev = ctx->ifc_dev;
1301 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1302 align, 0, /* alignment, bounds */
1303 BUS_SPACE_MAXADDR, /* lowaddr */
1304 BUS_SPACE_MAXADDR, /* highaddr */
1305 NULL, NULL, /* filter, filterarg */
1308 size, /* maxsegsize */
1309 BUS_DMA_ALLOCNOW, /* flags */
1310 NULL, /* lockfunc */
1315 "%s: bus_dma_tag_create failed: %d\n",
1320 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1321 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1324 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1325 __func__, (uintmax_t)size, err);
1329 dma->idi_paddr = IF_BAD_DMA;
1330 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1331 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1332 if (err || dma->idi_paddr == IF_BAD_DMA) {
1334 "%s: bus_dmamap_load failed: %d\n",
1339 dma->idi_size = size;
1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1345 bus_dma_tag_destroy(dma->idi_tag);
1347 dma->idi_tag = NULL;
1353 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1355 if_shared_ctx_t sctx = ctx->ifc_sctx;
1357 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1359 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1363 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1366 iflib_dma_info_t *dmaiter;
1369 for (i = 0; i < count; i++, dmaiter++) {
1370 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1374 iflib_dma_free_multi(dmalist, i);
1379 iflib_dma_free(iflib_dma_info_t dma)
1381 if (dma->idi_tag == NULL)
1383 if (dma->idi_paddr != IF_BAD_DMA) {
1384 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1385 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1386 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1387 dma->idi_paddr = IF_BAD_DMA;
1389 if (dma->idi_vaddr != NULL) {
1390 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1391 dma->idi_vaddr = NULL;
1393 bus_dma_tag_destroy(dma->idi_tag);
1394 dma->idi_tag = NULL;
1398 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1401 iflib_dma_info_t *dmaiter = dmalist;
1403 for (i = 0; i < count; i++, dmaiter++)
1404 iflib_dma_free(*dmaiter);
1407 #ifdef EARLY_AP_STARTUP
1408 static const int iflib_started = 1;
1411 * We used to abuse the smp_started flag to decide if the queues have been
1412 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1413 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1414 * is set. Run a SYSINIT() strictly after that to just set a usable
1418 static int iflib_started;
1421 iflib_record_started(void *arg)
1426 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1427 iflib_record_started, NULL);
1431 iflib_fast_intr(void *arg)
1433 iflib_filter_info_t info = arg;
1434 struct grouptask *gtask = info->ifi_task;
1438 return (FILTER_STRAY);
1440 DBG_COUNTER_INC(fast_intrs);
1441 if (info->ifi_filter != NULL) {
1442 result = info->ifi_filter(info->ifi_filter_arg);
1443 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1447 GROUPTASK_ENQUEUE(gtask);
1448 return (FILTER_HANDLED);
1452 iflib_fast_intr_rxtx(void *arg)
1454 iflib_filter_info_t info = arg;
1455 struct grouptask *gtask = info->ifi_task;
1457 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1460 int i, cidx, result;
1462 bool intr_enable, intr_legacy;
1465 return (FILTER_STRAY);
1467 DBG_COUNTER_INC(fast_intrs);
1468 if (info->ifi_filter != NULL) {
1469 result = info->ifi_filter(info->ifi_filter_arg);
1470 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1475 sc = ctx->ifc_softc;
1476 intr_enable = false;
1477 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1478 MPASS(rxq->ifr_ntxqirq);
1479 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1480 txqid = rxq->ifr_txqid[i];
1481 txq = &ctx->ifc_txqs[txqid];
1482 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1483 BUS_DMASYNC_POSTREAD);
1484 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1488 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1491 GROUPTASK_ENQUEUE(&txq->ift_task);
1493 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1494 cidx = rxq->ifr_cq_cidx;
1496 cidx = rxq->ifr_fl[0].ifl_cidx;
1497 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1498 GROUPTASK_ENQUEUE(gtask);
1503 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1504 DBG_COUNTER_INC(rx_intr_enables);
1507 IFDI_INTR_ENABLE(ctx);
1508 return (FILTER_HANDLED);
1513 iflib_fast_intr_ctx(void *arg)
1515 iflib_filter_info_t info = arg;
1516 struct grouptask *gtask = info->ifi_task;
1520 return (FILTER_STRAY);
1522 DBG_COUNTER_INC(fast_intrs);
1523 if (info->ifi_filter != NULL) {
1524 result = info->ifi_filter(info->ifi_filter_arg);
1525 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1529 GROUPTASK_ENQUEUE(gtask);
1530 return (FILTER_HANDLED);
1534 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1535 driver_filter_t filter, driver_intr_t handler, void *arg,
1538 struct resource *res;
1540 device_t dev = ctx->ifc_dev;
1544 if (ctx->ifc_flags & IFC_LEGACY)
1545 flags |= RF_SHAREABLE;
1548 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1551 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1555 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1556 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1557 filter, handler, arg, &tag);
1560 "failed to setup interrupt for rid %d, name %s: %d\n",
1561 rid, name ? name : "unknown", rc);
1564 bus_describe_intr(dev, res, tag, "%s", name);
1570 /*********************************************************************
1572 * Allocate DMA resources for TX buffers as well as memory for the TX
1573 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1574 * iflib_sw_tx_desc_array structure, storing all the information that
1575 * is needed to transmit a packet on the wire. This is called only
1576 * once at attach, setup is done every reset.
1578 **********************************************************************/
1580 iflib_txsd_alloc(iflib_txq_t txq)
1582 if_ctx_t ctx = txq->ift_ctx;
1583 if_shared_ctx_t sctx = ctx->ifc_sctx;
1584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1585 device_t dev = ctx->ifc_dev;
1586 bus_size_t tsomaxsize;
1587 int err, nsegments, ntsosegments;
1590 nsegments = scctx->isc_tx_nsegments;
1591 ntsosegments = scctx->isc_tx_tso_segments_max;
1592 tsomaxsize = scctx->isc_tx_tso_size_max;
1593 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1594 tsomaxsize += sizeof(struct ether_vlan_header);
1595 MPASS(scctx->isc_ntxd[0] > 0);
1596 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1597 MPASS(nsegments > 0);
1598 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1599 MPASS(ntsosegments > 0);
1600 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1604 * Set up DMA tags for TX buffers.
1606 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1607 1, 0, /* alignment, bounds */
1608 BUS_SPACE_MAXADDR, /* lowaddr */
1609 BUS_SPACE_MAXADDR, /* highaddr */
1610 NULL, NULL, /* filter, filterarg */
1611 sctx->isc_tx_maxsize, /* maxsize */
1612 nsegments, /* nsegments */
1613 sctx->isc_tx_maxsegsize, /* maxsegsize */
1615 NULL, /* lockfunc */
1616 NULL, /* lockfuncarg */
1617 &txq->ift_buf_tag))) {
1618 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1619 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1620 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1623 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1624 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1625 1, 0, /* alignment, bounds */
1626 BUS_SPACE_MAXADDR, /* lowaddr */
1627 BUS_SPACE_MAXADDR, /* highaddr */
1628 NULL, NULL, /* filter, filterarg */
1629 tsomaxsize, /* maxsize */
1630 ntsosegments, /* nsegments */
1631 sctx->isc_tso_maxsegsize,/* maxsegsize */
1633 NULL, /* lockfunc */
1634 NULL, /* lockfuncarg */
1635 &txq->ift_tso_buf_tag))) {
1636 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1641 /* Allocate memory for the TX mbuf map. */
1642 if (!(txq->ift_sds.ifsd_m =
1643 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1644 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1645 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1651 * Create the DMA maps for TX buffers.
1653 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1654 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1655 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1657 "Unable to allocate TX buffer DMA map memory\n");
1661 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1662 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1663 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1665 "Unable to allocate TSO TX buffer map memory\n");
1669 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1670 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1671 &txq->ift_sds.ifsd_map[i]);
1673 device_printf(dev, "Unable to create TX DMA map\n");
1678 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1679 &txq->ift_sds.ifsd_tso_map[i]);
1681 device_printf(dev, "Unable to create TSO TX DMA map\n");
1687 /* We free all, it handles case where we are in the middle */
1688 iflib_tx_structures_free(ctx);
1693 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1698 if (txq->ift_sds.ifsd_map != NULL)
1699 map = txq->ift_sds.ifsd_map[i];
1701 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1702 bus_dmamap_unload(txq->ift_buf_tag, map);
1703 bus_dmamap_destroy(txq->ift_buf_tag, map);
1704 txq->ift_sds.ifsd_map[i] = NULL;
1708 if (txq->ift_sds.ifsd_tso_map != NULL)
1709 map = txq->ift_sds.ifsd_tso_map[i];
1711 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1712 BUS_DMASYNC_POSTWRITE);
1713 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1714 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1715 txq->ift_sds.ifsd_tso_map[i] = NULL;
1720 iflib_txq_destroy(iflib_txq_t txq)
1722 if_ctx_t ctx = txq->ift_ctx;
1724 for (int i = 0; i < txq->ift_size; i++)
1725 iflib_txsd_destroy(ctx, txq, i);
1726 if (txq->ift_sds.ifsd_map != NULL) {
1727 free(txq->ift_sds.ifsd_map, M_IFLIB);
1728 txq->ift_sds.ifsd_map = NULL;
1730 if (txq->ift_sds.ifsd_tso_map != NULL) {
1731 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1732 txq->ift_sds.ifsd_tso_map = NULL;
1734 if (txq->ift_sds.ifsd_m != NULL) {
1735 free(txq->ift_sds.ifsd_m, M_IFLIB);
1736 txq->ift_sds.ifsd_m = NULL;
1738 if (txq->ift_buf_tag != NULL) {
1739 bus_dma_tag_destroy(txq->ift_buf_tag);
1740 txq->ift_buf_tag = NULL;
1742 if (txq->ift_tso_buf_tag != NULL) {
1743 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1744 txq->ift_tso_buf_tag = NULL;
1749 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1753 mp = &txq->ift_sds.ifsd_m[i];
1757 if (txq->ift_sds.ifsd_map != NULL) {
1758 bus_dmamap_sync(txq->ift_buf_tag,
1759 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1760 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1762 if (txq->ift_sds.ifsd_tso_map != NULL) {
1763 bus_dmamap_sync(txq->ift_tso_buf_tag,
1764 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1765 bus_dmamap_unload(txq->ift_tso_buf_tag,
1766 txq->ift_sds.ifsd_tso_map[i]);
1769 DBG_COUNTER_INC(tx_frees);
1774 iflib_txq_setup(iflib_txq_t txq)
1776 if_ctx_t ctx = txq->ift_ctx;
1777 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1778 if_shared_ctx_t sctx = ctx->ifc_sctx;
1779 iflib_dma_info_t di;
1782 /* Set number of descriptors available */
1783 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1784 /* XXX make configurable */
1785 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1788 txq->ift_cidx_processed = 0;
1789 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1790 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1792 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1793 bzero((void *)di->idi_vaddr, di->idi_size);
1795 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1796 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1797 bus_dmamap_sync(di->idi_tag, di->idi_map,
1798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1802 /*********************************************************************
1804 * Allocate DMA resources for RX buffers as well as memory for the RX
1805 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1806 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1807 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1808 * Since we use use one entry in iflib_sw_rx_desc_array per received
1809 * packet, the maximum number of entries we'll need is equal to the
1810 * number of hardware receive descriptors that we've allocated.
1812 **********************************************************************/
1814 iflib_rxsd_alloc(iflib_rxq_t rxq)
1816 if_ctx_t ctx = rxq->ifr_ctx;
1817 if_shared_ctx_t sctx = ctx->ifc_sctx;
1818 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1819 device_t dev = ctx->ifc_dev;
1823 MPASS(scctx->isc_nrxd[0] > 0);
1824 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1827 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1828 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1829 /* Set up DMA tag for RX buffers. */
1830 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1831 1, 0, /* alignment, bounds */
1832 BUS_SPACE_MAXADDR, /* lowaddr */
1833 BUS_SPACE_MAXADDR, /* highaddr */
1834 NULL, NULL, /* filter, filterarg */
1835 sctx->isc_rx_maxsize, /* maxsize */
1836 sctx->isc_rx_nsegments, /* nsegments */
1837 sctx->isc_rx_maxsegsize, /* maxsegsize */
1839 NULL, /* lockfunc */
1844 "Unable to allocate RX DMA tag: %d\n", err);
1848 /* Allocate memory for the RX mbuf map. */
1849 if (!(fl->ifl_sds.ifsd_m =
1850 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1851 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1853 "Unable to allocate RX mbuf map memory\n");
1858 /* Allocate memory for the direct RX cluster pointer map. */
1859 if (!(fl->ifl_sds.ifsd_cl =
1860 (caddr_t *) malloc(sizeof(caddr_t) *
1861 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1863 "Unable to allocate RX cluster map memory\n");
1868 /* Allocate memory for the RX cluster bus address map. */
1869 if (!(fl->ifl_sds.ifsd_ba =
1870 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1871 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1873 "Unable to allocate RX bus address map memory\n");
1879 * Create the DMA maps for RX buffers.
1881 if (!(fl->ifl_sds.ifsd_map =
1882 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1884 "Unable to allocate RX buffer DMA map memory\n");
1888 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1889 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1890 &fl->ifl_sds.ifsd_map[i]);
1892 device_printf(dev, "Unable to create RX buffer DMA map\n");
1900 iflib_rx_structures_free(ctx);
1906 * Internal service routines
1909 struct rxq_refill_cb_arg {
1911 bus_dma_segment_t seg;
1916 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1918 struct rxq_refill_cb_arg *cb_arg = arg;
1920 cb_arg->error = error;
1921 cb_arg->seg = segs[0];
1922 cb_arg->nseg = nseg;
1926 * _iflib_fl_refill - refill an rxq free-buffer list
1927 * @ctx: the iflib context
1928 * @fl: the free list to refill
1929 * @count: the number of new buffers to allocate
1931 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1932 * The caller must assure that @count does not exceed the queue's capacity.
1935 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1937 struct if_rxd_update iru;
1938 struct rxq_refill_cb_arg cb_arg;
1942 bus_dmamap_t *sd_map;
1943 bus_addr_t bus_addr, *sd_ba;
1944 int err, frag_idx, i, idx, n, pidx;
1947 sd_m = fl->ifl_sds.ifsd_m;
1948 sd_map = fl->ifl_sds.ifsd_map;
1949 sd_cl = fl->ifl_sds.ifsd_cl;
1950 sd_ba = fl->ifl_sds.ifsd_ba;
1951 pidx = fl->ifl_pidx;
1953 frag_idx = fl->ifl_fragidx;
1954 credits = fl->ifl_credits;
1959 MPASS(credits + n <= fl->ifl_size);
1961 if (pidx < fl->ifl_cidx)
1962 MPASS(pidx + n <= fl->ifl_cidx);
1963 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1964 MPASS(fl->ifl_gen == 0);
1965 if (pidx > fl->ifl_cidx)
1966 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1968 DBG_COUNTER_INC(fl_refills);
1970 DBG_COUNTER_INC(fl_refills_large);
1971 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1974 * We allocate an uninitialized mbuf + cluster, mbuf is
1975 * initialized after rx.
1977 * If the cluster is still set then we know a minimum sized packet was received
1979 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1982 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1983 MPASS(frag_idx >= 0);
1984 if ((cl = sd_cl[frag_idx]) == NULL) {
1985 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1989 MPASS(sd_map != NULL);
1990 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1991 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1993 if (err != 0 || cb_arg.error) {
1997 if (fl->ifl_zone == zone_pack)
1998 uma_zfree(fl->ifl_zone, cl);
2002 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2003 sd_cl[frag_idx] = cl;
2005 fl->ifl_cl_enqueued++;
2008 bus_addr = sd_ba[frag_idx];
2010 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2011 BUS_DMASYNC_PREREAD);
2013 if (sd_m[frag_idx] == NULL) {
2014 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2019 bit_set(fl->ifl_rx_bitmap, frag_idx);
2021 fl->ifl_m_enqueued++;
2024 DBG_COUNTER_INC(rx_allocs);
2025 fl->ifl_rxd_idxs[i] = frag_idx;
2026 fl->ifl_bus_addrs[i] = bus_addr;
2027 fl->ifl_vm_addrs[i] = cl;
2030 MPASS(credits <= fl->ifl_size);
2031 if (++idx == fl->ifl_size) {
2035 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2036 iru.iru_pidx = pidx;
2038 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2042 fl->ifl_credits = credits;
2047 iru.iru_pidx = pidx;
2049 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2051 fl->ifl_credits = credits;
2053 DBG_COUNTER_INC(rxd_flush);
2054 if (fl->ifl_pidx == 0)
2055 pidx = fl->ifl_size - 1;
2057 pidx = fl->ifl_pidx - 1;
2059 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2060 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2061 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2062 fl->ifl_fragidx = frag_idx;
2065 static __inline void
2066 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2068 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2069 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2071 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2074 MPASS(fl->ifl_credits <= fl->ifl_size);
2075 MPASS(reclaimable == delta);
2077 if (reclaimable > 0)
2078 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2082 iflib_in_detach(if_ctx_t ctx)
2087 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2093 iflib_fl_bufs_free(iflib_fl_t fl)
2095 iflib_dma_info_t idi = fl->ifl_ifdi;
2096 bus_dmamap_t sd_map;
2099 for (i = 0; i < fl->ifl_size; i++) {
2100 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2101 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2103 if (*sd_cl != NULL) {
2104 sd_map = fl->ifl_sds.ifsd_map[i];
2105 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2106 BUS_DMASYNC_POSTREAD);
2107 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2109 uma_zfree(fl->ifl_zone, *sd_cl);
2110 // XXX: Should this get moved out?
2111 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2112 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2113 if (*sd_m != NULL) {
2114 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2115 uma_zfree(zone_mbuf, *sd_m);
2118 MPASS(*sd_cl == NULL);
2119 MPASS(*sd_m == NULL);
2122 fl->ifl_m_dequeued++;
2123 fl->ifl_cl_dequeued++;
2129 for (i = 0; i < fl->ifl_size; i++) {
2130 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2131 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2135 * Reset free list values
2137 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2138 bzero(idi->idi_vaddr, idi->idi_size);
2141 /*********************************************************************
2143 * Initialize a free list and its buffers.
2145 **********************************************************************/
2147 iflib_fl_setup(iflib_fl_t fl)
2149 iflib_rxq_t rxq = fl->ifl_rxq;
2150 if_ctx_t ctx = rxq->ifr_ctx;
2152 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2154 ** Free current RX buffer structs and their mbufs
2156 iflib_fl_bufs_free(fl);
2157 /* Now replenish the mbufs */
2158 MPASS(fl->ifl_credits == 0);
2159 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2160 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2161 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2162 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2163 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2166 /* avoid pre-allocating zillions of clusters to an idle card
2167 * potentially speeding up attach
2169 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2170 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2171 if (min(128, fl->ifl_size) != fl->ifl_credits)
2177 MPASS(fl->ifl_ifdi != NULL);
2178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2183 /*********************************************************************
2185 * Free receive ring data structures
2187 **********************************************************************/
2189 iflib_rx_sds_free(iflib_rxq_t rxq)
2194 if (rxq->ifr_fl != NULL) {
2195 for (i = 0; i < rxq->ifr_nfl; i++) {
2196 fl = &rxq->ifr_fl[i];
2197 if (fl->ifl_buf_tag != NULL) {
2198 if (fl->ifl_sds.ifsd_map != NULL) {
2199 for (j = 0; j < fl->ifl_size; j++) {
2200 if (fl->ifl_sds.ifsd_map[j] ==
2205 fl->ifl_sds.ifsd_map[j],
2206 BUS_DMASYNC_POSTREAD);
2209 fl->ifl_sds.ifsd_map[j]);
2212 bus_dma_tag_destroy(fl->ifl_buf_tag);
2213 fl->ifl_buf_tag = NULL;
2215 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2216 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2217 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2218 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2219 fl->ifl_sds.ifsd_m = NULL;
2220 fl->ifl_sds.ifsd_cl = NULL;
2221 fl->ifl_sds.ifsd_ba = NULL;
2222 fl->ifl_sds.ifsd_map = NULL;
2224 free(rxq->ifr_fl, M_IFLIB);
2226 rxq->ifr_cq_cidx = 0;
2234 iflib_timer(void *arg)
2236 iflib_txq_t txq = arg;
2237 if_ctx_t ctx = txq->ift_ctx;
2238 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2239 uint64_t this_tick = ticks;
2240 uint32_t reset_on = hz / 2;
2242 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2246 ** Check on the state of the TX queue(s), this
2247 ** can be done without the lock because its RO
2248 ** and the HUNG state will be static if set.
2250 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2251 txq->ift_last_timer_tick = this_tick;
2252 IFDI_TIMER(ctx, txq->ift_id);
2253 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2254 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2255 (sctx->isc_pause_frames == 0)))
2258 if (ifmp_ring_is_stalled(txq->ift_br))
2259 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2260 txq->ift_cleaned_prev = txq->ift_cleaned;
2263 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2264 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2266 /* handle any laggards */
2267 if (txq->ift_db_pending)
2268 GROUPTASK_ENQUEUE(&txq->ift_task);
2270 sctx->isc_pause_frames = 0;
2271 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2272 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2276 device_printf(ctx->ifc_dev,
2277 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2278 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2280 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2281 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2282 iflib_admin_intr_deferred(ctx);
2287 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2289 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2292 * XXX don't set the max_frame_size to larger
2293 * than the hardware can handle
2295 if (sctx->isc_max_frame_size <= MCLBYTES)
2296 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2298 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2302 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2305 return (ctx->ifc_rx_mbuf_sz);
2309 iflib_init_locked(if_ctx_t ctx)
2311 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2312 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2313 if_t ifp = ctx->ifc_ifp;
2317 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2319 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2320 IFDI_INTR_DISABLE(ctx);
2322 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2323 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2324 /* Set hardware offload abilities */
2325 if_clearhwassist(ifp);
2326 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2327 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2328 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2329 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2330 if (if_getcapenable(ifp) & IFCAP_TSO4)
2331 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2332 if (if_getcapenable(ifp) & IFCAP_TSO6)
2333 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2335 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2337 callout_stop(&txq->ift_timer);
2338 CALLOUT_UNLOCK(txq);
2339 iflib_netmap_txq_init(ctx, txq);
2343 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2344 * that drivers can use the value when setting up the hardware receive
2347 iflib_calc_rx_mbuf_sz(ctx);
2350 i = if_getdrvflags(ifp);
2353 MPASS(if_getdrvflags(ifp) == i);
2354 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2355 /* XXX this should really be done on a per-queue basis */
2356 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2357 MPASS(rxq->ifr_id == i);
2358 iflib_netmap_rxq_init(ctx, rxq);
2361 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2362 if (iflib_fl_setup(fl)) {
2363 device_printf(ctx->ifc_dev,
2364 "setting up free list %d failed - "
2365 "check cluster settings\n", j);
2371 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2372 IFDI_INTR_ENABLE(ctx);
2373 txq = ctx->ifc_txqs;
2374 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2375 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2376 txq->ift_timer.c_cpu);
2380 iflib_media_change(if_t ifp)
2382 if_ctx_t ctx = if_getsoftc(ifp);
2386 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2387 iflib_init_locked(ctx);
2393 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2395 if_ctx_t ctx = if_getsoftc(ifp);
2398 IFDI_UPDATE_ADMIN_STATUS(ctx);
2399 IFDI_MEDIA_STATUS(ctx, ifmr);
2404 iflib_stop(if_ctx_t ctx)
2406 iflib_txq_t txq = ctx->ifc_txqs;
2407 iflib_rxq_t rxq = ctx->ifc_rxqs;
2408 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2409 if_shared_ctx_t sctx = ctx->ifc_sctx;
2410 iflib_dma_info_t di;
2414 /* Tell the stack that the interface is no longer active */
2415 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2417 IFDI_INTR_DISABLE(ctx);
2422 iflib_debug_reset();
2423 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2424 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2425 /* make sure all transmitters have completed before proceeding XXX */
2428 callout_stop(&txq->ift_timer);
2429 CALLOUT_UNLOCK(txq);
2431 /* clean any enqueued buffers */
2432 iflib_ifmp_purge(txq);
2433 /* Free any existing tx buffers. */
2434 for (j = 0; j < txq->ift_size; j++) {
2435 iflib_txsd_free(ctx, txq, j);
2437 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2438 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2439 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2440 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2441 txq->ift_pullups = 0;
2442 ifmp_ring_reset_stats(txq->ift_br);
2443 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2444 bzero((void *)di->idi_vaddr, di->idi_size);
2446 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2447 /* make sure all transmitters have completed before proceeding XXX */
2449 rxq->ifr_cq_cidx = 0;
2450 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2451 bzero((void *)di->idi_vaddr, di->idi_size);
2452 /* also resets the free lists pidx/cidx */
2453 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2454 iflib_fl_bufs_free(fl);
2458 static inline caddr_t
2459 calc_next_rxd(iflib_fl_t fl, int cidx)
2463 caddr_t start, end, cur, next;
2465 nrxd = fl->ifl_size;
2466 size = fl->ifl_rxd_size;
2467 start = fl->ifl_ifdi->idi_vaddr;
2469 if (__predict_false(size == 0))
2471 cur = start + size*cidx;
2472 end = start + size*nrxd;
2473 next = CACHE_PTR_NEXT(cur);
2474 return (next < end ? next : start);
2478 prefetch_pkts(iflib_fl_t fl, int cidx)
2481 int nrxd = fl->ifl_size;
2485 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2486 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2487 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2488 next_rxd = calc_next_rxd(fl, cidx);
2490 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2491 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2494 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2495 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2500 static struct mbuf *
2501 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2502 int *pf_rv, if_rxd_info_t ri)
2508 int flid, cidx, len, next;
2511 flid = irf->irf_flid;
2512 cidx = irf->irf_idx;
2513 fl = &rxq->ifr_fl[flid];
2515 sd->ifsd_cidx = cidx;
2516 m = fl->ifl_sds.ifsd_m[cidx];
2517 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2520 fl->ifl_m_dequeued++;
2522 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2523 prefetch_pkts(fl, cidx);
2524 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2525 prefetch(&fl->ifl_sds.ifsd_map[next]);
2526 map = fl->ifl_sds.ifsd_map[cidx];
2527 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2529 /* not valid assert if bxe really does SGE from non-contiguous elements */
2530 MPASS(fl->ifl_cidx == cidx);
2531 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2533 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2534 payload = *sd->ifsd_cl;
2535 payload += ri->iri_pad;
2536 len = ri->iri_len - ri->iri_pad;
2537 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2538 len | PFIL_MEMPTR | PFIL_IN, NULL);
2543 * The filter ate it. Everything is recycled.
2548 case PFIL_REALLOCED:
2550 * The filter copied it. Everything is recycled.
2552 m = pfil_mem2mbuf(payload);
2557 * Filter said it was OK, so receive like
2560 fl->ifl_sds.ifsd_m[cidx] = NULL;
2566 fl->ifl_sds.ifsd_m[cidx] = NULL;
2571 bus_dmamap_unload(fl->ifl_buf_tag, map);
2572 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2573 if (__predict_false(fl->ifl_cidx == 0))
2575 bit_clear(fl->ifl_rx_bitmap, cidx);
2579 static struct mbuf *
2580 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2582 struct mbuf *m, *mh, *mt;
2584 int *pf_rv_ptr, flags, i, padlen;
2593 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2596 MPASS(*sd->ifsd_cl != NULL);
2599 * Exclude zero-length frags & frags from
2600 * packets the filter has consumed or dropped
2602 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2603 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2605 /* everything saved here */
2610 /* XXX we can save the cluster here, but not the mbuf */
2611 m_init(m, M_NOWAIT, MT_DATA, 0);
2616 flags = M_PKTHDR|M_EXT;
2618 padlen = ri->iri_pad;
2623 /* assuming padding is only on the first fragment */
2627 *sd->ifsd_cl = NULL;
2629 /* Can these two be made one ? */
2630 m_init(m, M_NOWAIT, MT_DATA, flags);
2631 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2633 * These must follow m_init and m_cljset
2635 m->m_data += padlen;
2636 ri->iri_len -= padlen;
2637 m->m_len = ri->iri_frags[i].irf_len;
2638 } while (++i < ri->iri_nfrags);
2644 * Process one software descriptor
2646 static struct mbuf *
2647 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2653 /* should I merge this back in now that the two paths are basically duplicated? */
2654 if (ri->iri_nfrags == 1 &&
2655 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2656 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2658 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2660 if (pf_rv == PFIL_PASS) {
2661 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2662 #ifndef __NO_STRICT_ALIGNMENT
2666 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2667 m->m_len = ri->iri_frags[0].irf_len;
2670 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2671 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2674 m->m_pkthdr.len = ri->iri_len;
2675 m->m_pkthdr.rcvif = ri->iri_ifp;
2676 m->m_flags |= ri->iri_flags;
2677 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2678 m->m_pkthdr.flowid = ri->iri_flowid;
2679 M_HASHTYPE_SET(m, ri->iri_rsstype);
2680 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2681 m->m_pkthdr.csum_data = ri->iri_csum_data;
2685 #if defined(INET6) || defined(INET)
2687 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2689 CURVNET_SET(lc->ifp->if_vnet);
2691 *v6 = V_ip6_forwarding;
2694 *v4 = V_ipforwarding;
2700 * Returns true if it's possible this packet could be LROed.
2701 * if it returns false, it is guaranteed that tcp_lro_rx()
2702 * would not return zero.
2705 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2707 struct ether_header *eh;
2709 eh = mtod(m, struct ether_header *);
2710 switch (eh->ether_type) {
2712 case htons(ETHERTYPE_IPV6):
2713 return (!v6_forwarding);
2716 case htons(ETHERTYPE_IP):
2717 return (!v4_forwarding);
2725 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2731 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2734 if_ctx_t ctx = rxq->ifr_ctx;
2735 if_shared_ctx_t sctx = ctx->ifc_sctx;
2736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2739 struct if_rxd_info ri;
2740 int err, budget_left, rx_bytes, rx_pkts;
2743 bool v4_forwarding, v6_forwarding, lro_possible;
2746 * XXX early demux data packets so that if_input processing only handles
2747 * acks in interrupt context
2749 struct mbuf *m, *mh, *mt, *mf;
2751 lro_possible = v4_forwarding = v6_forwarding = false;
2755 rx_pkts = rx_bytes = 0;
2756 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2757 cidxp = &rxq->ifr_cq_cidx;
2759 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2760 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2761 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2762 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2763 DBG_COUNTER_INC(rx_unavail);
2767 /* pfil needs the vnet to be set */
2768 CURVNET_SET_QUIET(ifp->if_vnet);
2769 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2770 if (__predict_false(!CTX_ACTIVE(ctx))) {
2771 DBG_COUNTER_INC(rx_ctx_inactive);
2775 * Reset client set fields to their default values
2778 ri.iri_qsidx = rxq->ifr_id;
2779 ri.iri_cidx = *cidxp;
2781 ri.iri_frags = rxq->ifr_frags;
2782 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2787 rx_bytes += ri.iri_len;
2788 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2789 *cidxp = ri.iri_cidx;
2790 /* Update our consumer index */
2791 /* XXX NB: shurd - check if this is still safe */
2792 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2793 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2794 /* was this only a completion queue message? */
2795 if (__predict_false(ri.iri_nfrags == 0))
2798 MPASS(ri.iri_nfrags != 0);
2799 MPASS(ri.iri_len != 0);
2801 /* will advance the cidx on the corresponding free lists */
2802 m = iflib_rxd_pkt_get(rxq, &ri);
2805 if (avail == 0 && budget_left)
2806 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2808 if (__predict_false(m == NULL))
2811 /* imm_pkt: -- cxgb */
2820 /* make sure that we can refill faster than drain */
2821 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2822 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2824 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2826 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2828 while (mh != NULL) {
2831 m->m_nextpkt = NULL;
2832 #ifndef __NO_STRICT_ALIGNMENT
2833 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2836 rx_bytes += m->m_pkthdr.len;
2838 #if defined(INET6) || defined(INET)
2840 if (!lro_possible) {
2841 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2842 if (lro_possible && mf != NULL) {
2843 ifp->if_input(ifp, mf);
2844 DBG_COUNTER_INC(rx_if_input);
2848 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2849 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2850 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2856 ifp->if_input(ifp, m);
2857 DBG_COUNTER_INC(rx_if_input);
2868 ifp->if_input(ifp, mf);
2869 DBG_COUNTER_INC(rx_if_input);
2872 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2873 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2876 * Flush any outstanding LRO work
2878 #if defined(INET6) || defined(INET)
2879 tcp_lro_flush_all(&rxq->ifr_lc);
2883 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2886 ctx->ifc_flags |= IFC_DO_RESET;
2887 iflib_admin_intr_deferred(ctx);
2892 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2893 static inline qidx_t
2894 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2896 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2897 qidx_t minthresh = txq->ift_size / 8;
2898 if (in_use > 4*minthresh)
2899 return (notify_count);
2900 if (in_use > 2*minthresh)
2901 return (notify_count >> 1);
2902 if (in_use > minthresh)
2903 return (notify_count >> 3);
2907 static inline qidx_t
2908 txq_max_rs_deferred(iflib_txq_t txq)
2910 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2911 qidx_t minthresh = txq->ift_size / 8;
2912 if (txq->ift_in_use > 4*minthresh)
2913 return (notify_count);
2914 if (txq->ift_in_use > 2*minthresh)
2915 return (notify_count >> 1);
2916 if (txq->ift_in_use > minthresh)
2917 return (notify_count >> 2);
2921 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2922 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2924 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2925 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2926 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2928 /* forward compatibility for cxgb */
2929 #define FIRST_QSET(ctx) 0
2930 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2931 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2932 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2933 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2935 /* XXX we should be setting this to something other than zero */
2936 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2937 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2938 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2941 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2947 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2948 if (ring || txq->ift_db_pending >= max) {
2949 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2950 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2952 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2953 txq->ift_db_pending = txq->ift_npending = 0;
2961 print_pkt(if_pkt_info_t pi)
2963 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2964 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2965 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2966 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2967 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2968 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2972 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2973 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2974 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2975 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2978 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2980 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2981 struct ether_vlan_header *eh;
2985 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2986 M_WRITABLE(m) == 0) {
2987 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2991 DBG_COUNTER_INC(tx_frees);
2997 * Determine where frame payload starts.
2998 * Jump over vlan headers if already present,
2999 * helpful for QinQ too.
3001 if (__predict_false(m->m_len < sizeof(*eh))) {
3003 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3006 eh = mtod(m, struct ether_vlan_header *);
3007 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3008 pi->ipi_etype = ntohs(eh->evl_proto);
3009 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3011 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3012 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3015 switch (pi->ipi_etype) {
3020 struct ip *ip = NULL;
3021 struct tcphdr *th = NULL;
3024 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3025 if (__predict_false(m->m_len < minthlen)) {
3027 * if this code bloat is causing too much of a hit
3028 * move it to a separate function and mark it noinline
3030 if (m->m_len == pi->ipi_ehdrlen) {
3033 if (n->m_len >= sizeof(*ip)) {
3034 ip = (struct ip *)n->m_data;
3035 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3036 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3039 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3041 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3045 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3047 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3048 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3049 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3052 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3053 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3056 pi->ipi_ip_hlen = ip->ip_hl << 2;
3057 pi->ipi_ipproto = ip->ip_p;
3058 pi->ipi_flags |= IPI_TX_IPV4;
3060 /* TCP checksum offload may require TCP header length */
3061 if (IS_TX_OFFLOAD4(pi)) {
3062 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3063 if (__predict_false(th == NULL)) {
3065 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3067 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3069 pi->ipi_tcp_hflags = th->th_flags;
3070 pi->ipi_tcp_hlen = th->th_off << 2;
3071 pi->ipi_tcp_seq = th->th_seq;
3074 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3077 * TSO always requires hardware checksum offload.
3079 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3080 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3081 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3082 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3083 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3085 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3089 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3096 case ETHERTYPE_IPV6:
3098 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3100 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3102 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3104 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3107 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3109 /* XXX-BZ this will go badly in case of ext hdrs. */
3110 pi->ipi_ipproto = ip6->ip6_nxt;
3111 pi->ipi_flags |= IPI_TX_IPV6;
3113 /* TCP checksum offload may require TCP header length */
3114 if (IS_TX_OFFLOAD6(pi)) {
3115 if (pi->ipi_ipproto == IPPROTO_TCP) {
3116 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3118 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3121 pi->ipi_tcp_hflags = th->th_flags;
3122 pi->ipi_tcp_hlen = th->th_off << 2;
3123 pi->ipi_tcp_seq = th->th_seq;
3126 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3129 * TSO always requires hardware checksum offload.
3131 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3132 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3133 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3140 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3141 pi->ipi_ip_hlen = 0;
3150 * If dodgy hardware rejects the scatter gather chain we've handed it
3151 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3154 static __noinline struct mbuf *
3155 iflib_remove_mbuf(iflib_txq_t txq)
3158 struct mbuf *m, **ifsd_m;
3160 ifsd_m = txq->ift_sds.ifsd_m;
3161 ntxd = txq->ift_size;
3162 pidx = txq->ift_pidx & (ntxd - 1);
3163 ifsd_m = txq->ift_sds.ifsd_m;
3165 ifsd_m[pidx] = NULL;
3166 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3167 if (txq->ift_sds.ifsd_tso_map != NULL)
3168 bus_dmamap_unload(txq->ift_tso_buf_tag,
3169 txq->ift_sds.ifsd_tso_map[pidx]);
3171 txq->ift_dequeued++;
3176 static inline caddr_t
3177 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3181 caddr_t start, end, cur, next;
3183 ntxd = txq->ift_size;
3184 size = txq->ift_txd_size[qid];
3185 start = txq->ift_ifdi[qid].idi_vaddr;
3187 if (__predict_false(size == 0))
3189 cur = start + size*cidx;
3190 end = start + size*ntxd;
3191 next = CACHE_PTR_NEXT(cur);
3192 return (next < end ? next : start);
3196 * Pad an mbuf to ensure a minimum ethernet frame size.
3197 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3199 static __noinline int
3200 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3203 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3204 * and ARP message is the smallest common payload I can think of
3206 static char pad[18]; /* just zeros */
3208 struct mbuf *new_head;
3210 if (!M_WRITABLE(*m_head)) {
3211 new_head = m_dup(*m_head, M_NOWAIT);
3212 if (new_head == NULL) {
3214 device_printf(dev, "cannot pad short frame, m_dup() failed");
3215 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3216 DBG_COUNTER_INC(tx_frees);
3223 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3224 n > 0; n -= sizeof(pad))
3225 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3230 device_printf(dev, "cannot pad short frame\n");
3231 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3232 DBG_COUNTER_INC(tx_frees);
3240 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3243 if_shared_ctx_t sctx;
3244 if_softc_ctx_t scctx;
3245 bus_dma_tag_t buf_tag;
3246 bus_dma_segment_t *segs;
3247 struct mbuf *m_head, **ifsd_m;
3250 struct if_pkt_info pi;
3252 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3255 sctx = ctx->ifc_sctx;
3256 scctx = &ctx->ifc_softc_ctx;
3257 segs = txq->ift_segs;
3258 ntxd = txq->ift_size;
3263 * If we're doing TSO the next descriptor to clean may be quite far ahead
3265 cidx = txq->ift_cidx;
3266 pidx = txq->ift_pidx;
3267 if (ctx->ifc_flags & IFC_PREFETCH) {
3268 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3269 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3270 next_txd = calc_next_txd(txq, cidx, 0);
3274 /* prefetch the next cache line of mbuf pointers and flags */
3275 prefetch(&txq->ift_sds.ifsd_m[next]);
3276 prefetch(&txq->ift_sds.ifsd_map[next]);
3277 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3279 map = txq->ift_sds.ifsd_map[pidx];
3280 ifsd_m = txq->ift_sds.ifsd_m;
3282 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3283 buf_tag = txq->ift_tso_buf_tag;
3284 max_segs = scctx->isc_tx_tso_segments_max;
3285 map = txq->ift_sds.ifsd_tso_map[pidx];
3286 MPASS(buf_tag != NULL);
3287 MPASS(max_segs > 0);
3289 buf_tag = txq->ift_buf_tag;
3290 max_segs = scctx->isc_tx_nsegments;
3291 map = txq->ift_sds.ifsd_map[pidx];
3293 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3294 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3295 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3297 DBG_COUNTER_INC(encap_txd_encap_fail);
3304 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3306 pi.ipi_qsidx = txq->ift_id;
3307 pi.ipi_len = m_head->m_pkthdr.len;
3308 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3309 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3311 /* deliberate bitwise OR to make one condition */
3312 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3313 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3314 DBG_COUNTER_INC(encap_txd_encap_fail);
3321 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3324 if (__predict_false(err)) {
3327 /* try collapse once and defrag once */
3329 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3330 /* try defrag if collapsing fails */
3335 txq->ift_mbuf_defrag++;
3336 m_head = m_defrag(*m_headp, M_NOWAIT);
3339 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3340 * failed to map an mbuf that was run through m_defrag
3343 if (__predict_false(m_head == NULL || remap > 1))
3350 txq->ift_no_tx_dma_setup++;
3353 txq->ift_no_tx_dma_setup++;
3355 DBG_COUNTER_INC(tx_frees);
3359 txq->ift_map_failed++;
3360 DBG_COUNTER_INC(encap_load_mbuf_fail);
3361 DBG_COUNTER_INC(encap_txd_encap_fail);
3364 ifsd_m[pidx] = m_head;
3366 * XXX assumes a 1 to 1 relationship between segments and
3367 * descriptors - this does not hold true on all drivers, e.g.
3370 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3371 txq->ift_no_desc_avail++;
3372 bus_dmamap_unload(buf_tag, map);
3373 DBG_COUNTER_INC(encap_txq_avail_fail);
3374 DBG_COUNTER_INC(encap_txd_encap_fail);
3375 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3376 GROUPTASK_ENQUEUE(&txq->ift_task);
3380 * On Intel cards we can greatly reduce the number of TX interrupts
3381 * we see by only setting report status on every Nth descriptor.
3382 * However, this also means that the driver will need to keep track
3383 * of the descriptors that RS was set on to check them for the DD bit.
3385 txq->ift_rs_pending += nsegs + 1;
3386 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3387 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3388 pi.ipi_flags |= IPI_TX_INTR;
3389 txq->ift_rs_pending = 0;
3393 pi.ipi_nsegs = nsegs;
3395 MPASS(pidx >= 0 && pidx < txq->ift_size);
3399 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3400 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3401 DBG_COUNTER_INC(tx_encap);
3402 MPASS(pi.ipi_new_pidx < txq->ift_size);
3404 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3405 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3406 ndesc += txq->ift_size;
3410 * drivers can need as many as
3413 MPASS(ndesc <= pi.ipi_nsegs + 2);
3414 MPASS(pi.ipi_new_pidx != pidx);
3416 txq->ift_in_use += ndesc;
3419 * We update the last software descriptor again here because there may
3420 * be a sentinel and/or there may be more mbufs than segments
3422 txq->ift_pidx = pi.ipi_new_pidx;
3423 txq->ift_npending += pi.ipi_ndescs;
3425 *m_headp = m_head = iflib_remove_mbuf(txq);
3427 txq->ift_txd_encap_efbig++;
3436 * err can't possibly be non-zero here, so we don't neet to test it
3437 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3442 txq->ift_mbuf_defrag_failed++;
3443 txq->ift_map_failed++;
3445 DBG_COUNTER_INC(tx_frees);
3447 DBG_COUNTER_INC(encap_txd_encap_fail);
3452 iflib_tx_desc_free(iflib_txq_t txq, int n)
3454 uint32_t qsize, cidx, mask, gen;
3455 struct mbuf *m, **ifsd_m;
3458 cidx = txq->ift_cidx;
3460 qsize = txq->ift_size;
3462 ifsd_m = txq->ift_sds.ifsd_m;
3463 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3467 prefetch(ifsd_m[(cidx + 3) & mask]);
3468 prefetch(ifsd_m[(cidx + 4) & mask]);
3470 if ((m = ifsd_m[cidx]) != NULL) {
3471 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3472 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3473 bus_dmamap_sync(txq->ift_tso_buf_tag,
3474 txq->ift_sds.ifsd_tso_map[cidx],
3475 BUS_DMASYNC_POSTWRITE);
3476 bus_dmamap_unload(txq->ift_tso_buf_tag,
3477 txq->ift_sds.ifsd_tso_map[cidx]);
3479 bus_dmamap_sync(txq->ift_buf_tag,
3480 txq->ift_sds.ifsd_map[cidx],
3481 BUS_DMASYNC_POSTWRITE);
3482 bus_dmamap_unload(txq->ift_buf_tag,
3483 txq->ift_sds.ifsd_map[cidx]);
3485 /* XXX we don't support any drivers that batch packets yet */
3486 MPASS(m->m_nextpkt == NULL);
3488 ifsd_m[cidx] = NULL;
3490 txq->ift_dequeued++;
3492 DBG_COUNTER_INC(tx_frees);
3494 if (__predict_false(++cidx == qsize)) {
3499 txq->ift_cidx = cidx;
3504 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3507 if_ctx_t ctx = txq->ift_ctx;
3509 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3510 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3513 * Need a rate-limiting check so that this isn't called every time
3515 iflib_tx_credits_update(ctx, txq);
3516 reclaim = DESC_RECLAIMABLE(txq);
3518 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3520 if (iflib_verbose_debug) {
3521 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3522 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3529 iflib_tx_desc_free(txq, reclaim);
3530 txq->ift_cleaned += reclaim;
3531 txq->ift_in_use -= reclaim;
3536 static struct mbuf **
3537 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3540 struct mbuf **items;
3543 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3544 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3546 prefetch(items[(cidx + offset) & (size-1)]);
3547 if (remaining > 1) {
3548 prefetch2cachelines(&items[next]);
3549 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3550 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3551 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3553 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3557 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3560 ifmp_ring_check_drainage(txq->ift_br, budget);
3564 iflib_txq_can_drain(struct ifmp_ring *r)
3566 iflib_txq_t txq = r->cookie;
3567 if_ctx_t ctx = txq->ift_ctx;
3569 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3571 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3572 BUS_DMASYNC_POSTREAD);
3573 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3578 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3580 iflib_txq_t txq = r->cookie;
3581 if_ctx_t ctx = txq->ift_ctx;
3582 if_t ifp = ctx->ifc_ifp;
3583 struct mbuf **mp, *m;
3584 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3585 int reclaimed, err, in_use_prev, desc_used;
3586 bool do_prefetch, ring, rang;
3588 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3589 !LINK_ACTIVE(ctx))) {
3590 DBG_COUNTER_INC(txq_drain_notready);
3593 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3594 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3595 avail = IDXDIFF(pidx, cidx, r->size);
3596 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3597 DBG_COUNTER_INC(txq_drain_flushing);
3598 for (i = 0; i < avail; i++) {
3599 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3600 m_free(r->items[(cidx + i) & (r->size-1)]);
3601 r->items[(cidx + i) & (r->size-1)] = NULL;
3606 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3607 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3609 callout_stop(&txq->ift_timer);
3610 CALLOUT_UNLOCK(txq);
3611 DBG_COUNTER_INC(txq_drain_oactive);
3615 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3616 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3617 count = MIN(avail, TX_BATCH_SIZE);
3619 if (iflib_verbose_debug)
3620 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3621 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3623 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3624 avail = TXQ_AVAIL(txq);
3626 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3627 int rem = do_prefetch ? count - i : 0;
3629 mp = _ring_peek_one(r, cidx, i, rem);
3630 MPASS(mp != NULL && *mp != NULL);
3631 if (__predict_false(*mp == (struct mbuf *)txq)) {
3636 in_use_prev = txq->ift_in_use;
3637 err = iflib_encap(txq, mp);
3638 if (__predict_false(err)) {
3639 /* no room - bail out */
3643 /* we can't send this packet - skip it */
3649 DBG_COUNTER_INC(tx_sent);
3650 bytes_sent += m->m_pkthdr.len;
3651 mcast_sent += !!(m->m_flags & M_MCAST);
3652 avail = TXQ_AVAIL(txq);
3654 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3655 desc_used += (txq->ift_in_use - in_use_prev);
3656 ETHER_BPF_MTAP(ifp, m);
3657 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3659 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3662 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3663 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3664 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3665 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3666 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3668 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3670 if (iflib_verbose_debug)
3671 printf("consumed=%d\n", consumed);
3677 iflib_txq_drain_always(struct ifmp_ring *r)
3683 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3691 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3693 callout_stop(&txq->ift_timer);
3694 CALLOUT_UNLOCK(txq);
3696 avail = IDXDIFF(pidx, cidx, r->size);
3697 for (i = 0; i < avail; i++) {
3698 mp = _ring_peek_one(r, cidx, i, avail - i);
3699 if (__predict_false(*mp == (struct mbuf *)txq))
3702 DBG_COUNTER_INC(tx_frees);
3704 MPASS(ifmp_ring_is_stalled(r) == 0);
3709 iflib_ifmp_purge(iflib_txq_t txq)
3711 struct ifmp_ring *r;
3714 r->drain = iflib_txq_drain_free;
3715 r->can_drain = iflib_txq_drain_always;
3717 ifmp_ring_check_drainage(r, r->size);
3719 r->drain = iflib_txq_drain;
3720 r->can_drain = iflib_txq_can_drain;
3724 _task_fn_tx(void *context)
3726 iflib_txq_t txq = context;
3727 if_ctx_t ctx = txq->ift_ctx;
3728 #if defined(ALTQ) || defined(DEV_NETMAP)
3729 if_t ifp = ctx->ifc_ifp;
3731 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3733 #ifdef IFLIB_DIAGNOSTICS
3734 txq->ift_cpu_exec_count[curcpu]++;
3736 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3739 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3740 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3741 BUS_DMASYNC_POSTREAD);
3742 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3743 netmap_tx_irq(ifp, txq->ift_id);
3744 if (ctx->ifc_flags & IFC_LEGACY)
3745 IFDI_INTR_ENABLE(ctx);
3747 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3752 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3753 iflib_altq_if_start(ifp);
3755 if (txq->ift_db_pending)
3756 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3758 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3760 * When abdicating, we always need to check drainage, not just when we don't enqueue
3763 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3764 if (ctx->ifc_flags & IFC_LEGACY)
3765 IFDI_INTR_ENABLE(ctx);
3767 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3771 _task_fn_rx(void *context)
3773 iflib_rxq_t rxq = context;
3774 if_ctx_t ctx = rxq->ifr_ctx;
3778 #ifdef IFLIB_DIAGNOSTICS
3779 rxq->ifr_cpu_exec_count[curcpu]++;
3781 DBG_COUNTER_INC(task_fn_rxs);
3782 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3786 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3788 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3793 budget = ctx->ifc_sysctl_rx_budget;
3795 budget = 16; /* XXX */
3796 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3797 if (ctx->ifc_flags & IFC_LEGACY)
3798 IFDI_INTR_ENABLE(ctx);
3800 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3801 DBG_COUNTER_INC(rx_intr_enables);
3803 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3806 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3810 _task_fn_admin(void *context)
3812 if_ctx_t ctx = context;
3813 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3816 bool oactive, running, do_reset, do_watchdog, in_detach;
3817 uint32_t reset_on = hz / 2;
3820 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3821 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3822 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3823 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3824 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3825 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3828 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3834 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3836 callout_stop(&txq->ift_timer);
3837 CALLOUT_UNLOCK(txq);
3840 ctx->ifc_watchdog_events++;
3841 IFDI_WATCHDOG_RESET(ctx);
3843 IFDI_UPDATE_ADMIN_STATUS(ctx);
3844 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3847 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3848 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3850 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3852 IFDI_LINK_INTR_ENABLE(ctx);
3854 iflib_if_init_locked(ctx);
3857 if (LINK_ACTIVE(ctx) == 0)
3859 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3860 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3865 _task_fn_iov(void *context)
3867 if_ctx_t ctx = context;
3869 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3870 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3874 IFDI_VFLR_HANDLE(ctx);
3879 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3882 if_int_delay_info_t info;
3885 info = (if_int_delay_info_t)arg1;
3886 ctx = info->iidi_ctx;
3887 info->iidi_req = req;
3888 info->iidi_oidp = oidp;
3890 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3895 /*********************************************************************
3899 **********************************************************************/
3902 iflib_if_init_locked(if_ctx_t ctx)
3905 iflib_init_locked(ctx);
3910 iflib_if_init(void *arg)
3915 iflib_if_init_locked(ctx);
3920 iflib_if_transmit(if_t ifp, struct mbuf *m)
3922 if_ctx_t ctx = if_getsoftc(ifp);
3926 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3928 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3929 DBG_COUNTER_INC(tx_frees);
3934 MPASS(m->m_nextpkt == NULL);
3935 /* ALTQ-enabled interfaces always use queue 0. */
3937 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3938 qidx = QIDX(ctx, m);
3940 * XXX calculate buf_ring based on flowid (divvy up bits?)
3942 txq = &ctx->ifc_txqs[qidx];
3944 #ifdef DRIVER_BACKPRESSURE
3945 if (txq->ift_closed) {
3947 next = m->m_nextpkt;
3948 m->m_nextpkt = NULL;
3950 DBG_COUNTER_INC(tx_frees);
3962 next = next->m_nextpkt;
3963 } while (next != NULL);
3965 if (count > nitems(marr))
3966 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3967 /* XXX check nextpkt */
3969 /* XXX simplify for now */
3970 DBG_COUNTER_INC(tx_frees);
3973 for (next = m, i = 0; next != NULL; i++) {
3975 next = next->m_nextpkt;
3976 mp[i]->m_nextpkt = NULL;
3979 DBG_COUNTER_INC(tx_seen);
3980 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3983 GROUPTASK_ENQUEUE(&txq->ift_task);
3986 GROUPTASK_ENQUEUE(&txq->ift_task);
3987 /* support forthcoming later */
3988 #ifdef DRIVER_BACKPRESSURE
3989 txq->ift_closed = TRUE;
3991 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3993 DBG_COUNTER_INC(tx_frees);
4001 * The overall approach to integrating iflib with ALTQ is to continue to use
4002 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4003 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4004 * is redundant/unnecessary, but doing so minimizes the amount of
4005 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4006 * redundantly queueing to an intermediate mp_ring is swamped by the
4007 * performance limitations inherent in using ALTQ.
4009 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4010 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4011 * given interface. If ALTQ is enabled for an interface, then all
4012 * transmitted packets for that interface will be submitted to the ALTQ
4013 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4014 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4015 * update stats that the iflib machinery handles, and which is sensitve to
4016 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4017 * will be installed as the start routine for use by ALTQ facilities that
4018 * need to trigger queue drains on a scheduled basis.
4022 iflib_altq_if_start(if_t ifp)
4024 struct ifaltq *ifq = &ifp->if_snd;
4028 IFQ_DEQUEUE_NOLOCK(ifq, m);
4030 iflib_if_transmit(ifp, m);
4031 IFQ_DEQUEUE_NOLOCK(ifq, m);
4037 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4041 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4042 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4044 iflib_altq_if_start(ifp);
4046 err = iflib_if_transmit(ifp, m);
4053 iflib_if_qflush(if_t ifp)
4055 if_ctx_t ctx = if_getsoftc(ifp);
4056 iflib_txq_t txq = ctx->ifc_txqs;
4060 ctx->ifc_flags |= IFC_QFLUSH;
4062 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4063 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4064 iflib_txq_check_drain(txq, 0);
4066 ctx->ifc_flags &= ~IFC_QFLUSH;
4070 * When ALTQ is enabled, this will also take care of purging the
4077 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4078 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4079 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4080 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4083 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4085 if_ctx_t ctx = if_getsoftc(ifp);
4086 struct ifreq *ifr = (struct ifreq *)data;
4087 #if defined(INET) || defined(INET6)
4088 struct ifaddr *ifa = (struct ifaddr *)data;
4090 bool avoid_reset = false;
4091 int err = 0, reinit = 0, bits;
4096 if (ifa->ifa_addr->sa_family == AF_INET)
4100 if (ifa->ifa_addr->sa_family == AF_INET6)
4104 ** Calling init results in link renegotiation,
4105 ** so we avoid doing it when possible.
4108 if_setflagbits(ifp, IFF_UP,0);
4109 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4112 if (!(if_getflags(ifp) & IFF_NOARP))
4113 arp_ifinit(ifp, ifa);
4116 err = ether_ioctl(ifp, command, data);
4120 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4124 bits = if_getdrvflags(ifp);
4125 /* stop the driver and free any clusters before proceeding */
4128 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4130 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4131 ctx->ifc_flags |= IFC_MULTISEG;
4133 ctx->ifc_flags &= ~IFC_MULTISEG;
4135 err = if_setmtu(ifp, ifr->ifr_mtu);
4137 iflib_init_locked(ctx);
4139 if_setdrvflags(ifp, bits);
4145 if (if_getflags(ifp) & IFF_UP) {
4146 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4147 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4148 (IFF_PROMISC | IFF_ALLMULTI)) {
4149 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4153 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4156 ctx->ifc_if_flags = if_getflags(ifp);
4161 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4163 IFDI_INTR_DISABLE(ctx);
4164 IFDI_MULTI_SET(ctx);
4165 IFDI_INTR_ENABLE(ctx);
4171 IFDI_MEDIA_SET(ctx);
4176 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4180 struct ifi2creq i2c;
4182 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4185 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4189 if (i2c.len > sizeof(i2c.data)) {
4194 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4195 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4201 int mask, setmask, oldmask;
4203 oldmask = if_getcapenable(ifp);
4204 mask = ifr->ifr_reqcap ^ oldmask;
4205 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4208 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4210 setmask |= (mask & IFCAP_FLAGS);
4211 setmask |= (mask & IFCAP_WOL);
4214 * If any RX csum has changed, change all the ones that
4215 * are supported by the driver.
4217 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4218 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4219 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4223 * want to ensure that traffic has stopped before we change any of the flags
4227 bits = if_getdrvflags(ifp);
4228 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4231 if_togglecapenable(ifp, setmask);
4233 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4234 iflib_init_locked(ctx);
4236 if_setdrvflags(ifp, bits);
4243 case SIOCGPRIVATE_0:
4247 err = IFDI_PRIV_IOCTL(ctx, command, data);
4251 err = ether_ioctl(ifp, command, data);
4260 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4262 if_ctx_t ctx = if_getsoftc(ifp);
4264 return (IFDI_GET_COUNTER(ctx, cnt));
4267 /*********************************************************************
4269 * OTHER FUNCTIONS EXPORTED TO THE STACK
4271 **********************************************************************/
4274 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4276 if_ctx_t ctx = if_getsoftc(ifp);
4278 if ((void *)ctx != arg)
4281 if ((vtag == 0) || (vtag > 4095))
4285 IFDI_VLAN_REGISTER(ctx, vtag);
4286 /* Re-init to load the changes */
4287 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4288 iflib_if_init_locked(ctx);
4293 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4295 if_ctx_t ctx = if_getsoftc(ifp);
4297 if ((void *)ctx != arg)
4300 if ((vtag == 0) || (vtag > 4095))
4304 IFDI_VLAN_UNREGISTER(ctx, vtag);
4305 /* Re-init to load the changes */
4306 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4307 iflib_if_init_locked(ctx);
4312 iflib_led_func(void *arg, int onoff)
4317 IFDI_LED_FUNC(ctx, onoff);
4321 /*********************************************************************
4323 * BUS FUNCTION DEFINITIONS
4325 **********************************************************************/
4328 iflib_device_probe(device_t dev)
4330 const pci_vendor_info_t *ent;
4331 if_shared_ctx_t sctx;
4332 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4333 uint16_t pci_vendor_id;
4335 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4338 pci_vendor_id = pci_get_vendor(dev);
4339 pci_device_id = pci_get_device(dev);
4340 pci_subvendor_id = pci_get_subvendor(dev);
4341 pci_subdevice_id = pci_get_subdevice(dev);
4342 pci_rev_id = pci_get_revid(dev);
4343 if (sctx->isc_parse_devinfo != NULL)
4344 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4346 ent = sctx->isc_vendor_info;
4347 while (ent->pvi_vendor_id != 0) {
4348 if (pci_vendor_id != ent->pvi_vendor_id) {
4352 if ((pci_device_id == ent->pvi_device_id) &&
4353 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4354 (ent->pvi_subvendor_id == 0)) &&
4355 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4356 (ent->pvi_subdevice_id == 0)) &&
4357 ((pci_rev_id == ent->pvi_rev_id) ||
4358 (ent->pvi_rev_id == 0))) {
4360 device_set_desc_copy(dev, ent->pvi_name);
4361 /* this needs to be changed to zero if the bus probing code
4362 * ever stops re-probing on best match because the sctx
4363 * may have its values over written by register calls
4364 * in subsequent probes
4366 return (BUS_PROBE_DEFAULT);
4374 iflib_device_probe_vendor(device_t dev)
4378 probe = iflib_device_probe(dev);
4379 if (probe == BUS_PROBE_DEFAULT)
4380 return (BUS_PROBE_VENDOR);
4386 iflib_reset_qvalues(if_ctx_t ctx)
4388 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4389 if_shared_ctx_t sctx = ctx->ifc_sctx;
4390 device_t dev = ctx->ifc_dev;
4393 if (ctx->ifc_sysctl_ntxqs != 0)
4394 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4395 if (ctx->ifc_sysctl_nrxqs != 0)
4396 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4398 for (i = 0; i < sctx->isc_ntxqs; i++) {
4399 if (ctx->ifc_sysctl_ntxds[i] != 0)
4400 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4402 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4405 for (i = 0; i < sctx->isc_nrxqs; i++) {
4406 if (ctx->ifc_sysctl_nrxds[i] != 0)
4407 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4409 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4412 for (i = 0; i < sctx->isc_nrxqs; i++) {
4413 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4414 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4415 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4416 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4418 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4419 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4420 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4421 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4423 if (!powerof2(scctx->isc_nrxd[i])) {
4424 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4425 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4426 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4430 for (i = 0; i < sctx->isc_ntxqs; i++) {
4431 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4432 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4433 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4434 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4436 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4437 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4438 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4439 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4441 if (!powerof2(scctx->isc_ntxd[i])) {
4442 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4443 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4444 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4450 iflib_add_pfil(if_ctx_t ctx)
4452 struct pfil_head *pfil;
4453 struct pfil_head_args pa;
4457 pa.pa_version = PFIL_VERSION;
4458 pa.pa_flags = PFIL_IN;
4459 pa.pa_type = PFIL_TYPE_ETHERNET;
4460 pa.pa_headname = ctx->ifc_ifp->if_xname;
4461 pfil = pfil_head_register(&pa);
4463 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4469 iflib_rem_pfil(if_ctx_t ctx)
4471 struct pfil_head *pfil;
4475 rxq = ctx->ifc_rxqs;
4477 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4480 pfil_head_unregister(pfil);
4484 get_ctx_core_offset(if_ctx_t ctx)
4486 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4487 struct cpu_offset *op;
4489 uint16_t ret = ctx->ifc_sysctl_core_offset;
4491 if (ret != CORE_OFFSET_UNSPECIFIED)
4494 if (ctx->ifc_sysctl_separate_txrx)
4495 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4497 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4499 mtx_lock(&cpu_offset_mtx);
4500 SLIST_FOREACH(op, &cpu_offsets, entries) {
4501 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4504 MPASS(op->refcount < UINT_MAX);
4509 if (ret == CORE_OFFSET_UNSPECIFIED) {
4511 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4514 device_printf(ctx->ifc_dev,
4515 "allocation for cpu offset failed.\n");
4519 CPU_COPY(&ctx->ifc_cpus, &op->set);
4520 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4523 mtx_unlock(&cpu_offset_mtx);
4529 unref_ctx_core_offset(if_ctx_t ctx)
4531 struct cpu_offset *op, *top;
4533 mtx_lock(&cpu_offset_mtx);
4534 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4535 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4536 MPASS(op->refcount > 0);
4538 if (op->refcount == 0) {
4539 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4545 mtx_unlock(&cpu_offset_mtx);
4549 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4553 if_softc_ctx_t scctx;
4554 kobjop_desc_t kobj_desc;
4555 kobj_method_t *kobj_method;
4557 uint16_t main_rxq, main_txq;
4559 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4562 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4563 device_set_softc(dev, ctx);
4564 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4567 ctx->ifc_sctx = sctx;
4569 ctx->ifc_softc = sc;
4571 if ((err = iflib_register(ctx)) != 0) {
4572 device_printf(dev, "iflib_register failed %d\n", err);
4575 iflib_add_device_sysctl_pre(ctx);
4577 scctx = &ctx->ifc_softc_ctx;
4580 iflib_reset_qvalues(ctx);
4582 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4583 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4586 _iflib_pre_assert(scctx);
4587 ctx->ifc_txrx = *scctx->isc_txrx;
4589 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4590 ctx->ifc_mediap = scctx->isc_media;
4593 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4594 MPASS(scctx->isc_tx_csum_flags);
4597 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4598 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4600 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4601 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4602 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4603 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4605 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4606 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4608 /* XXX change for per-queue sizes */
4609 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4610 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4612 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4613 MAX_SINGLE_PACKET_FRACTION)
4614 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4615 MAX_SINGLE_PACKET_FRACTION);
4616 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4617 MAX_SINGLE_PACKET_FRACTION)
4618 scctx->isc_tx_tso_segments_max = max(1,
4619 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4621 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4622 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4624 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4627 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4630 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4631 * into account. In the worst case, each of these calls will
4632 * add another mbuf and, thus, the requirement for another DMA
4633 * segment. So for best performance, it doesn't make sense to
4634 * advertize a maximum of TSO segments that typically will
4635 * require defragmentation in iflib_encap().
4637 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4638 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4640 if (scctx->isc_rss_table_size == 0)
4641 scctx->isc_rss_table_size = 64;
4642 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4644 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4645 /* XXX format name */
4646 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4647 NULL, NULL, "admin");
4649 /* Set up cpu set. If it fails, use the set of all CPUs. */
4650 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4651 device_printf(dev, "Unable to fetch CPU list\n");
4652 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4654 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4657 ** Now set up MSI or MSI-X, should return us the number of supported
4658 ** vectors (will be 1 for a legacy interrupt and MSI).
4660 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4661 msix = scctx->isc_vectors;
4662 } else if (scctx->isc_msix_bar != 0)
4664 * The simple fact that isc_msix_bar is not 0 does not mean we
4665 * we have a good value there that is known to work.
4667 msix = iflib_msix_init(ctx);
4669 scctx->isc_vectors = 1;
4670 scctx->isc_ntxqsets = 1;
4671 scctx->isc_nrxqsets = 1;
4672 scctx->isc_intr = IFLIB_INTR_LEGACY;
4675 /* Get memory for the station queues */
4676 if ((err = iflib_queues_alloc(ctx))) {
4677 device_printf(dev, "Unable to allocate queue memory\n");
4678 goto fail_intr_free;
4681 if ((err = iflib_qset_structures_setup(ctx)))
4685 * Now that we know how many queues there are, get the core offset.
4687 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4690 * Group taskqueues aren't properly set up until SMP is started,
4691 * so we disable interrupts until we can handle them post
4694 * XXX: disabling interrupts doesn't actually work, at least for
4695 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4696 * we do null handling and depend on this not causing too large an
4699 IFDI_INTR_DISABLE(ctx);
4703 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4704 * aren't the default NULL implementation.
4706 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4707 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4709 if (kobj_method == &kobj_desc->deflt) {
4711 "MSI-X requires ifdi_rx_queue_intr_enable method");
4715 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4716 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4718 if (kobj_method == &kobj_desc->deflt) {
4720 "MSI-X requires ifdi_tx_queue_intr_enable method");
4726 * Assign the MSI-X vectors.
4727 * Note that the default NULL ifdi_msix_intr_assign method will
4730 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4732 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4738 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4742 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4743 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4748 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4750 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4751 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4756 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4757 * This must appear after the call to ether_ifattach() because
4758 * ether_ifattach() sets if_hdrlen to the default value.
4760 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4761 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4763 if ((err = iflib_netmap_attach(ctx))) {
4764 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4769 NETDUMP_SET(ctx->ifc_ifp, iflib);
4771 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4772 iflib_add_device_sysctl_post(ctx);
4773 iflib_add_pfil(ctx);
4774 ctx->ifc_flags |= IFC_INIT_DONE;
4780 ether_ifdetach(ctx->ifc_ifp);
4782 iflib_free_intr_mem(ctx);
4784 iflib_tx_structures_free(ctx);
4785 iflib_rx_structures_free(ctx);
4790 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4791 free(ctx->ifc_softc, M_IFLIB);
4797 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4798 struct iflib_cloneattach_ctx *clctx)
4803 if_softc_ctx_t scctx;
4809 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4810 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4811 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4812 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4813 ctx->ifc_flags |= IFC_PSEUDO;
4815 ctx->ifc_sctx = sctx;
4816 ctx->ifc_softc = sc;
4819 if ((err = iflib_register(ctx)) != 0) {
4820 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4823 iflib_add_device_sysctl_pre(ctx);
4825 scctx = &ctx->ifc_softc_ctx;
4828 iflib_reset_qvalues(ctx);
4830 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4831 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4834 if (sctx->isc_flags & IFLIB_GEN_MAC)
4835 ether_gen_addr(ifp, &ctx->ifc_mac);
4836 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4837 clctx->cc_params)) != 0) {
4838 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4841 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4842 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4843 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4846 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4847 MPASS(scctx->isc_tx_csum_flags);
4850 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4851 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4853 ifp->if_flags |= IFF_NOGROUP;
4854 if (sctx->isc_flags & IFLIB_PSEUDO) {
4855 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4857 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4858 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4864 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4865 * This must appear after the call to ether_ifattach() because
4866 * ether_ifattach() sets if_hdrlen to the default value.
4868 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4869 if_setifheaderlen(ifp,
4870 sizeof(struct ether_vlan_header));
4872 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4873 iflib_add_device_sysctl_post(ctx);
4874 ctx->ifc_flags |= IFC_INIT_DONE;
4877 _iflib_pre_assert(scctx);
4878 ctx->ifc_txrx = *scctx->isc_txrx;
4880 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4881 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4882 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4883 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4885 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4886 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4888 /* XXX change for per-queue sizes */
4889 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4890 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4892 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4893 MAX_SINGLE_PACKET_FRACTION)
4894 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4895 MAX_SINGLE_PACKET_FRACTION);
4896 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4897 MAX_SINGLE_PACKET_FRACTION)
4898 scctx->isc_tx_tso_segments_max = max(1,
4899 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4901 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4902 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4904 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4907 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4910 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4911 * into account. In the worst case, each of these calls will
4912 * add another mbuf and, thus, the requirement for another DMA
4913 * segment. So for best performance, it doesn't make sense to
4914 * advertize a maximum of TSO segments that typically will
4915 * require defragmentation in iflib_encap().
4917 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4918 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4920 if (scctx->isc_rss_table_size == 0)
4921 scctx->isc_rss_table_size = 64;
4922 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4924 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4925 /* XXX format name */
4926 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4927 NULL, NULL, "admin");
4929 /* XXX --- can support > 1 -- but keep it simple for now */
4930 scctx->isc_intr = IFLIB_INTR_LEGACY;
4932 /* Get memory for the station queues */
4933 if ((err = iflib_queues_alloc(ctx))) {
4934 device_printf(dev, "Unable to allocate queue memory\n");
4935 goto fail_iflib_detach;
4938 if ((err = iflib_qset_structures_setup(ctx))) {
4939 device_printf(dev, "qset structure setup failed %d\n", err);
4944 * XXX What if anything do we want to do about interrupts?
4946 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4947 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4948 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4953 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4954 * This must appear after the call to ether_ifattach() because
4955 * ether_ifattach() sets if_hdrlen to the default value.
4957 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4958 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4960 /* XXX handle more than one queue */
4961 for (i = 0; i < scctx->isc_nrxqsets; i++)
4962 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4966 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4967 iflib_add_device_sysctl_post(ctx);
4968 ctx->ifc_flags |= IFC_INIT_DONE;
4973 ether_ifdetach(ctx->ifc_ifp);
4975 iflib_tx_structures_free(ctx);
4976 iflib_rx_structures_free(ctx);
4982 free(ctx->ifc_softc, M_IFLIB);
4988 iflib_pseudo_deregister(if_ctx_t ctx)
4990 if_t ifp = ctx->ifc_ifp;
4994 struct taskqgroup *tqg;
4997 /* Unregister VLAN events */
4998 if (ctx->ifc_vlan_attach_event != NULL)
4999 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5000 if (ctx->ifc_vlan_detach_event != NULL)
5001 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5003 ether_ifdetach(ifp);
5004 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5005 CTX_LOCK_DESTROY(ctx);
5006 /* XXX drain any dependent tasks */
5007 tqg = qgroup_if_io_tqg;
5008 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5009 callout_drain(&txq->ift_timer);
5010 if (txq->ift_task.gt_uniq != NULL)
5011 taskqgroup_detach(tqg, &txq->ift_task);
5013 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5014 if (rxq->ifr_task.gt_uniq != NULL)
5015 taskqgroup_detach(tqg, &rxq->ifr_task);
5017 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5018 free(fl->ifl_rx_bitmap, M_IFLIB);
5020 tqg = qgroup_if_config_tqg;
5021 if (ctx->ifc_admin_task.gt_uniq != NULL)
5022 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5023 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5024 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5028 iflib_tx_structures_free(ctx);
5029 iflib_rx_structures_free(ctx);
5030 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5031 free(ctx->ifc_softc, M_IFLIB);
5037 iflib_device_attach(device_t dev)
5040 if_shared_ctx_t sctx;
5042 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5045 pci_enable_busmaster(dev);
5047 return (iflib_device_register(dev, NULL, sctx, &ctx));
5051 iflib_device_deregister(if_ctx_t ctx)
5053 if_t ifp = ctx->ifc_ifp;
5056 device_t dev = ctx->ifc_dev;
5058 struct taskqgroup *tqg;
5061 /* Make sure VLANS are not using driver */
5062 if (if_vlantrunkinuse(ifp)) {
5063 device_printf(dev, "Vlan in use, detach first\n");
5067 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5068 device_printf(dev, "SR-IOV in use; detach first.\n");
5074 ctx->ifc_flags |= IFC_IN_DETACH;
5081 /* Unregister VLAN events */
5082 if (ctx->ifc_vlan_attach_event != NULL)
5083 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5084 if (ctx->ifc_vlan_detach_event != NULL)
5085 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5087 iflib_netmap_detach(ifp);
5088 ether_ifdetach(ifp);
5089 iflib_rem_pfil(ctx);
5090 if (ctx->ifc_led_dev != NULL)
5091 led_destroy(ctx->ifc_led_dev);
5092 /* XXX drain any dependent tasks */
5093 tqg = qgroup_if_io_tqg;
5094 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5095 callout_drain(&txq->ift_timer);
5096 if (txq->ift_task.gt_uniq != NULL)
5097 taskqgroup_detach(tqg, &txq->ift_task);
5099 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5100 if (rxq->ifr_task.gt_uniq != NULL)
5101 taskqgroup_detach(tqg, &rxq->ifr_task);
5103 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5104 free(fl->ifl_rx_bitmap, M_IFLIB);
5106 tqg = qgroup_if_config_tqg;
5107 if (ctx->ifc_admin_task.gt_uniq != NULL)
5108 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5109 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5110 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5115 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5116 CTX_LOCK_DESTROY(ctx);
5117 device_set_softc(ctx->ifc_dev, NULL);
5118 iflib_free_intr_mem(ctx);
5120 bus_generic_detach(dev);
5123 iflib_tx_structures_free(ctx);
5124 iflib_rx_structures_free(ctx);
5125 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5126 free(ctx->ifc_softc, M_IFLIB);
5127 unref_ctx_core_offset(ctx);
5128 STATE_LOCK_DESTROY(ctx);
5134 iflib_free_intr_mem(if_ctx_t ctx)
5137 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5138 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5140 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5141 pci_release_msi(ctx->ifc_dev);
5143 if (ctx->ifc_msix_mem != NULL) {
5144 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5145 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5146 ctx->ifc_msix_mem = NULL;
5151 iflib_device_detach(device_t dev)
5153 if_ctx_t ctx = device_get_softc(dev);
5155 return (iflib_device_deregister(ctx));
5159 iflib_device_suspend(device_t dev)
5161 if_ctx_t ctx = device_get_softc(dev);
5167 return bus_generic_suspend(dev);
5170 iflib_device_shutdown(device_t dev)
5172 if_ctx_t ctx = device_get_softc(dev);
5178 return bus_generic_suspend(dev);
5183 iflib_device_resume(device_t dev)
5185 if_ctx_t ctx = device_get_softc(dev);
5186 iflib_txq_t txq = ctx->ifc_txqs;
5190 iflib_if_init_locked(ctx);
5192 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5193 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5195 return (bus_generic_resume(dev));
5199 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5202 if_ctx_t ctx = device_get_softc(dev);
5205 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5212 iflib_device_iov_uninit(device_t dev)
5214 if_ctx_t ctx = device_get_softc(dev);
5217 IFDI_IOV_UNINIT(ctx);
5222 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5225 if_ctx_t ctx = device_get_softc(dev);
5228 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5234 /*********************************************************************
5236 * MODULE FUNCTION DEFINITIONS
5238 **********************************************************************/
5241 * - Start a fast taskqueue thread for each core
5242 * - Start a taskqueue for control operations
5245 iflib_module_init(void)
5251 iflib_module_event_handler(module_t mod, int what, void *arg)
5257 if ((err = iflib_module_init()) != 0)
5263 return (EOPNOTSUPP);
5269 /*********************************************************************
5271 * PUBLIC FUNCTION DEFINITIONS
5272 * ordered as in iflib.h
5274 **********************************************************************/
5278 _iflib_assert(if_shared_ctx_t sctx)
5282 MPASS(sctx->isc_tx_maxsize);
5283 MPASS(sctx->isc_tx_maxsegsize);
5285 MPASS(sctx->isc_rx_maxsize);
5286 MPASS(sctx->isc_rx_nsegments);
5287 MPASS(sctx->isc_rx_maxsegsize);
5289 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5290 for (i = 0; i < sctx->isc_nrxqs; i++) {
5291 MPASS(sctx->isc_nrxd_min[i]);
5292 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5293 MPASS(sctx->isc_nrxd_max[i]);
5294 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5295 MPASS(sctx->isc_nrxd_default[i]);
5296 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5299 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5300 for (i = 0; i < sctx->isc_ntxqs; i++) {
5301 MPASS(sctx->isc_ntxd_min[i]);
5302 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5303 MPASS(sctx->isc_ntxd_max[i]);
5304 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5305 MPASS(sctx->isc_ntxd_default[i]);
5306 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5311 _iflib_pre_assert(if_softc_ctx_t scctx)
5314 MPASS(scctx->isc_txrx->ift_txd_encap);
5315 MPASS(scctx->isc_txrx->ift_txd_flush);
5316 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5317 MPASS(scctx->isc_txrx->ift_rxd_available);
5318 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5319 MPASS(scctx->isc_txrx->ift_rxd_refill);
5320 MPASS(scctx->isc_txrx->ift_rxd_flush);
5324 iflib_register(if_ctx_t ctx)
5326 if_shared_ctx_t sctx = ctx->ifc_sctx;
5327 driver_t *driver = sctx->isc_driver;
5328 device_t dev = ctx->ifc_dev;
5331 _iflib_assert(sctx);
5334 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5335 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5337 device_printf(dev, "can not allocate ifnet structure\n");
5342 * Initialize our context's device specific methods
5344 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5345 kobj_class_compile((kobj_class_t) driver);
5348 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5349 if_setsoftc(ifp, ctx);
5350 if_setdev(ifp, dev);
5351 if_setinitfn(ifp, iflib_if_init);
5352 if_setioctlfn(ifp, iflib_if_ioctl);
5354 if_setstartfn(ifp, iflib_altq_if_start);
5355 if_settransmitfn(ifp, iflib_altq_if_transmit);
5356 if_setsendqready(ifp);
5358 if_settransmitfn(ifp, iflib_if_transmit);
5360 if_setqflushfn(ifp, iflib_if_qflush);
5361 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5363 ctx->ifc_vlan_attach_event =
5364 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5365 EVENTHANDLER_PRI_FIRST);
5366 ctx->ifc_vlan_detach_event =
5367 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5368 EVENTHANDLER_PRI_FIRST);
5370 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5371 ctx->ifc_mediap = &ctx->ifc_media;
5372 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5373 iflib_media_change, iflib_media_status);
5379 iflib_queues_alloc(if_ctx_t ctx)
5381 if_shared_ctx_t sctx = ctx->ifc_sctx;
5382 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5383 device_t dev = ctx->ifc_dev;
5384 int nrxqsets = scctx->isc_nrxqsets;
5385 int ntxqsets = scctx->isc_ntxqsets;
5388 iflib_fl_t fl = NULL;
5389 int i, j, cpu, err, txconf, rxconf;
5390 iflib_dma_info_t ifdip;
5391 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5392 uint32_t *txqsizes = scctx->isc_txqsizes;
5393 uint8_t nrxqs = sctx->isc_nrxqs;
5394 uint8_t ntxqs = sctx->isc_ntxqs;
5395 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5399 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5400 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5402 /* Allocate the TX ring struct memory */
5403 if (!(ctx->ifc_txqs =
5404 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5405 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5406 device_printf(dev, "Unable to allocate TX ring memory\n");
5411 /* Now allocate the RX */
5412 if (!(ctx->ifc_rxqs =
5413 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5414 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5415 device_printf(dev, "Unable to allocate RX ring memory\n");
5420 txq = ctx->ifc_txqs;
5421 rxq = ctx->ifc_rxqs;
5424 * XXX handle allocation failure
5426 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5427 /* Set up some basics */
5429 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5430 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5432 "Unable to allocate TX DMA info memory\n");
5436 txq->ift_ifdi = ifdip;
5437 for (j = 0; j < ntxqs; j++, ifdip++) {
5438 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5440 "Unable to allocate TX descriptors\n");
5444 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5445 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5449 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5450 txq->ift_br_offset = 1;
5452 txq->ift_br_offset = 0;
5455 txq->ift_timer.c_cpu = cpu;
5457 if (iflib_txsd_alloc(txq)) {
5458 device_printf(dev, "Critical Failure setting up TX buffers\n");
5463 /* Initialize the TX lock */
5464 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5465 device_get_nameunit(dev), txq->ift_id);
5466 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5467 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5469 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5470 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5472 /* XXX free any allocated rings */
5473 device_printf(dev, "Unable to allocate buf_ring\n");
5478 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5479 /* Set up some basics */
5481 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5482 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5484 "Unable to allocate RX DMA info memory\n");
5489 rxq->ifr_ifdi = ifdip;
5490 /* XXX this needs to be changed if #rx queues != #tx queues */
5491 rxq->ifr_ntxqirq = 1;
5492 rxq->ifr_txqid[0] = i;
5493 for (j = 0; j < nrxqs; j++, ifdip++) {
5494 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5496 "Unable to allocate RX descriptors\n");
5500 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5504 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5505 rxq->ifr_fl_offset = 1;
5507 rxq->ifr_fl_offset = 0;
5509 rxq->ifr_nfl = nfree_lists;
5511 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5512 device_printf(dev, "Unable to allocate free list memory\n");
5517 for (j = 0; j < nfree_lists; j++) {
5518 fl[j].ifl_rxq = rxq;
5520 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5521 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5523 /* Allocate receive buffers for the ring */
5524 if (iflib_rxsd_alloc(rxq)) {
5526 "Critical Failure setting up receive buffers\n");
5531 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5532 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5537 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5538 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5539 for (i = 0; i < ntxqsets; i++) {
5540 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5542 for (j = 0; j < ntxqs; j++, di++) {
5543 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5544 paddrs[i*ntxqs + j] = di->idi_paddr;
5547 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5548 device_printf(ctx->ifc_dev,
5549 "Unable to allocate device TX queue\n");
5550 iflib_tx_structures_free(ctx);
5551 free(vaddrs, M_IFLIB);
5552 free(paddrs, M_IFLIB);
5555 free(vaddrs, M_IFLIB);
5556 free(paddrs, M_IFLIB);
5559 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5560 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5561 for (i = 0; i < nrxqsets; i++) {
5562 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5564 for (j = 0; j < nrxqs; j++, di++) {
5565 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5566 paddrs[i*nrxqs + j] = di->idi_paddr;
5569 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5570 device_printf(ctx->ifc_dev,
5571 "Unable to allocate device RX queue\n");
5572 iflib_tx_structures_free(ctx);
5573 free(vaddrs, M_IFLIB);
5574 free(paddrs, M_IFLIB);
5577 free(vaddrs, M_IFLIB);
5578 free(paddrs, M_IFLIB);
5582 /* XXX handle allocation failure changes */
5586 if (ctx->ifc_rxqs != NULL)
5587 free(ctx->ifc_rxqs, M_IFLIB);
5588 ctx->ifc_rxqs = NULL;
5589 if (ctx->ifc_txqs != NULL)
5590 free(ctx->ifc_txqs, M_IFLIB);
5591 ctx->ifc_txqs = NULL;
5597 iflib_tx_structures_setup(if_ctx_t ctx)
5599 iflib_txq_t txq = ctx->ifc_txqs;
5602 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5603 iflib_txq_setup(txq);
5609 iflib_tx_structures_free(if_ctx_t ctx)
5611 iflib_txq_t txq = ctx->ifc_txqs;
5612 if_shared_ctx_t sctx = ctx->ifc_sctx;
5615 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5616 iflib_txq_destroy(txq);
5617 for (j = 0; j < sctx->isc_ntxqs; j++)
5618 iflib_dma_free(&txq->ift_ifdi[j]);
5620 free(ctx->ifc_txqs, M_IFLIB);
5621 ctx->ifc_txqs = NULL;
5622 IFDI_QUEUES_FREE(ctx);
5625 /*********************************************************************
5627 * Initialize all receive rings.
5629 **********************************************************************/
5631 iflib_rx_structures_setup(if_ctx_t ctx)
5633 iflib_rxq_t rxq = ctx->ifc_rxqs;
5635 #if defined(INET6) || defined(INET)
5639 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5640 #if defined(INET6) || defined(INET)
5641 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5642 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5643 TCP_LRO_ENTRIES, min(1024,
5644 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5646 device_printf(ctx->ifc_dev,
5647 "LRO Initialization failed!\n");
5652 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5655 #if defined(INET6) || defined(INET)
5658 * Free LRO resources allocated so far, we will only handle
5659 * the rings that completed, the failing case will have
5660 * cleaned up for itself. 'q' failed, so its the terminus.
5662 rxq = ctx->ifc_rxqs;
5663 for (i = 0; i < q; ++i, rxq++) {
5664 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5665 tcp_lro_free(&rxq->ifr_lc);
5671 /*********************************************************************
5673 * Free all receive rings.
5675 **********************************************************************/
5677 iflib_rx_structures_free(if_ctx_t ctx)
5679 iflib_rxq_t rxq = ctx->ifc_rxqs;
5682 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5683 iflib_rx_sds_free(rxq);
5684 #if defined(INET6) || defined(INET)
5685 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5686 tcp_lro_free(&rxq->ifr_lc);
5689 free(ctx->ifc_rxqs, M_IFLIB);
5690 ctx->ifc_rxqs = NULL;
5694 iflib_qset_structures_setup(if_ctx_t ctx)
5699 * It is expected that the caller takes care of freeing queues if this
5702 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5703 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5707 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5708 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5714 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5715 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5718 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5723 find_nth(if_ctx_t ctx, int qid)
5726 int i, cpuid, eqid, count;
5728 CPU_COPY(&ctx->ifc_cpus, &cpus);
5729 count = CPU_COUNT(&cpus);
5731 /* clear up to the qid'th bit */
5732 for (i = 0; i < eqid; i++) {
5733 cpuid = CPU_FFS(&cpus);
5735 CPU_CLR(cpuid-1, &cpus);
5737 cpuid = CPU_FFS(&cpus);
5743 extern struct cpu_group *cpu_top; /* CPU topology */
5746 find_child_with_core(int cpu, struct cpu_group *grp)
5750 if (grp->cg_children == 0)
5753 MPASS(grp->cg_child);
5754 for (i = 0; i < grp->cg_children; i++) {
5755 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5763 * Find the nth "close" core to the specified core
5764 * "close" is defined as the deepest level that shares
5765 * at least an L2 cache. With threads, this will be
5766 * threads on the same core. If the shared cache is L3
5767 * or higher, simply returns the same core.
5770 find_close_core(int cpu, int core_offset)
5772 struct cpu_group *grp;
5781 while ((i = find_child_with_core(cpu, grp)) != -1) {
5782 /* If the child only has one cpu, don't descend */
5783 if (grp->cg_child[i].cg_count <= 1)
5785 grp = &grp->cg_child[i];
5788 /* If they don't share at least an L2 cache, use the same CPU */
5789 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5793 CPU_COPY(&grp->cg_mask, &cs);
5795 /* Add the selected CPU offset to core offset. */
5796 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5797 if (fcpu - 1 == cpu)
5799 CPU_CLR(fcpu - 1, &cs);
5805 CPU_COPY(&grp->cg_mask, &cs);
5806 for (i = core_offset % grp->cg_count; i > 0; i--) {
5807 MPASS(CPU_FFS(&cs));
5808 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5810 MPASS(CPU_FFS(&cs));
5811 return CPU_FFS(&cs) - 1;
5815 find_close_core(int cpu, int core_offset __unused)
5822 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5826 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5827 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5828 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5830 case IFLIB_INTR_RXTX:
5831 /* RX queues get the specified core */
5832 return qid / CPU_COUNT(&ctx->ifc_cpus);
5838 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5839 #define find_close_core(cpuid, tid) CPU_FIRST()
5840 #define find_nth(ctx, gid) CPU_FIRST()
5843 /* Just to avoid copy/paste */
5845 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5846 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5850 int co, cpuid, err, tid;
5853 co = ctx->ifc_sysctl_core_offset;
5854 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5855 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5856 cpuid = find_nth(ctx, qid + co);
5857 tid = get_core_offset(ctx, type, qid);
5859 device_printf(dev, "get_core_offset failed\n");
5860 return (EOPNOTSUPP);
5862 cpuid = find_close_core(cpuid, tid);
5863 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5866 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5870 if (cpuid > ctx->ifc_cpuid_highest)
5871 ctx->ifc_cpuid_highest = cpuid;
5877 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5878 iflib_intr_type_t type, driver_filter_t *filter,
5879 void *filter_arg, int qid, const char *name)
5882 struct grouptask *gtask;
5883 struct taskqgroup *tqg;
5884 iflib_filter_info_t info;
5887 driver_filter_t *intr_fast;
5890 info = &ctx->ifc_filter_info;
5894 /* XXX merge tx/rx for netmap? */
5896 q = &ctx->ifc_txqs[qid];
5897 info = &ctx->ifc_txqs[qid].ift_filter_info;
5898 gtask = &ctx->ifc_txqs[qid].ift_task;
5899 tqg = qgroup_if_io_tqg;
5901 intr_fast = iflib_fast_intr;
5902 GROUPTASK_INIT(gtask, 0, fn, q);
5903 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5906 q = &ctx->ifc_rxqs[qid];
5907 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5908 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5909 tqg = qgroup_if_io_tqg;
5911 intr_fast = iflib_fast_intr;
5912 GROUPTASK_INIT(gtask, 0, fn, q);
5914 case IFLIB_INTR_RXTX:
5915 q = &ctx->ifc_rxqs[qid];
5916 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5917 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5918 tqg = qgroup_if_io_tqg;
5920 intr_fast = iflib_fast_intr_rxtx;
5921 GROUPTASK_INIT(gtask, 0, fn, q);
5923 case IFLIB_INTR_ADMIN:
5926 info = &ctx->ifc_filter_info;
5927 gtask = &ctx->ifc_admin_task;
5928 tqg = qgroup_if_config_tqg;
5929 fn = _task_fn_admin;
5930 intr_fast = iflib_fast_intr_ctx;
5933 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5938 info->ifi_filter = filter;
5939 info->ifi_filter_arg = filter_arg;
5940 info->ifi_task = gtask;
5944 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5946 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5949 if (type == IFLIB_INTR_ADMIN)
5953 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5958 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
5965 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5967 struct grouptask *gtask;
5968 struct taskqgroup *tqg;
5975 q = &ctx->ifc_txqs[qid];
5976 gtask = &ctx->ifc_txqs[qid].ift_task;
5977 tqg = qgroup_if_io_tqg;
5981 q = &ctx->ifc_rxqs[qid];
5982 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5983 tqg = qgroup_if_io_tqg;
5986 case IFLIB_INTR_IOV:
5988 gtask = &ctx->ifc_vflr_task;
5989 tqg = qgroup_if_config_tqg;
5993 panic("unknown net intr type");
5995 GROUPTASK_INIT(gtask, 0, fn, q);
5997 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6000 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6003 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6008 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6012 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6015 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6016 rman_get_rid(irq->ii_res), irq->ii_res);
6020 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6022 iflib_txq_t txq = ctx->ifc_txqs;
6023 iflib_rxq_t rxq = ctx->ifc_rxqs;
6024 if_irq_t irq = &ctx->ifc_legacy_irq;
6025 iflib_filter_info_t info;
6027 struct grouptask *gtask;
6028 struct resource *res;
6029 struct taskqgroup *tqg;
6034 q = &ctx->ifc_rxqs[0];
6035 info = &rxq[0].ifr_filter_info;
6036 gtask = &rxq[0].ifr_task;
6037 tqg = qgroup_if_io_tqg;
6041 ctx->ifc_flags |= IFC_LEGACY;
6042 info->ifi_filter = filter;
6043 info->ifi_filter_arg = filter_arg;
6044 info->ifi_task = gtask;
6048 /* We allocate a single interrupt resource */
6049 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx,
6050 NULL, info, name)) != 0)
6052 GROUPTASK_INIT(gtask, 0, fn, q);
6054 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6056 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6057 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6063 iflib_led_create(if_ctx_t ctx)
6066 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6067 device_get_nameunit(ctx->ifc_dev));
6071 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6074 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6078 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6081 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6085 iflib_admin_intr_deferred(if_ctx_t ctx)
6088 struct grouptask *gtask;
6090 gtask = &ctx->ifc_admin_task;
6091 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6094 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6098 iflib_iov_intr_deferred(if_ctx_t ctx)
6101 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6105 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6108 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6113 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6117 GROUPTASK_INIT(gtask, 0, fn, ctx);
6118 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6123 iflib_config_gtask_deinit(struct grouptask *gtask)
6126 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6130 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6132 if_t ifp = ctx->ifc_ifp;
6133 iflib_txq_t txq = ctx->ifc_txqs;
6135 if_setbaudrate(ifp, baudrate);
6136 if (baudrate >= IF_Gbps(10)) {
6138 ctx->ifc_flags |= IFC_PREFETCH;
6141 /* If link down, disable watchdog */
6142 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6143 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6144 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6146 ctx->ifc_link_state = link_state;
6147 if_link_state_change(ifp, link_state);
6151 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6155 int credits_pre = txq->ift_cidx_processed;
6158 if (ctx->isc_txd_credits_update == NULL)
6161 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6162 BUS_DMASYNC_POSTREAD);
6163 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6166 txq->ift_processed += credits;
6167 txq->ift_cidx_processed += credits;
6169 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6170 if (txq->ift_cidx_processed >= txq->ift_size)
6171 txq->ift_cidx_processed -= txq->ift_size;
6176 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6181 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6182 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6183 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6184 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6189 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6190 const char *description, if_int_delay_info_t info,
6191 int offset, int value)
6193 info->iidi_ctx = ctx;
6194 info->iidi_offset = offset;
6195 info->iidi_value = value;
6196 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6197 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6198 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6199 info, 0, iflib_sysctl_int_delay, "I", description);
6203 iflib_ctx_lock_get(if_ctx_t ctx)
6206 return (&ctx->ifc_ctx_sx);
6210 iflib_msix_init(if_ctx_t ctx)
6212 device_t dev = ctx->ifc_dev;
6213 if_shared_ctx_t sctx = ctx->ifc_sctx;
6214 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6215 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6216 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6218 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6219 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6222 device_printf(dev, "msix_init qsets capped at %d\n",
6223 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6225 /* Override by tuneable */
6226 if (scctx->isc_disable_msix)
6229 /* First try MSI-X */
6230 if ((msgs = pci_msix_count(dev)) == 0) {
6232 device_printf(dev, "MSI-X not supported or disabled\n");
6236 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6238 * bar == -1 => "trust me I know what I'm doing"
6239 * Some drivers are for hardware that is so shoddily
6240 * documented that no one knows which bars are which
6241 * so the developer has to map all bars. This hack
6242 * allows shoddy garbage to use MSI-X in this framework.
6245 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6246 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6247 if (ctx->ifc_msix_mem == NULL) {
6248 device_printf(dev, "Unable to map MSI-X table\n");
6253 admincnt = sctx->isc_admin_intrcnt;
6255 /* use only 1 qset in debug mode */
6256 queuemsgs = min(msgs - admincnt, 1);
6258 queuemsgs = msgs - admincnt;
6261 queues = imin(queuemsgs, rss_getnumbuckets());
6265 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6268 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6269 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6271 /* If we're doing RSS, clamp at the number of RSS buckets */
6272 if (queues > rss_getnumbuckets())
6273 queues = rss_getnumbuckets();
6275 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6276 rx_queues = iflib_num_rx_queues;
6280 if (rx_queues > scctx->isc_nrxqsets)
6281 rx_queues = scctx->isc_nrxqsets;
6284 * We want this to be all logical CPUs by default
6286 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6287 tx_queues = iflib_num_tx_queues;
6289 tx_queues = mp_ncpus;
6291 if (tx_queues > scctx->isc_ntxqsets)
6292 tx_queues = scctx->isc_ntxqsets;
6294 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6296 if (tx_queues != rx_queues)
6298 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6299 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6301 tx_queues = min(rx_queues, tx_queues);
6302 rx_queues = min(rx_queues, tx_queues);
6305 vectors = rx_queues + admincnt;
6306 if (msgs < vectors) {
6308 "insufficient number of MSI-X vectors "
6309 "(supported %d, need %d)\n", msgs, vectors);
6313 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6316 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6317 if (vectors != msgs) {
6319 "Unable to allocate sufficient MSI-X vectors "
6320 "(got %d, need %d)\n", vectors, msgs);
6321 pci_release_msi(dev);
6323 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6325 ctx->ifc_msix_mem = NULL;
6329 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6331 scctx->isc_vectors = vectors;
6332 scctx->isc_nrxqsets = rx_queues;
6333 scctx->isc_ntxqsets = tx_queues;
6334 scctx->isc_intr = IFLIB_INTR_MSIX;
6339 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6342 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6344 ctx->ifc_msix_mem = NULL;
6349 vectors = pci_msi_count(dev);
6350 scctx->isc_nrxqsets = 1;
6351 scctx->isc_ntxqsets = 1;
6352 scctx->isc_vectors = vectors;
6353 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6354 device_printf(dev,"Using an MSI interrupt\n");
6355 scctx->isc_intr = IFLIB_INTR_MSI;
6357 scctx->isc_vectors = 1;
6358 device_printf(dev,"Using a Legacy interrupt\n");
6359 scctx->isc_intr = IFLIB_INTR_LEGACY;
6365 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6368 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6371 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6373 const char *ring_state = "UNKNOWN";
6376 rc = sysctl_wire_old_buffer(req, 0);
6380 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6385 ring_state = ring_states[state[3]];
6387 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6388 state[0], state[1], state[2], ring_state);
6389 rc = sbuf_finish(sb);
6394 enum iflib_ndesc_handler {
6400 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6402 if_ctx_t ctx = (void *)arg1;
6403 enum iflib_ndesc_handler type = arg2;
6404 char buf[256] = {0};
6411 case IFLIB_NTXD_HANDLER:
6412 ndesc = ctx->ifc_sysctl_ntxds;
6414 nqs = ctx->ifc_sctx->isc_ntxqs;
6416 case IFLIB_NRXD_HANDLER:
6417 ndesc = ctx->ifc_sysctl_nrxds;
6419 nqs = ctx->ifc_sctx->isc_nrxqs;
6422 printf("%s: unhandled type\n", __func__);
6428 for (i=0; i<8; i++) {
6433 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6436 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6437 if (rc || req->newptr == NULL)
6440 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6441 i++, p = strsep(&next, " ,")) {
6442 ndesc[i] = strtoul(p, NULL, 10);
6448 #define NAME_BUFLEN 32
6450 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6452 device_t dev = iflib_get_dev(ctx);
6453 struct sysctl_oid_list *child, *oid_list;
6454 struct sysctl_ctx_list *ctx_list;
6455 struct sysctl_oid *node;
6457 ctx_list = device_get_sysctl_ctx(dev);
6458 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6459 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6460 CTLFLAG_RD, NULL, "IFLIB fields");
6461 oid_list = SYSCTL_CHILDREN(node);
6463 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6464 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6467 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6468 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6469 "# of txqs to use, 0 => use default #");
6470 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6471 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6472 "# of rxqs to use, 0 => use default #");
6473 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6474 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6475 "permit #txq != #rxq");
6476 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6477 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6478 "disable MSI-X (default 0)");
6479 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6480 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6481 "set the RX budget");
6482 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6483 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6484 "cause TX to abdicate instead of running to completion");
6485 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6486 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6487 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6488 "offset to start using cores at");
6489 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6490 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6491 "use separate cores for TX and RX");
6493 /* XXX change for per-queue sizes */
6494 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6495 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6496 mp_ndesc_handler, "A",
6497 "list of # of TX descriptors to use, 0 = use default #");
6498 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6499 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6500 mp_ndesc_handler, "A",
6501 "list of # of RX descriptors to use, 0 = use default #");
6505 iflib_add_device_sysctl_post(if_ctx_t ctx)
6507 if_shared_ctx_t sctx = ctx->ifc_sctx;
6508 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6509 device_t dev = iflib_get_dev(ctx);
6510 struct sysctl_oid_list *child;
6511 struct sysctl_ctx_list *ctx_list;
6516 char namebuf[NAME_BUFLEN];
6518 struct sysctl_oid *queue_node, *fl_node, *node;
6519 struct sysctl_oid_list *queue_list, *fl_list;
6520 ctx_list = device_get_sysctl_ctx(dev);
6522 node = ctx->ifc_sysctl_node;
6523 child = SYSCTL_CHILDREN(node);
6525 if (scctx->isc_ntxqsets > 100)
6527 else if (scctx->isc_ntxqsets > 10)
6531 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6532 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6533 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6534 CTLFLAG_RD, NULL, "Queue Name");
6535 queue_list = SYSCTL_CHILDREN(queue_node);
6537 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6539 &txq->ift_dequeued, "total mbufs freed");
6540 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6542 &txq->ift_enqueued, "total mbufs enqueued");
6544 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6546 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6547 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6549 &txq->ift_pullups, "# of times m_pullup was called");
6550 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6552 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6553 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6555 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6556 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6558 &txq->ift_map_failed, "# of times DMA map failed");
6559 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6561 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6562 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6564 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6565 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6567 &txq->ift_pidx, 1, "Producer Index");
6568 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6570 &txq->ift_cidx, 1, "Consumer Index");
6571 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6573 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6574 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6576 &txq->ift_in_use, 1, "descriptors in use");
6577 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6579 &txq->ift_processed, "descriptors procesed for clean");
6580 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6582 &txq->ift_cleaned, "total cleaned");
6583 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6584 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6585 0, mp_ring_state_handler, "A", "soft ring state");
6586 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6587 CTLFLAG_RD, &txq->ift_br->enqueues,
6588 "# of enqueues to the mp_ring for this queue");
6589 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6590 CTLFLAG_RD, &txq->ift_br->drops,
6591 "# of drops in the mp_ring for this queue");
6592 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6593 CTLFLAG_RD, &txq->ift_br->starts,
6594 "# of normal consumer starts in the mp_ring for this queue");
6595 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6596 CTLFLAG_RD, &txq->ift_br->stalls,
6597 "# of consumer stalls in the mp_ring for this queue");
6598 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6599 CTLFLAG_RD, &txq->ift_br->restarts,
6600 "# of consumer restarts in the mp_ring for this queue");
6601 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6602 CTLFLAG_RD, &txq->ift_br->abdications,
6603 "# of consumer abdications in the mp_ring for this queue");
6606 if (scctx->isc_nrxqsets > 100)
6608 else if (scctx->isc_nrxqsets > 10)
6612 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6613 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6614 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6615 CTLFLAG_RD, NULL, "Queue Name");
6616 queue_list = SYSCTL_CHILDREN(queue_node);
6617 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6618 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6620 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6623 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6624 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6625 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6626 CTLFLAG_RD, NULL, "freelist Name");
6627 fl_list = SYSCTL_CHILDREN(fl_node);
6628 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6630 &fl->ifl_pidx, 1, "Producer Index");
6631 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6633 &fl->ifl_cidx, 1, "Consumer Index");
6634 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6636 &fl->ifl_credits, 1, "credits available");
6638 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6640 &fl->ifl_m_enqueued, "mbufs allocated");
6641 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6643 &fl->ifl_m_dequeued, "mbufs freed");
6644 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6646 &fl->ifl_cl_enqueued, "clusters allocated");
6647 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6649 &fl->ifl_cl_dequeued, "clusters freed");
6658 iflib_request_reset(if_ctx_t ctx)
6662 ctx->ifc_flags |= IFC_DO_RESET;
6666 #ifndef __NO_STRICT_ALIGNMENT
6667 static struct mbuf *
6668 iflib_fixup_rx(struct mbuf *m)
6672 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6673 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6674 m->m_data += ETHER_HDR_LEN;
6677 MGETHDR(n, M_NOWAIT, MT_DATA);
6682 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6683 m->m_data += ETHER_HDR_LEN;
6684 m->m_len -= ETHER_HDR_LEN;
6685 n->m_len = ETHER_HDR_LEN;
6686 M_MOVE_PKTHDR(n, m);
6695 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6699 ctx = if_getsoftc(ifp);
6701 *nrxr = NRXQSETS(ctx);
6702 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6703 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6708 iflib_netdump_event(if_t ifp, enum netdump_ev event)
6711 if_softc_ctx_t scctx;
6716 ctx = if_getsoftc(ifp);
6717 scctx = &ctx->ifc_softc_ctx;
6721 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6722 rxq = &ctx->ifc_rxqs[i];
6723 for (j = 0; j < rxq->ifr_nfl; j++) {
6725 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6728 iflib_no_tx_batch = 1;
6736 iflib_netdump_transmit(if_t ifp, struct mbuf *m)
6742 ctx = if_getsoftc(ifp);
6743 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6747 txq = &ctx->ifc_txqs[0];
6748 error = iflib_encap(txq, &m);
6750 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6755 iflib_netdump_poll(if_t ifp, int count)
6758 if_softc_ctx_t scctx;
6762 ctx = if_getsoftc(ifp);
6763 scctx = &ctx->ifc_softc_ctx;
6765 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6769 txq = &ctx->ifc_txqs[0];
6770 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6772 for (i = 0; i < scctx->isc_nrxqsets; i++)
6773 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6776 #endif /* NETDUMP */