2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
96 #include <dev/pci/pci_iov.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
177 int ifc_watchdog_events;
178 struct cdev *ifc_led_dev;
179 struct resource *ifc_msix_mem;
181 struct if_irq ifc_legacy_irq;
182 struct grouptask ifc_admin_task;
183 struct grouptask ifc_vflr_task;
184 struct iflib_filter_info ifc_filter_info;
185 struct ifmedia ifc_media;
187 struct sysctl_oid *ifc_sysctl_node;
188 uint16_t ifc_sysctl_ntxqs;
189 uint16_t ifc_sysctl_nrxqs;
190 uint16_t ifc_sysctl_qs_eq_override;
191 uint16_t ifc_sysctl_rx_budget;
192 uint16_t ifc_sysctl_tx_abdicate;
194 qidx_t ifc_sysctl_ntxds[8];
195 qidx_t ifc_sysctl_nrxds[8];
196 struct if_txrx ifc_txrx;
197 #define isc_txd_encap ifc_txrx.ift_txd_encap
198 #define isc_txd_flush ifc_txrx.ift_txd_flush
199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
200 #define isc_rxd_available ifc_txrx.ift_rxd_available
201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
207 eventhandler_tag ifc_vlan_attach_event;
208 eventhandler_tag ifc_vlan_detach_event;
209 uint8_t ifc_mac[ETHER_ADDR_LEN];
210 char ifc_mtx_name[16];
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (&ctx->ifc_media);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 /* bnxt supports 64 with hardware LRO enabled */
292 #define IFLIB_MAX_RX_SEGS 64
293 #define IFLIB_RX_COPY_THRESH 128
294 #define IFLIB_MAX_RX_REFRESH 32
295 /* The minimum descriptors per second before we start coalescing */
296 #define IFLIB_MIN_DESC_SEC 16384
297 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
298 #define IFLIB_QUEUE_IDLE 0
299 #define IFLIB_QUEUE_HUNG 1
300 #define IFLIB_QUEUE_WORKING 2
301 /* maximum number of txqs that can share an rx interrupt */
302 #define IFLIB_MAX_TX_SHARED_INTR 4
304 /* this should really scale with ring size - this is a fairly arbitrary value */
305 #define TX_BATCH_SIZE 32
307 #define IFLIB_RESTART_BUDGET 8
310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
316 qidx_t ift_cidx_processed;
319 uint8_t ift_br_offset;
320 uint16_t ift_npending;
321 uint16_t ift_db_pending;
322 uint16_t ift_rs_pending;
324 uint8_t ift_txd_size[8];
325 uint64_t ift_processed;
326 uint64_t ift_cleaned;
327 uint64_t ift_cleaned_prev;
329 uint64_t ift_enqueued;
330 uint64_t ift_dequeued;
332 uint64_t ift_no_tx_dma_setup;
333 uint64_t ift_no_desc_avail;
334 uint64_t ift_mbuf_defrag_failed;
335 uint64_t ift_mbuf_defrag;
336 uint64_t ift_map_failed;
337 uint64_t ift_txd_encap_efbig;
338 uint64_t ift_pullups;
339 uint64_t ift_last_timer_tick;
342 struct mtx ift_db_mtx;
344 /* constant values */
346 struct ifmp_ring *ift_br;
347 struct grouptask ift_task;
350 struct callout ift_timer;
352 if_txsd_vec_t ift_sds;
355 uint8_t ift_update_freq;
356 struct iflib_filter_info ift_filter_info;
357 bus_dma_tag_t ift_desc_tag;
358 bus_dma_tag_t ift_tso_desc_tag;
359 iflib_dma_info_t ift_ifdi;
360 #define MTX_NAME_LEN 16
361 char ift_mtx_name[MTX_NAME_LEN];
362 char ift_db_mtx_name[MTX_NAME_LEN];
363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
364 #ifdef IFLIB_DIAGNOSTICS
365 uint64_t ift_cpu_exec_count[256];
367 } __aligned(CACHE_LINE_SIZE);
374 uint8_t ifl_rxd_size;
376 uint64_t ifl_m_enqueued;
377 uint64_t ifl_m_dequeued;
378 uint64_t ifl_cl_enqueued;
379 uint64_t ifl_cl_dequeued;
383 bitstr_t *ifl_rx_bitmap;
387 uint16_t ifl_buf_size;
390 iflib_rxsd_array_t ifl_sds;
393 bus_dma_tag_t ifl_desc_tag;
394 iflib_dma_info_t ifl_ifdi;
395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
396 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
397 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
398 } __aligned(CACHE_LINE_SIZE);
401 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
407 else if (pidx < cidx)
408 used = size - cidx + pidx;
409 else if (gen == 0 && pidx == cidx)
411 else if (gen == 1 && pidx == cidx)
419 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
421 #define IDXDIFF(head, tail, wrap) \
422 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
425 /* If there is a separate completion queue -
426 * these are the cq cidx and pidx. Otherwise
433 uint8_t ifr_fl_offset;
439 uint8_t ifr_lro_enabled;
442 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
443 struct lro_ctrl ifr_lc;
444 struct grouptask ifr_task;
445 struct iflib_filter_info ifr_filter_info;
446 iflib_dma_info_t ifr_ifdi;
448 /* dynamically allocate if any drivers need a value substantially larger than this */
449 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
450 #ifdef IFLIB_DIAGNOSTICS
451 uint64_t ifr_cpu_exec_count[256];
453 } __aligned(CACHE_LINE_SIZE);
455 typedef struct if_rxsd {
457 struct mbuf **ifsd_m;
462 /* multiple of word size */
464 #define PKT_INFO_SIZE 6
465 #define RXD_INFO_SIZE 5
466 #define PKT_TYPE uint64_t
468 #define PKT_INFO_SIZE 11
469 #define RXD_INFO_SIZE 8
470 #define PKT_TYPE uint32_t
472 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
473 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
475 typedef struct if_pkt_info_pad {
476 PKT_TYPE pkt_val[PKT_INFO_SIZE];
477 } *if_pkt_info_pad_t;
478 typedef struct if_rxd_info_pad {
479 PKT_TYPE rxd_val[RXD_INFO_SIZE];
480 } *if_rxd_info_pad_t;
482 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
483 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
487 pkt_info_zero(if_pkt_info_t pi)
489 if_pkt_info_pad_t pi_pad;
491 pi_pad = (if_pkt_info_pad_t)pi;
492 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
493 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
495 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
496 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
500 static device_method_t iflib_pseudo_methods[] = {
501 DEVMETHOD(device_attach, noop_attach),
502 DEVMETHOD(device_detach, iflib_pseudo_detach),
506 driver_t iflib_pseudodriver = {
507 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
511 rxd_info_zero(if_rxd_info_t ri)
513 if_rxd_info_pad_t ri_pad;
516 ri_pad = (if_rxd_info_pad_t)ri;
517 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
518 ri_pad->rxd_val[i] = 0;
519 ri_pad->rxd_val[i+1] = 0;
520 ri_pad->rxd_val[i+2] = 0;
521 ri_pad->rxd_val[i+3] = 0;
524 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
529 * Only allow a single packet to take up most 1/nth of the tx ring
531 #define MAX_SINGLE_PACKET_FRACTION 12
532 #define IF_BAD_DMA (bus_addr_t)-1
534 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
536 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
537 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
538 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
539 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
542 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
543 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
544 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
545 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
549 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
550 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
553 iflib_set_detach(if_ctx_t ctx)
556 ctx->ifc_flags |= IFC_IN_DETACH;
560 /* Our boot-time initialization hook */
561 static int iflib_module_event_handler(module_t, int, void *);
563 static moduledata_t iflib_moduledata = {
565 iflib_module_event_handler,
569 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
570 MODULE_VERSION(iflib, 1);
572 MODULE_DEPEND(iflib, pci, 1, 1, 1);
573 MODULE_DEPEND(iflib, ether, 1, 1, 1);
575 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
576 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
578 #ifndef IFLIB_DEBUG_COUNTERS
580 #define IFLIB_DEBUG_COUNTERS 1
582 #define IFLIB_DEBUG_COUNTERS 0
583 #endif /* !INVARIANTS */
586 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
587 "iflib driver parameters");
590 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
592 static int iflib_min_tx_latency = 0;
593 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
594 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
595 static int iflib_no_tx_batch = 0;
596 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
597 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
600 #if IFLIB_DEBUG_COUNTERS
602 static int iflib_tx_seen;
603 static int iflib_tx_sent;
604 static int iflib_tx_encap;
605 static int iflib_rx_allocs;
606 static int iflib_fl_refills;
607 static int iflib_fl_refills_large;
608 static int iflib_tx_frees;
610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
611 &iflib_tx_seen, 0, "# tx mbufs seen");
612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
613 &iflib_tx_sent, 0, "# tx mbufs sent");
614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
615 &iflib_tx_encap, 0, "# tx mbufs encapped");
616 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
617 &iflib_tx_frees, 0, "# tx frees");
618 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
619 &iflib_rx_allocs, 0, "# rx allocations");
620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
621 &iflib_fl_refills, 0, "# refills");
622 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
623 &iflib_fl_refills_large, 0, "# large refills");
626 static int iflib_txq_drain_flushing;
627 static int iflib_txq_drain_oactive;
628 static int iflib_txq_drain_notready;
630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
631 &iflib_txq_drain_flushing, 0, "# drain flushes");
632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
633 &iflib_txq_drain_oactive, 0, "# drain oactives");
634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
635 &iflib_txq_drain_notready, 0, "# drain notready");
638 static int iflib_encap_load_mbuf_fail;
639 static int iflib_encap_pad_mbuf_fail;
640 static int iflib_encap_txq_avail_fail;
641 static int iflib_encap_txd_encap_fail;
643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
652 static int iflib_task_fn_rxs;
653 static int iflib_rx_intr_enables;
654 static int iflib_fast_intrs;
655 static int iflib_rx_unavail;
656 static int iflib_rx_ctx_inactive;
657 static int iflib_rx_if_input;
658 static int iflib_rx_mbuf_null;
659 static int iflib_rxd_flush;
661 static int iflib_verbose_debug;
663 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
664 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
666 &iflib_rx_intr_enables, 0, "# rx intr enables");
667 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
668 &iflib_fast_intrs, 0, "# fast_intr calls");
669 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
670 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
671 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
672 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
673 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
674 &iflib_rx_if_input, 0, "# times rxeof called if_input");
675 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
676 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
677 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
678 &iflib_rxd_flush, 0, "# times rxd_flush called");
679 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
680 &iflib_verbose_debug, 0, "enable verbose debugging");
682 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
684 iflib_debug_reset(void)
686 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
687 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
688 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
689 iflib_txq_drain_notready =
690 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
691 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
692 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
694 iflib_rx_ctx_inactive = iflib_rx_if_input =
695 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
699 #define DBG_COUNTER_INC(name)
700 static void iflib_debug_reset(void) {}
703 #define IFLIB_DEBUG 0
705 static void iflib_tx_structures_free(if_ctx_t ctx);
706 static void iflib_rx_structures_free(if_ctx_t ctx);
707 static int iflib_queues_alloc(if_ctx_t ctx);
708 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
709 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
710 static int iflib_qset_structures_setup(if_ctx_t ctx);
711 static int iflib_msix_init(if_ctx_t ctx);
712 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
713 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
714 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
716 static void iflib_altq_if_start(if_t ifp);
717 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
719 static int iflib_register(if_ctx_t);
720 static void iflib_init_locked(if_ctx_t ctx);
721 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
722 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
723 static void iflib_ifmp_purge(iflib_txq_t txq);
724 static void _iflib_pre_assert(if_softc_ctx_t scctx);
725 static void iflib_if_init_locked(if_ctx_t ctx);
726 static void iflib_free_intr_mem(if_ctx_t ctx);
727 #ifndef __NO_STRICT_ALIGNMENT
728 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
731 NETDUMP_DEFINE(iflib);
734 #include <sys/selinfo.h>
735 #include <net/netmap.h>
736 #include <dev/netmap/netmap_kern.h>
738 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
740 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
743 * device-specific sysctl variables:
745 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
746 * During regular operations the CRC is stripped, but on some
747 * hardware reception of frames not multiple of 64 is slower,
748 * so using crcstrip=0 helps in benchmarks.
750 * iflib_rx_miss, iflib_rx_miss_bufs:
751 * count packets that might be missed due to lost interrupts.
753 SYSCTL_DECL(_dev_netmap);
755 * The xl driver by default strips CRCs and we do not override it.
758 int iflib_crcstrip = 1;
759 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
760 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
762 int iflib_rx_miss, iflib_rx_miss_bufs;
763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
764 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
765 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
766 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
769 * Register/unregister. We are already under netmap lock.
770 * Only called on the first register or the last unregister.
773 iflib_netmap_register(struct netmap_adapter *na, int onoff)
775 struct ifnet *ifp = na->ifp;
776 if_ctx_t ctx = ifp->if_softc;
780 IFDI_INTR_DISABLE(ctx);
782 /* Tell the stack that the interface is no longer active */
783 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
786 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
788 /* enable or disable flags and callbacks in na and ifp */
790 nm_set_native_flags(na);
792 nm_clear_native_flags(na);
795 iflib_init_locked(ctx);
796 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
797 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
799 nm_clear_native_flags(na);
805 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
807 struct netmap_adapter *na = kring->na;
808 u_int const lim = kring->nkr_num_slots - 1;
809 u_int head = kring->rhead;
810 struct netmap_ring *ring = kring->ring;
812 struct if_rxd_update iru;
813 if_ctx_t ctx = rxq->ifr_ctx;
814 iflib_fl_t fl = &rxq->ifr_fl[0];
815 uint32_t refill_pidx, nic_i;
816 #if IFLIB_DEBUG_COUNTERS
820 if (nm_i == head && __predict_true(!init))
822 iru_init(&iru, rxq, 0 /* flid */);
823 map = fl->ifl_sds.ifsd_map;
824 refill_pidx = netmap_idx_k2n(kring, nm_i);
826 * IMPORTANT: we must leave one free slot in the ring,
827 * so move head back by one unit
829 head = nm_prev(head, lim);
831 DBG_COUNTER_INC(fl_refills);
832 while (nm_i != head) {
833 #if IFLIB_DEBUG_COUNTERS
835 DBG_COUNTER_INC(fl_refills_large);
837 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
838 struct netmap_slot *slot = &ring->slot[nm_i];
839 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
840 uint32_t nic_i_dma = refill_pidx;
841 nic_i = netmap_idx_k2n(kring, nm_i);
843 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
845 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
846 return netmap_ring_reinit(kring);
848 fl->ifl_vm_addrs[tmp_pidx] = addr;
849 if (__predict_false(init) && map) {
850 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
851 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
852 /* buffer has changed, reload map */
853 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
855 slot->flags &= ~NS_BUF_CHANGED;
857 nm_i = nm_next(nm_i, lim);
858 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
859 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
862 iru.iru_pidx = refill_pidx;
863 iru.iru_count = tmp_pidx+1;
864 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
870 for (int n = 0; n < iru.iru_count; n++) {
871 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
872 BUS_DMASYNC_PREREAD);
873 /* XXX - change this to not use the netmap func*/
874 nic_i_dma = nm_next(nic_i_dma, lim);
878 kring->nr_hwcur = head;
881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
883 if (__predict_true(nic_i != UINT_MAX)) {
884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
885 DBG_COUNTER_INC(rxd_flush);
891 * Reconcile kernel and user view of the transmit ring.
893 * All information is in the kring.
894 * Userspace wants to send packets up to the one before kring->rhead,
895 * kernel knows kring->nr_hwcur is the first unsent packet.
897 * Here we push packets out (as many as possible), and possibly
898 * reclaim buffers from previously completed transmission.
900 * The caller (netmap) guarantees that there is only one instance
901 * running at any time. Any interference with other driver
902 * methods should be handled by the individual drivers.
905 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
907 struct netmap_adapter *na = kring->na;
908 struct ifnet *ifp = na->ifp;
909 struct netmap_ring *ring = kring->ring;
910 u_int nm_i; /* index into the netmap kring */
911 u_int nic_i; /* index into the NIC ring */
913 u_int const lim = kring->nkr_num_slots - 1;
914 u_int const head = kring->rhead;
915 struct if_pkt_info pi;
918 * interrupts on every tx packet are expensive so request
919 * them every half ring, or where NS_REPORT is set
921 u_int report_frequency = kring->nkr_num_slots >> 1;
922 /* device-specific */
923 if_ctx_t ctx = ifp->if_softc;
924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
926 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
931 * First part: process new packets to send.
932 * nm_i is the current index in the netmap kring,
933 * nic_i is the corresponding index in the NIC ring.
935 * If we have packets to send (nm_i != head)
936 * iterate over the netmap ring, fetch length and update
937 * the corresponding slot in the NIC ring. Some drivers also
938 * need to update the buffer's physical address in the NIC slot
939 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
941 * The netmap_reload_map() calls is especially expensive,
942 * even when (as in this case) the tag is 0, so do only
943 * when the buffer has actually changed.
945 * If possible do not set the report/intr bit on all slots,
946 * but only a few times per ring or when NS_REPORT is set.
948 * Finally, on 10G and faster drivers, it might be useful
949 * to prefetch the next slot and txr entry.
952 nm_i = kring->nr_hwcur;
953 if (nm_i != head) { /* we have new packets to send */
955 pi.ipi_segs = txq->ift_segs;
956 pi.ipi_qsidx = kring->ring_id;
957 nic_i = netmap_idx_k2n(kring, nm_i);
959 __builtin_prefetch(&ring->slot[nm_i]);
960 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
961 if (txq->ift_sds.ifsd_map)
962 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
964 for (n = 0; nm_i != head; n++) {
965 struct netmap_slot *slot = &ring->slot[nm_i];
966 u_int len = slot->len;
968 void *addr = PNMB(na, slot, &paddr);
969 int flags = (slot->flags & NS_REPORT ||
970 nic_i == 0 || nic_i == report_frequency) ?
973 /* device-specific */
975 pi.ipi_segs[0].ds_addr = paddr;
976 pi.ipi_segs[0].ds_len = len;
980 pi.ipi_flags = flags;
982 /* Fill the slot in the NIC ring. */
983 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
984 DBG_COUNTER_INC(tx_encap);
986 /* prefetch for next round */
987 __builtin_prefetch(&ring->slot[nm_i + 1]);
988 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
989 if (txq->ift_sds.ifsd_map) {
990 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
992 NM_CHECK_ADDR_LEN(na, addr, len);
994 if (slot->flags & NS_BUF_CHANGED) {
995 /* buffer has changed, reload map */
996 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
998 /* make sure changes to the buffer are synced */
999 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1000 BUS_DMASYNC_PREWRITE);
1002 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1003 nm_i = nm_next(nm_i, lim);
1004 nic_i = nm_next(nic_i, lim);
1006 kring->nr_hwcur = nm_i;
1008 /* synchronize the NIC ring */
1009 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1010 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1012 /* (re)start the tx unit up to slot nic_i (excluded) */
1013 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1017 * Second part: reclaim buffers for completed transmissions.
1019 * If there are unclaimed buffers, attempt to reclaim them.
1020 * If none are reclaimed, and TX IRQs are not in use, do an initial
1021 * minimal delay, then trigger the tx handler which will spin in the
1024 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1025 if (iflib_tx_credits_update(ctx, txq)) {
1026 /* some tx completed, increment avail */
1027 nic_i = txq->ift_cidx_processed;
1028 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1031 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1032 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1033 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1034 iflib_timer, txq, txq->ift_timer.c_cpu);
1040 * Reconcile kernel and user view of the receive ring.
1041 * Same as for the txsync, this routine must be efficient.
1042 * The caller guarantees a single invocations, but races against
1043 * the rest of the driver should be handled here.
1045 * On call, kring->rhead is the first packet that userspace wants
1046 * to keep, and kring->rcur is the wakeup point.
1047 * The kernel has previously reported packets up to kring->rtail.
1049 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1050 * of whether or not we received an interrupt.
1053 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1055 struct netmap_adapter *na = kring->na;
1056 struct netmap_ring *ring = kring->ring;
1057 uint32_t nm_i; /* index into the netmap ring */
1058 uint32_t nic_i; /* index into the NIC ring */
1060 u_int const lim = kring->nkr_num_slots - 1;
1061 u_int const head = kring->rhead;
1062 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1063 struct if_rxd_info ri;
1065 struct ifnet *ifp = na->ifp;
1066 if_ctx_t ctx = ifp->if_softc;
1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1068 iflib_fl_t fl = rxq->ifr_fl;
1070 return netmap_ring_reinit(kring);
1072 /* XXX check sync modes */
1073 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1074 if (fl->ifl_sds.ifsd_map == NULL)
1076 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1080 * First part: import newly received packets.
1082 * nm_i is the index of the next free slot in the netmap ring,
1083 * nic_i is the index of the next received packet in the NIC ring,
1084 * and they may differ in case if_init() has been called while
1085 * in netmap mode. For the receive ring we have
1087 * nic_i = rxr->next_check;
1088 * nm_i = kring->nr_hwtail (previous)
1090 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1092 * rxr->next_check is set to 0 on a ring reinit
1094 if (netmap_no_pendintr || force_update) {
1095 int crclen = iflib_crcstrip ? 0 : 4;
1098 for (i = 0; i < rxq->ifr_nfl; i++) {
1099 fl = &rxq->ifr_fl[i];
1100 nic_i = fl->ifl_cidx;
1101 nm_i = netmap_idx_n2k(kring, nic_i);
1102 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1103 for (n = 0; avail > 0; n++, avail--) {
1105 ri.iri_frags = rxq->ifr_frags;
1106 ri.iri_qsidx = kring->ring_id;
1107 ri.iri_ifp = ctx->ifc_ifp;
1108 ri.iri_cidx = nic_i;
1110 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1111 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1112 ring->slot[nm_i].flags = 0;
1113 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1114 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1115 nm_i = nm_next(nm_i, lim);
1116 nic_i = nm_next(nic_i, lim);
1118 if (n) { /* update the state variables */
1119 if (netmap_no_pendintr && !force_update) {
1122 iflib_rx_miss_bufs += n;
1124 fl->ifl_cidx = nic_i;
1125 kring->nr_hwtail = nm_i;
1127 kring->nr_kflags &= ~NKR_PENDINTR;
1131 * Second part: skip past packets that userspace has released.
1132 * (kring->nr_hwcur to head excluded),
1133 * and make the buffers available for reception.
1134 * As usual nm_i is the index in the netmap ring,
1135 * nic_i is the index in the NIC ring, and
1136 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1138 /* XXX not sure how this will work with multiple free lists */
1139 nm_i = kring->nr_hwcur;
1141 return (netmap_fl_refill(rxq, kring, nm_i, false));
1145 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1147 struct ifnet *ifp = na->ifp;
1148 if_ctx_t ctx = ifp->if_softc;
1152 IFDI_INTR_ENABLE(ctx);
1154 IFDI_INTR_DISABLE(ctx);
1161 iflib_netmap_attach(if_ctx_t ctx)
1163 struct netmap_adapter na;
1164 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1166 bzero(&na, sizeof(na));
1168 na.ifp = ctx->ifc_ifp;
1169 na.na_flags = NAF_BDG_MAYSLEEP;
1170 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1171 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1173 na.num_tx_desc = scctx->isc_ntxd[0];
1174 na.num_rx_desc = scctx->isc_nrxd[0];
1175 na.nm_txsync = iflib_netmap_txsync;
1176 na.nm_rxsync = iflib_netmap_rxsync;
1177 na.nm_register = iflib_netmap_register;
1178 na.nm_intr = iflib_netmap_intr;
1179 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1180 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1181 return (netmap_attach(&na));
1185 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1187 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1188 struct netmap_slot *slot;
1190 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1193 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1196 * In netmap mode, set the map for the packet buffer.
1197 * NOTE: Some drivers (not this one) also need to set
1198 * the physical buffer address in the NIC ring.
1199 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1200 * netmap slot index, si
1202 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1203 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1208 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1210 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1211 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1212 struct netmap_slot *slot;
1215 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1218 nm_i = netmap_idx_n2k(kring, 0);
1219 netmap_fl_refill(rxq, kring, nm_i, true);
1223 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1225 struct netmap_kring *kring;
1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1230 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1231 netmap_tx_irq(ctx->ifc_ifp, txqid);
1232 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1236 *reset_on = hz / 1000;
1241 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1244 #define iflib_netmap_txq_init(ctx, txq)
1245 #define iflib_netmap_rxq_init(ctx, rxq)
1246 #define iflib_netmap_detach(ifp)
1248 #define iflib_netmap_attach(ctx) (0)
1249 #define netmap_rx_irq(ifp, qid, budget) (0)
1250 #define netmap_tx_irq(ifp, qid) do {} while (0)
1251 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1255 #if defined(__i386__) || defined(__amd64__)
1256 static __inline void
1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1261 static __inline void
1262 prefetch2cachelines(void *x)
1264 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1265 #if (CACHE_LINE_SIZE < 128)
1266 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1271 #define prefetch2cachelines(x)
1275 iflib_gen_mac(if_ctx_t ctx)
1279 char uuid[HOSTUUIDLEN+1];
1280 char buf[HOSTUUIDLEN+16];
1282 unsigned char digest[16];
1286 uuid[HOSTUUIDLEN] = 0;
1287 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1288 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1290 * Generate a pseudo-random, deterministic MAC
1291 * address based on the UUID and unit number.
1292 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1295 MD5Update(&mdctx, buf, strlen(buf));
1296 MD5Final(digest, &mdctx);
1307 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1311 fl = &rxq->ifr_fl[flid];
1312 iru->iru_paddrs = fl->ifl_bus_addrs;
1313 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1314 iru->iru_idxs = fl->ifl_rxd_idxs;
1315 iru->iru_qsidx = rxq->ifr_id;
1316 iru->iru_buf_size = fl->ifl_buf_size;
1317 iru->iru_flidx = fl->ifl_id;
1321 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1325 *(bus_addr_t *) arg = segs[0].ds_addr;
1329 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1332 if_shared_ctx_t sctx = ctx->ifc_sctx;
1333 device_t dev = ctx->ifc_dev;
1335 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1337 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1338 sctx->isc_q_align, 0, /* alignment, bounds */
1339 BUS_SPACE_MAXADDR, /* lowaddr */
1340 BUS_SPACE_MAXADDR, /* highaddr */
1341 NULL, NULL, /* filter, filterarg */
1344 size, /* maxsegsize */
1345 BUS_DMA_ALLOCNOW, /* flags */
1346 NULL, /* lockfunc */
1351 "%s: bus_dma_tag_create failed: %d\n",
1356 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1357 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1360 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1361 __func__, (uintmax_t)size, err);
1365 dma->idi_paddr = IF_BAD_DMA;
1366 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1367 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1368 if (err || dma->idi_paddr == IF_BAD_DMA) {
1370 "%s: bus_dmamap_load failed: %d\n",
1375 dma->idi_size = size;
1379 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1381 bus_dma_tag_destroy(dma->idi_tag);
1383 dma->idi_tag = NULL;
1389 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1392 iflib_dma_info_t *dmaiter;
1395 for (i = 0; i < count; i++, dmaiter++) {
1396 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1400 iflib_dma_free_multi(dmalist, i);
1405 iflib_dma_free(iflib_dma_info_t dma)
1407 if (dma->idi_tag == NULL)
1409 if (dma->idi_paddr != IF_BAD_DMA) {
1410 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1411 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1412 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1413 dma->idi_paddr = IF_BAD_DMA;
1415 if (dma->idi_vaddr != NULL) {
1416 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1417 dma->idi_vaddr = NULL;
1419 bus_dma_tag_destroy(dma->idi_tag);
1420 dma->idi_tag = NULL;
1424 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1427 iflib_dma_info_t *dmaiter = dmalist;
1429 for (i = 0; i < count; i++, dmaiter++)
1430 iflib_dma_free(*dmaiter);
1433 #ifdef EARLY_AP_STARTUP
1434 static const int iflib_started = 1;
1437 * We used to abuse the smp_started flag to decide if the queues have been
1438 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1439 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1440 * is set. Run a SYSINIT() strictly after that to just set a usable
1444 static int iflib_started;
1447 iflib_record_started(void *arg)
1452 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1453 iflib_record_started, NULL);
1457 iflib_fast_intr(void *arg)
1459 iflib_filter_info_t info = arg;
1460 struct grouptask *gtask = info->ifi_task;
1462 return (FILTER_HANDLED);
1464 DBG_COUNTER_INC(fast_intrs);
1465 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1466 return (FILTER_HANDLED);
1468 GROUPTASK_ENQUEUE(gtask);
1469 return (FILTER_HANDLED);
1473 iflib_fast_intr_rxtx(void *arg)
1475 iflib_filter_info_t info = arg;
1476 struct grouptask *gtask = info->ifi_task;
1477 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1478 if_ctx_t ctx = NULL;;
1482 return (FILTER_HANDLED);
1484 DBG_COUNTER_INC(fast_intrs);
1485 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1486 return (FILTER_HANDLED);
1488 MPASS(rxq->ifr_ntxqirq);
1489 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1490 qidx_t txqid = rxq->ifr_txqid[i];
1494 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1495 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1498 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1500 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1501 cidx = rxq->ifr_cq_cidx;
1503 cidx = rxq->ifr_fl[0].ifl_cidx;
1504 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1505 GROUPTASK_ENQUEUE(gtask);
1507 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1508 DBG_COUNTER_INC(rx_intr_enables);
1510 return (FILTER_HANDLED);
1515 iflib_fast_intr_ctx(void *arg)
1517 iflib_filter_info_t info = arg;
1518 struct grouptask *gtask = info->ifi_task;
1521 return (FILTER_HANDLED);
1523 DBG_COUNTER_INC(fast_intrs);
1524 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1525 return (FILTER_HANDLED);
1527 GROUPTASK_ENQUEUE(gtask);
1528 return (FILTER_HANDLED);
1532 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1533 driver_filter_t filter, driver_intr_t handler, void *arg,
1537 struct resource *res;
1539 device_t dev = ctx->ifc_dev;
1542 if (ctx->ifc_flags & IFC_LEGACY)
1543 flags |= RF_SHAREABLE;
1546 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1549 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1553 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1554 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1555 filter, handler, arg, &tag);
1558 "failed to setup interrupt for rid %d, name %s: %d\n",
1559 rid, name ? name : "unknown", rc);
1562 bus_describe_intr(dev, res, tag, "%s", name);
1569 /*********************************************************************
1571 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1572 * the information needed to transmit a packet on the wire. This is
1573 * called only once at attach, setup is done every reset.
1575 **********************************************************************/
1578 iflib_txsd_alloc(iflib_txq_t txq)
1580 if_ctx_t ctx = txq->ift_ctx;
1581 if_shared_ctx_t sctx = ctx->ifc_sctx;
1582 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1583 device_t dev = ctx->ifc_dev;
1584 bus_size_t tsomaxsize;
1585 int err, nsegments, ntsosegments;
1587 nsegments = scctx->isc_tx_nsegments;
1588 ntsosegments = scctx->isc_tx_tso_segments_max;
1589 tsomaxsize = scctx->isc_tx_tso_size_max;
1590 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1591 tsomaxsize += sizeof(struct ether_vlan_header);
1592 MPASS(scctx->isc_ntxd[0] > 0);
1593 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1594 MPASS(nsegments > 0);
1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1596 MPASS(ntsosegments > 0);
1597 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1601 * Setup DMA descriptor areas.
1603 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1604 1, 0, /* alignment, bounds */
1605 BUS_SPACE_MAXADDR, /* lowaddr */
1606 BUS_SPACE_MAXADDR, /* highaddr */
1607 NULL, NULL, /* filter, filterarg */
1608 sctx->isc_tx_maxsize, /* maxsize */
1609 nsegments, /* nsegments */
1610 sctx->isc_tx_maxsegsize, /* maxsegsize */
1612 NULL, /* lockfunc */
1613 NULL, /* lockfuncarg */
1614 &txq->ift_desc_tag))) {
1615 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1616 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1617 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1620 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) &
1621 (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1622 1, 0, /* alignment, bounds */
1623 BUS_SPACE_MAXADDR, /* lowaddr */
1624 BUS_SPACE_MAXADDR, /* highaddr */
1625 NULL, NULL, /* filter, filterarg */
1626 tsomaxsize, /* maxsize */
1627 ntsosegments, /* nsegments */
1628 sctx->isc_tso_maxsegsize,/* maxsegsize */
1630 NULL, /* lockfunc */
1631 NULL, /* lockfuncarg */
1632 &txq->ift_tso_desc_tag))) {
1633 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1637 if (!(txq->ift_sds.ifsd_m =
1638 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1639 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1640 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1645 /* Create the descriptor buffer dma maps */
1646 if (!(txq->ift_sds.ifsd_map =
1647 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1648 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1653 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1654 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1656 device_printf(dev, "Unable to create TX DMA map\n");
1662 /* We free all, it handles case where we are in the middle */
1663 iflib_tx_structures_free(ctx);
1668 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1673 if (txq->ift_sds.ifsd_map != NULL)
1674 map = txq->ift_sds.ifsd_map[i];
1676 bus_dmamap_unload(txq->ift_desc_tag, map);
1677 bus_dmamap_destroy(txq->ift_desc_tag, map);
1678 txq->ift_sds.ifsd_map[i] = NULL;
1683 iflib_txq_destroy(iflib_txq_t txq)
1685 if_ctx_t ctx = txq->ift_ctx;
1687 for (int i = 0; i < txq->ift_size; i++)
1688 iflib_txsd_destroy(ctx, txq, i);
1689 if (txq->ift_sds.ifsd_map != NULL) {
1690 free(txq->ift_sds.ifsd_map, M_IFLIB);
1691 txq->ift_sds.ifsd_map = NULL;
1693 if (txq->ift_sds.ifsd_m != NULL) {
1694 free(txq->ift_sds.ifsd_m, M_IFLIB);
1695 txq->ift_sds.ifsd_m = NULL;
1697 if (txq->ift_desc_tag != NULL) {
1698 bus_dma_tag_destroy(txq->ift_desc_tag);
1699 txq->ift_desc_tag = NULL;
1701 if (txq->ift_tso_desc_tag != NULL) {
1702 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1703 txq->ift_tso_desc_tag = NULL;
1708 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1712 mp = &txq->ift_sds.ifsd_m[i];
1716 if (txq->ift_sds.ifsd_map != NULL) {
1717 bus_dmamap_sync(txq->ift_desc_tag,
1718 txq->ift_sds.ifsd_map[i],
1719 BUS_DMASYNC_POSTWRITE);
1720 bus_dmamap_unload(txq->ift_desc_tag,
1721 txq->ift_sds.ifsd_map[i]);
1724 DBG_COUNTER_INC(tx_frees);
1729 iflib_txq_setup(iflib_txq_t txq)
1731 if_ctx_t ctx = txq->ift_ctx;
1732 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1733 if_shared_ctx_t sctx = ctx->ifc_sctx;
1734 iflib_dma_info_t di;
1737 /* Set number of descriptors available */
1738 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1739 /* XXX make configurable */
1740 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1743 txq->ift_cidx_processed = 0;
1744 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1745 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1747 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1748 bzero((void *)di->idi_vaddr, di->idi_size);
1750 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1751 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1752 bus_dmamap_sync(di->idi_tag, di->idi_map,
1753 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1757 /*********************************************************************
1759 * Allocate memory for rx_buffer structures. Since we use one
1760 * rx_buffer per received packet, the maximum number of rx_buffer's
1761 * that we'll need is equal to the number of receive descriptors
1762 * that we've allocated.
1764 **********************************************************************/
1766 iflib_rxsd_alloc(iflib_rxq_t rxq)
1768 if_ctx_t ctx = rxq->ifr_ctx;
1769 if_shared_ctx_t sctx = ctx->ifc_sctx;
1770 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1771 device_t dev = ctx->ifc_dev;
1775 MPASS(scctx->isc_nrxd[0] > 0);
1776 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1779 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1780 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1781 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1782 1, 0, /* alignment, bounds */
1783 BUS_SPACE_MAXADDR, /* lowaddr */
1784 BUS_SPACE_MAXADDR, /* highaddr */
1785 NULL, NULL, /* filter, filterarg */
1786 sctx->isc_rx_maxsize, /* maxsize */
1787 sctx->isc_rx_nsegments, /* nsegments */
1788 sctx->isc_rx_maxsegsize, /* maxsegsize */
1790 NULL, /* lockfunc */
1794 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1798 if (!(fl->ifl_sds.ifsd_m =
1799 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1800 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1801 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1805 if (!(fl->ifl_sds.ifsd_cl =
1806 (caddr_t *) malloc(sizeof(caddr_t) *
1807 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1808 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1813 if (!(fl->ifl_sds.ifsd_ba =
1814 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1815 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1816 device_printf(dev, "Unable to allocate rx bus addr memory\n");
1821 /* Create the descriptor buffer dma maps */
1822 if (!(fl->ifl_sds.ifsd_map =
1823 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1824 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1829 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1830 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1832 device_printf(dev, "Unable to create RX buffer DMA map\n");
1840 iflib_rx_structures_free(ctx);
1846 * Internal service routines
1849 struct rxq_refill_cb_arg {
1851 bus_dma_segment_t seg;
1856 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1858 struct rxq_refill_cb_arg *cb_arg = arg;
1860 cb_arg->error = error;
1861 cb_arg->seg = segs[0];
1862 cb_arg->nseg = nseg;
1866 * rxq_refill - refill an rxq free-buffer list
1867 * @ctx: the iflib context
1868 * @rxq: the free-list to refill
1869 * @n: the number of new buffers to allocate
1871 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1872 * The caller must assure that @n does not exceed the queue's capacity.
1875 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1878 int idx, frag_idx = fl->ifl_fragidx;
1879 int pidx = fl->ifl_pidx;
1882 struct if_rxd_update iru;
1883 struct rxq_refill_cb_arg cb_arg;
1884 bus_dmamap_t *sd_map;
1886 bus_addr_t bus_addr, *sd_ba;
1890 sd_m = fl->ifl_sds.ifsd_m;
1891 sd_map = fl->ifl_sds.ifsd_map;
1892 sd_cl = fl->ifl_sds.ifsd_cl;
1893 sd_ba = fl->ifl_sds.ifsd_ba;
1895 credits = fl->ifl_credits;
1899 MPASS(credits + n <= fl->ifl_size);
1901 if (pidx < fl->ifl_cidx)
1902 MPASS(pidx + n <= fl->ifl_cidx);
1903 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1904 MPASS(fl->ifl_gen == 0);
1905 if (pidx > fl->ifl_cidx)
1906 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1908 DBG_COUNTER_INC(fl_refills);
1910 DBG_COUNTER_INC(fl_refills_large);
1911 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1914 * We allocate an uninitialized mbuf + cluster, mbuf is
1915 * initialized after rx.
1917 * If the cluster is still set then we know a minimum sized packet was received
1919 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1920 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1921 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1922 if ((cl = sd_cl[frag_idx]) == NULL) {
1923 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1927 MPASS(sd_map != NULL);
1928 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1929 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1930 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1931 BUS_DMASYNC_PREREAD);
1933 if (err != 0 || cb_arg.error) {
1937 if (fl->ifl_zone == zone_pack)
1938 uma_zfree(fl->ifl_zone, cl);
1942 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
1943 sd_cl[frag_idx] = cl;
1945 fl->ifl_cl_enqueued++;
1948 bus_addr = sd_ba[frag_idx];
1951 bit_set(fl->ifl_rx_bitmap, frag_idx);
1952 MPASS(sd_m[frag_idx] == NULL);
1953 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1958 fl->ifl_m_enqueued++;
1961 DBG_COUNTER_INC(rx_allocs);
1962 fl->ifl_rxd_idxs[i] = frag_idx;
1963 fl->ifl_bus_addrs[i] = bus_addr;
1964 fl->ifl_vm_addrs[i] = cl;
1967 MPASS(credits <= fl->ifl_size);
1968 if (++idx == fl->ifl_size) {
1972 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1973 iru.iru_pidx = pidx;
1975 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1979 fl->ifl_credits = credits;
1985 iru.iru_pidx = pidx;
1987 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1989 fl->ifl_credits = credits;
1991 DBG_COUNTER_INC(rxd_flush);
1992 if (fl->ifl_pidx == 0)
1993 pidx = fl->ifl_size - 1;
1995 pidx = fl->ifl_pidx - 1;
1997 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1999 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2000 fl->ifl_fragidx = frag_idx;
2003 static __inline void
2004 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2006 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2007 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2009 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2012 MPASS(fl->ifl_credits <= fl->ifl_size);
2013 MPASS(reclaimable == delta);
2015 if (reclaimable > 0)
2016 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2020 iflib_in_detach(if_ctx_t ctx)
2024 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2030 iflib_fl_bufs_free(iflib_fl_t fl)
2032 iflib_dma_info_t idi = fl->ifl_ifdi;
2035 for (i = 0; i < fl->ifl_size; i++) {
2036 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2037 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2039 if (*sd_cl != NULL) {
2040 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
2041 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2043 uma_zfree(fl->ifl_zone, *sd_cl);
2044 // XXX: Should this get moved out?
2045 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2046 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2047 if (*sd_m != NULL) {
2048 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2049 uma_zfree(zone_mbuf, *sd_m);
2052 MPASS(*sd_cl == NULL);
2053 MPASS(*sd_m == NULL);
2056 fl->ifl_m_dequeued++;
2057 fl->ifl_cl_dequeued++;
2063 for (i = 0; i < fl->ifl_size; i++) {
2064 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2065 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2069 * Reset free list values
2071 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2072 bzero(idi->idi_vaddr, idi->idi_size);
2075 /*********************************************************************
2077 * Initialize a receive ring and its buffers.
2079 **********************************************************************/
2081 iflib_fl_setup(iflib_fl_t fl)
2083 iflib_rxq_t rxq = fl->ifl_rxq;
2084 if_ctx_t ctx = rxq->ifr_ctx;
2085 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2087 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2089 ** Free current RX buffer structs and their mbufs
2091 iflib_fl_bufs_free(fl);
2092 /* Now replenish the mbufs */
2093 MPASS(fl->ifl_credits == 0);
2095 * XXX don't set the max_frame_size to larger
2096 * than the hardware can handle
2098 if (sctx->isc_max_frame_size <= 2048)
2099 fl->ifl_buf_size = MCLBYTES;
2100 #ifndef CONTIGMALLOC_WORKS
2102 fl->ifl_buf_size = MJUMPAGESIZE;
2104 else if (sctx->isc_max_frame_size <= 4096)
2105 fl->ifl_buf_size = MJUMPAGESIZE;
2106 else if (sctx->isc_max_frame_size <= 9216)
2107 fl->ifl_buf_size = MJUM9BYTES;
2109 fl->ifl_buf_size = MJUM16BYTES;
2111 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2112 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2113 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2114 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2117 /* avoid pre-allocating zillions of clusters to an idle card
2118 * potentially speeding up attach
2120 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2121 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2122 if (min(128, fl->ifl_size) != fl->ifl_credits)
2128 MPASS(fl->ifl_ifdi != NULL);
2129 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2134 /*********************************************************************
2136 * Free receive ring data structures
2138 **********************************************************************/
2140 iflib_rx_sds_free(iflib_rxq_t rxq)
2145 if (rxq->ifr_fl != NULL) {
2146 for (i = 0; i < rxq->ifr_nfl; i++) {
2147 fl = &rxq->ifr_fl[i];
2148 if (fl->ifl_desc_tag != NULL) {
2149 bus_dma_tag_destroy(fl->ifl_desc_tag);
2150 fl->ifl_desc_tag = NULL;
2152 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2153 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2154 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2155 /* XXX destroy maps first */
2156 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2157 fl->ifl_sds.ifsd_m = NULL;
2158 fl->ifl_sds.ifsd_cl = NULL;
2159 fl->ifl_sds.ifsd_ba = NULL;
2160 fl->ifl_sds.ifsd_map = NULL;
2162 free(rxq->ifr_fl, M_IFLIB);
2164 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2169 * MI independent logic
2173 iflib_timer(void *arg)
2175 iflib_txq_t txq = arg;
2176 if_ctx_t ctx = txq->ift_ctx;
2177 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2178 uint64_t this_tick = ticks;
2179 uint32_t reset_on = hz / 2;
2181 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2184 ** Check on the state of the TX queue(s), this
2185 ** can be done without the lock because its RO
2186 ** and the HUNG state will be static if set.
2188 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2189 txq->ift_last_timer_tick = this_tick;
2190 IFDI_TIMER(ctx, txq->ift_id);
2191 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2192 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2193 (sctx->isc_pause_frames == 0)))
2196 if (ifmp_ring_is_stalled(txq->ift_br))
2197 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2198 txq->ift_cleaned_prev = txq->ift_cleaned;
2201 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2202 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2204 /* handle any laggards */
2205 if (txq->ift_db_pending)
2206 GROUPTASK_ENQUEUE(&txq->ift_task);
2208 sctx->isc_pause_frames = 0;
2209 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2210 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2213 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2214 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2216 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2217 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2218 iflib_admin_intr_deferred(ctx);
2223 iflib_init_locked(if_ctx_t ctx)
2225 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2226 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2227 if_t ifp = ctx->ifc_ifp;
2231 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2234 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2235 IFDI_INTR_DISABLE(ctx);
2237 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2238 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2239 /* Set hardware offload abilities */
2240 if_clearhwassist(ifp);
2241 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2242 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2243 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2244 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2245 if (if_getcapenable(ifp) & IFCAP_TSO4)
2246 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2247 if (if_getcapenable(ifp) & IFCAP_TSO6)
2248 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2250 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2252 callout_stop(&txq->ift_timer);
2253 CALLOUT_UNLOCK(txq);
2254 iflib_netmap_txq_init(ctx, txq);
2257 i = if_getdrvflags(ifp);
2260 MPASS(if_getdrvflags(ifp) == i);
2261 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2262 /* XXX this should really be done on a per-queue basis */
2263 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2264 MPASS(rxq->ifr_id == i);
2265 iflib_netmap_rxq_init(ctx, rxq);
2268 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2269 if (iflib_fl_setup(fl)) {
2270 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2276 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2277 IFDI_INTR_ENABLE(ctx);
2278 txq = ctx->ifc_txqs;
2279 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2280 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2281 txq->ift_timer.c_cpu);
2285 iflib_media_change(if_t ifp)
2287 if_ctx_t ctx = if_getsoftc(ifp);
2291 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2292 iflib_init_locked(ctx);
2298 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2300 if_ctx_t ctx = if_getsoftc(ifp);
2303 IFDI_UPDATE_ADMIN_STATUS(ctx);
2304 IFDI_MEDIA_STATUS(ctx, ifmr);
2309 iflib_stop(if_ctx_t ctx)
2311 iflib_txq_t txq = ctx->ifc_txqs;
2312 iflib_rxq_t rxq = ctx->ifc_rxqs;
2313 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2314 if_shared_ctx_t sctx = ctx->ifc_sctx;
2315 iflib_dma_info_t di;
2319 /* Tell the stack that the interface is no longer active */
2320 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2322 IFDI_INTR_DISABLE(ctx);
2327 iflib_debug_reset();
2328 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2329 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2330 /* make sure all transmitters have completed before proceeding XXX */
2333 callout_stop(&txq->ift_timer);
2334 CALLOUT_UNLOCK(txq);
2336 /* clean any enqueued buffers */
2337 iflib_ifmp_purge(txq);
2338 /* Free any existing tx buffers. */
2339 for (j = 0; j < txq->ift_size; j++) {
2340 iflib_txsd_free(ctx, txq, j);
2342 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2343 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2344 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2345 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2346 txq->ift_pullups = 0;
2347 ifmp_ring_reset_stats(txq->ift_br);
2348 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2349 bzero((void *)di->idi_vaddr, di->idi_size);
2351 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2352 /* make sure all transmitters have completed before proceeding XXX */
2354 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2355 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2356 bzero((void *)di->idi_vaddr, di->idi_size);
2357 /* also resets the free lists pidx/cidx */
2358 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2359 iflib_fl_bufs_free(fl);
2363 static inline caddr_t
2364 calc_next_rxd(iflib_fl_t fl, int cidx)
2368 caddr_t start, end, cur, next;
2370 nrxd = fl->ifl_size;
2371 size = fl->ifl_rxd_size;
2372 start = fl->ifl_ifdi->idi_vaddr;
2374 if (__predict_false(size == 0))
2376 cur = start + size*cidx;
2377 end = start + size*nrxd;
2378 next = CACHE_PTR_NEXT(cur);
2379 return (next < end ? next : start);
2383 prefetch_pkts(iflib_fl_t fl, int cidx)
2386 int nrxd = fl->ifl_size;
2390 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2391 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2392 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2393 next_rxd = calc_next_rxd(fl, cidx);
2395 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2396 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2397 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2398 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2399 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2400 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2401 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2402 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2406 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2411 iflib_dma_info_t di;
2415 flid = irf->irf_flid;
2416 cidx = irf->irf_idx;
2417 fl = &rxq->ifr_fl[flid];
2419 sd->ifsd_cidx = cidx;
2420 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2421 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2424 fl->ifl_m_dequeued++;
2426 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2427 prefetch_pkts(fl, cidx);
2428 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2429 prefetch(&fl->ifl_sds.ifsd_map[next]);
2430 map = fl->ifl_sds.ifsd_map[cidx];
2432 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2433 bus_dmamap_sync(di->idi_tag, di->idi_map,
2434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2436 /* not valid assert if bxe really does SGE from non-contiguous elements */
2437 MPASS(fl->ifl_cidx == cidx);
2439 bus_dmamap_unload(fl->ifl_desc_tag, map);
2440 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2441 if (__predict_false(fl->ifl_cidx == 0))
2443 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2444 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2445 bit_clear(fl->ifl_rx_bitmap, cidx);
2448 static struct mbuf *
2449 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2451 int i, padlen , flags;
2452 struct mbuf *m, *mh, *mt;
2458 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2460 MPASS(*sd->ifsd_cl != NULL);
2461 MPASS(*sd->ifsd_m != NULL);
2463 /* Don't include zero-length frags */
2464 if (ri->iri_frags[i].irf_len == 0) {
2465 /* XXX we can save the cluster here, but not the mbuf */
2466 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2467 m_free(*sd->ifsd_m);
2474 flags = M_PKTHDR|M_EXT;
2476 padlen = ri->iri_pad;
2481 /* assuming padding is only on the first fragment */
2485 *sd->ifsd_cl = NULL;
2487 /* Can these two be made one ? */
2488 m_init(m, M_NOWAIT, MT_DATA, flags);
2489 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2491 * These must follow m_init and m_cljset
2493 m->m_data += padlen;
2494 ri->iri_len -= padlen;
2495 m->m_len = ri->iri_frags[i].irf_len;
2496 } while (++i < ri->iri_nfrags);
2502 * Process one software descriptor
2504 static struct mbuf *
2505 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2510 /* should I merge this back in now that the two paths are basically duplicated? */
2511 if (ri->iri_nfrags == 1 &&
2512 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2513 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2516 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2517 #ifndef __NO_STRICT_ALIGNMENT
2521 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2522 m->m_len = ri->iri_frags[0].irf_len;
2524 m = assemble_segments(rxq, ri, &sd);
2526 m->m_pkthdr.len = ri->iri_len;
2527 m->m_pkthdr.rcvif = ri->iri_ifp;
2528 m->m_flags |= ri->iri_flags;
2529 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2530 m->m_pkthdr.flowid = ri->iri_flowid;
2531 M_HASHTYPE_SET(m, ri->iri_rsstype);
2532 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2533 m->m_pkthdr.csum_data = ri->iri_csum_data;
2537 #if defined(INET6) || defined(INET)
2539 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2541 CURVNET_SET(lc->ifp->if_vnet);
2543 *v6 = VNET(ip6_forwarding);
2546 *v4 = VNET(ipforwarding);
2552 * Returns true if it's possible this packet could be LROed.
2553 * if it returns false, it is guaranteed that tcp_lro_rx()
2554 * would not return zero.
2557 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2559 struct ether_header *eh;
2562 eh = mtod(m, struct ether_header *);
2563 eh_type = ntohs(eh->ether_type);
2566 case ETHERTYPE_IPV6:
2567 return !v6_forwarding;
2571 return !v4_forwarding;
2579 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2585 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2587 if_ctx_t ctx = rxq->ifr_ctx;
2588 if_shared_ctx_t sctx = ctx->ifc_sctx;
2589 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2592 struct if_rxd_info ri;
2593 int err, budget_left, rx_bytes, rx_pkts;
2597 bool v4_forwarding, v6_forwarding, lro_possible;
2600 * XXX early demux data packets so that if_input processing only handles
2601 * acks in interrupt context
2603 struct mbuf *m, *mh, *mt, *mf;
2605 lro_possible = v4_forwarding = v6_forwarding = false;
2609 rx_pkts = rx_bytes = 0;
2610 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2611 cidxp = &rxq->ifr_cq_cidx;
2613 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2614 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2615 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2616 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2617 DBG_COUNTER_INC(rx_unavail);
2621 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2622 if (__predict_false(!CTX_ACTIVE(ctx))) {
2623 DBG_COUNTER_INC(rx_ctx_inactive);
2627 * Reset client set fields to their default values
2630 ri.iri_qsidx = rxq->ifr_id;
2631 ri.iri_cidx = *cidxp;
2633 ri.iri_frags = rxq->ifr_frags;
2634 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2638 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2639 *cidxp = ri.iri_cidx;
2640 /* Update our consumer index */
2641 /* XXX NB: shurd - check if this is still safe */
2642 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2643 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2644 rxq->ifr_cq_gen = 0;
2646 /* was this only a completion queue message? */
2647 if (__predict_false(ri.iri_nfrags == 0))
2650 MPASS(ri.iri_nfrags != 0);
2651 MPASS(ri.iri_len != 0);
2653 /* will advance the cidx on the corresponding free lists */
2654 m = iflib_rxd_pkt_get(rxq, &ri);
2657 if (avail == 0 && budget_left)
2658 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2660 if (__predict_false(m == NULL)) {
2661 DBG_COUNTER_INC(rx_mbuf_null);
2664 /* imm_pkt: -- cxgb */
2672 /* make sure that we can refill faster than drain */
2673 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2674 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2676 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2678 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2680 while (mh != NULL) {
2683 m->m_nextpkt = NULL;
2684 #ifndef __NO_STRICT_ALIGNMENT
2685 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2688 rx_bytes += m->m_pkthdr.len;
2690 #if defined(INET6) || defined(INET)
2692 if (!lro_possible) {
2693 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2694 if (lro_possible && mf != NULL) {
2695 ifp->if_input(ifp, mf);
2696 DBG_COUNTER_INC(rx_if_input);
2700 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2701 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2702 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2708 ifp->if_input(ifp, m);
2709 DBG_COUNTER_INC(rx_if_input);
2720 ifp->if_input(ifp, mf);
2721 DBG_COUNTER_INC(rx_if_input);
2724 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2725 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2728 * Flush any outstanding LRO work
2730 #if defined(INET6) || defined(INET)
2731 tcp_lro_flush_all(&rxq->ifr_lc);
2735 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2738 ctx->ifc_flags |= IFC_DO_RESET;
2739 iflib_admin_intr_deferred(ctx);
2744 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2745 static inline qidx_t
2746 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2748 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2749 qidx_t minthresh = txq->ift_size / 8;
2750 if (in_use > 4*minthresh)
2751 return (notify_count);
2752 if (in_use > 2*minthresh)
2753 return (notify_count >> 1);
2754 if (in_use > minthresh)
2755 return (notify_count >> 3);
2759 static inline qidx_t
2760 txq_max_rs_deferred(iflib_txq_t txq)
2762 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2763 qidx_t minthresh = txq->ift_size / 8;
2764 if (txq->ift_in_use > 4*minthresh)
2765 return (notify_count);
2766 if (txq->ift_in_use > 2*minthresh)
2767 return (notify_count >> 1);
2768 if (txq->ift_in_use > minthresh)
2769 return (notify_count >> 2);
2773 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2774 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2776 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2777 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2778 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2780 /* forward compatibility for cxgb */
2781 #define FIRST_QSET(ctx) 0
2782 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2783 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2784 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2785 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2787 /* XXX we should be setting this to something other than zero */
2788 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2789 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2790 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2793 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2799 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2800 if (ring || txq->ift_db_pending >= max) {
2801 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2802 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2803 txq->ift_db_pending = txq->ift_npending = 0;
2811 print_pkt(if_pkt_info_t pi)
2813 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2814 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2815 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2816 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2817 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2818 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2822 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2823 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2824 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2825 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2828 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2830 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2831 struct ether_vlan_header *eh;
2835 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2836 M_WRITABLE(m) == 0) {
2837 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2841 DBG_COUNTER_INC(tx_frees);
2847 * Determine where frame payload starts.
2848 * Jump over vlan headers if already present,
2849 * helpful for QinQ too.
2851 if (__predict_false(m->m_len < sizeof(*eh))) {
2853 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2856 eh = mtod(m, struct ether_vlan_header *);
2857 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2858 pi->ipi_etype = ntohs(eh->evl_proto);
2859 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2861 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2862 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2865 switch (pi->ipi_etype) {
2870 struct ip *ip = NULL;
2871 struct tcphdr *th = NULL;
2874 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2875 if (__predict_false(m->m_len < minthlen)) {
2877 * if this code bloat is causing too much of a hit
2878 * move it to a separate function and mark it noinline
2880 if (m->m_len == pi->ipi_ehdrlen) {
2883 if (n->m_len >= sizeof(*ip)) {
2884 ip = (struct ip *)n->m_data;
2885 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2886 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2889 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2891 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2895 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2897 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2898 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2899 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2902 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2903 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2904 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2906 pi->ipi_ip_hlen = ip->ip_hl << 2;
2907 pi->ipi_ipproto = ip->ip_p;
2908 pi->ipi_flags |= IPI_TX_IPV4;
2910 /* TCP checksum offload may require TCP header length */
2911 if (IS_TX_OFFLOAD4(pi)) {
2912 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2913 if (__predict_false(th == NULL)) {
2915 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2917 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2919 pi->ipi_tcp_hflags = th->th_flags;
2920 pi->ipi_tcp_hlen = th->th_off << 2;
2921 pi->ipi_tcp_seq = th->th_seq;
2924 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2927 * TSO always requires hardware checksum offload.
2929 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
2930 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2931 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2932 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2933 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2935 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2939 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2946 case ETHERTYPE_IPV6:
2948 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2950 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2952 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2954 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2957 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2959 /* XXX-BZ this will go badly in case of ext hdrs. */
2960 pi->ipi_ipproto = ip6->ip6_nxt;
2961 pi->ipi_flags |= IPI_TX_IPV6;
2963 /* TCP checksum offload may require TCP header length */
2964 if (IS_TX_OFFLOAD6(pi)) {
2965 if (pi->ipi_ipproto == IPPROTO_TCP) {
2966 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2968 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2971 pi->ipi_tcp_hflags = th->th_flags;
2972 pi->ipi_tcp_hlen = th->th_off << 2;
2973 pi->ipi_tcp_seq = th->th_seq;
2976 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2979 * TSO always requires hardware checksum offload.
2981 pi->ipi_csum_flags |= CSUM_IP6_TCP;
2982 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2983 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2990 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2991 pi->ipi_ip_hlen = 0;
3000 * If dodgy hardware rejects the scatter gather chain we've handed it
3001 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3004 static __noinline struct mbuf *
3005 iflib_remove_mbuf(iflib_txq_t txq)
3008 struct mbuf *m, **ifsd_m;
3009 bus_dmamap_t *ifsd_map;
3011 ifsd_m = txq->ift_sds.ifsd_m;
3012 ntxd = txq->ift_size;
3013 pidx = txq->ift_pidx & (ntxd - 1);
3014 ifsd_m = txq->ift_sds.ifsd_m;
3015 ifsd_map = txq->ift_sds.ifsd_map;
3017 ifsd_m[pidx] = NULL;
3018 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[pidx]);
3020 txq->ift_dequeued++;
3025 static inline caddr_t
3026 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3030 caddr_t start, end, cur, next;
3032 ntxd = txq->ift_size;
3033 size = txq->ift_txd_size[qid];
3034 start = txq->ift_ifdi[qid].idi_vaddr;
3036 if (__predict_false(size == 0))
3038 cur = start + size*cidx;
3039 end = start + size*ntxd;
3040 next = CACHE_PTR_NEXT(cur);
3041 return (next < end ? next : start);
3045 * Pad an mbuf to ensure a minimum ethernet frame size.
3046 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3048 static __noinline int
3049 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3052 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3053 * and ARP message is the smallest common payload I can think of
3055 static char pad[18]; /* just zeros */
3057 struct mbuf *new_head;
3059 if (!M_WRITABLE(*m_head)) {
3060 new_head = m_dup(*m_head, M_NOWAIT);
3061 if (new_head == NULL) {
3063 device_printf(dev, "cannot pad short frame, m_dup() failed");
3064 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3065 DBG_COUNTER_INC(tx_frees);
3072 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3073 n > 0; n -= sizeof(pad))
3074 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3079 device_printf(dev, "cannot pad short frame\n");
3080 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3081 DBG_COUNTER_INC(tx_frees);
3089 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3092 if_shared_ctx_t sctx;
3093 if_softc_ctx_t scctx;
3094 bus_dma_segment_t *segs;
3095 struct mbuf *m_head, **ifsd_m;
3098 struct if_pkt_info pi;
3100 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3101 bus_dma_tag_t desc_tag;
3104 sctx = ctx->ifc_sctx;
3105 scctx = &ctx->ifc_softc_ctx;
3106 segs = txq->ift_segs;
3107 ntxd = txq->ift_size;
3112 * If we're doing TSO the next descriptor to clean may be quite far ahead
3114 cidx = txq->ift_cidx;
3115 pidx = txq->ift_pidx;
3116 if (ctx->ifc_flags & IFC_PREFETCH) {
3117 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3118 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3119 next_txd = calc_next_txd(txq, cidx, 0);
3123 /* prefetch the next cache line of mbuf pointers and flags */
3124 prefetch(&txq->ift_sds.ifsd_m[next]);
3125 prefetch(&txq->ift_sds.ifsd_map[next]);
3126 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3128 map = txq->ift_sds.ifsd_map[pidx];
3129 ifsd_m = txq->ift_sds.ifsd_m;
3131 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3132 desc_tag = txq->ift_tso_desc_tag;
3133 max_segs = scctx->isc_tx_tso_segments_max;
3134 MPASS(desc_tag != NULL);
3135 MPASS(max_segs > 0);
3137 desc_tag = txq->ift_desc_tag;
3138 max_segs = scctx->isc_tx_nsegments;
3140 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3141 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3142 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3144 DBG_COUNTER_INC(encap_txd_encap_fail);
3151 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3153 pi.ipi_qsidx = txq->ift_id;
3154 pi.ipi_len = m_head->m_pkthdr.len;
3155 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3156 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3158 /* deliberate bitwise OR to make one condition */
3159 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3160 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3161 DBG_COUNTER_INC(encap_txd_encap_fail);
3168 err = bus_dmamap_load_mbuf_sg(desc_tag, map, m_head, segs, &nsegs,
3171 if (__predict_false(err)) {
3174 /* try collapse once and defrag once */
3176 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3177 /* try defrag if collapsing fails */
3182 txq->ift_mbuf_defrag++;
3183 m_head = m_defrag(*m_headp, M_NOWAIT);
3186 if (__predict_false(m_head == NULL))
3192 txq->ift_no_tx_dma_setup++;
3195 txq->ift_no_tx_dma_setup++;
3197 DBG_COUNTER_INC(tx_frees);
3201 txq->ift_map_failed++;
3202 DBG_COUNTER_INC(encap_load_mbuf_fail);
3203 DBG_COUNTER_INC(encap_txd_encap_fail);
3206 ifsd_m[pidx] = m_head;
3208 * XXX assumes a 1 to 1 relationship between segments and
3209 * descriptors - this does not hold true on all drivers, e.g.
3212 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3213 txq->ift_no_desc_avail++;
3214 bus_dmamap_unload(desc_tag, map);
3215 DBG_COUNTER_INC(encap_txq_avail_fail);
3216 DBG_COUNTER_INC(encap_txd_encap_fail);
3217 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3218 GROUPTASK_ENQUEUE(&txq->ift_task);
3222 * On Intel cards we can greatly reduce the number of TX interrupts
3223 * we see by only setting report status on every Nth descriptor.
3224 * However, this also means that the driver will need to keep track
3225 * of the descriptors that RS was set on to check them for the DD bit.
3227 txq->ift_rs_pending += nsegs + 1;
3228 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3229 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3230 pi.ipi_flags |= IPI_TX_INTR;
3231 txq->ift_rs_pending = 0;
3235 pi.ipi_nsegs = nsegs;
3237 MPASS(pidx >= 0 && pidx < txq->ift_size);
3241 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3242 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3243 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3244 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3245 DBG_COUNTER_INC(tx_encap);
3246 MPASS(pi.ipi_new_pidx < txq->ift_size);
3248 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3249 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3250 ndesc += txq->ift_size;
3254 * drivers can need as many as
3257 MPASS(ndesc <= pi.ipi_nsegs + 2);
3258 MPASS(pi.ipi_new_pidx != pidx);
3260 txq->ift_in_use += ndesc;
3263 * We update the last software descriptor again here because there may
3264 * be a sentinel and/or there may be more mbufs than segments
3266 txq->ift_pidx = pi.ipi_new_pidx;
3267 txq->ift_npending += pi.ipi_ndescs;
3269 *m_headp = m_head = iflib_remove_mbuf(txq);
3271 txq->ift_txd_encap_efbig++;
3280 * err can't possibly be non-zero here, so we don't neet to test it
3281 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3286 txq->ift_mbuf_defrag_failed++;
3287 txq->ift_map_failed++;
3289 DBG_COUNTER_INC(tx_frees);
3291 DBG_COUNTER_INC(encap_txd_encap_fail);
3296 iflib_tx_desc_free(iflib_txq_t txq, int n)
3298 uint32_t qsize, cidx, mask, gen;
3299 struct mbuf *m, **ifsd_m;
3300 bus_dmamap_t *ifsd_map;
3303 cidx = txq->ift_cidx;
3305 qsize = txq->ift_size;
3307 ifsd_m = txq->ift_sds.ifsd_m;
3308 ifsd_map = txq->ift_sds.ifsd_map;
3309 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3313 prefetch(ifsd_m[(cidx + 3) & mask]);
3314 prefetch(ifsd_m[(cidx + 4) & mask]);
3316 if ((m = ifsd_m[cidx]) != NULL) {
3317 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3318 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3319 /* XXX we don't support any drivers that batch packets yet */
3320 MPASS(m->m_nextpkt == NULL);
3322 ifsd_m[cidx] = NULL;
3324 txq->ift_dequeued++;
3326 DBG_COUNTER_INC(tx_frees);
3328 if (__predict_false(++cidx == qsize)) {
3333 txq->ift_cidx = cidx;
3338 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3341 if_ctx_t ctx = txq->ift_ctx;
3343 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3344 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3347 * Need a rate-limiting check so that this isn't called every time
3349 iflib_tx_credits_update(ctx, txq);
3350 reclaim = DESC_RECLAIMABLE(txq);
3352 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3354 if (iflib_verbose_debug) {
3355 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3356 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3363 iflib_tx_desc_free(txq, reclaim);
3364 txq->ift_cleaned += reclaim;
3365 txq->ift_in_use -= reclaim;
3370 static struct mbuf **
3371 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3374 struct mbuf **items;
3377 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3378 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3380 prefetch(items[(cidx + offset) & (size-1)]);
3381 if (remaining > 1) {
3382 prefetch2cachelines(&items[next]);
3383 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3384 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3385 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3387 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3391 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3394 ifmp_ring_check_drainage(txq->ift_br, budget);
3398 iflib_txq_can_drain(struct ifmp_ring *r)
3400 iflib_txq_t txq = r->cookie;
3401 if_ctx_t ctx = txq->ift_ctx;
3403 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3404 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3408 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3410 iflib_txq_t txq = r->cookie;
3411 if_ctx_t ctx = txq->ift_ctx;
3412 struct ifnet *ifp = ctx->ifc_ifp;
3413 struct mbuf **mp, *m;
3414 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3415 int reclaimed, err, in_use_prev, desc_used;
3416 bool do_prefetch, ring, rang;
3418 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3419 !LINK_ACTIVE(ctx))) {
3420 DBG_COUNTER_INC(txq_drain_notready);
3423 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3424 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3425 avail = IDXDIFF(pidx, cidx, r->size);
3426 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3427 DBG_COUNTER_INC(txq_drain_flushing);
3428 for (i = 0; i < avail; i++) {
3429 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3430 m_free(r->items[(cidx + i) & (r->size-1)]);
3431 r->items[(cidx + i) & (r->size-1)] = NULL;
3436 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3437 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3439 callout_stop(&txq->ift_timer);
3440 CALLOUT_UNLOCK(txq);
3441 DBG_COUNTER_INC(txq_drain_oactive);
3445 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3446 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3447 count = MIN(avail, TX_BATCH_SIZE);
3449 if (iflib_verbose_debug)
3450 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3451 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3453 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3454 avail = TXQ_AVAIL(txq);
3456 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3457 int rem = do_prefetch ? count - i : 0;
3459 mp = _ring_peek_one(r, cidx, i, rem);
3460 MPASS(mp != NULL && *mp != NULL);
3461 if (__predict_false(*mp == (struct mbuf *)txq)) {
3466 in_use_prev = txq->ift_in_use;
3467 err = iflib_encap(txq, mp);
3468 if (__predict_false(err)) {
3469 /* no room - bail out */
3473 /* we can't send this packet - skip it */
3479 DBG_COUNTER_INC(tx_sent);
3480 bytes_sent += m->m_pkthdr.len;
3481 mcast_sent += !!(m->m_flags & M_MCAST);
3482 avail = TXQ_AVAIL(txq);
3484 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3485 desc_used += (txq->ift_in_use - in_use_prev);
3486 ETHER_BPF_MTAP(ifp, m);
3487 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3489 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3492 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3493 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3494 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3495 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3496 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3498 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3500 if (iflib_verbose_debug)
3501 printf("consumed=%d\n", consumed);
3507 iflib_txq_drain_always(struct ifmp_ring *r)
3513 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3521 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3523 callout_stop(&txq->ift_timer);
3524 CALLOUT_UNLOCK(txq);
3526 avail = IDXDIFF(pidx, cidx, r->size);
3527 for (i = 0; i < avail; i++) {
3528 mp = _ring_peek_one(r, cidx, i, avail - i);
3529 if (__predict_false(*mp == (struct mbuf *)txq))
3532 DBG_COUNTER_INC(tx_frees);
3534 MPASS(ifmp_ring_is_stalled(r) == 0);
3539 iflib_ifmp_purge(iflib_txq_t txq)
3541 struct ifmp_ring *r;
3544 r->drain = iflib_txq_drain_free;
3545 r->can_drain = iflib_txq_drain_always;
3547 ifmp_ring_check_drainage(r, r->size);
3549 r->drain = iflib_txq_drain;
3550 r->can_drain = iflib_txq_can_drain;
3554 _task_fn_tx(void *context)
3556 iflib_txq_t txq = context;
3557 if_ctx_t ctx = txq->ift_ctx;
3558 struct ifnet *ifp = ctx->ifc_ifp;
3559 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3561 #ifdef IFLIB_DIAGNOSTICS
3562 txq->ift_cpu_exec_count[curcpu]++;
3564 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3566 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3567 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3568 netmap_tx_irq(ifp, txq->ift_id);
3569 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3573 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3574 iflib_altq_if_start(ifp);
3576 if (txq->ift_db_pending)
3577 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3579 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3581 * When abdicating, we always need to check drainage, not just when we don't enqueue
3584 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3585 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3586 if (ctx->ifc_flags & IFC_LEGACY)
3587 IFDI_INTR_ENABLE(ctx);
3592 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3593 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3598 _task_fn_rx(void *context)
3600 iflib_rxq_t rxq = context;
3601 if_ctx_t ctx = rxq->ifr_ctx;
3605 #ifdef IFLIB_DIAGNOSTICS
3606 rxq->ifr_cpu_exec_count[curcpu]++;
3608 DBG_COUNTER_INC(task_fn_rxs);
3609 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3613 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3615 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3620 budget = ctx->ifc_sysctl_rx_budget;
3622 budget = 16; /* XXX */
3623 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3624 if (ctx->ifc_flags & IFC_LEGACY)
3625 IFDI_INTR_ENABLE(ctx);
3630 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3631 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3632 DBG_COUNTER_INC(rx_intr_enables);
3635 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3638 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3642 _task_fn_admin(void *context)
3644 if_ctx_t ctx = context;
3645 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3648 bool oactive, running, do_reset, do_watchdog, in_detach;
3649 uint32_t reset_on = hz / 2;
3652 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3653 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3654 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3655 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3656 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3657 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3660 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3666 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3668 callout_stop(&txq->ift_timer);
3669 CALLOUT_UNLOCK(txq);
3672 ctx->ifc_watchdog_events++;
3673 IFDI_WATCHDOG_RESET(ctx);
3675 IFDI_UPDATE_ADMIN_STATUS(ctx);
3676 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3679 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3680 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3682 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3684 IFDI_LINK_INTR_ENABLE(ctx);
3686 iflib_if_init_locked(ctx);
3689 if (LINK_ACTIVE(ctx) == 0)
3691 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3692 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3697 _task_fn_iov(void *context)
3699 if_ctx_t ctx = context;
3701 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3702 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3706 IFDI_VFLR_HANDLE(ctx);
3711 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3714 if_int_delay_info_t info;
3717 info = (if_int_delay_info_t)arg1;
3718 ctx = info->iidi_ctx;
3719 info->iidi_req = req;
3720 info->iidi_oidp = oidp;
3722 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3727 /*********************************************************************
3731 **********************************************************************/
3734 iflib_if_init_locked(if_ctx_t ctx)
3737 iflib_init_locked(ctx);
3742 iflib_if_init(void *arg)
3747 iflib_if_init_locked(ctx);
3752 iflib_if_transmit(if_t ifp, struct mbuf *m)
3754 if_ctx_t ctx = if_getsoftc(ifp);
3758 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3760 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3761 DBG_COUNTER_INC(tx_frees);
3766 MPASS(m->m_nextpkt == NULL);
3767 /* ALTQ-enabled interfaces always use queue 0. */
3769 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3770 qidx = QIDX(ctx, m);
3772 * XXX calculate buf_ring based on flowid (divvy up bits?)
3774 txq = &ctx->ifc_txqs[qidx];
3776 #ifdef DRIVER_BACKPRESSURE
3777 if (txq->ift_closed) {
3779 next = m->m_nextpkt;
3780 m->m_nextpkt = NULL;
3782 DBG_COUNTER_INC(tx_frees);
3794 next = next->m_nextpkt;
3795 } while (next != NULL);
3797 if (count > nitems(marr))
3798 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3799 /* XXX check nextpkt */
3801 /* XXX simplify for now */
3802 DBG_COUNTER_INC(tx_frees);
3805 for (next = m, i = 0; next != NULL; i++) {
3807 next = next->m_nextpkt;
3808 mp[i]->m_nextpkt = NULL;
3811 DBG_COUNTER_INC(tx_seen);
3812 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3815 GROUPTASK_ENQUEUE(&txq->ift_task);
3818 GROUPTASK_ENQUEUE(&txq->ift_task);
3819 /* support forthcoming later */
3820 #ifdef DRIVER_BACKPRESSURE
3821 txq->ift_closed = TRUE;
3823 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3825 DBG_COUNTER_INC(tx_frees);
3833 * The overall approach to integrating iflib with ALTQ is to continue to use
3834 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3835 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
3836 * is redundant/unnecessary, but doing so minimizes the amount of
3837 * ALTQ-specific code required in iflib. It is assumed that the overhead of
3838 * redundantly queueing to an intermediate mp_ring is swamped by the
3839 * performance limitations inherent in using ALTQ.
3841 * When ALTQ support is compiled in, all iflib drivers will use a transmit
3842 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
3843 * given interface. If ALTQ is enabled for an interface, then all
3844 * transmitted packets for that interface will be submitted to the ALTQ
3845 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
3846 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
3847 * update stats that the iflib machinery handles, and which is sensitve to
3848 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
3849 * will be installed as the start routine for use by ALTQ facilities that
3850 * need to trigger queue drains on a scheduled basis.
3854 iflib_altq_if_start(if_t ifp)
3856 struct ifaltq *ifq = &ifp->if_snd;
3860 IFQ_DEQUEUE_NOLOCK(ifq, m);
3862 iflib_if_transmit(ifp, m);
3863 IFQ_DEQUEUE_NOLOCK(ifq, m);
3869 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
3873 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
3874 IFQ_ENQUEUE(&ifp->if_snd, m, err);
3876 iflib_altq_if_start(ifp);
3878 err = iflib_if_transmit(ifp, m);
3885 iflib_if_qflush(if_t ifp)
3887 if_ctx_t ctx = if_getsoftc(ifp);
3888 iflib_txq_t txq = ctx->ifc_txqs;
3892 ctx->ifc_flags |= IFC_QFLUSH;
3894 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3895 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3896 iflib_txq_check_drain(txq, 0);
3898 ctx->ifc_flags &= ~IFC_QFLUSH;
3902 * When ALTQ is enabled, this will also take care of purging the
3909 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3910 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3911 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
3912 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
3915 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3917 if_ctx_t ctx = if_getsoftc(ifp);
3918 struct ifreq *ifr = (struct ifreq *)data;
3919 #if defined(INET) || defined(INET6)
3920 struct ifaddr *ifa = (struct ifaddr *)data;
3922 bool avoid_reset = FALSE;
3923 int err = 0, reinit = 0, bits;
3928 if (ifa->ifa_addr->sa_family == AF_INET)
3932 if (ifa->ifa_addr->sa_family == AF_INET6)
3936 ** Calling init results in link renegotiation,
3937 ** so we avoid doing it when possible.
3940 if_setflagbits(ifp, IFF_UP,0);
3941 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3944 if (!(if_getflags(ifp) & IFF_NOARP))
3945 arp_ifinit(ifp, ifa);
3948 err = ether_ioctl(ifp, command, data);
3952 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3956 bits = if_getdrvflags(ifp);
3957 /* stop the driver and free any clusters before proceeding */
3960 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3962 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3963 ctx->ifc_flags |= IFC_MULTISEG;
3965 ctx->ifc_flags &= ~IFC_MULTISEG;
3967 err = if_setmtu(ifp, ifr->ifr_mtu);
3969 iflib_init_locked(ctx);
3971 if_setdrvflags(ifp, bits);
3977 if (if_getflags(ifp) & IFF_UP) {
3978 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3979 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3980 (IFF_PROMISC | IFF_ALLMULTI)) {
3981 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3985 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3988 ctx->ifc_if_flags = if_getflags(ifp);
3993 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3995 IFDI_INTR_DISABLE(ctx);
3996 IFDI_MULTI_SET(ctx);
3997 IFDI_INTR_ENABLE(ctx);
4003 IFDI_MEDIA_SET(ctx);
4008 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4012 struct ifi2creq i2c;
4014 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4017 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4021 if (i2c.len > sizeof(i2c.data)) {
4026 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4027 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4033 int mask, setmask, oldmask;
4035 oldmask = if_getcapenable(ifp);
4036 mask = ifr->ifr_reqcap ^ oldmask;
4037 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4040 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4042 setmask |= (mask & IFCAP_FLAGS);
4043 setmask |= (mask & IFCAP_WOL);
4046 * If any RX csum has changed, change all the ones that
4047 * are supported by the driver.
4049 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4050 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4051 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4055 * want to ensure that traffic has stopped before we change any of the flags
4059 bits = if_getdrvflags(ifp);
4060 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4063 if_togglecapenable(ifp, setmask);
4065 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4066 iflib_init_locked(ctx);
4068 if_setdrvflags(ifp, bits);
4075 case SIOCGPRIVATE_0:
4079 err = IFDI_PRIV_IOCTL(ctx, command, data);
4083 err = ether_ioctl(ifp, command, data);
4092 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4094 if_ctx_t ctx = if_getsoftc(ifp);
4096 return (IFDI_GET_COUNTER(ctx, cnt));
4099 /*********************************************************************
4101 * OTHER FUNCTIONS EXPORTED TO THE STACK
4103 **********************************************************************/
4106 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4108 if_ctx_t ctx = if_getsoftc(ifp);
4110 if ((void *)ctx != arg)
4113 if ((vtag == 0) || (vtag > 4095))
4117 IFDI_VLAN_REGISTER(ctx, vtag);
4118 /* Re-init to load the changes */
4119 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4120 iflib_if_init_locked(ctx);
4125 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4127 if_ctx_t ctx = if_getsoftc(ifp);
4129 if ((void *)ctx != arg)
4132 if ((vtag == 0) || (vtag > 4095))
4136 IFDI_VLAN_UNREGISTER(ctx, vtag);
4137 /* Re-init to load the changes */
4138 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4139 iflib_if_init_locked(ctx);
4144 iflib_led_func(void *arg, int onoff)
4149 IFDI_LED_FUNC(ctx, onoff);
4153 /*********************************************************************
4155 * BUS FUNCTION DEFINITIONS
4157 **********************************************************************/
4160 iflib_device_probe(device_t dev)
4162 pci_vendor_info_t *ent;
4164 uint16_t pci_vendor_id, pci_device_id;
4165 uint16_t pci_subvendor_id, pci_subdevice_id;
4166 uint16_t pci_rev_id;
4167 if_shared_ctx_t sctx;
4169 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4172 pci_vendor_id = pci_get_vendor(dev);
4173 pci_device_id = pci_get_device(dev);
4174 pci_subvendor_id = pci_get_subvendor(dev);
4175 pci_subdevice_id = pci_get_subdevice(dev);
4176 pci_rev_id = pci_get_revid(dev);
4177 if (sctx->isc_parse_devinfo != NULL)
4178 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4180 ent = sctx->isc_vendor_info;
4181 while (ent->pvi_vendor_id != 0) {
4182 if (pci_vendor_id != ent->pvi_vendor_id) {
4186 if ((pci_device_id == ent->pvi_device_id) &&
4187 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4188 (ent->pvi_subvendor_id == 0)) &&
4189 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4190 (ent->pvi_subdevice_id == 0)) &&
4191 ((pci_rev_id == ent->pvi_rev_id) ||
4192 (ent->pvi_rev_id == 0))) {
4194 device_set_desc_copy(dev, ent->pvi_name);
4195 /* this needs to be changed to zero if the bus probing code
4196 * ever stops re-probing on best match because the sctx
4197 * may have its values over written by register calls
4198 * in subsequent probes
4200 return (BUS_PROBE_DEFAULT);
4208 iflib_reset_qvalues(if_ctx_t ctx)
4210 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4211 if_shared_ctx_t sctx = ctx->ifc_sctx;
4212 device_t dev = ctx->ifc_dev;
4215 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4216 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4218 * XXX sanity check that ntxd & nrxd are a power of 2
4220 if (ctx->ifc_sysctl_ntxqs != 0)
4221 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4222 if (ctx->ifc_sysctl_nrxqs != 0)
4223 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4225 for (i = 0; i < sctx->isc_ntxqs; i++) {
4226 if (ctx->ifc_sysctl_ntxds[i] != 0)
4227 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4229 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4232 for (i = 0; i < sctx->isc_nrxqs; i++) {
4233 if (ctx->ifc_sysctl_nrxds[i] != 0)
4234 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4236 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4239 for (i = 0; i < sctx->isc_nrxqs; i++) {
4240 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4241 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4242 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4243 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4245 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4246 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4247 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4248 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4252 for (i = 0; i < sctx->isc_ntxqs; i++) {
4253 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4254 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4255 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4256 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4258 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4259 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4260 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4261 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4267 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4272 if_softc_ctx_t scctx;
4278 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4281 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4282 device_set_softc(dev, ctx);
4283 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4286 ctx->ifc_sctx = sctx;
4288 ctx->ifc_softc = sc;
4290 if ((err = iflib_register(ctx)) != 0) {
4291 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4294 device_printf(dev, "iflib_register failed %d\n", err);
4297 iflib_add_device_sysctl_pre(ctx);
4299 scctx = &ctx->ifc_softc_ctx;
4302 iflib_reset_qvalues(ctx);
4304 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4306 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4309 _iflib_pre_assert(scctx);
4310 ctx->ifc_txrx = *scctx->isc_txrx;
4313 MPASS(scctx->isc_capabilities);
4314 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4315 MPASS(scctx->isc_tx_csum_flags);
4318 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4319 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4321 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4322 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4323 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4324 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4326 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4327 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4329 /* XXX change for per-queue sizes */
4330 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4331 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4332 for (i = 0; i < sctx->isc_nrxqs; i++) {
4333 if (!powerof2(scctx->isc_nrxd[i])) {
4334 /* round down instead? */
4335 device_printf(dev, "# rx descriptors must be a power of 2\n");
4340 for (i = 0; i < sctx->isc_ntxqs; i++) {
4341 if (!powerof2(scctx->isc_ntxd[i])) {
4343 "# tx descriptors must be a power of 2");
4349 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4350 MAX_SINGLE_PACKET_FRACTION)
4351 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4352 MAX_SINGLE_PACKET_FRACTION);
4353 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4354 MAX_SINGLE_PACKET_FRACTION)
4355 scctx->isc_tx_tso_segments_max = max(1,
4356 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4358 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4359 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4361 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4364 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4367 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4368 * into account. In the worst case, each of these calls will
4369 * add another mbuf and, thus, the requirement for another DMA
4370 * segment. So for best performance, it doesn't make sense to
4371 * advertize a maximum of TSO segments that typically will
4372 * require defragmentation in iflib_encap().
4374 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4375 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4377 if (scctx->isc_rss_table_size == 0)
4378 scctx->isc_rss_table_size = 64;
4379 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4381 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4382 /* XXX format name */
4383 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4385 /* Set up cpu set. If it fails, use the set of all CPUs. */
4386 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4387 device_printf(dev, "Unable to fetch CPU list\n");
4388 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4390 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4393 ** Now setup MSI or MSI/X, should
4394 ** return us the number of supported
4395 ** vectors. (Will be 1 for MSI)
4397 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4398 msix = scctx->isc_vectors;
4399 } else if (scctx->isc_msix_bar != 0)
4401 * The simple fact that isc_msix_bar is not 0 does not mean we
4402 * we have a good value there that is known to work.
4404 msix = iflib_msix_init(ctx);
4406 scctx->isc_vectors = 1;
4407 scctx->isc_ntxqsets = 1;
4408 scctx->isc_nrxqsets = 1;
4409 scctx->isc_intr = IFLIB_INTR_LEGACY;
4412 /* Get memory for the station queues */
4413 if ((err = iflib_queues_alloc(ctx))) {
4414 device_printf(dev, "Unable to allocate queue memory\n");
4418 if ((err = iflib_qset_structures_setup(ctx)))
4422 * Group taskqueues aren't properly set up until SMP is started,
4423 * so we disable interrupts until we can handle them post
4426 * XXX: disabling interrupts doesn't actually work, at least for
4427 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4428 * we do null handling and depend on this not causing too large an
4431 IFDI_INTR_DISABLE(ctx);
4432 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4433 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4434 goto fail_intr_free;
4438 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4442 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4443 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4444 goto fail_intr_free;
4448 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4450 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4451 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4456 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4457 * This must appear after the call to ether_ifattach() because
4458 * ether_ifattach() sets if_hdrlen to the default value.
4460 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4461 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4463 if ((err = iflib_netmap_attach(ctx))) {
4464 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4469 NETDUMP_SET(ctx->ifc_ifp, iflib);
4471 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4472 iflib_add_device_sysctl_post(ctx);
4473 ctx->ifc_flags |= IFC_INIT_DONE;
4478 ether_ifdetach(ctx->ifc_ifp);
4481 iflib_tx_structures_free(ctx);
4482 iflib_rx_structures_free(ctx);
4484 iflib_free_intr_mem(ctx);
4492 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4493 struct iflib_cloneattach_ctx *clctx)
4498 if_softc_ctx_t scctx;
4504 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4505 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4506 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4507 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4508 ctx->ifc_flags |= IFC_PSEUDO;
4510 ctx->ifc_sctx = sctx;
4511 ctx->ifc_softc = sc;
4514 if ((err = iflib_register(ctx)) != 0) {
4515 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4520 iflib_add_device_sysctl_pre(ctx);
4522 scctx = &ctx->ifc_softc_ctx;
4526 * XXX sanity check that ntxd & nrxd are a power of 2
4528 iflib_reset_qvalues(ctx);
4530 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4531 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4534 if (sctx->isc_flags & IFLIB_GEN_MAC)
4536 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4537 clctx->cc_params)) != 0) {
4538 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4541 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4542 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4543 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4546 MPASS(scctx->isc_capabilities);
4547 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4548 MPASS(scctx->isc_tx_csum_flags);
4551 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4552 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4554 ifp->if_flags |= IFF_NOGROUP;
4555 if (sctx->isc_flags & IFLIB_PSEUDO) {
4556 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4558 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4559 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4565 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4566 * This must appear after the call to ether_ifattach() because
4567 * ether_ifattach() sets if_hdrlen to the default value.
4569 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4570 if_setifheaderlen(ifp,
4571 sizeof(struct ether_vlan_header));
4573 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4574 iflib_add_device_sysctl_post(ctx);
4575 ctx->ifc_flags |= IFC_INIT_DONE;
4578 _iflib_pre_assert(scctx);
4579 ctx->ifc_txrx = *scctx->isc_txrx;
4581 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4582 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4583 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4584 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4586 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4587 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4589 /* XXX change for per-queue sizes */
4590 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4591 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4592 for (i = 0; i < sctx->isc_nrxqs; i++) {
4593 if (!powerof2(scctx->isc_nrxd[i])) {
4594 /* round down instead? */
4595 device_printf(dev, "# rx descriptors must be a power of 2\n");
4600 for (i = 0; i < sctx->isc_ntxqs; i++) {
4601 if (!powerof2(scctx->isc_ntxd[i])) {
4603 "# tx descriptors must be a power of 2");
4609 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4610 MAX_SINGLE_PACKET_FRACTION)
4611 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4612 MAX_SINGLE_PACKET_FRACTION);
4613 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4614 MAX_SINGLE_PACKET_FRACTION)
4615 scctx->isc_tx_tso_segments_max = max(1,
4616 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4618 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4619 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4621 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4624 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4627 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4628 * into account. In the worst case, each of these calls will
4629 * add another mbuf and, thus, the requirement for another DMA
4630 * segment. So for best performance, it doesn't make sense to
4631 * advertize a maximum of TSO segments that typically will
4632 * require defragmentation in iflib_encap().
4634 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4635 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4637 if (scctx->isc_rss_table_size == 0)
4638 scctx->isc_rss_table_size = 64;
4639 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4641 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4642 /* XXX format name */
4643 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4645 /* XXX --- can support > 1 -- but keep it simple for now */
4646 scctx->isc_intr = IFLIB_INTR_LEGACY;
4648 /* Get memory for the station queues */
4649 if ((err = iflib_queues_alloc(ctx))) {
4650 device_printf(dev, "Unable to allocate queue memory\n");
4654 if ((err = iflib_qset_structures_setup(ctx))) {
4655 device_printf(dev, "qset structure setup failed %d\n", err);
4660 * XXX What if anything do we want to do about interrupts?
4662 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4663 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4664 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4669 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4670 * This must appear after the call to ether_ifattach() because
4671 * ether_ifattach() sets if_hdrlen to the default value.
4673 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4674 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4676 /* XXX handle more than one queue */
4677 for (i = 0; i < scctx->isc_nrxqsets; i++)
4678 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4682 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4683 iflib_add_device_sysctl_post(ctx);
4684 ctx->ifc_flags |= IFC_INIT_DONE;
4687 ether_ifdetach(ctx->ifc_ifp);
4689 iflib_tx_structures_free(ctx);
4690 iflib_rx_structures_free(ctx);
4697 iflib_pseudo_deregister(if_ctx_t ctx)
4699 if_t ifp = ctx->ifc_ifp;
4703 struct taskqgroup *tqg;
4706 /* Unregister VLAN events */
4707 if (ctx->ifc_vlan_attach_event != NULL)
4708 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4709 if (ctx->ifc_vlan_detach_event != NULL)
4710 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4712 ether_ifdetach(ifp);
4713 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4714 CTX_LOCK_DESTROY(ctx);
4715 /* XXX drain any dependent tasks */
4716 tqg = qgroup_if_io_tqg;
4717 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4718 callout_drain(&txq->ift_timer);
4719 if (txq->ift_task.gt_uniq != NULL)
4720 taskqgroup_detach(tqg, &txq->ift_task);
4722 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4723 if (rxq->ifr_task.gt_uniq != NULL)
4724 taskqgroup_detach(tqg, &rxq->ifr_task);
4726 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4727 free(fl->ifl_rx_bitmap, M_IFLIB);
4729 tqg = qgroup_if_config_tqg;
4730 if (ctx->ifc_admin_task.gt_uniq != NULL)
4731 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4732 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4733 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4737 iflib_tx_structures_free(ctx);
4738 iflib_rx_structures_free(ctx);
4739 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4740 free(ctx->ifc_softc, M_IFLIB);
4746 iflib_device_attach(device_t dev)
4749 if_shared_ctx_t sctx;
4751 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4754 pci_enable_busmaster(dev);
4756 return (iflib_device_register(dev, NULL, sctx, &ctx));
4760 iflib_device_deregister(if_ctx_t ctx)
4762 if_t ifp = ctx->ifc_ifp;
4765 device_t dev = ctx->ifc_dev;
4767 struct taskqgroup *tqg;
4770 /* Make sure VLANS are not using driver */
4771 if (if_vlantrunkinuse(ifp)) {
4772 device_printf(dev, "Vlan in use, detach first\n");
4776 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
4777 device_printf(dev, "SR-IOV in use; detach first.\n");
4783 ctx->ifc_flags |= IFC_IN_DETACH;
4790 /* Unregister VLAN events */
4791 if (ctx->ifc_vlan_attach_event != NULL)
4792 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4793 if (ctx->ifc_vlan_detach_event != NULL)
4794 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4796 iflib_netmap_detach(ifp);
4797 ether_ifdetach(ifp);
4798 if (ctx->ifc_led_dev != NULL)
4799 led_destroy(ctx->ifc_led_dev);
4800 /* XXX drain any dependent tasks */
4801 tqg = qgroup_if_io_tqg;
4802 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4803 callout_drain(&txq->ift_timer);
4804 if (txq->ift_task.gt_uniq != NULL)
4805 taskqgroup_detach(tqg, &txq->ift_task);
4807 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4808 if (rxq->ifr_task.gt_uniq != NULL)
4809 taskqgroup_detach(tqg, &rxq->ifr_task);
4811 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4812 free(fl->ifl_rx_bitmap, M_IFLIB);
4815 tqg = qgroup_if_config_tqg;
4816 if (ctx->ifc_admin_task.gt_uniq != NULL)
4817 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4818 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4819 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4824 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4825 CTX_LOCK_DESTROY(ctx);
4826 device_set_softc(ctx->ifc_dev, NULL);
4827 iflib_free_intr_mem(ctx);
4829 bus_generic_detach(dev);
4832 iflib_tx_structures_free(ctx);
4833 iflib_rx_structures_free(ctx);
4834 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4835 free(ctx->ifc_softc, M_IFLIB);
4836 STATE_LOCK_DESTROY(ctx);
4842 iflib_free_intr_mem(if_ctx_t ctx)
4845 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4846 pci_release_msi(ctx->ifc_dev);
4848 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4849 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4851 if (ctx->ifc_msix_mem != NULL) {
4852 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4853 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4854 ctx->ifc_msix_mem = NULL;
4859 iflib_device_detach(device_t dev)
4861 if_ctx_t ctx = device_get_softc(dev);
4863 return (iflib_device_deregister(ctx));
4867 iflib_device_suspend(device_t dev)
4869 if_ctx_t ctx = device_get_softc(dev);
4875 return bus_generic_suspend(dev);
4878 iflib_device_shutdown(device_t dev)
4880 if_ctx_t ctx = device_get_softc(dev);
4886 return bus_generic_suspend(dev);
4891 iflib_device_resume(device_t dev)
4893 if_ctx_t ctx = device_get_softc(dev);
4894 iflib_txq_t txq = ctx->ifc_txqs;
4898 iflib_init_locked(ctx);
4900 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4901 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4903 return (bus_generic_resume(dev));
4907 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4910 if_ctx_t ctx = device_get_softc(dev);
4913 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4920 iflib_device_iov_uninit(device_t dev)
4922 if_ctx_t ctx = device_get_softc(dev);
4925 IFDI_IOV_UNINIT(ctx);
4930 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4933 if_ctx_t ctx = device_get_softc(dev);
4936 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4942 /*********************************************************************
4944 * MODULE FUNCTION DEFINITIONS
4946 **********************************************************************/
4949 * - Start a fast taskqueue thread for each core
4950 * - Start a taskqueue for control operations
4953 iflib_module_init(void)
4959 iflib_module_event_handler(module_t mod, int what, void *arg)
4965 if ((err = iflib_module_init()) != 0)
4971 return (EOPNOTSUPP);
4977 /*********************************************************************
4979 * PUBLIC FUNCTION DEFINITIONS
4980 * ordered as in iflib.h
4982 **********************************************************************/
4986 _iflib_assert(if_shared_ctx_t sctx)
4988 MPASS(sctx->isc_tx_maxsize);
4989 MPASS(sctx->isc_tx_maxsegsize);
4991 MPASS(sctx->isc_rx_maxsize);
4992 MPASS(sctx->isc_rx_nsegments);
4993 MPASS(sctx->isc_rx_maxsegsize);
4995 MPASS(sctx->isc_nrxd_min[0]);
4996 MPASS(sctx->isc_nrxd_max[0]);
4997 MPASS(sctx->isc_nrxd_default[0]);
4998 MPASS(sctx->isc_ntxd_min[0]);
4999 MPASS(sctx->isc_ntxd_max[0]);
5000 MPASS(sctx->isc_ntxd_default[0]);
5004 _iflib_pre_assert(if_softc_ctx_t scctx)
5007 MPASS(scctx->isc_txrx->ift_txd_encap);
5008 MPASS(scctx->isc_txrx->ift_txd_flush);
5009 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5010 MPASS(scctx->isc_txrx->ift_rxd_available);
5011 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5012 MPASS(scctx->isc_txrx->ift_rxd_refill);
5013 MPASS(scctx->isc_txrx->ift_rxd_flush);
5017 iflib_register(if_ctx_t ctx)
5019 if_shared_ctx_t sctx = ctx->ifc_sctx;
5020 driver_t *driver = sctx->isc_driver;
5021 device_t dev = ctx->ifc_dev;
5024 _iflib_assert(sctx);
5027 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5028 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5030 device_printf(dev, "can not allocate ifnet structure\n");
5035 * Initialize our context's device specific methods
5037 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5038 kobj_class_compile((kobj_class_t) driver);
5041 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5042 if_setsoftc(ifp, ctx);
5043 if_setdev(ifp, dev);
5044 if_setinitfn(ifp, iflib_if_init);
5045 if_setioctlfn(ifp, iflib_if_ioctl);
5047 if_setstartfn(ifp, iflib_altq_if_start);
5048 if_settransmitfn(ifp, iflib_altq_if_transmit);
5049 if_setsendqready(ifp);
5051 if_settransmitfn(ifp, iflib_if_transmit);
5053 if_setqflushfn(ifp, iflib_if_qflush);
5054 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5056 ctx->ifc_vlan_attach_event =
5057 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5058 EVENTHANDLER_PRI_FIRST);
5059 ctx->ifc_vlan_detach_event =
5060 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5061 EVENTHANDLER_PRI_FIRST);
5063 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5064 iflib_media_change, iflib_media_status);
5071 iflib_queues_alloc(if_ctx_t ctx)
5073 if_shared_ctx_t sctx = ctx->ifc_sctx;
5074 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5075 device_t dev = ctx->ifc_dev;
5076 int nrxqsets = scctx->isc_nrxqsets;
5077 int ntxqsets = scctx->isc_ntxqsets;
5080 iflib_fl_t fl = NULL;
5081 int i, j, cpu, err, txconf, rxconf;
5082 iflib_dma_info_t ifdip;
5083 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5084 uint32_t *txqsizes = scctx->isc_txqsizes;
5085 uint8_t nrxqs = sctx->isc_nrxqs;
5086 uint8_t ntxqs = sctx->isc_ntxqs;
5087 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5091 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5092 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5094 /* Allocate the TX ring struct memory */
5095 if (!(ctx->ifc_txqs =
5096 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5097 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5098 device_printf(dev, "Unable to allocate TX ring memory\n");
5103 /* Now allocate the RX */
5104 if (!(ctx->ifc_rxqs =
5105 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5106 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5107 device_printf(dev, "Unable to allocate RX ring memory\n");
5112 txq = ctx->ifc_txqs;
5113 rxq = ctx->ifc_rxqs;
5116 * XXX handle allocation failure
5118 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5119 /* Set up some basics */
5121 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5122 device_printf(dev, "failed to allocate iflib_dma_info\n");
5126 txq->ift_ifdi = ifdip;
5127 for (j = 0; j < ntxqs; j++, ifdip++) {
5128 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5129 device_printf(dev, "Unable to allocate Descriptor memory\n");
5133 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5134 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5138 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5139 txq->ift_br_offset = 1;
5141 txq->ift_br_offset = 0;
5144 txq->ift_timer.c_cpu = cpu;
5146 if (iflib_txsd_alloc(txq)) {
5147 device_printf(dev, "Critical Failure setting up TX buffers\n");
5152 /* Initialize the TX lock */
5153 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5154 device_get_nameunit(dev), txq->ift_id);
5155 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5156 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5158 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5159 device_get_nameunit(dev), txq->ift_id);
5161 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5162 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5164 /* XXX free any allocated rings */
5165 device_printf(dev, "Unable to allocate buf_ring\n");
5170 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5171 /* Set up some basics */
5173 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5174 device_printf(dev, "failed to allocate iflib_dma_info\n");
5179 rxq->ifr_ifdi = ifdip;
5180 /* XXX this needs to be changed if #rx queues != #tx queues */
5181 rxq->ifr_ntxqirq = 1;
5182 rxq->ifr_txqid[0] = i;
5183 for (j = 0; j < nrxqs; j++, ifdip++) {
5184 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5185 device_printf(dev, "Unable to allocate Descriptor memory\n");
5189 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5193 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5194 rxq->ifr_fl_offset = 1;
5196 rxq->ifr_fl_offset = 0;
5198 rxq->ifr_nfl = nfree_lists;
5200 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5201 device_printf(dev, "Unable to allocate free list memory\n");
5206 for (j = 0; j < nfree_lists; j++) {
5207 fl[j].ifl_rxq = rxq;
5209 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5210 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5212 /* Allocate receive buffers for the ring */
5213 if (iflib_rxsd_alloc(rxq)) {
5215 "Critical Failure setting up receive buffers\n");
5220 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5221 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
5225 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5226 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5227 for (i = 0; i < ntxqsets; i++) {
5228 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5230 for (j = 0; j < ntxqs; j++, di++) {
5231 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5232 paddrs[i*ntxqs + j] = di->idi_paddr;
5235 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5236 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5237 iflib_tx_structures_free(ctx);
5238 free(vaddrs, M_IFLIB);
5239 free(paddrs, M_IFLIB);
5242 free(vaddrs, M_IFLIB);
5243 free(paddrs, M_IFLIB);
5246 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5247 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5248 for (i = 0; i < nrxqsets; i++) {
5249 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5251 for (j = 0; j < nrxqs; j++, di++) {
5252 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5253 paddrs[i*nrxqs + j] = di->idi_paddr;
5256 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5257 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5258 iflib_tx_structures_free(ctx);
5259 free(vaddrs, M_IFLIB);
5260 free(paddrs, M_IFLIB);
5263 free(vaddrs, M_IFLIB);
5264 free(paddrs, M_IFLIB);
5268 /* XXX handle allocation failure changes */
5272 if (ctx->ifc_rxqs != NULL)
5273 free(ctx->ifc_rxqs, M_IFLIB);
5274 ctx->ifc_rxqs = NULL;
5275 if (ctx->ifc_txqs != NULL)
5276 free(ctx->ifc_txqs, M_IFLIB);
5277 ctx->ifc_txqs = NULL;
5283 iflib_tx_structures_setup(if_ctx_t ctx)
5285 iflib_txq_t txq = ctx->ifc_txqs;
5288 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5289 iflib_txq_setup(txq);
5295 iflib_tx_structures_free(if_ctx_t ctx)
5297 iflib_txq_t txq = ctx->ifc_txqs;
5298 if_shared_ctx_t sctx = ctx->ifc_sctx;
5301 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5302 iflib_txq_destroy(txq);
5303 for (j = 0; j < sctx->isc_ntxqs; j++)
5304 iflib_dma_free(&txq->ift_ifdi[j]);
5306 free(ctx->ifc_txqs, M_IFLIB);
5307 ctx->ifc_txqs = NULL;
5308 IFDI_QUEUES_FREE(ctx);
5311 /*********************************************************************
5313 * Initialize all receive rings.
5315 **********************************************************************/
5317 iflib_rx_structures_setup(if_ctx_t ctx)
5319 iflib_rxq_t rxq = ctx->ifc_rxqs;
5321 #if defined(INET6) || defined(INET)
5325 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5326 #if defined(INET6) || defined(INET)
5327 tcp_lro_free(&rxq->ifr_lc);
5328 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5329 TCP_LRO_ENTRIES, min(1024,
5330 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5331 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5334 rxq->ifr_lro_enabled = TRUE;
5336 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5339 #if defined(INET6) || defined(INET)
5342 * Free RX software descriptors allocated so far, we will only handle
5343 * the rings that completed, the failing case will have
5344 * cleaned up for itself. 'q' failed, so its the terminus.
5346 rxq = ctx->ifc_rxqs;
5347 for (i = 0; i < q; ++i, rxq++) {
5348 iflib_rx_sds_free(rxq);
5349 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5355 /*********************************************************************
5357 * Free all receive rings.
5359 **********************************************************************/
5361 iflib_rx_structures_free(if_ctx_t ctx)
5363 iflib_rxq_t rxq = ctx->ifc_rxqs;
5365 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5366 iflib_rx_sds_free(rxq);
5368 free(ctx->ifc_rxqs, M_IFLIB);
5369 ctx->ifc_rxqs = NULL;
5373 iflib_qset_structures_setup(if_ctx_t ctx)
5378 * It is expected that the caller takes care of freeing queues if this
5381 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5382 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5386 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5387 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5393 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5394 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5397 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5402 find_nth(if_ctx_t ctx, int qid)
5405 int i, cpuid, eqid, count;
5407 CPU_COPY(&ctx->ifc_cpus, &cpus);
5408 count = CPU_COUNT(&cpus);
5410 /* clear up to the qid'th bit */
5411 for (i = 0; i < eqid; i++) {
5412 cpuid = CPU_FFS(&cpus);
5414 CPU_CLR(cpuid-1, &cpus);
5416 cpuid = CPU_FFS(&cpus);
5422 extern struct cpu_group *cpu_top; /* CPU topology */
5425 find_child_with_core(int cpu, struct cpu_group *grp)
5429 if (grp->cg_children == 0)
5432 MPASS(grp->cg_child);
5433 for (i = 0; i < grp->cg_children; i++) {
5434 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5442 * Find the nth "close" core to the specified core
5443 * "close" is defined as the deepest level that shares
5444 * at least an L2 cache. With threads, this will be
5445 * threads on the same core. If the sahred cache is L3
5446 * or higher, simply returns the same core.
5449 find_close_core(int cpu, int core_offset)
5451 struct cpu_group *grp;
5460 while ((i = find_child_with_core(cpu, grp)) != -1) {
5461 /* If the child only has one cpu, don't descend */
5462 if (grp->cg_child[i].cg_count <= 1)
5464 grp = &grp->cg_child[i];
5467 /* If they don't share at least an L2 cache, use the same CPU */
5468 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5472 CPU_COPY(&grp->cg_mask, &cs);
5474 /* Add the selected CPU offset to core offset. */
5475 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5476 if (fcpu - 1 == cpu)
5478 CPU_CLR(fcpu - 1, &cs);
5484 CPU_COPY(&grp->cg_mask, &cs);
5485 for (i = core_offset % grp->cg_count; i > 0; i--) {
5486 MPASS(CPU_FFS(&cs));
5487 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5489 MPASS(CPU_FFS(&cs));
5490 return CPU_FFS(&cs) - 1;
5494 find_close_core(int cpu, int core_offset __unused)
5501 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5505 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5506 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5507 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5509 case IFLIB_INTR_RXTX:
5510 /* RX queues get the specified core */
5511 return qid / CPU_COUNT(&ctx->ifc_cpus);
5517 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5518 #define find_close_core(cpuid, tid) CPU_FIRST()
5519 #define find_nth(ctx, gid) CPU_FIRST()
5522 /* Just to avoid copy/paste */
5524 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5525 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5530 cpuid = find_nth(ctx, qid);
5531 tid = get_core_offset(ctx, type, qid);
5533 cpuid = find_close_core(cpuid, tid);
5534 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5536 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5540 if (cpuid > ctx->ifc_cpuid_highest)
5541 ctx->ifc_cpuid_highest = cpuid;
5547 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5548 iflib_intr_type_t type, driver_filter_t *filter,
5549 void *filter_arg, int qid, const char *name)
5551 struct grouptask *gtask;
5552 struct taskqgroup *tqg;
5553 iflib_filter_info_t info;
5556 driver_filter_t *intr_fast;
5559 info = &ctx->ifc_filter_info;
5563 /* XXX merge tx/rx for netmap? */
5565 q = &ctx->ifc_txqs[qid];
5566 info = &ctx->ifc_txqs[qid].ift_filter_info;
5567 gtask = &ctx->ifc_txqs[qid].ift_task;
5568 tqg = qgroup_if_io_tqg;
5570 intr_fast = iflib_fast_intr;
5571 GROUPTASK_INIT(gtask, 0, fn, q);
5572 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5575 q = &ctx->ifc_rxqs[qid];
5576 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5577 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5578 tqg = qgroup_if_io_tqg;
5580 intr_fast = iflib_fast_intr;
5581 GROUPTASK_INIT(gtask, 0, fn, q);
5583 case IFLIB_INTR_RXTX:
5584 q = &ctx->ifc_rxqs[qid];
5585 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5586 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5587 tqg = qgroup_if_io_tqg;
5589 intr_fast = iflib_fast_intr_rxtx;
5590 GROUPTASK_INIT(gtask, 0, fn, q);
5592 case IFLIB_INTR_ADMIN:
5595 info = &ctx->ifc_filter_info;
5596 gtask = &ctx->ifc_admin_task;
5597 tqg = qgroup_if_config_tqg;
5598 fn = _task_fn_admin;
5599 intr_fast = iflib_fast_intr_ctx;
5602 panic("unknown net intr type");
5605 info->ifi_filter = filter;
5606 info->ifi_filter_arg = filter_arg;
5607 info->ifi_task = gtask;
5610 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5612 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5615 if (type == IFLIB_INTR_ADMIN)
5619 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5623 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5630 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5632 struct grouptask *gtask;
5633 struct taskqgroup *tqg;
5641 q = &ctx->ifc_txqs[qid];
5642 gtask = &ctx->ifc_txqs[qid].ift_task;
5643 tqg = qgroup_if_io_tqg;
5646 irq_num = rman_get_start(irq->ii_res);
5649 q = &ctx->ifc_rxqs[qid];
5650 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5651 tqg = qgroup_if_io_tqg;
5654 irq_num = rman_get_start(irq->ii_res);
5656 case IFLIB_INTR_IOV:
5658 gtask = &ctx->ifc_vflr_task;
5659 tqg = qgroup_if_config_tqg;
5663 panic("unknown net intr type");
5665 GROUPTASK_INIT(gtask, 0, fn, q);
5666 if (irq_num != -1) {
5667 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5669 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5672 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5677 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5680 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5683 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5687 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5689 iflib_txq_t txq = ctx->ifc_txqs;
5690 iflib_rxq_t rxq = ctx->ifc_rxqs;
5691 if_irq_t irq = &ctx->ifc_legacy_irq;
5692 iflib_filter_info_t info;
5693 struct grouptask *gtask;
5694 struct taskqgroup *tqg;
5700 q = &ctx->ifc_rxqs[0];
5701 info = &rxq[0].ifr_filter_info;
5702 gtask = &rxq[0].ifr_task;
5703 tqg = qgroup_if_io_tqg;
5704 tqrid = irq->ii_rid = *rid;
5707 ctx->ifc_flags |= IFC_LEGACY;
5708 info->ifi_filter = filter;
5709 info->ifi_filter_arg = filter_arg;
5710 info->ifi_task = gtask;
5711 info->ifi_ctx = ctx;
5713 /* We allocate a single interrupt resource */
5714 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5716 GROUPTASK_INIT(gtask, 0, fn, q);
5717 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5719 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5720 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5725 iflib_led_create(if_ctx_t ctx)
5728 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5729 device_get_nameunit(ctx->ifc_dev));
5733 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5736 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5740 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5743 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5747 iflib_admin_intr_deferred(if_ctx_t ctx)
5750 struct grouptask *gtask;
5752 gtask = &ctx->ifc_admin_task;
5753 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5756 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5760 iflib_iov_intr_deferred(if_ctx_t ctx)
5763 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5767 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5770 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5774 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5778 GROUPTASK_INIT(gtask, 0, fn, ctx);
5779 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5783 iflib_config_gtask_deinit(struct grouptask *gtask)
5786 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5790 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5792 if_t ifp = ctx->ifc_ifp;
5793 iflib_txq_t txq = ctx->ifc_txqs;
5795 if_setbaudrate(ifp, baudrate);
5796 if (baudrate >= IF_Gbps(10)) {
5798 ctx->ifc_flags |= IFC_PREFETCH;
5801 /* If link down, disable watchdog */
5802 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5803 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5804 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5806 ctx->ifc_link_state = link_state;
5807 if_link_state_change(ifp, link_state);
5811 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5815 int credits_pre = txq->ift_cidx_processed;
5818 if (ctx->isc_txd_credits_update == NULL)
5821 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5824 txq->ift_processed += credits;
5825 txq->ift_cidx_processed += credits;
5827 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5828 if (txq->ift_cidx_processed >= txq->ift_size)
5829 txq->ift_cidx_processed -= txq->ift_size;
5834 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5837 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5842 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5843 const char *description, if_int_delay_info_t info,
5844 int offset, int value)
5846 info->iidi_ctx = ctx;
5847 info->iidi_offset = offset;
5848 info->iidi_value = value;
5849 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5850 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5851 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5852 info, 0, iflib_sysctl_int_delay, "I", description);
5856 iflib_ctx_lock_get(if_ctx_t ctx)
5859 return (&ctx->ifc_ctx_sx);
5863 iflib_msix_init(if_ctx_t ctx)
5865 device_t dev = ctx->ifc_dev;
5866 if_shared_ctx_t sctx = ctx->ifc_sctx;
5867 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5868 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5869 int iflib_num_tx_queues, iflib_num_rx_queues;
5870 int err, admincnt, bar;
5872 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5873 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5875 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5877 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5878 admincnt = sctx->isc_admin_intrcnt;
5879 /* Override by tuneable */
5880 if (scctx->isc_disable_msix)
5884 * bar == -1 => "trust me I know what I'm doing"
5885 * Some drivers are for hardware that is so shoddily
5886 * documented that no one knows which bars are which
5887 * so the developer has to map all bars. This hack
5888 * allows shoddy garbage to use msix in this framework.
5891 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5892 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5893 if (ctx->ifc_msix_mem == NULL) {
5894 /* May not be enabled */
5895 device_printf(dev, "Unable to map MSIX table \n");
5899 /* First try MSI/X */
5900 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5901 device_printf(dev, "System has MSIX disabled \n");
5902 bus_release_resource(dev, SYS_RES_MEMORY,
5903 bar, ctx->ifc_msix_mem);
5904 ctx->ifc_msix_mem = NULL;
5908 /* use only 1 qset in debug mode */
5909 queuemsgs = min(msgs - admincnt, 1);
5911 queuemsgs = msgs - admincnt;
5914 queues = imin(queuemsgs, rss_getnumbuckets());
5918 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5919 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5920 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5922 /* If we're doing RSS, clamp at the number of RSS buckets */
5923 if (queues > rss_getnumbuckets())
5924 queues = rss_getnumbuckets();
5926 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5927 rx_queues = iflib_num_rx_queues;
5931 if (rx_queues > scctx->isc_nrxqsets)
5932 rx_queues = scctx->isc_nrxqsets;
5935 * We want this to be all logical CPUs by default
5937 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5938 tx_queues = iflib_num_tx_queues;
5940 tx_queues = mp_ncpus;
5942 if (tx_queues > scctx->isc_ntxqsets)
5943 tx_queues = scctx->isc_ntxqsets;
5945 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5947 if (tx_queues != rx_queues)
5949 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5950 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5952 tx_queues = min(rx_queues, tx_queues);
5953 rx_queues = min(rx_queues, tx_queues);
5956 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5958 vectors = rx_queues + admincnt;
5959 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5960 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors);
5961 scctx->isc_vectors = vectors;
5962 scctx->isc_nrxqsets = rx_queues;
5963 scctx->isc_ntxqsets = tx_queues;
5964 scctx->isc_intr = IFLIB_INTR_MSIX;
5969 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5970 bus_release_resource(dev, SYS_RES_MEMORY, bar,
5972 ctx->ifc_msix_mem = NULL;
5975 vectors = pci_msi_count(dev);
5976 scctx->isc_nrxqsets = 1;
5977 scctx->isc_ntxqsets = 1;
5978 scctx->isc_vectors = vectors;
5979 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5980 device_printf(dev,"Using an MSI interrupt\n");
5981 scctx->isc_intr = IFLIB_INTR_MSI;
5983 scctx->isc_vectors = 1;
5984 device_printf(dev,"Using a Legacy interrupt\n");
5985 scctx->isc_intr = IFLIB_INTR_LEGACY;
5991 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5994 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5997 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5999 const char *ring_state = "UNKNOWN";
6002 rc = sysctl_wire_old_buffer(req, 0);
6006 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6011 ring_state = ring_states[state[3]];
6013 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6014 state[0], state[1], state[2], ring_state);
6015 rc = sbuf_finish(sb);
6020 enum iflib_ndesc_handler {
6026 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6028 if_ctx_t ctx = (void *)arg1;
6029 enum iflib_ndesc_handler type = arg2;
6030 char buf[256] = {0};
6035 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6039 case IFLIB_NTXD_HANDLER:
6040 ndesc = ctx->ifc_sysctl_ntxds;
6042 nqs = ctx->ifc_sctx->isc_ntxqs;
6044 case IFLIB_NRXD_HANDLER:
6045 ndesc = ctx->ifc_sysctl_nrxds;
6047 nqs = ctx->ifc_sctx->isc_nrxqs;
6050 panic("unhandled type");
6055 for (i=0; i<8; i++) {
6060 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6063 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6064 if (rc || req->newptr == NULL)
6067 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6068 i++, p = strsep(&next, " ,")) {
6069 ndesc[i] = strtoul(p, NULL, 10);
6075 #define NAME_BUFLEN 32
6077 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6079 device_t dev = iflib_get_dev(ctx);
6080 struct sysctl_oid_list *child, *oid_list;
6081 struct sysctl_ctx_list *ctx_list;
6082 struct sysctl_oid *node;
6084 ctx_list = device_get_sysctl_ctx(dev);
6085 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6086 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6087 CTLFLAG_RD, NULL, "IFLIB fields");
6088 oid_list = SYSCTL_CHILDREN(node);
6090 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6091 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6094 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6095 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6096 "# of txqs to use, 0 => use default #");
6097 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6098 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6099 "# of rxqs to use, 0 => use default #");
6100 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6101 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6102 "permit #txq != #rxq");
6103 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6104 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6105 "disable MSIX (default 0)");
6106 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6107 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6108 "set the rx budget");
6109 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6110 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6111 "cause tx to abdicate instead of running to completion");
6113 /* XXX change for per-queue sizes */
6114 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6115 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6116 mp_ndesc_handler, "A",
6117 "list of # of tx descriptors to use, 0 = use default #");
6118 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6119 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6120 mp_ndesc_handler, "A",
6121 "list of # of rx descriptors to use, 0 = use default #");
6125 iflib_add_device_sysctl_post(if_ctx_t ctx)
6127 if_shared_ctx_t sctx = ctx->ifc_sctx;
6128 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6129 device_t dev = iflib_get_dev(ctx);
6130 struct sysctl_oid_list *child;
6131 struct sysctl_ctx_list *ctx_list;
6136 char namebuf[NAME_BUFLEN];
6138 struct sysctl_oid *queue_node, *fl_node, *node;
6139 struct sysctl_oid_list *queue_list, *fl_list;
6140 ctx_list = device_get_sysctl_ctx(dev);
6142 node = ctx->ifc_sysctl_node;
6143 child = SYSCTL_CHILDREN(node);
6145 if (scctx->isc_ntxqsets > 100)
6147 else if (scctx->isc_ntxqsets > 10)
6151 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6152 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6153 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6154 CTLFLAG_RD, NULL, "Queue Name");
6155 queue_list = SYSCTL_CHILDREN(queue_node);
6157 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6159 &txq->ift_dequeued, "total mbufs freed");
6160 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6162 &txq->ift_enqueued, "total mbufs enqueued");
6164 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6166 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6167 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6169 &txq->ift_pullups, "# of times m_pullup was called");
6170 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6172 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6173 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6175 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6176 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6178 &txq->ift_map_failed, "# of times dma map failed");
6179 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6181 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6182 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6184 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6185 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6187 &txq->ift_pidx, 1, "Producer Index");
6188 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6190 &txq->ift_cidx, 1, "Consumer Index");
6191 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6193 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6194 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6196 &txq->ift_in_use, 1, "descriptors in use");
6197 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6199 &txq->ift_processed, "descriptors procesed for clean");
6200 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6202 &txq->ift_cleaned, "total cleaned");
6203 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6204 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6205 0, mp_ring_state_handler, "A", "soft ring state");
6206 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6207 CTLFLAG_RD, &txq->ift_br->enqueues,
6208 "# of enqueues to the mp_ring for this queue");
6209 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6210 CTLFLAG_RD, &txq->ift_br->drops,
6211 "# of drops in the mp_ring for this queue");
6212 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6213 CTLFLAG_RD, &txq->ift_br->starts,
6214 "# of normal consumer starts in the mp_ring for this queue");
6215 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6216 CTLFLAG_RD, &txq->ift_br->stalls,
6217 "# of consumer stalls in the mp_ring for this queue");
6218 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6219 CTLFLAG_RD, &txq->ift_br->restarts,
6220 "# of consumer restarts in the mp_ring for this queue");
6221 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6222 CTLFLAG_RD, &txq->ift_br->abdications,
6223 "# of consumer abdications in the mp_ring for this queue");
6226 if (scctx->isc_nrxqsets > 100)
6228 else if (scctx->isc_nrxqsets > 10)
6232 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6233 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6234 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6235 CTLFLAG_RD, NULL, "Queue Name");
6236 queue_list = SYSCTL_CHILDREN(queue_node);
6237 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6238 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6240 &rxq->ifr_cq_pidx, 1, "Producer Index");
6241 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6243 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6246 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6247 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6248 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6249 CTLFLAG_RD, NULL, "freelist Name");
6250 fl_list = SYSCTL_CHILDREN(fl_node);
6251 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6253 &fl->ifl_pidx, 1, "Producer Index");
6254 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6256 &fl->ifl_cidx, 1, "Consumer Index");
6257 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6259 &fl->ifl_credits, 1, "credits available");
6261 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6263 &fl->ifl_m_enqueued, "mbufs allocated");
6264 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6266 &fl->ifl_m_dequeued, "mbufs freed");
6267 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6269 &fl->ifl_cl_enqueued, "clusters allocated");
6270 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6272 &fl->ifl_cl_dequeued, "clusters freed");
6281 iflib_request_reset(if_ctx_t ctx)
6285 ctx->ifc_flags |= IFC_DO_RESET;
6289 #ifndef __NO_STRICT_ALIGNMENT
6290 static struct mbuf *
6291 iflib_fixup_rx(struct mbuf *m)
6295 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6296 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6297 m->m_data += ETHER_HDR_LEN;
6300 MGETHDR(n, M_NOWAIT, MT_DATA);
6305 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6306 m->m_data += ETHER_HDR_LEN;
6307 m->m_len -= ETHER_HDR_LEN;
6308 n->m_len = ETHER_HDR_LEN;
6309 M_MOVE_PKTHDR(n, m);
6318 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6322 ctx = if_getsoftc(ifp);
6324 *nrxr = NRXQSETS(ctx);
6325 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6326 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6331 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6334 if_softc_ctx_t scctx;
6339 ctx = if_getsoftc(ifp);
6340 scctx = &ctx->ifc_softc_ctx;
6344 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6345 rxq = &ctx->ifc_rxqs[i];
6346 for (j = 0; j < rxq->ifr_nfl; j++) {
6348 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6351 iflib_no_tx_batch = 1;
6359 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6365 ctx = if_getsoftc(ifp);
6366 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6370 txq = &ctx->ifc_txqs[0];
6371 error = iflib_encap(txq, &m);
6373 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6378 iflib_netdump_poll(struct ifnet *ifp, int count)
6381 if_softc_ctx_t scctx;
6385 ctx = if_getsoftc(ifp);
6386 scctx = &ctx->ifc_softc_ctx;
6388 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6392 txq = &ctx->ifc_txqs[0];
6393 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6395 for (i = 0; i < scctx->isc_nrxqsets; i++)
6396 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6399 #endif /* NETDUMP */