2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
96 #include <dev/pci/pci_iov.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
174 uint32_t ifc_rx_mbuf_sz;
177 int ifc_watchdog_events;
178 struct cdev *ifc_led_dev;
179 struct resource *ifc_msix_mem;
181 struct if_irq ifc_legacy_irq;
182 struct grouptask ifc_admin_task;
183 struct grouptask ifc_vflr_task;
184 struct iflib_filter_info ifc_filter_info;
185 struct ifmedia ifc_media;
187 struct sysctl_oid *ifc_sysctl_node;
188 uint16_t ifc_sysctl_ntxqs;
189 uint16_t ifc_sysctl_nrxqs;
190 uint16_t ifc_sysctl_qs_eq_override;
191 uint16_t ifc_sysctl_rx_budget;
192 uint16_t ifc_sysctl_tx_abdicate;
193 uint16_t ifc_sysctl_core_offset;
194 #define CORE_OFFSET_UNSPECIFIED 0xffff
195 uint8_t ifc_sysctl_separate_txrx;
197 qidx_t ifc_sysctl_ntxds[8];
198 qidx_t ifc_sysctl_nrxds[8];
199 struct if_txrx ifc_txrx;
200 #define isc_txd_encap ifc_txrx.ift_txd_encap
201 #define isc_txd_flush ifc_txrx.ift_txd_flush
202 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
203 #define isc_rxd_available ifc_txrx.ift_rxd_available
204 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
206 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 uint8_t ifc_mac[ETHER_ADDR_LEN];
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (&ctx->ifc_media);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_buf_tag;
357 bus_dma_tag_t ift_tso_buf_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 16
360 char ift_mtx_name[MTX_NAME_LEN];
361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 uint64_t ift_cpu_exec_count[256];
365 } __aligned(CACHE_LINE_SIZE);
372 uint8_t ifl_rxd_size;
374 uint64_t ifl_m_enqueued;
375 uint64_t ifl_m_dequeued;
376 uint64_t ifl_cl_enqueued;
377 uint64_t ifl_cl_dequeued;
381 bitstr_t *ifl_rx_bitmap;
385 uint16_t ifl_buf_size;
388 iflib_rxsd_array_t ifl_sds;
391 bus_dma_tag_t ifl_buf_tag;
392 iflib_dma_info_t ifl_ifdi;
393 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
394 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
395 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
396 } __aligned(CACHE_LINE_SIZE);
399 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
405 else if (pidx < cidx)
406 used = size - cidx + pidx;
407 else if (gen == 0 && pidx == cidx)
409 else if (gen == 1 && pidx == cidx)
417 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
419 #define IDXDIFF(head, tail, wrap) \
420 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
427 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
428 * the command queue consumer index. Otherwise it's unused.
434 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
435 uint8_t ifr_fl_offset;
436 struct lro_ctrl ifr_lc;
437 struct grouptask ifr_task;
438 struct iflib_filter_info ifr_filter_info;
439 iflib_dma_info_t ifr_ifdi;
441 /* dynamically allocate if any drivers need a value substantially larger than this */
442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 uint64_t ifr_cpu_exec_count[256];
446 } __aligned(CACHE_LINE_SIZE);
448 typedef struct if_rxsd {
450 struct mbuf **ifsd_m;
455 /* multiple of word size */
457 #define PKT_INFO_SIZE 6
458 #define RXD_INFO_SIZE 5
459 #define PKT_TYPE uint64_t
461 #define PKT_INFO_SIZE 11
462 #define RXD_INFO_SIZE 8
463 #define PKT_TYPE uint32_t
465 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
466 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
468 typedef struct if_pkt_info_pad {
469 PKT_TYPE pkt_val[PKT_INFO_SIZE];
470 } *if_pkt_info_pad_t;
471 typedef struct if_rxd_info_pad {
472 PKT_TYPE rxd_val[RXD_INFO_SIZE];
473 } *if_rxd_info_pad_t;
475 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
476 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
480 pkt_info_zero(if_pkt_info_t pi)
482 if_pkt_info_pad_t pi_pad;
484 pi_pad = (if_pkt_info_pad_t)pi;
485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
493 static device_method_t iflib_pseudo_methods[] = {
494 DEVMETHOD(device_attach, noop_attach),
495 DEVMETHOD(device_detach, iflib_pseudo_detach),
499 driver_t iflib_pseudodriver = {
500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
504 rxd_info_zero(if_rxd_info_t ri)
506 if_rxd_info_pad_t ri_pad;
509 ri_pad = (if_rxd_info_pad_t)ri;
510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
511 ri_pad->rxd_val[i] = 0;
512 ri_pad->rxd_val[i+1] = 0;
513 ri_pad->rxd_val[i+2] = 0;
514 ri_pad->rxd_val[i+3] = 0;
517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
522 * Only allow a single packet to take up most 1/nth of the tx ring
524 #define MAX_SINGLE_PACKET_FRACTION 12
525 #define IF_BAD_DMA (bus_addr_t)-1
527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
543 iflib_set_detach(if_ctx_t ctx)
546 ctx->ifc_flags |= IFC_IN_DETACH;
550 /* Our boot-time initialization hook */
551 static int iflib_module_event_handler(module_t, int, void *);
553 static moduledata_t iflib_moduledata = {
555 iflib_module_event_handler,
559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
560 MODULE_VERSION(iflib, 1);
562 MODULE_DEPEND(iflib, pci, 1, 1, 1);
563 MODULE_DEPEND(iflib, ether, 1, 1, 1);
565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
568 #ifndef IFLIB_DEBUG_COUNTERS
570 #define IFLIB_DEBUG_COUNTERS 1
572 #define IFLIB_DEBUG_COUNTERS 0
573 #endif /* !INVARIANTS */
576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
577 "iflib driver parameters");
580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
582 static int iflib_min_tx_latency = 0;
583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
585 static int iflib_no_tx_batch = 0;
586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
590 #if IFLIB_DEBUG_COUNTERS
592 static int iflib_tx_seen;
593 static int iflib_tx_sent;
594 static int iflib_tx_encap;
595 static int iflib_rx_allocs;
596 static int iflib_fl_refills;
597 static int iflib_fl_refills_large;
598 static int iflib_tx_frees;
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
601 &iflib_tx_seen, 0, "# TX mbufs seen");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
603 &iflib_tx_sent, 0, "# TX mbufs sent");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
605 &iflib_tx_encap, 0, "# TX mbufs encapped");
606 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
607 &iflib_tx_frees, 0, "# TX frees");
608 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
609 &iflib_rx_allocs, 0, "# RX allocations");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
611 &iflib_fl_refills, 0, "# refills");
612 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
613 &iflib_fl_refills_large, 0, "# large refills");
616 static int iflib_txq_drain_flushing;
617 static int iflib_txq_drain_oactive;
618 static int iflib_txq_drain_notready;
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
621 &iflib_txq_drain_flushing, 0, "# drain flushes");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
623 &iflib_txq_drain_oactive, 0, "# drain oactives");
624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
625 &iflib_txq_drain_notready, 0, "# drain notready");
628 static int iflib_encap_load_mbuf_fail;
629 static int iflib_encap_pad_mbuf_fail;
630 static int iflib_encap_txq_avail_fail;
631 static int iflib_encap_txd_encap_fail;
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
636 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
638 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
640 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
642 static int iflib_task_fn_rxs;
643 static int iflib_rx_intr_enables;
644 static int iflib_fast_intrs;
645 static int iflib_rx_unavail;
646 static int iflib_rx_ctx_inactive;
647 static int iflib_rx_if_input;
648 static int iflib_rx_mbuf_null;
649 static int iflib_rxd_flush;
651 static int iflib_verbose_debug;
653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
656 &iflib_rx_intr_enables, 0, "# RX intr enables");
657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
658 &iflib_fast_intrs, 0, "# fast_intr calls");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
660 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
664 &iflib_rx_if_input, 0, "# times rxeof called if_input");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
666 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
668 &iflib_rxd_flush, 0, "# times rxd_flush called");
669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
670 &iflib_verbose_debug, 0, "enable verbose debugging");
672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
674 iflib_debug_reset(void)
676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
678 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
679 iflib_txq_drain_notready =
680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
684 iflib_rx_ctx_inactive = iflib_rx_if_input =
685 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
689 #define DBG_COUNTER_INC(name)
690 static void iflib_debug_reset(void) {}
693 #define IFLIB_DEBUG 0
695 static void iflib_tx_structures_free(if_ctx_t ctx);
696 static void iflib_rx_structures_free(if_ctx_t ctx);
697 static int iflib_queues_alloc(if_ctx_t ctx);
698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
700 static int iflib_qset_structures_setup(if_ctx_t ctx);
701 static int iflib_msix_init(if_ctx_t ctx);
702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
706 static void iflib_altq_if_start(if_t ifp);
707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
709 static int iflib_register(if_ctx_t);
710 static void iflib_deregister(if_ctx_t);
711 static void iflib_init_locked(if_ctx_t ctx);
712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
713 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
714 static void iflib_ifmp_purge(iflib_txq_t txq);
715 static void _iflib_pre_assert(if_softc_ctx_t scctx);
716 static void iflib_if_init_locked(if_ctx_t ctx);
717 static void iflib_free_intr_mem(if_ctx_t ctx);
718 #ifndef __NO_STRICT_ALIGNMENT
719 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
723 SLIST_HEAD_INITIALIZER(cpu_offsets);
725 SLIST_ENTRY(cpu_offset) entries;
727 unsigned int refcount;
730 static struct mtx cpu_offset_mtx;
731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
734 NETDUMP_DEFINE(iflib);
737 #include <sys/selinfo.h>
738 #include <net/netmap.h>
739 #include <dev/netmap/netmap_kern.h>
741 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
746 * device-specific sysctl variables:
748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
749 * During regular operations the CRC is stripped, but on some
750 * hardware reception of frames not multiple of 64 is slower,
751 * so using crcstrip=0 helps in benchmarks.
753 * iflib_rx_miss, iflib_rx_miss_bufs:
754 * count packets that might be missed due to lost interrupts.
756 SYSCTL_DECL(_dev_netmap);
758 * The xl driver by default strips CRCs and we do not override it.
761 int iflib_crcstrip = 1;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
765 int iflib_rx_miss, iflib_rx_miss_bufs;
766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
772 * Register/unregister. We are already under netmap lock.
773 * Only called on the first register or the last unregister.
776 iflib_netmap_register(struct netmap_adapter *na, int onoff)
779 if_ctx_t ctx = ifp->if_softc;
783 IFDI_INTR_DISABLE(ctx);
785 /* Tell the stack that the interface is no longer active */
786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
791 /* enable or disable flags and callbacks in na and ifp */
793 nm_set_native_flags(na);
795 nm_clear_native_flags(na);
798 iflib_init_locked(ctx);
799 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
800 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
802 nm_clear_native_flags(na);
808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
810 struct netmap_adapter *na = kring->na;
811 u_int const lim = kring->nkr_num_slots - 1;
812 u_int head = kring->rhead;
813 struct netmap_ring *ring = kring->ring;
815 struct if_rxd_update iru;
816 if_ctx_t ctx = rxq->ifr_ctx;
817 iflib_fl_t fl = &rxq->ifr_fl[0];
818 uint32_t refill_pidx, nic_i;
819 #if IFLIB_DEBUG_COUNTERS
823 if (nm_i == head && __predict_true(!init))
825 iru_init(&iru, rxq, 0 /* flid */);
826 map = fl->ifl_sds.ifsd_map;
827 refill_pidx = netmap_idx_k2n(kring, nm_i);
829 * IMPORTANT: we must leave one free slot in the ring,
830 * so move head back by one unit
832 head = nm_prev(head, lim);
834 DBG_COUNTER_INC(fl_refills);
835 while (nm_i != head) {
836 #if IFLIB_DEBUG_COUNTERS
838 DBG_COUNTER_INC(fl_refills_large);
840 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
841 struct netmap_slot *slot = &ring->slot[nm_i];
842 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
843 uint32_t nic_i_dma = refill_pidx;
844 nic_i = netmap_idx_k2n(kring, nm_i);
846 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
848 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
849 return netmap_ring_reinit(kring);
851 fl->ifl_vm_addrs[tmp_pidx] = addr;
852 if (__predict_false(init)) {
853 netmap_load_map(na, fl->ifl_buf_tag,
855 } else if (slot->flags & NS_BUF_CHANGED) {
856 /* buffer has changed, reload map */
857 netmap_reload_map(na, fl->ifl_buf_tag,
860 slot->flags &= ~NS_BUF_CHANGED;
862 nm_i = nm_next(nm_i, lim);
863 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
864 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
867 iru.iru_pidx = refill_pidx;
868 iru.iru_count = tmp_pidx+1;
869 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
871 for (int n = 0; n < iru.iru_count; n++) {
872 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
873 BUS_DMASYNC_PREREAD);
874 /* XXX - change this to not use the netmap func*/
875 nic_i_dma = nm_next(nic_i_dma, lim);
879 kring->nr_hwcur = head;
881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
883 if (__predict_true(nic_i != UINT_MAX)) {
884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
885 DBG_COUNTER_INC(rxd_flush);
891 * Reconcile kernel and user view of the transmit ring.
893 * All information is in the kring.
894 * Userspace wants to send packets up to the one before kring->rhead,
895 * kernel knows kring->nr_hwcur is the first unsent packet.
897 * Here we push packets out (as many as possible), and possibly
898 * reclaim buffers from previously completed transmission.
900 * The caller (netmap) guarantees that there is only one instance
901 * running at any time. Any interference with other driver
902 * methods should be handled by the individual drivers.
905 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
907 struct netmap_adapter *na = kring->na;
909 struct netmap_ring *ring = kring->ring;
910 u_int nm_i; /* index into the netmap kring */
911 u_int nic_i; /* index into the NIC ring */
913 u_int const lim = kring->nkr_num_slots - 1;
914 u_int const head = kring->rhead;
915 struct if_pkt_info pi;
918 * interrupts on every tx packet are expensive so request
919 * them every half ring, or where NS_REPORT is set
921 u_int report_frequency = kring->nkr_num_slots >> 1;
922 /* device-specific */
923 if_ctx_t ctx = ifp->if_softc;
924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
926 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
930 * First part: process new packets to send.
931 * nm_i is the current index in the netmap kring,
932 * nic_i is the corresponding index in the NIC ring.
934 * If we have packets to send (nm_i != head)
935 * iterate over the netmap ring, fetch length and update
936 * the corresponding slot in the NIC ring. Some drivers also
937 * need to update the buffer's physical address in the NIC slot
938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
940 * The netmap_reload_map() calls is especially expensive,
941 * even when (as in this case) the tag is 0, so do only
942 * when the buffer has actually changed.
944 * If possible do not set the report/intr bit on all slots,
945 * but only a few times per ring or when NS_REPORT is set.
947 * Finally, on 10G and faster drivers, it might be useful
948 * to prefetch the next slot and txr entry.
951 nm_i = kring->nr_hwcur;
952 if (nm_i != head) { /* we have new packets to send */
954 pi.ipi_segs = txq->ift_segs;
955 pi.ipi_qsidx = kring->ring_id;
956 nic_i = netmap_idx_k2n(kring, nm_i);
958 __builtin_prefetch(&ring->slot[nm_i]);
959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
962 for (n = 0; nm_i != head; n++) {
963 struct netmap_slot *slot = &ring->slot[nm_i];
964 u_int len = slot->len;
966 void *addr = PNMB(na, slot, &paddr);
967 int flags = (slot->flags & NS_REPORT ||
968 nic_i == 0 || nic_i == report_frequency) ?
971 /* device-specific */
973 pi.ipi_segs[0].ds_addr = paddr;
974 pi.ipi_segs[0].ds_len = len;
978 pi.ipi_flags = flags;
980 /* Fill the slot in the NIC ring. */
981 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
982 DBG_COUNTER_INC(tx_encap);
984 /* prefetch for next round */
985 __builtin_prefetch(&ring->slot[nm_i + 1]);
986 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
989 NM_CHECK_ADDR_LEN(na, addr, len);
991 if (slot->flags & NS_BUF_CHANGED) {
992 /* buffer has changed, reload map */
993 netmap_reload_map(na, txq->ift_buf_tag,
994 txq->ift_sds.ifsd_map[nic_i], addr);
996 /* make sure changes to the buffer are synced */
997 bus_dmamap_sync(txq->ift_buf_tag,
998 txq->ift_sds.ifsd_map[nic_i],
999 BUS_DMASYNC_PREWRITE);
1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1002 nm_i = nm_next(nm_i, lim);
1003 nic_i = nm_next(nic_i, lim);
1005 kring->nr_hwcur = nm_i;
1007 /* synchronize the NIC ring */
1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1011 /* (re)start the tx unit up to slot nic_i (excluded) */
1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1016 * Second part: reclaim buffers for completed transmissions.
1018 * If there are unclaimed buffers, attempt to reclaim them.
1019 * If none are reclaimed, and TX IRQs are not in use, do an initial
1020 * minimal delay, then trigger the tx handler which will spin in the
1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1024 if (iflib_tx_credits_update(ctx, txq)) {
1025 /* some tx completed, increment avail */
1026 nic_i = txq->ift_cidx_processed;
1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1033 iflib_timer, txq, txq->ift_timer.c_cpu);
1039 * Reconcile kernel and user view of the receive ring.
1040 * Same as for the txsync, this routine must be efficient.
1041 * The caller guarantees a single invocations, but races against
1042 * the rest of the driver should be handled here.
1044 * On call, kring->rhead is the first packet that userspace wants
1045 * to keep, and kring->rcur is the wakeup point.
1046 * The kernel has previously reported packets up to kring->rtail.
1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1049 * of whether or not we received an interrupt.
1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1054 struct netmap_adapter *na = kring->na;
1055 struct netmap_ring *ring = kring->ring;
1058 uint32_t nm_i; /* index into the netmap ring */
1059 uint32_t nic_i; /* index into the NIC ring */
1061 u_int const lim = kring->nkr_num_slots - 1;
1062 u_int const head = kring->rhead;
1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1064 struct if_rxd_info ri;
1066 if_ctx_t ctx = ifp->if_softc;
1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1069 return netmap_ring_reinit(kring);
1072 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1075 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1081 * First part: import newly received packets.
1083 * nm_i is the index of the next free slot in the netmap ring,
1084 * nic_i is the index of the next received packet in the NIC ring,
1085 * and they may differ in case if_init() has been called while
1086 * in netmap mode. For the receive ring we have
1088 * nic_i = rxr->next_check;
1089 * nm_i = kring->nr_hwtail (previous)
1091 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1093 * rxr->next_check is set to 0 on a ring reinit
1095 if (netmap_no_pendintr || force_update) {
1096 int crclen = iflib_crcstrip ? 0 : 4;
1099 for (i = 0; i < rxq->ifr_nfl; i++) {
1100 fl = &rxq->ifr_fl[i];
1101 nic_i = fl->ifl_cidx;
1102 nm_i = netmap_idx_n2k(kring, nic_i);
1103 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1104 rxq->ifr_id, nic_i, USHRT_MAX);
1105 for (n = 0; avail > 0; n++, avail--) {
1107 ri.iri_frags = rxq->ifr_frags;
1108 ri.iri_qsidx = kring->ring_id;
1109 ri.iri_ifp = ctx->ifc_ifp;
1110 ri.iri_cidx = nic_i;
1112 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1113 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1114 ring->slot[nm_i].flags = 0;
1115 bus_dmamap_sync(fl->ifl_buf_tag,
1116 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1117 nm_i = nm_next(nm_i, lim);
1118 nic_i = nm_next(nic_i, lim);
1120 if (n) { /* update the state variables */
1121 if (netmap_no_pendintr && !force_update) {
1124 iflib_rx_miss_bufs += n;
1126 fl->ifl_cidx = nic_i;
1127 kring->nr_hwtail = nm_i;
1129 kring->nr_kflags &= ~NKR_PENDINTR;
1133 * Second part: skip past packets that userspace has released.
1134 * (kring->nr_hwcur to head excluded),
1135 * and make the buffers available for reception.
1136 * As usual nm_i is the index in the netmap ring,
1137 * nic_i is the index in the NIC ring, and
1138 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1140 /* XXX not sure how this will work with multiple free lists */
1141 nm_i = kring->nr_hwcur;
1143 return (netmap_fl_refill(rxq, kring, nm_i, false));
1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1149 if_ctx_t ctx = na->ifp->if_softc;
1153 IFDI_INTR_ENABLE(ctx);
1155 IFDI_INTR_DISABLE(ctx);
1162 iflib_netmap_attach(if_ctx_t ctx)
1164 struct netmap_adapter na;
1165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1167 bzero(&na, sizeof(na));
1169 na.ifp = ctx->ifc_ifp;
1170 na.na_flags = NAF_BDG_MAYSLEEP;
1171 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1172 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1174 na.num_tx_desc = scctx->isc_ntxd[0];
1175 na.num_rx_desc = scctx->isc_nrxd[0];
1176 na.nm_txsync = iflib_netmap_txsync;
1177 na.nm_rxsync = iflib_netmap_rxsync;
1178 na.nm_register = iflib_netmap_register;
1179 na.nm_intr = iflib_netmap_intr;
1180 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1181 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1182 return (netmap_attach(&na));
1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1188 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1189 struct netmap_slot *slot;
1191 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1194 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1197 * In netmap mode, set the map for the packet buffer.
1198 * NOTE: Some drivers (not this one) also need to set
1199 * the physical buffer address in the NIC ring.
1200 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1201 * netmap slot index, si
1203 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1204 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1205 NMB(na, slot + si));
1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1212 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1213 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1214 struct netmap_slot *slot;
1217 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1220 nm_i = netmap_idx_n2k(kring, 0);
1221 netmap_fl_refill(rxq, kring, nm_i, true);
1225 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1227 struct netmap_kring *kring;
1230 txqid = txq->ift_id;
1231 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1233 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1234 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1235 BUS_DMASYNC_POSTREAD);
1236 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1237 netmap_tx_irq(ctx->ifc_ifp, txqid);
1238 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1242 *reset_on = hz / 1000;
1247 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1250 #define iflib_netmap_txq_init(ctx, txq)
1251 #define iflib_netmap_rxq_init(ctx, rxq)
1252 #define iflib_netmap_detach(ifp)
1254 #define iflib_netmap_attach(ctx) (0)
1255 #define netmap_rx_irq(ifp, qid, budget) (0)
1256 #define netmap_tx_irq(ifp, qid) do {} while (0)
1257 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1261 #if defined(__i386__) || defined(__amd64__)
1262 static __inline void
1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1267 static __inline void
1268 prefetch2cachelines(void *x)
1270 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1271 #if (CACHE_LINE_SIZE < 128)
1272 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1277 #define prefetch2cachelines(x)
1281 iflib_gen_mac(if_ctx_t ctx)
1285 char uuid[HOSTUUIDLEN+1];
1286 char buf[HOSTUUIDLEN+16];
1288 unsigned char digest[16];
1292 uuid[HOSTUUIDLEN] = 0;
1293 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1294 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1296 * Generate a pseudo-random, deterministic MAC
1297 * address based on the UUID and unit number.
1298 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1301 MD5Update(&mdctx, buf, strlen(buf));
1302 MD5Final(digest, &mdctx);
1313 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1317 fl = &rxq->ifr_fl[flid];
1318 iru->iru_paddrs = fl->ifl_bus_addrs;
1319 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1320 iru->iru_idxs = fl->ifl_rxd_idxs;
1321 iru->iru_qsidx = rxq->ifr_id;
1322 iru->iru_buf_size = fl->ifl_buf_size;
1323 iru->iru_flidx = fl->ifl_id;
1327 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1331 *(bus_addr_t *) arg = segs[0].ds_addr;
1335 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1338 device_t dev = ctx->ifc_dev;
1340 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1341 align, 0, /* alignment, bounds */
1342 BUS_SPACE_MAXADDR, /* lowaddr */
1343 BUS_SPACE_MAXADDR, /* highaddr */
1344 NULL, NULL, /* filter, filterarg */
1347 size, /* maxsegsize */
1348 BUS_DMA_ALLOCNOW, /* flags */
1349 NULL, /* lockfunc */
1354 "%s: bus_dma_tag_create failed: %d\n",
1359 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1360 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1363 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1364 __func__, (uintmax_t)size, err);
1368 dma->idi_paddr = IF_BAD_DMA;
1369 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1370 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1371 if (err || dma->idi_paddr == IF_BAD_DMA) {
1373 "%s: bus_dmamap_load failed: %d\n",
1378 dma->idi_size = size;
1382 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1384 bus_dma_tag_destroy(dma->idi_tag);
1386 dma->idi_tag = NULL;
1392 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1394 if_shared_ctx_t sctx = ctx->ifc_sctx;
1396 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1398 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1402 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1405 iflib_dma_info_t *dmaiter;
1408 for (i = 0; i < count; i++, dmaiter++) {
1409 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1413 iflib_dma_free_multi(dmalist, i);
1418 iflib_dma_free(iflib_dma_info_t dma)
1420 if (dma->idi_tag == NULL)
1422 if (dma->idi_paddr != IF_BAD_DMA) {
1423 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1424 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1425 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1426 dma->idi_paddr = IF_BAD_DMA;
1428 if (dma->idi_vaddr != NULL) {
1429 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1430 dma->idi_vaddr = NULL;
1432 bus_dma_tag_destroy(dma->idi_tag);
1433 dma->idi_tag = NULL;
1437 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1440 iflib_dma_info_t *dmaiter = dmalist;
1442 for (i = 0; i < count; i++, dmaiter++)
1443 iflib_dma_free(*dmaiter);
1446 #ifdef EARLY_AP_STARTUP
1447 static const int iflib_started = 1;
1450 * We used to abuse the smp_started flag to decide if the queues have been
1451 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1452 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1453 * is set. Run a SYSINIT() strictly after that to just set a usable
1457 static int iflib_started;
1460 iflib_record_started(void *arg)
1465 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1466 iflib_record_started, NULL);
1470 iflib_fast_intr(void *arg)
1472 iflib_filter_info_t info = arg;
1473 struct grouptask *gtask = info->ifi_task;
1477 return (FILTER_STRAY);
1479 DBG_COUNTER_INC(fast_intrs);
1480 if (info->ifi_filter != NULL) {
1481 result = info->ifi_filter(info->ifi_filter_arg);
1482 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1486 GROUPTASK_ENQUEUE(gtask);
1487 return (FILTER_HANDLED);
1491 iflib_fast_intr_rxtx(void *arg)
1493 iflib_filter_info_t info = arg;
1494 struct grouptask *gtask = info->ifi_task;
1496 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1499 int i, cidx, result;
1501 bool intr_enable, intr_legacy;
1504 return (FILTER_STRAY);
1506 DBG_COUNTER_INC(fast_intrs);
1507 if (info->ifi_filter != NULL) {
1508 result = info->ifi_filter(info->ifi_filter_arg);
1509 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1514 sc = ctx->ifc_softc;
1515 intr_enable = false;
1516 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1517 MPASS(rxq->ifr_ntxqirq);
1518 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1519 txqid = rxq->ifr_txqid[i];
1520 txq = &ctx->ifc_txqs[txqid];
1521 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1522 BUS_DMASYNC_POSTREAD);
1523 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1527 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1530 GROUPTASK_ENQUEUE(&txq->ift_task);
1532 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1533 cidx = rxq->ifr_cq_cidx;
1535 cidx = rxq->ifr_fl[0].ifl_cidx;
1536 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1537 GROUPTASK_ENQUEUE(gtask);
1542 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1543 DBG_COUNTER_INC(rx_intr_enables);
1546 IFDI_INTR_ENABLE(ctx);
1547 return (FILTER_HANDLED);
1552 iflib_fast_intr_ctx(void *arg)
1554 iflib_filter_info_t info = arg;
1555 struct grouptask *gtask = info->ifi_task;
1559 return (FILTER_STRAY);
1561 DBG_COUNTER_INC(fast_intrs);
1562 if (info->ifi_filter != NULL) {
1563 result = info->ifi_filter(info->ifi_filter_arg);
1564 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1568 GROUPTASK_ENQUEUE(gtask);
1569 return (FILTER_HANDLED);
1573 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1574 driver_filter_t filter, driver_intr_t handler, void *arg,
1578 struct resource *res;
1580 device_t dev = ctx->ifc_dev;
1583 if (ctx->ifc_flags & IFC_LEGACY)
1584 flags |= RF_SHAREABLE;
1587 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1590 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1594 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1595 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1596 filter, handler, arg, &tag);
1599 "failed to setup interrupt for rid %d, name %s: %d\n",
1600 rid, name ? name : "unknown", rc);
1603 bus_describe_intr(dev, res, tag, "%s", name);
1610 /*********************************************************************
1612 * Allocate DMA resources for TX buffers as well as memory for the TX
1613 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1614 * iflib_sw_tx_desc_array structure, storing all the information that
1615 * is needed to transmit a packet on the wire. This is called only
1616 * once at attach, setup is done every reset.
1618 **********************************************************************/
1620 iflib_txsd_alloc(iflib_txq_t txq)
1622 if_ctx_t ctx = txq->ift_ctx;
1623 if_shared_ctx_t sctx = ctx->ifc_sctx;
1624 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1625 device_t dev = ctx->ifc_dev;
1626 bus_size_t tsomaxsize;
1627 int err, nsegments, ntsosegments;
1630 nsegments = scctx->isc_tx_nsegments;
1631 ntsosegments = scctx->isc_tx_tso_segments_max;
1632 tsomaxsize = scctx->isc_tx_tso_size_max;
1633 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1634 tsomaxsize += sizeof(struct ether_vlan_header);
1635 MPASS(scctx->isc_ntxd[0] > 0);
1636 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1637 MPASS(nsegments > 0);
1638 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1639 MPASS(ntsosegments > 0);
1640 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1644 * Set up DMA tags for TX buffers.
1646 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1647 1, 0, /* alignment, bounds */
1648 BUS_SPACE_MAXADDR, /* lowaddr */
1649 BUS_SPACE_MAXADDR, /* highaddr */
1650 NULL, NULL, /* filter, filterarg */
1651 sctx->isc_tx_maxsize, /* maxsize */
1652 nsegments, /* nsegments */
1653 sctx->isc_tx_maxsegsize, /* maxsegsize */
1655 NULL, /* lockfunc */
1656 NULL, /* lockfuncarg */
1657 &txq->ift_buf_tag))) {
1658 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1659 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1660 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1663 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1664 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1665 1, 0, /* alignment, bounds */
1666 BUS_SPACE_MAXADDR, /* lowaddr */
1667 BUS_SPACE_MAXADDR, /* highaddr */
1668 NULL, NULL, /* filter, filterarg */
1669 tsomaxsize, /* maxsize */
1670 ntsosegments, /* nsegments */
1671 sctx->isc_tso_maxsegsize,/* maxsegsize */
1673 NULL, /* lockfunc */
1674 NULL, /* lockfuncarg */
1675 &txq->ift_tso_buf_tag))) {
1676 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1681 /* Allocate memory for the TX mbuf map. */
1682 if (!(txq->ift_sds.ifsd_m =
1683 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1684 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1685 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1691 * Create the DMA maps for TX buffers.
1693 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1694 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1695 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1697 "Unable to allocate TX buffer DMA map memory\n");
1701 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1702 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1703 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1705 "Unable to allocate TSO TX buffer map memory\n");
1709 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1710 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1711 &txq->ift_sds.ifsd_map[i]);
1713 device_printf(dev, "Unable to create TX DMA map\n");
1718 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1719 &txq->ift_sds.ifsd_tso_map[i]);
1721 device_printf(dev, "Unable to create TSO TX DMA map\n");
1727 /* We free all, it handles case where we are in the middle */
1728 iflib_tx_structures_free(ctx);
1733 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1738 if (txq->ift_sds.ifsd_map != NULL)
1739 map = txq->ift_sds.ifsd_map[i];
1741 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1742 bus_dmamap_unload(txq->ift_buf_tag, map);
1743 bus_dmamap_destroy(txq->ift_buf_tag, map);
1744 txq->ift_sds.ifsd_map[i] = NULL;
1748 if (txq->ift_sds.ifsd_tso_map != NULL)
1749 map = txq->ift_sds.ifsd_tso_map[i];
1751 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1752 BUS_DMASYNC_POSTWRITE);
1753 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1754 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1755 txq->ift_sds.ifsd_tso_map[i] = NULL;
1760 iflib_txq_destroy(iflib_txq_t txq)
1762 if_ctx_t ctx = txq->ift_ctx;
1764 for (int i = 0; i < txq->ift_size; i++)
1765 iflib_txsd_destroy(ctx, txq, i);
1766 if (txq->ift_sds.ifsd_map != NULL) {
1767 free(txq->ift_sds.ifsd_map, M_IFLIB);
1768 txq->ift_sds.ifsd_map = NULL;
1770 if (txq->ift_sds.ifsd_tso_map != NULL) {
1771 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1772 txq->ift_sds.ifsd_tso_map = NULL;
1774 if (txq->ift_sds.ifsd_m != NULL) {
1775 free(txq->ift_sds.ifsd_m, M_IFLIB);
1776 txq->ift_sds.ifsd_m = NULL;
1778 if (txq->ift_buf_tag != NULL) {
1779 bus_dma_tag_destroy(txq->ift_buf_tag);
1780 txq->ift_buf_tag = NULL;
1782 if (txq->ift_tso_buf_tag != NULL) {
1783 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1784 txq->ift_tso_buf_tag = NULL;
1789 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1793 mp = &txq->ift_sds.ifsd_m[i];
1797 if (txq->ift_sds.ifsd_map != NULL) {
1798 bus_dmamap_sync(txq->ift_buf_tag,
1799 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1800 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1802 if (txq->ift_sds.ifsd_tso_map != NULL) {
1803 bus_dmamap_sync(txq->ift_tso_buf_tag,
1804 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1805 bus_dmamap_unload(txq->ift_tso_buf_tag,
1806 txq->ift_sds.ifsd_tso_map[i]);
1809 DBG_COUNTER_INC(tx_frees);
1814 iflib_txq_setup(iflib_txq_t txq)
1816 if_ctx_t ctx = txq->ift_ctx;
1817 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1818 if_shared_ctx_t sctx = ctx->ifc_sctx;
1819 iflib_dma_info_t di;
1822 /* Set number of descriptors available */
1823 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1824 /* XXX make configurable */
1825 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1828 txq->ift_cidx_processed = 0;
1829 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1830 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1832 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1833 bzero((void *)di->idi_vaddr, di->idi_size);
1835 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1836 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1837 bus_dmamap_sync(di->idi_tag, di->idi_map,
1838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1842 /*********************************************************************
1844 * Allocate DMA resources for RX buffers as well as memory for the RX
1845 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1846 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1847 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1848 * Since we use use one entry in iflib_sw_rx_desc_array per received
1849 * packet, the maximum number of entries we'll need is equal to the
1850 * number of hardware receive descriptors that we've allocated.
1852 **********************************************************************/
1854 iflib_rxsd_alloc(iflib_rxq_t rxq)
1856 if_ctx_t ctx = rxq->ifr_ctx;
1857 if_shared_ctx_t sctx = ctx->ifc_sctx;
1858 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1859 device_t dev = ctx->ifc_dev;
1863 MPASS(scctx->isc_nrxd[0] > 0);
1864 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1867 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1868 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1869 /* Set up DMA tag for RX buffers. */
1870 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1871 1, 0, /* alignment, bounds */
1872 BUS_SPACE_MAXADDR, /* lowaddr */
1873 BUS_SPACE_MAXADDR, /* highaddr */
1874 NULL, NULL, /* filter, filterarg */
1875 sctx->isc_rx_maxsize, /* maxsize */
1876 sctx->isc_rx_nsegments, /* nsegments */
1877 sctx->isc_rx_maxsegsize, /* maxsegsize */
1879 NULL, /* lockfunc */
1884 "Unable to allocate RX DMA tag: %d\n", err);
1888 /* Allocate memory for the RX mbuf map. */
1889 if (!(fl->ifl_sds.ifsd_m =
1890 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1891 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1893 "Unable to allocate RX mbuf map memory\n");
1898 /* Allocate memory for the direct RX cluster pointer map. */
1899 if (!(fl->ifl_sds.ifsd_cl =
1900 (caddr_t *) malloc(sizeof(caddr_t) *
1901 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1903 "Unable to allocate RX cluster map memory\n");
1908 /* Allocate memory for the RX cluster bus address map. */
1909 if (!(fl->ifl_sds.ifsd_ba =
1910 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1911 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1913 "Unable to allocate RX bus address map memory\n");
1919 * Create the DMA maps for RX buffers.
1921 if (!(fl->ifl_sds.ifsd_map =
1922 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1924 "Unable to allocate RX buffer DMA map memory\n");
1928 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1929 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1930 &fl->ifl_sds.ifsd_map[i]);
1932 device_printf(dev, "Unable to create RX buffer DMA map\n");
1940 iflib_rx_structures_free(ctx);
1946 * Internal service routines
1949 struct rxq_refill_cb_arg {
1951 bus_dma_segment_t seg;
1956 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1958 struct rxq_refill_cb_arg *cb_arg = arg;
1960 cb_arg->error = error;
1961 cb_arg->seg = segs[0];
1962 cb_arg->nseg = nseg;
1966 * _iflib_fl_refill - refill an rxq free-buffer list
1967 * @ctx: the iflib context
1968 * @fl: the free list to refill
1969 * @count: the number of new buffers to allocate
1971 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1972 * The caller must assure that @count does not exceed the queue's capacity.
1975 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1977 struct if_rxd_update iru;
1978 struct rxq_refill_cb_arg cb_arg;
1982 bus_dmamap_t *sd_map;
1983 bus_addr_t bus_addr, *sd_ba;
1984 int err, frag_idx, i, idx, n, pidx;
1987 sd_m = fl->ifl_sds.ifsd_m;
1988 sd_map = fl->ifl_sds.ifsd_map;
1989 sd_cl = fl->ifl_sds.ifsd_cl;
1990 sd_ba = fl->ifl_sds.ifsd_ba;
1991 pidx = fl->ifl_pidx;
1993 frag_idx = fl->ifl_fragidx;
1994 credits = fl->ifl_credits;
1999 MPASS(credits + n <= fl->ifl_size);
2001 if (pidx < fl->ifl_cidx)
2002 MPASS(pidx + n <= fl->ifl_cidx);
2003 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2004 MPASS(fl->ifl_gen == 0);
2005 if (pidx > fl->ifl_cidx)
2006 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2008 DBG_COUNTER_INC(fl_refills);
2010 DBG_COUNTER_INC(fl_refills_large);
2011 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2014 * We allocate an uninitialized mbuf + cluster, mbuf is
2015 * initialized after rx.
2017 * If the cluster is still set then we know a minimum sized packet was received
2019 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2022 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2023 MPASS(frag_idx >= 0);
2024 if ((cl = sd_cl[frag_idx]) == NULL) {
2025 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
2029 MPASS(sd_map != NULL);
2030 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2031 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2033 if (err != 0 || cb_arg.error) {
2037 if (fl->ifl_zone == zone_pack)
2038 uma_zfree(fl->ifl_zone, cl);
2042 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2043 sd_cl[frag_idx] = cl;
2045 fl->ifl_cl_enqueued++;
2048 bus_addr = sd_ba[frag_idx];
2050 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2051 BUS_DMASYNC_PREREAD);
2053 MPASS(sd_m[frag_idx] == NULL);
2054 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2058 bit_set(fl->ifl_rx_bitmap, frag_idx);
2060 fl->ifl_m_enqueued++;
2063 DBG_COUNTER_INC(rx_allocs);
2064 fl->ifl_rxd_idxs[i] = frag_idx;
2065 fl->ifl_bus_addrs[i] = bus_addr;
2066 fl->ifl_vm_addrs[i] = cl;
2069 MPASS(credits <= fl->ifl_size);
2070 if (++idx == fl->ifl_size) {
2074 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2075 iru.iru_pidx = pidx;
2077 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2081 fl->ifl_credits = credits;
2086 iru.iru_pidx = pidx;
2088 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2090 fl->ifl_credits = credits;
2092 DBG_COUNTER_INC(rxd_flush);
2093 if (fl->ifl_pidx == 0)
2094 pidx = fl->ifl_size - 1;
2096 pidx = fl->ifl_pidx - 1;
2098 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2099 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2100 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2101 fl->ifl_fragidx = frag_idx;
2104 static __inline void
2105 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2107 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2108 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2110 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2113 MPASS(fl->ifl_credits <= fl->ifl_size);
2114 MPASS(reclaimable == delta);
2116 if (reclaimable > 0)
2117 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2121 iflib_in_detach(if_ctx_t ctx)
2126 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2132 iflib_fl_bufs_free(iflib_fl_t fl)
2134 iflib_dma_info_t idi = fl->ifl_ifdi;
2135 bus_dmamap_t sd_map;
2138 for (i = 0; i < fl->ifl_size; i++) {
2139 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2140 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2142 if (*sd_cl != NULL) {
2143 sd_map = fl->ifl_sds.ifsd_map[i];
2144 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2145 BUS_DMASYNC_POSTREAD);
2146 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2148 uma_zfree(fl->ifl_zone, *sd_cl);
2149 // XXX: Should this get moved out?
2150 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2151 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2152 if (*sd_m != NULL) {
2153 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2154 uma_zfree(zone_mbuf, *sd_m);
2157 MPASS(*sd_cl == NULL);
2158 MPASS(*sd_m == NULL);
2161 fl->ifl_m_dequeued++;
2162 fl->ifl_cl_dequeued++;
2168 for (i = 0; i < fl->ifl_size; i++) {
2169 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2170 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2174 * Reset free list values
2176 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2177 bzero(idi->idi_vaddr, idi->idi_size);
2180 /*********************************************************************
2182 * Initialize a free list and its buffers.
2184 **********************************************************************/
2186 iflib_fl_setup(iflib_fl_t fl)
2188 iflib_rxq_t rxq = fl->ifl_rxq;
2189 if_ctx_t ctx = rxq->ifr_ctx;
2191 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2193 ** Free current RX buffer structs and their mbufs
2195 iflib_fl_bufs_free(fl);
2196 /* Now replenish the mbufs */
2197 MPASS(fl->ifl_credits == 0);
2198 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2199 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2200 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2201 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2202 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2205 /* avoid pre-allocating zillions of clusters to an idle card
2206 * potentially speeding up attach
2208 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2209 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2210 if (min(128, fl->ifl_size) != fl->ifl_credits)
2216 MPASS(fl->ifl_ifdi != NULL);
2217 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2218 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2222 /*********************************************************************
2224 * Free receive ring data structures
2226 **********************************************************************/
2228 iflib_rx_sds_free(iflib_rxq_t rxq)
2233 if (rxq->ifr_fl != NULL) {
2234 for (i = 0; i < rxq->ifr_nfl; i++) {
2235 fl = &rxq->ifr_fl[i];
2236 if (fl->ifl_buf_tag != NULL) {
2237 if (fl->ifl_sds.ifsd_map != NULL) {
2238 for (j = 0; j < fl->ifl_size; j++) {
2239 if (fl->ifl_sds.ifsd_map[j] ==
2244 fl->ifl_sds.ifsd_map[j],
2245 BUS_DMASYNC_POSTREAD);
2248 fl->ifl_sds.ifsd_map[j]);
2251 bus_dma_tag_destroy(fl->ifl_buf_tag);
2252 fl->ifl_buf_tag = NULL;
2254 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2255 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2256 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2257 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2258 fl->ifl_sds.ifsd_m = NULL;
2259 fl->ifl_sds.ifsd_cl = NULL;
2260 fl->ifl_sds.ifsd_ba = NULL;
2261 fl->ifl_sds.ifsd_map = NULL;
2263 free(rxq->ifr_fl, M_IFLIB);
2265 rxq->ifr_cq_cidx = 0;
2273 iflib_timer(void *arg)
2275 iflib_txq_t txq = arg;
2276 if_ctx_t ctx = txq->ift_ctx;
2277 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2278 uint64_t this_tick = ticks;
2279 uint32_t reset_on = hz / 2;
2281 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2285 ** Check on the state of the TX queue(s), this
2286 ** can be done without the lock because its RO
2287 ** and the HUNG state will be static if set.
2289 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2290 txq->ift_last_timer_tick = this_tick;
2291 IFDI_TIMER(ctx, txq->ift_id);
2292 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2293 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2294 (sctx->isc_pause_frames == 0)))
2297 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2298 ifmp_ring_is_stalled(txq->ift_br)) {
2299 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2300 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2302 txq->ift_cleaned_prev = txq->ift_cleaned;
2305 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2306 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2308 /* handle any laggards */
2309 if (txq->ift_db_pending)
2310 GROUPTASK_ENQUEUE(&txq->ift_task);
2312 sctx->isc_pause_frames = 0;
2313 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2314 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2318 device_printf(ctx->ifc_dev,
2319 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2320 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2322 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2323 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2324 iflib_admin_intr_deferred(ctx);
2329 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2331 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2334 * XXX don't set the max_frame_size to larger
2335 * than the hardware can handle
2337 if (sctx->isc_max_frame_size <= MCLBYTES)
2338 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2340 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2344 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2347 return (ctx->ifc_rx_mbuf_sz);
2351 iflib_init_locked(if_ctx_t ctx)
2353 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2354 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2355 if_t ifp = ctx->ifc_ifp;
2359 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2361 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2362 IFDI_INTR_DISABLE(ctx);
2364 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2365 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2366 /* Set hardware offload abilities */
2367 if_clearhwassist(ifp);
2368 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2369 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2370 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2371 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2372 if (if_getcapenable(ifp) & IFCAP_TSO4)
2373 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2374 if (if_getcapenable(ifp) & IFCAP_TSO6)
2375 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2377 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2379 callout_stop(&txq->ift_timer);
2380 CALLOUT_UNLOCK(txq);
2381 iflib_netmap_txq_init(ctx, txq);
2385 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2386 * that drivers can use the value when setting up the hardware receive
2389 iflib_calc_rx_mbuf_sz(ctx);
2392 i = if_getdrvflags(ifp);
2395 MPASS(if_getdrvflags(ifp) == i);
2396 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2397 /* XXX this should really be done on a per-queue basis */
2398 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2399 MPASS(rxq->ifr_id == i);
2400 iflib_netmap_rxq_init(ctx, rxq);
2403 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2404 if (iflib_fl_setup(fl)) {
2405 device_printf(ctx->ifc_dev,
2406 "setting up free list %d failed - "
2407 "check cluster settings\n", j);
2413 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2414 IFDI_INTR_ENABLE(ctx);
2415 txq = ctx->ifc_txqs;
2416 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2417 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2418 txq->ift_timer.c_cpu);
2422 iflib_media_change(if_t ifp)
2424 if_ctx_t ctx = if_getsoftc(ifp);
2428 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2429 iflib_init_locked(ctx);
2435 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2437 if_ctx_t ctx = if_getsoftc(ifp);
2440 IFDI_UPDATE_ADMIN_STATUS(ctx);
2441 IFDI_MEDIA_STATUS(ctx, ifmr);
2446 iflib_stop(if_ctx_t ctx)
2448 iflib_txq_t txq = ctx->ifc_txqs;
2449 iflib_rxq_t rxq = ctx->ifc_rxqs;
2450 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2451 if_shared_ctx_t sctx = ctx->ifc_sctx;
2452 iflib_dma_info_t di;
2456 /* Tell the stack that the interface is no longer active */
2457 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2459 IFDI_INTR_DISABLE(ctx);
2464 iflib_debug_reset();
2465 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2466 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2467 /* make sure all transmitters have completed before proceeding XXX */
2470 callout_stop(&txq->ift_timer);
2471 CALLOUT_UNLOCK(txq);
2473 /* clean any enqueued buffers */
2474 iflib_ifmp_purge(txq);
2475 /* Free any existing tx buffers. */
2476 for (j = 0; j < txq->ift_size; j++) {
2477 iflib_txsd_free(ctx, txq, j);
2479 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2480 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2481 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2482 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2483 txq->ift_pullups = 0;
2484 ifmp_ring_reset_stats(txq->ift_br);
2485 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2486 bzero((void *)di->idi_vaddr, di->idi_size);
2488 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2489 /* make sure all transmitters have completed before proceeding XXX */
2491 rxq->ifr_cq_cidx = 0;
2492 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2493 bzero((void *)di->idi_vaddr, di->idi_size);
2494 /* also resets the free lists pidx/cidx */
2495 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2496 iflib_fl_bufs_free(fl);
2500 static inline caddr_t
2501 calc_next_rxd(iflib_fl_t fl, int cidx)
2505 caddr_t start, end, cur, next;
2507 nrxd = fl->ifl_size;
2508 size = fl->ifl_rxd_size;
2509 start = fl->ifl_ifdi->idi_vaddr;
2511 if (__predict_false(size == 0))
2513 cur = start + size*cidx;
2514 end = start + size*nrxd;
2515 next = CACHE_PTR_NEXT(cur);
2516 return (next < end ? next : start);
2520 prefetch_pkts(iflib_fl_t fl, int cidx)
2523 int nrxd = fl->ifl_size;
2527 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2528 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2529 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2530 next_rxd = calc_next_rxd(fl, cidx);
2532 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2533 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2534 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2535 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2536 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2537 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2538 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2539 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2543 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2551 flid = irf->irf_flid;
2552 cidx = irf->irf_idx;
2553 fl = &rxq->ifr_fl[flid];
2555 sd->ifsd_cidx = cidx;
2556 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2557 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2560 fl->ifl_m_dequeued++;
2562 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2563 prefetch_pkts(fl, cidx);
2564 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2565 prefetch(&fl->ifl_sds.ifsd_map[next]);
2566 map = fl->ifl_sds.ifsd_map[cidx];
2567 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2569 /* not valid assert if bxe really does SGE from non-contiguous elements */
2570 MPASS(fl->ifl_cidx == cidx);
2571 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2573 bus_dmamap_unload(fl->ifl_buf_tag, map);
2574 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2575 if (__predict_false(fl->ifl_cidx == 0))
2577 bit_clear(fl->ifl_rx_bitmap, cidx);
2580 static struct mbuf *
2581 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2583 int i, padlen , flags;
2584 struct mbuf *m, *mh, *mt;
2590 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2592 MPASS(*sd->ifsd_cl != NULL);
2593 MPASS(*sd->ifsd_m != NULL);
2595 /* Don't include zero-length frags */
2596 if (ri->iri_frags[i].irf_len == 0) {
2597 /* XXX we can save the cluster here, but not the mbuf */
2598 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2599 m_free(*sd->ifsd_m);
2606 flags = M_PKTHDR|M_EXT;
2608 padlen = ri->iri_pad;
2613 /* assuming padding is only on the first fragment */
2617 *sd->ifsd_cl = NULL;
2619 /* Can these two be made one ? */
2620 m_init(m, M_NOWAIT, MT_DATA, flags);
2621 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2623 * These must follow m_init and m_cljset
2625 m->m_data += padlen;
2626 ri->iri_len -= padlen;
2627 m->m_len = ri->iri_frags[i].irf_len;
2628 } while (++i < ri->iri_nfrags);
2634 * Process one software descriptor
2636 static struct mbuf *
2637 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2642 /* should I merge this back in now that the two paths are basically duplicated? */
2643 if (ri->iri_nfrags == 1 &&
2644 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2645 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2648 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2649 #ifndef __NO_STRICT_ALIGNMENT
2653 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2654 m->m_len = ri->iri_frags[0].irf_len;
2656 m = assemble_segments(rxq, ri, &sd);
2658 m->m_pkthdr.len = ri->iri_len;
2659 m->m_pkthdr.rcvif = ri->iri_ifp;
2660 m->m_flags |= ri->iri_flags;
2661 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2662 m->m_pkthdr.flowid = ri->iri_flowid;
2663 M_HASHTYPE_SET(m, ri->iri_rsstype);
2664 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2665 m->m_pkthdr.csum_data = ri->iri_csum_data;
2669 #if defined(INET6) || defined(INET)
2671 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2673 CURVNET_SET(lc->ifp->if_vnet);
2675 *v6 = VNET(ip6_forwarding);
2678 *v4 = VNET(ipforwarding);
2684 * Returns true if it's possible this packet could be LROed.
2685 * if it returns false, it is guaranteed that tcp_lro_rx()
2686 * would not return zero.
2689 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2691 struct ether_header *eh;
2694 eh = mtod(m, struct ether_header *);
2695 eh_type = ntohs(eh->ether_type);
2698 case ETHERTYPE_IPV6:
2699 return !v6_forwarding;
2703 return !v4_forwarding;
2711 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2717 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2720 if_ctx_t ctx = rxq->ifr_ctx;
2721 if_shared_ctx_t sctx = ctx->ifc_sctx;
2722 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2725 struct if_rxd_info ri;
2726 int err, budget_left, rx_bytes, rx_pkts;
2729 bool v4_forwarding, v6_forwarding, lro_possible;
2732 * XXX early demux data packets so that if_input processing only handles
2733 * acks in interrupt context
2735 struct mbuf *m, *mh, *mt, *mf;
2737 lro_possible = v4_forwarding = v6_forwarding = false;
2741 rx_pkts = rx_bytes = 0;
2742 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2743 cidxp = &rxq->ifr_cq_cidx;
2745 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2746 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2747 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2748 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2749 DBG_COUNTER_INC(rx_unavail);
2753 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2754 if (__predict_false(!CTX_ACTIVE(ctx))) {
2755 DBG_COUNTER_INC(rx_ctx_inactive);
2759 * Reset client set fields to their default values
2762 ri.iri_qsidx = rxq->ifr_id;
2763 ri.iri_cidx = *cidxp;
2765 ri.iri_frags = rxq->ifr_frags;
2766 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2770 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2771 *cidxp = ri.iri_cidx;
2772 /* Update our consumer index */
2773 /* XXX NB: shurd - check if this is still safe */
2774 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2775 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2776 /* was this only a completion queue message? */
2777 if (__predict_false(ri.iri_nfrags == 0))
2780 MPASS(ri.iri_nfrags != 0);
2781 MPASS(ri.iri_len != 0);
2783 /* will advance the cidx on the corresponding free lists */
2784 m = iflib_rxd_pkt_get(rxq, &ri);
2787 if (avail == 0 && budget_left)
2788 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2790 if (__predict_false(m == NULL)) {
2791 DBG_COUNTER_INC(rx_mbuf_null);
2794 /* imm_pkt: -- cxgb */
2802 /* make sure that we can refill faster than drain */
2803 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2804 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2806 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2808 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2810 while (mh != NULL) {
2813 m->m_nextpkt = NULL;
2814 #ifndef __NO_STRICT_ALIGNMENT
2815 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2818 rx_bytes += m->m_pkthdr.len;
2820 #if defined(INET6) || defined(INET)
2822 if (!lro_possible) {
2823 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2824 if (lro_possible && mf != NULL) {
2825 ifp->if_input(ifp, mf);
2826 DBG_COUNTER_INC(rx_if_input);
2830 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2831 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2832 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2838 ifp->if_input(ifp, m);
2839 DBG_COUNTER_INC(rx_if_input);
2850 ifp->if_input(ifp, mf);
2851 DBG_COUNTER_INC(rx_if_input);
2854 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2855 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2858 * Flush any outstanding LRO work
2860 #if defined(INET6) || defined(INET)
2861 tcp_lro_flush_all(&rxq->ifr_lc);
2865 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2868 ctx->ifc_flags |= IFC_DO_RESET;
2869 iflib_admin_intr_deferred(ctx);
2874 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2875 static inline qidx_t
2876 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2878 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2879 qidx_t minthresh = txq->ift_size / 8;
2880 if (in_use > 4*minthresh)
2881 return (notify_count);
2882 if (in_use > 2*minthresh)
2883 return (notify_count >> 1);
2884 if (in_use > minthresh)
2885 return (notify_count >> 3);
2889 static inline qidx_t
2890 txq_max_rs_deferred(iflib_txq_t txq)
2892 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2893 qidx_t minthresh = txq->ift_size / 8;
2894 if (txq->ift_in_use > 4*minthresh)
2895 return (notify_count);
2896 if (txq->ift_in_use > 2*minthresh)
2897 return (notify_count >> 1);
2898 if (txq->ift_in_use > minthresh)
2899 return (notify_count >> 2);
2903 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2904 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2906 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2907 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2908 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2910 /* forward compatibility for cxgb */
2911 #define FIRST_QSET(ctx) 0
2912 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2913 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2914 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2915 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2917 /* XXX we should be setting this to something other than zero */
2918 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2919 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2920 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2923 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2929 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2930 if (ring || txq->ift_db_pending >= max) {
2931 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2932 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2933 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2934 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2935 txq->ift_db_pending = txq->ift_npending = 0;
2943 print_pkt(if_pkt_info_t pi)
2945 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2946 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2947 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2948 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2949 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2950 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2954 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2955 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2956 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2957 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2960 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2962 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2963 struct ether_vlan_header *eh;
2967 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2968 M_WRITABLE(m) == 0) {
2969 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2973 DBG_COUNTER_INC(tx_frees);
2979 * Determine where frame payload starts.
2980 * Jump over vlan headers if already present,
2981 * helpful for QinQ too.
2983 if (__predict_false(m->m_len < sizeof(*eh))) {
2985 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2988 eh = mtod(m, struct ether_vlan_header *);
2989 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2990 pi->ipi_etype = ntohs(eh->evl_proto);
2991 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2993 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2994 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2997 switch (pi->ipi_etype) {
3002 struct ip *ip = NULL;
3003 struct tcphdr *th = NULL;
3006 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3007 if (__predict_false(m->m_len < minthlen)) {
3009 * if this code bloat is causing too much of a hit
3010 * move it to a separate function and mark it noinline
3012 if (m->m_len == pi->ipi_ehdrlen) {
3015 if (n->m_len >= sizeof(*ip)) {
3016 ip = (struct ip *)n->m_data;
3017 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3018 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3021 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3023 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3027 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3029 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3030 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3031 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3034 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3035 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3036 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3038 pi->ipi_ip_hlen = ip->ip_hl << 2;
3039 pi->ipi_ipproto = ip->ip_p;
3040 pi->ipi_flags |= IPI_TX_IPV4;
3042 /* TCP checksum offload may require TCP header length */
3043 if (IS_TX_OFFLOAD4(pi)) {
3044 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3045 if (__predict_false(th == NULL)) {
3047 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3049 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3051 pi->ipi_tcp_hflags = th->th_flags;
3052 pi->ipi_tcp_hlen = th->th_off << 2;
3053 pi->ipi_tcp_seq = th->th_seq;
3056 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3059 * TSO always requires hardware checksum offload.
3061 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3062 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3063 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3064 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3065 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3067 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3071 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3078 case ETHERTYPE_IPV6:
3080 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3082 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3084 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3086 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3089 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3091 /* XXX-BZ this will go badly in case of ext hdrs. */
3092 pi->ipi_ipproto = ip6->ip6_nxt;
3093 pi->ipi_flags |= IPI_TX_IPV6;
3095 /* TCP checksum offload may require TCP header length */
3096 if (IS_TX_OFFLOAD6(pi)) {
3097 if (pi->ipi_ipproto == IPPROTO_TCP) {
3098 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3100 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3103 pi->ipi_tcp_hflags = th->th_flags;
3104 pi->ipi_tcp_hlen = th->th_off << 2;
3105 pi->ipi_tcp_seq = th->th_seq;
3108 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3111 * TSO always requires hardware checksum offload.
3113 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3114 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3115 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3122 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3123 pi->ipi_ip_hlen = 0;
3132 * If dodgy hardware rejects the scatter gather chain we've handed it
3133 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3136 static __noinline struct mbuf *
3137 iflib_remove_mbuf(iflib_txq_t txq)
3140 struct mbuf *m, **ifsd_m;
3142 ifsd_m = txq->ift_sds.ifsd_m;
3143 ntxd = txq->ift_size;
3144 pidx = txq->ift_pidx & (ntxd - 1);
3145 ifsd_m = txq->ift_sds.ifsd_m;
3147 ifsd_m[pidx] = NULL;
3148 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3149 if (txq->ift_sds.ifsd_tso_map != NULL)
3150 bus_dmamap_unload(txq->ift_tso_buf_tag,
3151 txq->ift_sds.ifsd_tso_map[pidx]);
3153 txq->ift_dequeued++;
3158 static inline caddr_t
3159 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3163 caddr_t start, end, cur, next;
3165 ntxd = txq->ift_size;
3166 size = txq->ift_txd_size[qid];
3167 start = txq->ift_ifdi[qid].idi_vaddr;
3169 if (__predict_false(size == 0))
3171 cur = start + size*cidx;
3172 end = start + size*ntxd;
3173 next = CACHE_PTR_NEXT(cur);
3174 return (next < end ? next : start);
3178 * Pad an mbuf to ensure a minimum ethernet frame size.
3179 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3181 static __noinline int
3182 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3185 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3186 * and ARP message is the smallest common payload I can think of
3188 static char pad[18]; /* just zeros */
3190 struct mbuf *new_head;
3192 if (!M_WRITABLE(*m_head)) {
3193 new_head = m_dup(*m_head, M_NOWAIT);
3194 if (new_head == NULL) {
3196 device_printf(dev, "cannot pad short frame, m_dup() failed");
3197 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3198 DBG_COUNTER_INC(tx_frees);
3205 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3206 n > 0; n -= sizeof(pad))
3207 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3212 device_printf(dev, "cannot pad short frame\n");
3213 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3214 DBG_COUNTER_INC(tx_frees);
3222 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3225 if_shared_ctx_t sctx;
3226 if_softc_ctx_t scctx;
3227 bus_dma_tag_t buf_tag;
3228 bus_dma_segment_t *segs;
3229 struct mbuf *m_head, **ifsd_m;
3232 struct if_pkt_info pi;
3234 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3237 sctx = ctx->ifc_sctx;
3238 scctx = &ctx->ifc_softc_ctx;
3239 segs = txq->ift_segs;
3240 ntxd = txq->ift_size;
3245 * If we're doing TSO the next descriptor to clean may be quite far ahead
3247 cidx = txq->ift_cidx;
3248 pidx = txq->ift_pidx;
3249 if (ctx->ifc_flags & IFC_PREFETCH) {
3250 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3251 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3252 next_txd = calc_next_txd(txq, cidx, 0);
3256 /* prefetch the next cache line of mbuf pointers and flags */
3257 prefetch(&txq->ift_sds.ifsd_m[next]);
3258 prefetch(&txq->ift_sds.ifsd_map[next]);
3259 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3261 map = txq->ift_sds.ifsd_map[pidx];
3262 ifsd_m = txq->ift_sds.ifsd_m;
3264 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3265 buf_tag = txq->ift_tso_buf_tag;
3266 max_segs = scctx->isc_tx_tso_segments_max;
3267 map = txq->ift_sds.ifsd_tso_map[pidx];
3268 MPASS(buf_tag != NULL);
3269 MPASS(max_segs > 0);
3271 buf_tag = txq->ift_buf_tag;
3272 max_segs = scctx->isc_tx_nsegments;
3273 map = txq->ift_sds.ifsd_map[pidx];
3275 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3276 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3277 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3279 DBG_COUNTER_INC(encap_txd_encap_fail);
3286 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3288 pi.ipi_qsidx = txq->ift_id;
3289 pi.ipi_len = m_head->m_pkthdr.len;
3290 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3291 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3293 /* deliberate bitwise OR to make one condition */
3294 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3295 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3296 DBG_COUNTER_INC(encap_txd_encap_fail);
3303 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3306 if (__predict_false(err)) {
3309 /* try collapse once and defrag once */
3311 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3312 /* try defrag if collapsing fails */
3317 txq->ift_mbuf_defrag++;
3318 m_head = m_defrag(*m_headp, M_NOWAIT);
3321 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3322 * failed to map an mbuf that was run through m_defrag
3325 if (__predict_false(m_head == NULL || remap > 1))
3332 txq->ift_no_tx_dma_setup++;
3335 txq->ift_no_tx_dma_setup++;
3337 DBG_COUNTER_INC(tx_frees);
3341 txq->ift_map_failed++;
3342 DBG_COUNTER_INC(encap_load_mbuf_fail);
3343 DBG_COUNTER_INC(encap_txd_encap_fail);
3346 ifsd_m[pidx] = m_head;
3348 * XXX assumes a 1 to 1 relationship between segments and
3349 * descriptors - this does not hold true on all drivers, e.g.
3352 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3353 txq->ift_no_desc_avail++;
3354 bus_dmamap_unload(buf_tag, map);
3355 DBG_COUNTER_INC(encap_txq_avail_fail);
3356 DBG_COUNTER_INC(encap_txd_encap_fail);
3357 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3358 GROUPTASK_ENQUEUE(&txq->ift_task);
3362 * On Intel cards we can greatly reduce the number of TX interrupts
3363 * we see by only setting report status on every Nth descriptor.
3364 * However, this also means that the driver will need to keep track
3365 * of the descriptors that RS was set on to check them for the DD bit.
3367 txq->ift_rs_pending += nsegs + 1;
3368 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3369 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3370 pi.ipi_flags |= IPI_TX_INTR;
3371 txq->ift_rs_pending = 0;
3375 pi.ipi_nsegs = nsegs;
3377 MPASS(pidx >= 0 && pidx < txq->ift_size);
3381 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3382 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3383 DBG_COUNTER_INC(tx_encap);
3384 MPASS(pi.ipi_new_pidx < txq->ift_size);
3386 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3387 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3388 ndesc += txq->ift_size;
3392 * drivers can need as many as
3395 MPASS(ndesc <= pi.ipi_nsegs + 2);
3396 MPASS(pi.ipi_new_pidx != pidx);
3398 txq->ift_in_use += ndesc;
3401 * We update the last software descriptor again here because there may
3402 * be a sentinel and/or there may be more mbufs than segments
3404 txq->ift_pidx = pi.ipi_new_pidx;
3405 txq->ift_npending += pi.ipi_ndescs;
3407 *m_headp = m_head = iflib_remove_mbuf(txq);
3409 txq->ift_txd_encap_efbig++;
3418 * err can't possibly be non-zero here, so we don't neet to test it
3419 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3424 txq->ift_mbuf_defrag_failed++;
3425 txq->ift_map_failed++;
3427 DBG_COUNTER_INC(tx_frees);
3429 DBG_COUNTER_INC(encap_txd_encap_fail);
3434 iflib_tx_desc_free(iflib_txq_t txq, int n)
3436 uint32_t qsize, cidx, mask, gen;
3437 struct mbuf *m, **ifsd_m;
3440 cidx = txq->ift_cidx;
3442 qsize = txq->ift_size;
3444 ifsd_m = txq->ift_sds.ifsd_m;
3445 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3449 prefetch(ifsd_m[(cidx + 3) & mask]);
3450 prefetch(ifsd_m[(cidx + 4) & mask]);
3452 if ((m = ifsd_m[cidx]) != NULL) {
3453 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3454 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3455 bus_dmamap_sync(txq->ift_tso_buf_tag,
3456 txq->ift_sds.ifsd_tso_map[cidx],
3457 BUS_DMASYNC_POSTWRITE);
3458 bus_dmamap_unload(txq->ift_tso_buf_tag,
3459 txq->ift_sds.ifsd_tso_map[cidx]);
3461 bus_dmamap_sync(txq->ift_buf_tag,
3462 txq->ift_sds.ifsd_map[cidx],
3463 BUS_DMASYNC_POSTWRITE);
3464 bus_dmamap_unload(txq->ift_buf_tag,
3465 txq->ift_sds.ifsd_map[cidx]);
3467 /* XXX we don't support any drivers that batch packets yet */
3468 MPASS(m->m_nextpkt == NULL);
3470 ifsd_m[cidx] = NULL;
3472 txq->ift_dequeued++;
3474 DBG_COUNTER_INC(tx_frees);
3476 if (__predict_false(++cidx == qsize)) {
3481 txq->ift_cidx = cidx;
3486 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3489 if_ctx_t ctx = txq->ift_ctx;
3491 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3492 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3495 * Need a rate-limiting check so that this isn't called every time
3497 iflib_tx_credits_update(ctx, txq);
3498 reclaim = DESC_RECLAIMABLE(txq);
3500 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3502 if (iflib_verbose_debug) {
3503 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3504 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3511 iflib_tx_desc_free(txq, reclaim);
3512 txq->ift_cleaned += reclaim;
3513 txq->ift_in_use -= reclaim;
3518 static struct mbuf **
3519 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3522 struct mbuf **items;
3525 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3526 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3528 prefetch(items[(cidx + offset) & (size-1)]);
3529 if (remaining > 1) {
3530 prefetch2cachelines(&items[next]);
3531 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3532 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3533 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3535 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3539 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3542 ifmp_ring_check_drainage(txq->ift_br, budget);
3546 iflib_txq_can_drain(struct ifmp_ring *r)
3548 iflib_txq_t txq = r->cookie;
3549 if_ctx_t ctx = txq->ift_ctx;
3551 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3553 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3554 BUS_DMASYNC_POSTREAD);
3555 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3560 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3562 iflib_txq_t txq = r->cookie;
3563 if_ctx_t ctx = txq->ift_ctx;
3564 if_t ifp = ctx->ifc_ifp;
3565 struct mbuf **mp, *m;
3566 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3567 int reclaimed, err, in_use_prev, desc_used;
3568 bool do_prefetch, ring, rang;
3570 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3571 !LINK_ACTIVE(ctx))) {
3572 DBG_COUNTER_INC(txq_drain_notready);
3575 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3576 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3577 avail = IDXDIFF(pidx, cidx, r->size);
3578 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3579 DBG_COUNTER_INC(txq_drain_flushing);
3580 for (i = 0; i < avail; i++) {
3581 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3582 m_free(r->items[(cidx + i) & (r->size-1)]);
3583 r->items[(cidx + i) & (r->size-1)] = NULL;
3588 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3589 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3591 callout_stop(&txq->ift_timer);
3592 CALLOUT_UNLOCK(txq);
3593 DBG_COUNTER_INC(txq_drain_oactive);
3597 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3598 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3599 count = MIN(avail, TX_BATCH_SIZE);
3601 if (iflib_verbose_debug)
3602 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3603 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3605 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3606 avail = TXQ_AVAIL(txq);
3608 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3609 int rem = do_prefetch ? count - i : 0;
3611 mp = _ring_peek_one(r, cidx, i, rem);
3612 MPASS(mp != NULL && *mp != NULL);
3613 if (__predict_false(*mp == (struct mbuf *)txq)) {
3618 in_use_prev = txq->ift_in_use;
3619 err = iflib_encap(txq, mp);
3620 if (__predict_false(err)) {
3621 /* no room - bail out */
3625 /* we can't send this packet - skip it */
3631 DBG_COUNTER_INC(tx_sent);
3632 bytes_sent += m->m_pkthdr.len;
3633 mcast_sent += !!(m->m_flags & M_MCAST);
3634 avail = TXQ_AVAIL(txq);
3636 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3637 desc_used += (txq->ift_in_use - in_use_prev);
3638 ETHER_BPF_MTAP(ifp, m);
3639 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3641 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3644 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3645 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3646 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3647 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3648 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3650 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3652 if (iflib_verbose_debug)
3653 printf("consumed=%d\n", consumed);
3659 iflib_txq_drain_always(struct ifmp_ring *r)
3665 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3673 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3675 callout_stop(&txq->ift_timer);
3676 CALLOUT_UNLOCK(txq);
3678 avail = IDXDIFF(pidx, cidx, r->size);
3679 for (i = 0; i < avail; i++) {
3680 mp = _ring_peek_one(r, cidx, i, avail - i);
3681 if (__predict_false(*mp == (struct mbuf *)txq))
3684 DBG_COUNTER_INC(tx_frees);
3686 MPASS(ifmp_ring_is_stalled(r) == 0);
3691 iflib_ifmp_purge(iflib_txq_t txq)
3693 struct ifmp_ring *r;
3696 r->drain = iflib_txq_drain_free;
3697 r->can_drain = iflib_txq_drain_always;
3699 ifmp_ring_check_drainage(r, r->size);
3701 r->drain = iflib_txq_drain;
3702 r->can_drain = iflib_txq_can_drain;
3706 _task_fn_tx(void *context)
3708 iflib_txq_t txq = context;
3709 if_ctx_t ctx = txq->ift_ctx;
3710 #if defined(ALTQ) || defined(DEV_NETMAP)
3711 if_t ifp = ctx->ifc_ifp;
3713 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3715 #ifdef IFLIB_DIAGNOSTICS
3716 txq->ift_cpu_exec_count[curcpu]++;
3718 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3721 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3722 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3723 BUS_DMASYNC_POSTREAD);
3724 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3725 netmap_tx_irq(ifp, txq->ift_id);
3726 if (ctx->ifc_flags & IFC_LEGACY)
3727 IFDI_INTR_ENABLE(ctx);
3729 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3734 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3735 iflib_altq_if_start(ifp);
3737 if (txq->ift_db_pending)
3738 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3740 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3742 * When abdicating, we always need to check drainage, not just when we don't enqueue
3745 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3746 if (ctx->ifc_flags & IFC_LEGACY)
3747 IFDI_INTR_ENABLE(ctx);
3749 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3753 _task_fn_rx(void *context)
3755 iflib_rxq_t rxq = context;
3756 if_ctx_t ctx = rxq->ifr_ctx;
3760 #ifdef IFLIB_DIAGNOSTICS
3761 rxq->ifr_cpu_exec_count[curcpu]++;
3763 DBG_COUNTER_INC(task_fn_rxs);
3764 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3768 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3770 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3775 budget = ctx->ifc_sysctl_rx_budget;
3777 budget = 16; /* XXX */
3778 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3779 if (ctx->ifc_flags & IFC_LEGACY)
3780 IFDI_INTR_ENABLE(ctx);
3782 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3783 DBG_COUNTER_INC(rx_intr_enables);
3785 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3788 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3792 _task_fn_admin(void *context)
3794 if_ctx_t ctx = context;
3795 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3798 bool oactive, running, do_reset, do_watchdog, in_detach;
3799 uint32_t reset_on = hz / 2;
3802 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3803 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3804 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3805 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3806 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3807 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3810 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3816 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3818 callout_stop(&txq->ift_timer);
3819 CALLOUT_UNLOCK(txq);
3822 ctx->ifc_watchdog_events++;
3823 IFDI_WATCHDOG_RESET(ctx);
3825 IFDI_UPDATE_ADMIN_STATUS(ctx);
3826 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3829 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3830 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3832 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3834 IFDI_LINK_INTR_ENABLE(ctx);
3836 iflib_if_init_locked(ctx);
3839 if (LINK_ACTIVE(ctx) == 0)
3841 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3842 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3847 _task_fn_iov(void *context)
3849 if_ctx_t ctx = context;
3851 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3852 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3856 IFDI_VFLR_HANDLE(ctx);
3861 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3864 if_int_delay_info_t info;
3867 info = (if_int_delay_info_t)arg1;
3868 ctx = info->iidi_ctx;
3869 info->iidi_req = req;
3870 info->iidi_oidp = oidp;
3872 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3877 /*********************************************************************
3881 **********************************************************************/
3884 iflib_if_init_locked(if_ctx_t ctx)
3887 iflib_init_locked(ctx);
3892 iflib_if_init(void *arg)
3897 iflib_if_init_locked(ctx);
3902 iflib_if_transmit(if_t ifp, struct mbuf *m)
3904 if_ctx_t ctx = if_getsoftc(ifp);
3908 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3910 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3911 DBG_COUNTER_INC(tx_frees);
3916 MPASS(m->m_nextpkt == NULL);
3917 /* ALTQ-enabled interfaces always use queue 0. */
3919 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3920 qidx = QIDX(ctx, m);
3922 * XXX calculate buf_ring based on flowid (divvy up bits?)
3924 txq = &ctx->ifc_txqs[qidx];
3926 #ifdef DRIVER_BACKPRESSURE
3927 if (txq->ift_closed) {
3929 next = m->m_nextpkt;
3930 m->m_nextpkt = NULL;
3932 DBG_COUNTER_INC(tx_frees);
3944 next = next->m_nextpkt;
3945 } while (next != NULL);
3947 if (count > nitems(marr))
3948 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3949 /* XXX check nextpkt */
3951 /* XXX simplify for now */
3952 DBG_COUNTER_INC(tx_frees);
3955 for (next = m, i = 0; next != NULL; i++) {
3957 next = next->m_nextpkt;
3958 mp[i]->m_nextpkt = NULL;
3961 DBG_COUNTER_INC(tx_seen);
3962 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3965 GROUPTASK_ENQUEUE(&txq->ift_task);
3968 GROUPTASK_ENQUEUE(&txq->ift_task);
3969 /* support forthcoming later */
3970 #ifdef DRIVER_BACKPRESSURE
3971 txq->ift_closed = TRUE;
3973 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3975 DBG_COUNTER_INC(tx_frees);
3983 * The overall approach to integrating iflib with ALTQ is to continue to use
3984 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3985 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
3986 * is redundant/unnecessary, but doing so minimizes the amount of
3987 * ALTQ-specific code required in iflib. It is assumed that the overhead of
3988 * redundantly queueing to an intermediate mp_ring is swamped by the
3989 * performance limitations inherent in using ALTQ.
3991 * When ALTQ support is compiled in, all iflib drivers will use a transmit
3992 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
3993 * given interface. If ALTQ is enabled for an interface, then all
3994 * transmitted packets for that interface will be submitted to the ALTQ
3995 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
3996 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
3997 * update stats that the iflib machinery handles, and which is sensitve to
3998 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
3999 * will be installed as the start routine for use by ALTQ facilities that
4000 * need to trigger queue drains on a scheduled basis.
4004 iflib_altq_if_start(if_t ifp)
4006 struct ifaltq *ifq = &ifp->if_snd;
4010 IFQ_DEQUEUE_NOLOCK(ifq, m);
4012 iflib_if_transmit(ifp, m);
4013 IFQ_DEQUEUE_NOLOCK(ifq, m);
4019 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4023 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4024 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4026 iflib_altq_if_start(ifp);
4028 err = iflib_if_transmit(ifp, m);
4035 iflib_if_qflush(if_t ifp)
4037 if_ctx_t ctx = if_getsoftc(ifp);
4038 iflib_txq_t txq = ctx->ifc_txqs;
4042 ctx->ifc_flags |= IFC_QFLUSH;
4044 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4045 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4046 iflib_txq_check_drain(txq, 0);
4048 ctx->ifc_flags &= ~IFC_QFLUSH;
4052 * When ALTQ is enabled, this will also take care of purging the
4059 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4060 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4061 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4062 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4065 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4067 if_ctx_t ctx = if_getsoftc(ifp);
4068 struct ifreq *ifr = (struct ifreq *)data;
4069 #if defined(INET) || defined(INET6)
4070 struct ifaddr *ifa = (struct ifaddr *)data;
4072 bool avoid_reset = false;
4073 int err = 0, reinit = 0, bits;
4078 if (ifa->ifa_addr->sa_family == AF_INET)
4082 if (ifa->ifa_addr->sa_family == AF_INET6)
4086 ** Calling init results in link renegotiation,
4087 ** so we avoid doing it when possible.
4090 if_setflagbits(ifp, IFF_UP,0);
4091 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4094 if (!(if_getflags(ifp) & IFF_NOARP))
4095 arp_ifinit(ifp, ifa);
4098 err = ether_ioctl(ifp, command, data);
4102 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4106 bits = if_getdrvflags(ifp);
4107 /* stop the driver and free any clusters before proceeding */
4110 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4112 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4113 ctx->ifc_flags |= IFC_MULTISEG;
4115 ctx->ifc_flags &= ~IFC_MULTISEG;
4117 err = if_setmtu(ifp, ifr->ifr_mtu);
4119 iflib_init_locked(ctx);
4121 if_setdrvflags(ifp, bits);
4127 if (if_getflags(ifp) & IFF_UP) {
4128 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4129 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4130 (IFF_PROMISC | IFF_ALLMULTI)) {
4131 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4135 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4138 ctx->ifc_if_flags = if_getflags(ifp);
4143 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4145 IFDI_INTR_DISABLE(ctx);
4146 IFDI_MULTI_SET(ctx);
4147 IFDI_INTR_ENABLE(ctx);
4153 IFDI_MEDIA_SET(ctx);
4158 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4162 struct ifi2creq i2c;
4164 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4167 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4171 if (i2c.len > sizeof(i2c.data)) {
4176 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4177 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4183 int mask, setmask, oldmask;
4185 oldmask = if_getcapenable(ifp);
4186 mask = ifr->ifr_reqcap ^ oldmask;
4187 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4190 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4192 setmask |= (mask & IFCAP_FLAGS);
4193 setmask |= (mask & IFCAP_WOL);
4196 * If any RX csum has changed, change all the ones that
4197 * are supported by the driver.
4199 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4200 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4201 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4205 * want to ensure that traffic has stopped before we change any of the flags
4209 bits = if_getdrvflags(ifp);
4210 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4213 if_togglecapenable(ifp, setmask);
4215 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4216 iflib_init_locked(ctx);
4218 if_setdrvflags(ifp, bits);
4225 case SIOCGPRIVATE_0:
4229 err = IFDI_PRIV_IOCTL(ctx, command, data);
4233 err = ether_ioctl(ifp, command, data);
4242 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4244 if_ctx_t ctx = if_getsoftc(ifp);
4246 return (IFDI_GET_COUNTER(ctx, cnt));
4249 /*********************************************************************
4251 * OTHER FUNCTIONS EXPORTED TO THE STACK
4253 **********************************************************************/
4256 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4258 if_ctx_t ctx = if_getsoftc(ifp);
4260 if ((void *)ctx != arg)
4263 if ((vtag == 0) || (vtag > 4095))
4266 if (iflib_in_detach(ctx))
4270 IFDI_VLAN_REGISTER(ctx, vtag);
4271 /* Re-init to load the changes */
4272 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4273 iflib_if_init_locked(ctx);
4278 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4280 if_ctx_t ctx = if_getsoftc(ifp);
4282 if ((void *)ctx != arg)
4285 if ((vtag == 0) || (vtag > 4095))
4289 IFDI_VLAN_UNREGISTER(ctx, vtag);
4290 /* Re-init to load the changes */
4291 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4292 iflib_if_init_locked(ctx);
4297 iflib_led_func(void *arg, int onoff)
4302 IFDI_LED_FUNC(ctx, onoff);
4306 /*********************************************************************
4308 * BUS FUNCTION DEFINITIONS
4310 **********************************************************************/
4313 iflib_device_probe(device_t dev)
4315 pci_vendor_info_t *ent;
4317 uint16_t pci_vendor_id, pci_device_id;
4318 uint16_t pci_subvendor_id, pci_subdevice_id;
4319 uint16_t pci_rev_id;
4320 if_shared_ctx_t sctx;
4322 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4325 pci_vendor_id = pci_get_vendor(dev);
4326 pci_device_id = pci_get_device(dev);
4327 pci_subvendor_id = pci_get_subvendor(dev);
4328 pci_subdevice_id = pci_get_subdevice(dev);
4329 pci_rev_id = pci_get_revid(dev);
4330 if (sctx->isc_parse_devinfo != NULL)
4331 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4333 ent = sctx->isc_vendor_info;
4334 while (ent->pvi_vendor_id != 0) {
4335 if (pci_vendor_id != ent->pvi_vendor_id) {
4339 if ((pci_device_id == ent->pvi_device_id) &&
4340 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4341 (ent->pvi_subvendor_id == 0)) &&
4342 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4343 (ent->pvi_subdevice_id == 0)) &&
4344 ((pci_rev_id == ent->pvi_rev_id) ||
4345 (ent->pvi_rev_id == 0))) {
4347 device_set_desc_copy(dev, ent->pvi_name);
4348 /* this needs to be changed to zero if the bus probing code
4349 * ever stops re-probing on best match because the sctx
4350 * may have its values over written by register calls
4351 * in subsequent probes
4353 return (BUS_PROBE_DEFAULT);
4361 iflib_device_probe_vendor(device_t dev)
4365 probe = iflib_device_probe(dev);
4366 if (probe == BUS_PROBE_DEFAULT)
4367 return (BUS_PROBE_VENDOR);
4373 iflib_reset_qvalues(if_ctx_t ctx)
4375 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4376 if_shared_ctx_t sctx = ctx->ifc_sctx;
4377 device_t dev = ctx->ifc_dev;
4380 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4381 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4382 if (ctx->ifc_sysctl_ntxqs != 0)
4383 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4384 if (ctx->ifc_sysctl_nrxqs != 0)
4385 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4387 for (i = 0; i < sctx->isc_ntxqs; i++) {
4388 if (ctx->ifc_sysctl_ntxds[i] != 0)
4389 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4391 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4394 for (i = 0; i < sctx->isc_nrxqs; i++) {
4395 if (ctx->ifc_sysctl_nrxds[i] != 0)
4396 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4398 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4401 for (i = 0; i < sctx->isc_nrxqs; i++) {
4402 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4403 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4404 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4405 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4407 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4408 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4409 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4410 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4412 if (!powerof2(scctx->isc_nrxd[i])) {
4413 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4414 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4415 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4419 for (i = 0; i < sctx->isc_ntxqs; i++) {
4420 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4421 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4422 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4423 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4425 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4426 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4427 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4428 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4430 if (!powerof2(scctx->isc_ntxd[i])) {
4431 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4432 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4433 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4439 get_ctx_core_offset(if_ctx_t ctx)
4441 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4442 struct cpu_offset *op;
4444 uint16_t ret = ctx->ifc_sysctl_core_offset;
4446 if (ret != CORE_OFFSET_UNSPECIFIED)
4449 if (ctx->ifc_sysctl_separate_txrx)
4450 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4452 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4454 mtx_lock(&cpu_offset_mtx);
4455 SLIST_FOREACH(op, &cpu_offsets, entries) {
4456 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4459 MPASS(op->refcount < UINT_MAX);
4464 if (ret == CORE_OFFSET_UNSPECIFIED) {
4466 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4469 device_printf(ctx->ifc_dev,
4470 "allocation for cpu offset failed.\n");
4474 CPU_COPY(&ctx->ifc_cpus, &op->set);
4475 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4478 mtx_unlock(&cpu_offset_mtx);
4484 unref_ctx_core_offset(if_ctx_t ctx)
4486 struct cpu_offset *op, *top;
4488 mtx_lock(&cpu_offset_mtx);
4489 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4490 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4491 MPASS(op->refcount > 0);
4493 if (op->refcount == 0) {
4494 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4500 mtx_unlock(&cpu_offset_mtx);
4504 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4508 if_softc_ctx_t scctx;
4509 kobjop_desc_t kobj_desc;
4510 kobj_method_t *kobj_method;
4512 uint16_t main_rxq, main_txq;
4514 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4517 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4518 device_set_softc(dev, ctx);
4519 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4522 ctx->ifc_sctx = sctx;
4524 ctx->ifc_softc = sc;
4526 if ((err = iflib_register(ctx)) != 0) {
4527 device_printf(dev, "iflib_register failed %d\n", err);
4530 iflib_add_device_sysctl_pre(ctx);
4532 scctx = &ctx->ifc_softc_ctx;
4535 iflib_reset_qvalues(ctx);
4537 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4538 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4541 _iflib_pre_assert(scctx);
4542 ctx->ifc_txrx = *scctx->isc_txrx;
4545 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4546 MPASS(scctx->isc_tx_csum_flags);
4549 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4550 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4552 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4553 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4554 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4555 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4557 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4558 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4560 /* XXX change for per-queue sizes */
4561 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4562 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4564 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4565 MAX_SINGLE_PACKET_FRACTION)
4566 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4567 MAX_SINGLE_PACKET_FRACTION);
4568 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4569 MAX_SINGLE_PACKET_FRACTION)
4570 scctx->isc_tx_tso_segments_max = max(1,
4571 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4573 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4574 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4576 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4579 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4582 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4583 * into account. In the worst case, each of these calls will
4584 * add another mbuf and, thus, the requirement for another DMA
4585 * segment. So for best performance, it doesn't make sense to
4586 * advertize a maximum of TSO segments that typically will
4587 * require defragmentation in iflib_encap().
4589 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4590 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4592 if (scctx->isc_rss_table_size == 0)
4593 scctx->isc_rss_table_size = 64;
4594 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4596 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4597 /* XXX format name */
4598 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4601 /* Set up cpu set. If it fails, use the set of all CPUs. */
4602 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4603 device_printf(dev, "Unable to fetch CPU list\n");
4604 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4606 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4609 ** Now set up MSI or MSI-X, should return us the number of supported
4610 ** vectors (will be 1 for a legacy interrupt and MSI).
4612 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4613 msix = scctx->isc_vectors;
4614 } else if (scctx->isc_msix_bar != 0)
4616 * The simple fact that isc_msix_bar is not 0 does not mean we
4617 * we have a good value there that is known to work.
4619 msix = iflib_msix_init(ctx);
4621 scctx->isc_vectors = 1;
4622 scctx->isc_ntxqsets = 1;
4623 scctx->isc_nrxqsets = 1;
4624 scctx->isc_intr = IFLIB_INTR_LEGACY;
4627 /* Get memory for the station queues */
4628 if ((err = iflib_queues_alloc(ctx))) {
4629 device_printf(dev, "Unable to allocate queue memory\n");
4630 goto fail_intr_free;
4633 if ((err = iflib_qset_structures_setup(ctx)))
4637 * Now that we know how many queues there are, get the core offset.
4639 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4642 * Group taskqueues aren't properly set up until SMP is started,
4643 * so we disable interrupts until we can handle them post
4646 * XXX: disabling interrupts doesn't actually work, at least for
4647 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4648 * we do null handling and depend on this not causing too large an
4651 IFDI_INTR_DISABLE(ctx);
4655 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4656 * aren't the default NULL implementation.
4658 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4659 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4661 if (kobj_method == &kobj_desc->deflt) {
4663 "MSI-X requires ifdi_rx_queue_intr_enable method");
4667 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4668 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4670 if (kobj_method == &kobj_desc->deflt) {
4672 "MSI-X requires ifdi_tx_queue_intr_enable method");
4678 * Assign the MSI-X vectors.
4679 * Note that the default NULL ifdi_msix_intr_assign method will
4682 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4684 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4688 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4690 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4694 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4695 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4700 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4702 goto fail_intr_free;
4705 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4707 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4708 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4713 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4714 * This must appear after the call to ether_ifattach() because
4715 * ether_ifattach() sets if_hdrlen to the default value.
4717 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4718 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4720 if ((err = iflib_netmap_attach(ctx))) {
4721 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4726 NETDUMP_SET(ctx->ifc_ifp, iflib);
4728 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4729 iflib_add_device_sysctl_post(ctx);
4730 ctx->ifc_flags |= IFC_INIT_DONE;
4736 ether_ifdetach(ctx->ifc_ifp);
4738 iflib_free_intr_mem(ctx);
4740 iflib_tx_structures_free(ctx);
4741 iflib_rx_structures_free(ctx);
4742 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4746 iflib_deregister(ctx);
4748 device_set_softc(ctx->ifc_dev, NULL);
4749 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4750 free(ctx->ifc_softc, M_IFLIB);
4756 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4757 struct iflib_cloneattach_ctx *clctx)
4762 if_softc_ctx_t scctx;
4768 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4769 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4770 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4771 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4772 ctx->ifc_flags |= IFC_PSEUDO;
4774 ctx->ifc_sctx = sctx;
4775 ctx->ifc_softc = sc;
4778 if ((err = iflib_register(ctx)) != 0) {
4779 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4782 iflib_add_device_sysctl_pre(ctx);
4784 scctx = &ctx->ifc_softc_ctx;
4787 iflib_reset_qvalues(ctx);
4789 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4790 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4793 if (sctx->isc_flags & IFLIB_GEN_MAC)
4795 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4796 clctx->cc_params)) != 0) {
4797 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4800 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4801 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4802 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4805 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4806 MPASS(scctx->isc_tx_csum_flags);
4809 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4810 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4812 ifp->if_flags |= IFF_NOGROUP;
4813 if (sctx->isc_flags & IFLIB_PSEUDO) {
4814 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4816 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4817 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4823 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4824 * This must appear after the call to ether_ifattach() because
4825 * ether_ifattach() sets if_hdrlen to the default value.
4827 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4828 if_setifheaderlen(ifp,
4829 sizeof(struct ether_vlan_header));
4831 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4832 iflib_add_device_sysctl_post(ctx);
4833 ctx->ifc_flags |= IFC_INIT_DONE;
4836 _iflib_pre_assert(scctx);
4837 ctx->ifc_txrx = *scctx->isc_txrx;
4839 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4840 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4841 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4842 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4844 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4845 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4847 /* XXX change for per-queue sizes */
4848 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4849 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4851 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4852 MAX_SINGLE_PACKET_FRACTION)
4853 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4854 MAX_SINGLE_PACKET_FRACTION);
4855 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4856 MAX_SINGLE_PACKET_FRACTION)
4857 scctx->isc_tx_tso_segments_max = max(1,
4858 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4860 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4861 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4863 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4866 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4869 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4870 * into account. In the worst case, each of these calls will
4871 * add another mbuf and, thus, the requirement for another DMA
4872 * segment. So for best performance, it doesn't make sense to
4873 * advertize a maximum of TSO segments that typically will
4874 * require defragmentation in iflib_encap().
4876 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4877 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4879 if (scctx->isc_rss_table_size == 0)
4880 scctx->isc_rss_table_size = 64;
4881 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4883 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4884 /* XXX format name */
4885 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4888 /* XXX --- can support > 1 -- but keep it simple for now */
4889 scctx->isc_intr = IFLIB_INTR_LEGACY;
4891 /* Get memory for the station queues */
4892 if ((err = iflib_queues_alloc(ctx))) {
4893 device_printf(dev, "Unable to allocate queue memory\n");
4894 goto fail_iflib_detach;
4897 if ((err = iflib_qset_structures_setup(ctx))) {
4898 device_printf(dev, "qset structure setup failed %d\n", err);
4903 * XXX What if anything do we want to do about interrupts?
4905 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4906 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4907 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4912 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4913 * This must appear after the call to ether_ifattach() because
4914 * ether_ifattach() sets if_hdrlen to the default value.
4916 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4917 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4919 /* XXX handle more than one queue */
4920 for (i = 0; i < scctx->isc_nrxqsets; i++)
4921 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4925 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4926 iflib_add_device_sysctl_post(ctx);
4927 ctx->ifc_flags |= IFC_INIT_DONE;
4932 ether_ifdetach(ctx->ifc_ifp);
4934 iflib_tx_structures_free(ctx);
4935 iflib_rx_structures_free(ctx);
4940 iflib_deregister(ctx);
4942 free(ctx->ifc_softc, M_IFLIB);
4948 iflib_pseudo_deregister(if_ctx_t ctx)
4950 if_t ifp = ctx->ifc_ifp;
4954 struct taskqgroup *tqg;
4957 ether_ifdetach(ifp);
4958 /* XXX drain any dependent tasks */
4959 tqg = qgroup_if_io_tqg;
4960 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4961 callout_drain(&txq->ift_timer);
4962 if (txq->ift_task.gt_uniq != NULL)
4963 taskqgroup_detach(tqg, &txq->ift_task);
4965 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4966 if (rxq->ifr_task.gt_uniq != NULL)
4967 taskqgroup_detach(tqg, &rxq->ifr_task);
4969 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4970 free(fl->ifl_rx_bitmap, M_IFLIB);
4972 tqg = qgroup_if_config_tqg;
4973 if (ctx->ifc_admin_task.gt_uniq != NULL)
4974 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4975 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4976 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4978 iflib_tx_structures_free(ctx);
4979 iflib_rx_structures_free(ctx);
4981 iflib_deregister(ctx);
4983 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4984 free(ctx->ifc_softc, M_IFLIB);
4990 iflib_device_attach(device_t dev)
4993 if_shared_ctx_t sctx;
4995 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4998 pci_enable_busmaster(dev);
5000 return (iflib_device_register(dev, NULL, sctx, &ctx));
5004 iflib_device_deregister(if_ctx_t ctx)
5006 if_t ifp = ctx->ifc_ifp;
5009 device_t dev = ctx->ifc_dev;
5011 struct taskqgroup *tqg;
5014 /* Make sure VLANS are not using driver */
5015 if (if_vlantrunkinuse(ifp)) {
5016 device_printf(dev, "Vlan in use, detach first\n");
5020 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5021 device_printf(dev, "SR-IOV in use; detach first.\n");
5027 ctx->ifc_flags |= IFC_IN_DETACH;
5034 iflib_netmap_detach(ifp);
5035 ether_ifdetach(ifp);
5036 if (ctx->ifc_led_dev != NULL)
5037 led_destroy(ctx->ifc_led_dev);
5038 /* XXX drain any dependent tasks */
5039 tqg = qgroup_if_io_tqg;
5040 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5041 callout_drain(&txq->ift_timer);
5042 if (txq->ift_task.gt_uniq != NULL)
5043 taskqgroup_detach(tqg, &txq->ift_task);
5045 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5046 if (rxq->ifr_task.gt_uniq != NULL)
5047 taskqgroup_detach(tqg, &rxq->ifr_task);
5049 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5050 free(fl->ifl_rx_bitmap, M_IFLIB);
5052 tqg = qgroup_if_config_tqg;
5053 if (ctx->ifc_admin_task.gt_uniq != NULL)
5054 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5055 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5056 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5061 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5062 iflib_free_intr_mem(ctx);
5064 bus_generic_detach(dev);
5066 iflib_tx_structures_free(ctx);
5067 iflib_rx_structures_free(ctx);
5069 iflib_deregister(ctx);
5071 device_set_softc(ctx->ifc_dev, NULL);
5072 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5073 free(ctx->ifc_softc, M_IFLIB);
5074 unref_ctx_core_offset(ctx);
5080 iflib_free_intr_mem(if_ctx_t ctx)
5083 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5084 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5086 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5087 pci_release_msi(ctx->ifc_dev);
5089 if (ctx->ifc_msix_mem != NULL) {
5090 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5091 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5092 ctx->ifc_msix_mem = NULL;
5097 iflib_device_detach(device_t dev)
5099 if_ctx_t ctx = device_get_softc(dev);
5101 return (iflib_device_deregister(ctx));
5105 iflib_device_suspend(device_t dev)
5107 if_ctx_t ctx = device_get_softc(dev);
5113 return bus_generic_suspend(dev);
5116 iflib_device_shutdown(device_t dev)
5118 if_ctx_t ctx = device_get_softc(dev);
5124 return bus_generic_suspend(dev);
5129 iflib_device_resume(device_t dev)
5131 if_ctx_t ctx = device_get_softc(dev);
5132 iflib_txq_t txq = ctx->ifc_txqs;
5136 iflib_if_init_locked(ctx);
5138 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5139 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5141 return (bus_generic_resume(dev));
5145 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5148 if_ctx_t ctx = device_get_softc(dev);
5151 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5158 iflib_device_iov_uninit(device_t dev)
5160 if_ctx_t ctx = device_get_softc(dev);
5163 IFDI_IOV_UNINIT(ctx);
5168 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5171 if_ctx_t ctx = device_get_softc(dev);
5174 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5180 /*********************************************************************
5182 * MODULE FUNCTION DEFINITIONS
5184 **********************************************************************/
5187 * - Start a fast taskqueue thread for each core
5188 * - Start a taskqueue for control operations
5191 iflib_module_init(void)
5197 iflib_module_event_handler(module_t mod, int what, void *arg)
5203 if ((err = iflib_module_init()) != 0)
5209 return (EOPNOTSUPP);
5215 /*********************************************************************
5217 * PUBLIC FUNCTION DEFINITIONS
5218 * ordered as in iflib.h
5220 **********************************************************************/
5224 _iflib_assert(if_shared_ctx_t sctx)
5228 MPASS(sctx->isc_tx_maxsize);
5229 MPASS(sctx->isc_tx_maxsegsize);
5231 MPASS(sctx->isc_rx_maxsize);
5232 MPASS(sctx->isc_rx_nsegments);
5233 MPASS(sctx->isc_rx_maxsegsize);
5235 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5236 for (i = 0; i < sctx->isc_nrxqs; i++) {
5237 MPASS(sctx->isc_nrxd_min[i]);
5238 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5239 MPASS(sctx->isc_nrxd_max[i]);
5240 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5241 MPASS(sctx->isc_nrxd_default[i]);
5242 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5245 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5246 for (i = 0; i < sctx->isc_ntxqs; i++) {
5247 MPASS(sctx->isc_ntxd_min[i]);
5248 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5249 MPASS(sctx->isc_ntxd_max[i]);
5250 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5251 MPASS(sctx->isc_ntxd_default[i]);
5252 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5257 _iflib_pre_assert(if_softc_ctx_t scctx)
5260 MPASS(scctx->isc_txrx->ift_txd_encap);
5261 MPASS(scctx->isc_txrx->ift_txd_flush);
5262 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5263 MPASS(scctx->isc_txrx->ift_rxd_available);
5264 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5265 MPASS(scctx->isc_txrx->ift_rxd_refill);
5266 MPASS(scctx->isc_txrx->ift_rxd_flush);
5270 iflib_register(if_ctx_t ctx)
5272 if_shared_ctx_t sctx = ctx->ifc_sctx;
5273 driver_t *driver = sctx->isc_driver;
5274 device_t dev = ctx->ifc_dev;
5277 _iflib_assert(sctx);
5280 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5281 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5283 device_printf(dev, "can not allocate ifnet structure\n");
5288 * Initialize our context's device specific methods
5290 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5291 kobj_class_compile((kobj_class_t) driver);
5293 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5294 if_setsoftc(ifp, ctx);
5295 if_setdev(ifp, dev);
5296 if_setinitfn(ifp, iflib_if_init);
5297 if_setioctlfn(ifp, iflib_if_ioctl);
5299 if_setstartfn(ifp, iflib_altq_if_start);
5300 if_settransmitfn(ifp, iflib_altq_if_transmit);
5301 if_setsendqready(ifp);
5303 if_settransmitfn(ifp, iflib_if_transmit);
5305 if_setqflushfn(ifp, iflib_if_qflush);
5306 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5308 ctx->ifc_vlan_attach_event =
5309 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5310 EVENTHANDLER_PRI_FIRST);
5311 ctx->ifc_vlan_detach_event =
5312 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5313 EVENTHANDLER_PRI_FIRST);
5315 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5316 iflib_media_change, iflib_media_status);
5322 iflib_deregister(if_ctx_t ctx)
5324 if_t ifp = ctx->ifc_ifp;
5326 /* Remove all media */
5327 ifmedia_removeall(&ctx->ifc_media);
5329 /* Unregister VLAN events */
5330 if (ctx->ifc_vlan_attach_event != NULL) {
5331 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5332 ctx->ifc_vlan_attach_event = NULL;
5334 if (ctx->ifc_vlan_detach_event != NULL) {
5335 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5336 ctx->ifc_vlan_detach_event = NULL;
5339 /* Release kobject reference */
5340 kobj_delete((kobj_t) ctx, NULL);
5342 /* Free the ifnet structure */
5345 STATE_LOCK_DESTROY(ctx);
5347 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5348 CTX_LOCK_DESTROY(ctx);
5352 iflib_queues_alloc(if_ctx_t ctx)
5354 if_shared_ctx_t sctx = ctx->ifc_sctx;
5355 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5356 device_t dev = ctx->ifc_dev;
5357 int nrxqsets = scctx->isc_nrxqsets;
5358 int ntxqsets = scctx->isc_ntxqsets;
5361 iflib_fl_t fl = NULL;
5362 int i, j, cpu, err, txconf, rxconf;
5363 iflib_dma_info_t ifdip;
5364 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5365 uint32_t *txqsizes = scctx->isc_txqsizes;
5366 uint8_t nrxqs = sctx->isc_nrxqs;
5367 uint8_t ntxqs = sctx->isc_ntxqs;
5368 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5372 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5373 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5375 /* Allocate the TX ring struct memory */
5376 if (!(ctx->ifc_txqs =
5377 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5378 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5379 device_printf(dev, "Unable to allocate TX ring memory\n");
5384 /* Now allocate the RX */
5385 if (!(ctx->ifc_rxqs =
5386 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5387 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5388 device_printf(dev, "Unable to allocate RX ring memory\n");
5393 txq = ctx->ifc_txqs;
5394 rxq = ctx->ifc_rxqs;
5397 * XXX handle allocation failure
5399 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5400 /* Set up some basics */
5402 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5403 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5405 "Unable to allocate TX DMA info memory\n");
5409 txq->ift_ifdi = ifdip;
5410 for (j = 0; j < ntxqs; j++, ifdip++) {
5411 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5413 "Unable to allocate TX descriptors\n");
5417 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5418 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5422 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5423 txq->ift_br_offset = 1;
5425 txq->ift_br_offset = 0;
5428 txq->ift_timer.c_cpu = cpu;
5430 if (iflib_txsd_alloc(txq)) {
5431 device_printf(dev, "Critical Failure setting up TX buffers\n");
5436 /* Initialize the TX lock */
5437 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5438 device_get_nameunit(dev), txq->ift_id);
5439 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5440 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5442 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5443 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5445 /* XXX free any allocated rings */
5446 device_printf(dev, "Unable to allocate buf_ring\n");
5451 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5452 /* Set up some basics */
5454 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5455 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5457 "Unable to allocate RX DMA info memory\n");
5462 rxq->ifr_ifdi = ifdip;
5463 /* XXX this needs to be changed if #rx queues != #tx queues */
5464 rxq->ifr_ntxqirq = 1;
5465 rxq->ifr_txqid[0] = i;
5466 for (j = 0; j < nrxqs; j++, ifdip++) {
5467 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5469 "Unable to allocate RX descriptors\n");
5473 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5477 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5478 rxq->ifr_fl_offset = 1;
5480 rxq->ifr_fl_offset = 0;
5482 rxq->ifr_nfl = nfree_lists;
5484 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5485 device_printf(dev, "Unable to allocate free list memory\n");
5490 for (j = 0; j < nfree_lists; j++) {
5491 fl[j].ifl_rxq = rxq;
5493 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5494 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5496 /* Allocate receive buffers for the ring */
5497 if (iflib_rxsd_alloc(rxq)) {
5499 "Critical Failure setting up receive buffers\n");
5504 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5505 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5510 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5511 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5512 for (i = 0; i < ntxqsets; i++) {
5513 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5515 for (j = 0; j < ntxqs; j++, di++) {
5516 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5517 paddrs[i*ntxqs + j] = di->idi_paddr;
5520 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5521 device_printf(ctx->ifc_dev,
5522 "Unable to allocate device TX queue\n");
5523 iflib_tx_structures_free(ctx);
5524 free(vaddrs, M_IFLIB);
5525 free(paddrs, M_IFLIB);
5528 free(vaddrs, M_IFLIB);
5529 free(paddrs, M_IFLIB);
5532 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5533 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5534 for (i = 0; i < nrxqsets; i++) {
5535 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5537 for (j = 0; j < nrxqs; j++, di++) {
5538 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5539 paddrs[i*nrxqs + j] = di->idi_paddr;
5542 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5543 device_printf(ctx->ifc_dev,
5544 "Unable to allocate device RX queue\n");
5545 iflib_tx_structures_free(ctx);
5546 free(vaddrs, M_IFLIB);
5547 free(paddrs, M_IFLIB);
5550 free(vaddrs, M_IFLIB);
5551 free(paddrs, M_IFLIB);
5555 /* XXX handle allocation failure changes */
5559 if (ctx->ifc_rxqs != NULL)
5560 free(ctx->ifc_rxqs, M_IFLIB);
5561 ctx->ifc_rxqs = NULL;
5562 if (ctx->ifc_txqs != NULL)
5563 free(ctx->ifc_txqs, M_IFLIB);
5564 ctx->ifc_txqs = NULL;
5570 iflib_tx_structures_setup(if_ctx_t ctx)
5572 iflib_txq_t txq = ctx->ifc_txqs;
5575 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5576 iflib_txq_setup(txq);
5582 iflib_tx_structures_free(if_ctx_t ctx)
5584 iflib_txq_t txq = ctx->ifc_txqs;
5585 if_shared_ctx_t sctx = ctx->ifc_sctx;
5588 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5589 iflib_txq_destroy(txq);
5590 for (j = 0; j < sctx->isc_ntxqs; j++)
5591 iflib_dma_free(&txq->ift_ifdi[j]);
5593 free(ctx->ifc_txqs, M_IFLIB);
5594 ctx->ifc_txqs = NULL;
5595 IFDI_QUEUES_FREE(ctx);
5598 /*********************************************************************
5600 * Initialize all receive rings.
5602 **********************************************************************/
5604 iflib_rx_structures_setup(if_ctx_t ctx)
5606 iflib_rxq_t rxq = ctx->ifc_rxqs;
5608 #if defined(INET6) || defined(INET)
5612 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5613 #if defined(INET6) || defined(INET)
5614 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5615 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5616 TCP_LRO_ENTRIES, min(1024,
5617 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5619 device_printf(ctx->ifc_dev,
5620 "LRO Initialization failed!\n");
5625 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5628 #if defined(INET6) || defined(INET)
5631 * Free LRO resources allocated so far, we will only handle
5632 * the rings that completed, the failing case will have
5633 * cleaned up for itself. 'q' failed, so its the terminus.
5635 rxq = ctx->ifc_rxqs;
5636 for (i = 0; i < q; ++i, rxq++) {
5637 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5638 tcp_lro_free(&rxq->ifr_lc);
5644 /*********************************************************************
5646 * Free all receive rings.
5648 **********************************************************************/
5650 iflib_rx_structures_free(if_ctx_t ctx)
5652 iflib_rxq_t rxq = ctx->ifc_rxqs;
5655 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5656 iflib_rx_sds_free(rxq);
5657 #if defined(INET6) || defined(INET)
5658 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5659 tcp_lro_free(&rxq->ifr_lc);
5662 free(ctx->ifc_rxqs, M_IFLIB);
5663 ctx->ifc_rxqs = NULL;
5667 iflib_qset_structures_setup(if_ctx_t ctx)
5672 * It is expected that the caller takes care of freeing queues if this
5675 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5676 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5680 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5681 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5687 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5688 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5691 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5696 find_nth(if_ctx_t ctx, int qid)
5699 int i, cpuid, eqid, count;
5701 CPU_COPY(&ctx->ifc_cpus, &cpus);
5702 count = CPU_COUNT(&cpus);
5704 /* clear up to the qid'th bit */
5705 for (i = 0; i < eqid; i++) {
5706 cpuid = CPU_FFS(&cpus);
5708 CPU_CLR(cpuid-1, &cpus);
5710 cpuid = CPU_FFS(&cpus);
5716 extern struct cpu_group *cpu_top; /* CPU topology */
5719 find_child_with_core(int cpu, struct cpu_group *grp)
5723 if (grp->cg_children == 0)
5726 MPASS(grp->cg_child);
5727 for (i = 0; i < grp->cg_children; i++) {
5728 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5736 * Find the nth "close" core to the specified core
5737 * "close" is defined as the deepest level that shares
5738 * at least an L2 cache. With threads, this will be
5739 * threads on the same core. If the shared cache is L3
5740 * or higher, simply returns the same core.
5743 find_close_core(int cpu, int core_offset)
5745 struct cpu_group *grp;
5754 while ((i = find_child_with_core(cpu, grp)) != -1) {
5755 /* If the child only has one cpu, don't descend */
5756 if (grp->cg_child[i].cg_count <= 1)
5758 grp = &grp->cg_child[i];
5761 /* If they don't share at least an L2 cache, use the same CPU */
5762 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5766 CPU_COPY(&grp->cg_mask, &cs);
5768 /* Add the selected CPU offset to core offset. */
5769 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5770 if (fcpu - 1 == cpu)
5772 CPU_CLR(fcpu - 1, &cs);
5778 CPU_COPY(&grp->cg_mask, &cs);
5779 for (i = core_offset % grp->cg_count; i > 0; i--) {
5780 MPASS(CPU_FFS(&cs));
5781 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5783 MPASS(CPU_FFS(&cs));
5784 return CPU_FFS(&cs) - 1;
5788 find_close_core(int cpu, int core_offset __unused)
5795 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5799 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5800 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5801 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5803 case IFLIB_INTR_RXTX:
5804 /* RX queues get the specified core */
5805 return qid / CPU_COUNT(&ctx->ifc_cpus);
5811 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5812 #define find_close_core(cpuid, tid) CPU_FIRST()
5813 #define find_nth(ctx, gid) CPU_FIRST()
5816 /* Just to avoid copy/paste */
5818 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5819 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5823 int co, cpuid, err, tid;
5826 co = ctx->ifc_sysctl_core_offset;
5827 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5828 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5829 cpuid = find_nth(ctx, qid + co);
5830 tid = get_core_offset(ctx, type, qid);
5832 device_printf(dev, "get_core_offset failed\n");
5833 return (EOPNOTSUPP);
5835 cpuid = find_close_core(cpuid, tid);
5836 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid,
5837 rman_get_start(irq->ii_res), name);
5839 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5843 if (cpuid > ctx->ifc_cpuid_highest)
5844 ctx->ifc_cpuid_highest = cpuid;
5850 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5851 iflib_intr_type_t type, driver_filter_t *filter,
5852 void *filter_arg, int qid, const char *name)
5855 struct grouptask *gtask;
5856 struct taskqgroup *tqg;
5857 iflib_filter_info_t info;
5860 driver_filter_t *intr_fast;
5863 info = &ctx->ifc_filter_info;
5867 /* XXX merge tx/rx for netmap? */
5869 q = &ctx->ifc_txqs[qid];
5870 info = &ctx->ifc_txqs[qid].ift_filter_info;
5871 gtask = &ctx->ifc_txqs[qid].ift_task;
5872 tqg = qgroup_if_io_tqg;
5874 intr_fast = iflib_fast_intr;
5875 GROUPTASK_INIT(gtask, 0, fn, q);
5876 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5879 q = &ctx->ifc_rxqs[qid];
5880 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5881 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5882 tqg = qgroup_if_io_tqg;
5884 intr_fast = iflib_fast_intr;
5885 GROUPTASK_INIT(gtask, 0, fn, q);
5887 case IFLIB_INTR_RXTX:
5888 q = &ctx->ifc_rxqs[qid];
5889 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5890 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5891 tqg = qgroup_if_io_tqg;
5893 intr_fast = iflib_fast_intr_rxtx;
5894 GROUPTASK_INIT(gtask, 0, fn, q);
5896 case IFLIB_INTR_ADMIN:
5899 info = &ctx->ifc_filter_info;
5900 gtask = &ctx->ifc_admin_task;
5901 tqg = qgroup_if_config_tqg;
5902 fn = _task_fn_admin;
5903 intr_fast = iflib_fast_intr_ctx;
5906 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5911 info->ifi_filter = filter;
5912 info->ifi_filter_arg = filter_arg;
5913 info->ifi_task = gtask;
5917 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5919 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5922 if (type == IFLIB_INTR_ADMIN)
5926 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5931 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res),
5939 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5941 struct grouptask *gtask;
5942 struct taskqgroup *tqg;
5949 q = &ctx->ifc_txqs[qid];
5950 gtask = &ctx->ifc_txqs[qid].ift_task;
5951 tqg = qgroup_if_io_tqg;
5955 q = &ctx->ifc_rxqs[qid];
5956 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5957 tqg = qgroup_if_io_tqg;
5960 case IFLIB_INTR_IOV:
5962 gtask = &ctx->ifc_vflr_task;
5963 tqg = qgroup_if_config_tqg;
5967 panic("unknown net intr type");
5969 GROUPTASK_INIT(gtask, 0, fn, q);
5971 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5974 taskqgroup_attach(tqg, gtask, q,
5975 rman_get_start(irq->ii_res), name);
5977 taskqgroup_attach(tqg, gtask, q, -1, name);
5982 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5986 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5989 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
5990 rman_get_rid(irq->ii_res), irq->ii_res);
5994 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5996 iflib_txq_t txq = ctx->ifc_txqs;
5997 iflib_rxq_t rxq = ctx->ifc_rxqs;
5998 if_irq_t irq = &ctx->ifc_legacy_irq;
5999 iflib_filter_info_t info;
6000 struct grouptask *gtask;
6001 struct taskqgroup *tqg;
6008 q = &ctx->ifc_rxqs[0];
6009 info = &rxq[0].ifr_filter_info;
6010 gtask = &rxq[0].ifr_task;
6011 tqg = qgroup_if_io_tqg;
6012 tqrid = irq->ii_rid = *rid;
6014 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6016 ctx->ifc_flags |= IFC_LEGACY;
6017 info->ifi_filter = filter;
6018 info->ifi_filter_arg = filter_arg;
6019 info->ifi_task = gtask;
6020 info->ifi_ctx = rx_only ? ctx : q;
6022 /* We allocate a single interrupt resource */
6023 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6024 iflib_fast_intr_rxtx, NULL, info, name);
6027 GROUPTASK_INIT(gtask, 0, fn, q);
6028 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
6030 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6031 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq,
6032 rman_get_start(irq->ii_res), "tx");
6037 iflib_led_create(if_ctx_t ctx)
6040 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6041 device_get_nameunit(ctx->ifc_dev));
6045 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6048 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6052 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6055 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6059 iflib_admin_intr_deferred(if_ctx_t ctx)
6062 struct grouptask *gtask;
6064 gtask = &ctx->ifc_admin_task;
6065 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6068 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6072 iflib_iov_intr_deferred(if_ctx_t ctx)
6075 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6079 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
6082 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
6086 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6090 GROUPTASK_INIT(gtask, 0, fn, ctx);
6091 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
6095 iflib_config_gtask_deinit(struct grouptask *gtask)
6098 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6102 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6104 if_t ifp = ctx->ifc_ifp;
6105 iflib_txq_t txq = ctx->ifc_txqs;
6107 if_setbaudrate(ifp, baudrate);
6108 if (baudrate >= IF_Gbps(10)) {
6110 ctx->ifc_flags |= IFC_PREFETCH;
6113 /* If link down, disable watchdog */
6114 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6115 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6116 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6118 ctx->ifc_link_state = link_state;
6119 if_link_state_change(ifp, link_state);
6123 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6127 int credits_pre = txq->ift_cidx_processed;
6130 if (ctx->isc_txd_credits_update == NULL)
6133 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6134 BUS_DMASYNC_POSTREAD);
6135 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6138 txq->ift_processed += credits;
6139 txq->ift_cidx_processed += credits;
6141 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6142 if (txq->ift_cidx_processed >= txq->ift_size)
6143 txq->ift_cidx_processed -= txq->ift_size;
6148 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6153 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6154 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6155 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6156 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6161 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6162 const char *description, if_int_delay_info_t info,
6163 int offset, int value)
6165 info->iidi_ctx = ctx;
6166 info->iidi_offset = offset;
6167 info->iidi_value = value;
6168 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6169 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6170 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6171 info, 0, iflib_sysctl_int_delay, "I", description);
6175 iflib_ctx_lock_get(if_ctx_t ctx)
6178 return (&ctx->ifc_ctx_sx);
6182 iflib_msix_init(if_ctx_t ctx)
6184 device_t dev = ctx->ifc_dev;
6185 if_shared_ctx_t sctx = ctx->ifc_sctx;
6186 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6187 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6188 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6190 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6191 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6194 device_printf(dev, "msix_init qsets capped at %d\n",
6195 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6197 /* Override by tuneable */
6198 if (scctx->isc_disable_msix)
6201 /* First try MSI-X */
6202 if ((msgs = pci_msix_count(dev)) == 0) {
6204 device_printf(dev, "MSI-X not supported or disabled\n");
6208 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6210 * bar == -1 => "trust me I know what I'm doing"
6211 * Some drivers are for hardware that is so shoddily
6212 * documented that no one knows which bars are which
6213 * so the developer has to map all bars. This hack
6214 * allows shoddy garbage to use MSI-X in this framework.
6217 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6218 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6219 if (ctx->ifc_msix_mem == NULL) {
6220 device_printf(dev, "Unable to map MSI-X table\n");
6225 admincnt = sctx->isc_admin_intrcnt;
6227 /* use only 1 qset in debug mode */
6228 queuemsgs = min(msgs - admincnt, 1);
6230 queuemsgs = msgs - admincnt;
6233 queues = imin(queuemsgs, rss_getnumbuckets());
6237 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6240 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6241 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6243 /* If we're doing RSS, clamp at the number of RSS buckets */
6244 if (queues > rss_getnumbuckets())
6245 queues = rss_getnumbuckets();
6247 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6248 rx_queues = iflib_num_rx_queues;
6252 if (rx_queues > scctx->isc_nrxqsets)
6253 rx_queues = scctx->isc_nrxqsets;
6256 * We want this to be all logical CPUs by default
6258 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6259 tx_queues = iflib_num_tx_queues;
6261 tx_queues = mp_ncpus;
6263 if (tx_queues > scctx->isc_ntxqsets)
6264 tx_queues = scctx->isc_ntxqsets;
6266 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6268 if (tx_queues != rx_queues)
6270 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6271 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6273 tx_queues = min(rx_queues, tx_queues);
6274 rx_queues = min(rx_queues, tx_queues);
6277 vectors = rx_queues + admincnt;
6278 if (msgs < vectors) {
6280 "insufficient number of MSI-X vectors "
6281 "(supported %d, need %d)\n", msgs, vectors);
6285 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6288 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6289 if (vectors != msgs) {
6291 "Unable to allocate sufficient MSI-X vectors "
6292 "(got %d, need %d)\n", vectors, msgs);
6293 pci_release_msi(dev);
6295 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6297 ctx->ifc_msix_mem = NULL;
6301 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6303 scctx->isc_vectors = vectors;
6304 scctx->isc_nrxqsets = rx_queues;
6305 scctx->isc_ntxqsets = tx_queues;
6306 scctx->isc_intr = IFLIB_INTR_MSIX;
6311 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6314 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6316 ctx->ifc_msix_mem = NULL;
6321 vectors = pci_msi_count(dev);
6322 scctx->isc_nrxqsets = 1;
6323 scctx->isc_ntxqsets = 1;
6324 scctx->isc_vectors = vectors;
6325 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6326 device_printf(dev,"Using an MSI interrupt\n");
6327 scctx->isc_intr = IFLIB_INTR_MSI;
6329 scctx->isc_vectors = 1;
6330 device_printf(dev,"Using a Legacy interrupt\n");
6331 scctx->isc_intr = IFLIB_INTR_LEGACY;
6337 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6340 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6343 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6345 const char *ring_state = "UNKNOWN";
6348 rc = sysctl_wire_old_buffer(req, 0);
6352 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6357 ring_state = ring_states[state[3]];
6359 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6360 state[0], state[1], state[2], ring_state);
6361 rc = sbuf_finish(sb);
6366 enum iflib_ndesc_handler {
6372 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6374 if_ctx_t ctx = (void *)arg1;
6375 enum iflib_ndesc_handler type = arg2;
6376 char buf[256] = {0};
6383 case IFLIB_NTXD_HANDLER:
6384 ndesc = ctx->ifc_sysctl_ntxds;
6386 nqs = ctx->ifc_sctx->isc_ntxqs;
6388 case IFLIB_NRXD_HANDLER:
6389 ndesc = ctx->ifc_sysctl_nrxds;
6391 nqs = ctx->ifc_sctx->isc_nrxqs;
6394 printf("%s: unhandled type\n", __func__);
6400 for (i=0; i<8; i++) {
6405 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6408 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6409 if (rc || req->newptr == NULL)
6412 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6413 i++, p = strsep(&next, " ,")) {
6414 ndesc[i] = strtoul(p, NULL, 10);
6420 #define NAME_BUFLEN 32
6422 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6424 device_t dev = iflib_get_dev(ctx);
6425 struct sysctl_oid_list *child, *oid_list;
6426 struct sysctl_ctx_list *ctx_list;
6427 struct sysctl_oid *node;
6429 ctx_list = device_get_sysctl_ctx(dev);
6430 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6431 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6432 CTLFLAG_RD, NULL, "IFLIB fields");
6433 oid_list = SYSCTL_CHILDREN(node);
6435 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6436 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6439 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6440 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6441 "# of txqs to use, 0 => use default #");
6442 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6443 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6444 "# of rxqs to use, 0 => use default #");
6445 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6446 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6447 "permit #txq != #rxq");
6448 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6449 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6450 "disable MSI-X (default 0)");
6451 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6452 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6453 "set the RX budget");
6454 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6455 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6456 "cause TX to abdicate instead of running to completion");
6457 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6458 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6459 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6460 "offset to start using cores at");
6461 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6462 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6463 "use separate cores for TX and RX");
6465 /* XXX change for per-queue sizes */
6466 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6467 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6468 mp_ndesc_handler, "A",
6469 "list of # of TX descriptors to use, 0 = use default #");
6470 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6471 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6472 mp_ndesc_handler, "A",
6473 "list of # of RX descriptors to use, 0 = use default #");
6477 iflib_add_device_sysctl_post(if_ctx_t ctx)
6479 if_shared_ctx_t sctx = ctx->ifc_sctx;
6480 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6481 device_t dev = iflib_get_dev(ctx);
6482 struct sysctl_oid_list *child;
6483 struct sysctl_ctx_list *ctx_list;
6488 char namebuf[NAME_BUFLEN];
6490 struct sysctl_oid *queue_node, *fl_node, *node;
6491 struct sysctl_oid_list *queue_list, *fl_list;
6492 ctx_list = device_get_sysctl_ctx(dev);
6494 node = ctx->ifc_sysctl_node;
6495 child = SYSCTL_CHILDREN(node);
6497 if (scctx->isc_ntxqsets > 100)
6499 else if (scctx->isc_ntxqsets > 10)
6503 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6504 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6505 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6506 CTLFLAG_RD, NULL, "Queue Name");
6507 queue_list = SYSCTL_CHILDREN(queue_node);
6509 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6511 &txq->ift_dequeued, "total mbufs freed");
6512 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6514 &txq->ift_enqueued, "total mbufs enqueued");
6516 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6518 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6519 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6521 &txq->ift_pullups, "# of times m_pullup was called");
6522 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6524 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6525 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6527 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6528 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6530 &txq->ift_map_failed, "# of times DMA map failed");
6531 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6533 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6534 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6536 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6537 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6539 &txq->ift_pidx, 1, "Producer Index");
6540 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6542 &txq->ift_cidx, 1, "Consumer Index");
6543 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6545 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6546 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6548 &txq->ift_in_use, 1, "descriptors in use");
6549 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6551 &txq->ift_processed, "descriptors procesed for clean");
6552 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6554 &txq->ift_cleaned, "total cleaned");
6555 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6556 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6557 0, mp_ring_state_handler, "A", "soft ring state");
6558 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6559 CTLFLAG_RD, &txq->ift_br->enqueues,
6560 "# of enqueues to the mp_ring for this queue");
6561 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6562 CTLFLAG_RD, &txq->ift_br->drops,
6563 "# of drops in the mp_ring for this queue");
6564 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6565 CTLFLAG_RD, &txq->ift_br->starts,
6566 "# of normal consumer starts in the mp_ring for this queue");
6567 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6568 CTLFLAG_RD, &txq->ift_br->stalls,
6569 "# of consumer stalls in the mp_ring for this queue");
6570 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6571 CTLFLAG_RD, &txq->ift_br->restarts,
6572 "# of consumer restarts in the mp_ring for this queue");
6573 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6574 CTLFLAG_RD, &txq->ift_br->abdications,
6575 "# of consumer abdications in the mp_ring for this queue");
6578 if (scctx->isc_nrxqsets > 100)
6580 else if (scctx->isc_nrxqsets > 10)
6584 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6585 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6586 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6587 CTLFLAG_RD, NULL, "Queue Name");
6588 queue_list = SYSCTL_CHILDREN(queue_node);
6589 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6590 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6592 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6595 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6596 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6597 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6598 CTLFLAG_RD, NULL, "freelist Name");
6599 fl_list = SYSCTL_CHILDREN(fl_node);
6600 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6602 &fl->ifl_pidx, 1, "Producer Index");
6603 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6605 &fl->ifl_cidx, 1, "Consumer Index");
6606 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6608 &fl->ifl_credits, 1, "credits available");
6610 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6612 &fl->ifl_m_enqueued, "mbufs allocated");
6613 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6615 &fl->ifl_m_dequeued, "mbufs freed");
6616 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6618 &fl->ifl_cl_enqueued, "clusters allocated");
6619 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6621 &fl->ifl_cl_dequeued, "clusters freed");
6630 iflib_request_reset(if_ctx_t ctx)
6634 ctx->ifc_flags |= IFC_DO_RESET;
6638 #ifndef __NO_STRICT_ALIGNMENT
6639 static struct mbuf *
6640 iflib_fixup_rx(struct mbuf *m)
6644 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6645 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6646 m->m_data += ETHER_HDR_LEN;
6649 MGETHDR(n, M_NOWAIT, MT_DATA);
6654 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6655 m->m_data += ETHER_HDR_LEN;
6656 m->m_len -= ETHER_HDR_LEN;
6657 n->m_len = ETHER_HDR_LEN;
6658 M_MOVE_PKTHDR(n, m);
6667 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6671 ctx = if_getsoftc(ifp);
6673 *nrxr = NRXQSETS(ctx);
6674 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6675 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6680 iflib_netdump_event(if_t ifp, enum netdump_ev event)
6683 if_softc_ctx_t scctx;
6688 ctx = if_getsoftc(ifp);
6689 scctx = &ctx->ifc_softc_ctx;
6693 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6694 rxq = &ctx->ifc_rxqs[i];
6695 for (j = 0; j < rxq->ifr_nfl; j++) {
6697 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6700 iflib_no_tx_batch = 1;
6708 iflib_netdump_transmit(if_t ifp, struct mbuf *m)
6714 ctx = if_getsoftc(ifp);
6715 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6719 txq = &ctx->ifc_txqs[0];
6720 error = iflib_encap(txq, &m);
6722 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6727 iflib_netdump_poll(if_t ifp, int count)
6730 if_softc_ctx_t scctx;
6734 ctx = if_getsoftc(ifp);
6735 scctx = &ctx->ifc_softc_ctx;
6737 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6741 txq = &ctx->ifc_txqs[0];
6742 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6744 for (i = 0; i < scctx->isc_nrxqsets; i++)
6745 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6748 #endif /* NETDUMP */