2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
63 #include <netinet/in.h>
64 #include <netinet/in_pcb.h>
65 #include <netinet/tcp_lro.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/if_ether.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
78 #include <dev/led/led.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pci_private.h>
83 #include <net/iflib.h>
87 #if defined(__i386__) || defined(__amd64__)
88 #include <sys/memdesc.h>
89 #include <machine/bus.h>
90 #include <machine/md_var.h>
91 #include <machine/specialreg.h>
92 #include <x86/include/busdma_impl.h>
93 #include <x86/iommu/busdma_dmar.h>
96 #include <sys/bitstring.h>
98 * enable accounting of every mbuf as it comes in to and goes out of
99 * iflib's software descriptor references
101 #define MEMORY_LOGGING 0
103 * Enable mbuf vectors for compressing long mbuf chains
108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
109 * we prefetch needs to be determined by the time spent in m_free vis a vis
110 * the cost of a prefetch. This will of course vary based on the workload:
111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
112 * is quite expensive, thus suggesting very little prefetch.
113 * - small packet forwarding which is just returning a single mbuf to
114 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 typedef struct iflib_txq *iflib_txq_t;
134 typedef struct iflib_rxq *iflib_rxq_t;
136 typedef struct iflib_fl *iflib_fl_t;
140 typedef struct iflib_filter_info {
141 driver_filter_t *ifi_filter;
142 void *ifi_filter_arg;
143 struct grouptask *ifi_task;
145 } *iflib_filter_info_t;
150 * Pointer to hardware driver's softc
157 if_shared_ctx_t ifc_sctx;
158 struct if_softc_ctx ifc_softc_ctx;
162 uint16_t ifc_nhwtxqs;
163 uint16_t ifc_nhwrxqs;
165 iflib_txq_t ifc_txqs;
166 iflib_rxq_t ifc_rxqs;
167 uint32_t ifc_if_flags;
169 uint32_t ifc_max_fl_buf_size;
174 int ifc_watchdog_events;
175 struct cdev *ifc_led_dev;
176 struct resource *ifc_msix_mem;
178 struct if_irq ifc_legacy_irq;
179 struct grouptask ifc_admin_task;
180 struct grouptask ifc_vflr_task;
181 struct iflib_filter_info ifc_filter_info;
182 struct ifmedia ifc_media;
184 struct sysctl_oid *ifc_sysctl_node;
185 uint16_t ifc_sysctl_ntxqs;
186 uint16_t ifc_sysctl_nrxqs;
187 uint16_t ifc_sysctl_qs_eq_override;
189 qidx_t ifc_sysctl_ntxds[8];
190 qidx_t ifc_sysctl_nrxds[8];
191 struct if_txrx ifc_txrx;
192 #define isc_txd_encap ifc_txrx.ift_txd_encap
193 #define isc_txd_flush ifc_txrx.ift_txd_flush
194 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
195 #define isc_rxd_available ifc_txrx.ift_rxd_available
196 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
198 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
201 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
202 eventhandler_tag ifc_vlan_attach_event;
203 eventhandler_tag ifc_vlan_detach_event;
204 uint8_t ifc_mac[ETHER_ADDR_LEN];
205 char ifc_mtx_name[16];
210 iflib_get_softc(if_ctx_t ctx)
213 return (ctx->ifc_softc);
217 iflib_get_dev(if_ctx_t ctx)
220 return (ctx->ifc_dev);
224 iflib_get_ifp(if_ctx_t ctx)
227 return (ctx->ifc_ifp);
231 iflib_get_media(if_ctx_t ctx)
234 return (&ctx->ifc_media);
238 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
241 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
245 iflib_get_softc_ctx(if_ctx_t ctx)
248 return (&ctx->ifc_softc_ctx);
252 iflib_get_sctx(if_ctx_t ctx)
255 return (ctx->ifc_sctx);
258 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
259 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
260 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
262 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
263 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
265 #define RX_SW_DESC_MAP_CREATED (1 << 0)
266 #define TX_SW_DESC_MAP_CREATED (1 << 1)
267 #define RX_SW_DESC_INUSE (1 << 3)
268 #define TX_SW_DESC_MAPPED (1 << 4)
270 #define M_TOOBIG M_UNUSED_8
272 typedef struct iflib_sw_rx_desc_array {
273 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
274 struct mbuf **ifsd_m; /* pkthdr mbufs */
275 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
277 } iflib_rxsd_array_t;
279 typedef struct iflib_sw_tx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
286 /* magic number that should be high enough for any hardware */
287 #define IFLIB_MAX_TX_SEGS 128
288 #define IFLIB_MAX_RX_SEGS 32
289 #define IFLIB_RX_COPY_THRESH 128
290 #define IFLIB_MAX_RX_REFRESH 32
291 /* The minimum descriptors per second before we start coalescing */
292 #define IFLIB_MIN_DESC_SEC 16384
293 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
294 #define IFLIB_QUEUE_IDLE 0
295 #define IFLIB_QUEUE_HUNG 1
296 #define IFLIB_QUEUE_WORKING 2
297 /* maximum number of txqs that can share an rx interrupt */
298 #define IFLIB_MAX_TX_SHARED_INTR 4
300 /* this should really scale with ring size - this is a fairly arbitrary value */
301 #define TX_BATCH_SIZE 32
303 #define IFLIB_RESTART_BUDGET 8
305 #define IFC_LEGACY 0x001
306 #define IFC_QFLUSH 0x002
307 #define IFC_MULTISEG 0x004
308 #define IFC_DMAR 0x008
309 #define IFC_SC_ALLOCATED 0x010
310 #define IFC_INIT_DONE 0x020
311 #define IFC_PREFETCH 0x040
312 #define IFC_DO_RESET 0x080
313 #define IFC_CHECK_HUNG 0x100
315 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
316 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
317 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
321 qidx_t ift_cidx_processed;
324 uint8_t ift_br_offset;
325 uint16_t ift_npending;
326 uint16_t ift_db_pending;
327 uint16_t ift_rs_pending;
329 uint8_t ift_txd_size[8];
330 uint64_t ift_processed;
331 uint64_t ift_cleaned;
332 uint64_t ift_cleaned_prev;
334 uint64_t ift_enqueued;
335 uint64_t ift_dequeued;
337 uint64_t ift_no_tx_dma_setup;
338 uint64_t ift_no_desc_avail;
339 uint64_t ift_mbuf_defrag_failed;
340 uint64_t ift_mbuf_defrag;
341 uint64_t ift_map_failed;
342 uint64_t ift_txd_encap_efbig;
343 uint64_t ift_pullups;
346 struct mtx ift_db_mtx;
348 /* constant values */
350 struct ifmp_ring *ift_br;
351 struct grouptask ift_task;
354 struct callout ift_timer;
356 if_txsd_vec_t ift_sds;
359 uint8_t ift_update_freq;
360 struct iflib_filter_info ift_filter_info;
361 bus_dma_tag_t ift_desc_tag;
362 bus_dma_tag_t ift_tso_desc_tag;
363 iflib_dma_info_t ift_ifdi;
364 #define MTX_NAME_LEN 16
365 char ift_mtx_name[MTX_NAME_LEN];
366 char ift_db_mtx_name[MTX_NAME_LEN];
367 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
368 #ifdef IFLIB_DIAGNOSTICS
369 uint64_t ift_cpu_exec_count[256];
371 } __aligned(CACHE_LINE_SIZE);
378 uint8_t ifl_rxd_size;
380 uint64_t ifl_m_enqueued;
381 uint64_t ifl_m_dequeued;
382 uint64_t ifl_cl_enqueued;
383 uint64_t ifl_cl_dequeued;
387 bitstr_t *ifl_rx_bitmap;
391 uint16_t ifl_buf_size;
394 iflib_rxsd_array_t ifl_sds;
397 bus_dma_tag_t ifl_desc_tag;
398 iflib_dma_info_t ifl_ifdi;
399 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
400 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
401 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
402 } __aligned(CACHE_LINE_SIZE);
405 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
411 else if (pidx < cidx)
412 used = size - cidx + pidx;
413 else if (gen == 0 && pidx == cidx)
415 else if (gen == 1 && pidx == cidx)
423 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
425 #define IDXDIFF(head, tail, wrap) \
426 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
429 /* If there is a separate completion queue -
430 * these are the cq cidx and pidx. Otherwise
437 uint8_t ifr_fl_offset;
443 uint8_t ifr_lro_enabled;
446 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
447 struct lro_ctrl ifr_lc;
448 struct grouptask ifr_task;
449 struct iflib_filter_info ifr_filter_info;
450 iflib_dma_info_t ifr_ifdi;
452 /* dynamically allocate if any drivers need a value substantially larger than this */
453 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
454 #ifdef IFLIB_DIAGNOSTICS
455 uint64_t ifr_cpu_exec_count[256];
457 } __aligned(CACHE_LINE_SIZE);
459 typedef struct if_rxsd {
461 struct mbuf **ifsd_m;
466 /* multiple of word size */
468 #define PKT_INFO_SIZE 6
469 #define RXD_INFO_SIZE 5
470 #define PKT_TYPE uint64_t
472 #define PKT_INFO_SIZE 11
473 #define RXD_INFO_SIZE 8
474 #define PKT_TYPE uint32_t
476 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
477 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
479 typedef struct if_pkt_info_pad {
480 PKT_TYPE pkt_val[PKT_INFO_SIZE];
481 } *if_pkt_info_pad_t;
482 typedef struct if_rxd_info_pad {
483 PKT_TYPE rxd_val[RXD_INFO_SIZE];
484 } *if_rxd_info_pad_t;
486 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
487 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
491 pkt_info_zero(if_pkt_info_t pi)
493 if_pkt_info_pad_t pi_pad;
495 pi_pad = (if_pkt_info_pad_t)pi;
496 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
497 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
499 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
500 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
505 rxd_info_zero(if_rxd_info_t ri)
507 if_rxd_info_pad_t ri_pad;
510 ri_pad = (if_rxd_info_pad_t)ri;
511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
512 ri_pad->rxd_val[i] = 0;
513 ri_pad->rxd_val[i+1] = 0;
514 ri_pad->rxd_val[i+2] = 0;
515 ri_pad->rxd_val[i+3] = 0;
518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
523 * Only allow a single packet to take up most 1/nth of the tx ring
525 #define MAX_SINGLE_PACKET_FRACTION 12
526 #define IF_BAD_DMA (bus_addr_t)-1
528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
530 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
532 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
533 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
534 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 /* Our boot-time initialization hook */
542 static int iflib_module_event_handler(module_t, int, void *);
544 static moduledata_t iflib_moduledata = {
546 iflib_module_event_handler,
550 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
551 MODULE_VERSION(iflib, 1);
553 MODULE_DEPEND(iflib, pci, 1, 1, 1);
554 MODULE_DEPEND(iflib, ether, 1, 1, 1);
556 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
557 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
559 #ifndef IFLIB_DEBUG_COUNTERS
561 #define IFLIB_DEBUG_COUNTERS 1
563 #define IFLIB_DEBUG_COUNTERS 0
564 #endif /* !INVARIANTS */
567 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
568 "iflib driver parameters");
571 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
573 static int iflib_min_tx_latency = 0;
574 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
575 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
576 static int iflib_no_tx_batch = 0;
577 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
578 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
581 #if IFLIB_DEBUG_COUNTERS
583 static int iflib_tx_seen;
584 static int iflib_tx_sent;
585 static int iflib_tx_encap;
586 static int iflib_rx_allocs;
587 static int iflib_fl_refills;
588 static int iflib_fl_refills_large;
589 static int iflib_tx_frees;
591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
592 &iflib_tx_seen, 0, "# tx mbufs seen");
593 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
594 &iflib_tx_sent, 0, "# tx mbufs sent");
595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
596 &iflib_tx_encap, 0, "# tx mbufs encapped");
597 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
598 &iflib_tx_frees, 0, "# tx frees");
599 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
600 &iflib_rx_allocs, 0, "# rx allocations");
601 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
602 &iflib_fl_refills, 0, "# refills");
603 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
604 &iflib_fl_refills_large, 0, "# large refills");
607 static int iflib_txq_drain_flushing;
608 static int iflib_txq_drain_oactive;
609 static int iflib_txq_drain_notready;
610 static int iflib_txq_drain_encapfail;
612 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
613 &iflib_txq_drain_flushing, 0, "# drain flushes");
614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
615 &iflib_txq_drain_oactive, 0, "# drain oactives");
616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
617 &iflib_txq_drain_notready, 0, "# drain notready");
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
619 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
622 static int iflib_encap_load_mbuf_fail;
623 static int iflib_encap_txq_avail_fail;
624 static int iflib_encap_txd_encap_fail;
626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
627 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
629 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
631 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
633 static int iflib_task_fn_rxs;
634 static int iflib_rx_intr_enables;
635 static int iflib_fast_intrs;
636 static int iflib_intr_link;
637 static int iflib_intr_msix;
638 static int iflib_rx_unavail;
639 static int iflib_rx_ctx_inactive;
640 static int iflib_rx_zero_len;
641 static int iflib_rx_if_input;
642 static int iflib_rx_mbuf_null;
643 static int iflib_rxd_flush;
645 static int iflib_verbose_debug;
647 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
648 &iflib_intr_link, 0, "# intr link calls");
649 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
650 &iflib_intr_msix, 0, "# intr msix calls");
651 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
652 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
654 &iflib_rx_intr_enables, 0, "# rx intr enables");
655 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
656 &iflib_fast_intrs, 0, "# fast_intr calls");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
658 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
660 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
662 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
664 &iflib_rx_if_input, 0, "# times rxeof called if_input");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
666 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
668 &iflib_rxd_flush, 0, "# times rxd_flush called");
669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
670 &iflib_verbose_debug, 0, "enable verbose debugging");
672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
674 iflib_debug_reset(void)
676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
678 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
679 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
680 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail =
681 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables =
682 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
683 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
684 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
688 #define DBG_COUNTER_INC(name)
689 static void iflib_debug_reset(void) {}
694 #define IFLIB_DEBUG 0
696 static void iflib_tx_structures_free(if_ctx_t ctx);
697 static void iflib_rx_structures_free(if_ctx_t ctx);
698 static int iflib_queues_alloc(if_ctx_t ctx);
699 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
700 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
701 static int iflib_qset_structures_setup(if_ctx_t ctx);
702 static int iflib_msix_init(if_ctx_t ctx);
703 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
704 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
705 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
706 static int iflib_register(if_ctx_t);
707 static void iflib_init_locked(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
710 static void iflib_ifmp_purge(iflib_txq_t txq);
711 static void _iflib_pre_assert(if_softc_ctx_t scctx);
712 static void iflib_stop(if_ctx_t ctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 #ifndef __NO_STRICT_ALIGNMENT
715 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
719 #include <sys/selinfo.h>
720 #include <net/netmap.h>
721 #include <dev/netmap/netmap_kern.h>
723 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
726 * device-specific sysctl variables:
728 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
729 * During regular operations the CRC is stripped, but on some
730 * hardware reception of frames not multiple of 64 is slower,
731 * so using crcstrip=0 helps in benchmarks.
733 * iflib_rx_miss, iflib_rx_miss_bufs:
734 * count packets that might be missed due to lost interrupts.
736 SYSCTL_DECL(_dev_netmap);
738 * The xl driver by default strips CRCs and we do not override it.
741 int iflib_crcstrip = 1;
742 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
743 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
745 int iflib_rx_miss, iflib_rx_miss_bufs;
746 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
747 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
748 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
749 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
752 * Register/unregister. We are already under netmap lock.
753 * Only called on the first register or the last unregister.
756 iflib_netmap_register(struct netmap_adapter *na, int onoff)
758 struct ifnet *ifp = na->ifp;
759 if_ctx_t ctx = ifp->if_softc;
763 IFDI_INTR_DISABLE(ctx);
765 /* Tell the stack that the interface is no longer active */
766 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
769 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
771 /* enable or disable flags and callbacks in na and ifp */
773 nm_set_native_flags(na);
775 nm_clear_native_flags(na);
778 iflib_init_locked(ctx);
779 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
780 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
782 nm_clear_native_flags(na);
788 * Reconcile kernel and user view of the transmit ring.
790 * All information is in the kring.
791 * Userspace wants to send packets up to the one before kring->rhead,
792 * kernel knows kring->nr_hwcur is the first unsent packet.
794 * Here we push packets out (as many as possible), and possibly
795 * reclaim buffers from previously completed transmission.
797 * The caller (netmap) guarantees that there is only one instance
798 * running at any time. Any interference with other driver
799 * methods should be handled by the individual drivers.
802 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
804 struct netmap_adapter *na = kring->na;
805 struct ifnet *ifp = na->ifp;
806 struct netmap_ring *ring = kring->ring;
807 u_int nm_i; /* index into the netmap ring */
808 u_int nic_i; /* index into the NIC ring */
810 u_int const lim = kring->nkr_num_slots - 1;
811 u_int const head = kring->rhead;
812 struct if_pkt_info pi;
815 * interrupts on every tx packet are expensive so request
816 * them every half ring, or where NS_REPORT is set
818 u_int report_frequency = kring->nkr_num_slots >> 1;
819 /* device-specific */
820 if_ctx_t ctx = ifp->if_softc;
821 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
823 if (txq->ift_sds.ifsd_map)
824 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
825 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
829 * First part: process new packets to send.
830 * nm_i is the current index in the netmap ring,
831 * nic_i is the corresponding index in the NIC ring.
833 * If we have packets to send (nm_i != head)
834 * iterate over the netmap ring, fetch length and update
835 * the corresponding slot in the NIC ring. Some drivers also
836 * need to update the buffer's physical address in the NIC slot
837 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
839 * The netmap_reload_map() calls is especially expensive,
840 * even when (as in this case) the tag is 0, so do only
841 * when the buffer has actually changed.
843 * If possible do not set the report/intr bit on all slots,
844 * but only a few times per ring or when NS_REPORT is set.
846 * Finally, on 10G and faster drivers, it might be useful
847 * to prefetch the next slot and txr entry.
850 nm_i = kring->nr_hwcur;
852 pi.ipi_segs = txq->ift_segs;
853 pi.ipi_qsidx = kring->ring_id;
854 if (nm_i != head) { /* we have new packets to send */
855 nic_i = netmap_idx_k2n(kring, nm_i);
857 __builtin_prefetch(&ring->slot[nm_i]);
858 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
859 if (txq->ift_sds.ifsd_map)
860 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
862 for (n = 0; nm_i != head; n++) {
863 struct netmap_slot *slot = &ring->slot[nm_i];
864 u_int len = slot->len;
866 void *addr = PNMB(na, slot, &paddr);
867 int flags = (slot->flags & NS_REPORT ||
868 nic_i == 0 || nic_i == report_frequency) ?
871 /* device-specific */
873 pi.ipi_segs[0].ds_addr = paddr;
874 pi.ipi_segs[0].ds_len = len;
878 pi.ipi_flags = flags;
880 /* Fill the slot in the NIC ring. */
881 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
883 /* prefetch for next round */
884 __builtin_prefetch(&ring->slot[nm_i + 1]);
885 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
886 if (txq->ift_sds.ifsd_map) {
887 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
889 NM_CHECK_ADDR_LEN(na, addr, len);
891 if (slot->flags & NS_BUF_CHANGED) {
892 /* buffer has changed, reload map */
893 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
895 /* make sure changes to the buffer are synced */
896 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
897 BUS_DMASYNC_PREWRITE);
899 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
900 nm_i = nm_next(nm_i, lim);
901 nic_i = nm_next(nic_i, lim);
903 kring->nr_hwcur = head;
905 /* synchronize the NIC ring */
906 if (txq->ift_sds.ifsd_map)
907 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
910 /* (re)start the tx unit up to slot nic_i (excluded) */
911 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
915 * Second part: reclaim buffers for completed transmissions.
917 if (iflib_tx_credits_update(ctx, txq)) {
918 /* some tx completed, increment avail */
919 nic_i = txq->ift_cidx_processed;
920 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
926 * Reconcile kernel and user view of the receive ring.
927 * Same as for the txsync, this routine must be efficient.
928 * The caller guarantees a single invocations, but races against
929 * the rest of the driver should be handled here.
931 * On call, kring->rhead is the first packet that userspace wants
932 * to keep, and kring->rcur is the wakeup point.
933 * The kernel has previously reported packets up to kring->rtail.
935 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
936 * of whether or not we received an interrupt.
939 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
941 struct netmap_adapter *na = kring->na;
942 struct netmap_ring *ring = kring->ring;
943 uint32_t nm_i; /* index into the netmap ring */
944 uint32_t nic_i, nic_i_start; /* index into the NIC ring */
946 u_int const lim = kring->nkr_num_slots - 1;
947 u_int const head = kring->rhead;
948 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
949 struct if_rxd_info ri;
950 struct if_rxd_update iru;
952 struct ifnet *ifp = na->ifp;
953 if_ctx_t ctx = ifp->if_softc;
954 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
955 iflib_fl_t fl = rxq->ifr_fl;
957 return netmap_ring_reinit(kring);
959 /* XXX check sync modes */
960 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
961 if (fl->ifl_sds.ifsd_map == NULL)
963 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
964 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
967 * First part: import newly received packets.
969 * nm_i is the index of the next free slot in the netmap ring,
970 * nic_i is the index of the next received packet in the NIC ring,
971 * and they may differ in case if_init() has been called while
972 * in netmap mode. For the receive ring we have
974 * nic_i = rxr->next_check;
975 * nm_i = kring->nr_hwtail (previous)
977 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
979 * rxr->next_check is set to 0 on a ring reinit
981 if (netmap_no_pendintr || force_update) {
982 int crclen = iflib_crcstrip ? 0 : 4;
984 uint16_t slot_flags = kring->nkr_slot_flags;
986 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) {
987 nic_i = fl->ifl_cidx;
988 nm_i = netmap_idx_n2k(kring, nic_i);
989 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
990 for (n = 0; avail > 0; n++, avail--) {
992 ri.iri_frags = rxq->ifr_frags;
993 ri.iri_qsidx = kring->ring_id;
994 ri.iri_ifp = ctx->ifc_ifp;
997 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
998 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
999 ring->slot[nm_i].flags = slot_flags;
1000 if (fl->ifl_sds.ifsd_map)
1001 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1002 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1003 nm_i = nm_next(nm_i, lim);
1004 nic_i = nm_next(nic_i, lim);
1006 if (n) { /* update the state variables */
1007 if (netmap_no_pendintr && !force_update) {
1010 iflib_rx_miss_bufs += n;
1012 fl->ifl_cidx = nic_i;
1013 kring->nr_hwtail = nm_i;
1015 kring->nr_kflags &= ~NKR_PENDINTR;
1019 * Second part: skip past packets that userspace has released.
1020 * (kring->nr_hwcur to head excluded),
1021 * and make the buffers available for reception.
1022 * As usual nm_i is the index in the netmap ring,
1023 * nic_i is the index in the NIC ring, and
1024 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1026 /* XXX not sure how this will work with multiple free lists */
1027 nm_i = kring->nr_hwcur;
1031 iru.iru_paddrs = fl->ifl_bus_addrs;
1032 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1033 iru.iru_idxs = fl->ifl_rxd_idxs;
1034 iru.iru_qsidx = rxq->ifr_id;
1035 iru.iru_buf_size = fl->ifl_buf_size;
1036 iru.iru_flidx = fl->ifl_id;
1037 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i);
1038 for (i = 0; nm_i != head; i++) {
1039 struct netmap_slot *slot = &ring->slot[nm_i];
1040 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
1042 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
1045 fl->ifl_vm_addrs[i] = addr;
1046 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) {
1047 /* buffer has changed, reload map */
1048 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr);
1050 slot->flags &= ~NS_BUF_CHANGED;
1052 nm_i = nm_next(nm_i, lim);
1053 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim);
1054 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH)
1057 iru.iru_pidx = nic_i_start;
1060 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1061 if (fl->ifl_sds.ifsd_map == NULL) {
1062 nic_i_start = nic_i;
1065 nic_i = nic_i_start;
1066 for (n = 0; n < iru.iru_count; n++) {
1067 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i],
1068 BUS_DMASYNC_PREREAD);
1069 nic_i = nm_next(nic_i, lim);
1071 nic_i_start = nic_i;
1073 kring->nr_hwcur = head;
1075 if (fl->ifl_sds.ifsd_map)
1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1079 * IMPORTANT: we must leave one free slot in the ring,
1080 * so move nic_i back by one unit
1082 nic_i = nm_prev(nic_i, lim);
1083 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
1087 return netmap_ring_reinit(kring);
1091 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1093 struct ifnet *ifp = na->ifp;
1094 if_ctx_t ctx = ifp->if_softc;
1098 IFDI_INTR_ENABLE(ctx);
1100 IFDI_INTR_DISABLE(ctx);
1107 iflib_netmap_attach(if_ctx_t ctx)
1109 struct netmap_adapter na;
1110 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1112 bzero(&na, sizeof(na));
1114 na.ifp = ctx->ifc_ifp;
1115 na.na_flags = NAF_BDG_MAYSLEEP;
1116 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1117 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1119 na.num_tx_desc = scctx->isc_ntxd[0];
1120 na.num_rx_desc = scctx->isc_nrxd[0];
1121 na.nm_txsync = iflib_netmap_txsync;
1122 na.nm_rxsync = iflib_netmap_rxsync;
1123 na.nm_register = iflib_netmap_register;
1124 na.nm_intr = iflib_netmap_intr;
1125 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1126 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1127 return (netmap_attach(&na));
1131 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1133 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1134 struct netmap_slot *slot;
1136 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1139 if (txq->ift_sds.ifsd_map == NULL)
1142 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1145 * In netmap mode, set the map for the packet buffer.
1146 * NOTE: Some drivers (not this one) also need to set
1147 * the physical buffer address in the NIC ring.
1148 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1149 * netmap slot index, si
1151 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1152 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1156 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1158 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1159 struct netmap_slot *slot;
1160 struct if_rxd_update iru;
1164 uint32_t i, j, pidx_start;
1166 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1169 fl = &rxq->ifr_fl[0];
1170 map = fl->ifl_sds.ifsd_map;
1171 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0];
1172 iru.iru_paddrs = fl->ifl_bus_addrs;
1173 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1174 iru.iru_idxs = fl->ifl_rxd_idxs;
1175 iru.iru_qsidx = rxq->ifr_id;
1176 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size;
1179 for (pidx_start = i = j = 0; i < nrxd; i++, j++) {
1180 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i);
1183 fl->ifl_rxd_idxs[j] = i;
1184 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]);
1186 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr);
1190 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1)
1193 iru.iru_pidx = pidx_start;
1197 MPASS(pidx_start + j <= nrxd);
1198 /* Update descriptors and the cached value */
1199 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1201 /* preserve queue */
1202 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) {
1203 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1204 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1205 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t);
1207 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1);
1210 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1213 #define iflib_netmap_txq_init(ctx, txq)
1214 #define iflib_netmap_rxq_init(ctx, rxq)
1215 #define iflib_netmap_detach(ifp)
1217 #define iflib_netmap_attach(ctx) (0)
1218 #define netmap_rx_irq(ifp, qid, budget) (0)
1219 #define netmap_tx_irq(ifp, qid) do {} while (0)
1223 #if defined(__i386__) || defined(__amd64__)
1224 static __inline void
1227 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1234 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1238 *(bus_addr_t *) arg = segs[0].ds_addr;
1242 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1245 if_shared_ctx_t sctx = ctx->ifc_sctx;
1246 device_t dev = ctx->ifc_dev;
1248 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1250 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1251 sctx->isc_q_align, 0, /* alignment, bounds */
1252 BUS_SPACE_MAXADDR, /* lowaddr */
1253 BUS_SPACE_MAXADDR, /* highaddr */
1254 NULL, NULL, /* filter, filterarg */
1257 size, /* maxsegsize */
1258 BUS_DMA_ALLOCNOW, /* flags */
1259 NULL, /* lockfunc */
1264 "%s: bus_dma_tag_create failed: %d\n",
1269 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1270 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1273 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1274 __func__, (uintmax_t)size, err);
1278 dma->idi_paddr = IF_BAD_DMA;
1279 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1280 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1281 if (err || dma->idi_paddr == IF_BAD_DMA) {
1283 "%s: bus_dmamap_load failed: %d\n",
1288 dma->idi_size = size;
1292 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1294 bus_dma_tag_destroy(dma->idi_tag);
1296 dma->idi_tag = NULL;
1302 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1305 iflib_dma_info_t *dmaiter;
1308 for (i = 0; i < count; i++, dmaiter++) {
1309 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1313 iflib_dma_free_multi(dmalist, i);
1318 iflib_dma_free(iflib_dma_info_t dma)
1320 if (dma->idi_tag == NULL)
1322 if (dma->idi_paddr != IF_BAD_DMA) {
1323 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1324 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1325 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1326 dma->idi_paddr = IF_BAD_DMA;
1328 if (dma->idi_vaddr != NULL) {
1329 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1330 dma->idi_vaddr = NULL;
1332 bus_dma_tag_destroy(dma->idi_tag);
1333 dma->idi_tag = NULL;
1337 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1340 iflib_dma_info_t *dmaiter = dmalist;
1342 for (i = 0; i < count; i++, dmaiter++)
1343 iflib_dma_free(*dmaiter);
1346 #ifdef EARLY_AP_STARTUP
1347 static const int iflib_started = 1;
1350 * We used to abuse the smp_started flag to decide if the queues have been
1351 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1352 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1353 * is set. Run a SYSINIT() strictly after that to just set a usable
1357 static int iflib_started;
1360 iflib_record_started(void *arg)
1365 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1366 iflib_record_started, NULL);
1370 iflib_fast_intr(void *arg)
1372 iflib_filter_info_t info = arg;
1373 struct grouptask *gtask = info->ifi_task;
1375 return (FILTER_HANDLED);
1377 DBG_COUNTER_INC(fast_intrs);
1378 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1379 return (FILTER_HANDLED);
1381 GROUPTASK_ENQUEUE(gtask);
1382 return (FILTER_HANDLED);
1386 iflib_fast_intr_rxtx(void *arg)
1388 iflib_filter_info_t info = arg;
1389 struct grouptask *gtask = info->ifi_task;
1390 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1395 return (FILTER_HANDLED);
1397 DBG_COUNTER_INC(fast_intrs);
1398 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1399 return (FILTER_HANDLED);
1401 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1402 qidx_t txqid = rxq->ifr_txqid[i];
1406 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1407 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1410 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1412 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1413 cidx = rxq->ifr_cq_cidx;
1415 cidx = rxq->ifr_fl[0].ifl_cidx;
1416 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1417 GROUPTASK_ENQUEUE(gtask);
1419 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1420 return (FILTER_HANDLED);
1425 iflib_fast_intr_ctx(void *arg)
1427 iflib_filter_info_t info = arg;
1428 struct grouptask *gtask = info->ifi_task;
1431 return (FILTER_HANDLED);
1433 DBG_COUNTER_INC(fast_intrs);
1434 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1435 return (FILTER_HANDLED);
1437 GROUPTASK_ENQUEUE(gtask);
1438 return (FILTER_HANDLED);
1442 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1443 driver_filter_t filter, driver_intr_t handler, void *arg,
1447 struct resource *res;
1449 device_t dev = ctx->ifc_dev;
1452 if (ctx->ifc_flags & IFC_LEGACY)
1453 flags |= RF_SHAREABLE;
1456 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1459 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1463 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1464 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1465 filter, handler, arg, &tag);
1468 "failed to setup interrupt for rid %d, name %s: %d\n",
1469 rid, name ? name : "unknown", rc);
1472 bus_describe_intr(dev, res, tag, "%s", name);
1479 /*********************************************************************
1481 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1482 * the information needed to transmit a packet on the wire. This is
1483 * called only once at attach, setup is done every reset.
1485 **********************************************************************/
1488 iflib_txsd_alloc(iflib_txq_t txq)
1490 if_ctx_t ctx = txq->ift_ctx;
1491 if_shared_ctx_t sctx = ctx->ifc_sctx;
1492 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1493 device_t dev = ctx->ifc_dev;
1494 int err, nsegments, ntsosegments;
1496 nsegments = scctx->isc_tx_nsegments;
1497 ntsosegments = scctx->isc_tx_tso_segments_max;
1498 MPASS(scctx->isc_ntxd[0] > 0);
1499 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1500 MPASS(nsegments > 0);
1501 MPASS(ntsosegments > 0);
1503 * Setup DMA descriptor areas.
1505 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1506 1, 0, /* alignment, bounds */
1507 BUS_SPACE_MAXADDR, /* lowaddr */
1508 BUS_SPACE_MAXADDR, /* highaddr */
1509 NULL, NULL, /* filter, filterarg */
1510 sctx->isc_tx_maxsize, /* maxsize */
1511 nsegments, /* nsegments */
1512 sctx->isc_tx_maxsegsize, /* maxsegsize */
1514 NULL, /* lockfunc */
1515 NULL, /* lockfuncarg */
1516 &txq->ift_desc_tag))) {
1517 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1518 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1519 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1522 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1523 1, 0, /* alignment, bounds */
1524 BUS_SPACE_MAXADDR, /* lowaddr */
1525 BUS_SPACE_MAXADDR, /* highaddr */
1526 NULL, NULL, /* filter, filterarg */
1527 scctx->isc_tx_tso_size_max, /* maxsize */
1528 ntsosegments, /* nsegments */
1529 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1531 NULL, /* lockfunc */
1532 NULL, /* lockfuncarg */
1533 &txq->ift_tso_desc_tag))) {
1534 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1538 if (!(txq->ift_sds.ifsd_flags =
1539 (uint8_t *) malloc(sizeof(uint8_t) *
1540 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1541 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1545 if (!(txq->ift_sds.ifsd_m =
1546 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1547 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1548 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1553 /* Create the descriptor buffer dma maps */
1554 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1555 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1558 if (!(txq->ift_sds.ifsd_map =
1559 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1560 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1565 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1566 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1568 device_printf(dev, "Unable to create TX DMA map\n");
1575 /* We free all, it handles case where we are in the middle */
1576 iflib_tx_structures_free(ctx);
1581 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1586 if (txq->ift_sds.ifsd_map != NULL)
1587 map = txq->ift_sds.ifsd_map[i];
1589 bus_dmamap_unload(txq->ift_desc_tag, map);
1590 bus_dmamap_destroy(txq->ift_desc_tag, map);
1591 txq->ift_sds.ifsd_map[i] = NULL;
1596 iflib_txq_destroy(iflib_txq_t txq)
1598 if_ctx_t ctx = txq->ift_ctx;
1600 for (int i = 0; i < txq->ift_size; i++)
1601 iflib_txsd_destroy(ctx, txq, i);
1602 if (txq->ift_sds.ifsd_map != NULL) {
1603 free(txq->ift_sds.ifsd_map, M_IFLIB);
1604 txq->ift_sds.ifsd_map = NULL;
1606 if (txq->ift_sds.ifsd_m != NULL) {
1607 free(txq->ift_sds.ifsd_m, M_IFLIB);
1608 txq->ift_sds.ifsd_m = NULL;
1610 if (txq->ift_sds.ifsd_flags != NULL) {
1611 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1612 txq->ift_sds.ifsd_flags = NULL;
1614 if (txq->ift_desc_tag != NULL) {
1615 bus_dma_tag_destroy(txq->ift_desc_tag);
1616 txq->ift_desc_tag = NULL;
1618 if (txq->ift_tso_desc_tag != NULL) {
1619 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1620 txq->ift_tso_desc_tag = NULL;
1625 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1629 mp = &txq->ift_sds.ifsd_m[i];
1633 if (txq->ift_sds.ifsd_map != NULL) {
1634 bus_dmamap_sync(txq->ift_desc_tag,
1635 txq->ift_sds.ifsd_map[i],
1636 BUS_DMASYNC_POSTWRITE);
1637 bus_dmamap_unload(txq->ift_desc_tag,
1638 txq->ift_sds.ifsd_map[i]);
1641 DBG_COUNTER_INC(tx_frees);
1646 iflib_txq_setup(iflib_txq_t txq)
1648 if_ctx_t ctx = txq->ift_ctx;
1649 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1650 iflib_dma_info_t di;
1653 /* Set number of descriptors available */
1654 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1655 /* XXX make configurable */
1656 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1659 txq->ift_cidx_processed = 0;
1660 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1661 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1663 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1664 bzero((void *)di->idi_vaddr, di->idi_size);
1666 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1667 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1668 bus_dmamap_sync(di->idi_tag, di->idi_map,
1669 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1673 /*********************************************************************
1675 * Allocate memory for rx_buffer structures. Since we use one
1676 * rx_buffer per received packet, the maximum number of rx_buffer's
1677 * that we'll need is equal to the number of receive descriptors
1678 * that we've allocated.
1680 **********************************************************************/
1682 iflib_rxsd_alloc(iflib_rxq_t rxq)
1684 if_ctx_t ctx = rxq->ifr_ctx;
1685 if_shared_ctx_t sctx = ctx->ifc_sctx;
1686 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1687 device_t dev = ctx->ifc_dev;
1691 MPASS(scctx->isc_nrxd[0] > 0);
1692 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1695 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1696 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1697 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1698 1, 0, /* alignment, bounds */
1699 BUS_SPACE_MAXADDR, /* lowaddr */
1700 BUS_SPACE_MAXADDR, /* highaddr */
1701 NULL, NULL, /* filter, filterarg */
1702 sctx->isc_rx_maxsize, /* maxsize */
1703 sctx->isc_rx_nsegments, /* nsegments */
1704 sctx->isc_rx_maxsegsize, /* maxsegsize */
1706 NULL, /* lockfunc */
1710 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1714 if (!(fl->ifl_sds.ifsd_flags =
1715 (uint8_t *) malloc(sizeof(uint8_t) *
1716 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1717 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1721 if (!(fl->ifl_sds.ifsd_m =
1722 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1723 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1724 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1728 if (!(fl->ifl_sds.ifsd_cl =
1729 (caddr_t *) malloc(sizeof(caddr_t) *
1730 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1731 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1736 /* Create the descriptor buffer dma maps */
1737 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1738 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1741 if (!(fl->ifl_sds.ifsd_map =
1742 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1743 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1748 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1749 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1751 device_printf(dev, "Unable to create RX buffer DMA map\n");
1760 iflib_rx_structures_free(ctx);
1766 * Internal service routines
1769 struct rxq_refill_cb_arg {
1771 bus_dma_segment_t seg;
1776 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1778 struct rxq_refill_cb_arg *cb_arg = arg;
1780 cb_arg->error = error;
1781 cb_arg->seg = segs[0];
1782 cb_arg->nseg = nseg;
1787 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1789 #define IS_DMAR(ctx) (0)
1793 * rxq_refill - refill an rxq free-buffer list
1794 * @ctx: the iflib context
1795 * @rxq: the free-list to refill
1796 * @n: the number of new buffers to allocate
1798 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1799 * The caller must assure that @n does not exceed the queue's capacity.
1802 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1805 int idx, frag_idx = fl->ifl_fragidx;
1806 int pidx = fl->ifl_pidx;
1810 struct if_rxd_update iru;
1811 bus_dmamap_t *sd_map;
1816 sd_m = fl->ifl_sds.ifsd_m;
1817 sd_map = fl->ifl_sds.ifsd_map;
1818 sd_cl = fl->ifl_sds.ifsd_cl;
1819 sd_flags = fl->ifl_sds.ifsd_flags;
1824 MPASS(fl->ifl_credits + n <= fl->ifl_size);
1826 if (pidx < fl->ifl_cidx)
1827 MPASS(pidx + n <= fl->ifl_cidx);
1828 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size))
1829 MPASS(fl->ifl_gen == 0);
1830 if (pidx > fl->ifl_cidx)
1831 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1833 DBG_COUNTER_INC(fl_refills);
1835 DBG_COUNTER_INC(fl_refills_large);
1836 iru.iru_paddrs = fl->ifl_bus_addrs;
1837 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1838 iru.iru_idxs = fl->ifl_rxd_idxs;
1839 iru.iru_qsidx = fl->ifl_rxq->ifr_id;
1840 iru.iru_buf_size = fl->ifl_buf_size;
1841 iru.iru_flidx = fl->ifl_id;
1844 * We allocate an uninitialized mbuf + cluster, mbuf is
1845 * initialized after rx.
1847 * If the cluster is still set then we know a minimum sized packet was received
1849 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1850 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1851 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1852 if ((cl = sd_cl[frag_idx]) == NULL) {
1853 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1856 fl->ifl_cl_enqueued++;
1859 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1863 fl->ifl_m_enqueued++;
1866 DBG_COUNTER_INC(rx_allocs);
1867 #if defined(__i386__) || defined(__amd64__)
1868 if (!IS_DMAR(ctx)) {
1869 bus_addr = pmap_kextract((vm_offset_t)cl);
1873 struct rxq_refill_cb_arg cb_arg;
1878 MPASS(sd_map != NULL);
1879 MPASS(sd_map[frag_idx] != NULL);
1880 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1881 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1882 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1883 BUS_DMASYNC_PREREAD);
1885 if (err != 0 || cb_arg.error) {
1889 if (fl->ifl_zone == zone_pack)
1890 uma_zfree(fl->ifl_zone, cl);
1895 bus_addr = cb_arg.seg.ds_addr;
1897 bit_set(fl->ifl_rx_bitmap, frag_idx);
1898 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1900 MPASS(sd_m[frag_idx] == NULL);
1901 sd_cl[frag_idx] = cl;
1903 fl->ifl_rxd_idxs[i] = frag_idx;
1904 fl->ifl_bus_addrs[i] = bus_addr;
1905 fl->ifl_vm_addrs[i] = cl;
1908 MPASS(fl->ifl_credits <= fl->ifl_size);
1909 if (++idx == fl->ifl_size) {
1913 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1914 iru.iru_pidx = pidx;
1916 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1924 DBG_COUNTER_INC(rxd_flush);
1925 if (fl->ifl_pidx == 0)
1926 pidx = fl->ifl_size - 1;
1928 pidx = fl->ifl_pidx - 1;
1931 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1932 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1933 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1934 fl->ifl_fragidx = frag_idx;
1937 static __inline void
1938 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1940 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1941 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1943 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1946 MPASS(fl->ifl_credits <= fl->ifl_size);
1947 MPASS(reclaimable == delta);
1949 if (reclaimable > 0)
1950 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1954 iflib_fl_bufs_free(iflib_fl_t fl)
1956 iflib_dma_info_t idi = fl->ifl_ifdi;
1959 for (i = 0; i < fl->ifl_size; i++) {
1960 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1961 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1962 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1964 if (*sd_flags & RX_SW_DESC_INUSE) {
1965 if (fl->ifl_sds.ifsd_map != NULL) {
1966 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1967 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1968 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1970 if (*sd_m != NULL) {
1971 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1972 uma_zfree(zone_mbuf, *sd_m);
1975 uma_zfree(fl->ifl_zone, *sd_cl);
1978 MPASS(*sd_cl == NULL);
1979 MPASS(*sd_m == NULL);
1982 fl->ifl_m_dequeued++;
1983 fl->ifl_cl_dequeued++;
1989 for (i = 0; i < fl->ifl_size; i++) {
1990 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
1991 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
1992 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
1996 * Reset free list values
1998 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
1999 bzero(idi->idi_vaddr, idi->idi_size);
2002 /*********************************************************************
2004 * Initialize a receive ring and its buffers.
2006 **********************************************************************/
2008 iflib_fl_setup(iflib_fl_t fl)
2010 iflib_rxq_t rxq = fl->ifl_rxq;
2011 if_ctx_t ctx = rxq->ifr_ctx;
2012 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2014 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size);
2016 ** Free current RX buffer structs and their mbufs
2018 iflib_fl_bufs_free(fl);
2019 /* Now replenish the mbufs */
2020 MPASS(fl->ifl_credits == 0);
2022 * XXX don't set the max_frame_size to larger
2023 * than the hardware can handle
2025 if (sctx->isc_max_frame_size <= 2048)
2026 fl->ifl_buf_size = MCLBYTES;
2027 #ifndef CONTIGMALLOC_WORKS
2029 fl->ifl_buf_size = MJUMPAGESIZE;
2031 else if (sctx->isc_max_frame_size <= 4096)
2032 fl->ifl_buf_size = MJUMPAGESIZE;
2033 else if (sctx->isc_max_frame_size <= 9216)
2034 fl->ifl_buf_size = MJUM9BYTES;
2036 fl->ifl_buf_size = MJUM16BYTES;
2038 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2039 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2040 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2041 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2044 /* avoid pre-allocating zillions of clusters to an idle card
2045 * potentially speeding up attach
2047 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2048 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2049 if (min(128, fl->ifl_size) != fl->ifl_credits)
2055 MPASS(fl->ifl_ifdi != NULL);
2056 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2057 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2061 /*********************************************************************
2063 * Free receive ring data structures
2065 **********************************************************************/
2067 iflib_rx_sds_free(iflib_rxq_t rxq)
2072 if (rxq->ifr_fl != NULL) {
2073 for (i = 0; i < rxq->ifr_nfl; i++) {
2074 fl = &rxq->ifr_fl[i];
2075 if (fl->ifl_desc_tag != NULL) {
2076 bus_dma_tag_destroy(fl->ifl_desc_tag);
2077 fl->ifl_desc_tag = NULL;
2079 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2080 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2081 /* XXX destroy maps first */
2082 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2083 fl->ifl_sds.ifsd_m = NULL;
2084 fl->ifl_sds.ifsd_cl = NULL;
2085 fl->ifl_sds.ifsd_map = NULL;
2087 free(rxq->ifr_fl, M_IFLIB);
2089 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2094 * MI independent logic
2098 iflib_timer(void *arg)
2100 iflib_txq_t txq = arg;
2101 if_ctx_t ctx = txq->ift_ctx;
2102 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2104 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2107 ** Check on the state of the TX queue(s), this
2108 ** can be done without the lock because its RO
2109 ** and the HUNG state will be static if set.
2111 IFDI_TIMER(ctx, txq->ift_id);
2112 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2113 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2114 (sctx->isc_pause_frames == 0)))
2117 if (ifmp_ring_is_stalled(txq->ift_br))
2118 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2119 txq->ift_cleaned_prev = txq->ift_cleaned;
2120 /* handle any laggards */
2121 if (txq->ift_db_pending)
2122 GROUPTASK_ENQUEUE(&txq->ift_task);
2124 sctx->isc_pause_frames = 0;
2125 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2126 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2130 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2131 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2132 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2134 IFDI_WATCHDOG_RESET(ctx);
2135 ctx->ifc_watchdog_events++;
2137 ctx->ifc_flags |= IFC_DO_RESET;
2138 iflib_admin_intr_deferred(ctx);
2143 iflib_init_locked(if_ctx_t ctx)
2145 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2146 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2147 if_t ifp = ctx->ifc_ifp;
2151 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2154 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2155 IFDI_INTR_DISABLE(ctx);
2157 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2158 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2159 /* Set hardware offload abilities */
2160 if_clearhwassist(ifp);
2161 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2162 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2163 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2164 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2165 if (if_getcapenable(ifp) & IFCAP_TSO4)
2166 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2167 if (if_getcapenable(ifp) & IFCAP_TSO6)
2168 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2170 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2172 callout_stop(&txq->ift_timer);
2173 CALLOUT_UNLOCK(txq);
2174 iflib_netmap_txq_init(ctx, txq);
2176 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2177 MPASS(rxq->ifr_id == i);
2178 iflib_netmap_rxq_init(ctx, rxq);
2181 i = if_getdrvflags(ifp);
2184 MPASS(if_getdrvflags(ifp) == i);
2185 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2186 /* XXX this should really be done on a per-queue basis */
2187 if (if_getcapenable(ifp) & IFCAP_NETMAP)
2189 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2190 if (iflib_fl_setup(fl)) {
2191 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2197 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2198 IFDI_INTR_ENABLE(ctx);
2199 txq = ctx->ifc_txqs;
2200 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2201 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2202 txq->ift_timer.c_cpu);
2206 iflib_media_change(if_t ifp)
2208 if_ctx_t ctx = if_getsoftc(ifp);
2212 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2213 iflib_init_locked(ctx);
2219 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2221 if_ctx_t ctx = if_getsoftc(ifp);
2224 IFDI_UPDATE_ADMIN_STATUS(ctx);
2225 IFDI_MEDIA_STATUS(ctx, ifmr);
2230 iflib_stop(if_ctx_t ctx)
2232 iflib_txq_t txq = ctx->ifc_txqs;
2233 iflib_rxq_t rxq = ctx->ifc_rxqs;
2234 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2235 iflib_dma_info_t di;
2239 /* Tell the stack that the interface is no longer active */
2240 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2242 IFDI_INTR_DISABLE(ctx);
2247 iflib_debug_reset();
2248 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2249 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2250 /* make sure all transmitters have completed before proceeding XXX */
2252 /* clean any enqueued buffers */
2253 iflib_ifmp_purge(txq);
2254 /* Free any existing tx buffers. */
2255 for (j = 0; j < txq->ift_size; j++) {
2256 iflib_txsd_free(ctx, txq, j);
2258 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2259 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2260 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2261 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2262 txq->ift_pullups = 0;
2263 ifmp_ring_reset_stats(txq->ift_br);
2264 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2265 bzero((void *)di->idi_vaddr, di->idi_size);
2267 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2268 /* make sure all transmitters have completed before proceeding XXX */
2270 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2271 bzero((void *)di->idi_vaddr, di->idi_size);
2272 /* also resets the free lists pidx/cidx */
2273 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2274 iflib_fl_bufs_free(fl);
2278 static inline caddr_t
2279 calc_next_rxd(iflib_fl_t fl, int cidx)
2283 caddr_t start, end, cur, next;
2285 nrxd = fl->ifl_size;
2286 size = fl->ifl_rxd_size;
2287 start = fl->ifl_ifdi->idi_vaddr;
2289 if (__predict_false(size == 0))
2291 cur = start + size*cidx;
2292 end = start + size*nrxd;
2293 next = CACHE_PTR_NEXT(cur);
2294 return (next < end ? next : start);
2298 prefetch_pkts(iflib_fl_t fl, int cidx)
2301 int nrxd = fl->ifl_size;
2305 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2306 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2307 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2308 next_rxd = calc_next_rxd(fl, cidx);
2310 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2311 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2312 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2313 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2314 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2315 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2316 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2317 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2321 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2326 iflib_dma_info_t di;
2330 flid = irf->irf_flid;
2331 cidx = irf->irf_idx;
2332 fl = &rxq->ifr_fl[flid];
2334 sd->ifsd_cidx = cidx;
2335 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2336 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2339 fl->ifl_m_dequeued++;
2341 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2342 prefetch_pkts(fl, cidx);
2343 if (fl->ifl_sds.ifsd_map != NULL) {
2344 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2345 prefetch(&fl->ifl_sds.ifsd_map[next]);
2346 map = fl->ifl_sds.ifsd_map[cidx];
2348 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2349 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2350 bus_dmamap_sync(di->idi_tag, di->idi_map,
2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2353 /* not valid assert if bxe really does SGE from non-contiguous elements */
2354 MPASS(fl->ifl_cidx == cidx);
2356 bus_dmamap_unload(fl->ifl_desc_tag, map);
2358 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2359 if (__predict_false(fl->ifl_cidx == 0))
2362 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2364 bit_clear(fl->ifl_rx_bitmap, cidx);
2367 static struct mbuf *
2368 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2370 int i, padlen , flags;
2371 struct mbuf *m, *mh, *mt;
2377 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2379 MPASS(*sd->ifsd_cl != NULL);
2380 MPASS(*sd->ifsd_m != NULL);
2382 /* Don't include zero-length frags */
2383 if (ri->iri_frags[i].irf_len == 0) {
2384 /* XXX we can save the cluster here, but not the mbuf */
2385 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2386 m_free(*sd->ifsd_m);
2393 flags = M_PKTHDR|M_EXT;
2395 padlen = ri->iri_pad;
2400 /* assuming padding is only on the first fragment */
2404 *sd->ifsd_cl = NULL;
2406 /* Can these two be made one ? */
2407 m_init(m, M_NOWAIT, MT_DATA, flags);
2408 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2410 * These must follow m_init and m_cljset
2412 m->m_data += padlen;
2413 ri->iri_len -= padlen;
2414 m->m_len = ri->iri_frags[i].irf_len;
2415 } while (++i < ri->iri_nfrags);
2421 * Process one software descriptor
2423 static struct mbuf *
2424 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2429 /* should I merge this back in now that the two paths are basically duplicated? */
2430 if (ri->iri_nfrags == 1 &&
2431 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2432 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2435 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2436 #ifndef __NO_STRICT_ALIGNMENT
2440 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2441 m->m_len = ri->iri_frags[0].irf_len;
2443 m = assemble_segments(rxq, ri, &sd);
2445 m->m_pkthdr.len = ri->iri_len;
2446 m->m_pkthdr.rcvif = ri->iri_ifp;
2447 m->m_flags |= ri->iri_flags;
2448 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2449 m->m_pkthdr.flowid = ri->iri_flowid;
2450 M_HASHTYPE_SET(m, ri->iri_rsstype);
2451 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2452 m->m_pkthdr.csum_data = ri->iri_csum_data;
2457 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2459 if_ctx_t ctx = rxq->ifr_ctx;
2460 if_shared_ctx_t sctx = ctx->ifc_sctx;
2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2464 struct if_rxd_info ri;
2465 int err, budget_left, rx_bytes, rx_pkts;
2471 * XXX early demux data packets so that if_input processing only handles
2472 * acks in interrupt context
2474 struct mbuf *m, *mh, *mt;
2478 if (ifp->if_capenable & IFCAP_NETMAP) {
2480 if (netmap_rx_irq(ifp, rxq->ifr_id, &work))
2487 rx_pkts = rx_bytes = 0;
2488 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2489 cidxp = &rxq->ifr_cq_cidx;
2491 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2492 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2493 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2494 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2495 DBG_COUNTER_INC(rx_unavail);
2499 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2500 if (__predict_false(!CTX_ACTIVE(ctx))) {
2501 DBG_COUNTER_INC(rx_ctx_inactive);
2505 * Reset client set fields to their default values
2508 ri.iri_qsidx = rxq->ifr_id;
2509 ri.iri_cidx = *cidxp;
2511 ri.iri_frags = rxq->ifr_frags;
2512 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2516 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2517 *cidxp = ri.iri_cidx;
2518 /* Update our consumer index */
2519 /* XXX NB: shurd - check if this is still safe */
2520 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2521 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2522 rxq->ifr_cq_gen = 0;
2524 /* was this only a completion queue message? */
2525 if (__predict_false(ri.iri_nfrags == 0))
2528 MPASS(ri.iri_nfrags != 0);
2529 MPASS(ri.iri_len != 0);
2531 /* will advance the cidx on the corresponding free lists */
2532 m = iflib_rxd_pkt_get(rxq, &ri);
2533 if (avail == 0 && budget_left)
2534 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2536 if (__predict_false(m == NULL)) {
2537 DBG_COUNTER_INC(rx_mbuf_null);
2540 /* imm_pkt: -- cxgb */
2548 /* make sure that we can refill faster than drain */
2549 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2550 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2552 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2553 while (mh != NULL) {
2556 m->m_nextpkt = NULL;
2557 #ifndef __NO_STRICT_ALIGNMENT
2558 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2561 rx_bytes += m->m_pkthdr.len;
2563 #if defined(INET6) || defined(INET)
2564 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2567 DBG_COUNTER_INC(rx_if_input);
2568 ifp->if_input(ifp, m);
2571 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2572 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2575 * Flush any outstanding LRO work
2577 #if defined(INET6) || defined(INET)
2578 tcp_lro_flush_all(&rxq->ifr_lc);
2582 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2585 ctx->ifc_flags |= IFC_DO_RESET;
2586 iflib_admin_intr_deferred(ctx);
2591 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2592 static inline qidx_t
2593 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2595 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2596 qidx_t minthresh = txq->ift_size / 8;
2597 if (in_use > 4*minthresh)
2598 return (notify_count);
2599 if (in_use > 2*minthresh)
2600 return (notify_count >> 1);
2601 if (in_use > minthresh)
2602 return (notify_count >> 3);
2606 static inline qidx_t
2607 txq_max_rs_deferred(iflib_txq_t txq)
2609 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2610 qidx_t minthresh = txq->ift_size / 8;
2611 if (txq->ift_in_use > 4*minthresh)
2612 return (notify_count);
2613 if (txq->ift_in_use > 2*minthresh)
2614 return (notify_count >> 1);
2615 if (txq->ift_in_use > minthresh)
2616 return (notify_count >> 2);
2620 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2621 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2623 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2624 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2625 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2627 /* forward compatibility for cxgb */
2628 #define FIRST_QSET(ctx) 0
2629 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2630 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2631 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2632 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2634 /* XXX we should be setting this to something other than zero */
2635 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2636 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2639 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2645 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2646 if (ring || txq->ift_db_pending >= max) {
2647 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2648 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2649 txq->ift_db_pending = txq->ift_npending = 0;
2657 print_pkt(if_pkt_info_t pi)
2659 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2660 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2661 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2662 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2663 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2664 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2668 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2669 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2672 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2674 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2675 struct ether_vlan_header *eh;
2679 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2680 M_WRITABLE(m) == 0) {
2681 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2690 * Determine where frame payload starts.
2691 * Jump over vlan headers if already present,
2692 * helpful for QinQ too.
2694 if (__predict_false(m->m_len < sizeof(*eh))) {
2696 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2699 eh = mtod(m, struct ether_vlan_header *);
2700 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2701 pi->ipi_etype = ntohs(eh->evl_proto);
2702 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2704 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2705 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2708 switch (pi->ipi_etype) {
2712 struct ip *ip = NULL;
2713 struct tcphdr *th = NULL;
2716 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2717 if (__predict_false(m->m_len < minthlen)) {
2719 * if this code bloat is causing too much of a hit
2720 * move it to a separate function and mark it noinline
2722 if (m->m_len == pi->ipi_ehdrlen) {
2725 if (n->m_len >= sizeof(*ip)) {
2726 ip = (struct ip *)n->m_data;
2727 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2728 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2731 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2733 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2737 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2739 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2740 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2741 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2744 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2745 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2746 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2748 pi->ipi_ip_hlen = ip->ip_hl << 2;
2749 pi->ipi_ipproto = ip->ip_p;
2750 pi->ipi_flags |= IPI_TX_IPV4;
2752 if (pi->ipi_csum_flags & CSUM_IP)
2755 if (pi->ipi_ipproto == IPPROTO_TCP) {
2756 if (__predict_false(th == NULL)) {
2758 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2760 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2762 pi->ipi_tcp_hflags = th->th_flags;
2763 pi->ipi_tcp_hlen = th->th_off << 2;
2764 pi->ipi_tcp_seq = th->th_seq;
2767 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2769 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2770 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2771 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2772 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2774 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2781 case ETHERTYPE_IPV6:
2783 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2785 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2787 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2788 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2791 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2793 /* XXX-BZ this will go badly in case of ext hdrs. */
2794 pi->ipi_ipproto = ip6->ip6_nxt;
2795 pi->ipi_flags |= IPI_TX_IPV6;
2797 if (pi->ipi_ipproto == IPPROTO_TCP) {
2798 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2799 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2802 pi->ipi_tcp_hflags = th->th_flags;
2803 pi->ipi_tcp_hlen = th->th_off << 2;
2807 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2810 * The corresponding flag is set by the stack in the IPv4
2811 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2812 * So, set it here because the rest of the flow requires it.
2814 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2815 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2816 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2822 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2823 pi->ipi_ip_hlen = 0;
2831 static __noinline struct mbuf *
2832 collapse_pkthdr(struct mbuf *m0)
2834 struct mbuf *m, *m_next, *tmp;
2838 while (m_next != NULL && m_next->m_len == 0) {
2842 m_next = m_next->m_next;
2846 if ((m_next->m_flags & M_EXT) == 0) {
2847 m = m_defrag(m, M_NOWAIT);
2849 tmp = m_next->m_next;
2850 memcpy(m_next, m, MPKTHSIZE);
2858 * If dodgy hardware rejects the scatter gather chain we've handed it
2859 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2862 static __noinline struct mbuf *
2863 iflib_remove_mbuf(iflib_txq_t txq)
2866 struct mbuf *m, *mh, **ifsd_m;
2868 pidx = txq->ift_pidx;
2869 ifsd_m = txq->ift_sds.ifsd_m;
2870 ntxd = txq->ift_size;
2871 mh = m = ifsd_m[pidx];
2872 ifsd_m[pidx] = NULL;
2874 txq->ift_dequeued++;
2879 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2881 txq->ift_dequeued++;
2890 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2891 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2892 int max_segs, int flags)
2895 if_shared_ctx_t sctx;
2896 if_softc_ctx_t scctx;
2897 int i, next, pidx, err, ntxd, count;
2898 struct mbuf *m, *tmp, **ifsd_m;
2903 * Please don't ever do this
2905 if (__predict_false(m->m_len == 0))
2906 *m0 = m = collapse_pkthdr(m);
2909 sctx = ctx->ifc_sctx;
2910 scctx = &ctx->ifc_softc_ctx;
2911 ifsd_m = txq->ift_sds.ifsd_m;
2912 ntxd = txq->ift_size;
2913 pidx = txq->ift_pidx;
2915 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2917 err = bus_dmamap_load_mbuf_sg(tag, map,
2918 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2921 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
2925 if (__predict_false(m->m_len <= 0)) {
2934 } while (m != NULL);
2935 if (count > *nsegs) {
2937 ifsd_m[pidx]->m_flags |= M_TOOBIG;
2943 next = (pidx + count) & (ntxd-1);
2944 MPASS(ifsd_m[next] == NULL);
2949 } while (m != NULL);
2951 int buflen, sgsize, maxsegsz, max_sgsize;
2957 if (m->m_pkthdr.csum_flags & CSUM_TSO)
2958 maxsegsz = scctx->isc_tx_tso_segsize_max;
2960 maxsegsz = sctx->isc_tx_maxsegsize;
2963 if (__predict_false(m->m_len <= 0)) {
2971 vaddr = (vm_offset_t)m->m_data;
2973 * see if we can't be smarter about physically
2974 * contiguous mappings
2976 next = (pidx + count) & (ntxd-1);
2977 MPASS(ifsd_m[next] == NULL);
2979 txq->ift_enqueued++;
2982 while (buflen > 0) {
2985 max_sgsize = MIN(buflen, maxsegsz);
2986 curaddr = pmap_kextract(vaddr);
2987 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
2988 sgsize = MIN(sgsize, max_sgsize);
2989 segs[i].ds_addr = curaddr;
2990 segs[i].ds_len = sgsize;
2998 } while (m != NULL);
3003 *m0 = iflib_remove_mbuf(txq);
3007 static inline caddr_t
3008 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3012 caddr_t start, end, cur, next;
3014 ntxd = txq->ift_size;
3015 size = txq->ift_txd_size[qid];
3016 start = txq->ift_ifdi[qid].idi_vaddr;
3018 if (__predict_false(size == 0))
3020 cur = start + size*cidx;
3021 end = start + size*ntxd;
3022 next = CACHE_PTR_NEXT(cur);
3023 return (next < end ? next : start);
3027 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3030 if_shared_ctx_t sctx;
3031 if_softc_ctx_t scctx;
3032 bus_dma_segment_t *segs;
3033 struct mbuf *m_head;
3036 struct if_pkt_info pi;
3038 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3039 bus_dma_tag_t desc_tag;
3041 segs = txq->ift_segs;
3043 sctx = ctx->ifc_sctx;
3044 scctx = &ctx->ifc_softc_ctx;
3045 segs = txq->ift_segs;
3046 ntxd = txq->ift_size;
3051 * If we're doing TSO the next descriptor to clean may be quite far ahead
3053 cidx = txq->ift_cidx;
3054 pidx = txq->ift_pidx;
3055 if (ctx->ifc_flags & IFC_PREFETCH) {
3056 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3057 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3058 next_txd = calc_next_txd(txq, cidx, 0);
3062 /* prefetch the next cache line of mbuf pointers and flags */
3063 prefetch(&txq->ift_sds.ifsd_m[next]);
3064 if (txq->ift_sds.ifsd_map != NULL) {
3065 prefetch(&txq->ift_sds.ifsd_map[next]);
3066 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3067 prefetch(&txq->ift_sds.ifsd_flags[next]);
3069 } else if (txq->ift_sds.ifsd_map != NULL)
3070 map = txq->ift_sds.ifsd_map[pidx];
3072 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3073 desc_tag = txq->ift_tso_desc_tag;
3074 max_segs = scctx->isc_tx_tso_segments_max;
3076 desc_tag = txq->ift_desc_tag;
3077 max_segs = scctx->isc_tx_nsegments;
3082 pi.ipi_len = m_head->m_pkthdr.len;
3083 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3084 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3085 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3087 pi.ipi_qsidx = txq->ift_id;
3089 /* deliberate bitwise OR to make one condition */
3090 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3091 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3097 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3099 if (__predict_false(err)) {
3102 /* try collapse once and defrag once */
3104 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3106 m_head = m_defrag(*m_headp, M_NOWAIT);
3108 if (__predict_false(m_head == NULL))
3110 txq->ift_mbuf_defrag++;
3115 txq->ift_no_tx_dma_setup++;
3118 txq->ift_no_tx_dma_setup++;
3120 DBG_COUNTER_INC(tx_frees);
3124 txq->ift_map_failed++;
3125 DBG_COUNTER_INC(encap_load_mbuf_fail);
3130 * XXX assumes a 1 to 1 relationship between segments and
3131 * descriptors - this does not hold true on all drivers, e.g.
3134 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3135 txq->ift_no_desc_avail++;
3137 bus_dmamap_unload(desc_tag, map);
3138 DBG_COUNTER_INC(encap_txq_avail_fail);
3139 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3140 GROUPTASK_ENQUEUE(&txq->ift_task);
3144 * On Intel cards we can greatly reduce the number of TX interrupts
3145 * we see by only setting report status on every Nth descriptor.
3146 * However, this also means that the driver will need to keep track
3147 * of the descriptors that RS was set on to check them for the DD bit.
3149 txq->ift_rs_pending += nsegs + 1;
3150 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3151 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3152 pi.ipi_flags |= IPI_TX_INTR;
3153 txq->ift_rs_pending = 0;
3157 pi.ipi_nsegs = nsegs;
3159 MPASS(pidx >= 0 && pidx < txq->ift_size);
3164 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3165 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3167 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3169 DBG_COUNTER_INC(tx_encap);
3170 MPASS(pi.ipi_new_pidx < txq->ift_size);
3172 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3173 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3174 ndesc += txq->ift_size;
3178 * drivers can need as many as
3181 MPASS(ndesc <= pi.ipi_nsegs + 2);
3182 MPASS(pi.ipi_new_pidx != pidx);
3184 txq->ift_in_use += ndesc;
3187 * We update the last software descriptor again here because there may
3188 * be a sentinel and/or there may be more mbufs than segments
3190 txq->ift_pidx = pi.ipi_new_pidx;
3191 txq->ift_npending += pi.ipi_ndescs;
3192 } else if (__predict_false(err == EFBIG && remap < 2)) {
3193 *m_headp = m_head = iflib_remove_mbuf(txq);
3195 txq->ift_txd_encap_efbig++;
3198 DBG_COUNTER_INC(encap_txd_encap_fail);
3202 txq->ift_mbuf_defrag_failed++;
3203 txq->ift_map_failed++;
3205 DBG_COUNTER_INC(tx_frees);
3211 iflib_tx_desc_free(iflib_txq_t txq, int n)
3214 uint32_t qsize, cidx, mask, gen;
3215 struct mbuf *m, **ifsd_m;
3216 uint8_t *ifsd_flags;
3217 bus_dmamap_t *ifsd_map;
3220 cidx = txq->ift_cidx;
3222 qsize = txq->ift_size;
3224 hasmap = txq->ift_sds.ifsd_map != NULL;
3225 ifsd_flags = txq->ift_sds.ifsd_flags;
3226 ifsd_m = txq->ift_sds.ifsd_m;
3227 ifsd_map = txq->ift_sds.ifsd_map;
3228 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3232 prefetch(ifsd_m[(cidx + 3) & mask]);
3233 prefetch(ifsd_m[(cidx + 4) & mask]);
3235 if (ifsd_m[cidx] != NULL) {
3236 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3237 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3238 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3240 * does it matter if it's not the TSO tag? If so we'll
3241 * have to add the type to flags
3243 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3244 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3246 if ((m = ifsd_m[cidx]) != NULL) {
3247 /* XXX we don't support any drivers that batch packets yet */
3248 MPASS(m->m_nextpkt == NULL);
3249 /* if the number of clusters exceeds the number of segments
3250 * there won't be space on the ring to save a pointer to each
3251 * cluster so we simply free the list here
3253 if (m->m_flags & M_TOOBIG) {
3258 ifsd_m[cidx] = NULL;
3260 txq->ift_dequeued++;
3262 DBG_COUNTER_INC(tx_frees);
3265 if (__predict_false(++cidx == qsize)) {
3270 txq->ift_cidx = cidx;
3275 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3278 if_ctx_t ctx = txq->ift_ctx;
3280 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3281 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3284 * Need a rate-limiting check so that this isn't called every time
3286 iflib_tx_credits_update(ctx, txq);
3287 reclaim = DESC_RECLAIMABLE(txq);
3289 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3291 if (iflib_verbose_debug) {
3292 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3293 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3300 iflib_tx_desc_free(txq, reclaim);
3301 txq->ift_cleaned += reclaim;
3302 txq->ift_in_use -= reclaim;
3307 static struct mbuf **
3308 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3311 struct mbuf **items;
3314 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3315 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3317 prefetch(items[(cidx + offset) & (size-1)]);
3318 if (remaining > 1) {
3319 prefetch(&items[next]);
3320 prefetch(items[(cidx + offset + 1) & (size-1)]);
3321 prefetch(items[(cidx + offset + 2) & (size-1)]);
3322 prefetch(items[(cidx + offset + 3) & (size-1)]);
3324 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3328 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3331 ifmp_ring_check_drainage(txq->ift_br, budget);
3335 iflib_txq_can_drain(struct ifmp_ring *r)
3337 iflib_txq_t txq = r->cookie;
3338 if_ctx_t ctx = txq->ift_ctx;
3340 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3341 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3345 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3347 iflib_txq_t txq = r->cookie;
3348 if_ctx_t ctx = txq->ift_ctx;
3349 struct ifnet *ifp = ctx->ifc_ifp;
3350 struct mbuf **mp, *m;
3351 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3352 int reclaimed, err, in_use_prev, desc_used;
3353 bool do_prefetch, ring, rang;
3355 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3356 !LINK_ACTIVE(ctx))) {
3357 DBG_COUNTER_INC(txq_drain_notready);
3360 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3361 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3362 avail = IDXDIFF(pidx, cidx, r->size);
3363 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3364 DBG_COUNTER_INC(txq_drain_flushing);
3365 for (i = 0; i < avail; i++) {
3366 m_free(r->items[(cidx + i) & (r->size-1)]);
3367 r->items[(cidx + i) & (r->size-1)] = NULL;
3372 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3373 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3375 callout_stop(&txq->ift_timer);
3376 CALLOUT_UNLOCK(txq);
3377 DBG_COUNTER_INC(txq_drain_oactive);
3381 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3382 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3383 count = MIN(avail, TX_BATCH_SIZE);
3385 if (iflib_verbose_debug)
3386 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3387 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3389 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3390 avail = TXQ_AVAIL(txq);
3391 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3392 int pidx_prev, rem = do_prefetch ? count - i : 0;
3394 mp = _ring_peek_one(r, cidx, i, rem);
3395 MPASS(mp != NULL && *mp != NULL);
3396 if (__predict_false(*mp == (struct mbuf *)txq)) {
3401 in_use_prev = txq->ift_in_use;
3402 pidx_prev = txq->ift_pidx;
3403 err = iflib_encap(txq, mp);
3404 if (__predict_false(err)) {
3405 DBG_COUNTER_INC(txq_drain_encapfail);
3406 /* no room - bail out */
3410 DBG_COUNTER_INC(txq_drain_encapfail);
3411 /* we can't send this packet - skip it */
3417 DBG_COUNTER_INC(tx_sent);
3418 bytes_sent += m->m_pkthdr.len;
3419 mcast_sent += !!(m->m_flags & M_MCAST);
3420 avail = TXQ_AVAIL(txq);
3422 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3423 desc_used += (txq->ift_in_use - in_use_prev);
3424 ETHER_BPF_MTAP(ifp, m);
3425 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3427 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3430 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3431 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3432 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3433 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3434 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3436 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3438 if (iflib_verbose_debug)
3439 printf("consumed=%d\n", consumed);
3445 iflib_txq_drain_always(struct ifmp_ring *r)
3451 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3459 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3461 callout_stop(&txq->ift_timer);
3462 CALLOUT_UNLOCK(txq);
3464 avail = IDXDIFF(pidx, cidx, r->size);
3465 for (i = 0; i < avail; i++) {
3466 mp = _ring_peek_one(r, cidx, i, avail - i);
3467 if (__predict_false(*mp == (struct mbuf *)txq))
3471 MPASS(ifmp_ring_is_stalled(r) == 0);
3476 iflib_ifmp_purge(iflib_txq_t txq)
3478 struct ifmp_ring *r;
3481 r->drain = iflib_txq_drain_free;
3482 r->can_drain = iflib_txq_drain_always;
3484 ifmp_ring_check_drainage(r, r->size);
3486 r->drain = iflib_txq_drain;
3487 r->can_drain = iflib_txq_can_drain;
3491 _task_fn_tx(void *context)
3493 iflib_txq_t txq = context;
3494 if_ctx_t ctx = txq->ift_ctx;
3495 struct ifnet *ifp = ctx->ifc_ifp;
3498 #ifdef IFLIB_DIAGNOSTICS
3499 txq->ift_cpu_exec_count[curcpu]++;
3501 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3503 if ((ifp->if_capenable & IFCAP_NETMAP)) {
3504 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3505 netmap_tx_irq(ifp, txq->ift_id);
3506 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3509 if (txq->ift_db_pending)
3510 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3512 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3513 if (ctx->ifc_flags & IFC_LEGACY)
3514 IFDI_INTR_ENABLE(ctx);
3516 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3517 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3522 _task_fn_rx(void *context)
3524 iflib_rxq_t rxq = context;
3525 if_ctx_t ctx = rxq->ifr_ctx;
3529 #ifdef IFLIB_DIAGNOSTICS
3530 rxq->ifr_cpu_exec_count[curcpu]++;
3532 DBG_COUNTER_INC(task_fn_rxs);
3533 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3535 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) {
3536 if (ctx->ifc_flags & IFC_LEGACY)
3537 IFDI_INTR_ENABLE(ctx);
3539 DBG_COUNTER_INC(rx_intr_enables);
3540 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3541 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3544 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3547 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3551 _task_fn_admin(void *context)
3553 if_ctx_t ctx = context;
3554 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3558 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) {
3559 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3565 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3567 callout_stop(&txq->ift_timer);
3568 CALLOUT_UNLOCK(txq);
3570 IFDI_UPDATE_ADMIN_STATUS(ctx);
3571 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3572 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3573 IFDI_LINK_INTR_ENABLE(ctx);
3574 if (ctx->ifc_flags & IFC_DO_RESET) {
3575 ctx->ifc_flags &= ~IFC_DO_RESET;
3576 iflib_if_init_locked(ctx);
3580 if (LINK_ACTIVE(ctx) == 0)
3582 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3583 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3588 _task_fn_iov(void *context)
3590 if_ctx_t ctx = context;
3592 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3596 IFDI_VFLR_HANDLE(ctx);
3601 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3604 if_int_delay_info_t info;
3607 info = (if_int_delay_info_t)arg1;
3608 ctx = info->iidi_ctx;
3609 info->iidi_req = req;
3610 info->iidi_oidp = oidp;
3612 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3617 /*********************************************************************
3621 **********************************************************************/
3624 iflib_if_init_locked(if_ctx_t ctx)
3627 iflib_init_locked(ctx);
3632 iflib_if_init(void *arg)
3637 iflib_if_init_locked(ctx);
3642 iflib_if_transmit(if_t ifp, struct mbuf *m)
3644 if_ctx_t ctx = if_getsoftc(ifp);
3649 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3650 DBG_COUNTER_INC(tx_frees);
3655 MPASS(m->m_nextpkt == NULL);
3657 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3658 qidx = QIDX(ctx, m);
3660 * XXX calculate buf_ring based on flowid (divvy up bits?)
3662 txq = &ctx->ifc_txqs[qidx];
3664 #ifdef DRIVER_BACKPRESSURE
3665 if (txq->ift_closed) {
3667 next = m->m_nextpkt;
3668 m->m_nextpkt = NULL;
3681 next = next->m_nextpkt;
3682 } while (next != NULL);
3684 if (count > nitems(marr))
3685 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3686 /* XXX check nextpkt */
3688 /* XXX simplify for now */
3689 DBG_COUNTER_INC(tx_frees);
3692 for (next = m, i = 0; next != NULL; i++) {
3694 next = next->m_nextpkt;
3695 mp[i]->m_nextpkt = NULL;
3698 DBG_COUNTER_INC(tx_seen);
3699 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3702 GROUPTASK_ENQUEUE(&txq->ift_task);
3703 /* support forthcoming later */
3704 #ifdef DRIVER_BACKPRESSURE
3705 txq->ift_closed = TRUE;
3707 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3709 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) {
3710 GROUPTASK_ENQUEUE(&txq->ift_task);
3717 iflib_if_qflush(if_t ifp)
3719 if_ctx_t ctx = if_getsoftc(ifp);
3720 iflib_txq_t txq = ctx->ifc_txqs;
3724 ctx->ifc_flags |= IFC_QFLUSH;
3726 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3727 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3728 iflib_txq_check_drain(txq, 0);
3730 ctx->ifc_flags &= ~IFC_QFLUSH;
3737 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3738 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3739 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3742 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3744 if_ctx_t ctx = if_getsoftc(ifp);
3745 struct ifreq *ifr = (struct ifreq *)data;
3746 #if defined(INET) || defined(INET6)
3747 struct ifaddr *ifa = (struct ifaddr *)data;
3749 bool avoid_reset = FALSE;
3750 int err = 0, reinit = 0, bits;
3755 if (ifa->ifa_addr->sa_family == AF_INET)
3759 if (ifa->ifa_addr->sa_family == AF_INET6)
3763 ** Calling init results in link renegotiation,
3764 ** so we avoid doing it when possible.
3767 if_setflagbits(ifp, IFF_UP,0);
3768 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3771 if (!(if_getflags(ifp) & IFF_NOARP))
3772 arp_ifinit(ifp, ifa);
3775 err = ether_ioctl(ifp, command, data);
3779 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3783 bits = if_getdrvflags(ifp);
3784 /* stop the driver and free any clusters before proceeding */
3787 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3788 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3789 ctx->ifc_flags |= IFC_MULTISEG;
3791 ctx->ifc_flags &= ~IFC_MULTISEG;
3792 err = if_setmtu(ifp, ifr->ifr_mtu);
3794 iflib_init_locked(ctx);
3795 if_setdrvflags(ifp, bits);
3800 if (if_getflags(ifp) & IFF_UP) {
3801 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3802 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3803 (IFF_PROMISC | IFF_ALLMULTI)) {
3804 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3808 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3811 ctx->ifc_if_flags = if_getflags(ifp);
3816 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3818 IFDI_INTR_DISABLE(ctx);
3819 IFDI_MULTI_SET(ctx);
3820 IFDI_INTR_ENABLE(ctx);
3826 IFDI_MEDIA_SET(ctx);
3830 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3834 struct ifi2creq i2c;
3836 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3839 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3843 if (i2c.len > sizeof(i2c.data)) {
3848 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3849 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3856 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3859 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3861 setmask |= (mask & IFCAP_FLAGS);
3863 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
3864 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
3865 if ((mask & IFCAP_WOL) &&
3866 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3867 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3870 * want to ensure that traffic has stopped before we change any of the flags
3874 bits = if_getdrvflags(ifp);
3875 if (bits & IFF_DRV_RUNNING)
3877 if_togglecapenable(ifp, setmask);
3878 if (bits & IFF_DRV_RUNNING)
3879 iflib_init_locked(ctx);
3880 if_setdrvflags(ifp, bits);
3885 case SIOCGPRIVATE_0:
3889 err = IFDI_PRIV_IOCTL(ctx, command, data);
3893 err = ether_ioctl(ifp, command, data);
3902 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3904 if_ctx_t ctx = if_getsoftc(ifp);
3906 return (IFDI_GET_COUNTER(ctx, cnt));
3909 /*********************************************************************
3911 * OTHER FUNCTIONS EXPORTED TO THE STACK
3913 **********************************************************************/
3916 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
3918 if_ctx_t ctx = if_getsoftc(ifp);
3920 if ((void *)ctx != arg)
3923 if ((vtag == 0) || (vtag > 4095))
3927 IFDI_VLAN_REGISTER(ctx, vtag);
3928 /* Re-init to load the changes */
3929 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3930 iflib_init_locked(ctx);
3935 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
3937 if_ctx_t ctx = if_getsoftc(ifp);
3939 if ((void *)ctx != arg)
3942 if ((vtag == 0) || (vtag > 4095))
3946 IFDI_VLAN_UNREGISTER(ctx, vtag);
3947 /* Re-init to load the changes */
3948 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3949 iflib_init_locked(ctx);
3954 iflib_led_func(void *arg, int onoff)
3959 IFDI_LED_FUNC(ctx, onoff);
3963 /*********************************************************************
3965 * BUS FUNCTION DEFINITIONS
3967 **********************************************************************/
3970 iflib_device_probe(device_t dev)
3972 pci_vendor_info_t *ent;
3974 uint16_t pci_vendor_id, pci_device_id;
3975 uint16_t pci_subvendor_id, pci_subdevice_id;
3976 uint16_t pci_rev_id;
3977 if_shared_ctx_t sctx;
3979 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3982 pci_vendor_id = pci_get_vendor(dev);
3983 pci_device_id = pci_get_device(dev);
3984 pci_subvendor_id = pci_get_subvendor(dev);
3985 pci_subdevice_id = pci_get_subdevice(dev);
3986 pci_rev_id = pci_get_revid(dev);
3987 if (sctx->isc_parse_devinfo != NULL)
3988 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
3990 ent = sctx->isc_vendor_info;
3991 while (ent->pvi_vendor_id != 0) {
3992 if (pci_vendor_id != ent->pvi_vendor_id) {
3996 if ((pci_device_id == ent->pvi_device_id) &&
3997 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
3998 (ent->pvi_subvendor_id == 0)) &&
3999 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4000 (ent->pvi_subdevice_id == 0)) &&
4001 ((pci_rev_id == ent->pvi_rev_id) ||
4002 (ent->pvi_rev_id == 0))) {
4004 device_set_desc_copy(dev, ent->pvi_name);
4005 /* this needs to be changed to zero if the bus probing code
4006 * ever stops re-probing on best match because the sctx
4007 * may have its values over written by register calls
4008 * in subsequent probes
4010 return (BUS_PROBE_DEFAULT);
4018 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4020 int err, rid, msix, msix_bar;
4023 if_softc_ctx_t scctx;
4029 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4032 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4033 device_set_softc(dev, ctx);
4034 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4037 ctx->ifc_sctx = sctx;
4039 ctx->ifc_softc = sc;
4041 if ((err = iflib_register(ctx)) != 0) {
4042 device_printf(dev, "iflib_register failed %d\n", err);
4045 iflib_add_device_sysctl_pre(ctx);
4047 scctx = &ctx->ifc_softc_ctx;
4051 * XXX sanity check that ntxd & nrxd are a power of 2
4053 if (ctx->ifc_sysctl_ntxqs != 0)
4054 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4055 if (ctx->ifc_sysctl_nrxqs != 0)
4056 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4058 for (i = 0; i < sctx->isc_ntxqs; i++) {
4059 if (ctx->ifc_sysctl_ntxds[i] != 0)
4060 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4062 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4065 for (i = 0; i < sctx->isc_nrxqs; i++) {
4066 if (ctx->ifc_sysctl_nrxds[i] != 0)
4067 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4069 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4072 for (i = 0; i < sctx->isc_nrxqs; i++) {
4073 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4074 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4075 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4076 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4078 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4079 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4080 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4081 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4085 for (i = 0; i < sctx->isc_ntxqs; i++) {
4086 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4087 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4088 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4089 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4091 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4092 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4093 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4094 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4098 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4099 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4102 _iflib_pre_assert(scctx);
4103 ctx->ifc_txrx = *scctx->isc_txrx;
4106 MPASS(scctx->isc_capenable);
4107 if (scctx->isc_capenable & IFCAP_TXCSUM)
4108 MPASS(scctx->isc_tx_csum_flags);
4111 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4112 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4114 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4115 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4116 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4117 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4120 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4121 ctx->ifc_flags |= IFC_DMAR;
4122 #elif !(defined(__i386__) || defined(__amd64__))
4123 /* set unconditionally for !x86 */
4124 ctx->ifc_flags |= IFC_DMAR;
4127 msix_bar = scctx->isc_msix_bar;
4128 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4129 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4131 /* XXX change for per-queue sizes */
4132 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4133 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4134 for (i = 0; i < sctx->isc_nrxqs; i++) {
4135 if (!powerof2(scctx->isc_nrxd[i])) {
4136 /* round down instead? */
4137 device_printf(dev, "# rx descriptors must be a power of 2\n");
4142 for (i = 0; i < sctx->isc_ntxqs; i++) {
4143 if (!powerof2(scctx->isc_ntxd[i])) {
4145 "# tx descriptors must be a power of 2");
4151 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4152 MAX_SINGLE_PACKET_FRACTION)
4153 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4154 MAX_SINGLE_PACKET_FRACTION);
4155 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4156 MAX_SINGLE_PACKET_FRACTION)
4157 scctx->isc_tx_tso_segments_max = max(1,
4158 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4161 * Protect the stack against modern hardware
4163 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4164 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4166 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4167 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4168 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4169 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4170 if (scctx->isc_rss_table_size == 0)
4171 scctx->isc_rss_table_size = 64;
4172 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4174 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4175 /* XXX format name */
4176 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4178 ** Now setup MSI or MSI/X, should
4179 ** return us the number of supported
4180 ** vectors. (Will be 1 for MSI)
4182 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4183 msix = scctx->isc_vectors;
4184 } else if (scctx->isc_msix_bar != 0)
4186 * The simple fact that isc_msix_bar is not 0 does not mean we
4187 * we have a good value there that is known to work.
4189 msix = iflib_msix_init(ctx);
4191 scctx->isc_vectors = 1;
4192 scctx->isc_ntxqsets = 1;
4193 scctx->isc_nrxqsets = 1;
4194 scctx->isc_intr = IFLIB_INTR_LEGACY;
4197 /* Get memory for the station queues */
4198 if ((err = iflib_queues_alloc(ctx))) {
4199 device_printf(dev, "Unable to allocate queue memory\n");
4203 if ((err = iflib_qset_structures_setup(ctx))) {
4204 device_printf(dev, "qset structure setup failed %d\n", err);
4209 * Group taskqueues aren't properly set up until SMP is started,
4210 * so we disable interrupts until we can handle them post
4213 * XXX: disabling interrupts doesn't actually work, at least for
4214 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4215 * we do null handling and depend on this not causing too large an
4218 IFDI_INTR_DISABLE(ctx);
4219 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4220 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4221 goto fail_intr_free;
4225 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4229 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4230 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4231 goto fail_intr_free;
4234 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4235 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4236 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4239 if ((err = iflib_netmap_attach(ctx))) {
4240 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4245 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4246 iflib_add_device_sysctl_post(ctx);
4247 ctx->ifc_flags |= IFC_INIT_DONE;
4250 ether_ifdetach(ctx->ifc_ifp);
4252 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4253 pci_release_msi(ctx->ifc_dev);
4255 /* XXX free queues */
4262 iflib_device_attach(device_t dev)
4265 if_shared_ctx_t sctx;
4267 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4270 pci_enable_busmaster(dev);
4272 return (iflib_device_register(dev, NULL, sctx, &ctx));
4276 iflib_device_deregister(if_ctx_t ctx)
4278 if_t ifp = ctx->ifc_ifp;
4281 device_t dev = ctx->ifc_dev;
4283 struct taskqgroup *tqg;
4286 /* Make sure VLANS are not using driver */
4287 if (if_vlantrunkinuse(ifp)) {
4288 device_printf(dev,"Vlan in use, detach first\n");
4293 ctx->ifc_in_detach = 1;
4297 /* Unregister VLAN events */
4298 if (ctx->ifc_vlan_attach_event != NULL)
4299 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4300 if (ctx->ifc_vlan_detach_event != NULL)
4301 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4303 iflib_netmap_detach(ifp);
4304 ether_ifdetach(ifp);
4305 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4306 CTX_LOCK_DESTROY(ctx);
4307 if (ctx->ifc_led_dev != NULL)
4308 led_destroy(ctx->ifc_led_dev);
4309 /* XXX drain any dependent tasks */
4310 tqg = qgroup_if_io_tqg;
4311 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4312 callout_drain(&txq->ift_timer);
4313 if (txq->ift_task.gt_uniq != NULL)
4314 taskqgroup_detach(tqg, &txq->ift_task);
4316 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4317 if (rxq->ifr_task.gt_uniq != NULL)
4318 taskqgroup_detach(tqg, &rxq->ifr_task);
4320 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4321 free(fl->ifl_rx_bitmap, M_IFLIB);
4324 tqg = qgroup_if_config_tqg;
4325 if (ctx->ifc_admin_task.gt_uniq != NULL)
4326 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4327 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4328 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4331 device_set_softc(ctx->ifc_dev, NULL);
4332 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4333 pci_release_msi(dev);
4335 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4336 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4338 if (ctx->ifc_msix_mem != NULL) {
4339 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4340 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4341 ctx->ifc_msix_mem = NULL;
4344 bus_generic_detach(dev);
4347 iflib_tx_structures_free(ctx);
4348 iflib_rx_structures_free(ctx);
4349 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4350 free(ctx->ifc_softc, M_IFLIB);
4357 iflib_device_detach(device_t dev)
4359 if_ctx_t ctx = device_get_softc(dev);
4361 return (iflib_device_deregister(ctx));
4365 iflib_device_suspend(device_t dev)
4367 if_ctx_t ctx = device_get_softc(dev);
4373 return bus_generic_suspend(dev);
4376 iflib_device_shutdown(device_t dev)
4378 if_ctx_t ctx = device_get_softc(dev);
4384 return bus_generic_suspend(dev);
4389 iflib_device_resume(device_t dev)
4391 if_ctx_t ctx = device_get_softc(dev);
4392 iflib_txq_t txq = ctx->ifc_txqs;
4396 iflib_init_locked(ctx);
4398 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4399 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4401 return (bus_generic_resume(dev));
4405 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4408 if_ctx_t ctx = device_get_softc(dev);
4411 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4418 iflib_device_iov_uninit(device_t dev)
4420 if_ctx_t ctx = device_get_softc(dev);
4423 IFDI_IOV_UNINIT(ctx);
4428 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4431 if_ctx_t ctx = device_get_softc(dev);
4434 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4440 /*********************************************************************
4442 * MODULE FUNCTION DEFINITIONS
4444 **********************************************************************/
4447 * - Start a fast taskqueue thread for each core
4448 * - Start a taskqueue for control operations
4451 iflib_module_init(void)
4457 iflib_module_event_handler(module_t mod, int what, void *arg)
4463 if ((err = iflib_module_init()) != 0)
4469 return (EOPNOTSUPP);
4475 /*********************************************************************
4477 * PUBLIC FUNCTION DEFINITIONS
4478 * ordered as in iflib.h
4480 **********************************************************************/
4484 _iflib_assert(if_shared_ctx_t sctx)
4486 MPASS(sctx->isc_tx_maxsize);
4487 MPASS(sctx->isc_tx_maxsegsize);
4489 MPASS(sctx->isc_rx_maxsize);
4490 MPASS(sctx->isc_rx_nsegments);
4491 MPASS(sctx->isc_rx_maxsegsize);
4493 MPASS(sctx->isc_nrxd_min[0]);
4494 MPASS(sctx->isc_nrxd_max[0]);
4495 MPASS(sctx->isc_nrxd_default[0]);
4496 MPASS(sctx->isc_ntxd_min[0]);
4497 MPASS(sctx->isc_ntxd_max[0]);
4498 MPASS(sctx->isc_ntxd_default[0]);
4502 _iflib_pre_assert(if_softc_ctx_t scctx)
4505 MPASS(scctx->isc_txrx->ift_txd_encap);
4506 MPASS(scctx->isc_txrx->ift_txd_flush);
4507 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4508 MPASS(scctx->isc_txrx->ift_rxd_available);
4509 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4510 MPASS(scctx->isc_txrx->ift_rxd_refill);
4511 MPASS(scctx->isc_txrx->ift_rxd_flush);
4515 iflib_register(if_ctx_t ctx)
4517 if_shared_ctx_t sctx = ctx->ifc_sctx;
4518 driver_t *driver = sctx->isc_driver;
4519 device_t dev = ctx->ifc_dev;
4522 _iflib_assert(sctx);
4524 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4526 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4528 device_printf(dev, "can not allocate ifnet structure\n");
4533 * Initialize our context's device specific methods
4535 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4536 kobj_class_compile((kobj_class_t) driver);
4539 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4540 if_setsoftc(ifp, ctx);
4541 if_setdev(ifp, dev);
4542 if_setinitfn(ifp, iflib_if_init);
4543 if_setioctlfn(ifp, iflib_if_ioctl);
4544 if_settransmitfn(ifp, iflib_if_transmit);
4545 if_setqflushfn(ifp, iflib_if_qflush);
4546 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4548 ctx->ifc_vlan_attach_event =
4549 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4550 EVENTHANDLER_PRI_FIRST);
4551 ctx->ifc_vlan_detach_event =
4552 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4553 EVENTHANDLER_PRI_FIRST);
4555 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4556 iflib_media_change, iflib_media_status);
4563 iflib_queues_alloc(if_ctx_t ctx)
4565 if_shared_ctx_t sctx = ctx->ifc_sctx;
4566 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4567 device_t dev = ctx->ifc_dev;
4568 int nrxqsets = scctx->isc_nrxqsets;
4569 int ntxqsets = scctx->isc_ntxqsets;
4572 iflib_fl_t fl = NULL;
4573 int i, j, cpu, err, txconf, rxconf;
4574 iflib_dma_info_t ifdip;
4575 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4576 uint32_t *txqsizes = scctx->isc_txqsizes;
4577 uint8_t nrxqs = sctx->isc_nrxqs;
4578 uint8_t ntxqs = sctx->isc_ntxqs;
4579 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4582 struct ifmp_ring **brscp;
4584 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4585 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4591 /* Allocate the TX ring struct memory */
4593 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4594 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4595 device_printf(dev, "Unable to allocate TX ring memory\n");
4600 /* Now allocate the RX */
4602 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4603 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4604 device_printf(dev, "Unable to allocate RX ring memory\n");
4609 ctx->ifc_txqs = txq;
4610 ctx->ifc_rxqs = rxq;
4613 * XXX handle allocation failure
4615 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4616 /* Set up some basics */
4618 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4619 device_printf(dev, "failed to allocate iflib_dma_info\n");
4623 txq->ift_ifdi = ifdip;
4624 for (j = 0; j < ntxqs; j++, ifdip++) {
4625 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4626 device_printf(dev, "Unable to allocate Descriptor memory\n");
4630 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4631 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4635 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4636 txq->ift_br_offset = 1;
4638 txq->ift_br_offset = 0;
4641 txq->ift_timer.c_cpu = cpu;
4643 if (iflib_txsd_alloc(txq)) {
4644 device_printf(dev, "Critical Failure setting up TX buffers\n");
4649 /* Initialize the TX lock */
4650 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4651 device_get_nameunit(dev), txq->ift_id);
4652 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4653 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4655 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4656 device_get_nameunit(dev), txq->ift_id);
4658 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4659 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4661 /* XXX free any allocated rings */
4662 device_printf(dev, "Unable to allocate buf_ring\n");
4667 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4668 /* Set up some basics */
4670 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4671 device_printf(dev, "failed to allocate iflib_dma_info\n");
4676 rxq->ifr_ifdi = ifdip;
4677 /* XXX this needs to be changed if #rx queues != #tx queues */
4678 rxq->ifr_ntxqirq = 1;
4679 rxq->ifr_txqid[0] = i;
4680 for (j = 0; j < nrxqs; j++, ifdip++) {
4681 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4682 device_printf(dev, "Unable to allocate Descriptor memory\n");
4686 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4690 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4691 rxq->ifr_fl_offset = 1;
4693 rxq->ifr_fl_offset = 0;
4695 rxq->ifr_nfl = nfree_lists;
4697 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4698 device_printf(dev, "Unable to allocate free list memory\n");
4703 for (j = 0; j < nfree_lists; j++) {
4704 fl[j].ifl_rxq = rxq;
4706 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4707 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4709 /* Allocate receive buffers for the ring*/
4710 if (iflib_rxsd_alloc(rxq)) {
4712 "Critical Failure setting up receive buffers\n");
4717 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4718 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4722 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4723 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4724 for (i = 0; i < ntxqsets; i++) {
4725 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4727 for (j = 0; j < ntxqs; j++, di++) {
4728 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4729 paddrs[i*ntxqs + j] = di->idi_paddr;
4732 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4733 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4734 iflib_tx_structures_free(ctx);
4735 free(vaddrs, M_IFLIB);
4736 free(paddrs, M_IFLIB);
4739 free(vaddrs, M_IFLIB);
4740 free(paddrs, M_IFLIB);
4743 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4744 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4745 for (i = 0; i < nrxqsets; i++) {
4746 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4748 for (j = 0; j < nrxqs; j++, di++) {
4749 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4750 paddrs[i*nrxqs + j] = di->idi_paddr;
4753 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4754 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4755 iflib_tx_structures_free(ctx);
4756 free(vaddrs, M_IFLIB);
4757 free(paddrs, M_IFLIB);
4760 free(vaddrs, M_IFLIB);
4761 free(paddrs, M_IFLIB);
4765 /* XXX handle allocation failure changes */
4768 if (ctx->ifc_rxqs != NULL)
4769 free(ctx->ifc_rxqs, M_IFLIB);
4770 ctx->ifc_rxqs = NULL;
4771 if (ctx->ifc_txqs != NULL)
4772 free(ctx->ifc_txqs, M_IFLIB);
4773 ctx->ifc_txqs = NULL;
4776 free(brscp, M_IFLIB);
4786 iflib_tx_structures_setup(if_ctx_t ctx)
4788 iflib_txq_t txq = ctx->ifc_txqs;
4791 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4792 iflib_txq_setup(txq);
4798 iflib_tx_structures_free(if_ctx_t ctx)
4800 iflib_txq_t txq = ctx->ifc_txqs;
4803 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4804 iflib_txq_destroy(txq);
4805 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4806 iflib_dma_free(&txq->ift_ifdi[j]);
4808 free(ctx->ifc_txqs, M_IFLIB);
4809 ctx->ifc_txqs = NULL;
4810 IFDI_QUEUES_FREE(ctx);
4813 /*********************************************************************
4815 * Initialize all receive rings.
4817 **********************************************************************/
4819 iflib_rx_structures_setup(if_ctx_t ctx)
4821 iflib_rxq_t rxq = ctx->ifc_rxqs;
4823 #if defined(INET6) || defined(INET)
4827 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4828 #if defined(INET6) || defined(INET)
4829 tcp_lro_free(&rxq->ifr_lc);
4830 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4831 TCP_LRO_ENTRIES, min(1024,
4832 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4833 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4836 rxq->ifr_lro_enabled = TRUE;
4838 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4841 #if defined(INET6) || defined(INET)
4844 * Free RX software descriptors allocated so far, we will only handle
4845 * the rings that completed, the failing case will have
4846 * cleaned up for itself. 'q' failed, so its the terminus.
4848 rxq = ctx->ifc_rxqs;
4849 for (i = 0; i < q; ++i, rxq++) {
4850 iflib_rx_sds_free(rxq);
4851 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4857 /*********************************************************************
4859 * Free all receive rings.
4861 **********************************************************************/
4863 iflib_rx_structures_free(if_ctx_t ctx)
4865 iflib_rxq_t rxq = ctx->ifc_rxqs;
4867 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4868 iflib_rx_sds_free(rxq);
4873 iflib_qset_structures_setup(if_ctx_t ctx)
4877 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4880 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4881 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4882 iflib_tx_structures_free(ctx);
4883 iflib_rx_structures_free(ctx);
4889 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4890 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4893 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4897 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4899 int i, cpuid, eqid, count;
4901 CPU_COPY(&ctx->ifc_cpus, cpus);
4902 count = CPU_COUNT(&ctx->ifc_cpus);
4904 /* clear up to the qid'th bit */
4905 for (i = 0; i < eqid; i++) {
4906 cpuid = CPU_FFS(cpus);
4908 CPU_CLR(cpuid-1, cpus);
4910 cpuid = CPU_FFS(cpus);
4916 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
4917 iflib_intr_type_t type, driver_filter_t *filter,
4918 void *filter_arg, int qid, char *name)
4920 struct grouptask *gtask;
4921 struct taskqgroup *tqg;
4922 iflib_filter_info_t info;
4925 int tqrid, err, cpuid;
4926 driver_filter_t *intr_fast;
4929 info = &ctx->ifc_filter_info;
4933 /* XXX merge tx/rx for netmap? */
4935 q = &ctx->ifc_txqs[qid];
4936 info = &ctx->ifc_txqs[qid].ift_filter_info;
4937 gtask = &ctx->ifc_txqs[qid].ift_task;
4938 tqg = qgroup_if_io_tqg;
4940 intr_fast = iflib_fast_intr;
4941 GROUPTASK_INIT(gtask, 0, fn, q);
4944 q = &ctx->ifc_rxqs[qid];
4945 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4946 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4947 tqg = qgroup_if_io_tqg;
4949 intr_fast = iflib_fast_intr;
4950 GROUPTASK_INIT(gtask, 0, fn, q);
4952 case IFLIB_INTR_RXTX:
4953 q = &ctx->ifc_rxqs[qid];
4954 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4955 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4956 tqg = qgroup_if_io_tqg;
4958 intr_fast = iflib_fast_intr_rxtx;
4959 GROUPTASK_INIT(gtask, 0, fn, q);
4961 case IFLIB_INTR_ADMIN:
4964 info = &ctx->ifc_filter_info;
4965 gtask = &ctx->ifc_admin_task;
4966 tqg = qgroup_if_config_tqg;
4967 fn = _task_fn_admin;
4968 intr_fast = iflib_fast_intr_ctx;
4971 panic("unknown net intr type");
4974 info->ifi_filter = filter;
4975 info->ifi_filter_arg = filter_arg;
4976 info->ifi_task = gtask;
4979 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
4981 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
4984 if (type == IFLIB_INTR_ADMIN)
4988 cpuid = find_nth(ctx, &cpus, qid);
4989 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name);
4991 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4998 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name)
5000 struct grouptask *gtask;
5001 struct taskqgroup *tqg;
5007 q = &ctx->ifc_txqs[qid];
5008 gtask = &ctx->ifc_txqs[qid].ift_task;
5009 tqg = qgroup_if_io_tqg;
5013 q = &ctx->ifc_rxqs[qid];
5014 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5015 tqg = qgroup_if_io_tqg;
5018 case IFLIB_INTR_IOV:
5020 gtask = &ctx->ifc_vflr_task;
5021 tqg = qgroup_if_config_tqg;
5026 panic("unknown net intr type");
5028 GROUPTASK_INIT(gtask, 0, fn, q);
5029 taskqgroup_attach(tqg, gtask, q, rid, name);
5033 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5036 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5039 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5043 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5045 iflib_txq_t txq = ctx->ifc_txqs;
5046 iflib_rxq_t rxq = ctx->ifc_rxqs;
5047 if_irq_t irq = &ctx->ifc_legacy_irq;
5048 iflib_filter_info_t info;
5049 struct grouptask *gtask;
5050 struct taskqgroup *tqg;
5056 q = &ctx->ifc_rxqs[0];
5057 info = &rxq[0].ifr_filter_info;
5058 gtask = &rxq[0].ifr_task;
5059 tqg = qgroup_if_io_tqg;
5060 tqrid = irq->ii_rid = *rid;
5063 ctx->ifc_flags |= IFC_LEGACY;
5064 info->ifi_filter = filter;
5065 info->ifi_filter_arg = filter_arg;
5066 info->ifi_task = gtask;
5067 info->ifi_ctx = ctx;
5069 /* We allocate a single interrupt resource */
5070 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5072 GROUPTASK_INIT(gtask, 0, fn, q);
5073 taskqgroup_attach(tqg, gtask, q, tqrid, name);
5075 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5076 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx");
5081 iflib_led_create(if_ctx_t ctx)
5084 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5085 device_get_nameunit(ctx->ifc_dev));
5089 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5092 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5096 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5099 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5103 iflib_admin_intr_deferred(if_ctx_t ctx)
5106 struct grouptask *gtask;
5108 gtask = &ctx->ifc_admin_task;
5109 MPASS(gtask->gt_taskqueue != NULL);
5112 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5116 iflib_iov_intr_deferred(if_ctx_t ctx)
5119 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5123 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5126 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5130 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
5134 GROUPTASK_INIT(gtask, 0, fn, ctx);
5135 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5139 iflib_config_gtask_deinit(struct grouptask *gtask)
5142 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5146 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5148 if_t ifp = ctx->ifc_ifp;
5149 iflib_txq_t txq = ctx->ifc_txqs;
5151 if_setbaudrate(ifp, baudrate);
5152 if (baudrate >= IF_Gbps(10))
5153 ctx->ifc_flags |= IFC_PREFETCH;
5155 /* If link down, disable watchdog */
5156 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5157 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5158 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5160 ctx->ifc_link_state = link_state;
5161 if_link_state_change(ifp, link_state);
5165 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5169 int credits_pre = txq->ift_cidx_processed;
5172 if (ctx->isc_txd_credits_update == NULL)
5175 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5178 txq->ift_processed += credits;
5179 txq->ift_cidx_processed += credits;
5181 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5182 if (txq->ift_cidx_processed >= txq->ift_size)
5183 txq->ift_cidx_processed -= txq->ift_size;
5188 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5191 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5196 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5197 const char *description, if_int_delay_info_t info,
5198 int offset, int value)
5200 info->iidi_ctx = ctx;
5201 info->iidi_offset = offset;
5202 info->iidi_value = value;
5203 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5204 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5205 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5206 info, 0, iflib_sysctl_int_delay, "I", description);
5210 iflib_ctx_lock_get(if_ctx_t ctx)
5213 return (&ctx->ifc_mtx);
5217 iflib_msix_init(if_ctx_t ctx)
5219 device_t dev = ctx->ifc_dev;
5220 if_shared_ctx_t sctx = ctx->ifc_sctx;
5221 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5222 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5223 int iflib_num_tx_queues, iflib_num_rx_queues;
5224 int err, admincnt, bar;
5226 iflib_num_tx_queues = scctx->isc_ntxqsets;
5227 iflib_num_rx_queues = scctx->isc_nrxqsets;
5229 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues);
5231 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5232 admincnt = sctx->isc_admin_intrcnt;
5233 /* Override by tuneable */
5234 if (scctx->isc_disable_msix)
5238 ** When used in a virtualized environment
5239 ** PCI BUSMASTER capability may not be set
5240 ** so explicity set it here and rewrite
5241 ** the ENABLE in the MSIX control register
5242 ** at this point to cause the host to
5243 ** successfully initialize us.
5248 pci_enable_busmaster(dev);
5250 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5251 rid += PCIR_MSIX_CTRL;
5252 msix_ctrl = pci_read_config(dev, rid, 2);
5253 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5254 pci_write_config(dev, rid, msix_ctrl, 2);
5256 device_printf(dev, "PCIY_MSIX capability not found; "
5257 "or rid %d == 0.\n", rid);
5263 * bar == -1 => "trust me I know what I'm doing"
5264 * Some drivers are for hardware that is so shoddily
5265 * documented that no one knows which bars are which
5266 * so the developer has to map all bars. This hack
5267 * allows shoddy garbage to use msix in this framework.
5270 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5271 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5272 if (ctx->ifc_msix_mem == NULL) {
5273 /* May not be enabled */
5274 device_printf(dev, "Unable to map MSIX table \n");
5278 /* First try MSI/X */
5279 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5280 device_printf(dev, "System has MSIX disabled \n");
5281 bus_release_resource(dev, SYS_RES_MEMORY,
5282 bar, ctx->ifc_msix_mem);
5283 ctx->ifc_msix_mem = NULL;
5287 /* use only 1 qset in debug mode */
5288 queuemsgs = min(msgs - admincnt, 1);
5290 queuemsgs = msgs - admincnt;
5292 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
5294 queues = imin(queuemsgs, rss_getnumbuckets());
5298 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5299 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5300 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5302 device_printf(dev, "Unable to fetch CPU list\n");
5303 /* Figure out a reasonable auto config value */
5304 queues = min(queuemsgs, mp_ncpus);
5307 /* If we're doing RSS, clamp at the number of RSS buckets */
5308 if (queues > rss_getnumbuckets())
5309 queues = rss_getnumbuckets();
5311 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5312 rx_queues = iflib_num_rx_queues;
5316 * We want this to be all logical CPUs by default
5318 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5319 tx_queues = iflib_num_tx_queues;
5321 tx_queues = mp_ncpus;
5323 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5325 if (tx_queues != rx_queues)
5326 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5327 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5329 tx_queues = min(rx_queues, tx_queues);
5330 rx_queues = min(rx_queues, tx_queues);
5333 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5335 vectors = rx_queues + admincnt;
5336 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5338 "Using MSIX interrupts with %d vectors\n", vectors);
5339 scctx->isc_vectors = vectors;
5340 scctx->isc_nrxqsets = rx_queues;
5341 scctx->isc_ntxqsets = tx_queues;
5342 scctx->isc_intr = IFLIB_INTR_MSIX;
5346 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5349 vectors = pci_msi_count(dev);
5350 scctx->isc_nrxqsets = 1;
5351 scctx->isc_ntxqsets = 1;
5352 scctx->isc_vectors = vectors;
5353 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5354 device_printf(dev,"Using an MSI interrupt\n");
5355 scctx->isc_intr = IFLIB_INTR_MSI;
5357 device_printf(dev,"Using a Legacy interrupt\n");
5358 scctx->isc_intr = IFLIB_INTR_LEGACY;
5364 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5367 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5370 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5372 char *ring_state = "UNKNOWN";
5375 rc = sysctl_wire_old_buffer(req, 0);
5379 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5384 ring_state = ring_states[state[3]];
5386 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5387 state[0], state[1], state[2], ring_state);
5388 rc = sbuf_finish(sb);
5393 enum iflib_ndesc_handler {
5399 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5401 if_ctx_t ctx = (void *)arg1;
5402 enum iflib_ndesc_handler type = arg2;
5403 char buf[256] = {0};
5408 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5412 case IFLIB_NTXD_HANDLER:
5413 ndesc = ctx->ifc_sysctl_ntxds;
5415 nqs = ctx->ifc_sctx->isc_ntxqs;
5417 case IFLIB_NRXD_HANDLER:
5418 ndesc = ctx->ifc_sysctl_nrxds;
5420 nqs = ctx->ifc_sctx->isc_nrxqs;
5426 for (i=0; i<8; i++) {
5431 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5434 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5435 if (rc || req->newptr == NULL)
5438 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5439 i++, p = strsep(&next, " ,")) {
5440 ndesc[i] = strtoul(p, NULL, 10);
5446 #define NAME_BUFLEN 32
5448 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5450 device_t dev = iflib_get_dev(ctx);
5451 struct sysctl_oid_list *child, *oid_list;
5452 struct sysctl_ctx_list *ctx_list;
5453 struct sysctl_oid *node;
5455 ctx_list = device_get_sysctl_ctx(dev);
5456 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5457 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5458 CTLFLAG_RD, NULL, "IFLIB fields");
5459 oid_list = SYSCTL_CHILDREN(node);
5461 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5462 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5465 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5466 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5467 "# of txqs to use, 0 => use default #");
5468 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5469 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5470 "# of rxqs to use, 0 => use default #");
5471 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5472 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5473 "permit #txq != #rxq");
5474 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5475 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5476 "disable MSIX (default 0)");
5478 /* XXX change for per-queue sizes */
5479 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5480 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5481 mp_ndesc_handler, "A",
5482 "list of # of tx descriptors to use, 0 = use default #");
5483 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5484 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5485 mp_ndesc_handler, "A",
5486 "list of # of rx descriptors to use, 0 = use default #");
5490 iflib_add_device_sysctl_post(if_ctx_t ctx)
5492 if_shared_ctx_t sctx = ctx->ifc_sctx;
5493 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5494 device_t dev = iflib_get_dev(ctx);
5495 struct sysctl_oid_list *child;
5496 struct sysctl_ctx_list *ctx_list;
5501 char namebuf[NAME_BUFLEN];
5503 struct sysctl_oid *queue_node, *fl_node, *node;
5504 struct sysctl_oid_list *queue_list, *fl_list;
5505 ctx_list = device_get_sysctl_ctx(dev);
5507 node = ctx->ifc_sysctl_node;
5508 child = SYSCTL_CHILDREN(node);
5510 if (scctx->isc_ntxqsets > 100)
5512 else if (scctx->isc_ntxqsets > 10)
5516 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5517 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5518 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5519 CTLFLAG_RD, NULL, "Queue Name");
5520 queue_list = SYSCTL_CHILDREN(queue_node);
5522 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5524 &txq->ift_dequeued, "total mbufs freed");
5525 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5527 &txq->ift_enqueued, "total mbufs enqueued");
5529 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5531 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5532 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5534 &txq->ift_pullups, "# of times m_pullup was called");
5535 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5537 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5538 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5540 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5541 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5543 &txq->ift_map_failed, "# of times dma map failed");
5544 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5546 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5547 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5549 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5550 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5552 &txq->ift_pidx, 1, "Producer Index");
5553 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5555 &txq->ift_cidx, 1, "Consumer Index");
5556 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5558 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5559 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5561 &txq->ift_in_use, 1, "descriptors in use");
5562 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5564 &txq->ift_processed, "descriptors procesed for clean");
5565 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5567 &txq->ift_cleaned, "total cleaned");
5568 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5569 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5570 0, mp_ring_state_handler, "A", "soft ring state");
5571 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5572 CTLFLAG_RD, &txq->ift_br->enqueues,
5573 "# of enqueues to the mp_ring for this queue");
5574 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5575 CTLFLAG_RD, &txq->ift_br->drops,
5576 "# of drops in the mp_ring for this queue");
5577 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5578 CTLFLAG_RD, &txq->ift_br->starts,
5579 "# of normal consumer starts in the mp_ring for this queue");
5580 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5581 CTLFLAG_RD, &txq->ift_br->stalls,
5582 "# of consumer stalls in the mp_ring for this queue");
5583 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5584 CTLFLAG_RD, &txq->ift_br->restarts,
5585 "# of consumer restarts in the mp_ring for this queue");
5586 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5587 CTLFLAG_RD, &txq->ift_br->abdications,
5588 "# of consumer abdications in the mp_ring for this queue");
5591 if (scctx->isc_nrxqsets > 100)
5593 else if (scctx->isc_nrxqsets > 10)
5597 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5598 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5599 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5600 CTLFLAG_RD, NULL, "Queue Name");
5601 queue_list = SYSCTL_CHILDREN(queue_node);
5602 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5603 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5605 &rxq->ifr_cq_pidx, 1, "Producer Index");
5606 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5608 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5611 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5612 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5613 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5614 CTLFLAG_RD, NULL, "freelist Name");
5615 fl_list = SYSCTL_CHILDREN(fl_node);
5616 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5618 &fl->ifl_pidx, 1, "Producer Index");
5619 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5621 &fl->ifl_cidx, 1, "Consumer Index");
5622 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5624 &fl->ifl_credits, 1, "credits available");
5626 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5628 &fl->ifl_m_enqueued, "mbufs allocated");
5629 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5631 &fl->ifl_m_dequeued, "mbufs freed");
5632 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5634 &fl->ifl_cl_enqueued, "clusters allocated");
5635 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5637 &fl->ifl_cl_dequeued, "clusters freed");
5645 #ifndef __NO_STRICT_ALIGNMENT
5646 static struct mbuf *
5647 iflib_fixup_rx(struct mbuf *m)
5651 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5652 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5653 m->m_data += ETHER_HDR_LEN;
5656 MGETHDR(n, M_NOWAIT, MT_DATA);
5661 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
5662 m->m_data += ETHER_HDR_LEN;
5663 m->m_len -= ETHER_HDR_LEN;
5664 n->m_len = ETHER_HDR_LEN;
5665 M_MOVE_PKTHDR(n, m);