2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 struct ether_addr ifc_mac;
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (ctx->ifc_mediap);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_buf_tag;
357 bus_dma_tag_t ift_tso_buf_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 32
360 char ift_mtx_name[MTX_NAME_LEN];
361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 uint64_t ift_cpu_exec_count[256];
365 } __aligned(CACHE_LINE_SIZE);
372 uint8_t ifl_rxd_size;
374 uint64_t ifl_m_enqueued;
375 uint64_t ifl_m_dequeued;
376 uint64_t ifl_cl_enqueued;
377 uint64_t ifl_cl_dequeued;
380 bitstr_t *ifl_rx_bitmap;
384 uint16_t ifl_buf_size;
387 iflib_rxsd_array_t ifl_sds;
390 bus_dma_tag_t ifl_buf_tag;
391 iflib_dma_info_t ifl_ifdi;
392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the completion queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct callout ifr_watchdog;
438 struct iflib_filter_info ifr_filter_info;
439 iflib_dma_info_t ifr_ifdi;
441 /* dynamically allocate if any drivers need a value substantially larger than this */
442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 uint64_t ifr_cpu_exec_count[256];
446 } __aligned(CACHE_LINE_SIZE);
448 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
708 static void iflib_init_locked(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
710 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
711 static void iflib_ifmp_purge(iflib_txq_t txq);
712 static void _iflib_pre_assert(if_softc_ctx_t scctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 static void iflib_free_intr_mem(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
720 SLIST_HEAD_INITIALIZER(cpu_offsets);
722 SLIST_ENTRY(cpu_offset) entries;
724 unsigned int refcount;
727 static struct mtx cpu_offset_mtx;
728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
731 DEBUGNET_DEFINE(iflib);
734 iflib_num_rx_descs(if_ctx_t ctx)
736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
737 if_shared_ctx_t sctx = ctx->ifc_sctx;
738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
740 return scctx->isc_nrxd[first_rxq];
744 iflib_num_tx_descs(if_ctx_t ctx)
746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
747 if_shared_ctx_t sctx = ctx->ifc_sctx;
748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
750 return scctx->isc_ntxd[first_txq];
754 #include <sys/selinfo.h>
755 #include <net/netmap.h>
756 #include <dev/netmap/netmap_kern.h>
758 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
763 * device-specific sysctl variables:
765 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
766 * During regular operations the CRC is stripped, but on some
767 * hardware reception of frames not multiple of 64 is slower,
768 * so using crcstrip=0 helps in benchmarks.
770 * iflib_rx_miss, iflib_rx_miss_bufs:
771 * count packets that might be missed due to lost interrupts.
773 SYSCTL_DECL(_dev_netmap);
775 * The xl driver by default strips CRCs and we do not override it.
778 int iflib_crcstrip = 1;
779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
780 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
782 int iflib_rx_miss, iflib_rx_miss_bufs;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
784 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
786 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
789 * Register/unregister. We are already under netmap lock.
790 * Only called on the first register or the last unregister.
793 iflib_netmap_register(struct netmap_adapter *na, int onoff)
796 if_ctx_t ctx = ifp->if_softc;
800 IFDI_INTR_DISABLE(ctx);
802 /* Tell the stack that the interface is no longer active */
803 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
811 * Enable (or disable) netmap flags, and intercept (or restore)
812 * ifp->if_transmit. This is done once the device has been stopped
813 * to prevent race conditions.
816 nm_set_native_flags(na);
818 nm_clear_native_flags(na);
821 iflib_init_locked(ctx);
822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
825 nm_clear_native_flags(na);
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
833 struct netmap_adapter *na = kring->na;
834 u_int const lim = kring->nkr_num_slots - 1;
835 u_int head = kring->rhead;
836 u_int nm_i = kring->nr_hwcur;
837 struct netmap_ring *ring = kring->ring;
839 struct if_rxd_update iru;
840 if_ctx_t ctx = rxq->ifr_ctx;
841 iflib_fl_t fl = &rxq->ifr_fl[0];
842 u_int nic_i_first, nic_i;
844 #if IFLIB_DEBUG_COUNTERS
849 * Netmap requires that we leave (at least) one free slot
850 * in the ring, so that it can distinguish between an empty
851 * ring (nr_hwcur == nr_hwtail, i.e. all the buffers owned by the
852 * user) and a full ring (nr_hwtail == (nr_hwcur - 1) mod N, i.e.
853 * all the buffers owned by the kernel).
854 * We thus set head (the refill limit) to nr_hwcur - 1
855 * at initialization. The rest of the code will then make sure
856 * than nr_hwtail never overcomes nr_hwcur.
858 if (__predict_false(init)) {
859 head = nm_prev(nm_i, lim);
860 } else if (nm_i == head) {
861 /* Nothing to do. We can leave early. */
865 iru_init(&iru, rxq, 0 /* flid */);
866 map = fl->ifl_sds.ifsd_map;
867 nic_i = netmap_idx_k2n(kring, nm_i);
868 DBG_COUNTER_INC(fl_refills);
869 while (nm_i != head) {
870 #if IFLIB_DEBUG_COUNTERS
872 DBG_COUNTER_INC(fl_refills_large);
875 for (i = 0; i < IFLIB_MAX_RX_REFRESH && nm_i != head; i++) {
876 struct netmap_slot *slot = &ring->slot[nm_i];
877 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
879 MPASS(i < IFLIB_MAX_RX_REFRESH);
881 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
882 return netmap_ring_reinit(kring);
884 fl->ifl_rxd_idxs[i] = nic_i;
886 if (__predict_false(init)) {
887 netmap_load_map(na, fl->ifl_buf_tag,
889 } else if (slot->flags & NS_BUF_CHANGED) {
890 /* buffer has changed, reload map */
891 netmap_reload_map(na, fl->ifl_buf_tag,
894 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
895 BUS_DMASYNC_PREREAD);
896 slot->flags &= ~NS_BUF_CHANGED;
898 nm_i = nm_next(nm_i, lim);
899 nic_i = nm_next(nic_i, lim);
902 iru.iru_pidx = nic_i_first;
904 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
906 kring->nr_hwcur = head;
908 /* The pidx argument of isc_rxd_flush() is the index of the last valid
909 * slot in the free list ring. We need therefore to decrement nic_i,
910 * similarly to what happens in iflib_fl_refill() for ifl_pidx. */
911 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
913 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
914 nm_prev(nic_i, lim));
915 DBG_COUNTER_INC(rxd_flush);
921 * Reconcile kernel and user view of the transmit ring.
923 * All information is in the kring.
924 * Userspace wants to send packets up to the one before kring->rhead,
925 * kernel knows kring->nr_hwcur is the first unsent packet.
927 * Here we push packets out (as many as possible), and possibly
928 * reclaim buffers from previously completed transmission.
930 * The caller (netmap) guarantees that there is only one instance
931 * running at any time. Any interference with other driver
932 * methods should be handled by the individual drivers.
935 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
937 struct netmap_adapter *na = kring->na;
939 struct netmap_ring *ring = kring->ring;
940 u_int nm_i; /* index into the netmap kring */
941 u_int nic_i; /* index into the NIC ring */
943 u_int const lim = kring->nkr_num_slots - 1;
944 u_int const head = kring->rhead;
945 struct if_pkt_info pi;
948 * interrupts on every tx packet are expensive so request
949 * them every half ring, or where NS_REPORT is set
951 u_int report_frequency = kring->nkr_num_slots >> 1;
952 /* device-specific */
953 if_ctx_t ctx = ifp->if_softc;
954 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
956 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
957 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
960 * First part: process new packets to send.
961 * nm_i is the current index in the netmap kring,
962 * nic_i is the corresponding index in the NIC ring.
964 * If we have packets to send (nm_i != head)
965 * iterate over the netmap ring, fetch length and update
966 * the corresponding slot in the NIC ring. Some drivers also
967 * need to update the buffer's physical address in the NIC slot
968 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
970 * The netmap_reload_map() calls is especially expensive,
971 * even when (as in this case) the tag is 0, so do only
972 * when the buffer has actually changed.
974 * If possible do not set the report/intr bit on all slots,
975 * but only a few times per ring or when NS_REPORT is set.
977 * Finally, on 10G and faster drivers, it might be useful
978 * to prefetch the next slot and txr entry.
981 nm_i = kring->nr_hwcur;
982 if (nm_i != head) { /* we have new packets to send */
984 pi.ipi_segs = txq->ift_segs;
985 pi.ipi_qsidx = kring->ring_id;
986 nic_i = netmap_idx_k2n(kring, nm_i);
988 __builtin_prefetch(&ring->slot[nm_i]);
989 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
990 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
992 for (n = 0; nm_i != head; n++) {
993 struct netmap_slot *slot = &ring->slot[nm_i];
994 u_int len = slot->len;
996 void *addr = PNMB(na, slot, &paddr);
997 int flags = (slot->flags & NS_REPORT ||
998 nic_i == 0 || nic_i == report_frequency) ?
1001 /* device-specific */
1003 pi.ipi_segs[0].ds_addr = paddr;
1004 pi.ipi_segs[0].ds_len = len;
1007 pi.ipi_pidx = nic_i;
1008 pi.ipi_flags = flags;
1010 /* Fill the slot in the NIC ring. */
1011 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1012 DBG_COUNTER_INC(tx_encap);
1014 /* prefetch for next round */
1015 __builtin_prefetch(&ring->slot[nm_i + 1]);
1016 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1017 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1019 NM_CHECK_ADDR_LEN(na, addr, len);
1021 if (slot->flags & NS_BUF_CHANGED) {
1022 /* buffer has changed, reload map */
1023 netmap_reload_map(na, txq->ift_buf_tag,
1024 txq->ift_sds.ifsd_map[nic_i], addr);
1026 /* make sure changes to the buffer are synced */
1027 bus_dmamap_sync(txq->ift_buf_tag,
1028 txq->ift_sds.ifsd_map[nic_i],
1029 BUS_DMASYNC_PREWRITE);
1031 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1032 nm_i = nm_next(nm_i, lim);
1033 nic_i = nm_next(nic_i, lim);
1035 kring->nr_hwcur = nm_i;
1037 /* synchronize the NIC ring */
1038 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1039 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1041 /* (re)start the tx unit up to slot nic_i (excluded) */
1042 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1046 * Second part: reclaim buffers for completed transmissions.
1048 * If there are unclaimed buffers, attempt to reclaim them.
1049 * If none are reclaimed, and TX IRQs are not in use, do an initial
1050 * minimal delay, then trigger the tx handler which will spin in the
1053 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1054 if (iflib_tx_credits_update(ctx, txq)) {
1055 /* some tx completed, increment avail */
1056 nic_i = txq->ift_cidx_processed;
1057 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1060 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1061 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1062 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1063 iflib_timer, txq, txq->ift_timer.c_cpu);
1069 * Reconcile kernel and user view of the receive ring.
1070 * Same as for the txsync, this routine must be efficient.
1071 * The caller guarantees a single invocations, but races against
1072 * the rest of the driver should be handled here.
1074 * On call, kring->rhead is the first packet that userspace wants
1075 * to keep, and kring->rcur is the wakeup point.
1076 * The kernel has previously reported packets up to kring->rtail.
1078 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1079 * of whether or not we received an interrupt.
1082 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1084 struct netmap_adapter *na = kring->na;
1085 struct netmap_ring *ring = kring->ring;
1087 uint32_t nm_i; /* index into the netmap ring */
1088 uint32_t nic_i; /* index into the NIC ring */
1090 u_int const lim = kring->nkr_num_slots - 1;
1091 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1093 if_ctx_t ctx = ifp->if_softc;
1094 if_shared_ctx_t sctx = ctx->ifc_sctx;
1095 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1096 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1097 iflib_fl_t fl = &rxq->ifr_fl[0];
1098 struct if_rxd_info ri;
1102 * netmap only uses free list 0, to avoid out of order consumption
1103 * of receive buffers
1106 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1107 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1110 * First part: import newly received packets.
1112 * nm_i is the index of the next free slot in the netmap ring,
1113 * nic_i is the index of the next received packet in the NIC ring
1114 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1115 * differ in case if_init() has been called while
1116 * in netmap mode. For the receive ring we have
1118 * nic_i = fl->ifl_cidx;
1119 * nm_i = kring->nr_hwtail (previous)
1121 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1123 * fl->ifl_cidx is set to 0 on a ring reinit
1125 if (netmap_no_pendintr || force_update) {
1126 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1127 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1128 int crclen = iflib_crcstrip ? 0 : 4;
1132 * For the free list consumer index, we use the same
1133 * logic as in iflib_rxeof().
1136 cidxp = &rxq->ifr_cq_cidx;
1138 cidxp = &fl->ifl_cidx;
1139 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1140 rxq->ifr_id, *cidxp, USHRT_MAX);
1142 nic_i = fl->ifl_cidx;
1143 nm_i = netmap_idx_n2k(kring, nic_i);
1144 MPASS(nm_i == kring->nr_hwtail);
1145 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1147 ri.iri_frags = rxq->ifr_frags;
1148 ri.iri_qsidx = kring->ring_id;
1149 ri.iri_ifp = ctx->ifc_ifp;
1150 ri.iri_cidx = *cidxp;
1152 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1153 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1154 ring->slot[nm_i].flags = 0;
1156 *cidxp = ri.iri_cidx;
1157 while (*cidxp >= scctx->isc_nrxd[0])
1158 *cidxp -= scctx->isc_nrxd[0];
1160 bus_dmamap_sync(fl->ifl_buf_tag,
1161 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1162 nm_i = nm_next(nm_i, lim);
1163 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1165 if (n) { /* update the state variables */
1166 if (netmap_no_pendintr && !force_update) {
1169 iflib_rx_miss_bufs += n;
1171 kring->nr_hwtail = nm_i;
1173 kring->nr_kflags &= ~NKR_PENDINTR;
1176 * Second part: skip past packets that userspace has released.
1177 * (kring->nr_hwcur to head excluded),
1178 * and make the buffers available for reception.
1179 * As usual nm_i is the index in the netmap ring,
1180 * nic_i is the index in the NIC ring, and
1181 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1183 netmap_fl_refill(rxq, kring, false);
1189 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1191 if_ctx_t ctx = na->ifp->if_softc;
1195 IFDI_INTR_ENABLE(ctx);
1197 IFDI_INTR_DISABLE(ctx);
1204 iflib_netmap_attach(if_ctx_t ctx)
1206 struct netmap_adapter na;
1208 bzero(&na, sizeof(na));
1210 na.ifp = ctx->ifc_ifp;
1211 na.na_flags = NAF_BDG_MAYSLEEP;
1212 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1213 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1215 na.num_tx_desc = iflib_num_tx_descs(ctx);
1216 na.num_rx_desc = iflib_num_rx_descs(ctx);
1217 na.nm_txsync = iflib_netmap_txsync;
1218 na.nm_rxsync = iflib_netmap_rxsync;
1219 na.nm_register = iflib_netmap_register;
1220 na.nm_intr = iflib_netmap_intr;
1221 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1222 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1223 return (netmap_attach(&na));
1227 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1229 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1230 struct netmap_slot *slot;
1232 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1235 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1238 * In netmap mode, set the map for the packet buffer.
1239 * NOTE: Some drivers (not this one) also need to set
1240 * the physical buffer address in the NIC ring.
1241 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1242 * netmap slot index, si
1244 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1245 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1246 NMB(na, slot + si));
1252 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1254 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1255 struct netmap_kring *kring;
1256 struct netmap_slot *slot;
1258 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1261 kring = na->rx_rings[rxq->ifr_id];
1262 netmap_fl_refill(rxq, kring, true);
1267 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1269 struct netmap_kring *kring;
1272 txqid = txq->ift_id;
1273 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX);
1277 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1278 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1279 BUS_DMASYNC_POSTREAD);
1280 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1281 netmap_tx_irq(ctx->ifc_ifp, txqid);
1282 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1286 *reset_on = hz / 1000;
1291 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1294 #define iflib_netmap_txq_init(ctx, txq) (0)
1295 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1296 #define iflib_netmap_detach(ifp)
1298 #define iflib_netmap_attach(ctx) (0)
1299 #define netmap_rx_irq(ifp, qid, budget) (0)
1300 #define netmap_tx_irq(ifp, qid) do {} while (0)
1301 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1304 #if defined(__i386__) || defined(__amd64__)
1305 static __inline void
1308 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1310 static __inline void
1311 prefetch2cachelines(void *x)
1313 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1314 #if (CACHE_LINE_SIZE < 128)
1315 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1320 #define prefetch2cachelines(x)
1324 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1328 fl = &rxq->ifr_fl[flid];
1329 iru->iru_paddrs = fl->ifl_bus_addrs;
1330 iru->iru_idxs = fl->ifl_rxd_idxs;
1331 iru->iru_qsidx = rxq->ifr_id;
1332 iru->iru_buf_size = fl->ifl_buf_size;
1333 iru->iru_flidx = fl->ifl_id;
1337 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1341 *(bus_addr_t *) arg = segs[0].ds_addr;
1345 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1348 device_t dev = ctx->ifc_dev;
1350 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1351 align, 0, /* alignment, bounds */
1352 BUS_SPACE_MAXADDR, /* lowaddr */
1353 BUS_SPACE_MAXADDR, /* highaddr */
1354 NULL, NULL, /* filter, filterarg */
1357 size, /* maxsegsize */
1358 BUS_DMA_ALLOCNOW, /* flags */
1359 NULL, /* lockfunc */
1364 "%s: bus_dma_tag_create failed: %d\n",
1369 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1370 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1373 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1374 __func__, (uintmax_t)size, err);
1378 dma->idi_paddr = IF_BAD_DMA;
1379 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1380 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1381 if (err || dma->idi_paddr == IF_BAD_DMA) {
1383 "%s: bus_dmamap_load failed: %d\n",
1388 dma->idi_size = size;
1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1394 bus_dma_tag_destroy(dma->idi_tag);
1396 dma->idi_tag = NULL;
1402 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1404 if_shared_ctx_t sctx = ctx->ifc_sctx;
1406 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1408 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1412 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1415 iflib_dma_info_t *dmaiter;
1418 for (i = 0; i < count; i++, dmaiter++) {
1419 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1423 iflib_dma_free_multi(dmalist, i);
1428 iflib_dma_free(iflib_dma_info_t dma)
1430 if (dma->idi_tag == NULL)
1432 if (dma->idi_paddr != IF_BAD_DMA) {
1433 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1435 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1436 dma->idi_paddr = IF_BAD_DMA;
1438 if (dma->idi_vaddr != NULL) {
1439 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1440 dma->idi_vaddr = NULL;
1442 bus_dma_tag_destroy(dma->idi_tag);
1443 dma->idi_tag = NULL;
1447 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1450 iflib_dma_info_t *dmaiter = dmalist;
1452 for (i = 0; i < count; i++, dmaiter++)
1453 iflib_dma_free(*dmaiter);
1457 iflib_fast_intr(void *arg)
1459 iflib_filter_info_t info = arg;
1460 struct grouptask *gtask = info->ifi_task;
1463 DBG_COUNTER_INC(fast_intrs);
1464 if (info->ifi_filter != NULL) {
1465 result = info->ifi_filter(info->ifi_filter_arg);
1466 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1470 GROUPTASK_ENQUEUE(gtask);
1471 return (FILTER_HANDLED);
1475 iflib_fast_intr_rxtx(void *arg)
1477 iflib_filter_info_t info = arg;
1478 struct grouptask *gtask = info->ifi_task;
1480 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1483 int i, cidx, result;
1485 bool intr_enable, intr_legacy;
1487 DBG_COUNTER_INC(fast_intrs);
1488 if (info->ifi_filter != NULL) {
1489 result = info->ifi_filter(info->ifi_filter_arg);
1490 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1495 sc = ctx->ifc_softc;
1496 intr_enable = false;
1497 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1498 MPASS(rxq->ifr_ntxqirq);
1499 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1500 txqid = rxq->ifr_txqid[i];
1501 txq = &ctx->ifc_txqs[txqid];
1502 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1503 BUS_DMASYNC_POSTREAD);
1504 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1508 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1511 GROUPTASK_ENQUEUE(&txq->ift_task);
1513 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1514 cidx = rxq->ifr_cq_cidx;
1516 cidx = rxq->ifr_fl[0].ifl_cidx;
1517 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1518 GROUPTASK_ENQUEUE(gtask);
1523 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1524 DBG_COUNTER_INC(rx_intr_enables);
1527 IFDI_INTR_ENABLE(ctx);
1528 return (FILTER_HANDLED);
1533 iflib_fast_intr_ctx(void *arg)
1535 iflib_filter_info_t info = arg;
1536 struct grouptask *gtask = info->ifi_task;
1539 DBG_COUNTER_INC(fast_intrs);
1540 if (info->ifi_filter != NULL) {
1541 result = info->ifi_filter(info->ifi_filter_arg);
1542 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1546 GROUPTASK_ENQUEUE(gtask);
1547 return (FILTER_HANDLED);
1551 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1552 driver_filter_t filter, driver_intr_t handler, void *arg,
1555 struct resource *res;
1557 device_t dev = ctx->ifc_dev;
1561 if (ctx->ifc_flags & IFC_LEGACY)
1562 flags |= RF_SHAREABLE;
1565 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1568 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1572 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1573 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1574 filter, handler, arg, &tag);
1577 "failed to setup interrupt for rid %d, name %s: %d\n",
1578 rid, name ? name : "unknown", rc);
1581 bus_describe_intr(dev, res, tag, "%s", name);
1587 /*********************************************************************
1589 * Allocate DMA resources for TX buffers as well as memory for the TX
1590 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1591 * iflib_sw_tx_desc_array structure, storing all the information that
1592 * is needed to transmit a packet on the wire. This is called only
1593 * once at attach, setup is done every reset.
1595 **********************************************************************/
1597 iflib_txsd_alloc(iflib_txq_t txq)
1599 if_ctx_t ctx = txq->ift_ctx;
1600 if_shared_ctx_t sctx = ctx->ifc_sctx;
1601 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1602 device_t dev = ctx->ifc_dev;
1603 bus_size_t tsomaxsize;
1604 int err, nsegments, ntsosegments;
1607 nsegments = scctx->isc_tx_nsegments;
1608 ntsosegments = scctx->isc_tx_tso_segments_max;
1609 tsomaxsize = scctx->isc_tx_tso_size_max;
1610 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1611 tsomaxsize += sizeof(struct ether_vlan_header);
1612 MPASS(scctx->isc_ntxd[0] > 0);
1613 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1614 MPASS(nsegments > 0);
1615 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1616 MPASS(ntsosegments > 0);
1617 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1621 * Set up DMA tags for TX buffers.
1623 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1624 1, 0, /* alignment, bounds */
1625 BUS_SPACE_MAXADDR, /* lowaddr */
1626 BUS_SPACE_MAXADDR, /* highaddr */
1627 NULL, NULL, /* filter, filterarg */
1628 sctx->isc_tx_maxsize, /* maxsize */
1629 nsegments, /* nsegments */
1630 sctx->isc_tx_maxsegsize, /* maxsegsize */
1632 NULL, /* lockfunc */
1633 NULL, /* lockfuncarg */
1634 &txq->ift_buf_tag))) {
1635 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1636 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1637 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1640 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1641 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1642 1, 0, /* alignment, bounds */
1643 BUS_SPACE_MAXADDR, /* lowaddr */
1644 BUS_SPACE_MAXADDR, /* highaddr */
1645 NULL, NULL, /* filter, filterarg */
1646 tsomaxsize, /* maxsize */
1647 ntsosegments, /* nsegments */
1648 sctx->isc_tso_maxsegsize,/* maxsegsize */
1650 NULL, /* lockfunc */
1651 NULL, /* lockfuncarg */
1652 &txq->ift_tso_buf_tag))) {
1653 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1658 /* Allocate memory for the TX mbuf map. */
1659 if (!(txq->ift_sds.ifsd_m =
1660 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1661 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1662 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1668 * Create the DMA maps for TX buffers.
1670 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1671 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1672 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1674 "Unable to allocate TX buffer DMA map memory\n");
1678 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1679 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1680 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1682 "Unable to allocate TSO TX buffer map memory\n");
1686 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1687 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1688 &txq->ift_sds.ifsd_map[i]);
1690 device_printf(dev, "Unable to create TX DMA map\n");
1695 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1696 &txq->ift_sds.ifsd_tso_map[i]);
1698 device_printf(dev, "Unable to create TSO TX DMA map\n");
1704 /* We free all, it handles case where we are in the middle */
1705 iflib_tx_structures_free(ctx);
1710 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1714 if (txq->ift_sds.ifsd_map != NULL) {
1715 map = txq->ift_sds.ifsd_map[i];
1716 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1717 bus_dmamap_unload(txq->ift_buf_tag, map);
1718 bus_dmamap_destroy(txq->ift_buf_tag, map);
1719 txq->ift_sds.ifsd_map[i] = NULL;
1722 if (txq->ift_sds.ifsd_tso_map != NULL) {
1723 map = txq->ift_sds.ifsd_tso_map[i];
1724 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1725 BUS_DMASYNC_POSTWRITE);
1726 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1727 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1728 txq->ift_sds.ifsd_tso_map[i] = NULL;
1733 iflib_txq_destroy(iflib_txq_t txq)
1735 if_ctx_t ctx = txq->ift_ctx;
1737 for (int i = 0; i < txq->ift_size; i++)
1738 iflib_txsd_destroy(ctx, txq, i);
1740 if (txq->ift_br != NULL) {
1741 ifmp_ring_free(txq->ift_br);
1745 mtx_destroy(&txq->ift_mtx);
1747 if (txq->ift_sds.ifsd_map != NULL) {
1748 free(txq->ift_sds.ifsd_map, M_IFLIB);
1749 txq->ift_sds.ifsd_map = NULL;
1751 if (txq->ift_sds.ifsd_tso_map != NULL) {
1752 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1753 txq->ift_sds.ifsd_tso_map = NULL;
1755 if (txq->ift_sds.ifsd_m != NULL) {
1756 free(txq->ift_sds.ifsd_m, M_IFLIB);
1757 txq->ift_sds.ifsd_m = NULL;
1759 if (txq->ift_buf_tag != NULL) {
1760 bus_dma_tag_destroy(txq->ift_buf_tag);
1761 txq->ift_buf_tag = NULL;
1763 if (txq->ift_tso_buf_tag != NULL) {
1764 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1765 txq->ift_tso_buf_tag = NULL;
1767 if (txq->ift_ifdi != NULL) {
1768 free(txq->ift_ifdi, M_IFLIB);
1773 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1777 mp = &txq->ift_sds.ifsd_m[i];
1781 if (txq->ift_sds.ifsd_map != NULL) {
1782 bus_dmamap_sync(txq->ift_buf_tag,
1783 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1784 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1786 if (txq->ift_sds.ifsd_tso_map != NULL) {
1787 bus_dmamap_sync(txq->ift_tso_buf_tag,
1788 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1789 bus_dmamap_unload(txq->ift_tso_buf_tag,
1790 txq->ift_sds.ifsd_tso_map[i]);
1793 DBG_COUNTER_INC(tx_frees);
1798 iflib_txq_setup(iflib_txq_t txq)
1800 if_ctx_t ctx = txq->ift_ctx;
1801 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1802 if_shared_ctx_t sctx = ctx->ifc_sctx;
1803 iflib_dma_info_t di;
1806 /* Set number of descriptors available */
1807 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1808 /* XXX make configurable */
1809 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1812 txq->ift_cidx_processed = 0;
1813 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1814 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1816 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1817 bzero((void *)di->idi_vaddr, di->idi_size);
1819 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1820 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1821 bus_dmamap_sync(di->idi_tag, di->idi_map,
1822 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1826 /*********************************************************************
1828 * Allocate DMA resources for RX buffers as well as memory for the RX
1829 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1830 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1831 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1832 * Since we use use one entry in iflib_sw_rx_desc_array per received
1833 * packet, the maximum number of entries we'll need is equal to the
1834 * number of hardware receive descriptors that we've allocated.
1836 **********************************************************************/
1838 iflib_rxsd_alloc(iflib_rxq_t rxq)
1840 if_ctx_t ctx = rxq->ifr_ctx;
1841 if_shared_ctx_t sctx = ctx->ifc_sctx;
1842 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1843 device_t dev = ctx->ifc_dev;
1847 MPASS(scctx->isc_nrxd[0] > 0);
1848 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1851 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1852 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1853 /* Set up DMA tag for RX buffers. */
1854 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1855 1, 0, /* alignment, bounds */
1856 BUS_SPACE_MAXADDR, /* lowaddr */
1857 BUS_SPACE_MAXADDR, /* highaddr */
1858 NULL, NULL, /* filter, filterarg */
1859 sctx->isc_rx_maxsize, /* maxsize */
1860 sctx->isc_rx_nsegments, /* nsegments */
1861 sctx->isc_rx_maxsegsize, /* maxsegsize */
1863 NULL, /* lockfunc */
1868 "Unable to allocate RX DMA tag: %d\n", err);
1872 /* Allocate memory for the RX mbuf map. */
1873 if (!(fl->ifl_sds.ifsd_m =
1874 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1875 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1877 "Unable to allocate RX mbuf map memory\n");
1882 /* Allocate memory for the direct RX cluster pointer map. */
1883 if (!(fl->ifl_sds.ifsd_cl =
1884 (caddr_t *) malloc(sizeof(caddr_t) *
1885 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1887 "Unable to allocate RX cluster map memory\n");
1892 /* Allocate memory for the RX cluster bus address map. */
1893 if (!(fl->ifl_sds.ifsd_ba =
1894 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1895 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1897 "Unable to allocate RX bus address map memory\n");
1903 * Create the DMA maps for RX buffers.
1905 if (!(fl->ifl_sds.ifsd_map =
1906 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1908 "Unable to allocate RX buffer DMA map memory\n");
1912 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1913 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1914 &fl->ifl_sds.ifsd_map[i]);
1916 device_printf(dev, "Unable to create RX buffer DMA map\n");
1924 iflib_rx_structures_free(ctx);
1930 * Internal service routines
1933 struct rxq_refill_cb_arg {
1935 bus_dma_segment_t seg;
1940 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1942 struct rxq_refill_cb_arg *cb_arg = arg;
1944 cb_arg->error = error;
1945 cb_arg->seg = segs[0];
1946 cb_arg->nseg = nseg;
1950 * iflib_fl_refill - refill an rxq free-buffer list
1951 * @ctx: the iflib context
1952 * @fl: the free list to refill
1953 * @count: the number of new buffers to allocate
1955 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1956 * The caller must assure that @count does not exceed the queue's capacity.
1959 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1961 struct if_rxd_update iru;
1962 struct rxq_refill_cb_arg cb_arg;
1966 bus_dmamap_t *sd_map;
1967 bus_addr_t bus_addr, *sd_ba;
1968 int err, frag_idx, i, idx, n, pidx;
1971 sd_m = fl->ifl_sds.ifsd_m;
1972 sd_map = fl->ifl_sds.ifsd_map;
1973 sd_cl = fl->ifl_sds.ifsd_cl;
1974 sd_ba = fl->ifl_sds.ifsd_ba;
1975 pidx = fl->ifl_pidx;
1977 frag_idx = fl->ifl_fragidx;
1978 credits = fl->ifl_credits;
1983 MPASS(credits + n <= fl->ifl_size);
1985 if (pidx < fl->ifl_cidx)
1986 MPASS(pidx + n <= fl->ifl_cidx);
1987 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1988 MPASS(fl->ifl_gen == 0);
1989 if (pidx > fl->ifl_cidx)
1990 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1992 DBG_COUNTER_INC(fl_refills);
1994 DBG_COUNTER_INC(fl_refills_large);
1995 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1998 * We allocate an uninitialized mbuf + cluster, mbuf is
1999 * initialized after rx.
2001 * If the cluster is still set then we know a minimum sized
2002 * packet was received
2004 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2007 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2008 MPASS(frag_idx >= 0);
2009 if ((cl = sd_cl[frag_idx]) == NULL) {
2010 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2011 if (__predict_false(cl == NULL))
2015 MPASS(sd_map != NULL);
2016 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2017 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2019 if (__predict_false(err != 0 || cb_arg.error)) {
2020 uma_zfree(fl->ifl_zone, cl);
2024 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2025 sd_cl[frag_idx] = cl;
2027 fl->ifl_cl_enqueued++;
2030 bus_addr = sd_ba[frag_idx];
2032 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2033 BUS_DMASYNC_PREREAD);
2035 if (sd_m[frag_idx] == NULL) {
2036 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2037 if (__predict_false(m == NULL))
2041 bit_set(fl->ifl_rx_bitmap, frag_idx);
2043 fl->ifl_m_enqueued++;
2046 DBG_COUNTER_INC(rx_allocs);
2047 fl->ifl_rxd_idxs[i] = frag_idx;
2048 fl->ifl_bus_addrs[i] = bus_addr;
2051 MPASS(credits <= fl->ifl_size);
2052 if (++idx == fl->ifl_size) {
2058 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2059 iru.iru_pidx = pidx;
2061 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2063 fl->ifl_credits = credits;
2069 if (n < count - 1) {
2071 iru.iru_pidx = pidx;
2073 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2075 fl->ifl_credits = credits;
2077 DBG_COUNTER_INC(rxd_flush);
2078 if (fl->ifl_pidx == 0)
2079 pidx = fl->ifl_size - 1;
2081 pidx = fl->ifl_pidx - 1;
2083 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2085 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2087 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2088 fl->ifl_fragidx = frag_idx + 1;
2089 if (fl->ifl_fragidx == fl->ifl_size)
2090 fl->ifl_fragidx = 0;
2092 fl->ifl_fragidx = frag_idx;
2096 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2099 static inline uint8_t
2100 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2102 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2103 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2105 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2108 MPASS(fl->ifl_credits <= fl->ifl_size);
2109 MPASS(reclaimable == delta);
2111 if (reclaimable > 0)
2112 return (iflib_fl_refill(ctx, fl, reclaimable));
2117 iflib_in_detach(if_ctx_t ctx)
2122 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2128 iflib_fl_bufs_free(iflib_fl_t fl)
2130 iflib_dma_info_t idi = fl->ifl_ifdi;
2131 bus_dmamap_t sd_map;
2134 for (i = 0; i < fl->ifl_size; i++) {
2135 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2136 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2138 if (*sd_cl != NULL) {
2139 sd_map = fl->ifl_sds.ifsd_map[i];
2140 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2141 BUS_DMASYNC_POSTREAD);
2142 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2143 uma_zfree(fl->ifl_zone, *sd_cl);
2145 if (*sd_m != NULL) {
2146 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2147 uma_zfree(zone_mbuf, *sd_m);
2151 MPASS(*sd_m == NULL);
2154 fl->ifl_m_dequeued++;
2155 fl->ifl_cl_dequeued++;
2159 for (i = 0; i < fl->ifl_size; i++) {
2160 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2161 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2165 * Reset free list values
2167 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2168 bzero(idi->idi_vaddr, idi->idi_size);
2171 /*********************************************************************
2173 * Initialize a free list and its buffers.
2175 **********************************************************************/
2177 iflib_fl_setup(iflib_fl_t fl)
2179 iflib_rxq_t rxq = fl->ifl_rxq;
2180 if_ctx_t ctx = rxq->ifr_ctx;
2181 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2184 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2186 ** Free current RX buffer structs and their mbufs
2188 iflib_fl_bufs_free(fl);
2189 /* Now replenish the mbufs */
2190 MPASS(fl->ifl_credits == 0);
2191 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2192 if (scctx->isc_rxd_buf_size[qidx] != 0)
2193 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2195 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2197 * ifl_buf_size may be a driver-supplied value, so pull it up
2198 * to the selected mbuf size.
2200 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2201 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2202 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2203 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2204 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2207 /* avoid pre-allocating zillions of clusters to an idle card
2208 * potentially speeding up attach
2210 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2211 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2212 if (min(128, fl->ifl_size) != fl->ifl_credits)
2218 MPASS(fl->ifl_ifdi != NULL);
2219 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2220 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2224 /*********************************************************************
2226 * Free receive ring data structures
2228 **********************************************************************/
2230 iflib_rx_sds_free(iflib_rxq_t rxq)
2235 if (rxq->ifr_fl != NULL) {
2236 for (i = 0; i < rxq->ifr_nfl; i++) {
2237 fl = &rxq->ifr_fl[i];
2238 if (fl->ifl_buf_tag != NULL) {
2239 if (fl->ifl_sds.ifsd_map != NULL) {
2240 for (j = 0; j < fl->ifl_size; j++) {
2243 fl->ifl_sds.ifsd_map[j],
2244 BUS_DMASYNC_POSTREAD);
2247 fl->ifl_sds.ifsd_map[j]);
2250 fl->ifl_sds.ifsd_map[j]);
2253 bus_dma_tag_destroy(fl->ifl_buf_tag);
2254 fl->ifl_buf_tag = NULL;
2256 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2257 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2258 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2259 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2260 fl->ifl_sds.ifsd_m = NULL;
2261 fl->ifl_sds.ifsd_cl = NULL;
2262 fl->ifl_sds.ifsd_ba = NULL;
2263 fl->ifl_sds.ifsd_map = NULL;
2265 free(rxq->ifr_fl, M_IFLIB);
2267 free(rxq->ifr_ifdi, M_IFLIB);
2268 rxq->ifr_ifdi = NULL;
2269 rxq->ifr_cq_cidx = 0;
2277 iflib_timer(void *arg)
2279 iflib_txq_t txq = arg;
2280 if_ctx_t ctx = txq->ift_ctx;
2281 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2282 uint64_t this_tick = ticks;
2283 uint32_t reset_on = hz / 2;
2285 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2289 ** Check on the state of the TX queue(s), this
2290 ** can be done without the lock because its RO
2291 ** and the HUNG state will be static if set.
2293 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2294 txq->ift_last_timer_tick = this_tick;
2295 IFDI_TIMER(ctx, txq->ift_id);
2296 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2297 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2298 (sctx->isc_pause_frames == 0)))
2301 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2302 ifmp_ring_is_stalled(txq->ift_br)) {
2303 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2304 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2306 txq->ift_cleaned_prev = txq->ift_cleaned;
2309 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2310 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2312 /* handle any laggards */
2313 if (txq->ift_db_pending)
2314 GROUPTASK_ENQUEUE(&txq->ift_task);
2316 sctx->isc_pause_frames = 0;
2317 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2318 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2322 device_printf(ctx->ifc_dev,
2323 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2324 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2326 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2327 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2328 iflib_admin_intr_deferred(ctx);
2333 iflib_get_mbuf_size_for(unsigned int size)
2336 if (size <= MCLBYTES)
2339 return (MJUMPAGESIZE);
2343 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2345 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2348 * XXX don't set the max_frame_size to larger
2349 * than the hardware can handle
2351 ctx->ifc_rx_mbuf_sz =
2352 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2356 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2359 return (ctx->ifc_rx_mbuf_sz);
2363 iflib_init_locked(if_ctx_t ctx)
2365 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2366 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2367 if_t ifp = ctx->ifc_ifp;
2371 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2373 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2374 IFDI_INTR_DISABLE(ctx);
2376 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2377 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2378 /* Set hardware offload abilities */
2379 if_clearhwassist(ifp);
2380 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2381 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2382 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2383 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2384 if (if_getcapenable(ifp) & IFCAP_TSO4)
2385 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2386 if (if_getcapenable(ifp) & IFCAP_TSO6)
2387 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2389 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2391 callout_stop(&txq->ift_timer);
2392 CALLOUT_UNLOCK(txq);
2393 iflib_netmap_txq_init(ctx, txq);
2397 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2398 * that drivers can use the value when setting up the hardware receive
2401 iflib_calc_rx_mbuf_sz(ctx);
2404 i = if_getdrvflags(ifp);
2407 MPASS(if_getdrvflags(ifp) == i);
2408 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2409 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2410 /* This rxq is in netmap mode. Skip normal init. */
2413 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2414 if (iflib_fl_setup(fl)) {
2415 device_printf(ctx->ifc_dev,
2416 "setting up free list %d failed - "
2417 "check cluster settings\n", j);
2423 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2424 IFDI_INTR_ENABLE(ctx);
2425 txq = ctx->ifc_txqs;
2426 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2427 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2428 txq->ift_timer.c_cpu);
2432 iflib_media_change(if_t ifp)
2434 if_ctx_t ctx = if_getsoftc(ifp);
2438 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2439 iflib_init_locked(ctx);
2445 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2447 if_ctx_t ctx = if_getsoftc(ifp);
2450 IFDI_UPDATE_ADMIN_STATUS(ctx);
2451 IFDI_MEDIA_STATUS(ctx, ifmr);
2456 iflib_stop(if_ctx_t ctx)
2458 iflib_txq_t txq = ctx->ifc_txqs;
2459 iflib_rxq_t rxq = ctx->ifc_rxqs;
2460 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2461 if_shared_ctx_t sctx = ctx->ifc_sctx;
2462 iflib_dma_info_t di;
2466 /* Tell the stack that the interface is no longer active */
2467 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2469 IFDI_INTR_DISABLE(ctx);
2474 iflib_debug_reset();
2475 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2476 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2477 /* make sure all transmitters have completed before proceeding XXX */
2480 callout_stop(&txq->ift_timer);
2481 CALLOUT_UNLOCK(txq);
2483 /* clean any enqueued buffers */
2484 iflib_ifmp_purge(txq);
2485 /* Free any existing tx buffers. */
2486 for (j = 0; j < txq->ift_size; j++) {
2487 iflib_txsd_free(ctx, txq, j);
2489 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2490 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2491 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2492 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2493 txq->ift_pullups = 0;
2494 ifmp_ring_reset_stats(txq->ift_br);
2495 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2496 bzero((void *)di->idi_vaddr, di->idi_size);
2498 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2499 /* make sure all transmitters have completed before proceeding XXX */
2501 rxq->ifr_cq_cidx = 0;
2502 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2503 bzero((void *)di->idi_vaddr, di->idi_size);
2504 /* also resets the free lists pidx/cidx */
2505 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2506 iflib_fl_bufs_free(fl);
2510 static inline caddr_t
2511 calc_next_rxd(iflib_fl_t fl, int cidx)
2515 caddr_t start, end, cur, next;
2517 nrxd = fl->ifl_size;
2518 size = fl->ifl_rxd_size;
2519 start = fl->ifl_ifdi->idi_vaddr;
2521 if (__predict_false(size == 0))
2523 cur = start + size*cidx;
2524 end = start + size*nrxd;
2525 next = CACHE_PTR_NEXT(cur);
2526 return (next < end ? next : start);
2530 prefetch_pkts(iflib_fl_t fl, int cidx)
2533 int nrxd = fl->ifl_size;
2537 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2538 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2539 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2540 next_rxd = calc_next_rxd(fl, cidx);
2542 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2543 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2544 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2545 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2546 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2547 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2548 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2549 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2552 static struct mbuf *
2553 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2554 int *pf_rv, if_rxd_info_t ri)
2560 int flid, cidx, len, next;
2563 flid = irf->irf_flid;
2564 cidx = irf->irf_idx;
2565 fl = &rxq->ifr_fl[flid];
2567 m = fl->ifl_sds.ifsd_m[cidx];
2568 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2571 fl->ifl_m_dequeued++;
2573 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2574 prefetch_pkts(fl, cidx);
2575 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2576 prefetch(&fl->ifl_sds.ifsd_map[next]);
2577 map = fl->ifl_sds.ifsd_map[cidx];
2579 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2581 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2582 irf->irf_len != 0) {
2583 payload = *sd->ifsd_cl;
2584 payload += ri->iri_pad;
2585 len = ri->iri_len - ri->iri_pad;
2586 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2587 len | PFIL_MEMPTR | PFIL_IN, NULL);
2592 * The filter ate it. Everything is recycled.
2597 case PFIL_REALLOCED:
2599 * The filter copied it. Everything is recycled.
2601 m = pfil_mem2mbuf(payload);
2606 * Filter said it was OK, so receive like
2609 fl->ifl_sds.ifsd_m[cidx] = NULL;
2615 fl->ifl_sds.ifsd_m[cidx] = NULL;
2619 if (unload && irf->irf_len != 0)
2620 bus_dmamap_unload(fl->ifl_buf_tag, map);
2621 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2622 if (__predict_false(fl->ifl_cidx == 0))
2624 bit_clear(fl->ifl_rx_bitmap, cidx);
2628 static struct mbuf *
2629 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2631 struct mbuf *m, *mh, *mt;
2633 int *pf_rv_ptr, flags, i, padlen;
2642 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2645 MPASS(*sd->ifsd_cl != NULL);
2648 * Exclude zero-length frags & frags from
2649 * packets the filter has consumed or dropped
2651 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2652 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2654 /* everything saved here */
2659 /* XXX we can save the cluster here, but not the mbuf */
2660 m_init(m, M_NOWAIT, MT_DATA, 0);
2665 flags = M_PKTHDR|M_EXT;
2667 padlen = ri->iri_pad;
2672 /* assuming padding is only on the first fragment */
2676 *sd->ifsd_cl = NULL;
2678 /* Can these two be made one ? */
2679 m_init(m, M_NOWAIT, MT_DATA, flags);
2680 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2682 * These must follow m_init and m_cljset
2684 m->m_data += padlen;
2685 ri->iri_len -= padlen;
2686 m->m_len = ri->iri_frags[i].irf_len;
2687 } while (++i < ri->iri_nfrags);
2693 * Process one software descriptor
2695 static struct mbuf *
2696 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2702 /* should I merge this back in now that the two paths are basically duplicated? */
2703 if (ri->iri_nfrags == 1 &&
2704 ri->iri_frags[0].irf_len != 0 &&
2705 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2706 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2708 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2710 if (pf_rv == PFIL_PASS) {
2711 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2712 #ifndef __NO_STRICT_ALIGNMENT
2716 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2717 m->m_len = ri->iri_frags[0].irf_len;
2720 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2723 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2726 m->m_pkthdr.len = ri->iri_len;
2727 m->m_pkthdr.rcvif = ri->iri_ifp;
2728 m->m_flags |= ri->iri_flags;
2729 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2730 m->m_pkthdr.flowid = ri->iri_flowid;
2731 M_HASHTYPE_SET(m, ri->iri_rsstype);
2732 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2733 m->m_pkthdr.csum_data = ri->iri_csum_data;
2737 #if defined(INET6) || defined(INET)
2739 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2741 CURVNET_SET(lc->ifp->if_vnet);
2743 *v6 = V_ip6_forwarding;
2746 *v4 = V_ipforwarding;
2752 * Returns true if it's possible this packet could be LROed.
2753 * if it returns false, it is guaranteed that tcp_lro_rx()
2754 * would not return zero.
2757 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2759 struct ether_header *eh;
2761 eh = mtod(m, struct ether_header *);
2762 switch (eh->ether_type) {
2764 case htons(ETHERTYPE_IPV6):
2765 return (!v6_forwarding);
2768 case htons(ETHERTYPE_IP):
2769 return (!v4_forwarding);
2777 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2783 _task_fn_rx_watchdog(void *context)
2785 iflib_rxq_t rxq = context;
2787 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2791 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2794 if_ctx_t ctx = rxq->ifr_ctx;
2795 if_shared_ctx_t sctx = ctx->ifc_sctx;
2796 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2799 struct if_rxd_info ri;
2800 int err, budget_left, rx_bytes, rx_pkts;
2803 bool v4_forwarding, v6_forwarding, lro_possible;
2807 * XXX early demux data packets so that if_input processing only handles
2808 * acks in interrupt context
2810 struct mbuf *m, *mh, *mt, *mf;
2814 lro_possible = v4_forwarding = v6_forwarding = false;
2818 rx_pkts = rx_bytes = 0;
2819 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2820 cidxp = &rxq->ifr_cq_cidx;
2822 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2823 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2824 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2825 retval |= iflib_fl_refill_all(ctx, fl);
2826 DBG_COUNTER_INC(rx_unavail);
2830 /* pfil needs the vnet to be set */
2831 CURVNET_SET_QUIET(ifp->if_vnet);
2832 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2833 if (__predict_false(!CTX_ACTIVE(ctx))) {
2834 DBG_COUNTER_INC(rx_ctx_inactive);
2838 * Reset client set fields to their default values
2841 ri.iri_qsidx = rxq->ifr_id;
2842 ri.iri_cidx = *cidxp;
2844 ri.iri_frags = rxq->ifr_frags;
2845 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2850 rx_bytes += ri.iri_len;
2851 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2852 *cidxp = ri.iri_cidx;
2853 /* Update our consumer index */
2854 /* XXX NB: shurd - check if this is still safe */
2855 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2856 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2857 /* was this only a completion queue message? */
2858 if (__predict_false(ri.iri_nfrags == 0))
2861 MPASS(ri.iri_nfrags != 0);
2862 MPASS(ri.iri_len != 0);
2864 /* will advance the cidx on the corresponding free lists */
2865 m = iflib_rxd_pkt_get(rxq, &ri);
2868 if (avail == 0 && budget_left)
2869 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2871 if (__predict_false(m == NULL))
2874 /* imm_pkt: -- cxgb */
2883 /* make sure that we can refill faster than drain */
2884 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2885 retval |= iflib_fl_refill_all(ctx, fl);
2887 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2889 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2891 while (mh != NULL) {
2894 m->m_nextpkt = NULL;
2895 #ifndef __NO_STRICT_ALIGNMENT
2896 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2899 rx_bytes += m->m_pkthdr.len;
2901 #if defined(INET6) || defined(INET)
2903 if (!lro_possible) {
2904 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2905 if (lro_possible && mf != NULL) {
2906 ifp->if_input(ifp, mf);
2907 DBG_COUNTER_INC(rx_if_input);
2911 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2912 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2913 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2919 ifp->if_input(ifp, m);
2920 DBG_COUNTER_INC(rx_if_input);
2931 ifp->if_input(ifp, mf);
2932 DBG_COUNTER_INC(rx_if_input);
2935 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2936 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2939 * Flush any outstanding LRO work
2941 #if defined(INET6) || defined(INET)
2942 tcp_lro_flush_all(&rxq->ifr_lc);
2944 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2945 retval |= IFLIB_RXEOF_MORE;
2949 ctx->ifc_flags |= IFC_DO_RESET;
2950 iflib_admin_intr_deferred(ctx);
2955 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2956 static inline qidx_t
2957 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2959 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2960 qidx_t minthresh = txq->ift_size / 8;
2961 if (in_use > 4*minthresh)
2962 return (notify_count);
2963 if (in_use > 2*minthresh)
2964 return (notify_count >> 1);
2965 if (in_use > minthresh)
2966 return (notify_count >> 3);
2970 static inline qidx_t
2971 txq_max_rs_deferred(iflib_txq_t txq)
2973 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2974 qidx_t minthresh = txq->ift_size / 8;
2975 if (txq->ift_in_use > 4*minthresh)
2976 return (notify_count);
2977 if (txq->ift_in_use > 2*minthresh)
2978 return (notify_count >> 1);
2979 if (txq->ift_in_use > minthresh)
2980 return (notify_count >> 2);
2984 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2985 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2987 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2988 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2989 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2991 /* forward compatibility for cxgb */
2992 #define FIRST_QSET(ctx) 0
2993 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2994 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2995 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2996 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2998 /* XXX we should be setting this to something other than zero */
2999 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3000 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3001 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3004 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
3010 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
3011 if (ring || txq->ift_db_pending >= max) {
3012 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3013 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3014 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3015 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3016 txq->ift_db_pending = txq->ift_npending = 0;
3024 print_pkt(if_pkt_info_t pi)
3026 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3027 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3028 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3029 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3030 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3031 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3035 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3036 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3037 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3038 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3041 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3043 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3044 struct ether_vlan_header *eh;
3048 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3049 M_WRITABLE(m) == 0) {
3050 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3054 DBG_COUNTER_INC(tx_frees);
3060 * Determine where frame payload starts.
3061 * Jump over vlan headers if already present,
3062 * helpful for QinQ too.
3064 if (__predict_false(m->m_len < sizeof(*eh))) {
3066 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3069 eh = mtod(m, struct ether_vlan_header *);
3070 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3071 pi->ipi_etype = ntohs(eh->evl_proto);
3072 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3074 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3075 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3078 switch (pi->ipi_etype) {
3083 struct ip *ip = NULL;
3084 struct tcphdr *th = NULL;
3087 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3088 if (__predict_false(m->m_len < minthlen)) {
3090 * if this code bloat is causing too much of a hit
3091 * move it to a separate function and mark it noinline
3093 if (m->m_len == pi->ipi_ehdrlen) {
3096 if (n->m_len >= sizeof(*ip)) {
3097 ip = (struct ip *)n->m_data;
3098 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3099 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3102 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3104 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3108 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3110 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3111 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3112 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3115 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3116 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3117 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3119 pi->ipi_ip_hlen = ip->ip_hl << 2;
3120 pi->ipi_ipproto = ip->ip_p;
3121 pi->ipi_flags |= IPI_TX_IPV4;
3123 /* TCP checksum offload may require TCP header length */
3124 if (IS_TX_OFFLOAD4(pi)) {
3125 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3126 if (__predict_false(th == NULL)) {
3128 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3130 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3132 pi->ipi_tcp_hflags = th->th_flags;
3133 pi->ipi_tcp_hlen = th->th_off << 2;
3134 pi->ipi_tcp_seq = th->th_seq;
3137 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3140 * TSO always requires hardware checksum offload.
3142 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3143 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3144 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3145 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3146 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3148 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3152 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3159 case ETHERTYPE_IPV6:
3161 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3163 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3165 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3167 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3170 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3172 /* XXX-BZ this will go badly in case of ext hdrs. */
3173 pi->ipi_ipproto = ip6->ip6_nxt;
3174 pi->ipi_flags |= IPI_TX_IPV6;
3176 /* TCP checksum offload may require TCP header length */
3177 if (IS_TX_OFFLOAD6(pi)) {
3178 if (pi->ipi_ipproto == IPPROTO_TCP) {
3179 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3181 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3184 pi->ipi_tcp_hflags = th->th_flags;
3185 pi->ipi_tcp_hlen = th->th_off << 2;
3186 pi->ipi_tcp_seq = th->th_seq;
3189 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3192 * TSO always requires hardware checksum offload.
3194 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3195 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3196 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3203 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3204 pi->ipi_ip_hlen = 0;
3213 * If dodgy hardware rejects the scatter gather chain we've handed it
3214 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3217 static __noinline struct mbuf *
3218 iflib_remove_mbuf(iflib_txq_t txq)
3221 struct mbuf *m, **ifsd_m;
3223 ifsd_m = txq->ift_sds.ifsd_m;
3224 ntxd = txq->ift_size;
3225 pidx = txq->ift_pidx & (ntxd - 1);
3226 ifsd_m = txq->ift_sds.ifsd_m;
3228 ifsd_m[pidx] = NULL;
3229 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3230 if (txq->ift_sds.ifsd_tso_map != NULL)
3231 bus_dmamap_unload(txq->ift_tso_buf_tag,
3232 txq->ift_sds.ifsd_tso_map[pidx]);
3234 txq->ift_dequeued++;
3239 static inline caddr_t
3240 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3244 caddr_t start, end, cur, next;
3246 ntxd = txq->ift_size;
3247 size = txq->ift_txd_size[qid];
3248 start = txq->ift_ifdi[qid].idi_vaddr;
3250 if (__predict_false(size == 0))
3252 cur = start + size*cidx;
3253 end = start + size*ntxd;
3254 next = CACHE_PTR_NEXT(cur);
3255 return (next < end ? next : start);
3259 * Pad an mbuf to ensure a minimum ethernet frame size.
3260 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3262 static __noinline int
3263 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3266 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3267 * and ARP message is the smallest common payload I can think of
3269 static char pad[18]; /* just zeros */
3271 struct mbuf *new_head;
3273 if (!M_WRITABLE(*m_head)) {
3274 new_head = m_dup(*m_head, M_NOWAIT);
3275 if (new_head == NULL) {
3277 device_printf(dev, "cannot pad short frame, m_dup() failed");
3278 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3279 DBG_COUNTER_INC(tx_frees);
3286 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3287 n > 0; n -= sizeof(pad))
3288 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3293 device_printf(dev, "cannot pad short frame\n");
3294 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3295 DBG_COUNTER_INC(tx_frees);
3303 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3306 if_shared_ctx_t sctx;
3307 if_softc_ctx_t scctx;
3308 bus_dma_tag_t buf_tag;
3309 bus_dma_segment_t *segs;
3310 struct mbuf *m_head, **ifsd_m;
3313 struct if_pkt_info pi;
3315 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3318 sctx = ctx->ifc_sctx;
3319 scctx = &ctx->ifc_softc_ctx;
3320 segs = txq->ift_segs;
3321 ntxd = txq->ift_size;
3326 * If we're doing TSO the next descriptor to clean may be quite far ahead
3328 cidx = txq->ift_cidx;
3329 pidx = txq->ift_pidx;
3330 if (ctx->ifc_flags & IFC_PREFETCH) {
3331 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3332 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3333 next_txd = calc_next_txd(txq, cidx, 0);
3337 /* prefetch the next cache line of mbuf pointers and flags */
3338 prefetch(&txq->ift_sds.ifsd_m[next]);
3339 prefetch(&txq->ift_sds.ifsd_map[next]);
3340 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3342 map = txq->ift_sds.ifsd_map[pidx];
3343 ifsd_m = txq->ift_sds.ifsd_m;
3345 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3346 buf_tag = txq->ift_tso_buf_tag;
3347 max_segs = scctx->isc_tx_tso_segments_max;
3348 map = txq->ift_sds.ifsd_tso_map[pidx];
3349 MPASS(buf_tag != NULL);
3350 MPASS(max_segs > 0);
3352 buf_tag = txq->ift_buf_tag;
3353 max_segs = scctx->isc_tx_nsegments;
3354 map = txq->ift_sds.ifsd_map[pidx];
3356 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3357 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3358 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3360 DBG_COUNTER_INC(encap_txd_encap_fail);
3367 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3369 pi.ipi_qsidx = txq->ift_id;
3370 pi.ipi_len = m_head->m_pkthdr.len;
3371 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3372 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3374 /* deliberate bitwise OR to make one condition */
3375 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3376 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3377 DBG_COUNTER_INC(encap_txd_encap_fail);
3384 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3387 if (__predict_false(err)) {
3390 /* try collapse once and defrag once */
3392 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3393 /* try defrag if collapsing fails */
3398 txq->ift_mbuf_defrag++;
3399 m_head = m_defrag(*m_headp, M_NOWAIT);
3402 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3403 * failed to map an mbuf that was run through m_defrag
3406 if (__predict_false(m_head == NULL || remap > 1))
3413 txq->ift_no_tx_dma_setup++;
3416 txq->ift_no_tx_dma_setup++;
3418 DBG_COUNTER_INC(tx_frees);
3422 txq->ift_map_failed++;
3423 DBG_COUNTER_INC(encap_load_mbuf_fail);
3424 DBG_COUNTER_INC(encap_txd_encap_fail);
3427 ifsd_m[pidx] = m_head;
3429 * XXX assumes a 1 to 1 relationship between segments and
3430 * descriptors - this does not hold true on all drivers, e.g.
3433 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3434 txq->ift_no_desc_avail++;
3435 bus_dmamap_unload(buf_tag, map);
3436 DBG_COUNTER_INC(encap_txq_avail_fail);
3437 DBG_COUNTER_INC(encap_txd_encap_fail);
3438 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3439 GROUPTASK_ENQUEUE(&txq->ift_task);
3443 * On Intel cards we can greatly reduce the number of TX interrupts
3444 * we see by only setting report status on every Nth descriptor.
3445 * However, this also means that the driver will need to keep track
3446 * of the descriptors that RS was set on to check them for the DD bit.
3448 txq->ift_rs_pending += nsegs + 1;
3449 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3450 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3451 pi.ipi_flags |= IPI_TX_INTR;
3452 txq->ift_rs_pending = 0;
3456 pi.ipi_nsegs = nsegs;
3458 MPASS(pidx >= 0 && pidx < txq->ift_size);
3462 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3463 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3464 DBG_COUNTER_INC(tx_encap);
3465 MPASS(pi.ipi_new_pidx < txq->ift_size);
3467 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3468 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3469 ndesc += txq->ift_size;
3473 * drivers can need as many as
3476 MPASS(ndesc <= pi.ipi_nsegs + 2);
3477 MPASS(pi.ipi_new_pidx != pidx);
3479 txq->ift_in_use += ndesc;
3482 * We update the last software descriptor again here because there may
3483 * be a sentinel and/or there may be more mbufs than segments
3485 txq->ift_pidx = pi.ipi_new_pidx;
3486 txq->ift_npending += pi.ipi_ndescs;
3488 *m_headp = m_head = iflib_remove_mbuf(txq);
3490 txq->ift_txd_encap_efbig++;
3499 * err can't possibly be non-zero here, so we don't neet to test it
3500 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3505 txq->ift_mbuf_defrag_failed++;
3506 txq->ift_map_failed++;
3508 DBG_COUNTER_INC(tx_frees);
3510 DBG_COUNTER_INC(encap_txd_encap_fail);
3515 iflib_tx_desc_free(iflib_txq_t txq, int n)
3517 uint32_t qsize, cidx, mask, gen;
3518 struct mbuf *m, **ifsd_m;
3521 cidx = txq->ift_cidx;
3523 qsize = txq->ift_size;
3525 ifsd_m = txq->ift_sds.ifsd_m;
3526 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3530 prefetch(ifsd_m[(cidx + 3) & mask]);
3531 prefetch(ifsd_m[(cidx + 4) & mask]);
3533 if ((m = ifsd_m[cidx]) != NULL) {
3534 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3535 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3536 bus_dmamap_sync(txq->ift_tso_buf_tag,
3537 txq->ift_sds.ifsd_tso_map[cidx],
3538 BUS_DMASYNC_POSTWRITE);
3539 bus_dmamap_unload(txq->ift_tso_buf_tag,
3540 txq->ift_sds.ifsd_tso_map[cidx]);
3542 bus_dmamap_sync(txq->ift_buf_tag,
3543 txq->ift_sds.ifsd_map[cidx],
3544 BUS_DMASYNC_POSTWRITE);
3545 bus_dmamap_unload(txq->ift_buf_tag,
3546 txq->ift_sds.ifsd_map[cidx]);
3548 /* XXX we don't support any drivers that batch packets yet */
3549 MPASS(m->m_nextpkt == NULL);
3551 ifsd_m[cidx] = NULL;
3553 txq->ift_dequeued++;
3555 DBG_COUNTER_INC(tx_frees);
3557 if (__predict_false(++cidx == qsize)) {
3562 txq->ift_cidx = cidx;
3567 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3570 if_ctx_t ctx = txq->ift_ctx;
3572 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3573 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3576 * Need a rate-limiting check so that this isn't called every time
3578 iflib_tx_credits_update(ctx, txq);
3579 reclaim = DESC_RECLAIMABLE(txq);
3581 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3583 if (iflib_verbose_debug) {
3584 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3585 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3592 iflib_tx_desc_free(txq, reclaim);
3593 txq->ift_cleaned += reclaim;
3594 txq->ift_in_use -= reclaim;
3599 static struct mbuf **
3600 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3603 struct mbuf **items;
3606 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3607 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3609 prefetch(items[(cidx + offset) & (size-1)]);
3610 if (remaining > 1) {
3611 prefetch2cachelines(&items[next]);
3612 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3613 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3614 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3616 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3620 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3623 ifmp_ring_check_drainage(txq->ift_br, budget);
3627 iflib_txq_can_drain(struct ifmp_ring *r)
3629 iflib_txq_t txq = r->cookie;
3630 if_ctx_t ctx = txq->ift_ctx;
3632 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3634 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3635 BUS_DMASYNC_POSTREAD);
3636 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3641 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3643 iflib_txq_t txq = r->cookie;
3644 if_ctx_t ctx = txq->ift_ctx;
3645 if_t ifp = ctx->ifc_ifp;
3646 struct mbuf *m, **mp;
3647 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3648 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3649 bool do_prefetch, rang, ring;
3651 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3652 !LINK_ACTIVE(ctx))) {
3653 DBG_COUNTER_INC(txq_drain_notready);
3656 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3657 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3658 avail = IDXDIFF(pidx, cidx, r->size);
3659 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3660 DBG_COUNTER_INC(txq_drain_flushing);
3661 for (i = 0; i < avail; i++) {
3662 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3663 m_free(r->items[(cidx + i) & (r->size-1)]);
3664 r->items[(cidx + i) & (r->size-1)] = NULL;
3669 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3670 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3672 callout_stop(&txq->ift_timer);
3673 CALLOUT_UNLOCK(txq);
3674 DBG_COUNTER_INC(txq_drain_oactive);
3678 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3679 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3680 count = MIN(avail, TX_BATCH_SIZE);
3682 if (iflib_verbose_debug)
3683 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3684 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3686 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3687 txq_avail = TXQ_AVAIL(txq);
3689 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3690 int rem = do_prefetch ? count - i : 0;
3692 mp = _ring_peek_one(r, cidx, i, rem);
3693 MPASS(mp != NULL && *mp != NULL);
3694 if (__predict_false(*mp == (struct mbuf *)txq)) {
3698 in_use_prev = txq->ift_in_use;
3699 err = iflib_encap(txq, mp);
3700 if (__predict_false(err)) {
3701 /* no room - bail out */
3705 /* we can't send this packet - skip it */
3711 DBG_COUNTER_INC(tx_sent);
3712 bytes_sent += m->m_pkthdr.len;
3713 mcast_sent += !!(m->m_flags & M_MCAST);
3714 txq_avail = TXQ_AVAIL(txq);
3716 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3717 ETHER_BPF_MTAP(ifp, m);
3718 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3720 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3723 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3724 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3725 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3726 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3727 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3729 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3731 if (iflib_verbose_debug)
3732 printf("consumed=%d\n", consumed);
3738 iflib_txq_drain_always(struct ifmp_ring *r)
3744 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3752 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3754 callout_stop(&txq->ift_timer);
3755 CALLOUT_UNLOCK(txq);
3757 avail = IDXDIFF(pidx, cidx, r->size);
3758 for (i = 0; i < avail; i++) {
3759 mp = _ring_peek_one(r, cidx, i, avail - i);
3760 if (__predict_false(*mp == (struct mbuf *)txq))
3763 DBG_COUNTER_INC(tx_frees);
3765 MPASS(ifmp_ring_is_stalled(r) == 0);
3770 iflib_ifmp_purge(iflib_txq_t txq)
3772 struct ifmp_ring *r;
3775 r->drain = iflib_txq_drain_free;
3776 r->can_drain = iflib_txq_drain_always;
3778 ifmp_ring_check_drainage(r, r->size);
3780 r->drain = iflib_txq_drain;
3781 r->can_drain = iflib_txq_can_drain;
3785 _task_fn_tx(void *context)
3787 iflib_txq_t txq = context;
3788 if_ctx_t ctx = txq->ift_ctx;
3789 if_t ifp = ctx->ifc_ifp;
3790 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3792 #ifdef IFLIB_DIAGNOSTICS
3793 txq->ift_cpu_exec_count[curcpu]++;
3795 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3798 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3799 netmap_tx_irq(ifp, txq->ift_id))
3803 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3804 iflib_altq_if_start(ifp);
3806 if (txq->ift_db_pending)
3807 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3809 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3811 * When abdicating, we always need to check drainage, not just when we don't enqueue
3814 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3818 if (ctx->ifc_flags & IFC_LEGACY)
3819 IFDI_INTR_ENABLE(ctx);
3821 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3825 _task_fn_rx(void *context)
3827 iflib_rxq_t rxq = context;
3828 if_ctx_t ctx = rxq->ifr_ctx;
3836 #ifdef IFLIB_DIAGNOSTICS
3837 rxq->ifr_cpu_exec_count[curcpu]++;
3839 DBG_COUNTER_INC(task_fn_rxs);
3840 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3843 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3844 if (nmirq != NM_IRQ_PASS) {
3845 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3849 budget = ctx->ifc_sysctl_rx_budget;
3851 budget = 16; /* XXX */
3852 more = iflib_rxeof(rxq, budget);
3856 if ((more & IFLIB_RXEOF_MORE) == 0) {
3857 if (ctx->ifc_flags & IFC_LEGACY)
3858 IFDI_INTR_ENABLE(ctx);
3860 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3861 DBG_COUNTER_INC(rx_intr_enables);
3863 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3866 if (more & IFLIB_RXEOF_MORE)
3867 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3868 else if (more & IFLIB_RXEOF_EMPTY)
3869 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3873 _task_fn_admin(void *context)
3875 if_ctx_t ctx = context;
3876 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3879 bool oactive, running, do_reset, do_watchdog, in_detach;
3880 uint32_t reset_on = hz / 2;
3883 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3884 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3885 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3886 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3887 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3888 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3891 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3897 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3899 callout_stop(&txq->ift_timer);
3900 CALLOUT_UNLOCK(txq);
3903 ctx->ifc_watchdog_events++;
3904 IFDI_WATCHDOG_RESET(ctx);
3906 IFDI_UPDATE_ADMIN_STATUS(ctx);
3907 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3910 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3911 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3913 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3915 IFDI_LINK_INTR_ENABLE(ctx);
3917 iflib_if_init_locked(ctx);
3920 if (LINK_ACTIVE(ctx) == 0)
3922 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3923 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3928 _task_fn_iov(void *context)
3930 if_ctx_t ctx = context;
3932 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3933 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3937 IFDI_VFLR_HANDLE(ctx);
3942 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3945 if_int_delay_info_t info;
3948 info = (if_int_delay_info_t)arg1;
3949 ctx = info->iidi_ctx;
3950 info->iidi_req = req;
3951 info->iidi_oidp = oidp;
3953 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3958 /*********************************************************************
3962 **********************************************************************/
3965 iflib_if_init_locked(if_ctx_t ctx)
3968 iflib_init_locked(ctx);
3973 iflib_if_init(void *arg)
3978 iflib_if_init_locked(ctx);
3983 iflib_if_transmit(if_t ifp, struct mbuf *m)
3985 if_ctx_t ctx = if_getsoftc(ifp);
3989 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3991 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3992 DBG_COUNTER_INC(tx_frees);
3997 MPASS(m->m_nextpkt == NULL);
3998 /* ALTQ-enabled interfaces always use queue 0. */
4000 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
4001 qidx = QIDX(ctx, m);
4003 * XXX calculate buf_ring based on flowid (divvy up bits?)
4005 txq = &ctx->ifc_txqs[qidx];
4007 #ifdef DRIVER_BACKPRESSURE
4008 if (txq->ift_closed) {
4010 next = m->m_nextpkt;
4011 m->m_nextpkt = NULL;
4013 DBG_COUNTER_INC(tx_frees);
4025 next = next->m_nextpkt;
4026 } while (next != NULL);
4028 if (count > nitems(marr))
4029 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4030 /* XXX check nextpkt */
4032 /* XXX simplify for now */
4033 DBG_COUNTER_INC(tx_frees);
4036 for (next = m, i = 0; next != NULL; i++) {
4038 next = next->m_nextpkt;
4039 mp[i]->m_nextpkt = NULL;
4042 DBG_COUNTER_INC(tx_seen);
4043 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4046 GROUPTASK_ENQUEUE(&txq->ift_task);
4049 GROUPTASK_ENQUEUE(&txq->ift_task);
4050 /* support forthcoming later */
4051 #ifdef DRIVER_BACKPRESSURE
4052 txq->ift_closed = TRUE;
4054 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4056 DBG_COUNTER_INC(tx_frees);
4064 * The overall approach to integrating iflib with ALTQ is to continue to use
4065 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4066 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4067 * is redundant/unnecessary, but doing so minimizes the amount of
4068 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4069 * redundantly queueing to an intermediate mp_ring is swamped by the
4070 * performance limitations inherent in using ALTQ.
4072 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4073 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4074 * given interface. If ALTQ is enabled for an interface, then all
4075 * transmitted packets for that interface will be submitted to the ALTQ
4076 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4077 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4078 * update stats that the iflib machinery handles, and which is sensitve to
4079 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4080 * will be installed as the start routine for use by ALTQ facilities that
4081 * need to trigger queue drains on a scheduled basis.
4085 iflib_altq_if_start(if_t ifp)
4087 struct ifaltq *ifq = &ifp->if_snd;
4091 IFQ_DEQUEUE_NOLOCK(ifq, m);
4093 iflib_if_transmit(ifp, m);
4094 IFQ_DEQUEUE_NOLOCK(ifq, m);
4100 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4104 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4105 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4107 iflib_altq_if_start(ifp);
4109 err = iflib_if_transmit(ifp, m);
4116 iflib_if_qflush(if_t ifp)
4118 if_ctx_t ctx = if_getsoftc(ifp);
4119 iflib_txq_t txq = ctx->ifc_txqs;
4123 ctx->ifc_flags |= IFC_QFLUSH;
4125 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4126 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4127 iflib_txq_check_drain(txq, 0);
4129 ctx->ifc_flags &= ~IFC_QFLUSH;
4133 * When ALTQ is enabled, this will also take care of purging the
4140 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4141 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4142 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4143 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4146 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4148 if_ctx_t ctx = if_getsoftc(ifp);
4149 struct ifreq *ifr = (struct ifreq *)data;
4150 #if defined(INET) || defined(INET6)
4151 struct ifaddr *ifa = (struct ifaddr *)data;
4153 bool avoid_reset = false;
4154 int err = 0, reinit = 0, bits;
4159 if (ifa->ifa_addr->sa_family == AF_INET)
4163 if (ifa->ifa_addr->sa_family == AF_INET6)
4167 ** Calling init results in link renegotiation,
4168 ** so we avoid doing it when possible.
4171 if_setflagbits(ifp, IFF_UP,0);
4172 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4175 if (!(if_getflags(ifp) & IFF_NOARP))
4176 arp_ifinit(ifp, ifa);
4179 err = ether_ioctl(ifp, command, data);
4183 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4187 bits = if_getdrvflags(ifp);
4188 /* stop the driver and free any clusters before proceeding */
4191 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4193 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4194 ctx->ifc_flags |= IFC_MULTISEG;
4196 ctx->ifc_flags &= ~IFC_MULTISEG;
4198 err = if_setmtu(ifp, ifr->ifr_mtu);
4200 iflib_init_locked(ctx);
4202 if_setdrvflags(ifp, bits);
4208 if (if_getflags(ifp) & IFF_UP) {
4209 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4210 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4211 (IFF_PROMISC | IFF_ALLMULTI)) {
4213 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4218 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4221 ctx->ifc_if_flags = if_getflags(ifp);
4226 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4228 IFDI_INTR_DISABLE(ctx);
4229 IFDI_MULTI_SET(ctx);
4230 IFDI_INTR_ENABLE(ctx);
4236 IFDI_MEDIA_SET(ctx);
4241 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4245 struct ifi2creq i2c;
4247 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4250 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4254 if (i2c.len > sizeof(i2c.data)) {
4259 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4260 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4266 int mask, setmask, oldmask;
4268 oldmask = if_getcapenable(ifp);
4269 mask = ifr->ifr_reqcap ^ oldmask;
4270 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4273 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4275 setmask |= (mask & IFCAP_FLAGS);
4276 setmask |= (mask & IFCAP_WOL);
4279 * If any RX csum has changed, change all the ones that
4280 * are supported by the driver.
4282 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4283 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4284 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4288 * want to ensure that traffic has stopped before we change any of the flags
4292 bits = if_getdrvflags(ifp);
4293 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4296 if_togglecapenable(ifp, setmask);
4298 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4299 iflib_init_locked(ctx);
4301 if_setdrvflags(ifp, bits);
4308 case SIOCGPRIVATE_0:
4312 err = IFDI_PRIV_IOCTL(ctx, command, data);
4316 err = ether_ioctl(ifp, command, data);
4325 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4327 if_ctx_t ctx = if_getsoftc(ifp);
4329 return (IFDI_GET_COUNTER(ctx, cnt));
4332 /*********************************************************************
4334 * OTHER FUNCTIONS EXPORTED TO THE STACK
4336 **********************************************************************/
4339 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4341 if_ctx_t ctx = if_getsoftc(ifp);
4343 if ((void *)ctx != arg)
4346 if ((vtag == 0) || (vtag > 4095))
4349 if (iflib_in_detach(ctx))
4353 /* Driver may need all untagged packets to be flushed */
4354 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4356 IFDI_VLAN_REGISTER(ctx, vtag);
4357 /* Re-init to load the changes, if required */
4358 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4359 iflib_init_locked(ctx);
4364 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4366 if_ctx_t ctx = if_getsoftc(ifp);
4368 if ((void *)ctx != arg)
4371 if ((vtag == 0) || (vtag > 4095))
4375 /* Driver may need all tagged packets to be flushed */
4376 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4378 IFDI_VLAN_UNREGISTER(ctx, vtag);
4379 /* Re-init to load the changes, if required */
4380 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4381 iflib_init_locked(ctx);
4386 iflib_led_func(void *arg, int onoff)
4391 IFDI_LED_FUNC(ctx, onoff);
4395 /*********************************************************************
4397 * BUS FUNCTION DEFINITIONS
4399 **********************************************************************/
4402 iflib_device_probe(device_t dev)
4404 const pci_vendor_info_t *ent;
4405 if_shared_ctx_t sctx;
4406 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4407 uint16_t pci_vendor_id;
4409 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4412 pci_vendor_id = pci_get_vendor(dev);
4413 pci_device_id = pci_get_device(dev);
4414 pci_subvendor_id = pci_get_subvendor(dev);
4415 pci_subdevice_id = pci_get_subdevice(dev);
4416 pci_rev_id = pci_get_revid(dev);
4417 if (sctx->isc_parse_devinfo != NULL)
4418 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4420 ent = sctx->isc_vendor_info;
4421 while (ent->pvi_vendor_id != 0) {
4422 if (pci_vendor_id != ent->pvi_vendor_id) {
4426 if ((pci_device_id == ent->pvi_device_id) &&
4427 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4428 (ent->pvi_subvendor_id == 0)) &&
4429 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4430 (ent->pvi_subdevice_id == 0)) &&
4431 ((pci_rev_id == ent->pvi_rev_id) ||
4432 (ent->pvi_rev_id == 0))) {
4434 device_set_desc_copy(dev, ent->pvi_name);
4435 /* this needs to be changed to zero if the bus probing code
4436 * ever stops re-probing on best match because the sctx
4437 * may have its values over written by register calls
4438 * in subsequent probes
4440 return (BUS_PROBE_DEFAULT);
4448 iflib_device_probe_vendor(device_t dev)
4452 probe = iflib_device_probe(dev);
4453 if (probe == BUS_PROBE_DEFAULT)
4454 return (BUS_PROBE_VENDOR);
4460 iflib_reset_qvalues(if_ctx_t ctx)
4462 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4463 if_shared_ctx_t sctx = ctx->ifc_sctx;
4464 device_t dev = ctx->ifc_dev;
4467 if (ctx->ifc_sysctl_ntxqs != 0)
4468 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4469 if (ctx->ifc_sysctl_nrxqs != 0)
4470 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4472 for (i = 0; i < sctx->isc_ntxqs; i++) {
4473 if (ctx->ifc_sysctl_ntxds[i] != 0)
4474 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4476 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4479 for (i = 0; i < sctx->isc_nrxqs; i++) {
4480 if (ctx->ifc_sysctl_nrxds[i] != 0)
4481 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4483 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4486 for (i = 0; i < sctx->isc_nrxqs; i++) {
4487 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4488 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4489 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4490 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4492 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4493 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4494 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4495 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4497 if (!powerof2(scctx->isc_nrxd[i])) {
4498 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4499 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4500 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4504 for (i = 0; i < sctx->isc_ntxqs; i++) {
4505 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4506 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4507 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4508 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4510 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4511 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4512 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4513 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4515 if (!powerof2(scctx->isc_ntxd[i])) {
4516 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4517 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4518 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4524 iflib_add_pfil(if_ctx_t ctx)
4526 struct pfil_head *pfil;
4527 struct pfil_head_args pa;
4531 pa.pa_version = PFIL_VERSION;
4532 pa.pa_flags = PFIL_IN;
4533 pa.pa_type = PFIL_TYPE_ETHERNET;
4534 pa.pa_headname = ctx->ifc_ifp->if_xname;
4535 pfil = pfil_head_register(&pa);
4537 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4543 iflib_rem_pfil(if_ctx_t ctx)
4545 struct pfil_head *pfil;
4549 rxq = ctx->ifc_rxqs;
4551 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4554 pfil_head_unregister(pfil);
4558 get_ctx_core_offset(if_ctx_t ctx)
4560 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4561 struct cpu_offset *op;
4563 uint16_t ret = ctx->ifc_sysctl_core_offset;
4565 if (ret != CORE_OFFSET_UNSPECIFIED)
4568 if (ctx->ifc_sysctl_separate_txrx)
4569 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4571 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4573 mtx_lock(&cpu_offset_mtx);
4574 SLIST_FOREACH(op, &cpu_offsets, entries) {
4575 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4578 MPASS(op->refcount < UINT_MAX);
4583 if (ret == CORE_OFFSET_UNSPECIFIED) {
4585 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4588 device_printf(ctx->ifc_dev,
4589 "allocation for cpu offset failed.\n");
4593 CPU_COPY(&ctx->ifc_cpus, &op->set);
4594 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4597 mtx_unlock(&cpu_offset_mtx);
4603 unref_ctx_core_offset(if_ctx_t ctx)
4605 struct cpu_offset *op, *top;
4607 mtx_lock(&cpu_offset_mtx);
4608 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4609 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4610 MPASS(op->refcount > 0);
4612 if (op->refcount == 0) {
4613 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4619 mtx_unlock(&cpu_offset_mtx);
4623 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4627 if_softc_ctx_t scctx;
4628 kobjop_desc_t kobj_desc;
4629 kobj_method_t *kobj_method;
4631 int num_txd, num_rxd;
4633 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4636 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4637 device_set_softc(dev, ctx);
4638 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4641 ctx->ifc_sctx = sctx;
4643 ctx->ifc_softc = sc;
4645 if ((err = iflib_register(ctx)) != 0) {
4646 device_printf(dev, "iflib_register failed %d\n", err);
4649 iflib_add_device_sysctl_pre(ctx);
4651 scctx = &ctx->ifc_softc_ctx;
4654 iflib_reset_qvalues(ctx);
4656 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4657 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4660 _iflib_pre_assert(scctx);
4661 ctx->ifc_txrx = *scctx->isc_txrx;
4663 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4664 ctx->ifc_mediap = scctx->isc_media;
4667 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4668 MPASS(scctx->isc_tx_csum_flags);
4671 if_setcapabilities(ifp,
4672 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4673 if_setcapenable(ifp,
4674 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4676 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4677 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4678 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4679 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4681 num_txd = iflib_num_tx_descs(ctx);
4682 num_rxd = iflib_num_rx_descs(ctx);
4684 /* XXX change for per-queue sizes */
4685 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4688 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4689 scctx->isc_tx_nsegments = max(1, num_txd /
4690 MAX_SINGLE_PACKET_FRACTION);
4691 if (scctx->isc_tx_tso_segments_max > num_txd /
4692 MAX_SINGLE_PACKET_FRACTION)
4693 scctx->isc_tx_tso_segments_max = max(1,
4694 num_txd / MAX_SINGLE_PACKET_FRACTION);
4696 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4697 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4699 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4702 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4705 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4706 * into account. In the worst case, each of these calls will
4707 * add another mbuf and, thus, the requirement for another DMA
4708 * segment. So for best performance, it doesn't make sense to
4709 * advertize a maximum of TSO segments that typically will
4710 * require defragmentation in iflib_encap().
4712 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4713 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4715 if (scctx->isc_rss_table_size == 0)
4716 scctx->isc_rss_table_size = 64;
4717 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4719 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4720 /* XXX format name */
4721 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4722 NULL, NULL, "admin");
4724 /* Set up cpu set. If it fails, use the set of all CPUs. */
4725 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4726 device_printf(dev, "Unable to fetch CPU list\n");
4727 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4729 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4732 ** Now set up MSI or MSI-X, should return us the number of supported
4733 ** vectors (will be 1 for a legacy interrupt and MSI).
4735 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4736 msix = scctx->isc_vectors;
4737 } else if (scctx->isc_msix_bar != 0)
4739 * The simple fact that isc_msix_bar is not 0 does not mean we
4740 * we have a good value there that is known to work.
4742 msix = iflib_msix_init(ctx);
4744 scctx->isc_vectors = 1;
4745 scctx->isc_ntxqsets = 1;
4746 scctx->isc_nrxqsets = 1;
4747 scctx->isc_intr = IFLIB_INTR_LEGACY;
4750 /* Get memory for the station queues */
4751 if ((err = iflib_queues_alloc(ctx))) {
4752 device_printf(dev, "Unable to allocate queue memory\n");
4753 goto fail_intr_free;
4756 if ((err = iflib_qset_structures_setup(ctx)))
4760 * Now that we know how many queues there are, get the core offset.
4762 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4766 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4767 * aren't the default NULL implementation.
4769 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4770 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4772 if (kobj_method == &kobj_desc->deflt) {
4774 "MSI-X requires ifdi_rx_queue_intr_enable method");
4778 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4779 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4781 if (kobj_method == &kobj_desc->deflt) {
4783 "MSI-X requires ifdi_tx_queue_intr_enable method");
4789 * Assign the MSI-X vectors.
4790 * Note that the default NULL ifdi_msix_intr_assign method will
4793 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4795 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4799 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4801 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4805 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4806 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4811 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4813 goto fail_intr_free;
4816 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4818 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4819 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4824 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4825 * This must appear after the call to ether_ifattach() because
4826 * ether_ifattach() sets if_hdrlen to the default value.
4828 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4829 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4831 if ((err = iflib_netmap_attach(ctx))) {
4832 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4837 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4839 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4840 iflib_add_device_sysctl_post(ctx);
4841 iflib_add_pfil(ctx);
4842 ctx->ifc_flags |= IFC_INIT_DONE;
4848 ether_ifdetach(ctx->ifc_ifp);
4850 iflib_free_intr_mem(ctx);
4852 iflib_tx_structures_free(ctx);
4853 iflib_rx_structures_free(ctx);
4854 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4858 iflib_deregister(ctx);
4860 device_set_softc(ctx->ifc_dev, NULL);
4861 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4862 free(ctx->ifc_softc, M_IFLIB);
4868 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4869 struct iflib_cloneattach_ctx *clctx)
4871 int num_txd, num_rxd;
4875 if_softc_ctx_t scctx;
4879 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4880 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4881 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4882 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4883 ctx->ifc_flags |= IFC_PSEUDO;
4885 ctx->ifc_sctx = sctx;
4886 ctx->ifc_softc = sc;
4889 if ((err = iflib_register(ctx)) != 0) {
4890 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4893 iflib_add_device_sysctl_pre(ctx);
4895 scctx = &ctx->ifc_softc_ctx;
4898 iflib_reset_qvalues(ctx);
4900 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4901 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4904 if (sctx->isc_flags & IFLIB_GEN_MAC)
4905 ether_gen_addr(ifp, &ctx->ifc_mac);
4906 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4907 clctx->cc_params)) != 0) {
4908 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4912 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4913 MPASS(scctx->isc_tx_csum_flags);
4916 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4917 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4919 ifp->if_flags |= IFF_NOGROUP;
4920 if (sctx->isc_flags & IFLIB_PSEUDO) {
4921 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4922 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4923 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4924 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4926 if_attach(ctx->ifc_ifp);
4927 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4930 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4931 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4937 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4938 * This must appear after the call to ether_ifattach() because
4939 * ether_ifattach() sets if_hdrlen to the default value.
4941 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4942 if_setifheaderlen(ifp,
4943 sizeof(struct ether_vlan_header));
4945 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4946 iflib_add_device_sysctl_post(ctx);
4947 ctx->ifc_flags |= IFC_INIT_DONE;
4951 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4952 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4953 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4955 _iflib_pre_assert(scctx);
4956 ctx->ifc_txrx = *scctx->isc_txrx;
4958 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4959 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4960 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4961 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4963 num_txd = iflib_num_tx_descs(ctx);
4964 num_rxd = iflib_num_rx_descs(ctx);
4966 /* XXX change for per-queue sizes */
4967 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4970 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4971 scctx->isc_tx_nsegments = max(1, num_txd /
4972 MAX_SINGLE_PACKET_FRACTION);
4973 if (scctx->isc_tx_tso_segments_max > num_txd /
4974 MAX_SINGLE_PACKET_FRACTION)
4975 scctx->isc_tx_tso_segments_max = max(1,
4976 num_txd / MAX_SINGLE_PACKET_FRACTION);
4978 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4979 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4981 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4984 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4987 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4988 * into account. In the worst case, each of these calls will
4989 * add another mbuf and, thus, the requirement for another DMA
4990 * segment. So for best performance, it doesn't make sense to
4991 * advertize a maximum of TSO segments that typically will
4992 * require defragmentation in iflib_encap().
4994 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4995 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4997 if (scctx->isc_rss_table_size == 0)
4998 scctx->isc_rss_table_size = 64;
4999 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5001 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5002 /* XXX format name */
5003 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5004 NULL, NULL, "admin");
5006 /* XXX --- can support > 1 -- but keep it simple for now */
5007 scctx->isc_intr = IFLIB_INTR_LEGACY;
5009 /* Get memory for the station queues */
5010 if ((err = iflib_queues_alloc(ctx))) {
5011 device_printf(dev, "Unable to allocate queue memory\n");
5012 goto fail_iflib_detach;
5015 if ((err = iflib_qset_structures_setup(ctx))) {
5016 device_printf(dev, "qset structure setup failed %d\n", err);
5021 * XXX What if anything do we want to do about interrupts?
5023 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5024 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5025 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5030 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5031 * This must appear after the call to ether_ifattach() because
5032 * ether_ifattach() sets if_hdrlen to the default value.
5034 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5035 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5037 /* XXX handle more than one queue */
5038 for (i = 0; i < scctx->isc_nrxqsets; i++)
5039 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5043 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5044 iflib_add_device_sysctl_post(ctx);
5045 ctx->ifc_flags |= IFC_INIT_DONE;
5050 ether_ifdetach(ctx->ifc_ifp);
5052 iflib_tx_structures_free(ctx);
5053 iflib_rx_structures_free(ctx);
5058 iflib_deregister(ctx);
5060 free(ctx->ifc_softc, M_IFLIB);
5066 iflib_pseudo_deregister(if_ctx_t ctx)
5068 if_t ifp = ctx->ifc_ifp;
5069 if_shared_ctx_t sctx = ctx->ifc_sctx;
5073 struct taskqgroup *tqg;
5076 /* Unregister VLAN event handlers early */
5077 iflib_unregister_vlan_handlers(ctx);
5079 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5080 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5084 ether_ifdetach(ifp);
5086 /* XXX drain any dependent tasks */
5087 tqg = qgroup_if_io_tqg;
5088 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5089 callout_drain(&txq->ift_timer);
5090 if (txq->ift_task.gt_uniq != NULL)
5091 taskqgroup_detach(tqg, &txq->ift_task);
5093 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5094 callout_drain(&rxq->ifr_watchdog);
5095 if (rxq->ifr_task.gt_uniq != NULL)
5096 taskqgroup_detach(tqg, &rxq->ifr_task);
5098 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5099 free(fl->ifl_rx_bitmap, M_IFLIB);
5101 tqg = qgroup_if_config_tqg;
5102 if (ctx->ifc_admin_task.gt_uniq != NULL)
5103 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5104 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5105 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5107 iflib_tx_structures_free(ctx);
5108 iflib_rx_structures_free(ctx);
5110 iflib_deregister(ctx);
5112 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5113 free(ctx->ifc_softc, M_IFLIB);
5119 iflib_device_attach(device_t dev)
5122 if_shared_ctx_t sctx;
5124 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5127 pci_enable_busmaster(dev);
5129 return (iflib_device_register(dev, NULL, sctx, &ctx));
5133 iflib_device_deregister(if_ctx_t ctx)
5135 if_t ifp = ctx->ifc_ifp;
5138 device_t dev = ctx->ifc_dev;
5140 struct taskqgroup *tqg;
5143 /* Make sure VLANS are not using driver */
5144 if (if_vlantrunkinuse(ifp)) {
5145 device_printf(dev, "Vlan in use, detach first\n");
5149 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5150 device_printf(dev, "SR-IOV in use; detach first.\n");
5156 ctx->ifc_flags |= IFC_IN_DETACH;
5159 /* Unregister VLAN handlers before calling iflib_stop() */
5160 iflib_unregister_vlan_handlers(ctx);
5162 iflib_netmap_detach(ifp);
5163 ether_ifdetach(ifp);
5169 iflib_rem_pfil(ctx);
5170 if (ctx->ifc_led_dev != NULL)
5171 led_destroy(ctx->ifc_led_dev);
5172 /* XXX drain any dependent tasks */
5173 tqg = qgroup_if_io_tqg;
5174 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5175 callout_drain(&txq->ift_timer);
5176 if (txq->ift_task.gt_uniq != NULL)
5177 taskqgroup_detach(tqg, &txq->ift_task);
5179 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5180 if (rxq->ifr_task.gt_uniq != NULL)
5181 taskqgroup_detach(tqg, &rxq->ifr_task);
5183 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5184 free(fl->ifl_rx_bitmap, M_IFLIB);
5186 tqg = qgroup_if_config_tqg;
5187 if (ctx->ifc_admin_task.gt_uniq != NULL)
5188 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5189 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5190 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5195 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5196 iflib_free_intr_mem(ctx);
5198 bus_generic_detach(dev);
5200 iflib_tx_structures_free(ctx);
5201 iflib_rx_structures_free(ctx);
5203 iflib_deregister(ctx);
5205 device_set_softc(ctx->ifc_dev, NULL);
5206 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5207 free(ctx->ifc_softc, M_IFLIB);
5208 unref_ctx_core_offset(ctx);
5214 iflib_free_intr_mem(if_ctx_t ctx)
5217 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5218 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5220 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5221 pci_release_msi(ctx->ifc_dev);
5223 if (ctx->ifc_msix_mem != NULL) {
5224 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5225 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5226 ctx->ifc_msix_mem = NULL;
5231 iflib_device_detach(device_t dev)
5233 if_ctx_t ctx = device_get_softc(dev);
5235 return (iflib_device_deregister(ctx));
5239 iflib_device_suspend(device_t dev)
5241 if_ctx_t ctx = device_get_softc(dev);
5247 return bus_generic_suspend(dev);
5250 iflib_device_shutdown(device_t dev)
5252 if_ctx_t ctx = device_get_softc(dev);
5258 return bus_generic_suspend(dev);
5263 iflib_device_resume(device_t dev)
5265 if_ctx_t ctx = device_get_softc(dev);
5266 iflib_txq_t txq = ctx->ifc_txqs;
5270 iflib_if_init_locked(ctx);
5272 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5273 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5275 return (bus_generic_resume(dev));
5279 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5282 if_ctx_t ctx = device_get_softc(dev);
5285 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5292 iflib_device_iov_uninit(device_t dev)
5294 if_ctx_t ctx = device_get_softc(dev);
5297 IFDI_IOV_UNINIT(ctx);
5302 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5305 if_ctx_t ctx = device_get_softc(dev);
5308 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5314 /*********************************************************************
5316 * MODULE FUNCTION DEFINITIONS
5318 **********************************************************************/
5321 * - Start a fast taskqueue thread for each core
5322 * - Start a taskqueue for control operations
5325 iflib_module_init(void)
5331 iflib_module_event_handler(module_t mod, int what, void *arg)
5337 if ((err = iflib_module_init()) != 0)
5343 return (EOPNOTSUPP);
5349 /*********************************************************************
5351 * PUBLIC FUNCTION DEFINITIONS
5352 * ordered as in iflib.h
5354 **********************************************************************/
5358 _iflib_assert(if_shared_ctx_t sctx)
5362 MPASS(sctx->isc_tx_maxsize);
5363 MPASS(sctx->isc_tx_maxsegsize);
5365 MPASS(sctx->isc_rx_maxsize);
5366 MPASS(sctx->isc_rx_nsegments);
5367 MPASS(sctx->isc_rx_maxsegsize);
5369 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5370 for (i = 0; i < sctx->isc_nrxqs; i++) {
5371 MPASS(sctx->isc_nrxd_min[i]);
5372 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5373 MPASS(sctx->isc_nrxd_max[i]);
5374 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5375 MPASS(sctx->isc_nrxd_default[i]);
5376 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5379 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5380 for (i = 0; i < sctx->isc_ntxqs; i++) {
5381 MPASS(sctx->isc_ntxd_min[i]);
5382 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5383 MPASS(sctx->isc_ntxd_max[i]);
5384 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5385 MPASS(sctx->isc_ntxd_default[i]);
5386 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5391 _iflib_pre_assert(if_softc_ctx_t scctx)
5394 MPASS(scctx->isc_txrx->ift_txd_encap);
5395 MPASS(scctx->isc_txrx->ift_txd_flush);
5396 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5397 MPASS(scctx->isc_txrx->ift_rxd_available);
5398 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5399 MPASS(scctx->isc_txrx->ift_rxd_refill);
5400 MPASS(scctx->isc_txrx->ift_rxd_flush);
5404 iflib_register(if_ctx_t ctx)
5406 if_shared_ctx_t sctx = ctx->ifc_sctx;
5407 driver_t *driver = sctx->isc_driver;
5408 device_t dev = ctx->ifc_dev;
5413 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5414 _iflib_assert(sctx);
5417 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5418 if (sctx->isc_flags & IFLIB_PSEUDO) {
5419 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5425 ifp = ctx->ifc_ifp = if_alloc(type);
5427 device_printf(dev, "can not allocate ifnet structure\n");
5432 * Initialize our context's device specific methods
5434 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5435 kobj_class_compile((kobj_class_t) driver);
5437 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5438 if_setsoftc(ifp, ctx);
5439 if_setdev(ifp, dev);
5440 if_setinitfn(ifp, iflib_if_init);
5441 if_setioctlfn(ifp, iflib_if_ioctl);
5443 if_setstartfn(ifp, iflib_altq_if_start);
5444 if_settransmitfn(ifp, iflib_altq_if_transmit);
5445 if_setsendqready(ifp);
5447 if_settransmitfn(ifp, iflib_if_transmit);
5449 if_setqflushfn(ifp, iflib_if_qflush);
5450 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5452 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5453 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5454 iflags |= IFF_POINTOPOINT;
5456 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5457 if_setflags(ifp, iflags);
5458 ctx->ifc_vlan_attach_event =
5459 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5460 EVENTHANDLER_PRI_FIRST);
5461 ctx->ifc_vlan_detach_event =
5462 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5463 EVENTHANDLER_PRI_FIRST);
5465 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5466 ctx->ifc_mediap = &ctx->ifc_media;
5467 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5468 iflib_media_change, iflib_media_status);
5474 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5476 /* Unregister VLAN events */
5477 if (ctx->ifc_vlan_attach_event != NULL) {
5478 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5479 ctx->ifc_vlan_attach_event = NULL;
5481 if (ctx->ifc_vlan_detach_event != NULL) {
5482 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5483 ctx->ifc_vlan_detach_event = NULL;
5489 iflib_deregister(if_ctx_t ctx)
5491 if_t ifp = ctx->ifc_ifp;
5493 /* Remove all media */
5494 ifmedia_removeall(&ctx->ifc_media);
5496 /* Ensure that VLAN event handlers are unregistered */
5497 iflib_unregister_vlan_handlers(ctx);
5499 /* Release kobject reference */
5500 kobj_delete((kobj_t) ctx, NULL);
5502 /* Free the ifnet structure */
5505 STATE_LOCK_DESTROY(ctx);
5507 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5508 CTX_LOCK_DESTROY(ctx);
5512 iflib_queues_alloc(if_ctx_t ctx)
5514 if_shared_ctx_t sctx = ctx->ifc_sctx;
5515 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5516 device_t dev = ctx->ifc_dev;
5517 int nrxqsets = scctx->isc_nrxqsets;
5518 int ntxqsets = scctx->isc_ntxqsets;
5521 iflib_fl_t fl = NULL;
5522 int i, j, cpu, err, txconf, rxconf;
5523 iflib_dma_info_t ifdip;
5524 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5525 uint32_t *txqsizes = scctx->isc_txqsizes;
5526 uint8_t nrxqs = sctx->isc_nrxqs;
5527 uint8_t ntxqs = sctx->isc_ntxqs;
5528 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5532 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5533 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5535 /* Allocate the TX ring struct memory */
5536 if (!(ctx->ifc_txqs =
5537 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5538 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5539 device_printf(dev, "Unable to allocate TX ring memory\n");
5544 /* Now allocate the RX */
5545 if (!(ctx->ifc_rxqs =
5546 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5547 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5548 device_printf(dev, "Unable to allocate RX ring memory\n");
5553 txq = ctx->ifc_txqs;
5554 rxq = ctx->ifc_rxqs;
5557 * XXX handle allocation failure
5559 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5560 /* Set up some basics */
5562 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5563 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5565 "Unable to allocate TX DMA info memory\n");
5569 txq->ift_ifdi = ifdip;
5570 for (j = 0; j < ntxqs; j++, ifdip++) {
5571 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5573 "Unable to allocate TX descriptors\n");
5577 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5578 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5582 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5583 txq->ift_br_offset = 1;
5585 txq->ift_br_offset = 0;
5588 txq->ift_timer.c_cpu = cpu;
5590 if (iflib_txsd_alloc(txq)) {
5591 device_printf(dev, "Critical Failure setting up TX buffers\n");
5596 /* Initialize the TX lock */
5597 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5598 device_get_nameunit(dev), txq->ift_id);
5599 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5600 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5602 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5603 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5605 /* XXX free any allocated rings */
5606 device_printf(dev, "Unable to allocate buf_ring\n");
5611 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5612 /* Set up some basics */
5613 callout_init(&rxq->ifr_watchdog, 1);
5615 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5616 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5618 "Unable to allocate RX DMA info memory\n");
5623 rxq->ifr_ifdi = ifdip;
5624 /* XXX this needs to be changed if #rx queues != #tx queues */
5625 rxq->ifr_ntxqirq = 1;
5626 rxq->ifr_txqid[0] = i;
5627 for (j = 0; j < nrxqs; j++, ifdip++) {
5628 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5630 "Unable to allocate RX descriptors\n");
5634 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5638 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5639 rxq->ifr_fl_offset = 1;
5641 rxq->ifr_fl_offset = 0;
5643 rxq->ifr_nfl = nfree_lists;
5645 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5646 device_printf(dev, "Unable to allocate free list memory\n");
5651 for (j = 0; j < nfree_lists; j++) {
5652 fl[j].ifl_rxq = rxq;
5654 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5655 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5657 /* Allocate receive buffers for the ring */
5658 if (iflib_rxsd_alloc(rxq)) {
5660 "Critical Failure setting up receive buffers\n");
5665 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5666 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5671 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5672 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5673 for (i = 0; i < ntxqsets; i++) {
5674 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5676 for (j = 0; j < ntxqs; j++, di++) {
5677 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5678 paddrs[i*ntxqs + j] = di->idi_paddr;
5681 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5682 device_printf(ctx->ifc_dev,
5683 "Unable to allocate device TX queue\n");
5684 iflib_tx_structures_free(ctx);
5685 free(vaddrs, M_IFLIB);
5686 free(paddrs, M_IFLIB);
5689 free(vaddrs, M_IFLIB);
5690 free(paddrs, M_IFLIB);
5693 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5694 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5695 for (i = 0; i < nrxqsets; i++) {
5696 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5698 for (j = 0; j < nrxqs; j++, di++) {
5699 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5700 paddrs[i*nrxqs + j] = di->idi_paddr;
5703 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5704 device_printf(ctx->ifc_dev,
5705 "Unable to allocate device RX queue\n");
5706 iflib_tx_structures_free(ctx);
5707 free(vaddrs, M_IFLIB);
5708 free(paddrs, M_IFLIB);
5711 free(vaddrs, M_IFLIB);
5712 free(paddrs, M_IFLIB);
5716 /* XXX handle allocation failure changes */
5720 if (ctx->ifc_rxqs != NULL)
5721 free(ctx->ifc_rxqs, M_IFLIB);
5722 ctx->ifc_rxqs = NULL;
5723 if (ctx->ifc_txqs != NULL)
5724 free(ctx->ifc_txqs, M_IFLIB);
5725 ctx->ifc_txqs = NULL;
5731 iflib_tx_structures_setup(if_ctx_t ctx)
5733 iflib_txq_t txq = ctx->ifc_txqs;
5736 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5737 iflib_txq_setup(txq);
5743 iflib_tx_structures_free(if_ctx_t ctx)
5745 iflib_txq_t txq = ctx->ifc_txqs;
5746 if_shared_ctx_t sctx = ctx->ifc_sctx;
5749 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5750 for (j = 0; j < sctx->isc_ntxqs; j++)
5751 iflib_dma_free(&txq->ift_ifdi[j]);
5752 iflib_txq_destroy(txq);
5754 free(ctx->ifc_txqs, M_IFLIB);
5755 ctx->ifc_txqs = NULL;
5756 IFDI_QUEUES_FREE(ctx);
5759 /*********************************************************************
5761 * Initialize all receive rings.
5763 **********************************************************************/
5765 iflib_rx_structures_setup(if_ctx_t ctx)
5767 iflib_rxq_t rxq = ctx->ifc_rxqs;
5769 #if defined(INET6) || defined(INET)
5773 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5774 #if defined(INET6) || defined(INET)
5775 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5776 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5777 TCP_LRO_ENTRIES, min(1024,
5778 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5780 device_printf(ctx->ifc_dev,
5781 "LRO Initialization failed!\n");
5786 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5789 #if defined(INET6) || defined(INET)
5792 * Free LRO resources allocated so far, we will only handle
5793 * the rings that completed, the failing case will have
5794 * cleaned up for itself. 'q' failed, so its the terminus.
5796 rxq = ctx->ifc_rxqs;
5797 for (i = 0; i < q; ++i, rxq++) {
5798 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5799 tcp_lro_free(&rxq->ifr_lc);
5805 /*********************************************************************
5807 * Free all receive rings.
5809 **********************************************************************/
5811 iflib_rx_structures_free(if_ctx_t ctx)
5813 iflib_rxq_t rxq = ctx->ifc_rxqs;
5814 if_shared_ctx_t sctx = ctx->ifc_sctx;
5817 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5818 for (j = 0; j < sctx->isc_nrxqs; j++)
5819 iflib_dma_free(&rxq->ifr_ifdi[j]);
5820 iflib_rx_sds_free(rxq);
5821 #if defined(INET6) || defined(INET)
5822 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5823 tcp_lro_free(&rxq->ifr_lc);
5826 free(ctx->ifc_rxqs, M_IFLIB);
5827 ctx->ifc_rxqs = NULL;
5831 iflib_qset_structures_setup(if_ctx_t ctx)
5836 * It is expected that the caller takes care of freeing queues if this
5839 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5840 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5844 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5845 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5851 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5852 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5855 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5860 find_nth(if_ctx_t ctx, int qid)
5863 int i, cpuid, eqid, count;
5865 CPU_COPY(&ctx->ifc_cpus, &cpus);
5866 count = CPU_COUNT(&cpus);
5868 /* clear up to the qid'th bit */
5869 for (i = 0; i < eqid; i++) {
5870 cpuid = CPU_FFS(&cpus);
5872 CPU_CLR(cpuid-1, &cpus);
5874 cpuid = CPU_FFS(&cpus);
5880 extern struct cpu_group *cpu_top; /* CPU topology */
5883 find_child_with_core(int cpu, struct cpu_group *grp)
5887 if (grp->cg_children == 0)
5890 MPASS(grp->cg_child);
5891 for (i = 0; i < grp->cg_children; i++) {
5892 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5900 * Find the nth "close" core to the specified core
5901 * "close" is defined as the deepest level that shares
5902 * at least an L2 cache. With threads, this will be
5903 * threads on the same core. If the shared cache is L3
5904 * or higher, simply returns the same core.
5907 find_close_core(int cpu, int core_offset)
5909 struct cpu_group *grp;
5918 while ((i = find_child_with_core(cpu, grp)) != -1) {
5919 /* If the child only has one cpu, don't descend */
5920 if (grp->cg_child[i].cg_count <= 1)
5922 grp = &grp->cg_child[i];
5925 /* If they don't share at least an L2 cache, use the same CPU */
5926 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5930 CPU_COPY(&grp->cg_mask, &cs);
5932 /* Add the selected CPU offset to core offset. */
5933 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5934 if (fcpu - 1 == cpu)
5936 CPU_CLR(fcpu - 1, &cs);
5942 CPU_COPY(&grp->cg_mask, &cs);
5943 for (i = core_offset % grp->cg_count; i > 0; i--) {
5944 MPASS(CPU_FFS(&cs));
5945 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5947 MPASS(CPU_FFS(&cs));
5948 return CPU_FFS(&cs) - 1;
5952 find_close_core(int cpu, int core_offset __unused)
5959 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5963 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5964 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5965 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5967 case IFLIB_INTR_RXTX:
5968 /* RX queues get the specified core */
5969 return qid / CPU_COUNT(&ctx->ifc_cpus);
5975 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5976 #define find_close_core(cpuid, tid) CPU_FIRST()
5977 #define find_nth(ctx, gid) CPU_FIRST()
5980 /* Just to avoid copy/paste */
5982 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5983 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5987 int co, cpuid, err, tid;
5990 co = ctx->ifc_sysctl_core_offset;
5991 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5992 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5993 cpuid = find_nth(ctx, qid + co);
5994 tid = get_core_offset(ctx, type, qid);
5996 device_printf(dev, "get_core_offset failed\n");
5997 return (EOPNOTSUPP);
5999 cpuid = find_close_core(cpuid, tid);
6000 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
6003 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6007 if (cpuid > ctx->ifc_cpuid_highest)
6008 ctx->ifc_cpuid_highest = cpuid;
6014 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6015 iflib_intr_type_t type, driver_filter_t *filter,
6016 void *filter_arg, int qid, const char *name)
6019 struct grouptask *gtask;
6020 struct taskqgroup *tqg;
6021 iflib_filter_info_t info;
6024 driver_filter_t *intr_fast;
6027 info = &ctx->ifc_filter_info;
6031 /* XXX merge tx/rx for netmap? */
6033 q = &ctx->ifc_txqs[qid];
6034 info = &ctx->ifc_txqs[qid].ift_filter_info;
6035 gtask = &ctx->ifc_txqs[qid].ift_task;
6036 tqg = qgroup_if_io_tqg;
6038 intr_fast = iflib_fast_intr;
6039 GROUPTASK_INIT(gtask, 0, fn, q);
6040 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6043 q = &ctx->ifc_rxqs[qid];
6044 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6045 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6046 tqg = qgroup_if_io_tqg;
6048 intr_fast = iflib_fast_intr;
6049 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6051 case IFLIB_INTR_RXTX:
6052 q = &ctx->ifc_rxqs[qid];
6053 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6054 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6055 tqg = qgroup_if_io_tqg;
6057 intr_fast = iflib_fast_intr_rxtx;
6058 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6060 case IFLIB_INTR_ADMIN:
6063 info = &ctx->ifc_filter_info;
6064 gtask = &ctx->ifc_admin_task;
6065 tqg = qgroup_if_config_tqg;
6066 fn = _task_fn_admin;
6067 intr_fast = iflib_fast_intr_ctx;
6070 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6075 info->ifi_filter = filter;
6076 info->ifi_filter_arg = filter_arg;
6077 info->ifi_task = gtask;
6081 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6083 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6086 if (type == IFLIB_INTR_ADMIN)
6090 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6095 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6102 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6104 struct grouptask *gtask;
6105 struct taskqgroup *tqg;
6112 q = &ctx->ifc_txqs[qid];
6113 gtask = &ctx->ifc_txqs[qid].ift_task;
6114 tqg = qgroup_if_io_tqg;
6116 GROUPTASK_INIT(gtask, 0, fn, q);
6119 q = &ctx->ifc_rxqs[qid];
6120 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6121 tqg = qgroup_if_io_tqg;
6123 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6125 case IFLIB_INTR_IOV:
6127 gtask = &ctx->ifc_vflr_task;
6128 tqg = qgroup_if_config_tqg;
6130 GROUPTASK_INIT(gtask, 0, fn, q);
6133 panic("unknown net intr type");
6136 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6139 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6142 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6147 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6151 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6154 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6155 rman_get_rid(irq->ii_res), irq->ii_res);
6159 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6161 iflib_txq_t txq = ctx->ifc_txqs;
6162 iflib_rxq_t rxq = ctx->ifc_rxqs;
6163 if_irq_t irq = &ctx->ifc_legacy_irq;
6164 iflib_filter_info_t info;
6166 struct grouptask *gtask;
6167 struct resource *res;
6168 struct taskqgroup *tqg;
6173 q = &ctx->ifc_rxqs[0];
6174 info = &rxq[0].ifr_filter_info;
6175 gtask = &rxq[0].ifr_task;
6176 tqg = qgroup_if_io_tqg;
6178 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6180 ctx->ifc_flags |= IFC_LEGACY;
6181 info->ifi_filter = filter;
6182 info->ifi_filter_arg = filter_arg;
6183 info->ifi_task = gtask;
6184 info->ifi_ctx = rx_only ? ctx : q;
6187 /* We allocate a single interrupt resource */
6188 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6189 iflib_fast_intr_rxtx, NULL, info, name);
6192 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6194 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6196 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6197 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6203 iflib_led_create(if_ctx_t ctx)
6206 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6207 device_get_nameunit(ctx->ifc_dev));
6211 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6214 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6218 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6221 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6225 iflib_admin_intr_deferred(if_ctx_t ctx)
6228 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6229 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6233 iflib_iov_intr_deferred(if_ctx_t ctx)
6236 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6240 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6243 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6248 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6252 GROUPTASK_INIT(gtask, 0, fn, ctx);
6253 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6258 iflib_config_gtask_deinit(struct grouptask *gtask)
6261 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6265 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6267 if_t ifp = ctx->ifc_ifp;
6268 iflib_txq_t txq = ctx->ifc_txqs;
6270 if_setbaudrate(ifp, baudrate);
6271 if (baudrate >= IF_Gbps(10)) {
6273 ctx->ifc_flags |= IFC_PREFETCH;
6276 /* If link down, disable watchdog */
6277 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6278 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6279 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6281 ctx->ifc_link_state = link_state;
6282 if_link_state_change(ifp, link_state);
6286 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6290 int credits_pre = txq->ift_cidx_processed;
6293 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6294 BUS_DMASYNC_POSTREAD);
6295 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6298 txq->ift_processed += credits;
6299 txq->ift_cidx_processed += credits;
6301 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6302 if (txq->ift_cidx_processed >= txq->ift_size)
6303 txq->ift_cidx_processed -= txq->ift_size;
6308 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6313 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6314 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6315 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6316 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6321 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6322 const char *description, if_int_delay_info_t info,
6323 int offset, int value)
6325 info->iidi_ctx = ctx;
6326 info->iidi_offset = offset;
6327 info->iidi_value = value;
6328 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6329 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6330 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6331 info, 0, iflib_sysctl_int_delay, "I", description);
6335 iflib_ctx_lock_get(if_ctx_t ctx)
6338 return (&ctx->ifc_ctx_sx);
6342 iflib_msix_init(if_ctx_t ctx)
6344 device_t dev = ctx->ifc_dev;
6345 if_shared_ctx_t sctx = ctx->ifc_sctx;
6346 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6347 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6348 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6350 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6351 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6354 device_printf(dev, "msix_init qsets capped at %d\n",
6355 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6357 /* Override by tuneable */
6358 if (scctx->isc_disable_msix)
6361 /* First try MSI-X */
6362 if ((msgs = pci_msix_count(dev)) == 0) {
6364 device_printf(dev, "MSI-X not supported or disabled\n");
6368 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6370 * bar == -1 => "trust me I know what I'm doing"
6371 * Some drivers are for hardware that is so shoddily
6372 * documented that no one knows which bars are which
6373 * so the developer has to map all bars. This hack
6374 * allows shoddy garbage to use MSI-X in this framework.
6377 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6378 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6379 if (ctx->ifc_msix_mem == NULL) {
6380 device_printf(dev, "Unable to map MSI-X table\n");
6385 admincnt = sctx->isc_admin_intrcnt;
6387 /* use only 1 qset in debug mode */
6388 queuemsgs = min(msgs - admincnt, 1);
6390 queuemsgs = msgs - admincnt;
6393 queues = imin(queuemsgs, rss_getnumbuckets());
6397 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6400 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6401 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6403 /* If we're doing RSS, clamp at the number of RSS buckets */
6404 if (queues > rss_getnumbuckets())
6405 queues = rss_getnumbuckets();
6407 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6408 rx_queues = iflib_num_rx_queues;
6412 if (rx_queues > scctx->isc_nrxqsets)
6413 rx_queues = scctx->isc_nrxqsets;
6416 * We want this to be all logical CPUs by default
6418 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6419 tx_queues = iflib_num_tx_queues;
6421 tx_queues = mp_ncpus;
6423 if (tx_queues > scctx->isc_ntxqsets)
6424 tx_queues = scctx->isc_ntxqsets;
6426 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6428 if (tx_queues != rx_queues)
6430 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6431 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6433 tx_queues = min(rx_queues, tx_queues);
6434 rx_queues = min(rx_queues, tx_queues);
6437 vectors = rx_queues + admincnt;
6438 if (msgs < vectors) {
6440 "insufficient number of MSI-X vectors "
6441 "(supported %d, need %d)\n", msgs, vectors);
6445 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6448 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6449 if (vectors != msgs) {
6451 "Unable to allocate sufficient MSI-X vectors "
6452 "(got %d, need %d)\n", vectors, msgs);
6453 pci_release_msi(dev);
6455 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6457 ctx->ifc_msix_mem = NULL;
6461 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6463 scctx->isc_vectors = vectors;
6464 scctx->isc_nrxqsets = rx_queues;
6465 scctx->isc_ntxqsets = tx_queues;
6466 scctx->isc_intr = IFLIB_INTR_MSIX;
6471 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6474 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6476 ctx->ifc_msix_mem = NULL;
6481 vectors = pci_msi_count(dev);
6482 scctx->isc_nrxqsets = 1;
6483 scctx->isc_ntxqsets = 1;
6484 scctx->isc_vectors = vectors;
6485 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6486 device_printf(dev,"Using an MSI interrupt\n");
6487 scctx->isc_intr = IFLIB_INTR_MSI;
6489 scctx->isc_vectors = 1;
6490 device_printf(dev,"Using a Legacy interrupt\n");
6491 scctx->isc_intr = IFLIB_INTR_LEGACY;
6497 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6500 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6503 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6505 const char *ring_state = "UNKNOWN";
6508 rc = sysctl_wire_old_buffer(req, 0);
6512 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6517 ring_state = ring_states[state[3]];
6519 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6520 state[0], state[1], state[2], ring_state);
6521 rc = sbuf_finish(sb);
6526 enum iflib_ndesc_handler {
6532 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6534 if_ctx_t ctx = (void *)arg1;
6535 enum iflib_ndesc_handler type = arg2;
6536 char buf[256] = {0};
6543 case IFLIB_NTXD_HANDLER:
6544 ndesc = ctx->ifc_sysctl_ntxds;
6546 nqs = ctx->ifc_sctx->isc_ntxqs;
6548 case IFLIB_NRXD_HANDLER:
6549 ndesc = ctx->ifc_sysctl_nrxds;
6551 nqs = ctx->ifc_sctx->isc_nrxqs;
6554 printf("%s: unhandled type\n", __func__);
6560 for (i=0; i<8; i++) {
6565 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6568 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6569 if (rc || req->newptr == NULL)
6572 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6573 i++, p = strsep(&next, " ,")) {
6574 ndesc[i] = strtoul(p, NULL, 10);
6580 #define NAME_BUFLEN 32
6582 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6584 device_t dev = iflib_get_dev(ctx);
6585 struct sysctl_oid_list *child, *oid_list;
6586 struct sysctl_ctx_list *ctx_list;
6587 struct sysctl_oid *node;
6589 ctx_list = device_get_sysctl_ctx(dev);
6590 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6591 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6592 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6593 oid_list = SYSCTL_CHILDREN(node);
6595 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6596 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6599 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6600 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6601 "# of txqs to use, 0 => use default #");
6602 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6603 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6604 "# of rxqs to use, 0 => use default #");
6605 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6606 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6607 "permit #txq != #rxq");
6608 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6609 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6610 "disable MSI-X (default 0)");
6611 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6612 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6613 "set the RX budget");
6614 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6615 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6616 "cause TX to abdicate instead of running to completion");
6617 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6618 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6619 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6620 "offset to start using cores at");
6621 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6622 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6623 "use separate cores for TX and RX");
6625 /* XXX change for per-queue sizes */
6626 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6627 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6628 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6629 "list of # of TX descriptors to use, 0 = use default #");
6630 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6631 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6632 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6633 "list of # of RX descriptors to use, 0 = use default #");
6637 iflib_add_device_sysctl_post(if_ctx_t ctx)
6639 if_shared_ctx_t sctx = ctx->ifc_sctx;
6640 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6641 device_t dev = iflib_get_dev(ctx);
6642 struct sysctl_oid_list *child;
6643 struct sysctl_ctx_list *ctx_list;
6648 char namebuf[NAME_BUFLEN];
6650 struct sysctl_oid *queue_node, *fl_node, *node;
6651 struct sysctl_oid_list *queue_list, *fl_list;
6652 ctx_list = device_get_sysctl_ctx(dev);
6654 node = ctx->ifc_sysctl_node;
6655 child = SYSCTL_CHILDREN(node);
6657 if (scctx->isc_ntxqsets > 100)
6659 else if (scctx->isc_ntxqsets > 10)
6663 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6664 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6665 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6666 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6667 queue_list = SYSCTL_CHILDREN(queue_node);
6669 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6671 &txq->ift_dequeued, "total mbufs freed");
6672 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6674 &txq->ift_enqueued, "total mbufs enqueued");
6676 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6678 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6679 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6681 &txq->ift_pullups, "# of times m_pullup was called");
6682 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6684 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6685 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6687 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6688 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6690 &txq->ift_map_failed, "# of times DMA map failed");
6691 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6693 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6694 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6696 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6697 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6699 &txq->ift_pidx, 1, "Producer Index");
6700 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6702 &txq->ift_cidx, 1, "Consumer Index");
6703 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6705 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6706 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6708 &txq->ift_in_use, 1, "descriptors in use");
6709 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6711 &txq->ift_processed, "descriptors procesed for clean");
6712 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6714 &txq->ift_cleaned, "total cleaned");
6715 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6716 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6717 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6718 mp_ring_state_handler, "A", "soft ring state");
6719 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6720 CTLFLAG_RD, &txq->ift_br->enqueues,
6721 "# of enqueues to the mp_ring for this queue");
6722 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6723 CTLFLAG_RD, &txq->ift_br->drops,
6724 "# of drops in the mp_ring for this queue");
6725 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6726 CTLFLAG_RD, &txq->ift_br->starts,
6727 "# of normal consumer starts in the mp_ring for this queue");
6728 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6729 CTLFLAG_RD, &txq->ift_br->stalls,
6730 "# of consumer stalls in the mp_ring for this queue");
6731 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6732 CTLFLAG_RD, &txq->ift_br->restarts,
6733 "# of consumer restarts in the mp_ring for this queue");
6734 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6735 CTLFLAG_RD, &txq->ift_br->abdications,
6736 "# of consumer abdications in the mp_ring for this queue");
6739 if (scctx->isc_nrxqsets > 100)
6741 else if (scctx->isc_nrxqsets > 10)
6745 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6746 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6747 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6748 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6749 queue_list = SYSCTL_CHILDREN(queue_node);
6750 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6751 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6753 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6756 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6757 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6758 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6759 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6760 fl_list = SYSCTL_CHILDREN(fl_node);
6761 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6763 &fl->ifl_pidx, 1, "Producer Index");
6764 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6766 &fl->ifl_cidx, 1, "Consumer Index");
6767 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6769 &fl->ifl_credits, 1, "credits available");
6770 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6772 &fl->ifl_buf_size, 1, "buffer size");
6774 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6776 &fl->ifl_m_enqueued, "mbufs allocated");
6777 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6779 &fl->ifl_m_dequeued, "mbufs freed");
6780 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6782 &fl->ifl_cl_enqueued, "clusters allocated");
6783 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6785 &fl->ifl_cl_dequeued, "clusters freed");
6794 iflib_request_reset(if_ctx_t ctx)
6798 ctx->ifc_flags |= IFC_DO_RESET;
6802 #ifndef __NO_STRICT_ALIGNMENT
6803 static struct mbuf *
6804 iflib_fixup_rx(struct mbuf *m)
6808 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6809 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6810 m->m_data += ETHER_HDR_LEN;
6813 MGETHDR(n, M_NOWAIT, MT_DATA);
6818 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6819 m->m_data += ETHER_HDR_LEN;
6820 m->m_len -= ETHER_HDR_LEN;
6821 n->m_len = ETHER_HDR_LEN;
6822 M_MOVE_PKTHDR(n, m);
6831 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6835 ctx = if_getsoftc(ifp);
6837 *nrxr = NRXQSETS(ctx);
6838 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6839 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6844 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6847 if_softc_ctx_t scctx;
6852 ctx = if_getsoftc(ifp);
6853 scctx = &ctx->ifc_softc_ctx;
6856 case DEBUGNET_START:
6857 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6858 rxq = &ctx->ifc_rxqs[i];
6859 for (j = 0; j < rxq->ifr_nfl; j++) {
6861 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6864 iflib_no_tx_batch = 1;
6872 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6878 ctx = if_getsoftc(ifp);
6879 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6883 txq = &ctx->ifc_txqs[0];
6884 error = iflib_encap(txq, &m);
6886 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6891 iflib_debugnet_poll(if_t ifp, int count)
6893 struct epoch_tracker et;
6895 if_softc_ctx_t scctx;
6899 ctx = if_getsoftc(ifp);
6900 scctx = &ctx->ifc_softc_ctx;
6902 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6906 txq = &ctx->ifc_txqs[0];
6907 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6909 NET_EPOCH_ENTER(et);
6910 for (i = 0; i < scctx->isc_nrxqsets; i++)
6911 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6915 #endif /* DEBUGNET */