2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
212 eventhandler_tag ifc_vlan_attach_event;
213 eventhandler_tag ifc_vlan_detach_event;
214 struct ether_addr ifc_mac;
218 iflib_get_softc(if_ctx_t ctx)
221 return (ctx->ifc_softc);
225 iflib_get_dev(if_ctx_t ctx)
228 return (ctx->ifc_dev);
232 iflib_get_ifp(if_ctx_t ctx)
235 return (ctx->ifc_ifp);
239 iflib_get_media(if_ctx_t ctx)
242 return (ctx->ifc_mediap);
246 iflib_get_flags(if_ctx_t ctx)
248 return (ctx->ifc_flags);
252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
259 iflib_get_softc_ctx(if_ctx_t ctx)
262 return (&ctx->ifc_softc_ctx);
266 iflib_get_sctx(if_ctx_t ctx)
269 return (ctx->ifc_sctx);
272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
289 struct mbuf **ifsd_m; /* pkthdr mbufs */
292 /* magic number that should be high enough for any hardware */
293 #define IFLIB_MAX_TX_SEGS 128
294 #define IFLIB_RX_COPY_THRESH 128
295 #define IFLIB_MAX_RX_REFRESH 32
296 /* The minimum descriptors per second before we start coalescing */
297 #define IFLIB_MIN_DESC_SEC 16384
298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
299 #define IFLIB_QUEUE_IDLE 0
300 #define IFLIB_QUEUE_HUNG 1
301 #define IFLIB_QUEUE_WORKING 2
302 /* maximum number of txqs that can share an rx interrupt */
303 #define IFLIB_MAX_TX_SHARED_INTR 4
305 /* this should really scale with ring size - this is a fairly arbitrary value */
306 #define TX_BATCH_SIZE 32
308 #define IFLIB_RESTART_BUDGET 8
310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
317 qidx_t ift_cidx_processed;
320 uint8_t ift_br_offset;
321 uint16_t ift_npending;
322 uint16_t ift_db_pending;
323 uint16_t ift_rs_pending;
325 uint8_t ift_txd_size[8];
326 uint64_t ift_processed;
327 uint64_t ift_cleaned;
328 uint64_t ift_cleaned_prev;
330 uint64_t ift_enqueued;
331 uint64_t ift_dequeued;
333 uint64_t ift_no_tx_dma_setup;
334 uint64_t ift_no_desc_avail;
335 uint64_t ift_mbuf_defrag_failed;
336 uint64_t ift_mbuf_defrag;
337 uint64_t ift_map_failed;
338 uint64_t ift_txd_encap_efbig;
339 uint64_t ift_pullups;
340 uint64_t ift_last_timer_tick;
343 struct mtx ift_db_mtx;
345 /* constant values */
347 struct ifmp_ring *ift_br;
348 struct grouptask ift_task;
351 struct callout ift_timer;
353 if_txsd_vec_t ift_sds;
356 uint8_t ift_update_freq;
357 struct iflib_filter_info ift_filter_info;
358 bus_dma_tag_t ift_buf_tag;
359 bus_dma_tag_t ift_tso_buf_tag;
360 iflib_dma_info_t ift_ifdi;
361 #define MTX_NAME_LEN 16
362 char ift_mtx_name[MTX_NAME_LEN];
363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
364 #ifdef IFLIB_DIAGNOSTICS
365 uint64_t ift_cpu_exec_count[256];
367 } __aligned(CACHE_LINE_SIZE);
374 uint8_t ifl_rxd_size;
376 uint64_t ifl_m_enqueued;
377 uint64_t ifl_m_dequeued;
378 uint64_t ifl_cl_enqueued;
379 uint64_t ifl_cl_dequeued;
382 bitstr_t *ifl_rx_bitmap;
386 uint16_t ifl_buf_size;
389 iflib_rxsd_array_t ifl_sds;
392 bus_dma_tag_t ifl_buf_tag;
393 iflib_dma_info_t ifl_ifdi;
394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 } __aligned(CACHE_LINE_SIZE);
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
406 else if (pidx < cidx)
407 used = size - cidx + pidx;
408 else if (gen == 0 && pidx == cidx)
410 else if (gen == 1 && pidx == cidx)
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
420 #define IDXDIFF(head, tail, wrap) \
421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
427 struct pfil_head *pfil;
429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
430 * the command queue consumer index. Otherwise it's unused.
436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
437 uint8_t ifr_fl_offset;
438 struct lro_ctrl ifr_lc;
439 struct grouptask ifr_task;
440 struct callout ifr_watchdog;
441 struct iflib_filter_info ifr_filter_info;
442 iflib_dma_info_t ifr_ifdi;
444 /* dynamically allocate if any drivers need a value substantially larger than this */
445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
446 #ifdef IFLIB_DIAGNOSTICS
447 uint64_t ifr_cpu_exec_count[256];
449 } __aligned(CACHE_LINE_SIZE);
451 typedef struct if_rxsd {
456 /* multiple of word size */
458 #define PKT_INFO_SIZE 6
459 #define RXD_INFO_SIZE 5
460 #define PKT_TYPE uint64_t
462 #define PKT_INFO_SIZE 11
463 #define RXD_INFO_SIZE 8
464 #define PKT_TYPE uint32_t
466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
469 typedef struct if_pkt_info_pad {
470 PKT_TYPE pkt_val[PKT_INFO_SIZE];
471 } *if_pkt_info_pad_t;
472 typedef struct if_rxd_info_pad {
473 PKT_TYPE rxd_val[RXD_INFO_SIZE];
474 } *if_rxd_info_pad_t;
476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
481 pkt_info_zero(if_pkt_info_t pi)
483 if_pkt_info_pad_t pi_pad;
485 pi_pad = (if_pkt_info_pad_t)pi;
486 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
487 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
489 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
490 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
494 static device_method_t iflib_pseudo_methods[] = {
495 DEVMETHOD(device_attach, noop_attach),
496 DEVMETHOD(device_detach, iflib_pseudo_detach),
500 driver_t iflib_pseudodriver = {
501 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
505 rxd_info_zero(if_rxd_info_t ri)
507 if_rxd_info_pad_t ri_pad;
510 ri_pad = (if_rxd_info_pad_t)ri;
511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
512 ri_pad->rxd_val[i] = 0;
513 ri_pad->rxd_val[i+1] = 0;
514 ri_pad->rxd_val[i+2] = 0;
515 ri_pad->rxd_val[i+3] = 0;
518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
523 * Only allow a single packet to take up most 1/nth of the tx ring
525 #define MAX_SINGLE_PACKET_FRACTION 12
526 #define IF_BAD_DMA (bus_addr_t)-1
528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
530 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
535 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
540 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
541 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
544 iflib_set_detach(if_ctx_t ctx)
547 ctx->ifc_flags |= IFC_IN_DETACH;
551 /* Our boot-time initialization hook */
552 static int iflib_module_event_handler(module_t, int, void *);
554 static moduledata_t iflib_moduledata = {
556 iflib_module_event_handler,
560 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
561 MODULE_VERSION(iflib, 1);
563 MODULE_DEPEND(iflib, pci, 1, 1, 1);
564 MODULE_DEPEND(iflib, ether, 1, 1, 1);
566 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
567 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
569 #ifndef IFLIB_DEBUG_COUNTERS
571 #define IFLIB_DEBUG_COUNTERS 1
573 #define IFLIB_DEBUG_COUNTERS 0
574 #endif /* !INVARIANTS */
577 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
578 "iflib driver parameters");
581 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
583 static int iflib_min_tx_latency = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
585 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
586 static int iflib_no_tx_batch = 0;
587 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
588 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
591 #if IFLIB_DEBUG_COUNTERS
593 static int iflib_tx_seen;
594 static int iflib_tx_sent;
595 static int iflib_tx_encap;
596 static int iflib_rx_allocs;
597 static int iflib_fl_refills;
598 static int iflib_fl_refills_large;
599 static int iflib_tx_frees;
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
602 &iflib_tx_seen, 0, "# TX mbufs seen");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
604 &iflib_tx_sent, 0, "# TX mbufs sent");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
606 &iflib_tx_encap, 0, "# TX mbufs encapped");
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
608 &iflib_tx_frees, 0, "# TX frees");
609 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
610 &iflib_rx_allocs, 0, "# RX allocations");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
612 &iflib_fl_refills, 0, "# refills");
613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
614 &iflib_fl_refills_large, 0, "# large refills");
617 static int iflib_txq_drain_flushing;
618 static int iflib_txq_drain_oactive;
619 static int iflib_txq_drain_notready;
621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
622 &iflib_txq_drain_flushing, 0, "# drain flushes");
623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
624 &iflib_txq_drain_oactive, 0, "# drain oactives");
625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
626 &iflib_txq_drain_notready, 0, "# drain notready");
629 static int iflib_encap_load_mbuf_fail;
630 static int iflib_encap_pad_mbuf_fail;
631 static int iflib_encap_txq_avail_fail;
632 static int iflib_encap_txd_encap_fail;
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
643 static int iflib_task_fn_rxs;
644 static int iflib_rx_intr_enables;
645 static int iflib_fast_intrs;
646 static int iflib_rx_unavail;
647 static int iflib_rx_ctx_inactive;
648 static int iflib_rx_if_input;
649 static int iflib_rxd_flush;
651 static int iflib_verbose_debug;
653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
656 &iflib_rx_intr_enables, 0, "# RX intr enables");
657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
658 &iflib_fast_intrs, 0, "# fast_intr calls");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
660 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
664 &iflib_rx_if_input, 0, "# times rxeof called if_input");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
666 &iflib_rxd_flush, 0, "# times rxd_flush called");
667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
668 &iflib_verbose_debug, 0, "enable verbose debugging");
670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
672 iflib_debug_reset(void)
674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
676 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
677 iflib_txq_drain_notready =
678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
682 iflib_rx_ctx_inactive = iflib_rx_if_input =
687 #define DBG_COUNTER_INC(name)
688 static void iflib_debug_reset(void) {}
691 #define IFLIB_DEBUG 0
693 static void iflib_tx_structures_free(if_ctx_t ctx);
694 static void iflib_rx_structures_free(if_ctx_t ctx);
695 static int iflib_queues_alloc(if_ctx_t ctx);
696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
698 static int iflib_qset_structures_setup(if_ctx_t ctx);
699 static int iflib_msix_init(if_ctx_t ctx);
700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
704 static void iflib_altq_if_start(if_t ifp);
705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
707 static int iflib_register(if_ctx_t);
708 static void iflib_deregister(if_ctx_t);
709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
710 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
711 static void iflib_init_locked(if_ctx_t ctx);
712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
713 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
714 static void iflib_ifmp_purge(iflib_txq_t txq);
715 static void _iflib_pre_assert(if_softc_ctx_t scctx);
716 static void iflib_if_init_locked(if_ctx_t ctx);
717 static void iflib_free_intr_mem(if_ctx_t ctx);
718 #ifndef __NO_STRICT_ALIGNMENT
719 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
723 SLIST_HEAD_INITIALIZER(cpu_offsets);
725 SLIST_ENTRY(cpu_offset) entries;
727 unsigned int refcount;
730 static struct mtx cpu_offset_mtx;
731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
734 DEBUGNET_DEFINE(iflib);
737 #include <sys/selinfo.h>
738 #include <net/netmap.h>
739 #include <dev/netmap/netmap_kern.h>
741 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
746 * device-specific sysctl variables:
748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
749 * During regular operations the CRC is stripped, but on some
750 * hardware reception of frames not multiple of 64 is slower,
751 * so using crcstrip=0 helps in benchmarks.
753 * iflib_rx_miss, iflib_rx_miss_bufs:
754 * count packets that might be missed due to lost interrupts.
756 SYSCTL_DECL(_dev_netmap);
758 * The xl driver by default strips CRCs and we do not override it.
761 int iflib_crcstrip = 1;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
765 int iflib_rx_miss, iflib_rx_miss_bufs;
766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
772 * Register/unregister. We are already under netmap lock.
773 * Only called on the first register or the last unregister.
776 iflib_netmap_register(struct netmap_adapter *na, int onoff)
779 if_ctx_t ctx = ifp->if_softc;
783 IFDI_INTR_DISABLE(ctx);
785 /* Tell the stack that the interface is no longer active */
786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
791 /* enable or disable flags and callbacks in na and ifp */
793 nm_set_native_flags(na);
795 nm_clear_native_flags(na);
798 iflib_init_locked(ctx);
799 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
800 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
802 nm_clear_native_flags(na);
808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
810 struct netmap_adapter *na = kring->na;
811 u_int const lim = kring->nkr_num_slots - 1;
812 u_int head = kring->rhead;
813 struct netmap_ring *ring = kring->ring;
815 struct if_rxd_update iru;
816 if_ctx_t ctx = rxq->ifr_ctx;
817 iflib_fl_t fl = &rxq->ifr_fl[0];
818 uint32_t refill_pidx, nic_i;
819 #if IFLIB_DEBUG_COUNTERS
823 if (nm_i == head && __predict_true(!init))
825 iru_init(&iru, rxq, 0 /* flid */);
826 map = fl->ifl_sds.ifsd_map;
827 refill_pidx = netmap_idx_k2n(kring, nm_i);
829 * IMPORTANT: we must leave one free slot in the ring,
830 * so move head back by one unit
832 head = nm_prev(head, lim);
834 DBG_COUNTER_INC(fl_refills);
835 while (nm_i != head) {
836 #if IFLIB_DEBUG_COUNTERS
838 DBG_COUNTER_INC(fl_refills_large);
840 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
841 struct netmap_slot *slot = &ring->slot[nm_i];
842 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
843 uint32_t nic_i_dma = refill_pidx;
844 nic_i = netmap_idx_k2n(kring, nm_i);
846 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
848 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
849 return netmap_ring_reinit(kring);
851 fl->ifl_vm_addrs[tmp_pidx] = addr;
852 if (__predict_false(init)) {
853 netmap_load_map(na, fl->ifl_buf_tag,
855 } else if (slot->flags & NS_BUF_CHANGED) {
856 /* buffer has changed, reload map */
857 netmap_reload_map(na, fl->ifl_buf_tag,
860 slot->flags &= ~NS_BUF_CHANGED;
862 nm_i = nm_next(nm_i, lim);
863 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
864 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
867 iru.iru_pidx = refill_pidx;
868 iru.iru_count = tmp_pidx+1;
869 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
871 for (int n = 0; n < iru.iru_count; n++) {
872 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
873 BUS_DMASYNC_PREREAD);
874 /* XXX - change this to not use the netmap func*/
875 nic_i_dma = nm_next(nic_i_dma, lim);
879 kring->nr_hwcur = head;
881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
883 if (__predict_true(nic_i != UINT_MAX)) {
884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
885 DBG_COUNTER_INC(rxd_flush);
891 * Reconcile kernel and user view of the transmit ring.
893 * All information is in the kring.
894 * Userspace wants to send packets up to the one before kring->rhead,
895 * kernel knows kring->nr_hwcur is the first unsent packet.
897 * Here we push packets out (as many as possible), and possibly
898 * reclaim buffers from previously completed transmission.
900 * The caller (netmap) guarantees that there is only one instance
901 * running at any time. Any interference with other driver
902 * methods should be handled by the individual drivers.
905 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
907 struct netmap_adapter *na = kring->na;
909 struct netmap_ring *ring = kring->ring;
910 u_int nm_i; /* index into the netmap kring */
911 u_int nic_i; /* index into the NIC ring */
913 u_int const lim = kring->nkr_num_slots - 1;
914 u_int const head = kring->rhead;
915 struct if_pkt_info pi;
918 * interrupts on every tx packet are expensive so request
919 * them every half ring, or where NS_REPORT is set
921 u_int report_frequency = kring->nkr_num_slots >> 1;
922 /* device-specific */
923 if_ctx_t ctx = ifp->if_softc;
924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
926 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
930 * First part: process new packets to send.
931 * nm_i is the current index in the netmap kring,
932 * nic_i is the corresponding index in the NIC ring.
934 * If we have packets to send (nm_i != head)
935 * iterate over the netmap ring, fetch length and update
936 * the corresponding slot in the NIC ring. Some drivers also
937 * need to update the buffer's physical address in the NIC slot
938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
940 * The netmap_reload_map() calls is especially expensive,
941 * even when (as in this case) the tag is 0, so do only
942 * when the buffer has actually changed.
944 * If possible do not set the report/intr bit on all slots,
945 * but only a few times per ring or when NS_REPORT is set.
947 * Finally, on 10G and faster drivers, it might be useful
948 * to prefetch the next slot and txr entry.
951 nm_i = kring->nr_hwcur;
952 if (nm_i != head) { /* we have new packets to send */
954 pi.ipi_segs = txq->ift_segs;
955 pi.ipi_qsidx = kring->ring_id;
956 nic_i = netmap_idx_k2n(kring, nm_i);
958 __builtin_prefetch(&ring->slot[nm_i]);
959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
962 for (n = 0; nm_i != head; n++) {
963 struct netmap_slot *slot = &ring->slot[nm_i];
964 u_int len = slot->len;
966 void *addr = PNMB(na, slot, &paddr);
967 int flags = (slot->flags & NS_REPORT ||
968 nic_i == 0 || nic_i == report_frequency) ?
971 /* device-specific */
973 pi.ipi_segs[0].ds_addr = paddr;
974 pi.ipi_segs[0].ds_len = len;
978 pi.ipi_flags = flags;
980 /* Fill the slot in the NIC ring. */
981 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
982 DBG_COUNTER_INC(tx_encap);
984 /* prefetch for next round */
985 __builtin_prefetch(&ring->slot[nm_i + 1]);
986 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
989 NM_CHECK_ADDR_LEN(na, addr, len);
991 if (slot->flags & NS_BUF_CHANGED) {
992 /* buffer has changed, reload map */
993 netmap_reload_map(na, txq->ift_buf_tag,
994 txq->ift_sds.ifsd_map[nic_i], addr);
996 /* make sure changes to the buffer are synced */
997 bus_dmamap_sync(txq->ift_buf_tag,
998 txq->ift_sds.ifsd_map[nic_i],
999 BUS_DMASYNC_PREWRITE);
1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1002 nm_i = nm_next(nm_i, lim);
1003 nic_i = nm_next(nic_i, lim);
1005 kring->nr_hwcur = nm_i;
1007 /* synchronize the NIC ring */
1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1011 /* (re)start the tx unit up to slot nic_i (excluded) */
1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1016 * Second part: reclaim buffers for completed transmissions.
1018 * If there are unclaimed buffers, attempt to reclaim them.
1019 * If none are reclaimed, and TX IRQs are not in use, do an initial
1020 * minimal delay, then trigger the tx handler which will spin in the
1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1024 if (iflib_tx_credits_update(ctx, txq)) {
1025 /* some tx completed, increment avail */
1026 nic_i = txq->ift_cidx_processed;
1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1033 iflib_timer, txq, txq->ift_timer.c_cpu);
1039 * Reconcile kernel and user view of the receive ring.
1040 * Same as for the txsync, this routine must be efficient.
1041 * The caller guarantees a single invocations, but races against
1042 * the rest of the driver should be handled here.
1044 * On call, kring->rhead is the first packet that userspace wants
1045 * to keep, and kring->rcur is the wakeup point.
1046 * The kernel has previously reported packets up to kring->rtail.
1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1049 * of whether or not we received an interrupt.
1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1054 struct netmap_adapter *na = kring->na;
1055 struct netmap_ring *ring = kring->ring;
1058 uint32_t nm_i; /* index into the netmap ring */
1059 uint32_t nic_i; /* index into the NIC ring */
1061 u_int const lim = kring->nkr_num_slots - 1;
1062 u_int const head = kring->rhead;
1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1064 struct if_rxd_info ri;
1066 if_ctx_t ctx = ifp->if_softc;
1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1069 return netmap_ring_reinit(kring);
1072 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1075 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1081 * First part: import newly received packets.
1083 * nm_i is the index of the next free slot in the netmap ring,
1084 * nic_i is the index of the next received packet in the NIC ring,
1085 * and they may differ in case if_init() has been called while
1086 * in netmap mode. For the receive ring we have
1088 * nic_i = rxr->next_check;
1089 * nm_i = kring->nr_hwtail (previous)
1091 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1093 * rxr->next_check is set to 0 on a ring reinit
1095 if (netmap_no_pendintr || force_update) {
1096 int crclen = iflib_crcstrip ? 0 : 4;
1099 for (i = 0; i < rxq->ifr_nfl; i++) {
1100 fl = &rxq->ifr_fl[i];
1101 nic_i = fl->ifl_cidx;
1102 nm_i = netmap_idx_n2k(kring, nic_i);
1103 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1104 rxq->ifr_id, nic_i, USHRT_MAX);
1105 for (n = 0; avail > 0; n++, avail--) {
1107 ri.iri_frags = rxq->ifr_frags;
1108 ri.iri_qsidx = kring->ring_id;
1109 ri.iri_ifp = ctx->ifc_ifp;
1110 ri.iri_cidx = nic_i;
1112 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1113 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1114 ring->slot[nm_i].flags = 0;
1115 bus_dmamap_sync(fl->ifl_buf_tag,
1116 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1117 nm_i = nm_next(nm_i, lim);
1118 nic_i = nm_next(nic_i, lim);
1120 if (n) { /* update the state variables */
1121 if (netmap_no_pendintr && !force_update) {
1124 iflib_rx_miss_bufs += n;
1126 fl->ifl_cidx = nic_i;
1127 kring->nr_hwtail = nm_i;
1129 kring->nr_kflags &= ~NKR_PENDINTR;
1133 * Second part: skip past packets that userspace has released.
1134 * (kring->nr_hwcur to head excluded),
1135 * and make the buffers available for reception.
1136 * As usual nm_i is the index in the netmap ring,
1137 * nic_i is the index in the NIC ring, and
1138 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1140 /* XXX not sure how this will work with multiple free lists */
1141 nm_i = kring->nr_hwcur;
1143 return (netmap_fl_refill(rxq, kring, nm_i, false));
1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1149 if_ctx_t ctx = na->ifp->if_softc;
1153 IFDI_INTR_ENABLE(ctx);
1155 IFDI_INTR_DISABLE(ctx);
1162 iflib_netmap_attach(if_ctx_t ctx)
1164 struct netmap_adapter na;
1165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1167 bzero(&na, sizeof(na));
1169 na.ifp = ctx->ifc_ifp;
1170 na.na_flags = NAF_BDG_MAYSLEEP;
1171 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1172 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1174 na.num_tx_desc = scctx->isc_ntxd[0];
1175 na.num_rx_desc = scctx->isc_nrxd[0];
1176 na.nm_txsync = iflib_netmap_txsync;
1177 na.nm_rxsync = iflib_netmap_rxsync;
1178 na.nm_register = iflib_netmap_register;
1179 na.nm_intr = iflib_netmap_intr;
1180 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1181 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1182 return (netmap_attach(&na));
1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1188 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1189 struct netmap_slot *slot;
1191 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1194 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1197 * In netmap mode, set the map for the packet buffer.
1198 * NOTE: Some drivers (not this one) also need to set
1199 * the physical buffer address in the NIC ring.
1200 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1201 * netmap slot index, si
1203 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1204 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1205 NMB(na, slot + si));
1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1212 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1213 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1214 struct netmap_slot *slot;
1217 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1220 nm_i = netmap_idx_n2k(kring, 0);
1221 netmap_fl_refill(rxq, kring, nm_i, true);
1225 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1227 struct netmap_kring *kring;
1230 txqid = txq->ift_id;
1231 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1233 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1234 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1235 BUS_DMASYNC_POSTREAD);
1236 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1237 netmap_tx_irq(ctx->ifc_ifp, txqid);
1238 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1242 *reset_on = hz / 1000;
1247 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1250 #define iflib_netmap_txq_init(ctx, txq)
1251 #define iflib_netmap_rxq_init(ctx, rxq)
1252 #define iflib_netmap_detach(ifp)
1254 #define iflib_netmap_attach(ctx) (0)
1255 #define netmap_rx_irq(ifp, qid, budget) (0)
1256 #define netmap_tx_irq(ifp, qid) do {} while (0)
1257 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1260 #if defined(__i386__) || defined(__amd64__)
1261 static __inline void
1264 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1266 static __inline void
1267 prefetch2cachelines(void *x)
1269 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1270 #if (CACHE_LINE_SIZE < 128)
1271 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1276 #define prefetch2cachelines(x)
1280 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1284 fl = &rxq->ifr_fl[flid];
1285 iru->iru_paddrs = fl->ifl_bus_addrs;
1286 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1287 iru->iru_idxs = fl->ifl_rxd_idxs;
1288 iru->iru_qsidx = rxq->ifr_id;
1289 iru->iru_buf_size = fl->ifl_buf_size;
1290 iru->iru_flidx = fl->ifl_id;
1294 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1298 *(bus_addr_t *) arg = segs[0].ds_addr;
1302 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1305 device_t dev = ctx->ifc_dev;
1307 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1308 align, 0, /* alignment, bounds */
1309 BUS_SPACE_MAXADDR, /* lowaddr */
1310 BUS_SPACE_MAXADDR, /* highaddr */
1311 NULL, NULL, /* filter, filterarg */
1314 size, /* maxsegsize */
1315 BUS_DMA_ALLOCNOW, /* flags */
1316 NULL, /* lockfunc */
1321 "%s: bus_dma_tag_create failed: %d\n",
1326 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1327 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1330 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1331 __func__, (uintmax_t)size, err);
1335 dma->idi_paddr = IF_BAD_DMA;
1336 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1337 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1338 if (err || dma->idi_paddr == IF_BAD_DMA) {
1340 "%s: bus_dmamap_load failed: %d\n",
1345 dma->idi_size = size;
1349 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1351 bus_dma_tag_destroy(dma->idi_tag);
1353 dma->idi_tag = NULL;
1359 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1361 if_shared_ctx_t sctx = ctx->ifc_sctx;
1363 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1365 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1369 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1372 iflib_dma_info_t *dmaiter;
1375 for (i = 0; i < count; i++, dmaiter++) {
1376 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1380 iflib_dma_free_multi(dmalist, i);
1385 iflib_dma_free(iflib_dma_info_t dma)
1387 if (dma->idi_tag == NULL)
1389 if (dma->idi_paddr != IF_BAD_DMA) {
1390 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1391 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1392 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1393 dma->idi_paddr = IF_BAD_DMA;
1395 if (dma->idi_vaddr != NULL) {
1396 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1397 dma->idi_vaddr = NULL;
1399 bus_dma_tag_destroy(dma->idi_tag);
1400 dma->idi_tag = NULL;
1404 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1407 iflib_dma_info_t *dmaiter = dmalist;
1409 for (i = 0; i < count; i++, dmaiter++)
1410 iflib_dma_free(*dmaiter);
1414 iflib_fast_intr(void *arg)
1416 iflib_filter_info_t info = arg;
1417 struct grouptask *gtask = info->ifi_task;
1420 DBG_COUNTER_INC(fast_intrs);
1421 if (info->ifi_filter != NULL) {
1422 result = info->ifi_filter(info->ifi_filter_arg);
1423 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1427 GROUPTASK_ENQUEUE(gtask);
1428 return (FILTER_HANDLED);
1432 iflib_fast_intr_rxtx(void *arg)
1434 iflib_filter_info_t info = arg;
1435 struct grouptask *gtask = info->ifi_task;
1437 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1440 int i, cidx, result;
1442 bool intr_enable, intr_legacy;
1444 DBG_COUNTER_INC(fast_intrs);
1445 if (info->ifi_filter != NULL) {
1446 result = info->ifi_filter(info->ifi_filter_arg);
1447 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1452 sc = ctx->ifc_softc;
1453 intr_enable = false;
1454 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1455 MPASS(rxq->ifr_ntxqirq);
1456 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1457 txqid = rxq->ifr_txqid[i];
1458 txq = &ctx->ifc_txqs[txqid];
1459 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1460 BUS_DMASYNC_POSTREAD);
1461 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1465 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1468 GROUPTASK_ENQUEUE(&txq->ift_task);
1470 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1471 cidx = rxq->ifr_cq_cidx;
1473 cidx = rxq->ifr_fl[0].ifl_cidx;
1474 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1475 GROUPTASK_ENQUEUE(gtask);
1480 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1481 DBG_COUNTER_INC(rx_intr_enables);
1484 IFDI_INTR_ENABLE(ctx);
1485 return (FILTER_HANDLED);
1490 iflib_fast_intr_ctx(void *arg)
1492 iflib_filter_info_t info = arg;
1493 struct grouptask *gtask = info->ifi_task;
1496 DBG_COUNTER_INC(fast_intrs);
1497 if (info->ifi_filter != NULL) {
1498 result = info->ifi_filter(info->ifi_filter_arg);
1499 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1503 GROUPTASK_ENQUEUE(gtask);
1504 return (FILTER_HANDLED);
1508 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1509 driver_filter_t filter, driver_intr_t handler, void *arg,
1512 struct resource *res;
1514 device_t dev = ctx->ifc_dev;
1518 if (ctx->ifc_flags & IFC_LEGACY)
1519 flags |= RF_SHAREABLE;
1522 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1525 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1529 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1530 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1531 filter, handler, arg, &tag);
1534 "failed to setup interrupt for rid %d, name %s: %d\n",
1535 rid, name ? name : "unknown", rc);
1538 bus_describe_intr(dev, res, tag, "%s", name);
1544 /*********************************************************************
1546 * Allocate DMA resources for TX buffers as well as memory for the TX
1547 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1548 * iflib_sw_tx_desc_array structure, storing all the information that
1549 * is needed to transmit a packet on the wire. This is called only
1550 * once at attach, setup is done every reset.
1552 **********************************************************************/
1554 iflib_txsd_alloc(iflib_txq_t txq)
1556 if_ctx_t ctx = txq->ift_ctx;
1557 if_shared_ctx_t sctx = ctx->ifc_sctx;
1558 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1559 device_t dev = ctx->ifc_dev;
1560 bus_size_t tsomaxsize;
1561 int err, nsegments, ntsosegments;
1564 nsegments = scctx->isc_tx_nsegments;
1565 ntsosegments = scctx->isc_tx_tso_segments_max;
1566 tsomaxsize = scctx->isc_tx_tso_size_max;
1567 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1568 tsomaxsize += sizeof(struct ether_vlan_header);
1569 MPASS(scctx->isc_ntxd[0] > 0);
1570 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1571 MPASS(nsegments > 0);
1572 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1573 MPASS(ntsosegments > 0);
1574 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1578 * Set up DMA tags for TX buffers.
1580 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1581 1, 0, /* alignment, bounds */
1582 BUS_SPACE_MAXADDR, /* lowaddr */
1583 BUS_SPACE_MAXADDR, /* highaddr */
1584 NULL, NULL, /* filter, filterarg */
1585 sctx->isc_tx_maxsize, /* maxsize */
1586 nsegments, /* nsegments */
1587 sctx->isc_tx_maxsegsize, /* maxsegsize */
1589 NULL, /* lockfunc */
1590 NULL, /* lockfuncarg */
1591 &txq->ift_buf_tag))) {
1592 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1593 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1594 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1597 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1598 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1599 1, 0, /* alignment, bounds */
1600 BUS_SPACE_MAXADDR, /* lowaddr */
1601 BUS_SPACE_MAXADDR, /* highaddr */
1602 NULL, NULL, /* filter, filterarg */
1603 tsomaxsize, /* maxsize */
1604 ntsosegments, /* nsegments */
1605 sctx->isc_tso_maxsegsize,/* maxsegsize */
1607 NULL, /* lockfunc */
1608 NULL, /* lockfuncarg */
1609 &txq->ift_tso_buf_tag))) {
1610 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1615 /* Allocate memory for the TX mbuf map. */
1616 if (!(txq->ift_sds.ifsd_m =
1617 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1618 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1619 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1625 * Create the DMA maps for TX buffers.
1627 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1628 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1629 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1631 "Unable to allocate TX buffer DMA map memory\n");
1635 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1636 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1637 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1639 "Unable to allocate TSO TX buffer map memory\n");
1643 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1644 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1645 &txq->ift_sds.ifsd_map[i]);
1647 device_printf(dev, "Unable to create TX DMA map\n");
1652 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1653 &txq->ift_sds.ifsd_tso_map[i]);
1655 device_printf(dev, "Unable to create TSO TX DMA map\n");
1661 /* We free all, it handles case where we are in the middle */
1662 iflib_tx_structures_free(ctx);
1667 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1671 if (txq->ift_sds.ifsd_map != NULL) {
1672 map = txq->ift_sds.ifsd_map[i];
1673 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1674 bus_dmamap_unload(txq->ift_buf_tag, map);
1675 bus_dmamap_destroy(txq->ift_buf_tag, map);
1676 txq->ift_sds.ifsd_map[i] = NULL;
1679 if (txq->ift_sds.ifsd_tso_map != NULL) {
1680 map = txq->ift_sds.ifsd_tso_map[i];
1681 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1682 BUS_DMASYNC_POSTWRITE);
1683 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1684 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1685 txq->ift_sds.ifsd_tso_map[i] = NULL;
1690 iflib_txq_destroy(iflib_txq_t txq)
1692 if_ctx_t ctx = txq->ift_ctx;
1694 for (int i = 0; i < txq->ift_size; i++)
1695 iflib_txsd_destroy(ctx, txq, i);
1697 if (txq->ift_br != NULL) {
1698 ifmp_ring_free(txq->ift_br);
1702 mtx_destroy(&txq->ift_mtx);
1704 if (txq->ift_sds.ifsd_map != NULL) {
1705 free(txq->ift_sds.ifsd_map, M_IFLIB);
1706 txq->ift_sds.ifsd_map = NULL;
1708 if (txq->ift_sds.ifsd_tso_map != NULL) {
1709 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1710 txq->ift_sds.ifsd_tso_map = NULL;
1712 if (txq->ift_sds.ifsd_m != NULL) {
1713 free(txq->ift_sds.ifsd_m, M_IFLIB);
1714 txq->ift_sds.ifsd_m = NULL;
1716 if (txq->ift_buf_tag != NULL) {
1717 bus_dma_tag_destroy(txq->ift_buf_tag);
1718 txq->ift_buf_tag = NULL;
1720 if (txq->ift_tso_buf_tag != NULL) {
1721 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1722 txq->ift_tso_buf_tag = NULL;
1724 if (txq->ift_ifdi != NULL) {
1725 free(txq->ift_ifdi, M_IFLIB);
1730 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1734 mp = &txq->ift_sds.ifsd_m[i];
1738 if (txq->ift_sds.ifsd_map != NULL) {
1739 bus_dmamap_sync(txq->ift_buf_tag,
1740 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1741 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1743 if (txq->ift_sds.ifsd_tso_map != NULL) {
1744 bus_dmamap_sync(txq->ift_tso_buf_tag,
1745 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1746 bus_dmamap_unload(txq->ift_tso_buf_tag,
1747 txq->ift_sds.ifsd_tso_map[i]);
1750 DBG_COUNTER_INC(tx_frees);
1755 iflib_txq_setup(iflib_txq_t txq)
1757 if_ctx_t ctx = txq->ift_ctx;
1758 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1759 if_shared_ctx_t sctx = ctx->ifc_sctx;
1760 iflib_dma_info_t di;
1763 /* Set number of descriptors available */
1764 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1765 /* XXX make configurable */
1766 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1769 txq->ift_cidx_processed = 0;
1770 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1771 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1773 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1774 bzero((void *)di->idi_vaddr, di->idi_size);
1776 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1777 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1778 bus_dmamap_sync(di->idi_tag, di->idi_map,
1779 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1783 /*********************************************************************
1785 * Allocate DMA resources for RX buffers as well as memory for the RX
1786 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1787 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1788 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1789 * Since we use use one entry in iflib_sw_rx_desc_array per received
1790 * packet, the maximum number of entries we'll need is equal to the
1791 * number of hardware receive descriptors that we've allocated.
1793 **********************************************************************/
1795 iflib_rxsd_alloc(iflib_rxq_t rxq)
1797 if_ctx_t ctx = rxq->ifr_ctx;
1798 if_shared_ctx_t sctx = ctx->ifc_sctx;
1799 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1800 device_t dev = ctx->ifc_dev;
1804 MPASS(scctx->isc_nrxd[0] > 0);
1805 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1808 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1809 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1810 /* Set up DMA tag for RX buffers. */
1811 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1812 1, 0, /* alignment, bounds */
1813 BUS_SPACE_MAXADDR, /* lowaddr */
1814 BUS_SPACE_MAXADDR, /* highaddr */
1815 NULL, NULL, /* filter, filterarg */
1816 sctx->isc_rx_maxsize, /* maxsize */
1817 sctx->isc_rx_nsegments, /* nsegments */
1818 sctx->isc_rx_maxsegsize, /* maxsegsize */
1820 NULL, /* lockfunc */
1825 "Unable to allocate RX DMA tag: %d\n", err);
1829 /* Allocate memory for the RX mbuf map. */
1830 if (!(fl->ifl_sds.ifsd_m =
1831 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1832 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1834 "Unable to allocate RX mbuf map memory\n");
1839 /* Allocate memory for the direct RX cluster pointer map. */
1840 if (!(fl->ifl_sds.ifsd_cl =
1841 (caddr_t *) malloc(sizeof(caddr_t) *
1842 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1844 "Unable to allocate RX cluster map memory\n");
1849 /* Allocate memory for the RX cluster bus address map. */
1850 if (!(fl->ifl_sds.ifsd_ba =
1851 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1852 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1854 "Unable to allocate RX bus address map memory\n");
1860 * Create the DMA maps for RX buffers.
1862 if (!(fl->ifl_sds.ifsd_map =
1863 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1865 "Unable to allocate RX buffer DMA map memory\n");
1869 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1870 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1871 &fl->ifl_sds.ifsd_map[i]);
1873 device_printf(dev, "Unable to create RX buffer DMA map\n");
1881 iflib_rx_structures_free(ctx);
1887 * Internal service routines
1890 struct rxq_refill_cb_arg {
1892 bus_dma_segment_t seg;
1897 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1899 struct rxq_refill_cb_arg *cb_arg = arg;
1901 cb_arg->error = error;
1902 cb_arg->seg = segs[0];
1903 cb_arg->nseg = nseg;
1907 * _iflib_fl_refill - refill an rxq free-buffer list
1908 * @ctx: the iflib context
1909 * @fl: the free list to refill
1910 * @count: the number of new buffers to allocate
1912 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1913 * The caller must assure that @count does not exceed the queue's capacity.
1916 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1918 struct if_rxd_update iru;
1919 struct rxq_refill_cb_arg cb_arg;
1923 bus_dmamap_t *sd_map;
1924 bus_addr_t bus_addr, *sd_ba;
1925 int err, frag_idx, i, idx, n, pidx;
1928 sd_m = fl->ifl_sds.ifsd_m;
1929 sd_map = fl->ifl_sds.ifsd_map;
1930 sd_cl = fl->ifl_sds.ifsd_cl;
1931 sd_ba = fl->ifl_sds.ifsd_ba;
1932 pidx = fl->ifl_pidx;
1934 frag_idx = fl->ifl_fragidx;
1935 credits = fl->ifl_credits;
1940 MPASS(credits + n <= fl->ifl_size);
1942 if (pidx < fl->ifl_cidx)
1943 MPASS(pidx + n <= fl->ifl_cidx);
1944 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1945 MPASS(fl->ifl_gen == 0);
1946 if (pidx > fl->ifl_cidx)
1947 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1949 DBG_COUNTER_INC(fl_refills);
1951 DBG_COUNTER_INC(fl_refills_large);
1952 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1955 * We allocate an uninitialized mbuf + cluster, mbuf is
1956 * initialized after rx.
1958 * If the cluster is still set then we know a minimum sized packet was received
1960 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1963 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1964 MPASS(frag_idx >= 0);
1965 if ((cl = sd_cl[frag_idx]) == NULL) {
1966 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1970 MPASS(sd_map != NULL);
1971 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1972 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1974 if (err != 0 || cb_arg.error) {
1978 if (fl->ifl_zone == zone_pack)
1979 uma_zfree(fl->ifl_zone, cl);
1983 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
1984 sd_cl[frag_idx] = cl;
1986 fl->ifl_cl_enqueued++;
1989 bus_addr = sd_ba[frag_idx];
1991 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
1992 BUS_DMASYNC_PREREAD);
1994 if (sd_m[frag_idx] == NULL) {
1995 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2000 bit_set(fl->ifl_rx_bitmap, frag_idx);
2002 fl->ifl_m_enqueued++;
2005 DBG_COUNTER_INC(rx_allocs);
2006 fl->ifl_rxd_idxs[i] = frag_idx;
2007 fl->ifl_bus_addrs[i] = bus_addr;
2008 fl->ifl_vm_addrs[i] = cl;
2011 MPASS(credits <= fl->ifl_size);
2012 if (++idx == fl->ifl_size) {
2016 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2017 iru.iru_pidx = pidx;
2019 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2023 fl->ifl_credits = credits;
2028 iru.iru_pidx = pidx;
2030 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2032 fl->ifl_credits = credits;
2034 DBG_COUNTER_INC(rxd_flush);
2035 if (fl->ifl_pidx == 0)
2036 pidx = fl->ifl_size - 1;
2038 pidx = fl->ifl_pidx - 1;
2040 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2042 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2043 fl->ifl_fragidx = frag_idx + 1;
2044 if (fl->ifl_fragidx == fl->ifl_size)
2045 fl->ifl_fragidx = 0;
2047 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2050 static __inline uint8_t
2051 __iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2053 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2054 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2056 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2059 MPASS(fl->ifl_credits <= fl->ifl_size);
2060 MPASS(reclaimable == delta);
2062 if (reclaimable > 0)
2063 return (_iflib_fl_refill(ctx, fl, reclaimable));
2068 iflib_in_detach(if_ctx_t ctx)
2073 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2079 iflib_fl_bufs_free(iflib_fl_t fl)
2081 iflib_dma_info_t idi = fl->ifl_ifdi;
2082 bus_dmamap_t sd_map;
2085 for (i = 0; i < fl->ifl_size; i++) {
2086 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2087 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2089 if (*sd_cl != NULL) {
2090 sd_map = fl->ifl_sds.ifsd_map[i];
2091 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2092 BUS_DMASYNC_POSTREAD);
2093 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2095 uma_zfree(fl->ifl_zone, *sd_cl);
2096 if (*sd_m != NULL) {
2097 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2098 uma_zfree(zone_mbuf, *sd_m);
2101 MPASS(*sd_cl == NULL);
2102 MPASS(*sd_m == NULL);
2105 fl->ifl_m_dequeued++;
2106 fl->ifl_cl_dequeued++;
2112 for (i = 0; i < fl->ifl_size; i++) {
2113 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2114 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2118 * Reset free list values
2120 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2121 bzero(idi->idi_vaddr, idi->idi_size);
2124 /*********************************************************************
2126 * Initialize a free list and its buffers.
2128 **********************************************************************/
2130 iflib_fl_setup(iflib_fl_t fl)
2132 iflib_rxq_t rxq = fl->ifl_rxq;
2133 if_ctx_t ctx = rxq->ifr_ctx;
2134 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2137 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2139 ** Free current RX buffer structs and their mbufs
2141 iflib_fl_bufs_free(fl);
2142 /* Now replenish the mbufs */
2143 MPASS(fl->ifl_credits == 0);
2144 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2145 if (scctx->isc_rxd_buf_size[qidx] != 0)
2146 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2148 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2150 * ifl_buf_size may be a driver-supplied value, so pull it up
2151 * to the selected mbuf size.
2153 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2154 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2155 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2156 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2157 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2160 /* avoid pre-allocating zillions of clusters to an idle card
2161 * potentially speeding up attach
2163 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2164 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2165 if (min(128, fl->ifl_size) != fl->ifl_credits)
2171 MPASS(fl->ifl_ifdi != NULL);
2172 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2173 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2177 /*********************************************************************
2179 * Free receive ring data structures
2181 **********************************************************************/
2183 iflib_rx_sds_free(iflib_rxq_t rxq)
2188 if (rxq->ifr_fl != NULL) {
2189 for (i = 0; i < rxq->ifr_nfl; i++) {
2190 fl = &rxq->ifr_fl[i];
2191 if (fl->ifl_buf_tag != NULL) {
2192 if (fl->ifl_sds.ifsd_map != NULL) {
2193 for (j = 0; j < fl->ifl_size; j++) {
2196 fl->ifl_sds.ifsd_map[j],
2197 BUS_DMASYNC_POSTREAD);
2200 fl->ifl_sds.ifsd_map[j]);
2203 fl->ifl_sds.ifsd_map[j]);
2206 bus_dma_tag_destroy(fl->ifl_buf_tag);
2207 fl->ifl_buf_tag = NULL;
2209 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2210 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2211 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2212 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2213 fl->ifl_sds.ifsd_m = NULL;
2214 fl->ifl_sds.ifsd_cl = NULL;
2215 fl->ifl_sds.ifsd_ba = NULL;
2216 fl->ifl_sds.ifsd_map = NULL;
2218 free(rxq->ifr_fl, M_IFLIB);
2220 free(rxq->ifr_ifdi, M_IFLIB);
2221 rxq->ifr_ifdi = NULL;
2222 rxq->ifr_cq_cidx = 0;
2230 iflib_timer(void *arg)
2232 iflib_txq_t txq = arg;
2233 if_ctx_t ctx = txq->ift_ctx;
2234 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2235 uint64_t this_tick = ticks;
2236 uint32_t reset_on = hz / 2;
2238 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2242 ** Check on the state of the TX queue(s), this
2243 ** can be done without the lock because its RO
2244 ** and the HUNG state will be static if set.
2246 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2247 txq->ift_last_timer_tick = this_tick;
2248 IFDI_TIMER(ctx, txq->ift_id);
2249 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2250 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2251 (sctx->isc_pause_frames == 0)))
2254 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2255 ifmp_ring_is_stalled(txq->ift_br)) {
2256 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2257 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2259 txq->ift_cleaned_prev = txq->ift_cleaned;
2262 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2263 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2265 /* handle any laggards */
2266 if (txq->ift_db_pending)
2267 GROUPTASK_ENQUEUE(&txq->ift_task);
2269 sctx->isc_pause_frames = 0;
2270 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2271 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2275 device_printf(ctx->ifc_dev,
2276 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2277 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2280 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2281 iflib_admin_intr_deferred(ctx);
2286 iflib_get_mbuf_size_for(unsigned int size)
2289 if (size <= MCLBYTES)
2292 return (MJUMPAGESIZE);
2296 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2298 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2301 * XXX don't set the max_frame_size to larger
2302 * than the hardware can handle
2304 ctx->ifc_rx_mbuf_sz =
2305 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2309 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2312 return (ctx->ifc_rx_mbuf_sz);
2316 iflib_init_locked(if_ctx_t ctx)
2318 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2319 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2320 if_t ifp = ctx->ifc_ifp;
2324 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2326 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2327 IFDI_INTR_DISABLE(ctx);
2329 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2330 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2331 /* Set hardware offload abilities */
2332 if_clearhwassist(ifp);
2333 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2334 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2335 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2336 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2337 if (if_getcapenable(ifp) & IFCAP_TSO4)
2338 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2339 if (if_getcapenable(ifp) & IFCAP_TSO6)
2340 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2342 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2344 callout_stop(&txq->ift_timer);
2345 CALLOUT_UNLOCK(txq);
2346 iflib_netmap_txq_init(ctx, txq);
2350 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2351 * that drivers can use the value when setting up the hardware receive
2354 iflib_calc_rx_mbuf_sz(ctx);
2357 i = if_getdrvflags(ifp);
2360 MPASS(if_getdrvflags(ifp) == i);
2361 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2362 /* XXX this should really be done on a per-queue basis */
2363 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2364 MPASS(rxq->ifr_id == i);
2365 iflib_netmap_rxq_init(ctx, rxq);
2368 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2369 if (iflib_fl_setup(fl)) {
2370 device_printf(ctx->ifc_dev,
2371 "setting up free list %d failed - "
2372 "check cluster settings\n", j);
2378 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2379 IFDI_INTR_ENABLE(ctx);
2380 txq = ctx->ifc_txqs;
2381 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2382 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2383 txq->ift_timer.c_cpu);
2387 iflib_media_change(if_t ifp)
2389 if_ctx_t ctx = if_getsoftc(ifp);
2393 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2394 iflib_init_locked(ctx);
2400 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2402 if_ctx_t ctx = if_getsoftc(ifp);
2405 IFDI_UPDATE_ADMIN_STATUS(ctx);
2406 IFDI_MEDIA_STATUS(ctx, ifmr);
2411 iflib_stop(if_ctx_t ctx)
2413 iflib_txq_t txq = ctx->ifc_txqs;
2414 iflib_rxq_t rxq = ctx->ifc_rxqs;
2415 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2416 if_shared_ctx_t sctx = ctx->ifc_sctx;
2417 iflib_dma_info_t di;
2421 /* Tell the stack that the interface is no longer active */
2422 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2424 IFDI_INTR_DISABLE(ctx);
2429 iflib_debug_reset();
2430 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2431 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2432 /* make sure all transmitters have completed before proceeding XXX */
2435 callout_stop(&txq->ift_timer);
2436 CALLOUT_UNLOCK(txq);
2438 /* clean any enqueued buffers */
2439 iflib_ifmp_purge(txq);
2440 /* Free any existing tx buffers. */
2441 for (j = 0; j < txq->ift_size; j++) {
2442 iflib_txsd_free(ctx, txq, j);
2444 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2445 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2446 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2447 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2448 txq->ift_pullups = 0;
2449 ifmp_ring_reset_stats(txq->ift_br);
2450 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2451 bzero((void *)di->idi_vaddr, di->idi_size);
2453 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2454 /* make sure all transmitters have completed before proceeding XXX */
2456 rxq->ifr_cq_cidx = 0;
2457 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2458 bzero((void *)di->idi_vaddr, di->idi_size);
2459 /* also resets the free lists pidx/cidx */
2460 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2461 iflib_fl_bufs_free(fl);
2465 static inline caddr_t
2466 calc_next_rxd(iflib_fl_t fl, int cidx)
2470 caddr_t start, end, cur, next;
2472 nrxd = fl->ifl_size;
2473 size = fl->ifl_rxd_size;
2474 start = fl->ifl_ifdi->idi_vaddr;
2476 if (__predict_false(size == 0))
2478 cur = start + size*cidx;
2479 end = start + size*nrxd;
2480 next = CACHE_PTR_NEXT(cur);
2481 return (next < end ? next : start);
2485 prefetch_pkts(iflib_fl_t fl, int cidx)
2488 int nrxd = fl->ifl_size;
2492 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2493 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2494 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2495 next_rxd = calc_next_rxd(fl, cidx);
2497 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2498 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2499 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2500 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2501 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2502 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2503 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2504 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2507 static struct mbuf *
2508 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2509 int *pf_rv, if_rxd_info_t ri)
2515 int flid, cidx, len, next;
2518 flid = irf->irf_flid;
2519 cidx = irf->irf_idx;
2520 fl = &rxq->ifr_fl[flid];
2522 m = fl->ifl_sds.ifsd_m[cidx];
2523 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2526 fl->ifl_m_dequeued++;
2528 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2529 prefetch_pkts(fl, cidx);
2530 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2531 prefetch(&fl->ifl_sds.ifsd_map[next]);
2532 map = fl->ifl_sds.ifsd_map[cidx];
2534 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2536 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2537 irf->irf_len != 0) {
2538 payload = *sd->ifsd_cl;
2539 payload += ri->iri_pad;
2540 len = ri->iri_len - ri->iri_pad;
2541 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2542 len | PFIL_MEMPTR | PFIL_IN, NULL);
2547 * The filter ate it. Everything is recycled.
2552 case PFIL_REALLOCED:
2554 * The filter copied it. Everything is recycled.
2556 m = pfil_mem2mbuf(payload);
2561 * Filter said it was OK, so receive like
2564 fl->ifl_sds.ifsd_m[cidx] = NULL;
2570 fl->ifl_sds.ifsd_m[cidx] = NULL;
2574 if (unload && irf->irf_len != 0)
2575 bus_dmamap_unload(fl->ifl_buf_tag, map);
2576 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2577 if (__predict_false(fl->ifl_cidx == 0))
2579 bit_clear(fl->ifl_rx_bitmap, cidx);
2583 static struct mbuf *
2584 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2586 struct mbuf *m, *mh, *mt;
2588 int *pf_rv_ptr, flags, i, padlen;
2597 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2600 MPASS(*sd->ifsd_cl != NULL);
2603 * Exclude zero-length frags & frags from
2604 * packets the filter has consumed or dropped
2606 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2607 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2609 /* everything saved here */
2614 /* XXX we can save the cluster here, but not the mbuf */
2615 m_init(m, M_NOWAIT, MT_DATA, 0);
2620 flags = M_PKTHDR|M_EXT;
2622 padlen = ri->iri_pad;
2627 /* assuming padding is only on the first fragment */
2631 *sd->ifsd_cl = NULL;
2633 /* Can these two be made one ? */
2634 m_init(m, M_NOWAIT, MT_DATA, flags);
2635 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2637 * These must follow m_init and m_cljset
2639 m->m_data += padlen;
2640 ri->iri_len -= padlen;
2641 m->m_len = ri->iri_frags[i].irf_len;
2642 } while (++i < ri->iri_nfrags);
2648 * Process one software descriptor
2650 static struct mbuf *
2651 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2657 /* should I merge this back in now that the two paths are basically duplicated? */
2658 if (ri->iri_nfrags == 1 &&
2659 ri->iri_frags[0].irf_len != 0 &&
2660 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2661 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2663 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2665 if (pf_rv == PFIL_PASS) {
2666 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2667 #ifndef __NO_STRICT_ALIGNMENT
2671 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2672 m->m_len = ri->iri_frags[0].irf_len;
2675 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2678 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2681 m->m_pkthdr.len = ri->iri_len;
2682 m->m_pkthdr.rcvif = ri->iri_ifp;
2683 m->m_flags |= ri->iri_flags;
2684 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2685 m->m_pkthdr.flowid = ri->iri_flowid;
2686 M_HASHTYPE_SET(m, ri->iri_rsstype);
2687 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2688 m->m_pkthdr.csum_data = ri->iri_csum_data;
2692 #if defined(INET6) || defined(INET)
2694 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2696 CURVNET_SET(lc->ifp->if_vnet);
2698 *v6 = V_ip6_forwarding;
2701 *v4 = V_ipforwarding;
2707 * Returns true if it's possible this packet could be LROed.
2708 * if it returns false, it is guaranteed that tcp_lro_rx()
2709 * would not return zero.
2712 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2714 struct ether_header *eh;
2716 eh = mtod(m, struct ether_header *);
2717 switch (eh->ether_type) {
2719 case htons(ETHERTYPE_IPV6):
2720 return (!v6_forwarding);
2723 case htons(ETHERTYPE_IP):
2724 return (!v4_forwarding);
2732 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2738 _task_fn_rx_watchdog(void *context)
2740 iflib_rxq_t rxq = context;
2742 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2746 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2749 if_ctx_t ctx = rxq->ifr_ctx;
2750 if_shared_ctx_t sctx = ctx->ifc_sctx;
2751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2754 struct if_rxd_info ri;
2755 int err, budget_left, rx_bytes, rx_pkts;
2758 bool v4_forwarding, v6_forwarding, lro_possible;
2762 * XXX early demux data packets so that if_input processing only handles
2763 * acks in interrupt context
2765 struct mbuf *m, *mh, *mt, *mf;
2769 lro_possible = v4_forwarding = v6_forwarding = false;
2773 rx_pkts = rx_bytes = 0;
2774 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2775 cidxp = &rxq->ifr_cq_cidx;
2777 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2778 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2779 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2780 retval |= __iflib_fl_refill_all(ctx, fl);
2781 DBG_COUNTER_INC(rx_unavail);
2785 /* pfil needs the vnet to be set */
2786 CURVNET_SET_QUIET(ifp->if_vnet);
2787 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2788 if (__predict_false(!CTX_ACTIVE(ctx))) {
2789 DBG_COUNTER_INC(rx_ctx_inactive);
2793 * Reset client set fields to their default values
2796 ri.iri_qsidx = rxq->ifr_id;
2797 ri.iri_cidx = *cidxp;
2799 ri.iri_frags = rxq->ifr_frags;
2800 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2805 rx_bytes += ri.iri_len;
2806 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2807 *cidxp = ri.iri_cidx;
2808 /* Update our consumer index */
2809 /* XXX NB: shurd - check if this is still safe */
2810 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2811 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2812 /* was this only a completion queue message? */
2813 if (__predict_false(ri.iri_nfrags == 0))
2816 MPASS(ri.iri_nfrags != 0);
2817 MPASS(ri.iri_len != 0);
2819 /* will advance the cidx on the corresponding free lists */
2820 m = iflib_rxd_pkt_get(rxq, &ri);
2823 if (avail == 0 && budget_left)
2824 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2826 if (__predict_false(m == NULL))
2829 /* imm_pkt: -- cxgb */
2838 /* make sure that we can refill faster than drain */
2839 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2840 retval |= __iflib_fl_refill_all(ctx, fl);
2842 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2844 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2846 while (mh != NULL) {
2849 m->m_nextpkt = NULL;
2850 #ifndef __NO_STRICT_ALIGNMENT
2851 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2854 rx_bytes += m->m_pkthdr.len;
2856 #if defined(INET6) || defined(INET)
2858 if (!lro_possible) {
2859 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2860 if (lro_possible && mf != NULL) {
2861 ifp->if_input(ifp, mf);
2862 DBG_COUNTER_INC(rx_if_input);
2866 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2867 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2868 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2874 ifp->if_input(ifp, m);
2875 DBG_COUNTER_INC(rx_if_input);
2886 ifp->if_input(ifp, mf);
2887 DBG_COUNTER_INC(rx_if_input);
2890 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2891 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2894 * Flush any outstanding LRO work
2896 #if defined(INET6) || defined(INET)
2897 tcp_lro_flush_all(&rxq->ifr_lc);
2899 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2900 retval |= IFLIB_RXEOF_MORE;
2904 ctx->ifc_flags |= IFC_DO_RESET;
2905 iflib_admin_intr_deferred(ctx);
2910 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2911 static inline qidx_t
2912 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2914 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2915 qidx_t minthresh = txq->ift_size / 8;
2916 if (in_use > 4*minthresh)
2917 return (notify_count);
2918 if (in_use > 2*minthresh)
2919 return (notify_count >> 1);
2920 if (in_use > minthresh)
2921 return (notify_count >> 3);
2925 static inline qidx_t
2926 txq_max_rs_deferred(iflib_txq_t txq)
2928 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2929 qidx_t minthresh = txq->ift_size / 8;
2930 if (txq->ift_in_use > 4*minthresh)
2931 return (notify_count);
2932 if (txq->ift_in_use > 2*minthresh)
2933 return (notify_count >> 1);
2934 if (txq->ift_in_use > minthresh)
2935 return (notify_count >> 2);
2939 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2940 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2942 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2943 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2944 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2946 /* forward compatibility for cxgb */
2947 #define FIRST_QSET(ctx) 0
2948 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2949 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2950 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2951 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2953 /* XXX we should be setting this to something other than zero */
2954 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2955 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2956 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2959 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2965 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2966 if (ring || txq->ift_db_pending >= max) {
2967 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2968 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2969 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2970 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2971 txq->ift_db_pending = txq->ift_npending = 0;
2979 print_pkt(if_pkt_info_t pi)
2981 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2982 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2983 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2984 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2985 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2986 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2990 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2991 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2992 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2993 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2996 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2998 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2999 struct ether_vlan_header *eh;
3003 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3004 M_WRITABLE(m) == 0) {
3005 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3009 DBG_COUNTER_INC(tx_frees);
3015 * Determine where frame payload starts.
3016 * Jump over vlan headers if already present,
3017 * helpful for QinQ too.
3019 if (__predict_false(m->m_len < sizeof(*eh))) {
3021 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3024 eh = mtod(m, struct ether_vlan_header *);
3025 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3026 pi->ipi_etype = ntohs(eh->evl_proto);
3027 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3029 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3030 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3033 switch (pi->ipi_etype) {
3038 struct ip *ip = NULL;
3039 struct tcphdr *th = NULL;
3042 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3043 if (__predict_false(m->m_len < minthlen)) {
3045 * if this code bloat is causing too much of a hit
3046 * move it to a separate function and mark it noinline
3048 if (m->m_len == pi->ipi_ehdrlen) {
3051 if (n->m_len >= sizeof(*ip)) {
3052 ip = (struct ip *)n->m_data;
3053 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3057 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3059 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3063 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3065 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3066 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3067 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3070 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3071 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3072 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3074 pi->ipi_ip_hlen = ip->ip_hl << 2;
3075 pi->ipi_ipproto = ip->ip_p;
3076 pi->ipi_flags |= IPI_TX_IPV4;
3078 /* TCP checksum offload may require TCP header length */
3079 if (IS_TX_OFFLOAD4(pi)) {
3080 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3081 if (__predict_false(th == NULL)) {
3083 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3085 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3087 pi->ipi_tcp_hflags = th->th_flags;
3088 pi->ipi_tcp_hlen = th->th_off << 2;
3089 pi->ipi_tcp_seq = th->th_seq;
3092 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3095 * TSO always requires hardware checksum offload.
3097 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3098 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3099 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3100 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3101 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3103 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3107 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3114 case ETHERTYPE_IPV6:
3116 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3118 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3120 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3122 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3125 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3127 /* XXX-BZ this will go badly in case of ext hdrs. */
3128 pi->ipi_ipproto = ip6->ip6_nxt;
3129 pi->ipi_flags |= IPI_TX_IPV6;
3131 /* TCP checksum offload may require TCP header length */
3132 if (IS_TX_OFFLOAD6(pi)) {
3133 if (pi->ipi_ipproto == IPPROTO_TCP) {
3134 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3136 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3139 pi->ipi_tcp_hflags = th->th_flags;
3140 pi->ipi_tcp_hlen = th->th_off << 2;
3141 pi->ipi_tcp_seq = th->th_seq;
3144 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3147 * TSO always requires hardware checksum offload.
3149 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3150 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3151 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3158 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3159 pi->ipi_ip_hlen = 0;
3168 * If dodgy hardware rejects the scatter gather chain we've handed it
3169 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3172 static __noinline struct mbuf *
3173 iflib_remove_mbuf(iflib_txq_t txq)
3176 struct mbuf *m, **ifsd_m;
3178 ifsd_m = txq->ift_sds.ifsd_m;
3179 ntxd = txq->ift_size;
3180 pidx = txq->ift_pidx & (ntxd - 1);
3181 ifsd_m = txq->ift_sds.ifsd_m;
3183 ifsd_m[pidx] = NULL;
3184 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3185 if (txq->ift_sds.ifsd_tso_map != NULL)
3186 bus_dmamap_unload(txq->ift_tso_buf_tag,
3187 txq->ift_sds.ifsd_tso_map[pidx]);
3189 txq->ift_dequeued++;
3194 static inline caddr_t
3195 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3199 caddr_t start, end, cur, next;
3201 ntxd = txq->ift_size;
3202 size = txq->ift_txd_size[qid];
3203 start = txq->ift_ifdi[qid].idi_vaddr;
3205 if (__predict_false(size == 0))
3207 cur = start + size*cidx;
3208 end = start + size*ntxd;
3209 next = CACHE_PTR_NEXT(cur);
3210 return (next < end ? next : start);
3214 * Pad an mbuf to ensure a minimum ethernet frame size.
3215 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3217 static __noinline int
3218 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3221 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3222 * and ARP message is the smallest common payload I can think of
3224 static char pad[18]; /* just zeros */
3226 struct mbuf *new_head;
3228 if (!M_WRITABLE(*m_head)) {
3229 new_head = m_dup(*m_head, M_NOWAIT);
3230 if (new_head == NULL) {
3232 device_printf(dev, "cannot pad short frame, m_dup() failed");
3233 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3234 DBG_COUNTER_INC(tx_frees);
3241 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3242 n > 0; n -= sizeof(pad))
3243 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3248 device_printf(dev, "cannot pad short frame\n");
3249 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3250 DBG_COUNTER_INC(tx_frees);
3258 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3261 if_shared_ctx_t sctx;
3262 if_softc_ctx_t scctx;
3263 bus_dma_tag_t buf_tag;
3264 bus_dma_segment_t *segs;
3265 struct mbuf *m_head, **ifsd_m;
3268 struct if_pkt_info pi;
3270 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3273 sctx = ctx->ifc_sctx;
3274 scctx = &ctx->ifc_softc_ctx;
3275 segs = txq->ift_segs;
3276 ntxd = txq->ift_size;
3281 * If we're doing TSO the next descriptor to clean may be quite far ahead
3283 cidx = txq->ift_cidx;
3284 pidx = txq->ift_pidx;
3285 if (ctx->ifc_flags & IFC_PREFETCH) {
3286 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3287 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3288 next_txd = calc_next_txd(txq, cidx, 0);
3292 /* prefetch the next cache line of mbuf pointers and flags */
3293 prefetch(&txq->ift_sds.ifsd_m[next]);
3294 prefetch(&txq->ift_sds.ifsd_map[next]);
3295 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3297 map = txq->ift_sds.ifsd_map[pidx];
3298 ifsd_m = txq->ift_sds.ifsd_m;
3300 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3301 buf_tag = txq->ift_tso_buf_tag;
3302 max_segs = scctx->isc_tx_tso_segments_max;
3303 map = txq->ift_sds.ifsd_tso_map[pidx];
3304 MPASS(buf_tag != NULL);
3305 MPASS(max_segs > 0);
3307 buf_tag = txq->ift_buf_tag;
3308 max_segs = scctx->isc_tx_nsegments;
3309 map = txq->ift_sds.ifsd_map[pidx];
3311 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3312 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3313 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3315 DBG_COUNTER_INC(encap_txd_encap_fail);
3322 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3324 pi.ipi_qsidx = txq->ift_id;
3325 pi.ipi_len = m_head->m_pkthdr.len;
3326 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3327 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3329 /* deliberate bitwise OR to make one condition */
3330 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3331 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3332 DBG_COUNTER_INC(encap_txd_encap_fail);
3339 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3342 if (__predict_false(err)) {
3345 /* try collapse once and defrag once */
3347 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3348 /* try defrag if collapsing fails */
3353 txq->ift_mbuf_defrag++;
3354 m_head = m_defrag(*m_headp, M_NOWAIT);
3357 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3358 * failed to map an mbuf that was run through m_defrag
3361 if (__predict_false(m_head == NULL || remap > 1))
3368 txq->ift_no_tx_dma_setup++;
3371 txq->ift_no_tx_dma_setup++;
3373 DBG_COUNTER_INC(tx_frees);
3377 txq->ift_map_failed++;
3378 DBG_COUNTER_INC(encap_load_mbuf_fail);
3379 DBG_COUNTER_INC(encap_txd_encap_fail);
3382 ifsd_m[pidx] = m_head;
3384 * XXX assumes a 1 to 1 relationship between segments and
3385 * descriptors - this does not hold true on all drivers, e.g.
3388 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3389 txq->ift_no_desc_avail++;
3390 bus_dmamap_unload(buf_tag, map);
3391 DBG_COUNTER_INC(encap_txq_avail_fail);
3392 DBG_COUNTER_INC(encap_txd_encap_fail);
3393 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3394 GROUPTASK_ENQUEUE(&txq->ift_task);
3398 * On Intel cards we can greatly reduce the number of TX interrupts
3399 * we see by only setting report status on every Nth descriptor.
3400 * However, this also means that the driver will need to keep track
3401 * of the descriptors that RS was set on to check them for the DD bit.
3403 txq->ift_rs_pending += nsegs + 1;
3404 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3405 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3406 pi.ipi_flags |= IPI_TX_INTR;
3407 txq->ift_rs_pending = 0;
3411 pi.ipi_nsegs = nsegs;
3413 MPASS(pidx >= 0 && pidx < txq->ift_size);
3417 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3418 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3419 DBG_COUNTER_INC(tx_encap);
3420 MPASS(pi.ipi_new_pidx < txq->ift_size);
3422 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3423 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3424 ndesc += txq->ift_size;
3428 * drivers can need as many as
3431 MPASS(ndesc <= pi.ipi_nsegs + 2);
3432 MPASS(pi.ipi_new_pidx != pidx);
3434 txq->ift_in_use += ndesc;
3437 * We update the last software descriptor again here because there may
3438 * be a sentinel and/or there may be more mbufs than segments
3440 txq->ift_pidx = pi.ipi_new_pidx;
3441 txq->ift_npending += pi.ipi_ndescs;
3443 *m_headp = m_head = iflib_remove_mbuf(txq);
3445 txq->ift_txd_encap_efbig++;
3454 * err can't possibly be non-zero here, so we don't neet to test it
3455 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3460 txq->ift_mbuf_defrag_failed++;
3461 txq->ift_map_failed++;
3463 DBG_COUNTER_INC(tx_frees);
3465 DBG_COUNTER_INC(encap_txd_encap_fail);
3470 iflib_tx_desc_free(iflib_txq_t txq, int n)
3472 uint32_t qsize, cidx, mask, gen;
3473 struct mbuf *m, **ifsd_m;
3476 cidx = txq->ift_cidx;
3478 qsize = txq->ift_size;
3480 ifsd_m = txq->ift_sds.ifsd_m;
3481 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3485 prefetch(ifsd_m[(cidx + 3) & mask]);
3486 prefetch(ifsd_m[(cidx + 4) & mask]);
3488 if ((m = ifsd_m[cidx]) != NULL) {
3489 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3490 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3491 bus_dmamap_sync(txq->ift_tso_buf_tag,
3492 txq->ift_sds.ifsd_tso_map[cidx],
3493 BUS_DMASYNC_POSTWRITE);
3494 bus_dmamap_unload(txq->ift_tso_buf_tag,
3495 txq->ift_sds.ifsd_tso_map[cidx]);
3497 bus_dmamap_sync(txq->ift_buf_tag,
3498 txq->ift_sds.ifsd_map[cidx],
3499 BUS_DMASYNC_POSTWRITE);
3500 bus_dmamap_unload(txq->ift_buf_tag,
3501 txq->ift_sds.ifsd_map[cidx]);
3503 /* XXX we don't support any drivers that batch packets yet */
3504 MPASS(m->m_nextpkt == NULL);
3506 ifsd_m[cidx] = NULL;
3508 txq->ift_dequeued++;
3510 DBG_COUNTER_INC(tx_frees);
3512 if (__predict_false(++cidx == qsize)) {
3517 txq->ift_cidx = cidx;
3522 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3525 if_ctx_t ctx = txq->ift_ctx;
3527 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3528 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3531 * Need a rate-limiting check so that this isn't called every time
3533 iflib_tx_credits_update(ctx, txq);
3534 reclaim = DESC_RECLAIMABLE(txq);
3536 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3538 if (iflib_verbose_debug) {
3539 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3540 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3547 iflib_tx_desc_free(txq, reclaim);
3548 txq->ift_cleaned += reclaim;
3549 txq->ift_in_use -= reclaim;
3554 static struct mbuf **
3555 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3558 struct mbuf **items;
3561 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3562 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3564 prefetch(items[(cidx + offset) & (size-1)]);
3565 if (remaining > 1) {
3566 prefetch2cachelines(&items[next]);
3567 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3568 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3569 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3571 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3575 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3578 ifmp_ring_check_drainage(txq->ift_br, budget);
3582 iflib_txq_can_drain(struct ifmp_ring *r)
3584 iflib_txq_t txq = r->cookie;
3585 if_ctx_t ctx = txq->ift_ctx;
3587 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3589 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3590 BUS_DMASYNC_POSTREAD);
3591 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3596 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3598 iflib_txq_t txq = r->cookie;
3599 if_ctx_t ctx = txq->ift_ctx;
3600 if_t ifp = ctx->ifc_ifp;
3601 struct mbuf *m, **mp;
3602 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3603 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3604 bool do_prefetch, rang, ring;
3606 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3607 !LINK_ACTIVE(ctx))) {
3608 DBG_COUNTER_INC(txq_drain_notready);
3611 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3612 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3613 avail = IDXDIFF(pidx, cidx, r->size);
3614 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3615 DBG_COUNTER_INC(txq_drain_flushing);
3616 for (i = 0; i < avail; i++) {
3617 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3618 m_free(r->items[(cidx + i) & (r->size-1)]);
3619 r->items[(cidx + i) & (r->size-1)] = NULL;
3624 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3625 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3627 callout_stop(&txq->ift_timer);
3628 CALLOUT_UNLOCK(txq);
3629 DBG_COUNTER_INC(txq_drain_oactive);
3633 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3634 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3635 count = MIN(avail, TX_BATCH_SIZE);
3637 if (iflib_verbose_debug)
3638 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3639 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3641 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3642 txq_avail = TXQ_AVAIL(txq);
3644 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3645 int rem = do_prefetch ? count - i : 0;
3647 mp = _ring_peek_one(r, cidx, i, rem);
3648 MPASS(mp != NULL && *mp != NULL);
3649 if (__predict_false(*mp == (struct mbuf *)txq)) {
3653 in_use_prev = txq->ift_in_use;
3654 err = iflib_encap(txq, mp);
3655 if (__predict_false(err)) {
3656 /* no room - bail out */
3660 /* we can't send this packet - skip it */
3666 DBG_COUNTER_INC(tx_sent);
3667 bytes_sent += m->m_pkthdr.len;
3668 mcast_sent += !!(m->m_flags & M_MCAST);
3669 txq_avail = TXQ_AVAIL(txq);
3671 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3672 ETHER_BPF_MTAP(ifp, m);
3673 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3675 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3678 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3679 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3680 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3681 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3682 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3684 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3686 if (iflib_verbose_debug)
3687 printf("consumed=%d\n", consumed);
3693 iflib_txq_drain_always(struct ifmp_ring *r)
3699 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3707 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3709 callout_stop(&txq->ift_timer);
3710 CALLOUT_UNLOCK(txq);
3712 avail = IDXDIFF(pidx, cidx, r->size);
3713 for (i = 0; i < avail; i++) {
3714 mp = _ring_peek_one(r, cidx, i, avail - i);
3715 if (__predict_false(*mp == (struct mbuf *)txq))
3718 DBG_COUNTER_INC(tx_frees);
3720 MPASS(ifmp_ring_is_stalled(r) == 0);
3725 iflib_ifmp_purge(iflib_txq_t txq)
3727 struct ifmp_ring *r;
3730 r->drain = iflib_txq_drain_free;
3731 r->can_drain = iflib_txq_drain_always;
3733 ifmp_ring_check_drainage(r, r->size);
3735 r->drain = iflib_txq_drain;
3736 r->can_drain = iflib_txq_can_drain;
3740 _task_fn_tx(void *context)
3742 iflib_txq_t txq = context;
3743 if_ctx_t ctx = txq->ift_ctx;
3744 #if defined(ALTQ) || defined(DEV_NETMAP)
3745 if_t ifp = ctx->ifc_ifp;
3747 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3749 #ifdef IFLIB_DIAGNOSTICS
3750 txq->ift_cpu_exec_count[curcpu]++;
3752 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3755 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3756 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3757 BUS_DMASYNC_POSTREAD);
3758 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3759 netmap_tx_irq(ifp, txq->ift_id);
3760 if (ctx->ifc_flags & IFC_LEGACY)
3761 IFDI_INTR_ENABLE(ctx);
3763 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3768 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3769 iflib_altq_if_start(ifp);
3771 if (txq->ift_db_pending)
3772 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3774 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3776 * When abdicating, we always need to check drainage, not just when we don't enqueue
3779 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3780 if (ctx->ifc_flags & IFC_LEGACY)
3781 IFDI_INTR_ENABLE(ctx);
3783 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3787 _task_fn_rx(void *context)
3789 iflib_rxq_t rxq = context;
3790 if_ctx_t ctx = rxq->ifr_ctx;
3794 #ifdef IFLIB_DIAGNOSTICS
3795 rxq->ifr_cpu_exec_count[curcpu]++;
3797 DBG_COUNTER_INC(task_fn_rxs);
3798 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3801 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3803 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3809 budget = ctx->ifc_sysctl_rx_budget;
3811 budget = 16; /* XXX */
3812 more = iflib_rxeof(rxq, budget);
3816 if ((more & IFLIB_RXEOF_MORE) == 0) {
3817 if (ctx->ifc_flags & IFC_LEGACY)
3818 IFDI_INTR_ENABLE(ctx);
3820 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3821 DBG_COUNTER_INC(rx_intr_enables);
3823 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3826 if (more & IFLIB_RXEOF_MORE)
3827 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3828 else if (more & IFLIB_RXEOF_EMPTY)
3829 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3833 _task_fn_admin(void *context)
3835 if_ctx_t ctx = context;
3836 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3839 bool oactive, running, do_reset, do_watchdog, in_detach;
3840 uint32_t reset_on = hz / 2;
3843 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3844 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3845 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3846 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3847 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3848 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3851 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3857 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3859 callout_stop(&txq->ift_timer);
3860 CALLOUT_UNLOCK(txq);
3863 ctx->ifc_watchdog_events++;
3864 IFDI_WATCHDOG_RESET(ctx);
3866 IFDI_UPDATE_ADMIN_STATUS(ctx);
3867 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3870 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3871 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3873 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3875 IFDI_LINK_INTR_ENABLE(ctx);
3877 iflib_if_init_locked(ctx);
3880 if (LINK_ACTIVE(ctx) == 0)
3882 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3883 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3888 _task_fn_iov(void *context)
3890 if_ctx_t ctx = context;
3892 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3893 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3897 IFDI_VFLR_HANDLE(ctx);
3902 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3905 if_int_delay_info_t info;
3908 info = (if_int_delay_info_t)arg1;
3909 ctx = info->iidi_ctx;
3910 info->iidi_req = req;
3911 info->iidi_oidp = oidp;
3913 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3918 /*********************************************************************
3922 **********************************************************************/
3925 iflib_if_init_locked(if_ctx_t ctx)
3928 iflib_init_locked(ctx);
3933 iflib_if_init(void *arg)
3938 iflib_if_init_locked(ctx);
3943 iflib_if_transmit(if_t ifp, struct mbuf *m)
3945 if_ctx_t ctx = if_getsoftc(ifp);
3949 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3951 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3952 DBG_COUNTER_INC(tx_frees);
3957 MPASS(m->m_nextpkt == NULL);
3958 /* ALTQ-enabled interfaces always use queue 0. */
3960 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3961 qidx = QIDX(ctx, m);
3963 * XXX calculate buf_ring based on flowid (divvy up bits?)
3965 txq = &ctx->ifc_txqs[qidx];
3967 #ifdef DRIVER_BACKPRESSURE
3968 if (txq->ift_closed) {
3970 next = m->m_nextpkt;
3971 m->m_nextpkt = NULL;
3973 DBG_COUNTER_INC(tx_frees);
3985 next = next->m_nextpkt;
3986 } while (next != NULL);
3988 if (count > nitems(marr))
3989 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3990 /* XXX check nextpkt */
3992 /* XXX simplify for now */
3993 DBG_COUNTER_INC(tx_frees);
3996 for (next = m, i = 0; next != NULL; i++) {
3998 next = next->m_nextpkt;
3999 mp[i]->m_nextpkt = NULL;
4002 DBG_COUNTER_INC(tx_seen);
4003 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4006 GROUPTASK_ENQUEUE(&txq->ift_task);
4009 GROUPTASK_ENQUEUE(&txq->ift_task);
4010 /* support forthcoming later */
4011 #ifdef DRIVER_BACKPRESSURE
4012 txq->ift_closed = TRUE;
4014 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4016 DBG_COUNTER_INC(tx_frees);
4024 * The overall approach to integrating iflib with ALTQ is to continue to use
4025 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4026 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4027 * is redundant/unnecessary, but doing so minimizes the amount of
4028 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4029 * redundantly queueing to an intermediate mp_ring is swamped by the
4030 * performance limitations inherent in using ALTQ.
4032 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4033 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4034 * given interface. If ALTQ is enabled for an interface, then all
4035 * transmitted packets for that interface will be submitted to the ALTQ
4036 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4037 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4038 * update stats that the iflib machinery handles, and which is sensitve to
4039 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4040 * will be installed as the start routine for use by ALTQ facilities that
4041 * need to trigger queue drains on a scheduled basis.
4045 iflib_altq_if_start(if_t ifp)
4047 struct ifaltq *ifq = &ifp->if_snd;
4051 IFQ_DEQUEUE_NOLOCK(ifq, m);
4053 iflib_if_transmit(ifp, m);
4054 IFQ_DEQUEUE_NOLOCK(ifq, m);
4060 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4064 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4065 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4067 iflib_altq_if_start(ifp);
4069 err = iflib_if_transmit(ifp, m);
4076 iflib_if_qflush(if_t ifp)
4078 if_ctx_t ctx = if_getsoftc(ifp);
4079 iflib_txq_t txq = ctx->ifc_txqs;
4083 ctx->ifc_flags |= IFC_QFLUSH;
4085 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4086 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4087 iflib_txq_check_drain(txq, 0);
4089 ctx->ifc_flags &= ~IFC_QFLUSH;
4093 * When ALTQ is enabled, this will also take care of purging the
4100 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4101 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4102 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4103 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4106 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4108 if_ctx_t ctx = if_getsoftc(ifp);
4109 struct ifreq *ifr = (struct ifreq *)data;
4110 #if defined(INET) || defined(INET6)
4111 struct ifaddr *ifa = (struct ifaddr *)data;
4113 bool avoid_reset = false;
4114 int err = 0, reinit = 0, bits;
4119 if (ifa->ifa_addr->sa_family == AF_INET)
4123 if (ifa->ifa_addr->sa_family == AF_INET6)
4127 ** Calling init results in link renegotiation,
4128 ** so we avoid doing it when possible.
4131 if_setflagbits(ifp, IFF_UP,0);
4132 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4135 if (!(if_getflags(ifp) & IFF_NOARP))
4136 arp_ifinit(ifp, ifa);
4139 err = ether_ioctl(ifp, command, data);
4143 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4147 bits = if_getdrvflags(ifp);
4148 /* stop the driver and free any clusters before proceeding */
4151 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4153 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4154 ctx->ifc_flags |= IFC_MULTISEG;
4156 ctx->ifc_flags &= ~IFC_MULTISEG;
4158 err = if_setmtu(ifp, ifr->ifr_mtu);
4160 iflib_init_locked(ctx);
4162 if_setdrvflags(ifp, bits);
4168 if (if_getflags(ifp) & IFF_UP) {
4169 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4170 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4171 (IFF_PROMISC | IFF_ALLMULTI)) {
4172 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4176 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4179 ctx->ifc_if_flags = if_getflags(ifp);
4184 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4186 IFDI_INTR_DISABLE(ctx);
4187 IFDI_MULTI_SET(ctx);
4188 IFDI_INTR_ENABLE(ctx);
4194 IFDI_MEDIA_SET(ctx);
4199 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4203 struct ifi2creq i2c;
4205 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4208 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4212 if (i2c.len > sizeof(i2c.data)) {
4217 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4218 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4224 int mask, setmask, oldmask;
4226 oldmask = if_getcapenable(ifp);
4227 mask = ifr->ifr_reqcap ^ oldmask;
4228 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4231 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4233 setmask |= (mask & IFCAP_FLAGS);
4234 setmask |= (mask & IFCAP_WOL);
4237 * If any RX csum has changed, change all the ones that
4238 * are supported by the driver.
4240 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4241 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4242 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4246 * want to ensure that traffic has stopped before we change any of the flags
4250 bits = if_getdrvflags(ifp);
4251 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4254 if_togglecapenable(ifp, setmask);
4256 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4257 iflib_init_locked(ctx);
4259 if_setdrvflags(ifp, bits);
4266 case SIOCGPRIVATE_0:
4270 err = IFDI_PRIV_IOCTL(ctx, command, data);
4274 err = ether_ioctl(ifp, command, data);
4283 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4285 if_ctx_t ctx = if_getsoftc(ifp);
4287 return (IFDI_GET_COUNTER(ctx, cnt));
4290 /*********************************************************************
4292 * OTHER FUNCTIONS EXPORTED TO THE STACK
4294 **********************************************************************/
4297 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4299 if_ctx_t ctx = if_getsoftc(ifp);
4301 if ((void *)ctx != arg)
4304 if ((vtag == 0) || (vtag > 4095))
4307 if (iflib_in_detach(ctx))
4311 IFDI_VLAN_REGISTER(ctx, vtag);
4312 /* Re-init to load the changes */
4313 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4314 iflib_if_init_locked(ctx);
4319 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4321 if_ctx_t ctx = if_getsoftc(ifp);
4323 if ((void *)ctx != arg)
4326 if ((vtag == 0) || (vtag > 4095))
4330 IFDI_VLAN_UNREGISTER(ctx, vtag);
4331 /* Re-init to load the changes */
4332 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4333 iflib_if_init_locked(ctx);
4338 iflib_led_func(void *arg, int onoff)
4343 IFDI_LED_FUNC(ctx, onoff);
4347 /*********************************************************************
4349 * BUS FUNCTION DEFINITIONS
4351 **********************************************************************/
4354 iflib_device_probe(device_t dev)
4356 const pci_vendor_info_t *ent;
4357 if_shared_ctx_t sctx;
4358 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4359 uint16_t pci_vendor_id;
4361 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4364 pci_vendor_id = pci_get_vendor(dev);
4365 pci_device_id = pci_get_device(dev);
4366 pci_subvendor_id = pci_get_subvendor(dev);
4367 pci_subdevice_id = pci_get_subdevice(dev);
4368 pci_rev_id = pci_get_revid(dev);
4369 if (sctx->isc_parse_devinfo != NULL)
4370 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4372 ent = sctx->isc_vendor_info;
4373 while (ent->pvi_vendor_id != 0) {
4374 if (pci_vendor_id != ent->pvi_vendor_id) {
4378 if ((pci_device_id == ent->pvi_device_id) &&
4379 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4380 (ent->pvi_subvendor_id == 0)) &&
4381 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4382 (ent->pvi_subdevice_id == 0)) &&
4383 ((pci_rev_id == ent->pvi_rev_id) ||
4384 (ent->pvi_rev_id == 0))) {
4386 device_set_desc_copy(dev, ent->pvi_name);
4387 /* this needs to be changed to zero if the bus probing code
4388 * ever stops re-probing on best match because the sctx
4389 * may have its values over written by register calls
4390 * in subsequent probes
4392 return (BUS_PROBE_DEFAULT);
4400 iflib_device_probe_vendor(device_t dev)
4404 probe = iflib_device_probe(dev);
4405 if (probe == BUS_PROBE_DEFAULT)
4406 return (BUS_PROBE_VENDOR);
4412 iflib_reset_qvalues(if_ctx_t ctx)
4414 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4415 if_shared_ctx_t sctx = ctx->ifc_sctx;
4416 device_t dev = ctx->ifc_dev;
4419 if (ctx->ifc_sysctl_ntxqs != 0)
4420 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4421 if (ctx->ifc_sysctl_nrxqs != 0)
4422 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4424 for (i = 0; i < sctx->isc_ntxqs; i++) {
4425 if (ctx->ifc_sysctl_ntxds[i] != 0)
4426 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4428 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4431 for (i = 0; i < sctx->isc_nrxqs; i++) {
4432 if (ctx->ifc_sysctl_nrxds[i] != 0)
4433 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4435 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4438 for (i = 0; i < sctx->isc_nrxqs; i++) {
4439 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4440 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4441 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4442 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4444 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4445 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4446 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4447 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4449 if (!powerof2(scctx->isc_nrxd[i])) {
4450 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4451 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4452 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4456 for (i = 0; i < sctx->isc_ntxqs; i++) {
4457 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4458 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4459 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4460 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4462 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4463 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4464 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4465 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4467 if (!powerof2(scctx->isc_ntxd[i])) {
4468 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4469 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4470 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4476 iflib_add_pfil(if_ctx_t ctx)
4478 struct pfil_head *pfil;
4479 struct pfil_head_args pa;
4483 pa.pa_version = PFIL_VERSION;
4484 pa.pa_flags = PFIL_IN;
4485 pa.pa_type = PFIL_TYPE_ETHERNET;
4486 pa.pa_headname = ctx->ifc_ifp->if_xname;
4487 pfil = pfil_head_register(&pa);
4489 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4495 iflib_rem_pfil(if_ctx_t ctx)
4497 struct pfil_head *pfil;
4501 rxq = ctx->ifc_rxqs;
4503 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4506 pfil_head_unregister(pfil);
4510 get_ctx_core_offset(if_ctx_t ctx)
4512 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4513 struct cpu_offset *op;
4515 uint16_t ret = ctx->ifc_sysctl_core_offset;
4517 if (ret != CORE_OFFSET_UNSPECIFIED)
4520 if (ctx->ifc_sysctl_separate_txrx)
4521 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4523 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4525 mtx_lock(&cpu_offset_mtx);
4526 SLIST_FOREACH(op, &cpu_offsets, entries) {
4527 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4530 MPASS(op->refcount < UINT_MAX);
4535 if (ret == CORE_OFFSET_UNSPECIFIED) {
4537 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4540 device_printf(ctx->ifc_dev,
4541 "allocation for cpu offset failed.\n");
4545 CPU_COPY(&ctx->ifc_cpus, &op->set);
4546 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4549 mtx_unlock(&cpu_offset_mtx);
4555 unref_ctx_core_offset(if_ctx_t ctx)
4557 struct cpu_offset *op, *top;
4559 mtx_lock(&cpu_offset_mtx);
4560 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4561 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4562 MPASS(op->refcount > 0);
4564 if (op->refcount == 0) {
4565 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4571 mtx_unlock(&cpu_offset_mtx);
4575 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4579 if_softc_ctx_t scctx;
4580 kobjop_desc_t kobj_desc;
4581 kobj_method_t *kobj_method;
4583 uint16_t main_rxq, main_txq;
4585 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4588 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4589 device_set_softc(dev, ctx);
4590 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4593 ctx->ifc_sctx = sctx;
4595 ctx->ifc_softc = sc;
4597 if ((err = iflib_register(ctx)) != 0) {
4598 device_printf(dev, "iflib_register failed %d\n", err);
4601 iflib_add_device_sysctl_pre(ctx);
4603 scctx = &ctx->ifc_softc_ctx;
4606 iflib_reset_qvalues(ctx);
4608 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4609 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4612 _iflib_pre_assert(scctx);
4613 ctx->ifc_txrx = *scctx->isc_txrx;
4615 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4616 ctx->ifc_mediap = scctx->isc_media;
4619 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4620 MPASS(scctx->isc_tx_csum_flags);
4623 if_setcapabilities(ifp,
4624 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4625 if_setcapenable(ifp,
4626 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4628 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4629 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4630 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4631 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4633 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4634 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4636 /* XXX change for per-queue sizes */
4637 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4638 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4640 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4641 MAX_SINGLE_PACKET_FRACTION)
4642 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4643 MAX_SINGLE_PACKET_FRACTION);
4644 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4645 MAX_SINGLE_PACKET_FRACTION)
4646 scctx->isc_tx_tso_segments_max = max(1,
4647 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4649 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4650 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4652 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4655 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4658 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4659 * into account. In the worst case, each of these calls will
4660 * add another mbuf and, thus, the requirement for another DMA
4661 * segment. So for best performance, it doesn't make sense to
4662 * advertize a maximum of TSO segments that typically will
4663 * require defragmentation in iflib_encap().
4665 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4666 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4668 if (scctx->isc_rss_table_size == 0)
4669 scctx->isc_rss_table_size = 64;
4670 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4672 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4673 /* XXX format name */
4674 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4675 NULL, NULL, "admin");
4677 /* Set up cpu set. If it fails, use the set of all CPUs. */
4678 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4679 device_printf(dev, "Unable to fetch CPU list\n");
4680 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4682 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4685 ** Now set up MSI or MSI-X, should return us the number of supported
4686 ** vectors (will be 1 for a legacy interrupt and MSI).
4688 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4689 msix = scctx->isc_vectors;
4690 } else if (scctx->isc_msix_bar != 0)
4692 * The simple fact that isc_msix_bar is not 0 does not mean we
4693 * we have a good value there that is known to work.
4695 msix = iflib_msix_init(ctx);
4697 scctx->isc_vectors = 1;
4698 scctx->isc_ntxqsets = 1;
4699 scctx->isc_nrxqsets = 1;
4700 scctx->isc_intr = IFLIB_INTR_LEGACY;
4703 /* Get memory for the station queues */
4704 if ((err = iflib_queues_alloc(ctx))) {
4705 device_printf(dev, "Unable to allocate queue memory\n");
4706 goto fail_intr_free;
4709 if ((err = iflib_qset_structures_setup(ctx)))
4713 * Now that we know how many queues there are, get the core offset.
4715 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4719 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4720 * aren't the default NULL implementation.
4722 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4723 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4725 if (kobj_method == &kobj_desc->deflt) {
4727 "MSI-X requires ifdi_rx_queue_intr_enable method");
4731 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4732 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4734 if (kobj_method == &kobj_desc->deflt) {
4736 "MSI-X requires ifdi_tx_queue_intr_enable method");
4742 * Assign the MSI-X vectors.
4743 * Note that the default NULL ifdi_msix_intr_assign method will
4746 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4748 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4752 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4754 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4758 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4759 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4764 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4766 goto fail_intr_free;
4769 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4771 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4772 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4777 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4778 * This must appear after the call to ether_ifattach() because
4779 * ether_ifattach() sets if_hdrlen to the default value.
4781 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4782 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4784 if ((err = iflib_netmap_attach(ctx))) {
4785 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4790 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4792 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4793 iflib_add_device_sysctl_post(ctx);
4794 iflib_add_pfil(ctx);
4795 ctx->ifc_flags |= IFC_INIT_DONE;
4801 ether_ifdetach(ctx->ifc_ifp);
4803 iflib_free_intr_mem(ctx);
4805 iflib_tx_structures_free(ctx);
4806 iflib_rx_structures_free(ctx);
4807 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4811 iflib_deregister(ctx);
4813 device_set_softc(ctx->ifc_dev, NULL);
4814 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4815 free(ctx->ifc_softc, M_IFLIB);
4821 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4822 struct iflib_cloneattach_ctx *clctx)
4827 if_softc_ctx_t scctx;
4833 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4834 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4835 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4836 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4837 ctx->ifc_flags |= IFC_PSEUDO;
4839 ctx->ifc_sctx = sctx;
4840 ctx->ifc_softc = sc;
4843 if ((err = iflib_register(ctx)) != 0) {
4844 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4847 iflib_add_device_sysctl_pre(ctx);
4849 scctx = &ctx->ifc_softc_ctx;
4852 iflib_reset_qvalues(ctx);
4854 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4855 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4858 if (sctx->isc_flags & IFLIB_GEN_MAC)
4859 ether_gen_addr(ifp, &ctx->ifc_mac);
4860 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4861 clctx->cc_params)) != 0) {
4862 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4865 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4866 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4867 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4870 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4871 MPASS(scctx->isc_tx_csum_flags);
4874 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4875 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4877 ifp->if_flags |= IFF_NOGROUP;
4878 if (sctx->isc_flags & IFLIB_PSEUDO) {
4879 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4881 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4882 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4888 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4889 * This must appear after the call to ether_ifattach() because
4890 * ether_ifattach() sets if_hdrlen to the default value.
4892 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4893 if_setifheaderlen(ifp,
4894 sizeof(struct ether_vlan_header));
4896 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4897 iflib_add_device_sysctl_post(ctx);
4898 ctx->ifc_flags |= IFC_INIT_DONE;
4901 _iflib_pre_assert(scctx);
4902 ctx->ifc_txrx = *scctx->isc_txrx;
4904 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4905 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4906 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4907 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4909 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4910 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4912 /* XXX change for per-queue sizes */
4913 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4914 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4916 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4917 MAX_SINGLE_PACKET_FRACTION)
4918 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4919 MAX_SINGLE_PACKET_FRACTION);
4920 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4921 MAX_SINGLE_PACKET_FRACTION)
4922 scctx->isc_tx_tso_segments_max = max(1,
4923 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4925 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4926 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4928 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4931 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4934 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4935 * into account. In the worst case, each of these calls will
4936 * add another mbuf and, thus, the requirement for another DMA
4937 * segment. So for best performance, it doesn't make sense to
4938 * advertize a maximum of TSO segments that typically will
4939 * require defragmentation in iflib_encap().
4941 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4942 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4944 if (scctx->isc_rss_table_size == 0)
4945 scctx->isc_rss_table_size = 64;
4946 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4948 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4949 /* XXX format name */
4950 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4951 NULL, NULL, "admin");
4953 /* XXX --- can support > 1 -- but keep it simple for now */
4954 scctx->isc_intr = IFLIB_INTR_LEGACY;
4956 /* Get memory for the station queues */
4957 if ((err = iflib_queues_alloc(ctx))) {
4958 device_printf(dev, "Unable to allocate queue memory\n");
4959 goto fail_iflib_detach;
4962 if ((err = iflib_qset_structures_setup(ctx))) {
4963 device_printf(dev, "qset structure setup failed %d\n", err);
4968 * XXX What if anything do we want to do about interrupts?
4970 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4971 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4972 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4977 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4978 * This must appear after the call to ether_ifattach() because
4979 * ether_ifattach() sets if_hdrlen to the default value.
4981 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4982 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4984 /* XXX handle more than one queue */
4985 for (i = 0; i < scctx->isc_nrxqsets; i++)
4986 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4990 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4991 iflib_add_device_sysctl_post(ctx);
4992 ctx->ifc_flags |= IFC_INIT_DONE;
4997 ether_ifdetach(ctx->ifc_ifp);
4999 iflib_tx_structures_free(ctx);
5000 iflib_rx_structures_free(ctx);
5005 iflib_deregister(ctx);
5007 free(ctx->ifc_softc, M_IFLIB);
5013 iflib_pseudo_deregister(if_ctx_t ctx)
5015 if_t ifp = ctx->ifc_ifp;
5019 struct taskqgroup *tqg;
5022 /* Unregister VLAN event handlers early */
5023 iflib_unregister_vlan_handlers(ctx);
5025 ether_ifdetach(ifp);
5026 /* XXX drain any dependent tasks */
5027 tqg = qgroup_if_io_tqg;
5028 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5029 callout_drain(&txq->ift_timer);
5030 if (txq->ift_task.gt_uniq != NULL)
5031 taskqgroup_detach(tqg, &txq->ift_task);
5033 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5034 callout_drain(&rxq->ifr_watchdog);
5035 if (rxq->ifr_task.gt_uniq != NULL)
5036 taskqgroup_detach(tqg, &rxq->ifr_task);
5038 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5039 free(fl->ifl_rx_bitmap, M_IFLIB);
5041 tqg = qgroup_if_config_tqg;
5042 if (ctx->ifc_admin_task.gt_uniq != NULL)
5043 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5044 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5045 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5047 iflib_tx_structures_free(ctx);
5048 iflib_rx_structures_free(ctx);
5050 iflib_deregister(ctx);
5052 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5053 free(ctx->ifc_softc, M_IFLIB);
5059 iflib_device_attach(device_t dev)
5062 if_shared_ctx_t sctx;
5064 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5067 pci_enable_busmaster(dev);
5069 return (iflib_device_register(dev, NULL, sctx, &ctx));
5073 iflib_device_deregister(if_ctx_t ctx)
5075 if_t ifp = ctx->ifc_ifp;
5078 device_t dev = ctx->ifc_dev;
5080 struct taskqgroup *tqg;
5083 /* Make sure VLANS are not using driver */
5084 if (if_vlantrunkinuse(ifp)) {
5085 device_printf(dev, "Vlan in use, detach first\n");
5089 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5090 device_printf(dev, "SR-IOV in use; detach first.\n");
5096 ctx->ifc_flags |= IFC_IN_DETACH;
5099 /* Unregister VLAN handlers before calling iflib_stop() */
5100 iflib_unregister_vlan_handlers(ctx);
5102 iflib_netmap_detach(ifp);
5103 ether_ifdetach(ifp);
5109 iflib_rem_pfil(ctx);
5110 if (ctx->ifc_led_dev != NULL)
5111 led_destroy(ctx->ifc_led_dev);
5112 /* XXX drain any dependent tasks */
5113 tqg = qgroup_if_io_tqg;
5114 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5115 callout_drain(&txq->ift_timer);
5116 if (txq->ift_task.gt_uniq != NULL)
5117 taskqgroup_detach(tqg, &txq->ift_task);
5119 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5120 if (rxq->ifr_task.gt_uniq != NULL)
5121 taskqgroup_detach(tqg, &rxq->ifr_task);
5123 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5124 free(fl->ifl_rx_bitmap, M_IFLIB);
5126 tqg = qgroup_if_config_tqg;
5127 if (ctx->ifc_admin_task.gt_uniq != NULL)
5128 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5129 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5130 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5135 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5136 iflib_free_intr_mem(ctx);
5138 bus_generic_detach(dev);
5140 iflib_tx_structures_free(ctx);
5141 iflib_rx_structures_free(ctx);
5143 iflib_deregister(ctx);
5145 device_set_softc(ctx->ifc_dev, NULL);
5146 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5147 free(ctx->ifc_softc, M_IFLIB);
5148 unref_ctx_core_offset(ctx);
5154 iflib_free_intr_mem(if_ctx_t ctx)
5157 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5158 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5160 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5161 pci_release_msi(ctx->ifc_dev);
5163 if (ctx->ifc_msix_mem != NULL) {
5164 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5165 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5166 ctx->ifc_msix_mem = NULL;
5171 iflib_device_detach(device_t dev)
5173 if_ctx_t ctx = device_get_softc(dev);
5175 return (iflib_device_deregister(ctx));
5179 iflib_device_suspend(device_t dev)
5181 if_ctx_t ctx = device_get_softc(dev);
5187 return bus_generic_suspend(dev);
5190 iflib_device_shutdown(device_t dev)
5192 if_ctx_t ctx = device_get_softc(dev);
5198 return bus_generic_suspend(dev);
5203 iflib_device_resume(device_t dev)
5205 if_ctx_t ctx = device_get_softc(dev);
5206 iflib_txq_t txq = ctx->ifc_txqs;
5210 iflib_if_init_locked(ctx);
5212 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5213 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5215 return (bus_generic_resume(dev));
5219 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5222 if_ctx_t ctx = device_get_softc(dev);
5225 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5232 iflib_device_iov_uninit(device_t dev)
5234 if_ctx_t ctx = device_get_softc(dev);
5237 IFDI_IOV_UNINIT(ctx);
5242 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5245 if_ctx_t ctx = device_get_softc(dev);
5248 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5254 /*********************************************************************
5256 * MODULE FUNCTION DEFINITIONS
5258 **********************************************************************/
5261 * - Start a fast taskqueue thread for each core
5262 * - Start a taskqueue for control operations
5265 iflib_module_init(void)
5271 iflib_module_event_handler(module_t mod, int what, void *arg)
5277 if ((err = iflib_module_init()) != 0)
5283 return (EOPNOTSUPP);
5289 /*********************************************************************
5291 * PUBLIC FUNCTION DEFINITIONS
5292 * ordered as in iflib.h
5294 **********************************************************************/
5298 _iflib_assert(if_shared_ctx_t sctx)
5302 MPASS(sctx->isc_tx_maxsize);
5303 MPASS(sctx->isc_tx_maxsegsize);
5305 MPASS(sctx->isc_rx_maxsize);
5306 MPASS(sctx->isc_rx_nsegments);
5307 MPASS(sctx->isc_rx_maxsegsize);
5309 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5310 for (i = 0; i < sctx->isc_nrxqs; i++) {
5311 MPASS(sctx->isc_nrxd_min[i]);
5312 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5313 MPASS(sctx->isc_nrxd_max[i]);
5314 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5315 MPASS(sctx->isc_nrxd_default[i]);
5316 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5319 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5320 for (i = 0; i < sctx->isc_ntxqs; i++) {
5321 MPASS(sctx->isc_ntxd_min[i]);
5322 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5323 MPASS(sctx->isc_ntxd_max[i]);
5324 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5325 MPASS(sctx->isc_ntxd_default[i]);
5326 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5331 _iflib_pre_assert(if_softc_ctx_t scctx)
5334 MPASS(scctx->isc_txrx->ift_txd_encap);
5335 MPASS(scctx->isc_txrx->ift_txd_flush);
5336 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5337 MPASS(scctx->isc_txrx->ift_rxd_available);
5338 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5339 MPASS(scctx->isc_txrx->ift_rxd_refill);
5340 MPASS(scctx->isc_txrx->ift_rxd_flush);
5344 iflib_register(if_ctx_t ctx)
5346 if_shared_ctx_t sctx = ctx->ifc_sctx;
5347 driver_t *driver = sctx->isc_driver;
5348 device_t dev = ctx->ifc_dev;
5351 _iflib_assert(sctx);
5354 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5355 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5357 device_printf(dev, "can not allocate ifnet structure\n");
5362 * Initialize our context's device specific methods
5364 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5365 kobj_class_compile((kobj_class_t) driver);
5367 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5368 if_setsoftc(ifp, ctx);
5369 if_setdev(ifp, dev);
5370 if_setinitfn(ifp, iflib_if_init);
5371 if_setioctlfn(ifp, iflib_if_ioctl);
5373 if_setstartfn(ifp, iflib_altq_if_start);
5374 if_settransmitfn(ifp, iflib_altq_if_transmit);
5375 if_setsendqready(ifp);
5377 if_settransmitfn(ifp, iflib_if_transmit);
5379 if_setqflushfn(ifp, iflib_if_qflush);
5380 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
5383 ctx->ifc_vlan_attach_event =
5384 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5385 EVENTHANDLER_PRI_FIRST);
5386 ctx->ifc_vlan_detach_event =
5387 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5388 EVENTHANDLER_PRI_FIRST);
5390 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5391 ctx->ifc_mediap = &ctx->ifc_media;
5392 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5393 iflib_media_change, iflib_media_status);
5399 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5401 /* Unregister VLAN events */
5402 if (ctx->ifc_vlan_attach_event != NULL) {
5403 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5404 ctx->ifc_vlan_attach_event = NULL;
5406 if (ctx->ifc_vlan_detach_event != NULL) {
5407 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5408 ctx->ifc_vlan_detach_event = NULL;
5414 iflib_deregister(if_ctx_t ctx)
5416 if_t ifp = ctx->ifc_ifp;
5418 /* Remove all media */
5419 ifmedia_removeall(&ctx->ifc_media);
5421 /* Ensure that VLAN event handlers are unregistered */
5422 iflib_unregister_vlan_handlers(ctx);
5424 /* Release kobject reference */
5425 kobj_delete((kobj_t) ctx, NULL);
5427 /* Free the ifnet structure */
5430 STATE_LOCK_DESTROY(ctx);
5432 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5433 CTX_LOCK_DESTROY(ctx);
5437 iflib_queues_alloc(if_ctx_t ctx)
5439 if_shared_ctx_t sctx = ctx->ifc_sctx;
5440 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5441 device_t dev = ctx->ifc_dev;
5442 int nrxqsets = scctx->isc_nrxqsets;
5443 int ntxqsets = scctx->isc_ntxqsets;
5446 iflib_fl_t fl = NULL;
5447 int i, j, cpu, err, txconf, rxconf;
5448 iflib_dma_info_t ifdip;
5449 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5450 uint32_t *txqsizes = scctx->isc_txqsizes;
5451 uint8_t nrxqs = sctx->isc_nrxqs;
5452 uint8_t ntxqs = sctx->isc_ntxqs;
5453 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5457 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5458 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5460 /* Allocate the TX ring struct memory */
5461 if (!(ctx->ifc_txqs =
5462 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5463 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5464 device_printf(dev, "Unable to allocate TX ring memory\n");
5469 /* Now allocate the RX */
5470 if (!(ctx->ifc_rxqs =
5471 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5472 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5473 device_printf(dev, "Unable to allocate RX ring memory\n");
5478 txq = ctx->ifc_txqs;
5479 rxq = ctx->ifc_rxqs;
5482 * XXX handle allocation failure
5484 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5485 /* Set up some basics */
5487 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5488 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5490 "Unable to allocate TX DMA info memory\n");
5494 txq->ift_ifdi = ifdip;
5495 for (j = 0; j < ntxqs; j++, ifdip++) {
5496 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5498 "Unable to allocate TX descriptors\n");
5502 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5503 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5507 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5508 txq->ift_br_offset = 1;
5510 txq->ift_br_offset = 0;
5513 txq->ift_timer.c_cpu = cpu;
5515 if (iflib_txsd_alloc(txq)) {
5516 device_printf(dev, "Critical Failure setting up TX buffers\n");
5521 /* Initialize the TX lock */
5522 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5523 device_get_nameunit(dev), txq->ift_id);
5524 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5525 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5527 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5528 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5530 /* XXX free any allocated rings */
5531 device_printf(dev, "Unable to allocate buf_ring\n");
5536 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5537 /* Set up some basics */
5538 callout_init(&rxq->ifr_watchdog, 1);
5540 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5541 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5543 "Unable to allocate RX DMA info memory\n");
5548 rxq->ifr_ifdi = ifdip;
5549 /* XXX this needs to be changed if #rx queues != #tx queues */
5550 rxq->ifr_ntxqirq = 1;
5551 rxq->ifr_txqid[0] = i;
5552 for (j = 0; j < nrxqs; j++, ifdip++) {
5553 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5555 "Unable to allocate RX descriptors\n");
5559 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5563 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5564 rxq->ifr_fl_offset = 1;
5566 rxq->ifr_fl_offset = 0;
5568 rxq->ifr_nfl = nfree_lists;
5570 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5571 device_printf(dev, "Unable to allocate free list memory\n");
5576 for (j = 0; j < nfree_lists; j++) {
5577 fl[j].ifl_rxq = rxq;
5579 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5580 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5582 /* Allocate receive buffers for the ring */
5583 if (iflib_rxsd_alloc(rxq)) {
5585 "Critical Failure setting up receive buffers\n");
5590 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5591 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5596 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5597 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5598 for (i = 0; i < ntxqsets; i++) {
5599 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5601 for (j = 0; j < ntxqs; j++, di++) {
5602 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5603 paddrs[i*ntxqs + j] = di->idi_paddr;
5606 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5607 device_printf(ctx->ifc_dev,
5608 "Unable to allocate device TX queue\n");
5609 iflib_tx_structures_free(ctx);
5610 free(vaddrs, M_IFLIB);
5611 free(paddrs, M_IFLIB);
5614 free(vaddrs, M_IFLIB);
5615 free(paddrs, M_IFLIB);
5618 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5619 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5620 for (i = 0; i < nrxqsets; i++) {
5621 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5623 for (j = 0; j < nrxqs; j++, di++) {
5624 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5625 paddrs[i*nrxqs + j] = di->idi_paddr;
5628 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5629 device_printf(ctx->ifc_dev,
5630 "Unable to allocate device RX queue\n");
5631 iflib_tx_structures_free(ctx);
5632 free(vaddrs, M_IFLIB);
5633 free(paddrs, M_IFLIB);
5636 free(vaddrs, M_IFLIB);
5637 free(paddrs, M_IFLIB);
5641 /* XXX handle allocation failure changes */
5645 if (ctx->ifc_rxqs != NULL)
5646 free(ctx->ifc_rxqs, M_IFLIB);
5647 ctx->ifc_rxqs = NULL;
5648 if (ctx->ifc_txqs != NULL)
5649 free(ctx->ifc_txqs, M_IFLIB);
5650 ctx->ifc_txqs = NULL;
5656 iflib_tx_structures_setup(if_ctx_t ctx)
5658 iflib_txq_t txq = ctx->ifc_txqs;
5661 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5662 iflib_txq_setup(txq);
5668 iflib_tx_structures_free(if_ctx_t ctx)
5670 iflib_txq_t txq = ctx->ifc_txqs;
5671 if_shared_ctx_t sctx = ctx->ifc_sctx;
5674 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5675 for (j = 0; j < sctx->isc_ntxqs; j++)
5676 iflib_dma_free(&txq->ift_ifdi[j]);
5677 iflib_txq_destroy(txq);
5679 free(ctx->ifc_txqs, M_IFLIB);
5680 ctx->ifc_txqs = NULL;
5681 IFDI_QUEUES_FREE(ctx);
5684 /*********************************************************************
5686 * Initialize all receive rings.
5688 **********************************************************************/
5690 iflib_rx_structures_setup(if_ctx_t ctx)
5692 iflib_rxq_t rxq = ctx->ifc_rxqs;
5694 #if defined(INET6) || defined(INET)
5698 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5699 #if defined(INET6) || defined(INET)
5700 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5701 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5702 TCP_LRO_ENTRIES, min(1024,
5703 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5705 device_printf(ctx->ifc_dev,
5706 "LRO Initialization failed!\n");
5711 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5714 #if defined(INET6) || defined(INET)
5717 * Free LRO resources allocated so far, we will only handle
5718 * the rings that completed, the failing case will have
5719 * cleaned up for itself. 'q' failed, so its the terminus.
5721 rxq = ctx->ifc_rxqs;
5722 for (i = 0; i < q; ++i, rxq++) {
5723 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5724 tcp_lro_free(&rxq->ifr_lc);
5730 /*********************************************************************
5732 * Free all receive rings.
5734 **********************************************************************/
5736 iflib_rx_structures_free(if_ctx_t ctx)
5738 iflib_rxq_t rxq = ctx->ifc_rxqs;
5739 if_shared_ctx_t sctx = ctx->ifc_sctx;
5742 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5743 for (j = 0; j < sctx->isc_nrxqs; j++)
5744 iflib_dma_free(&rxq->ifr_ifdi[j]);
5745 iflib_rx_sds_free(rxq);
5746 #if defined(INET6) || defined(INET)
5747 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5748 tcp_lro_free(&rxq->ifr_lc);
5751 free(ctx->ifc_rxqs, M_IFLIB);
5752 ctx->ifc_rxqs = NULL;
5756 iflib_qset_structures_setup(if_ctx_t ctx)
5761 * It is expected that the caller takes care of freeing queues if this
5764 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5765 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5769 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5770 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5776 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5777 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5780 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5785 find_nth(if_ctx_t ctx, int qid)
5788 int i, cpuid, eqid, count;
5790 CPU_COPY(&ctx->ifc_cpus, &cpus);
5791 count = CPU_COUNT(&cpus);
5793 /* clear up to the qid'th bit */
5794 for (i = 0; i < eqid; i++) {
5795 cpuid = CPU_FFS(&cpus);
5797 CPU_CLR(cpuid-1, &cpus);
5799 cpuid = CPU_FFS(&cpus);
5805 extern struct cpu_group *cpu_top; /* CPU topology */
5808 find_child_with_core(int cpu, struct cpu_group *grp)
5812 if (grp->cg_children == 0)
5815 MPASS(grp->cg_child);
5816 for (i = 0; i < grp->cg_children; i++) {
5817 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5825 * Find the nth "close" core to the specified core
5826 * "close" is defined as the deepest level that shares
5827 * at least an L2 cache. With threads, this will be
5828 * threads on the same core. If the shared cache is L3
5829 * or higher, simply returns the same core.
5832 find_close_core(int cpu, int core_offset)
5834 struct cpu_group *grp;
5843 while ((i = find_child_with_core(cpu, grp)) != -1) {
5844 /* If the child only has one cpu, don't descend */
5845 if (grp->cg_child[i].cg_count <= 1)
5847 grp = &grp->cg_child[i];
5850 /* If they don't share at least an L2 cache, use the same CPU */
5851 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5855 CPU_COPY(&grp->cg_mask, &cs);
5857 /* Add the selected CPU offset to core offset. */
5858 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5859 if (fcpu - 1 == cpu)
5861 CPU_CLR(fcpu - 1, &cs);
5867 CPU_COPY(&grp->cg_mask, &cs);
5868 for (i = core_offset % grp->cg_count; i > 0; i--) {
5869 MPASS(CPU_FFS(&cs));
5870 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5872 MPASS(CPU_FFS(&cs));
5873 return CPU_FFS(&cs) - 1;
5877 find_close_core(int cpu, int core_offset __unused)
5884 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5888 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5889 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5890 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5892 case IFLIB_INTR_RXTX:
5893 /* RX queues get the specified core */
5894 return qid / CPU_COUNT(&ctx->ifc_cpus);
5900 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5901 #define find_close_core(cpuid, tid) CPU_FIRST()
5902 #define find_nth(ctx, gid) CPU_FIRST()
5905 /* Just to avoid copy/paste */
5907 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5908 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5912 int co, cpuid, err, tid;
5915 co = ctx->ifc_sysctl_core_offset;
5916 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5917 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5918 cpuid = find_nth(ctx, qid + co);
5919 tid = get_core_offset(ctx, type, qid);
5921 device_printf(dev, "get_core_offset failed\n");
5922 return (EOPNOTSUPP);
5924 cpuid = find_close_core(cpuid, tid);
5925 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5928 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5932 if (cpuid > ctx->ifc_cpuid_highest)
5933 ctx->ifc_cpuid_highest = cpuid;
5939 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5940 iflib_intr_type_t type, driver_filter_t *filter,
5941 void *filter_arg, int qid, const char *name)
5944 struct grouptask *gtask;
5945 struct taskqgroup *tqg;
5946 iflib_filter_info_t info;
5949 driver_filter_t *intr_fast;
5952 info = &ctx->ifc_filter_info;
5956 /* XXX merge tx/rx for netmap? */
5958 q = &ctx->ifc_txqs[qid];
5959 info = &ctx->ifc_txqs[qid].ift_filter_info;
5960 gtask = &ctx->ifc_txqs[qid].ift_task;
5961 tqg = qgroup_if_io_tqg;
5963 intr_fast = iflib_fast_intr;
5964 GROUPTASK_INIT(gtask, 0, fn, q);
5965 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5968 q = &ctx->ifc_rxqs[qid];
5969 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5970 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5971 tqg = qgroup_if_io_tqg;
5973 intr_fast = iflib_fast_intr;
5974 NET_GROUPTASK_INIT(gtask, 0, fn, q);
5976 case IFLIB_INTR_RXTX:
5977 q = &ctx->ifc_rxqs[qid];
5978 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5979 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5980 tqg = qgroup_if_io_tqg;
5982 intr_fast = iflib_fast_intr_rxtx;
5983 NET_GROUPTASK_INIT(gtask, 0, fn, q);
5985 case IFLIB_INTR_ADMIN:
5988 info = &ctx->ifc_filter_info;
5989 gtask = &ctx->ifc_admin_task;
5990 tqg = qgroup_if_config_tqg;
5991 fn = _task_fn_admin;
5992 intr_fast = iflib_fast_intr_ctx;
5995 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6000 info->ifi_filter = filter;
6001 info->ifi_filter_arg = filter_arg;
6002 info->ifi_task = gtask;
6006 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6008 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6011 if (type == IFLIB_INTR_ADMIN)
6015 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6020 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6027 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6029 struct grouptask *gtask;
6030 struct taskqgroup *tqg;
6037 q = &ctx->ifc_txqs[qid];
6038 gtask = &ctx->ifc_txqs[qid].ift_task;
6039 tqg = qgroup_if_io_tqg;
6041 GROUPTASK_INIT(gtask, 0, fn, q);
6044 q = &ctx->ifc_rxqs[qid];
6045 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6046 tqg = qgroup_if_io_tqg;
6048 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6050 case IFLIB_INTR_IOV:
6052 gtask = &ctx->ifc_vflr_task;
6053 tqg = qgroup_if_config_tqg;
6055 GROUPTASK_INIT(gtask, 0, fn, q);
6058 panic("unknown net intr type");
6061 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6064 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6067 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6072 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6076 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6079 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6080 rman_get_rid(irq->ii_res), irq->ii_res);
6084 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6086 iflib_txq_t txq = ctx->ifc_txqs;
6087 iflib_rxq_t rxq = ctx->ifc_rxqs;
6088 if_irq_t irq = &ctx->ifc_legacy_irq;
6089 iflib_filter_info_t info;
6091 struct grouptask *gtask;
6092 struct resource *res;
6093 struct taskqgroup *tqg;
6098 q = &ctx->ifc_rxqs[0];
6099 info = &rxq[0].ifr_filter_info;
6100 gtask = &rxq[0].ifr_task;
6101 tqg = qgroup_if_io_tqg;
6103 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6105 ctx->ifc_flags |= IFC_LEGACY;
6106 info->ifi_filter = filter;
6107 info->ifi_filter_arg = filter_arg;
6108 info->ifi_task = gtask;
6109 info->ifi_ctx = rx_only ? ctx : q;
6112 /* We allocate a single interrupt resource */
6113 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6114 iflib_fast_intr_rxtx, NULL, info, name);
6117 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6119 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6121 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6122 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6128 iflib_led_create(if_ctx_t ctx)
6131 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6132 device_get_nameunit(ctx->ifc_dev));
6136 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6139 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6143 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6146 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6150 iflib_admin_intr_deferred(if_ctx_t ctx)
6153 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6154 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6158 iflib_iov_intr_deferred(if_ctx_t ctx)
6161 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6165 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6168 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6173 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6177 GROUPTASK_INIT(gtask, 0, fn, ctx);
6178 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6183 iflib_config_gtask_deinit(struct grouptask *gtask)
6186 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6190 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6192 if_t ifp = ctx->ifc_ifp;
6193 iflib_txq_t txq = ctx->ifc_txqs;
6195 if_setbaudrate(ifp, baudrate);
6196 if (baudrate >= IF_Gbps(10)) {
6198 ctx->ifc_flags |= IFC_PREFETCH;
6201 /* If link down, disable watchdog */
6202 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6203 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6204 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6206 ctx->ifc_link_state = link_state;
6207 if_link_state_change(ifp, link_state);
6211 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6215 int credits_pre = txq->ift_cidx_processed;
6218 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6219 BUS_DMASYNC_POSTREAD);
6220 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6223 txq->ift_processed += credits;
6224 txq->ift_cidx_processed += credits;
6226 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6227 if (txq->ift_cidx_processed >= txq->ift_size)
6228 txq->ift_cidx_processed -= txq->ift_size;
6233 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6238 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6239 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6240 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6241 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6246 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6247 const char *description, if_int_delay_info_t info,
6248 int offset, int value)
6250 info->iidi_ctx = ctx;
6251 info->iidi_offset = offset;
6252 info->iidi_value = value;
6253 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6254 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6255 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6256 info, 0, iflib_sysctl_int_delay, "I", description);
6260 iflib_ctx_lock_get(if_ctx_t ctx)
6263 return (&ctx->ifc_ctx_sx);
6267 iflib_msix_init(if_ctx_t ctx)
6269 device_t dev = ctx->ifc_dev;
6270 if_shared_ctx_t sctx = ctx->ifc_sctx;
6271 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6272 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6273 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6275 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6276 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6279 device_printf(dev, "msix_init qsets capped at %d\n",
6280 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6282 /* Override by tuneable */
6283 if (scctx->isc_disable_msix)
6286 /* First try MSI-X */
6287 if ((msgs = pci_msix_count(dev)) == 0) {
6289 device_printf(dev, "MSI-X not supported or disabled\n");
6293 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6295 * bar == -1 => "trust me I know what I'm doing"
6296 * Some drivers are for hardware that is so shoddily
6297 * documented that no one knows which bars are which
6298 * so the developer has to map all bars. This hack
6299 * allows shoddy garbage to use MSI-X in this framework.
6302 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6303 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6304 if (ctx->ifc_msix_mem == NULL) {
6305 device_printf(dev, "Unable to map MSI-X table\n");
6310 admincnt = sctx->isc_admin_intrcnt;
6312 /* use only 1 qset in debug mode */
6313 queuemsgs = min(msgs - admincnt, 1);
6315 queuemsgs = msgs - admincnt;
6318 queues = imin(queuemsgs, rss_getnumbuckets());
6322 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6325 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6326 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6328 /* If we're doing RSS, clamp at the number of RSS buckets */
6329 if (queues > rss_getnumbuckets())
6330 queues = rss_getnumbuckets();
6332 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6333 rx_queues = iflib_num_rx_queues;
6337 if (rx_queues > scctx->isc_nrxqsets)
6338 rx_queues = scctx->isc_nrxqsets;
6341 * We want this to be all logical CPUs by default
6343 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6344 tx_queues = iflib_num_tx_queues;
6346 tx_queues = mp_ncpus;
6348 if (tx_queues > scctx->isc_ntxqsets)
6349 tx_queues = scctx->isc_ntxqsets;
6351 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6353 if (tx_queues != rx_queues)
6355 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6356 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6358 tx_queues = min(rx_queues, tx_queues);
6359 rx_queues = min(rx_queues, tx_queues);
6362 vectors = rx_queues + admincnt;
6363 if (msgs < vectors) {
6365 "insufficient number of MSI-X vectors "
6366 "(supported %d, need %d)\n", msgs, vectors);
6370 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6373 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6374 if (vectors != msgs) {
6376 "Unable to allocate sufficient MSI-X vectors "
6377 "(got %d, need %d)\n", vectors, msgs);
6378 pci_release_msi(dev);
6380 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6382 ctx->ifc_msix_mem = NULL;
6386 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6388 scctx->isc_vectors = vectors;
6389 scctx->isc_nrxqsets = rx_queues;
6390 scctx->isc_ntxqsets = tx_queues;
6391 scctx->isc_intr = IFLIB_INTR_MSIX;
6396 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6399 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6401 ctx->ifc_msix_mem = NULL;
6406 vectors = pci_msi_count(dev);
6407 scctx->isc_nrxqsets = 1;
6408 scctx->isc_ntxqsets = 1;
6409 scctx->isc_vectors = vectors;
6410 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6411 device_printf(dev,"Using an MSI interrupt\n");
6412 scctx->isc_intr = IFLIB_INTR_MSI;
6414 scctx->isc_vectors = 1;
6415 device_printf(dev,"Using a Legacy interrupt\n");
6416 scctx->isc_intr = IFLIB_INTR_LEGACY;
6422 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6425 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6428 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6430 const char *ring_state = "UNKNOWN";
6433 rc = sysctl_wire_old_buffer(req, 0);
6437 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6442 ring_state = ring_states[state[3]];
6444 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6445 state[0], state[1], state[2], ring_state);
6446 rc = sbuf_finish(sb);
6451 enum iflib_ndesc_handler {
6457 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6459 if_ctx_t ctx = (void *)arg1;
6460 enum iflib_ndesc_handler type = arg2;
6461 char buf[256] = {0};
6468 case IFLIB_NTXD_HANDLER:
6469 ndesc = ctx->ifc_sysctl_ntxds;
6471 nqs = ctx->ifc_sctx->isc_ntxqs;
6473 case IFLIB_NRXD_HANDLER:
6474 ndesc = ctx->ifc_sysctl_nrxds;
6476 nqs = ctx->ifc_sctx->isc_nrxqs;
6479 printf("%s: unhandled type\n", __func__);
6485 for (i=0; i<8; i++) {
6490 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6493 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6494 if (rc || req->newptr == NULL)
6497 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6498 i++, p = strsep(&next, " ,")) {
6499 ndesc[i] = strtoul(p, NULL, 10);
6505 #define NAME_BUFLEN 32
6507 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6509 device_t dev = iflib_get_dev(ctx);
6510 struct sysctl_oid_list *child, *oid_list;
6511 struct sysctl_ctx_list *ctx_list;
6512 struct sysctl_oid *node;
6514 ctx_list = device_get_sysctl_ctx(dev);
6515 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6516 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6517 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6518 oid_list = SYSCTL_CHILDREN(node);
6520 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6521 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6524 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6525 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6526 "# of txqs to use, 0 => use default #");
6527 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6528 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6529 "# of rxqs to use, 0 => use default #");
6530 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6531 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6532 "permit #txq != #rxq");
6533 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6534 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6535 "disable MSI-X (default 0)");
6536 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6537 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6538 "set the RX budget");
6539 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6540 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6541 "cause TX to abdicate instead of running to completion");
6542 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6543 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6544 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6545 "offset to start using cores at");
6546 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6547 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6548 "use separate cores for TX and RX");
6550 /* XXX change for per-queue sizes */
6551 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6552 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6553 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6554 "list of # of TX descriptors to use, 0 = use default #");
6555 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6556 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6557 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6558 "list of # of RX descriptors to use, 0 = use default #");
6562 iflib_add_device_sysctl_post(if_ctx_t ctx)
6564 if_shared_ctx_t sctx = ctx->ifc_sctx;
6565 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6566 device_t dev = iflib_get_dev(ctx);
6567 struct sysctl_oid_list *child;
6568 struct sysctl_ctx_list *ctx_list;
6573 char namebuf[NAME_BUFLEN];
6575 struct sysctl_oid *queue_node, *fl_node, *node;
6576 struct sysctl_oid_list *queue_list, *fl_list;
6577 ctx_list = device_get_sysctl_ctx(dev);
6579 node = ctx->ifc_sysctl_node;
6580 child = SYSCTL_CHILDREN(node);
6582 if (scctx->isc_ntxqsets > 100)
6584 else if (scctx->isc_ntxqsets > 10)
6588 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6589 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6590 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6591 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6592 queue_list = SYSCTL_CHILDREN(queue_node);
6594 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6596 &txq->ift_dequeued, "total mbufs freed");
6597 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6599 &txq->ift_enqueued, "total mbufs enqueued");
6601 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6603 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6604 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6606 &txq->ift_pullups, "# of times m_pullup was called");
6607 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6609 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6610 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6612 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6613 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6615 &txq->ift_map_failed, "# of times DMA map failed");
6616 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6618 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6619 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6621 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6622 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6624 &txq->ift_pidx, 1, "Producer Index");
6625 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6627 &txq->ift_cidx, 1, "Consumer Index");
6628 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6630 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6631 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6633 &txq->ift_in_use, 1, "descriptors in use");
6634 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6636 &txq->ift_processed, "descriptors procesed for clean");
6637 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6639 &txq->ift_cleaned, "total cleaned");
6640 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6641 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6642 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6643 mp_ring_state_handler, "A", "soft ring state");
6644 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6645 CTLFLAG_RD, &txq->ift_br->enqueues,
6646 "# of enqueues to the mp_ring for this queue");
6647 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6648 CTLFLAG_RD, &txq->ift_br->drops,
6649 "# of drops in the mp_ring for this queue");
6650 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6651 CTLFLAG_RD, &txq->ift_br->starts,
6652 "# of normal consumer starts in the mp_ring for this queue");
6653 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6654 CTLFLAG_RD, &txq->ift_br->stalls,
6655 "# of consumer stalls in the mp_ring for this queue");
6656 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6657 CTLFLAG_RD, &txq->ift_br->restarts,
6658 "# of consumer restarts in the mp_ring for this queue");
6659 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6660 CTLFLAG_RD, &txq->ift_br->abdications,
6661 "# of consumer abdications in the mp_ring for this queue");
6664 if (scctx->isc_nrxqsets > 100)
6666 else if (scctx->isc_nrxqsets > 10)
6670 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6671 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6672 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6673 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6674 queue_list = SYSCTL_CHILDREN(queue_node);
6675 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6676 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6678 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6681 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6682 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6683 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6684 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6685 fl_list = SYSCTL_CHILDREN(fl_node);
6686 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6688 &fl->ifl_pidx, 1, "Producer Index");
6689 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6691 &fl->ifl_cidx, 1, "Consumer Index");
6692 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6694 &fl->ifl_credits, 1, "credits available");
6695 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6697 &fl->ifl_buf_size, 1, "buffer size");
6699 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6701 &fl->ifl_m_enqueued, "mbufs allocated");
6702 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6704 &fl->ifl_m_dequeued, "mbufs freed");
6705 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6707 &fl->ifl_cl_enqueued, "clusters allocated");
6708 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6710 &fl->ifl_cl_dequeued, "clusters freed");
6719 iflib_request_reset(if_ctx_t ctx)
6723 ctx->ifc_flags |= IFC_DO_RESET;
6727 #ifndef __NO_STRICT_ALIGNMENT
6728 static struct mbuf *
6729 iflib_fixup_rx(struct mbuf *m)
6733 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6734 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6735 m->m_data += ETHER_HDR_LEN;
6738 MGETHDR(n, M_NOWAIT, MT_DATA);
6743 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6744 m->m_data += ETHER_HDR_LEN;
6745 m->m_len -= ETHER_HDR_LEN;
6746 n->m_len = ETHER_HDR_LEN;
6747 M_MOVE_PKTHDR(n, m);
6756 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6760 ctx = if_getsoftc(ifp);
6762 *nrxr = NRXQSETS(ctx);
6763 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6764 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6769 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6772 if_softc_ctx_t scctx;
6777 ctx = if_getsoftc(ifp);
6778 scctx = &ctx->ifc_softc_ctx;
6781 case DEBUGNET_START:
6782 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6783 rxq = &ctx->ifc_rxqs[i];
6784 for (j = 0; j < rxq->ifr_nfl; j++) {
6786 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6789 iflib_no_tx_batch = 1;
6797 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6803 ctx = if_getsoftc(ifp);
6804 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6808 txq = &ctx->ifc_txqs[0];
6809 error = iflib_encap(txq, &m);
6811 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6816 iflib_debugnet_poll(if_t ifp, int count)
6818 struct epoch_tracker et;
6820 if_softc_ctx_t scctx;
6824 ctx = if_getsoftc(ifp);
6825 scctx = &ctx->ifc_softc_ctx;
6827 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6831 txq = &ctx->ifc_txqs[0];
6832 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6834 NET_EPOCH_ENTER(et);
6835 for (i = 0; i < scctx->isc_nrxqsets; i++)
6836 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6840 #endif /* DEBUGNET */