2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
133 typedef struct iflib_txq *iflib_txq_t;
135 typedef struct iflib_rxq *iflib_rxq_t;
137 typedef struct iflib_fl *iflib_fl_t;
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
144 typedef struct iflib_filter_info {
145 driver_filter_t *ifi_filter;
146 void *ifi_filter_arg;
147 struct grouptask *ifi_task;
149 } *iflib_filter_info_t;
154 * Pointer to hardware driver's softc
161 if_shared_ctx_t ifc_sctx;
162 struct if_softc_ctx ifc_softc_ctx;
164 struct sx ifc_ctx_sx;
165 struct mtx ifc_state_mtx;
167 iflib_txq_t ifc_txqs;
168 iflib_rxq_t ifc_rxqs;
169 uint32_t ifc_if_flags;
171 uint32_t ifc_max_fl_buf_size;
172 uint32_t ifc_rx_mbuf_sz;
175 int ifc_watchdog_events;
176 struct cdev *ifc_led_dev;
177 struct resource *ifc_msix_mem;
179 struct if_irq ifc_legacy_irq;
180 struct grouptask ifc_admin_task;
181 struct grouptask ifc_vflr_task;
182 struct iflib_filter_info ifc_filter_info;
183 struct ifmedia ifc_media;
184 struct ifmedia *ifc_mediap;
186 struct sysctl_oid *ifc_sysctl_node;
187 uint16_t ifc_sysctl_ntxqs;
188 uint16_t ifc_sysctl_nrxqs;
189 uint16_t ifc_sysctl_qs_eq_override;
190 uint16_t ifc_sysctl_rx_budget;
191 uint16_t ifc_sysctl_tx_abdicate;
192 uint16_t ifc_sysctl_core_offset;
193 #define CORE_OFFSET_UNSPECIFIED 0xffff
194 uint8_t ifc_sysctl_separate_txrx;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 struct ether_addr ifc_mac;
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (ctx->ifc_mediap);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 #define IFLIB_RX_COPY_THRESH 128
292 #define IFLIB_MAX_RX_REFRESH 32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC 16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
296 #define IFLIB_QUEUE_IDLE 0
297 #define IFLIB_QUEUE_HUNG 1
298 #define IFLIB_QUEUE_WORKING 2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR 4
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE 32
305 #define IFLIB_RESTART_BUDGET 8
307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
314 qidx_t ift_cidx_processed;
317 uint8_t ift_br_offset;
318 uint16_t ift_npending;
319 uint16_t ift_db_pending;
320 uint16_t ift_rs_pending;
322 uint8_t ift_txd_size[8];
323 uint64_t ift_processed;
324 uint64_t ift_cleaned;
325 uint64_t ift_cleaned_prev;
327 uint64_t ift_enqueued;
328 uint64_t ift_dequeued;
330 uint64_t ift_no_tx_dma_setup;
331 uint64_t ift_no_desc_avail;
332 uint64_t ift_mbuf_defrag_failed;
333 uint64_t ift_mbuf_defrag;
334 uint64_t ift_map_failed;
335 uint64_t ift_txd_encap_efbig;
336 uint64_t ift_pullups;
337 uint64_t ift_last_timer_tick;
340 struct mtx ift_db_mtx;
342 /* constant values */
344 struct ifmp_ring *ift_br;
345 struct grouptask ift_task;
348 struct callout ift_timer;
350 if_txsd_vec_t ift_sds;
353 uint8_t ift_update_freq;
354 struct iflib_filter_info ift_filter_info;
355 bus_dma_tag_t ift_buf_tag;
356 bus_dma_tag_t ift_tso_buf_tag;
357 iflib_dma_info_t ift_ifdi;
358 #define MTX_NAME_LEN 16
359 char ift_mtx_name[MTX_NAME_LEN];
360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 uint64_t ift_cpu_exec_count[256];
364 } __aligned(CACHE_LINE_SIZE);
371 uint8_t ifl_rxd_size;
373 uint64_t ifl_m_enqueued;
374 uint64_t ifl_m_dequeued;
375 uint64_t ifl_cl_enqueued;
376 uint64_t ifl_cl_dequeued;
379 bitstr_t *ifl_rx_bitmap;
383 uint16_t ifl_buf_size;
386 iflib_rxsd_array_t ifl_sds;
389 bus_dma_tag_t ifl_buf_tag;
390 iflib_dma_info_t ifl_ifdi;
391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the command queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct iflib_filter_info ifr_filter_info;
438 iflib_dma_info_t ifr_ifdi;
440 /* dynamically allocate if any drivers need a value substantially larger than this */
441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
442 #ifdef IFLIB_DIAGNOSTICS
443 uint64_t ifr_cpu_exec_count[256];
445 } __aligned(CACHE_LINE_SIZE);
447 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static void iflib_init_locked(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
710 static void iflib_ifmp_purge(iflib_txq_t txq);
711 static void _iflib_pre_assert(if_softc_ctx_t scctx);
712 static void iflib_if_init_locked(if_ctx_t ctx);
713 static void iflib_free_intr_mem(if_ctx_t ctx);
714 #ifndef __NO_STRICT_ALIGNMENT
715 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
719 SLIST_HEAD_INITIALIZER(cpu_offsets);
721 SLIST_ENTRY(cpu_offset) entries;
723 unsigned int refcount;
726 static struct mtx cpu_offset_mtx;
727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
730 DEBUGNET_DEFINE(iflib);
733 #include <sys/selinfo.h>
734 #include <net/netmap.h>
735 #include <dev/netmap/netmap_kern.h>
737 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
742 * device-specific sysctl variables:
744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
745 * During regular operations the CRC is stripped, but on some
746 * hardware reception of frames not multiple of 64 is slower,
747 * so using crcstrip=0 helps in benchmarks.
749 * iflib_rx_miss, iflib_rx_miss_bufs:
750 * count packets that might be missed due to lost interrupts.
752 SYSCTL_DECL(_dev_netmap);
754 * The xl driver by default strips CRCs and we do not override it.
757 int iflib_crcstrip = 1;
758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
761 int iflib_rx_miss, iflib_rx_miss_bufs;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
768 * Register/unregister. We are already under netmap lock.
769 * Only called on the first register or the last unregister.
772 iflib_netmap_register(struct netmap_adapter *na, int onoff)
775 if_ctx_t ctx = ifp->if_softc;
779 IFDI_INTR_DISABLE(ctx);
781 /* Tell the stack that the interface is no longer active */
782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
787 /* enable or disable flags and callbacks in na and ifp */
789 nm_set_native_flags(na);
791 nm_clear_native_flags(na);
794 iflib_init_locked(ctx);
795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
798 nm_clear_native_flags(na);
804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
806 struct netmap_adapter *na = kring->na;
807 u_int const lim = kring->nkr_num_slots - 1;
808 u_int head = kring->rhead;
809 struct netmap_ring *ring = kring->ring;
811 struct if_rxd_update iru;
812 if_ctx_t ctx = rxq->ifr_ctx;
813 iflib_fl_t fl = &rxq->ifr_fl[0];
814 uint32_t refill_pidx, nic_i;
815 #if IFLIB_DEBUG_COUNTERS
819 if (nm_i == head && __predict_true(!init))
821 iru_init(&iru, rxq, 0 /* flid */);
822 map = fl->ifl_sds.ifsd_map;
823 refill_pidx = netmap_idx_k2n(kring, nm_i);
825 * IMPORTANT: we must leave one free slot in the ring,
826 * so move head back by one unit
828 head = nm_prev(head, lim);
830 DBG_COUNTER_INC(fl_refills);
831 while (nm_i != head) {
832 #if IFLIB_DEBUG_COUNTERS
834 DBG_COUNTER_INC(fl_refills_large);
836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
837 struct netmap_slot *slot = &ring->slot[nm_i];
838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
839 uint32_t nic_i_dma = refill_pidx;
840 nic_i = netmap_idx_k2n(kring, nm_i);
842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
845 return netmap_ring_reinit(kring);
847 fl->ifl_vm_addrs[tmp_pidx] = addr;
848 if (__predict_false(init)) {
849 netmap_load_map(na, fl->ifl_buf_tag,
851 } else if (slot->flags & NS_BUF_CHANGED) {
852 /* buffer has changed, reload map */
853 netmap_reload_map(na, fl->ifl_buf_tag,
856 slot->flags &= ~NS_BUF_CHANGED;
858 nm_i = nm_next(nm_i, lim);
859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
863 iru.iru_pidx = refill_pidx;
864 iru.iru_count = tmp_pidx+1;
865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
867 for (int n = 0; n < iru.iru_count; n++) {
868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
869 BUS_DMASYNC_PREREAD);
870 /* XXX - change this to not use the netmap func*/
871 nic_i_dma = nm_next(nic_i_dma, lim);
875 kring->nr_hwcur = head;
877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
879 if (__predict_true(nic_i != UINT_MAX)) {
880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
881 DBG_COUNTER_INC(rxd_flush);
887 * Reconcile kernel and user view of the transmit ring.
889 * All information is in the kring.
890 * Userspace wants to send packets up to the one before kring->rhead,
891 * kernel knows kring->nr_hwcur is the first unsent packet.
893 * Here we push packets out (as many as possible), and possibly
894 * reclaim buffers from previously completed transmission.
896 * The caller (netmap) guarantees that there is only one instance
897 * running at any time. Any interference with other driver
898 * methods should be handled by the individual drivers.
901 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
903 struct netmap_adapter *na = kring->na;
905 struct netmap_ring *ring = kring->ring;
906 u_int nm_i; /* index into the netmap kring */
907 u_int nic_i; /* index into the NIC ring */
909 u_int const lim = kring->nkr_num_slots - 1;
910 u_int const head = kring->rhead;
911 struct if_pkt_info pi;
914 * interrupts on every tx packet are expensive so request
915 * them every half ring, or where NS_REPORT is set
917 u_int report_frequency = kring->nkr_num_slots >> 1;
918 /* device-specific */
919 if_ctx_t ctx = ifp->if_softc;
920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
926 * First part: process new packets to send.
927 * nm_i is the current index in the netmap kring,
928 * nic_i is the corresponding index in the NIC ring.
930 * If we have packets to send (nm_i != head)
931 * iterate over the netmap ring, fetch length and update
932 * the corresponding slot in the NIC ring. Some drivers also
933 * need to update the buffer's physical address in the NIC slot
934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
936 * The netmap_reload_map() calls is especially expensive,
937 * even when (as in this case) the tag is 0, so do only
938 * when the buffer has actually changed.
940 * If possible do not set the report/intr bit on all slots,
941 * but only a few times per ring or when NS_REPORT is set.
943 * Finally, on 10G and faster drivers, it might be useful
944 * to prefetch the next slot and txr entry.
947 nm_i = kring->nr_hwcur;
948 if (nm_i != head) { /* we have new packets to send */
950 pi.ipi_segs = txq->ift_segs;
951 pi.ipi_qsidx = kring->ring_id;
952 nic_i = netmap_idx_k2n(kring, nm_i);
954 __builtin_prefetch(&ring->slot[nm_i]);
955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
958 for (n = 0; nm_i != head; n++) {
959 struct netmap_slot *slot = &ring->slot[nm_i];
960 u_int len = slot->len;
962 void *addr = PNMB(na, slot, &paddr);
963 int flags = (slot->flags & NS_REPORT ||
964 nic_i == 0 || nic_i == report_frequency) ?
967 /* device-specific */
969 pi.ipi_segs[0].ds_addr = paddr;
970 pi.ipi_segs[0].ds_len = len;
974 pi.ipi_flags = flags;
976 /* Fill the slot in the NIC ring. */
977 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
978 DBG_COUNTER_INC(tx_encap);
980 /* prefetch for next round */
981 __builtin_prefetch(&ring->slot[nm_i + 1]);
982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
985 NM_CHECK_ADDR_LEN(na, addr, len);
987 if (slot->flags & NS_BUF_CHANGED) {
988 /* buffer has changed, reload map */
989 netmap_reload_map(na, txq->ift_buf_tag,
990 txq->ift_sds.ifsd_map[nic_i], addr);
992 /* make sure changes to the buffer are synced */
993 bus_dmamap_sync(txq->ift_buf_tag,
994 txq->ift_sds.ifsd_map[nic_i],
995 BUS_DMASYNC_PREWRITE);
997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
998 nm_i = nm_next(nm_i, lim);
999 nic_i = nm_next(nic_i, lim);
1001 kring->nr_hwcur = nm_i;
1003 /* synchronize the NIC ring */
1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1007 /* (re)start the tx unit up to slot nic_i (excluded) */
1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1012 * Second part: reclaim buffers for completed transmissions.
1014 * If there are unclaimed buffers, attempt to reclaim them.
1015 * If none are reclaimed, and TX IRQs are not in use, do an initial
1016 * minimal delay, then trigger the tx handler which will spin in the
1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1020 if (iflib_tx_credits_update(ctx, txq)) {
1021 /* some tx completed, increment avail */
1022 nic_i = txq->ift_cidx_processed;
1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1029 iflib_timer, txq, txq->ift_timer.c_cpu);
1035 * Reconcile kernel and user view of the receive ring.
1036 * Same as for the txsync, this routine must be efficient.
1037 * The caller guarantees a single invocations, but races against
1038 * the rest of the driver should be handled here.
1040 * On call, kring->rhead is the first packet that userspace wants
1041 * to keep, and kring->rcur is the wakeup point.
1042 * The kernel has previously reported packets up to kring->rtail.
1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1045 * of whether or not we received an interrupt.
1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1050 struct netmap_adapter *na = kring->na;
1051 struct netmap_ring *ring = kring->ring;
1054 uint32_t nm_i; /* index into the netmap ring */
1055 uint32_t nic_i; /* index into the NIC ring */
1057 u_int const lim = kring->nkr_num_slots - 1;
1058 u_int const head = kring->rhead;
1059 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1060 struct if_rxd_info ri;
1062 if_ctx_t ctx = ifp->if_softc;
1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1065 return netmap_ring_reinit(kring);
1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1077 * First part: import newly received packets.
1079 * nm_i is the index of the next free slot in the netmap ring,
1080 * nic_i is the index of the next received packet in the NIC ring,
1081 * and they may differ in case if_init() has been called while
1082 * in netmap mode. For the receive ring we have
1084 * nic_i = rxr->next_check;
1085 * nm_i = kring->nr_hwtail (previous)
1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1089 * rxr->next_check is set to 0 on a ring reinit
1091 if (netmap_no_pendintr || force_update) {
1092 int crclen = iflib_crcstrip ? 0 : 4;
1095 for (i = 0; i < rxq->ifr_nfl; i++) {
1096 fl = &rxq->ifr_fl[i];
1097 nic_i = fl->ifl_cidx;
1098 nm_i = netmap_idx_n2k(kring, nic_i);
1099 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1100 rxq->ifr_id, nic_i, USHRT_MAX);
1101 for (n = 0; avail > 0; n++, avail--) {
1103 ri.iri_frags = rxq->ifr_frags;
1104 ri.iri_qsidx = kring->ring_id;
1105 ri.iri_ifp = ctx->ifc_ifp;
1106 ri.iri_cidx = nic_i;
1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1110 ring->slot[nm_i].flags = 0;
1111 bus_dmamap_sync(fl->ifl_buf_tag,
1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1113 nm_i = nm_next(nm_i, lim);
1114 nic_i = nm_next(nic_i, lim);
1116 if (n) { /* update the state variables */
1117 if (netmap_no_pendintr && !force_update) {
1120 iflib_rx_miss_bufs += n;
1122 fl->ifl_cidx = nic_i;
1123 kring->nr_hwtail = nm_i;
1125 kring->nr_kflags &= ~NKR_PENDINTR;
1129 * Second part: skip past packets that userspace has released.
1130 * (kring->nr_hwcur to head excluded),
1131 * and make the buffers available for reception.
1132 * As usual nm_i is the index in the netmap ring,
1133 * nic_i is the index in the NIC ring, and
1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1136 /* XXX not sure how this will work with multiple free lists */
1137 nm_i = kring->nr_hwcur;
1139 return (netmap_fl_refill(rxq, kring, nm_i, false));
1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1145 if_ctx_t ctx = na->ifp->if_softc;
1149 IFDI_INTR_ENABLE(ctx);
1151 IFDI_INTR_DISABLE(ctx);
1158 iflib_netmap_attach(if_ctx_t ctx)
1160 struct netmap_adapter na;
1161 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1163 bzero(&na, sizeof(na));
1165 na.ifp = ctx->ifc_ifp;
1166 na.na_flags = NAF_BDG_MAYSLEEP;
1167 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1168 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1170 na.num_tx_desc = scctx->isc_ntxd[0];
1171 na.num_rx_desc = scctx->isc_nrxd[0];
1172 na.nm_txsync = iflib_netmap_txsync;
1173 na.nm_rxsync = iflib_netmap_rxsync;
1174 na.nm_register = iflib_netmap_register;
1175 na.nm_intr = iflib_netmap_intr;
1176 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1177 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1178 return (netmap_attach(&na));
1182 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1184 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1185 struct netmap_slot *slot;
1187 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1190 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1193 * In netmap mode, set the map for the packet buffer.
1194 * NOTE: Some drivers (not this one) also need to set
1195 * the physical buffer address in the NIC ring.
1196 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1197 * netmap slot index, si
1199 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1200 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1201 NMB(na, slot + si));
1206 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1208 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1209 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1210 struct netmap_slot *slot;
1213 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1216 nm_i = netmap_idx_n2k(kring, 0);
1217 netmap_fl_refill(rxq, kring, nm_i, true);
1221 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1223 struct netmap_kring *kring;
1226 txqid = txq->ift_id;
1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1230 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1231 BUS_DMASYNC_POSTREAD);
1232 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1233 netmap_tx_irq(ctx->ifc_ifp, txqid);
1234 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1238 *reset_on = hz / 1000;
1243 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1246 #define iflib_netmap_txq_init(ctx, txq)
1247 #define iflib_netmap_rxq_init(ctx, rxq)
1248 #define iflib_netmap_detach(ifp)
1250 #define iflib_netmap_attach(ctx) (0)
1251 #define netmap_rx_irq(ifp, qid, budget) (0)
1252 #define netmap_tx_irq(ifp, qid) do {} while (0)
1253 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1256 #if defined(__i386__) || defined(__amd64__)
1257 static __inline void
1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1262 static __inline void
1263 prefetch2cachelines(void *x)
1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1266 #if (CACHE_LINE_SIZE < 128)
1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1272 #define prefetch2cachelines(x)
1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1280 fl = &rxq->ifr_fl[flid];
1281 iru->iru_paddrs = fl->ifl_bus_addrs;
1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1283 iru->iru_idxs = fl->ifl_rxd_idxs;
1284 iru->iru_qsidx = rxq->ifr_id;
1285 iru->iru_buf_size = fl->ifl_buf_size;
1286 iru->iru_flidx = fl->ifl_id;
1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1294 *(bus_addr_t *) arg = segs[0].ds_addr;
1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1301 device_t dev = ctx->ifc_dev;
1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1304 align, 0, /* alignment, bounds */
1305 BUS_SPACE_MAXADDR, /* lowaddr */
1306 BUS_SPACE_MAXADDR, /* highaddr */
1307 NULL, NULL, /* filter, filterarg */
1310 size, /* maxsegsize */
1311 BUS_DMA_ALLOCNOW, /* flags */
1312 NULL, /* lockfunc */
1317 "%s: bus_dma_tag_create failed: %d\n",
1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1327 __func__, (uintmax_t)size, err);
1331 dma->idi_paddr = IF_BAD_DMA;
1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1334 if (err || dma->idi_paddr == IF_BAD_DMA) {
1336 "%s: bus_dmamap_load failed: %d\n",
1341 dma->idi_size = size;
1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1347 bus_dma_tag_destroy(dma->idi_tag);
1349 dma->idi_tag = NULL;
1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1357 if_shared_ctx_t sctx = ctx->ifc_sctx;
1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1368 iflib_dma_info_t *dmaiter;
1371 for (i = 0; i < count; i++, dmaiter++) {
1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1376 iflib_dma_free_multi(dmalist, i);
1381 iflib_dma_free(iflib_dma_info_t dma)
1383 if (dma->idi_tag == NULL)
1385 if (dma->idi_paddr != IF_BAD_DMA) {
1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1389 dma->idi_paddr = IF_BAD_DMA;
1391 if (dma->idi_vaddr != NULL) {
1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1393 dma->idi_vaddr = NULL;
1395 bus_dma_tag_destroy(dma->idi_tag);
1396 dma->idi_tag = NULL;
1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1403 iflib_dma_info_t *dmaiter = dmalist;
1405 for (i = 0; i < count; i++, dmaiter++)
1406 iflib_dma_free(*dmaiter);
1409 #ifdef EARLY_AP_STARTUP
1410 static const int iflib_started = 1;
1413 * We used to abuse the smp_started flag to decide if the queues have been
1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1416 * is set. Run a SYSINIT() strictly after that to just set a usable
1420 static int iflib_started;
1423 iflib_record_started(void *arg)
1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1429 iflib_record_started, NULL);
1433 iflib_fast_intr(void *arg)
1435 iflib_filter_info_t info = arg;
1436 struct grouptask *gtask = info->ifi_task;
1440 return (FILTER_STRAY);
1442 DBG_COUNTER_INC(fast_intrs);
1443 if (info->ifi_filter != NULL) {
1444 result = info->ifi_filter(info->ifi_filter_arg);
1445 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1449 GROUPTASK_ENQUEUE(gtask);
1450 return (FILTER_HANDLED);
1454 iflib_fast_intr_rxtx(void *arg)
1456 iflib_filter_info_t info = arg;
1457 struct grouptask *gtask = info->ifi_task;
1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1462 int i, cidx, result;
1464 bool intr_enable, intr_legacy;
1467 return (FILTER_STRAY);
1469 DBG_COUNTER_INC(fast_intrs);
1470 if (info->ifi_filter != NULL) {
1471 result = info->ifi_filter(info->ifi_filter_arg);
1472 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1477 sc = ctx->ifc_softc;
1478 intr_enable = false;
1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1480 MPASS(rxq->ifr_ntxqirq);
1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1482 txqid = rxq->ifr_txqid[i];
1483 txq = &ctx->ifc_txqs[txqid];
1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1485 BUS_DMASYNC_POSTREAD);
1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1493 GROUPTASK_ENQUEUE(&txq->ift_task);
1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1496 cidx = rxq->ifr_cq_cidx;
1498 cidx = rxq->ifr_fl[0].ifl_cidx;
1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1500 GROUPTASK_ENQUEUE(gtask);
1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1506 DBG_COUNTER_INC(rx_intr_enables);
1509 IFDI_INTR_ENABLE(ctx);
1510 return (FILTER_HANDLED);
1515 iflib_fast_intr_ctx(void *arg)
1517 iflib_filter_info_t info = arg;
1518 struct grouptask *gtask = info->ifi_task;
1522 return (FILTER_STRAY);
1524 DBG_COUNTER_INC(fast_intrs);
1525 if (info->ifi_filter != NULL) {
1526 result = info->ifi_filter(info->ifi_filter_arg);
1527 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1531 GROUPTASK_ENQUEUE(gtask);
1532 return (FILTER_HANDLED);
1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1537 driver_filter_t filter, driver_intr_t handler, void *arg,
1540 struct resource *res;
1542 device_t dev = ctx->ifc_dev;
1546 if (ctx->ifc_flags & IFC_LEGACY)
1547 flags |= RF_SHAREABLE;
1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1559 filter, handler, arg, &tag);
1562 "failed to setup interrupt for rid %d, name %s: %d\n",
1563 rid, name ? name : "unknown", rc);
1566 bus_describe_intr(dev, res, tag, "%s", name);
1572 /*********************************************************************
1574 * Allocate DMA resources for TX buffers as well as memory for the TX
1575 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1576 * iflib_sw_tx_desc_array structure, storing all the information that
1577 * is needed to transmit a packet on the wire. This is called only
1578 * once at attach, setup is done every reset.
1580 **********************************************************************/
1582 iflib_txsd_alloc(iflib_txq_t txq)
1584 if_ctx_t ctx = txq->ift_ctx;
1585 if_shared_ctx_t sctx = ctx->ifc_sctx;
1586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1587 device_t dev = ctx->ifc_dev;
1588 bus_size_t tsomaxsize;
1589 int err, nsegments, ntsosegments;
1592 nsegments = scctx->isc_tx_nsegments;
1593 ntsosegments = scctx->isc_tx_tso_segments_max;
1594 tsomaxsize = scctx->isc_tx_tso_size_max;
1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1596 tsomaxsize += sizeof(struct ether_vlan_header);
1597 MPASS(scctx->isc_ntxd[0] > 0);
1598 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1599 MPASS(nsegments > 0);
1600 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1601 MPASS(ntsosegments > 0);
1602 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1606 * Set up DMA tags for TX buffers.
1608 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1609 1, 0, /* alignment, bounds */
1610 BUS_SPACE_MAXADDR, /* lowaddr */
1611 BUS_SPACE_MAXADDR, /* highaddr */
1612 NULL, NULL, /* filter, filterarg */
1613 sctx->isc_tx_maxsize, /* maxsize */
1614 nsegments, /* nsegments */
1615 sctx->isc_tx_maxsegsize, /* maxsegsize */
1617 NULL, /* lockfunc */
1618 NULL, /* lockfuncarg */
1619 &txq->ift_buf_tag))) {
1620 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1621 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1622 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1625 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1626 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1627 1, 0, /* alignment, bounds */
1628 BUS_SPACE_MAXADDR, /* lowaddr */
1629 BUS_SPACE_MAXADDR, /* highaddr */
1630 NULL, NULL, /* filter, filterarg */
1631 tsomaxsize, /* maxsize */
1632 ntsosegments, /* nsegments */
1633 sctx->isc_tso_maxsegsize,/* maxsegsize */
1635 NULL, /* lockfunc */
1636 NULL, /* lockfuncarg */
1637 &txq->ift_tso_buf_tag))) {
1638 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1643 /* Allocate memory for the TX mbuf map. */
1644 if (!(txq->ift_sds.ifsd_m =
1645 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1646 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1647 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1653 * Create the DMA maps for TX buffers.
1655 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1656 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1657 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1659 "Unable to allocate TX buffer DMA map memory\n");
1663 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1664 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1665 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1667 "Unable to allocate TSO TX buffer map memory\n");
1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1672 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1673 &txq->ift_sds.ifsd_map[i]);
1675 device_printf(dev, "Unable to create TX DMA map\n");
1680 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1681 &txq->ift_sds.ifsd_tso_map[i]);
1683 device_printf(dev, "Unable to create TSO TX DMA map\n");
1689 /* We free all, it handles case where we are in the middle */
1690 iflib_tx_structures_free(ctx);
1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1699 if (txq->ift_sds.ifsd_map != NULL) {
1700 map = txq->ift_sds.ifsd_map[i];
1701 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1702 bus_dmamap_unload(txq->ift_buf_tag, map);
1703 bus_dmamap_destroy(txq->ift_buf_tag, map);
1704 txq->ift_sds.ifsd_map[i] = NULL;
1707 if (txq->ift_sds.ifsd_tso_map != NULL) {
1708 map = txq->ift_sds.ifsd_tso_map[i];
1709 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1710 BUS_DMASYNC_POSTWRITE);
1711 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1712 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1713 txq->ift_sds.ifsd_tso_map[i] = NULL;
1718 iflib_txq_destroy(iflib_txq_t txq)
1720 if_ctx_t ctx = txq->ift_ctx;
1722 for (int i = 0; i < txq->ift_size; i++)
1723 iflib_txsd_destroy(ctx, txq, i);
1725 if (txq->ift_br != NULL) {
1726 ifmp_ring_free(txq->ift_br);
1730 mtx_destroy(&txq->ift_mtx);
1732 if (txq->ift_sds.ifsd_map != NULL) {
1733 free(txq->ift_sds.ifsd_map, M_IFLIB);
1734 txq->ift_sds.ifsd_map = NULL;
1736 if (txq->ift_sds.ifsd_tso_map != NULL) {
1737 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1738 txq->ift_sds.ifsd_tso_map = NULL;
1740 if (txq->ift_sds.ifsd_m != NULL) {
1741 free(txq->ift_sds.ifsd_m, M_IFLIB);
1742 txq->ift_sds.ifsd_m = NULL;
1744 if (txq->ift_buf_tag != NULL) {
1745 bus_dma_tag_destroy(txq->ift_buf_tag);
1746 txq->ift_buf_tag = NULL;
1748 if (txq->ift_tso_buf_tag != NULL) {
1749 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1750 txq->ift_tso_buf_tag = NULL;
1752 if (txq->ift_ifdi != NULL) {
1753 free(txq->ift_ifdi, M_IFLIB);
1758 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1762 mp = &txq->ift_sds.ifsd_m[i];
1766 if (txq->ift_sds.ifsd_map != NULL) {
1767 bus_dmamap_sync(txq->ift_buf_tag,
1768 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1769 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1771 if (txq->ift_sds.ifsd_tso_map != NULL) {
1772 bus_dmamap_sync(txq->ift_tso_buf_tag,
1773 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1774 bus_dmamap_unload(txq->ift_tso_buf_tag,
1775 txq->ift_sds.ifsd_tso_map[i]);
1778 DBG_COUNTER_INC(tx_frees);
1783 iflib_txq_setup(iflib_txq_t txq)
1785 if_ctx_t ctx = txq->ift_ctx;
1786 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1787 if_shared_ctx_t sctx = ctx->ifc_sctx;
1788 iflib_dma_info_t di;
1791 /* Set number of descriptors available */
1792 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1793 /* XXX make configurable */
1794 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1797 txq->ift_cidx_processed = 0;
1798 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1799 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1801 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1802 bzero((void *)di->idi_vaddr, di->idi_size);
1804 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1805 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1806 bus_dmamap_sync(di->idi_tag, di->idi_map,
1807 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1811 /*********************************************************************
1813 * Allocate DMA resources for RX buffers as well as memory for the RX
1814 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1815 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1816 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1817 * Since we use use one entry in iflib_sw_rx_desc_array per received
1818 * packet, the maximum number of entries we'll need is equal to the
1819 * number of hardware receive descriptors that we've allocated.
1821 **********************************************************************/
1823 iflib_rxsd_alloc(iflib_rxq_t rxq)
1825 if_ctx_t ctx = rxq->ifr_ctx;
1826 if_shared_ctx_t sctx = ctx->ifc_sctx;
1827 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1828 device_t dev = ctx->ifc_dev;
1832 MPASS(scctx->isc_nrxd[0] > 0);
1833 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1836 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1837 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1838 /* Set up DMA tag for RX buffers. */
1839 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1840 1, 0, /* alignment, bounds */
1841 BUS_SPACE_MAXADDR, /* lowaddr */
1842 BUS_SPACE_MAXADDR, /* highaddr */
1843 NULL, NULL, /* filter, filterarg */
1844 sctx->isc_rx_maxsize, /* maxsize */
1845 sctx->isc_rx_nsegments, /* nsegments */
1846 sctx->isc_rx_maxsegsize, /* maxsegsize */
1848 NULL, /* lockfunc */
1853 "Unable to allocate RX DMA tag: %d\n", err);
1857 /* Allocate memory for the RX mbuf map. */
1858 if (!(fl->ifl_sds.ifsd_m =
1859 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1860 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1862 "Unable to allocate RX mbuf map memory\n");
1867 /* Allocate memory for the direct RX cluster pointer map. */
1868 if (!(fl->ifl_sds.ifsd_cl =
1869 (caddr_t *) malloc(sizeof(caddr_t) *
1870 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1872 "Unable to allocate RX cluster map memory\n");
1877 /* Allocate memory for the RX cluster bus address map. */
1878 if (!(fl->ifl_sds.ifsd_ba =
1879 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1880 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1882 "Unable to allocate RX bus address map memory\n");
1888 * Create the DMA maps for RX buffers.
1890 if (!(fl->ifl_sds.ifsd_map =
1891 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1893 "Unable to allocate RX buffer DMA map memory\n");
1897 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1898 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1899 &fl->ifl_sds.ifsd_map[i]);
1901 device_printf(dev, "Unable to create RX buffer DMA map\n");
1909 iflib_rx_structures_free(ctx);
1915 * Internal service routines
1918 struct rxq_refill_cb_arg {
1920 bus_dma_segment_t seg;
1925 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1927 struct rxq_refill_cb_arg *cb_arg = arg;
1929 cb_arg->error = error;
1930 cb_arg->seg = segs[0];
1931 cb_arg->nseg = nseg;
1935 * _iflib_fl_refill - refill an rxq free-buffer list
1936 * @ctx: the iflib context
1937 * @fl: the free list to refill
1938 * @count: the number of new buffers to allocate
1940 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1941 * The caller must assure that @count does not exceed the queue's capacity.
1944 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1946 struct if_rxd_update iru;
1947 struct rxq_refill_cb_arg cb_arg;
1951 bus_dmamap_t *sd_map;
1952 bus_addr_t bus_addr, *sd_ba;
1953 int err, frag_idx, i, idx, n, pidx;
1956 sd_m = fl->ifl_sds.ifsd_m;
1957 sd_map = fl->ifl_sds.ifsd_map;
1958 sd_cl = fl->ifl_sds.ifsd_cl;
1959 sd_ba = fl->ifl_sds.ifsd_ba;
1960 pidx = fl->ifl_pidx;
1962 frag_idx = fl->ifl_fragidx;
1963 credits = fl->ifl_credits;
1968 MPASS(credits + n <= fl->ifl_size);
1970 if (pidx < fl->ifl_cidx)
1971 MPASS(pidx + n <= fl->ifl_cidx);
1972 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1973 MPASS(fl->ifl_gen == 0);
1974 if (pidx > fl->ifl_cidx)
1975 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1977 DBG_COUNTER_INC(fl_refills);
1979 DBG_COUNTER_INC(fl_refills_large);
1980 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1983 * We allocate an uninitialized mbuf + cluster, mbuf is
1984 * initialized after rx.
1986 * If the cluster is still set then we know a minimum sized packet was received
1988 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1991 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1992 MPASS(frag_idx >= 0);
1993 if ((cl = sd_cl[frag_idx]) == NULL) {
1994 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1998 MPASS(sd_map != NULL);
1999 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2000 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2002 if (err != 0 || cb_arg.error) {
2006 if (fl->ifl_zone == zone_pack)
2007 uma_zfree(fl->ifl_zone, cl);
2011 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2012 sd_cl[frag_idx] = cl;
2014 fl->ifl_cl_enqueued++;
2017 bus_addr = sd_ba[frag_idx];
2019 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2020 BUS_DMASYNC_PREREAD);
2022 if (sd_m[frag_idx] == NULL) {
2023 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2028 bit_set(fl->ifl_rx_bitmap, frag_idx);
2030 fl->ifl_m_enqueued++;
2033 DBG_COUNTER_INC(rx_allocs);
2034 fl->ifl_rxd_idxs[i] = frag_idx;
2035 fl->ifl_bus_addrs[i] = bus_addr;
2036 fl->ifl_vm_addrs[i] = cl;
2039 MPASS(credits <= fl->ifl_size);
2040 if (++idx == fl->ifl_size) {
2044 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2045 iru.iru_pidx = pidx;
2047 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2051 fl->ifl_credits = credits;
2056 iru.iru_pidx = pidx;
2058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2060 fl->ifl_credits = credits;
2062 DBG_COUNTER_INC(rxd_flush);
2063 if (fl->ifl_pidx == 0)
2064 pidx = fl->ifl_size - 1;
2066 pidx = fl->ifl_pidx - 1;
2068 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2069 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2070 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2071 fl->ifl_fragidx = frag_idx;
2074 static __inline void
2075 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2077 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2078 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2080 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2083 MPASS(fl->ifl_credits <= fl->ifl_size);
2084 MPASS(reclaimable == delta);
2086 if (reclaimable > 0)
2087 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2091 iflib_in_detach(if_ctx_t ctx)
2096 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2102 iflib_fl_bufs_free(iflib_fl_t fl)
2104 iflib_dma_info_t idi = fl->ifl_ifdi;
2105 bus_dmamap_t sd_map;
2108 for (i = 0; i < fl->ifl_size; i++) {
2109 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2110 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2112 if (*sd_cl != NULL) {
2113 sd_map = fl->ifl_sds.ifsd_map[i];
2114 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2115 BUS_DMASYNC_POSTREAD);
2116 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2118 uma_zfree(fl->ifl_zone, *sd_cl);
2119 if (*sd_m != NULL) {
2120 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2121 uma_zfree(zone_mbuf, *sd_m);
2124 MPASS(*sd_cl == NULL);
2125 MPASS(*sd_m == NULL);
2128 fl->ifl_m_dequeued++;
2129 fl->ifl_cl_dequeued++;
2135 for (i = 0; i < fl->ifl_size; i++) {
2136 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2137 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2141 * Reset free list values
2143 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2144 bzero(idi->idi_vaddr, idi->idi_size);
2147 /*********************************************************************
2149 * Initialize a free list and its buffers.
2151 **********************************************************************/
2153 iflib_fl_setup(iflib_fl_t fl)
2155 iflib_rxq_t rxq = fl->ifl_rxq;
2156 if_ctx_t ctx = rxq->ifr_ctx;
2158 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2160 ** Free current RX buffer structs and their mbufs
2162 iflib_fl_bufs_free(fl);
2163 /* Now replenish the mbufs */
2164 MPASS(fl->ifl_credits == 0);
2165 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2166 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2167 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2168 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2169 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2172 /* avoid pre-allocating zillions of clusters to an idle card
2173 * potentially speeding up attach
2175 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2176 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2177 if (min(128, fl->ifl_size) != fl->ifl_credits)
2183 MPASS(fl->ifl_ifdi != NULL);
2184 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2189 /*********************************************************************
2191 * Free receive ring data structures
2193 **********************************************************************/
2195 iflib_rx_sds_free(iflib_rxq_t rxq)
2200 if (rxq->ifr_fl != NULL) {
2201 for (i = 0; i < rxq->ifr_nfl; i++) {
2202 fl = &rxq->ifr_fl[i];
2203 if (fl->ifl_buf_tag != NULL) {
2204 if (fl->ifl_sds.ifsd_map != NULL) {
2205 for (j = 0; j < fl->ifl_size; j++) {
2208 fl->ifl_sds.ifsd_map[j],
2209 BUS_DMASYNC_POSTREAD);
2212 fl->ifl_sds.ifsd_map[j]);
2215 fl->ifl_sds.ifsd_map[j]);
2218 bus_dma_tag_destroy(fl->ifl_buf_tag);
2219 fl->ifl_buf_tag = NULL;
2221 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2222 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2223 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2224 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2225 fl->ifl_sds.ifsd_m = NULL;
2226 fl->ifl_sds.ifsd_cl = NULL;
2227 fl->ifl_sds.ifsd_ba = NULL;
2228 fl->ifl_sds.ifsd_map = NULL;
2230 free(rxq->ifr_fl, M_IFLIB);
2232 free(rxq->ifr_ifdi, M_IFLIB);
2233 rxq->ifr_ifdi = NULL;
2234 rxq->ifr_cq_cidx = 0;
2242 iflib_timer(void *arg)
2244 iflib_txq_t txq = arg;
2245 if_ctx_t ctx = txq->ift_ctx;
2246 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2247 uint64_t this_tick = ticks;
2248 uint32_t reset_on = hz / 2;
2250 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2254 ** Check on the state of the TX queue(s), this
2255 ** can be done without the lock because its RO
2256 ** and the HUNG state will be static if set.
2258 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2259 txq->ift_last_timer_tick = this_tick;
2260 IFDI_TIMER(ctx, txq->ift_id);
2261 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2262 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2263 (sctx->isc_pause_frames == 0)))
2266 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2267 ifmp_ring_is_stalled(txq->ift_br)) {
2268 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2269 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2271 txq->ift_cleaned_prev = txq->ift_cleaned;
2274 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2275 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2277 /* handle any laggards */
2278 if (txq->ift_db_pending)
2279 GROUPTASK_ENQUEUE(&txq->ift_task);
2281 sctx->isc_pause_frames = 0;
2282 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2283 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2287 device_printf(ctx->ifc_dev,
2288 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2289 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2291 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2292 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2293 iflib_admin_intr_deferred(ctx);
2298 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2300 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2303 * XXX don't set the max_frame_size to larger
2304 * than the hardware can handle
2306 if (sctx->isc_max_frame_size <= MCLBYTES)
2307 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2309 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2313 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2316 return (ctx->ifc_rx_mbuf_sz);
2320 iflib_init_locked(if_ctx_t ctx)
2322 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2323 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2324 if_t ifp = ctx->ifc_ifp;
2328 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2330 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2331 IFDI_INTR_DISABLE(ctx);
2333 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2334 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2335 /* Set hardware offload abilities */
2336 if_clearhwassist(ifp);
2337 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2338 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2339 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2340 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2341 if (if_getcapenable(ifp) & IFCAP_TSO4)
2342 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2343 if (if_getcapenable(ifp) & IFCAP_TSO6)
2344 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2346 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2348 callout_stop(&txq->ift_timer);
2349 CALLOUT_UNLOCK(txq);
2350 iflib_netmap_txq_init(ctx, txq);
2354 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2355 * that drivers can use the value when setting up the hardware receive
2358 iflib_calc_rx_mbuf_sz(ctx);
2361 i = if_getdrvflags(ifp);
2364 MPASS(if_getdrvflags(ifp) == i);
2365 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2366 /* XXX this should really be done on a per-queue basis */
2367 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2368 MPASS(rxq->ifr_id == i);
2369 iflib_netmap_rxq_init(ctx, rxq);
2372 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2373 if (iflib_fl_setup(fl)) {
2374 device_printf(ctx->ifc_dev,
2375 "setting up free list %d failed - "
2376 "check cluster settings\n", j);
2382 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2383 IFDI_INTR_ENABLE(ctx);
2384 txq = ctx->ifc_txqs;
2385 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2386 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2387 txq->ift_timer.c_cpu);
2391 iflib_media_change(if_t ifp)
2393 if_ctx_t ctx = if_getsoftc(ifp);
2397 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2398 iflib_init_locked(ctx);
2404 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2406 if_ctx_t ctx = if_getsoftc(ifp);
2409 IFDI_UPDATE_ADMIN_STATUS(ctx);
2410 IFDI_MEDIA_STATUS(ctx, ifmr);
2415 iflib_stop(if_ctx_t ctx)
2417 iflib_txq_t txq = ctx->ifc_txqs;
2418 iflib_rxq_t rxq = ctx->ifc_rxqs;
2419 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2420 if_shared_ctx_t sctx = ctx->ifc_sctx;
2421 iflib_dma_info_t di;
2425 /* Tell the stack that the interface is no longer active */
2426 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2428 IFDI_INTR_DISABLE(ctx);
2433 iflib_debug_reset();
2434 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2435 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2436 /* make sure all transmitters have completed before proceeding XXX */
2439 callout_stop(&txq->ift_timer);
2440 CALLOUT_UNLOCK(txq);
2442 /* clean any enqueued buffers */
2443 iflib_ifmp_purge(txq);
2444 /* Free any existing tx buffers. */
2445 for (j = 0; j < txq->ift_size; j++) {
2446 iflib_txsd_free(ctx, txq, j);
2448 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2449 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2450 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2451 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2452 txq->ift_pullups = 0;
2453 ifmp_ring_reset_stats(txq->ift_br);
2454 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2455 bzero((void *)di->idi_vaddr, di->idi_size);
2457 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2458 /* make sure all transmitters have completed before proceeding XXX */
2460 rxq->ifr_cq_cidx = 0;
2461 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2462 bzero((void *)di->idi_vaddr, di->idi_size);
2463 /* also resets the free lists pidx/cidx */
2464 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2465 iflib_fl_bufs_free(fl);
2469 static inline caddr_t
2470 calc_next_rxd(iflib_fl_t fl, int cidx)
2474 caddr_t start, end, cur, next;
2476 nrxd = fl->ifl_size;
2477 size = fl->ifl_rxd_size;
2478 start = fl->ifl_ifdi->idi_vaddr;
2480 if (__predict_false(size == 0))
2482 cur = start + size*cidx;
2483 end = start + size*nrxd;
2484 next = CACHE_PTR_NEXT(cur);
2485 return (next < end ? next : start);
2489 prefetch_pkts(iflib_fl_t fl, int cidx)
2492 int nrxd = fl->ifl_size;
2496 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2497 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2498 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2499 next_rxd = calc_next_rxd(fl, cidx);
2501 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2502 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2503 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2504 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2505 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2506 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2507 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2508 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2511 static struct mbuf *
2512 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2513 int *pf_rv, if_rxd_info_t ri)
2519 int flid, cidx, len, next;
2522 flid = irf->irf_flid;
2523 cidx = irf->irf_idx;
2524 fl = &rxq->ifr_fl[flid];
2526 sd->ifsd_cidx = cidx;
2527 m = fl->ifl_sds.ifsd_m[cidx];
2528 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2531 fl->ifl_m_dequeued++;
2533 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2534 prefetch_pkts(fl, cidx);
2535 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2536 prefetch(&fl->ifl_sds.ifsd_map[next]);
2537 map = fl->ifl_sds.ifsd_map[cidx];
2538 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2540 /* not valid assert if bxe really does SGE from non-contiguous elements */
2541 MPASS(fl->ifl_cidx == cidx);
2542 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2544 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2545 payload = *sd->ifsd_cl;
2546 payload += ri->iri_pad;
2547 len = ri->iri_len - ri->iri_pad;
2548 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2549 len | PFIL_MEMPTR | PFIL_IN, NULL);
2554 * The filter ate it. Everything is recycled.
2559 case PFIL_REALLOCED:
2561 * The filter copied it. Everything is recycled.
2563 m = pfil_mem2mbuf(payload);
2568 * Filter said it was OK, so receive like
2571 fl->ifl_sds.ifsd_m[cidx] = NULL;
2577 fl->ifl_sds.ifsd_m[cidx] = NULL;
2582 bus_dmamap_unload(fl->ifl_buf_tag, map);
2583 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2584 if (__predict_false(fl->ifl_cidx == 0))
2586 bit_clear(fl->ifl_rx_bitmap, cidx);
2590 static struct mbuf *
2591 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2593 struct mbuf *m, *mh, *mt;
2595 int *pf_rv_ptr, flags, i, padlen;
2604 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2607 MPASS(*sd->ifsd_cl != NULL);
2610 * Exclude zero-length frags & frags from
2611 * packets the filter has consumed or dropped
2613 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2614 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2616 /* everything saved here */
2621 /* XXX we can save the cluster here, but not the mbuf */
2622 m_init(m, M_NOWAIT, MT_DATA, 0);
2627 flags = M_PKTHDR|M_EXT;
2629 padlen = ri->iri_pad;
2634 /* assuming padding is only on the first fragment */
2638 *sd->ifsd_cl = NULL;
2640 /* Can these two be made one ? */
2641 m_init(m, M_NOWAIT, MT_DATA, flags);
2642 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2644 * These must follow m_init and m_cljset
2646 m->m_data += padlen;
2647 ri->iri_len -= padlen;
2648 m->m_len = ri->iri_frags[i].irf_len;
2649 } while (++i < ri->iri_nfrags);
2655 * Process one software descriptor
2657 static struct mbuf *
2658 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2664 /* should I merge this back in now that the two paths are basically duplicated? */
2665 if (ri->iri_nfrags == 1 &&
2666 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2667 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2669 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2671 if (pf_rv == PFIL_PASS) {
2672 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2673 #ifndef __NO_STRICT_ALIGNMENT
2677 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2678 m->m_len = ri->iri_frags[0].irf_len;
2681 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2682 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2685 m->m_pkthdr.len = ri->iri_len;
2686 m->m_pkthdr.rcvif = ri->iri_ifp;
2687 m->m_flags |= ri->iri_flags;
2688 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2689 m->m_pkthdr.flowid = ri->iri_flowid;
2690 M_HASHTYPE_SET(m, ri->iri_rsstype);
2691 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2692 m->m_pkthdr.csum_data = ri->iri_csum_data;
2696 #if defined(INET6) || defined(INET)
2698 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2700 CURVNET_SET(lc->ifp->if_vnet);
2702 *v6 = V_ip6_forwarding;
2705 *v4 = V_ipforwarding;
2711 * Returns true if it's possible this packet could be LROed.
2712 * if it returns false, it is guaranteed that tcp_lro_rx()
2713 * would not return zero.
2716 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2718 struct ether_header *eh;
2720 eh = mtod(m, struct ether_header *);
2721 switch (eh->ether_type) {
2723 case htons(ETHERTYPE_IPV6):
2724 return (!v6_forwarding);
2727 case htons(ETHERTYPE_IP):
2728 return (!v4_forwarding);
2736 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2742 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2745 if_ctx_t ctx = rxq->ifr_ctx;
2746 if_shared_ctx_t sctx = ctx->ifc_sctx;
2747 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2750 struct if_rxd_info ri;
2751 int err, budget_left, rx_bytes, rx_pkts;
2754 bool v4_forwarding, v6_forwarding, lro_possible;
2757 * XXX early demux data packets so that if_input processing only handles
2758 * acks in interrupt context
2760 struct mbuf *m, *mh, *mt, *mf;
2762 lro_possible = v4_forwarding = v6_forwarding = false;
2766 rx_pkts = rx_bytes = 0;
2767 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2768 cidxp = &rxq->ifr_cq_cidx;
2770 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2771 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2772 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2773 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2774 DBG_COUNTER_INC(rx_unavail);
2778 /* pfil needs the vnet to be set */
2779 CURVNET_SET_QUIET(ifp->if_vnet);
2780 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2781 if (__predict_false(!CTX_ACTIVE(ctx))) {
2782 DBG_COUNTER_INC(rx_ctx_inactive);
2786 * Reset client set fields to their default values
2789 ri.iri_qsidx = rxq->ifr_id;
2790 ri.iri_cidx = *cidxp;
2792 ri.iri_frags = rxq->ifr_frags;
2793 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2798 rx_bytes += ri.iri_len;
2799 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2800 *cidxp = ri.iri_cidx;
2801 /* Update our consumer index */
2802 /* XXX NB: shurd - check if this is still safe */
2803 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2804 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2805 /* was this only a completion queue message? */
2806 if (__predict_false(ri.iri_nfrags == 0))
2809 MPASS(ri.iri_nfrags != 0);
2810 MPASS(ri.iri_len != 0);
2812 /* will advance the cidx on the corresponding free lists */
2813 m = iflib_rxd_pkt_get(rxq, &ri);
2816 if (avail == 0 && budget_left)
2817 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2819 if (__predict_false(m == NULL))
2822 /* imm_pkt: -- cxgb */
2831 /* make sure that we can refill faster than drain */
2832 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2833 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2835 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2837 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2839 while (mh != NULL) {
2842 m->m_nextpkt = NULL;
2843 #ifndef __NO_STRICT_ALIGNMENT
2844 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2847 rx_bytes += m->m_pkthdr.len;
2849 #if defined(INET6) || defined(INET)
2851 if (!lro_possible) {
2852 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2853 if (lro_possible && mf != NULL) {
2854 ifp->if_input(ifp, mf);
2855 DBG_COUNTER_INC(rx_if_input);
2859 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2860 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2861 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2867 ifp->if_input(ifp, m);
2868 DBG_COUNTER_INC(rx_if_input);
2879 ifp->if_input(ifp, mf);
2880 DBG_COUNTER_INC(rx_if_input);
2883 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2884 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2887 * Flush any outstanding LRO work
2889 #if defined(INET6) || defined(INET)
2890 tcp_lro_flush_all(&rxq->ifr_lc);
2894 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2897 ctx->ifc_flags |= IFC_DO_RESET;
2898 iflib_admin_intr_deferred(ctx);
2903 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2904 static inline qidx_t
2905 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2907 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2908 qidx_t minthresh = txq->ift_size / 8;
2909 if (in_use > 4*minthresh)
2910 return (notify_count);
2911 if (in_use > 2*minthresh)
2912 return (notify_count >> 1);
2913 if (in_use > minthresh)
2914 return (notify_count >> 3);
2918 static inline qidx_t
2919 txq_max_rs_deferred(iflib_txq_t txq)
2921 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2922 qidx_t minthresh = txq->ift_size / 8;
2923 if (txq->ift_in_use > 4*minthresh)
2924 return (notify_count);
2925 if (txq->ift_in_use > 2*minthresh)
2926 return (notify_count >> 1);
2927 if (txq->ift_in_use > minthresh)
2928 return (notify_count >> 2);
2932 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2933 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2935 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2936 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2937 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2939 /* forward compatibility for cxgb */
2940 #define FIRST_QSET(ctx) 0
2941 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2942 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2943 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2944 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2946 /* XXX we should be setting this to something other than zero */
2947 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2948 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2949 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2952 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2958 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2959 if (ring || txq->ift_db_pending >= max) {
2960 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2961 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2963 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2964 txq->ift_db_pending = txq->ift_npending = 0;
2972 print_pkt(if_pkt_info_t pi)
2974 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2975 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2976 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2977 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2978 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2979 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2983 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2984 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2985 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2986 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2989 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2991 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2992 struct ether_vlan_header *eh;
2996 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2997 M_WRITABLE(m) == 0) {
2998 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3002 DBG_COUNTER_INC(tx_frees);
3008 * Determine where frame payload starts.
3009 * Jump over vlan headers if already present,
3010 * helpful for QinQ too.
3012 if (__predict_false(m->m_len < sizeof(*eh))) {
3014 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3017 eh = mtod(m, struct ether_vlan_header *);
3018 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3019 pi->ipi_etype = ntohs(eh->evl_proto);
3020 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3022 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3023 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3026 switch (pi->ipi_etype) {
3031 struct ip *ip = NULL;
3032 struct tcphdr *th = NULL;
3035 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3036 if (__predict_false(m->m_len < minthlen)) {
3038 * if this code bloat is causing too much of a hit
3039 * move it to a separate function and mark it noinline
3041 if (m->m_len == pi->ipi_ehdrlen) {
3044 if (n->m_len >= sizeof(*ip)) {
3045 ip = (struct ip *)n->m_data;
3046 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3047 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3050 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3052 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3056 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3058 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3059 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3060 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3063 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3064 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3065 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3067 pi->ipi_ip_hlen = ip->ip_hl << 2;
3068 pi->ipi_ipproto = ip->ip_p;
3069 pi->ipi_flags |= IPI_TX_IPV4;
3071 /* TCP checksum offload may require TCP header length */
3072 if (IS_TX_OFFLOAD4(pi)) {
3073 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3074 if (__predict_false(th == NULL)) {
3076 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3078 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3080 pi->ipi_tcp_hflags = th->th_flags;
3081 pi->ipi_tcp_hlen = th->th_off << 2;
3082 pi->ipi_tcp_seq = th->th_seq;
3085 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3088 * TSO always requires hardware checksum offload.
3090 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3091 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3092 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3093 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3094 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3096 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3100 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3107 case ETHERTYPE_IPV6:
3109 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3111 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3113 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3115 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3118 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3120 /* XXX-BZ this will go badly in case of ext hdrs. */
3121 pi->ipi_ipproto = ip6->ip6_nxt;
3122 pi->ipi_flags |= IPI_TX_IPV6;
3124 /* TCP checksum offload may require TCP header length */
3125 if (IS_TX_OFFLOAD6(pi)) {
3126 if (pi->ipi_ipproto == IPPROTO_TCP) {
3127 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3129 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3132 pi->ipi_tcp_hflags = th->th_flags;
3133 pi->ipi_tcp_hlen = th->th_off << 2;
3134 pi->ipi_tcp_seq = th->th_seq;
3137 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3140 * TSO always requires hardware checksum offload.
3142 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3143 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3144 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3151 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3152 pi->ipi_ip_hlen = 0;
3161 * If dodgy hardware rejects the scatter gather chain we've handed it
3162 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3165 static __noinline struct mbuf *
3166 iflib_remove_mbuf(iflib_txq_t txq)
3169 struct mbuf *m, **ifsd_m;
3171 ifsd_m = txq->ift_sds.ifsd_m;
3172 ntxd = txq->ift_size;
3173 pidx = txq->ift_pidx & (ntxd - 1);
3174 ifsd_m = txq->ift_sds.ifsd_m;
3176 ifsd_m[pidx] = NULL;
3177 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3178 if (txq->ift_sds.ifsd_tso_map != NULL)
3179 bus_dmamap_unload(txq->ift_tso_buf_tag,
3180 txq->ift_sds.ifsd_tso_map[pidx]);
3182 txq->ift_dequeued++;
3187 static inline caddr_t
3188 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3192 caddr_t start, end, cur, next;
3194 ntxd = txq->ift_size;
3195 size = txq->ift_txd_size[qid];
3196 start = txq->ift_ifdi[qid].idi_vaddr;
3198 if (__predict_false(size == 0))
3200 cur = start + size*cidx;
3201 end = start + size*ntxd;
3202 next = CACHE_PTR_NEXT(cur);
3203 return (next < end ? next : start);
3207 * Pad an mbuf to ensure a minimum ethernet frame size.
3208 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3210 static __noinline int
3211 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3214 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3215 * and ARP message is the smallest common payload I can think of
3217 static char pad[18]; /* just zeros */
3219 struct mbuf *new_head;
3221 if (!M_WRITABLE(*m_head)) {
3222 new_head = m_dup(*m_head, M_NOWAIT);
3223 if (new_head == NULL) {
3225 device_printf(dev, "cannot pad short frame, m_dup() failed");
3226 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3227 DBG_COUNTER_INC(tx_frees);
3234 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3235 n > 0; n -= sizeof(pad))
3236 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3241 device_printf(dev, "cannot pad short frame\n");
3242 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3243 DBG_COUNTER_INC(tx_frees);
3251 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3254 if_shared_ctx_t sctx;
3255 if_softc_ctx_t scctx;
3256 bus_dma_tag_t buf_tag;
3257 bus_dma_segment_t *segs;
3258 struct mbuf *m_head, **ifsd_m;
3261 struct if_pkt_info pi;
3263 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3266 sctx = ctx->ifc_sctx;
3267 scctx = &ctx->ifc_softc_ctx;
3268 segs = txq->ift_segs;
3269 ntxd = txq->ift_size;
3274 * If we're doing TSO the next descriptor to clean may be quite far ahead
3276 cidx = txq->ift_cidx;
3277 pidx = txq->ift_pidx;
3278 if (ctx->ifc_flags & IFC_PREFETCH) {
3279 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3280 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3281 next_txd = calc_next_txd(txq, cidx, 0);
3285 /* prefetch the next cache line of mbuf pointers and flags */
3286 prefetch(&txq->ift_sds.ifsd_m[next]);
3287 prefetch(&txq->ift_sds.ifsd_map[next]);
3288 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3290 map = txq->ift_sds.ifsd_map[pidx];
3291 ifsd_m = txq->ift_sds.ifsd_m;
3293 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3294 buf_tag = txq->ift_tso_buf_tag;
3295 max_segs = scctx->isc_tx_tso_segments_max;
3296 map = txq->ift_sds.ifsd_tso_map[pidx];
3297 MPASS(buf_tag != NULL);
3298 MPASS(max_segs > 0);
3300 buf_tag = txq->ift_buf_tag;
3301 max_segs = scctx->isc_tx_nsegments;
3302 map = txq->ift_sds.ifsd_map[pidx];
3304 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3305 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3306 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3308 DBG_COUNTER_INC(encap_txd_encap_fail);
3315 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3317 pi.ipi_qsidx = txq->ift_id;
3318 pi.ipi_len = m_head->m_pkthdr.len;
3319 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3320 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3322 /* deliberate bitwise OR to make one condition */
3323 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3324 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3325 DBG_COUNTER_INC(encap_txd_encap_fail);
3332 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3335 if (__predict_false(err)) {
3338 /* try collapse once and defrag once */
3340 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3341 /* try defrag if collapsing fails */
3346 txq->ift_mbuf_defrag++;
3347 m_head = m_defrag(*m_headp, M_NOWAIT);
3350 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3351 * failed to map an mbuf that was run through m_defrag
3354 if (__predict_false(m_head == NULL || remap > 1))
3361 txq->ift_no_tx_dma_setup++;
3364 txq->ift_no_tx_dma_setup++;
3366 DBG_COUNTER_INC(tx_frees);
3370 txq->ift_map_failed++;
3371 DBG_COUNTER_INC(encap_load_mbuf_fail);
3372 DBG_COUNTER_INC(encap_txd_encap_fail);
3375 ifsd_m[pidx] = m_head;
3377 * XXX assumes a 1 to 1 relationship between segments and
3378 * descriptors - this does not hold true on all drivers, e.g.
3381 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3382 txq->ift_no_desc_avail++;
3383 bus_dmamap_unload(buf_tag, map);
3384 DBG_COUNTER_INC(encap_txq_avail_fail);
3385 DBG_COUNTER_INC(encap_txd_encap_fail);
3386 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3387 GROUPTASK_ENQUEUE(&txq->ift_task);
3391 * On Intel cards we can greatly reduce the number of TX interrupts
3392 * we see by only setting report status on every Nth descriptor.
3393 * However, this also means that the driver will need to keep track
3394 * of the descriptors that RS was set on to check them for the DD bit.
3396 txq->ift_rs_pending += nsegs + 1;
3397 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3398 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3399 pi.ipi_flags |= IPI_TX_INTR;
3400 txq->ift_rs_pending = 0;
3404 pi.ipi_nsegs = nsegs;
3406 MPASS(pidx >= 0 && pidx < txq->ift_size);
3410 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3411 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3412 DBG_COUNTER_INC(tx_encap);
3413 MPASS(pi.ipi_new_pidx < txq->ift_size);
3415 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3416 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3417 ndesc += txq->ift_size;
3421 * drivers can need as many as
3424 MPASS(ndesc <= pi.ipi_nsegs + 2);
3425 MPASS(pi.ipi_new_pidx != pidx);
3427 txq->ift_in_use += ndesc;
3430 * We update the last software descriptor again here because there may
3431 * be a sentinel and/or there may be more mbufs than segments
3433 txq->ift_pidx = pi.ipi_new_pidx;
3434 txq->ift_npending += pi.ipi_ndescs;
3436 *m_headp = m_head = iflib_remove_mbuf(txq);
3438 txq->ift_txd_encap_efbig++;
3447 * err can't possibly be non-zero here, so we don't neet to test it
3448 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3453 txq->ift_mbuf_defrag_failed++;
3454 txq->ift_map_failed++;
3456 DBG_COUNTER_INC(tx_frees);
3458 DBG_COUNTER_INC(encap_txd_encap_fail);
3463 iflib_tx_desc_free(iflib_txq_t txq, int n)
3465 uint32_t qsize, cidx, mask, gen;
3466 struct mbuf *m, **ifsd_m;
3469 cidx = txq->ift_cidx;
3471 qsize = txq->ift_size;
3473 ifsd_m = txq->ift_sds.ifsd_m;
3474 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3478 prefetch(ifsd_m[(cidx + 3) & mask]);
3479 prefetch(ifsd_m[(cidx + 4) & mask]);
3481 if ((m = ifsd_m[cidx]) != NULL) {
3482 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3483 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3484 bus_dmamap_sync(txq->ift_tso_buf_tag,
3485 txq->ift_sds.ifsd_tso_map[cidx],
3486 BUS_DMASYNC_POSTWRITE);
3487 bus_dmamap_unload(txq->ift_tso_buf_tag,
3488 txq->ift_sds.ifsd_tso_map[cidx]);
3490 bus_dmamap_sync(txq->ift_buf_tag,
3491 txq->ift_sds.ifsd_map[cidx],
3492 BUS_DMASYNC_POSTWRITE);
3493 bus_dmamap_unload(txq->ift_buf_tag,
3494 txq->ift_sds.ifsd_map[cidx]);
3496 /* XXX we don't support any drivers that batch packets yet */
3497 MPASS(m->m_nextpkt == NULL);
3499 ifsd_m[cidx] = NULL;
3501 txq->ift_dequeued++;
3503 DBG_COUNTER_INC(tx_frees);
3505 if (__predict_false(++cidx == qsize)) {
3510 txq->ift_cidx = cidx;
3515 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3518 if_ctx_t ctx = txq->ift_ctx;
3520 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3521 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3524 * Need a rate-limiting check so that this isn't called every time
3526 iflib_tx_credits_update(ctx, txq);
3527 reclaim = DESC_RECLAIMABLE(txq);
3529 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3531 if (iflib_verbose_debug) {
3532 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3533 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3540 iflib_tx_desc_free(txq, reclaim);
3541 txq->ift_cleaned += reclaim;
3542 txq->ift_in_use -= reclaim;
3547 static struct mbuf **
3548 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3551 struct mbuf **items;
3554 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3555 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3557 prefetch(items[(cidx + offset) & (size-1)]);
3558 if (remaining > 1) {
3559 prefetch2cachelines(&items[next]);
3560 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3561 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3562 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3564 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3568 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3571 ifmp_ring_check_drainage(txq->ift_br, budget);
3575 iflib_txq_can_drain(struct ifmp_ring *r)
3577 iflib_txq_t txq = r->cookie;
3578 if_ctx_t ctx = txq->ift_ctx;
3580 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3582 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3583 BUS_DMASYNC_POSTREAD);
3584 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3589 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3591 iflib_txq_t txq = r->cookie;
3592 if_ctx_t ctx = txq->ift_ctx;
3593 if_t ifp = ctx->ifc_ifp;
3594 struct mbuf *m, **mp;
3595 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3596 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3597 bool do_prefetch, rang, ring;
3599 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3600 !LINK_ACTIVE(ctx))) {
3601 DBG_COUNTER_INC(txq_drain_notready);
3604 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3605 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3606 avail = IDXDIFF(pidx, cidx, r->size);
3607 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3608 DBG_COUNTER_INC(txq_drain_flushing);
3609 for (i = 0; i < avail; i++) {
3610 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3611 m_free(r->items[(cidx + i) & (r->size-1)]);
3612 r->items[(cidx + i) & (r->size-1)] = NULL;
3617 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3618 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3620 callout_stop(&txq->ift_timer);
3621 CALLOUT_UNLOCK(txq);
3622 DBG_COUNTER_INC(txq_drain_oactive);
3626 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3627 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3628 count = MIN(avail, TX_BATCH_SIZE);
3630 if (iflib_verbose_debug)
3631 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3632 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3634 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3635 txq_avail = TXQ_AVAIL(txq);
3637 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3638 int rem = do_prefetch ? count - i : 0;
3640 mp = _ring_peek_one(r, cidx, i, rem);
3641 MPASS(mp != NULL && *mp != NULL);
3642 if (__predict_false(*mp == (struct mbuf *)txq)) {
3646 in_use_prev = txq->ift_in_use;
3647 err = iflib_encap(txq, mp);
3648 if (__predict_false(err)) {
3649 /* no room - bail out */
3653 /* we can't send this packet - skip it */
3659 DBG_COUNTER_INC(tx_sent);
3660 bytes_sent += m->m_pkthdr.len;
3661 mcast_sent += !!(m->m_flags & M_MCAST);
3662 txq_avail = TXQ_AVAIL(txq);
3664 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3665 ETHER_BPF_MTAP(ifp, m);
3666 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3668 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3671 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3672 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3673 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3674 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3675 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3677 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3679 if (iflib_verbose_debug)
3680 printf("consumed=%d\n", consumed);
3686 iflib_txq_drain_always(struct ifmp_ring *r)
3692 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3700 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3702 callout_stop(&txq->ift_timer);
3703 CALLOUT_UNLOCK(txq);
3705 avail = IDXDIFF(pidx, cidx, r->size);
3706 for (i = 0; i < avail; i++) {
3707 mp = _ring_peek_one(r, cidx, i, avail - i);
3708 if (__predict_false(*mp == (struct mbuf *)txq))
3711 DBG_COUNTER_INC(tx_frees);
3713 MPASS(ifmp_ring_is_stalled(r) == 0);
3718 iflib_ifmp_purge(iflib_txq_t txq)
3720 struct ifmp_ring *r;
3723 r->drain = iflib_txq_drain_free;
3724 r->can_drain = iflib_txq_drain_always;
3726 ifmp_ring_check_drainage(r, r->size);
3728 r->drain = iflib_txq_drain;
3729 r->can_drain = iflib_txq_can_drain;
3733 _task_fn_tx(void *context)
3735 iflib_txq_t txq = context;
3736 if_ctx_t ctx = txq->ift_ctx;
3737 #if defined(ALTQ) || defined(DEV_NETMAP)
3738 if_t ifp = ctx->ifc_ifp;
3740 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3742 #ifdef IFLIB_DIAGNOSTICS
3743 txq->ift_cpu_exec_count[curcpu]++;
3745 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3748 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3749 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3750 BUS_DMASYNC_POSTREAD);
3751 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3752 netmap_tx_irq(ifp, txq->ift_id);
3753 if (ctx->ifc_flags & IFC_LEGACY)
3754 IFDI_INTR_ENABLE(ctx);
3756 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3761 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3762 iflib_altq_if_start(ifp);
3764 if (txq->ift_db_pending)
3765 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3767 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3769 * When abdicating, we always need to check drainage, not just when we don't enqueue
3772 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3773 if (ctx->ifc_flags & IFC_LEGACY)
3774 IFDI_INTR_ENABLE(ctx);
3776 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3780 _task_fn_rx(void *context)
3782 iflib_rxq_t rxq = context;
3783 if_ctx_t ctx = rxq->ifr_ctx;
3787 #ifdef IFLIB_DIAGNOSTICS
3788 rxq->ifr_cpu_exec_count[curcpu]++;
3790 DBG_COUNTER_INC(task_fn_rxs);
3791 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3795 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3797 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3802 budget = ctx->ifc_sysctl_rx_budget;
3804 budget = 16; /* XXX */
3805 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3806 if (ctx->ifc_flags & IFC_LEGACY)
3807 IFDI_INTR_ENABLE(ctx);
3809 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3810 DBG_COUNTER_INC(rx_intr_enables);
3812 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3815 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3819 _task_fn_admin(void *context)
3821 if_ctx_t ctx = context;
3822 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3825 bool oactive, running, do_reset, do_watchdog, in_detach;
3826 uint32_t reset_on = hz / 2;
3829 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3830 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3831 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3832 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3833 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3834 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3837 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3843 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3845 callout_stop(&txq->ift_timer);
3846 CALLOUT_UNLOCK(txq);
3849 ctx->ifc_watchdog_events++;
3850 IFDI_WATCHDOG_RESET(ctx);
3852 IFDI_UPDATE_ADMIN_STATUS(ctx);
3853 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3856 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3857 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3859 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3861 IFDI_LINK_INTR_ENABLE(ctx);
3863 iflib_if_init_locked(ctx);
3866 if (LINK_ACTIVE(ctx) == 0)
3868 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3869 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3874 _task_fn_iov(void *context)
3876 if_ctx_t ctx = context;
3878 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3879 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3883 IFDI_VFLR_HANDLE(ctx);
3888 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3891 if_int_delay_info_t info;
3894 info = (if_int_delay_info_t)arg1;
3895 ctx = info->iidi_ctx;
3896 info->iidi_req = req;
3897 info->iidi_oidp = oidp;
3899 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3904 /*********************************************************************
3908 **********************************************************************/
3911 iflib_if_init_locked(if_ctx_t ctx)
3914 iflib_init_locked(ctx);
3919 iflib_if_init(void *arg)
3924 iflib_if_init_locked(ctx);
3929 iflib_if_transmit(if_t ifp, struct mbuf *m)
3931 if_ctx_t ctx = if_getsoftc(ifp);
3935 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3937 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3938 DBG_COUNTER_INC(tx_frees);
3943 MPASS(m->m_nextpkt == NULL);
3944 /* ALTQ-enabled interfaces always use queue 0. */
3946 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3947 qidx = QIDX(ctx, m);
3949 * XXX calculate buf_ring based on flowid (divvy up bits?)
3951 txq = &ctx->ifc_txqs[qidx];
3953 #ifdef DRIVER_BACKPRESSURE
3954 if (txq->ift_closed) {
3956 next = m->m_nextpkt;
3957 m->m_nextpkt = NULL;
3959 DBG_COUNTER_INC(tx_frees);
3971 next = next->m_nextpkt;
3972 } while (next != NULL);
3974 if (count > nitems(marr))
3975 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3976 /* XXX check nextpkt */
3978 /* XXX simplify for now */
3979 DBG_COUNTER_INC(tx_frees);
3982 for (next = m, i = 0; next != NULL; i++) {
3984 next = next->m_nextpkt;
3985 mp[i]->m_nextpkt = NULL;
3988 DBG_COUNTER_INC(tx_seen);
3989 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3992 GROUPTASK_ENQUEUE(&txq->ift_task);
3995 GROUPTASK_ENQUEUE(&txq->ift_task);
3996 /* support forthcoming later */
3997 #ifdef DRIVER_BACKPRESSURE
3998 txq->ift_closed = TRUE;
4000 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4002 DBG_COUNTER_INC(tx_frees);
4010 * The overall approach to integrating iflib with ALTQ is to continue to use
4011 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4012 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4013 * is redundant/unnecessary, but doing so minimizes the amount of
4014 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4015 * redundantly queueing to an intermediate mp_ring is swamped by the
4016 * performance limitations inherent in using ALTQ.
4018 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4019 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4020 * given interface. If ALTQ is enabled for an interface, then all
4021 * transmitted packets for that interface will be submitted to the ALTQ
4022 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4023 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4024 * update stats that the iflib machinery handles, and which is sensitve to
4025 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4026 * will be installed as the start routine for use by ALTQ facilities that
4027 * need to trigger queue drains on a scheduled basis.
4031 iflib_altq_if_start(if_t ifp)
4033 struct ifaltq *ifq = &ifp->if_snd;
4037 IFQ_DEQUEUE_NOLOCK(ifq, m);
4039 iflib_if_transmit(ifp, m);
4040 IFQ_DEQUEUE_NOLOCK(ifq, m);
4046 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4050 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4051 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4053 iflib_altq_if_start(ifp);
4055 err = iflib_if_transmit(ifp, m);
4062 iflib_if_qflush(if_t ifp)
4064 if_ctx_t ctx = if_getsoftc(ifp);
4065 iflib_txq_t txq = ctx->ifc_txqs;
4069 ctx->ifc_flags |= IFC_QFLUSH;
4071 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4072 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4073 iflib_txq_check_drain(txq, 0);
4075 ctx->ifc_flags &= ~IFC_QFLUSH;
4079 * When ALTQ is enabled, this will also take care of purging the
4086 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4087 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4088 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4089 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4092 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4094 if_ctx_t ctx = if_getsoftc(ifp);
4095 struct ifreq *ifr = (struct ifreq *)data;
4096 #if defined(INET) || defined(INET6)
4097 struct ifaddr *ifa = (struct ifaddr *)data;
4099 bool avoid_reset = false;
4100 int err = 0, reinit = 0, bits;
4105 if (ifa->ifa_addr->sa_family == AF_INET)
4109 if (ifa->ifa_addr->sa_family == AF_INET6)
4113 ** Calling init results in link renegotiation,
4114 ** so we avoid doing it when possible.
4117 if_setflagbits(ifp, IFF_UP,0);
4118 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4121 if (!(if_getflags(ifp) & IFF_NOARP))
4122 arp_ifinit(ifp, ifa);
4125 err = ether_ioctl(ifp, command, data);
4129 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4133 bits = if_getdrvflags(ifp);
4134 /* stop the driver and free any clusters before proceeding */
4137 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4139 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4140 ctx->ifc_flags |= IFC_MULTISEG;
4142 ctx->ifc_flags &= ~IFC_MULTISEG;
4144 err = if_setmtu(ifp, ifr->ifr_mtu);
4146 iflib_init_locked(ctx);
4148 if_setdrvflags(ifp, bits);
4154 if (if_getflags(ifp) & IFF_UP) {
4155 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4156 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4157 (IFF_PROMISC | IFF_ALLMULTI)) {
4158 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4162 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4165 ctx->ifc_if_flags = if_getflags(ifp);
4170 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4172 IFDI_INTR_DISABLE(ctx);
4173 IFDI_MULTI_SET(ctx);
4174 IFDI_INTR_ENABLE(ctx);
4180 IFDI_MEDIA_SET(ctx);
4185 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4189 struct ifi2creq i2c;
4191 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4194 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4198 if (i2c.len > sizeof(i2c.data)) {
4203 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4204 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4210 int mask, setmask, oldmask;
4212 oldmask = if_getcapenable(ifp);
4213 mask = ifr->ifr_reqcap ^ oldmask;
4214 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4217 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4219 setmask |= (mask & IFCAP_FLAGS);
4220 setmask |= (mask & IFCAP_WOL);
4223 * If any RX csum has changed, change all the ones that
4224 * are supported by the driver.
4226 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4227 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4228 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4232 * want to ensure that traffic has stopped before we change any of the flags
4236 bits = if_getdrvflags(ifp);
4237 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4240 if_togglecapenable(ifp, setmask);
4242 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4243 iflib_init_locked(ctx);
4245 if_setdrvflags(ifp, bits);
4252 case SIOCGPRIVATE_0:
4256 err = IFDI_PRIV_IOCTL(ctx, command, data);
4260 err = ether_ioctl(ifp, command, data);
4269 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4271 if_ctx_t ctx = if_getsoftc(ifp);
4273 return (IFDI_GET_COUNTER(ctx, cnt));
4276 /*********************************************************************
4278 * OTHER FUNCTIONS EXPORTED TO THE STACK
4280 **********************************************************************/
4283 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4285 if_ctx_t ctx = if_getsoftc(ifp);
4287 if ((void *)ctx != arg)
4290 if ((vtag == 0) || (vtag > 4095))
4293 if (iflib_in_detach(ctx))
4297 IFDI_VLAN_REGISTER(ctx, vtag);
4298 /* Re-init to load the changes */
4299 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4300 iflib_if_init_locked(ctx);
4305 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4307 if_ctx_t ctx = if_getsoftc(ifp);
4309 if ((void *)ctx != arg)
4312 if ((vtag == 0) || (vtag > 4095))
4316 IFDI_VLAN_UNREGISTER(ctx, vtag);
4317 /* Re-init to load the changes */
4318 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4319 iflib_if_init_locked(ctx);
4324 iflib_led_func(void *arg, int onoff)
4329 IFDI_LED_FUNC(ctx, onoff);
4333 /*********************************************************************
4335 * BUS FUNCTION DEFINITIONS
4337 **********************************************************************/
4340 iflib_device_probe(device_t dev)
4342 const pci_vendor_info_t *ent;
4343 if_shared_ctx_t sctx;
4344 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4345 uint16_t pci_vendor_id;
4347 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4350 pci_vendor_id = pci_get_vendor(dev);
4351 pci_device_id = pci_get_device(dev);
4352 pci_subvendor_id = pci_get_subvendor(dev);
4353 pci_subdevice_id = pci_get_subdevice(dev);
4354 pci_rev_id = pci_get_revid(dev);
4355 if (sctx->isc_parse_devinfo != NULL)
4356 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4358 ent = sctx->isc_vendor_info;
4359 while (ent->pvi_vendor_id != 0) {
4360 if (pci_vendor_id != ent->pvi_vendor_id) {
4364 if ((pci_device_id == ent->pvi_device_id) &&
4365 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4366 (ent->pvi_subvendor_id == 0)) &&
4367 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4368 (ent->pvi_subdevice_id == 0)) &&
4369 ((pci_rev_id == ent->pvi_rev_id) ||
4370 (ent->pvi_rev_id == 0))) {
4372 device_set_desc_copy(dev, ent->pvi_name);
4373 /* this needs to be changed to zero if the bus probing code
4374 * ever stops re-probing on best match because the sctx
4375 * may have its values over written by register calls
4376 * in subsequent probes
4378 return (BUS_PROBE_DEFAULT);
4386 iflib_device_probe_vendor(device_t dev)
4390 probe = iflib_device_probe(dev);
4391 if (probe == BUS_PROBE_DEFAULT)
4392 return (BUS_PROBE_VENDOR);
4398 iflib_reset_qvalues(if_ctx_t ctx)
4400 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4401 if_shared_ctx_t sctx = ctx->ifc_sctx;
4402 device_t dev = ctx->ifc_dev;
4405 if (ctx->ifc_sysctl_ntxqs != 0)
4406 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4407 if (ctx->ifc_sysctl_nrxqs != 0)
4408 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4410 for (i = 0; i < sctx->isc_ntxqs; i++) {
4411 if (ctx->ifc_sysctl_ntxds[i] != 0)
4412 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4414 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4417 for (i = 0; i < sctx->isc_nrxqs; i++) {
4418 if (ctx->ifc_sysctl_nrxds[i] != 0)
4419 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4421 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4424 for (i = 0; i < sctx->isc_nrxqs; i++) {
4425 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4426 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4427 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4428 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4430 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4431 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4432 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4433 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4435 if (!powerof2(scctx->isc_nrxd[i])) {
4436 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4437 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4438 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4442 for (i = 0; i < sctx->isc_ntxqs; i++) {
4443 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4444 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4445 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4446 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4448 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4449 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4450 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4451 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4453 if (!powerof2(scctx->isc_ntxd[i])) {
4454 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4455 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4456 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4462 iflib_add_pfil(if_ctx_t ctx)
4464 struct pfil_head *pfil;
4465 struct pfil_head_args pa;
4469 pa.pa_version = PFIL_VERSION;
4470 pa.pa_flags = PFIL_IN;
4471 pa.pa_type = PFIL_TYPE_ETHERNET;
4472 pa.pa_headname = ctx->ifc_ifp->if_xname;
4473 pfil = pfil_head_register(&pa);
4475 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4481 iflib_rem_pfil(if_ctx_t ctx)
4483 struct pfil_head *pfil;
4487 rxq = ctx->ifc_rxqs;
4489 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4492 pfil_head_unregister(pfil);
4496 get_ctx_core_offset(if_ctx_t ctx)
4498 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4499 struct cpu_offset *op;
4501 uint16_t ret = ctx->ifc_sysctl_core_offset;
4503 if (ret != CORE_OFFSET_UNSPECIFIED)
4506 if (ctx->ifc_sysctl_separate_txrx)
4507 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4509 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4511 mtx_lock(&cpu_offset_mtx);
4512 SLIST_FOREACH(op, &cpu_offsets, entries) {
4513 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4516 MPASS(op->refcount < UINT_MAX);
4521 if (ret == CORE_OFFSET_UNSPECIFIED) {
4523 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4526 device_printf(ctx->ifc_dev,
4527 "allocation for cpu offset failed.\n");
4531 CPU_COPY(&ctx->ifc_cpus, &op->set);
4532 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4535 mtx_unlock(&cpu_offset_mtx);
4541 unref_ctx_core_offset(if_ctx_t ctx)
4543 struct cpu_offset *op, *top;
4545 mtx_lock(&cpu_offset_mtx);
4546 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4547 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4548 MPASS(op->refcount > 0);
4550 if (op->refcount == 0) {
4551 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4557 mtx_unlock(&cpu_offset_mtx);
4561 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4565 if_softc_ctx_t scctx;
4566 kobjop_desc_t kobj_desc;
4567 kobj_method_t *kobj_method;
4569 uint16_t main_rxq, main_txq;
4571 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4574 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4575 device_set_softc(dev, ctx);
4576 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4579 ctx->ifc_sctx = sctx;
4581 ctx->ifc_softc = sc;
4583 if ((err = iflib_register(ctx)) != 0) {
4584 device_printf(dev, "iflib_register failed %d\n", err);
4587 iflib_add_device_sysctl_pre(ctx);
4589 scctx = &ctx->ifc_softc_ctx;
4592 iflib_reset_qvalues(ctx);
4594 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4595 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4598 _iflib_pre_assert(scctx);
4599 ctx->ifc_txrx = *scctx->isc_txrx;
4601 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4602 ctx->ifc_mediap = scctx->isc_media;
4605 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4606 MPASS(scctx->isc_tx_csum_flags);
4609 if_setcapabilities(ifp,
4610 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4611 if_setcapenable(ifp,
4612 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4614 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4615 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4616 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4617 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4619 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4620 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4622 /* XXX change for per-queue sizes */
4623 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4624 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4626 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4627 MAX_SINGLE_PACKET_FRACTION)
4628 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4629 MAX_SINGLE_PACKET_FRACTION);
4630 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4631 MAX_SINGLE_PACKET_FRACTION)
4632 scctx->isc_tx_tso_segments_max = max(1,
4633 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4635 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4636 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4638 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4641 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4644 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4645 * into account. In the worst case, each of these calls will
4646 * add another mbuf and, thus, the requirement for another DMA
4647 * segment. So for best performance, it doesn't make sense to
4648 * advertize a maximum of TSO segments that typically will
4649 * require defragmentation in iflib_encap().
4651 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4652 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4654 if (scctx->isc_rss_table_size == 0)
4655 scctx->isc_rss_table_size = 64;
4656 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4658 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4659 /* XXX format name */
4660 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4661 NULL, NULL, "admin");
4663 /* Set up cpu set. If it fails, use the set of all CPUs. */
4664 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4665 device_printf(dev, "Unable to fetch CPU list\n");
4666 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4668 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4671 ** Now set up MSI or MSI-X, should return us the number of supported
4672 ** vectors (will be 1 for a legacy interrupt and MSI).
4674 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4675 msix = scctx->isc_vectors;
4676 } else if (scctx->isc_msix_bar != 0)
4678 * The simple fact that isc_msix_bar is not 0 does not mean we
4679 * we have a good value there that is known to work.
4681 msix = iflib_msix_init(ctx);
4683 scctx->isc_vectors = 1;
4684 scctx->isc_ntxqsets = 1;
4685 scctx->isc_nrxqsets = 1;
4686 scctx->isc_intr = IFLIB_INTR_LEGACY;
4689 /* Get memory for the station queues */
4690 if ((err = iflib_queues_alloc(ctx))) {
4691 device_printf(dev, "Unable to allocate queue memory\n");
4692 goto fail_intr_free;
4695 if ((err = iflib_qset_structures_setup(ctx)))
4699 * Now that we know how many queues there are, get the core offset.
4701 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4704 * Group taskqueues aren't properly set up until SMP is started,
4705 * so we disable interrupts until we can handle them post
4708 * XXX: disabling interrupts doesn't actually work, at least for
4709 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4710 * we do null handling and depend on this not causing too large an
4713 IFDI_INTR_DISABLE(ctx);
4717 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4718 * aren't the default NULL implementation.
4720 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4721 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4723 if (kobj_method == &kobj_desc->deflt) {
4725 "MSI-X requires ifdi_rx_queue_intr_enable method");
4729 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4730 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4732 if (kobj_method == &kobj_desc->deflt) {
4734 "MSI-X requires ifdi_tx_queue_intr_enable method");
4740 * Assign the MSI-X vectors.
4741 * Note that the default NULL ifdi_msix_intr_assign method will
4744 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4746 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4750 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4752 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4756 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4757 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4762 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4764 goto fail_intr_free;
4767 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4769 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4770 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4775 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4776 * This must appear after the call to ether_ifattach() because
4777 * ether_ifattach() sets if_hdrlen to the default value.
4779 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4780 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4782 if ((err = iflib_netmap_attach(ctx))) {
4783 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4788 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4790 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4791 iflib_add_device_sysctl_post(ctx);
4792 iflib_add_pfil(ctx);
4793 ctx->ifc_flags |= IFC_INIT_DONE;
4799 ether_ifdetach(ctx->ifc_ifp);
4801 iflib_free_intr_mem(ctx);
4803 iflib_tx_structures_free(ctx);
4804 iflib_rx_structures_free(ctx);
4805 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4809 iflib_deregister(ctx);
4811 device_set_softc(ctx->ifc_dev, NULL);
4812 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4813 free(ctx->ifc_softc, M_IFLIB);
4819 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4820 struct iflib_cloneattach_ctx *clctx)
4825 if_softc_ctx_t scctx;
4831 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4832 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4833 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4834 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4835 ctx->ifc_flags |= IFC_PSEUDO;
4837 ctx->ifc_sctx = sctx;
4838 ctx->ifc_softc = sc;
4841 if ((err = iflib_register(ctx)) != 0) {
4842 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4845 iflib_add_device_sysctl_pre(ctx);
4847 scctx = &ctx->ifc_softc_ctx;
4850 iflib_reset_qvalues(ctx);
4852 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4853 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4856 if (sctx->isc_flags & IFLIB_GEN_MAC)
4857 ether_gen_addr(ifp, &ctx->ifc_mac);
4858 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4859 clctx->cc_params)) != 0) {
4860 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4863 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4864 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4865 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4868 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4869 MPASS(scctx->isc_tx_csum_flags);
4872 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4873 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4875 ifp->if_flags |= IFF_NOGROUP;
4876 if (sctx->isc_flags & IFLIB_PSEUDO) {
4877 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4879 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4880 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4886 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4887 * This must appear after the call to ether_ifattach() because
4888 * ether_ifattach() sets if_hdrlen to the default value.
4890 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4891 if_setifheaderlen(ifp,
4892 sizeof(struct ether_vlan_header));
4894 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4895 iflib_add_device_sysctl_post(ctx);
4896 ctx->ifc_flags |= IFC_INIT_DONE;
4899 _iflib_pre_assert(scctx);
4900 ctx->ifc_txrx = *scctx->isc_txrx;
4902 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4903 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4904 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4905 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4907 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4908 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4910 /* XXX change for per-queue sizes */
4911 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4912 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4914 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4915 MAX_SINGLE_PACKET_FRACTION)
4916 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4917 MAX_SINGLE_PACKET_FRACTION);
4918 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4919 MAX_SINGLE_PACKET_FRACTION)
4920 scctx->isc_tx_tso_segments_max = max(1,
4921 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4923 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4924 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4926 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4929 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4932 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4933 * into account. In the worst case, each of these calls will
4934 * add another mbuf and, thus, the requirement for another DMA
4935 * segment. So for best performance, it doesn't make sense to
4936 * advertize a maximum of TSO segments that typically will
4937 * require defragmentation in iflib_encap().
4939 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4940 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4942 if (scctx->isc_rss_table_size == 0)
4943 scctx->isc_rss_table_size = 64;
4944 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4946 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4947 /* XXX format name */
4948 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4949 NULL, NULL, "admin");
4951 /* XXX --- can support > 1 -- but keep it simple for now */
4952 scctx->isc_intr = IFLIB_INTR_LEGACY;
4954 /* Get memory for the station queues */
4955 if ((err = iflib_queues_alloc(ctx))) {
4956 device_printf(dev, "Unable to allocate queue memory\n");
4957 goto fail_iflib_detach;
4960 if ((err = iflib_qset_structures_setup(ctx))) {
4961 device_printf(dev, "qset structure setup failed %d\n", err);
4966 * XXX What if anything do we want to do about interrupts?
4968 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4969 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4970 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4975 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4976 * This must appear after the call to ether_ifattach() because
4977 * ether_ifattach() sets if_hdrlen to the default value.
4979 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4980 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4982 /* XXX handle more than one queue */
4983 for (i = 0; i < scctx->isc_nrxqsets; i++)
4984 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4988 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4989 iflib_add_device_sysctl_post(ctx);
4990 ctx->ifc_flags |= IFC_INIT_DONE;
4995 ether_ifdetach(ctx->ifc_ifp);
4997 iflib_tx_structures_free(ctx);
4998 iflib_rx_structures_free(ctx);
5003 iflib_deregister(ctx);
5005 free(ctx->ifc_softc, M_IFLIB);
5011 iflib_pseudo_deregister(if_ctx_t ctx)
5013 if_t ifp = ctx->ifc_ifp;
5017 struct taskqgroup *tqg;
5020 /* Unregister VLAN event handlers early */
5021 iflib_unregister_vlan_handlers(ctx);
5023 ether_ifdetach(ifp);
5024 /* XXX drain any dependent tasks */
5025 tqg = qgroup_if_io_tqg;
5026 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5027 callout_drain(&txq->ift_timer);
5028 if (txq->ift_task.gt_uniq != NULL)
5029 taskqgroup_detach(tqg, &txq->ift_task);
5031 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5032 if (rxq->ifr_task.gt_uniq != NULL)
5033 taskqgroup_detach(tqg, &rxq->ifr_task);
5035 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5036 free(fl->ifl_rx_bitmap, M_IFLIB);
5038 tqg = qgroup_if_config_tqg;
5039 if (ctx->ifc_admin_task.gt_uniq != NULL)
5040 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5041 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5042 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5044 iflib_tx_structures_free(ctx);
5045 iflib_rx_structures_free(ctx);
5047 iflib_deregister(ctx);
5049 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5050 free(ctx->ifc_softc, M_IFLIB);
5056 iflib_device_attach(device_t dev)
5059 if_shared_ctx_t sctx;
5061 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5064 pci_enable_busmaster(dev);
5066 return (iflib_device_register(dev, NULL, sctx, &ctx));
5070 iflib_device_deregister(if_ctx_t ctx)
5072 if_t ifp = ctx->ifc_ifp;
5075 device_t dev = ctx->ifc_dev;
5077 struct taskqgroup *tqg;
5080 /* Make sure VLANS are not using driver */
5081 if (if_vlantrunkinuse(ifp)) {
5082 device_printf(dev, "Vlan in use, detach first\n");
5086 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5087 device_printf(dev, "SR-IOV in use; detach first.\n");
5093 ctx->ifc_flags |= IFC_IN_DETACH;
5096 /* Unregister VLAN handlers before calling iflib_stop() */
5097 iflib_unregister_vlan_handlers(ctx);
5099 iflib_netmap_detach(ifp);
5100 ether_ifdetach(ifp);
5106 iflib_rem_pfil(ctx);
5107 if (ctx->ifc_led_dev != NULL)
5108 led_destroy(ctx->ifc_led_dev);
5109 /* XXX drain any dependent tasks */
5110 tqg = qgroup_if_io_tqg;
5111 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5112 callout_drain(&txq->ift_timer);
5113 if (txq->ift_task.gt_uniq != NULL)
5114 taskqgroup_detach(tqg, &txq->ift_task);
5116 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5117 if (rxq->ifr_task.gt_uniq != NULL)
5118 taskqgroup_detach(tqg, &rxq->ifr_task);
5120 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5121 free(fl->ifl_rx_bitmap, M_IFLIB);
5123 tqg = qgroup_if_config_tqg;
5124 if (ctx->ifc_admin_task.gt_uniq != NULL)
5125 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5126 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5127 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5132 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5133 iflib_free_intr_mem(ctx);
5135 bus_generic_detach(dev);
5137 iflib_tx_structures_free(ctx);
5138 iflib_rx_structures_free(ctx);
5140 iflib_deregister(ctx);
5142 device_set_softc(ctx->ifc_dev, NULL);
5143 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5144 free(ctx->ifc_softc, M_IFLIB);
5145 unref_ctx_core_offset(ctx);
5151 iflib_free_intr_mem(if_ctx_t ctx)
5154 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5155 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5157 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5158 pci_release_msi(ctx->ifc_dev);
5160 if (ctx->ifc_msix_mem != NULL) {
5161 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5162 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5163 ctx->ifc_msix_mem = NULL;
5168 iflib_device_detach(device_t dev)
5170 if_ctx_t ctx = device_get_softc(dev);
5172 return (iflib_device_deregister(ctx));
5176 iflib_device_suspend(device_t dev)
5178 if_ctx_t ctx = device_get_softc(dev);
5184 return bus_generic_suspend(dev);
5187 iflib_device_shutdown(device_t dev)
5189 if_ctx_t ctx = device_get_softc(dev);
5195 return bus_generic_suspend(dev);
5200 iflib_device_resume(device_t dev)
5202 if_ctx_t ctx = device_get_softc(dev);
5203 iflib_txq_t txq = ctx->ifc_txqs;
5207 iflib_if_init_locked(ctx);
5209 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5210 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5212 return (bus_generic_resume(dev));
5216 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5219 if_ctx_t ctx = device_get_softc(dev);
5222 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5229 iflib_device_iov_uninit(device_t dev)
5231 if_ctx_t ctx = device_get_softc(dev);
5234 IFDI_IOV_UNINIT(ctx);
5239 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5242 if_ctx_t ctx = device_get_softc(dev);
5245 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5251 /*********************************************************************
5253 * MODULE FUNCTION DEFINITIONS
5255 **********************************************************************/
5258 * - Start a fast taskqueue thread for each core
5259 * - Start a taskqueue for control operations
5262 iflib_module_init(void)
5268 iflib_module_event_handler(module_t mod, int what, void *arg)
5274 if ((err = iflib_module_init()) != 0)
5280 return (EOPNOTSUPP);
5286 /*********************************************************************
5288 * PUBLIC FUNCTION DEFINITIONS
5289 * ordered as in iflib.h
5291 **********************************************************************/
5295 _iflib_assert(if_shared_ctx_t sctx)
5299 MPASS(sctx->isc_tx_maxsize);
5300 MPASS(sctx->isc_tx_maxsegsize);
5302 MPASS(sctx->isc_rx_maxsize);
5303 MPASS(sctx->isc_rx_nsegments);
5304 MPASS(sctx->isc_rx_maxsegsize);
5306 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5307 for (i = 0; i < sctx->isc_nrxqs; i++) {
5308 MPASS(sctx->isc_nrxd_min[i]);
5309 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5310 MPASS(sctx->isc_nrxd_max[i]);
5311 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5312 MPASS(sctx->isc_nrxd_default[i]);
5313 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5316 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5317 for (i = 0; i < sctx->isc_ntxqs; i++) {
5318 MPASS(sctx->isc_ntxd_min[i]);
5319 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5320 MPASS(sctx->isc_ntxd_max[i]);
5321 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5322 MPASS(sctx->isc_ntxd_default[i]);
5323 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5328 _iflib_pre_assert(if_softc_ctx_t scctx)
5331 MPASS(scctx->isc_txrx->ift_txd_encap);
5332 MPASS(scctx->isc_txrx->ift_txd_flush);
5333 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5334 MPASS(scctx->isc_txrx->ift_rxd_available);
5335 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5336 MPASS(scctx->isc_txrx->ift_rxd_refill);
5337 MPASS(scctx->isc_txrx->ift_rxd_flush);
5341 iflib_register(if_ctx_t ctx)
5343 if_shared_ctx_t sctx = ctx->ifc_sctx;
5344 driver_t *driver = sctx->isc_driver;
5345 device_t dev = ctx->ifc_dev;
5348 _iflib_assert(sctx);
5351 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5352 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5354 device_printf(dev, "can not allocate ifnet structure\n");
5359 * Initialize our context's device specific methods
5361 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5362 kobj_class_compile((kobj_class_t) driver);
5364 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5365 if_setsoftc(ifp, ctx);
5366 if_setdev(ifp, dev);
5367 if_setinitfn(ifp, iflib_if_init);
5368 if_setioctlfn(ifp, iflib_if_ioctl);
5370 if_setstartfn(ifp, iflib_altq_if_start);
5371 if_settransmitfn(ifp, iflib_altq_if_transmit);
5372 if_setsendqready(ifp);
5374 if_settransmitfn(ifp, iflib_if_transmit);
5376 if_setqflushfn(ifp, iflib_if_qflush);
5377 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5379 ctx->ifc_vlan_attach_event =
5380 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5381 EVENTHANDLER_PRI_FIRST);
5382 ctx->ifc_vlan_detach_event =
5383 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5384 EVENTHANDLER_PRI_FIRST);
5386 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5387 ctx->ifc_mediap = &ctx->ifc_media;
5388 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5389 iflib_media_change, iflib_media_status);
5395 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5397 /* Unregister VLAN events */
5398 if (ctx->ifc_vlan_attach_event != NULL) {
5399 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5400 ctx->ifc_vlan_attach_event = NULL;
5402 if (ctx->ifc_vlan_detach_event != NULL) {
5403 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5404 ctx->ifc_vlan_detach_event = NULL;
5410 iflib_deregister(if_ctx_t ctx)
5412 if_t ifp = ctx->ifc_ifp;
5414 /* Remove all media */
5415 ifmedia_removeall(&ctx->ifc_media);
5417 /* Ensure that VLAN event handlers are unregistered */
5418 iflib_unregister_vlan_handlers(ctx);
5420 /* Release kobject reference */
5421 kobj_delete((kobj_t) ctx, NULL);
5423 /* Free the ifnet structure */
5426 STATE_LOCK_DESTROY(ctx);
5428 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5429 CTX_LOCK_DESTROY(ctx);
5433 iflib_queues_alloc(if_ctx_t ctx)
5435 if_shared_ctx_t sctx = ctx->ifc_sctx;
5436 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5437 device_t dev = ctx->ifc_dev;
5438 int nrxqsets = scctx->isc_nrxqsets;
5439 int ntxqsets = scctx->isc_ntxqsets;
5442 iflib_fl_t fl = NULL;
5443 int i, j, cpu, err, txconf, rxconf;
5444 iflib_dma_info_t ifdip;
5445 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5446 uint32_t *txqsizes = scctx->isc_txqsizes;
5447 uint8_t nrxqs = sctx->isc_nrxqs;
5448 uint8_t ntxqs = sctx->isc_ntxqs;
5449 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5453 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5454 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5456 /* Allocate the TX ring struct memory */
5457 if (!(ctx->ifc_txqs =
5458 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5459 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5460 device_printf(dev, "Unable to allocate TX ring memory\n");
5465 /* Now allocate the RX */
5466 if (!(ctx->ifc_rxqs =
5467 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5468 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5469 device_printf(dev, "Unable to allocate RX ring memory\n");
5474 txq = ctx->ifc_txqs;
5475 rxq = ctx->ifc_rxqs;
5478 * XXX handle allocation failure
5480 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5481 /* Set up some basics */
5483 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5484 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5486 "Unable to allocate TX DMA info memory\n");
5490 txq->ift_ifdi = ifdip;
5491 for (j = 0; j < ntxqs; j++, ifdip++) {
5492 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5494 "Unable to allocate TX descriptors\n");
5498 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5499 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5503 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5504 txq->ift_br_offset = 1;
5506 txq->ift_br_offset = 0;
5509 txq->ift_timer.c_cpu = cpu;
5511 if (iflib_txsd_alloc(txq)) {
5512 device_printf(dev, "Critical Failure setting up TX buffers\n");
5517 /* Initialize the TX lock */
5518 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5519 device_get_nameunit(dev), txq->ift_id);
5520 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5521 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5523 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5524 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5526 /* XXX free any allocated rings */
5527 device_printf(dev, "Unable to allocate buf_ring\n");
5532 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5533 /* Set up some basics */
5535 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5536 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5538 "Unable to allocate RX DMA info memory\n");
5543 rxq->ifr_ifdi = ifdip;
5544 /* XXX this needs to be changed if #rx queues != #tx queues */
5545 rxq->ifr_ntxqirq = 1;
5546 rxq->ifr_txqid[0] = i;
5547 for (j = 0; j < nrxqs; j++, ifdip++) {
5548 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5550 "Unable to allocate RX descriptors\n");
5554 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5558 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5559 rxq->ifr_fl_offset = 1;
5561 rxq->ifr_fl_offset = 0;
5563 rxq->ifr_nfl = nfree_lists;
5565 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5566 device_printf(dev, "Unable to allocate free list memory\n");
5571 for (j = 0; j < nfree_lists; j++) {
5572 fl[j].ifl_rxq = rxq;
5574 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5575 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5577 /* Allocate receive buffers for the ring */
5578 if (iflib_rxsd_alloc(rxq)) {
5580 "Critical Failure setting up receive buffers\n");
5585 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5586 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5591 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5592 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5593 for (i = 0; i < ntxqsets; i++) {
5594 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5596 for (j = 0; j < ntxqs; j++, di++) {
5597 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5598 paddrs[i*ntxqs + j] = di->idi_paddr;
5601 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5602 device_printf(ctx->ifc_dev,
5603 "Unable to allocate device TX queue\n");
5604 iflib_tx_structures_free(ctx);
5605 free(vaddrs, M_IFLIB);
5606 free(paddrs, M_IFLIB);
5609 free(vaddrs, M_IFLIB);
5610 free(paddrs, M_IFLIB);
5613 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5614 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5615 for (i = 0; i < nrxqsets; i++) {
5616 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5618 for (j = 0; j < nrxqs; j++, di++) {
5619 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5620 paddrs[i*nrxqs + j] = di->idi_paddr;
5623 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5624 device_printf(ctx->ifc_dev,
5625 "Unable to allocate device RX queue\n");
5626 iflib_tx_structures_free(ctx);
5627 free(vaddrs, M_IFLIB);
5628 free(paddrs, M_IFLIB);
5631 free(vaddrs, M_IFLIB);
5632 free(paddrs, M_IFLIB);
5636 /* XXX handle allocation failure changes */
5640 if (ctx->ifc_rxqs != NULL)
5641 free(ctx->ifc_rxqs, M_IFLIB);
5642 ctx->ifc_rxqs = NULL;
5643 if (ctx->ifc_txqs != NULL)
5644 free(ctx->ifc_txqs, M_IFLIB);
5645 ctx->ifc_txqs = NULL;
5651 iflib_tx_structures_setup(if_ctx_t ctx)
5653 iflib_txq_t txq = ctx->ifc_txqs;
5656 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5657 iflib_txq_setup(txq);
5663 iflib_tx_structures_free(if_ctx_t ctx)
5665 iflib_txq_t txq = ctx->ifc_txqs;
5666 if_shared_ctx_t sctx = ctx->ifc_sctx;
5669 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5670 for (j = 0; j < sctx->isc_ntxqs; j++)
5671 iflib_dma_free(&txq->ift_ifdi[j]);
5672 iflib_txq_destroy(txq);
5674 free(ctx->ifc_txqs, M_IFLIB);
5675 ctx->ifc_txqs = NULL;
5676 IFDI_QUEUES_FREE(ctx);
5679 /*********************************************************************
5681 * Initialize all receive rings.
5683 **********************************************************************/
5685 iflib_rx_structures_setup(if_ctx_t ctx)
5687 iflib_rxq_t rxq = ctx->ifc_rxqs;
5689 #if defined(INET6) || defined(INET)
5693 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5694 #if defined(INET6) || defined(INET)
5695 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5696 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5697 TCP_LRO_ENTRIES, min(1024,
5698 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5700 device_printf(ctx->ifc_dev,
5701 "LRO Initialization failed!\n");
5706 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5709 #if defined(INET6) || defined(INET)
5712 * Free LRO resources allocated so far, we will only handle
5713 * the rings that completed, the failing case will have
5714 * cleaned up for itself. 'q' failed, so its the terminus.
5716 rxq = ctx->ifc_rxqs;
5717 for (i = 0; i < q; ++i, rxq++) {
5718 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5719 tcp_lro_free(&rxq->ifr_lc);
5725 /*********************************************************************
5727 * Free all receive rings.
5729 **********************************************************************/
5731 iflib_rx_structures_free(if_ctx_t ctx)
5733 iflib_rxq_t rxq = ctx->ifc_rxqs;
5734 if_shared_ctx_t sctx = ctx->ifc_sctx;
5737 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5738 for (j = 0; j < sctx->isc_nrxqs; j++)
5739 iflib_dma_free(&rxq->ifr_ifdi[j]);
5740 iflib_rx_sds_free(rxq);
5741 #if defined(INET6) || defined(INET)
5742 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5743 tcp_lro_free(&rxq->ifr_lc);
5746 free(ctx->ifc_rxqs, M_IFLIB);
5747 ctx->ifc_rxqs = NULL;
5751 iflib_qset_structures_setup(if_ctx_t ctx)
5756 * It is expected that the caller takes care of freeing queues if this
5759 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5760 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5764 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5765 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5771 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5772 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5775 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5780 find_nth(if_ctx_t ctx, int qid)
5783 int i, cpuid, eqid, count;
5785 CPU_COPY(&ctx->ifc_cpus, &cpus);
5786 count = CPU_COUNT(&cpus);
5788 /* clear up to the qid'th bit */
5789 for (i = 0; i < eqid; i++) {
5790 cpuid = CPU_FFS(&cpus);
5792 CPU_CLR(cpuid-1, &cpus);
5794 cpuid = CPU_FFS(&cpus);
5800 extern struct cpu_group *cpu_top; /* CPU topology */
5803 find_child_with_core(int cpu, struct cpu_group *grp)
5807 if (grp->cg_children == 0)
5810 MPASS(grp->cg_child);
5811 for (i = 0; i < grp->cg_children; i++) {
5812 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5820 * Find the nth "close" core to the specified core
5821 * "close" is defined as the deepest level that shares
5822 * at least an L2 cache. With threads, this will be
5823 * threads on the same core. If the shared cache is L3
5824 * or higher, simply returns the same core.
5827 find_close_core(int cpu, int core_offset)
5829 struct cpu_group *grp;
5838 while ((i = find_child_with_core(cpu, grp)) != -1) {
5839 /* If the child only has one cpu, don't descend */
5840 if (grp->cg_child[i].cg_count <= 1)
5842 grp = &grp->cg_child[i];
5845 /* If they don't share at least an L2 cache, use the same CPU */
5846 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5850 CPU_COPY(&grp->cg_mask, &cs);
5852 /* Add the selected CPU offset to core offset. */
5853 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5854 if (fcpu - 1 == cpu)
5856 CPU_CLR(fcpu - 1, &cs);
5862 CPU_COPY(&grp->cg_mask, &cs);
5863 for (i = core_offset % grp->cg_count; i > 0; i--) {
5864 MPASS(CPU_FFS(&cs));
5865 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5867 MPASS(CPU_FFS(&cs));
5868 return CPU_FFS(&cs) - 1;
5872 find_close_core(int cpu, int core_offset __unused)
5879 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5883 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5884 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5885 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5887 case IFLIB_INTR_RXTX:
5888 /* RX queues get the specified core */
5889 return qid / CPU_COUNT(&ctx->ifc_cpus);
5895 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5896 #define find_close_core(cpuid, tid) CPU_FIRST()
5897 #define find_nth(ctx, gid) CPU_FIRST()
5900 /* Just to avoid copy/paste */
5902 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5903 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5907 int co, cpuid, err, tid;
5910 co = ctx->ifc_sysctl_core_offset;
5911 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5912 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5913 cpuid = find_nth(ctx, qid + co);
5914 tid = get_core_offset(ctx, type, qid);
5916 device_printf(dev, "get_core_offset failed\n");
5917 return (EOPNOTSUPP);
5919 cpuid = find_close_core(cpuid, tid);
5920 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5923 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5927 if (cpuid > ctx->ifc_cpuid_highest)
5928 ctx->ifc_cpuid_highest = cpuid;
5934 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5935 iflib_intr_type_t type, driver_filter_t *filter,
5936 void *filter_arg, int qid, const char *name)
5939 struct grouptask *gtask;
5940 struct taskqgroup *tqg;
5941 iflib_filter_info_t info;
5944 driver_filter_t *intr_fast;
5947 info = &ctx->ifc_filter_info;
5951 /* XXX merge tx/rx for netmap? */
5953 q = &ctx->ifc_txqs[qid];
5954 info = &ctx->ifc_txqs[qid].ift_filter_info;
5955 gtask = &ctx->ifc_txqs[qid].ift_task;
5956 tqg = qgroup_if_io_tqg;
5958 intr_fast = iflib_fast_intr;
5959 GROUPTASK_INIT(gtask, 0, fn, q);
5960 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5963 q = &ctx->ifc_rxqs[qid];
5964 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5965 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5966 tqg = qgroup_if_io_tqg;
5968 intr_fast = iflib_fast_intr;
5969 GROUPTASK_INIT(gtask, 0, fn, q);
5971 case IFLIB_INTR_RXTX:
5972 q = &ctx->ifc_rxqs[qid];
5973 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5974 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5975 tqg = qgroup_if_io_tqg;
5977 intr_fast = iflib_fast_intr_rxtx;
5978 GROUPTASK_INIT(gtask, 0, fn, q);
5980 case IFLIB_INTR_ADMIN:
5983 info = &ctx->ifc_filter_info;
5984 gtask = &ctx->ifc_admin_task;
5985 tqg = qgroup_if_config_tqg;
5986 fn = _task_fn_admin;
5987 intr_fast = iflib_fast_intr_ctx;
5990 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5995 info->ifi_filter = filter;
5996 info->ifi_filter_arg = filter_arg;
5997 info->ifi_task = gtask;
6001 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6003 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6006 if (type == IFLIB_INTR_ADMIN)
6010 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6015 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6022 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6024 struct grouptask *gtask;
6025 struct taskqgroup *tqg;
6032 q = &ctx->ifc_txqs[qid];
6033 gtask = &ctx->ifc_txqs[qid].ift_task;
6034 tqg = qgroup_if_io_tqg;
6038 q = &ctx->ifc_rxqs[qid];
6039 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6040 tqg = qgroup_if_io_tqg;
6043 case IFLIB_INTR_IOV:
6045 gtask = &ctx->ifc_vflr_task;
6046 tqg = qgroup_if_config_tqg;
6050 panic("unknown net intr type");
6052 GROUPTASK_INIT(gtask, 0, fn, q);
6054 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6057 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6060 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6065 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6069 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6072 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6073 rman_get_rid(irq->ii_res), irq->ii_res);
6077 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6079 iflib_txq_t txq = ctx->ifc_txqs;
6080 iflib_rxq_t rxq = ctx->ifc_rxqs;
6081 if_irq_t irq = &ctx->ifc_legacy_irq;
6082 iflib_filter_info_t info;
6084 struct grouptask *gtask;
6085 struct resource *res;
6086 struct taskqgroup *tqg;
6092 q = &ctx->ifc_rxqs[0];
6093 info = &rxq[0].ifr_filter_info;
6094 gtask = &rxq[0].ifr_task;
6095 tqg = qgroup_if_io_tqg;
6098 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6100 ctx->ifc_flags |= IFC_LEGACY;
6101 info->ifi_filter = filter;
6102 info->ifi_filter_arg = filter_arg;
6103 info->ifi_task = gtask;
6104 info->ifi_ctx = rx_only ? ctx : q;
6107 /* We allocate a single interrupt resource */
6108 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6109 iflib_fast_intr_rxtx, NULL, info, name);
6112 GROUPTASK_INIT(gtask, 0, fn, q);
6114 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6116 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6117 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6123 iflib_led_create(if_ctx_t ctx)
6126 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6127 device_get_nameunit(ctx->ifc_dev));
6131 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6134 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6138 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6141 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6145 iflib_admin_intr_deferred(if_ctx_t ctx)
6148 struct grouptask *gtask;
6150 gtask = &ctx->ifc_admin_task;
6151 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6154 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6158 iflib_iov_intr_deferred(if_ctx_t ctx)
6161 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6165 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6168 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6173 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6177 GROUPTASK_INIT(gtask, 0, fn, ctx);
6178 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6183 iflib_config_gtask_deinit(struct grouptask *gtask)
6186 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6190 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6192 if_t ifp = ctx->ifc_ifp;
6193 iflib_txq_t txq = ctx->ifc_txqs;
6195 if_setbaudrate(ifp, baudrate);
6196 if (baudrate >= IF_Gbps(10)) {
6198 ctx->ifc_flags |= IFC_PREFETCH;
6201 /* If link down, disable watchdog */
6202 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6203 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6204 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6206 ctx->ifc_link_state = link_state;
6207 if_link_state_change(ifp, link_state);
6211 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6215 int credits_pre = txq->ift_cidx_processed;
6218 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6219 BUS_DMASYNC_POSTREAD);
6220 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6223 txq->ift_processed += credits;
6224 txq->ift_cidx_processed += credits;
6226 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6227 if (txq->ift_cidx_processed >= txq->ift_size)
6228 txq->ift_cidx_processed -= txq->ift_size;
6233 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6238 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6239 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6240 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6241 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6246 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6247 const char *description, if_int_delay_info_t info,
6248 int offset, int value)
6250 info->iidi_ctx = ctx;
6251 info->iidi_offset = offset;
6252 info->iidi_value = value;
6253 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6254 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6255 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6256 info, 0, iflib_sysctl_int_delay, "I", description);
6260 iflib_ctx_lock_get(if_ctx_t ctx)
6263 return (&ctx->ifc_ctx_sx);
6267 iflib_msix_init(if_ctx_t ctx)
6269 device_t dev = ctx->ifc_dev;
6270 if_shared_ctx_t sctx = ctx->ifc_sctx;
6271 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6272 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6273 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6275 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6276 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6279 device_printf(dev, "msix_init qsets capped at %d\n",
6280 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6282 /* Override by tuneable */
6283 if (scctx->isc_disable_msix)
6286 /* First try MSI-X */
6287 if ((msgs = pci_msix_count(dev)) == 0) {
6289 device_printf(dev, "MSI-X not supported or disabled\n");
6293 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6295 * bar == -1 => "trust me I know what I'm doing"
6296 * Some drivers are for hardware that is so shoddily
6297 * documented that no one knows which bars are which
6298 * so the developer has to map all bars. This hack
6299 * allows shoddy garbage to use MSI-X in this framework.
6302 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6303 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6304 if (ctx->ifc_msix_mem == NULL) {
6305 device_printf(dev, "Unable to map MSI-X table\n");
6310 admincnt = sctx->isc_admin_intrcnt;
6312 /* use only 1 qset in debug mode */
6313 queuemsgs = min(msgs - admincnt, 1);
6315 queuemsgs = msgs - admincnt;
6318 queues = imin(queuemsgs, rss_getnumbuckets());
6322 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6325 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6326 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6328 /* If we're doing RSS, clamp at the number of RSS buckets */
6329 if (queues > rss_getnumbuckets())
6330 queues = rss_getnumbuckets();
6332 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6333 rx_queues = iflib_num_rx_queues;
6337 if (rx_queues > scctx->isc_nrxqsets)
6338 rx_queues = scctx->isc_nrxqsets;
6341 * We want this to be all logical CPUs by default
6343 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6344 tx_queues = iflib_num_tx_queues;
6346 tx_queues = mp_ncpus;
6348 if (tx_queues > scctx->isc_ntxqsets)
6349 tx_queues = scctx->isc_ntxqsets;
6351 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6353 if (tx_queues != rx_queues)
6355 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6356 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6358 tx_queues = min(rx_queues, tx_queues);
6359 rx_queues = min(rx_queues, tx_queues);
6362 vectors = rx_queues + admincnt;
6363 if (msgs < vectors) {
6365 "insufficient number of MSI-X vectors "
6366 "(supported %d, need %d)\n", msgs, vectors);
6370 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6373 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6374 if (vectors != msgs) {
6376 "Unable to allocate sufficient MSI-X vectors "
6377 "(got %d, need %d)\n", vectors, msgs);
6378 pci_release_msi(dev);
6380 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6382 ctx->ifc_msix_mem = NULL;
6386 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6388 scctx->isc_vectors = vectors;
6389 scctx->isc_nrxqsets = rx_queues;
6390 scctx->isc_ntxqsets = tx_queues;
6391 scctx->isc_intr = IFLIB_INTR_MSIX;
6396 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6399 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6401 ctx->ifc_msix_mem = NULL;
6406 vectors = pci_msi_count(dev);
6407 scctx->isc_nrxqsets = 1;
6408 scctx->isc_ntxqsets = 1;
6409 scctx->isc_vectors = vectors;
6410 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6411 device_printf(dev,"Using an MSI interrupt\n");
6412 scctx->isc_intr = IFLIB_INTR_MSI;
6414 scctx->isc_vectors = 1;
6415 device_printf(dev,"Using a Legacy interrupt\n");
6416 scctx->isc_intr = IFLIB_INTR_LEGACY;
6422 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6425 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6428 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6430 const char *ring_state = "UNKNOWN";
6433 rc = sysctl_wire_old_buffer(req, 0);
6437 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6442 ring_state = ring_states[state[3]];
6444 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6445 state[0], state[1], state[2], ring_state);
6446 rc = sbuf_finish(sb);
6451 enum iflib_ndesc_handler {
6457 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6459 if_ctx_t ctx = (void *)arg1;
6460 enum iflib_ndesc_handler type = arg2;
6461 char buf[256] = {0};
6468 case IFLIB_NTXD_HANDLER:
6469 ndesc = ctx->ifc_sysctl_ntxds;
6471 nqs = ctx->ifc_sctx->isc_ntxqs;
6473 case IFLIB_NRXD_HANDLER:
6474 ndesc = ctx->ifc_sysctl_nrxds;
6476 nqs = ctx->ifc_sctx->isc_nrxqs;
6479 printf("%s: unhandled type\n", __func__);
6485 for (i=0; i<8; i++) {
6490 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6493 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6494 if (rc || req->newptr == NULL)
6497 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6498 i++, p = strsep(&next, " ,")) {
6499 ndesc[i] = strtoul(p, NULL, 10);
6505 #define NAME_BUFLEN 32
6507 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6509 device_t dev = iflib_get_dev(ctx);
6510 struct sysctl_oid_list *child, *oid_list;
6511 struct sysctl_ctx_list *ctx_list;
6512 struct sysctl_oid *node;
6514 ctx_list = device_get_sysctl_ctx(dev);
6515 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6516 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6517 CTLFLAG_RD, NULL, "IFLIB fields");
6518 oid_list = SYSCTL_CHILDREN(node);
6520 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6521 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6524 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6525 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6526 "# of txqs to use, 0 => use default #");
6527 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6528 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6529 "# of rxqs to use, 0 => use default #");
6530 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6531 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6532 "permit #txq != #rxq");
6533 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6534 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6535 "disable MSI-X (default 0)");
6536 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6537 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6538 "set the RX budget");
6539 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6540 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6541 "cause TX to abdicate instead of running to completion");
6542 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6543 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6544 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6545 "offset to start using cores at");
6546 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6547 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6548 "use separate cores for TX and RX");
6550 /* XXX change for per-queue sizes */
6551 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6552 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6553 mp_ndesc_handler, "A",
6554 "list of # of TX descriptors to use, 0 = use default #");
6555 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6556 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6557 mp_ndesc_handler, "A",
6558 "list of # of RX descriptors to use, 0 = use default #");
6562 iflib_add_device_sysctl_post(if_ctx_t ctx)
6564 if_shared_ctx_t sctx = ctx->ifc_sctx;
6565 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6566 device_t dev = iflib_get_dev(ctx);
6567 struct sysctl_oid_list *child;
6568 struct sysctl_ctx_list *ctx_list;
6573 char namebuf[NAME_BUFLEN];
6575 struct sysctl_oid *queue_node, *fl_node, *node;
6576 struct sysctl_oid_list *queue_list, *fl_list;
6577 ctx_list = device_get_sysctl_ctx(dev);
6579 node = ctx->ifc_sysctl_node;
6580 child = SYSCTL_CHILDREN(node);
6582 if (scctx->isc_ntxqsets > 100)
6584 else if (scctx->isc_ntxqsets > 10)
6588 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6589 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6590 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6591 CTLFLAG_RD, NULL, "Queue Name");
6592 queue_list = SYSCTL_CHILDREN(queue_node);
6594 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6596 &txq->ift_dequeued, "total mbufs freed");
6597 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6599 &txq->ift_enqueued, "total mbufs enqueued");
6601 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6603 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6604 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6606 &txq->ift_pullups, "# of times m_pullup was called");
6607 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6609 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6610 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6612 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6613 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6615 &txq->ift_map_failed, "# of times DMA map failed");
6616 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6618 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6619 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6621 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6622 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6624 &txq->ift_pidx, 1, "Producer Index");
6625 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6627 &txq->ift_cidx, 1, "Consumer Index");
6628 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6630 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6631 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6633 &txq->ift_in_use, 1, "descriptors in use");
6634 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6636 &txq->ift_processed, "descriptors procesed for clean");
6637 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6639 &txq->ift_cleaned, "total cleaned");
6640 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6641 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6642 0, mp_ring_state_handler, "A", "soft ring state");
6643 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6644 CTLFLAG_RD, &txq->ift_br->enqueues,
6645 "# of enqueues to the mp_ring for this queue");
6646 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6647 CTLFLAG_RD, &txq->ift_br->drops,
6648 "# of drops in the mp_ring for this queue");
6649 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6650 CTLFLAG_RD, &txq->ift_br->starts,
6651 "# of normal consumer starts in the mp_ring for this queue");
6652 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6653 CTLFLAG_RD, &txq->ift_br->stalls,
6654 "# of consumer stalls in the mp_ring for this queue");
6655 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6656 CTLFLAG_RD, &txq->ift_br->restarts,
6657 "# of consumer restarts in the mp_ring for this queue");
6658 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6659 CTLFLAG_RD, &txq->ift_br->abdications,
6660 "# of consumer abdications in the mp_ring for this queue");
6663 if (scctx->isc_nrxqsets > 100)
6665 else if (scctx->isc_nrxqsets > 10)
6669 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6670 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6671 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6672 CTLFLAG_RD, NULL, "Queue Name");
6673 queue_list = SYSCTL_CHILDREN(queue_node);
6674 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6675 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6677 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6680 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6681 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6682 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6683 CTLFLAG_RD, NULL, "freelist Name");
6684 fl_list = SYSCTL_CHILDREN(fl_node);
6685 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6687 &fl->ifl_pidx, 1, "Producer Index");
6688 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6690 &fl->ifl_cidx, 1, "Consumer Index");
6691 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6693 &fl->ifl_credits, 1, "credits available");
6695 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6697 &fl->ifl_m_enqueued, "mbufs allocated");
6698 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6700 &fl->ifl_m_dequeued, "mbufs freed");
6701 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6703 &fl->ifl_cl_enqueued, "clusters allocated");
6704 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6706 &fl->ifl_cl_dequeued, "clusters freed");
6715 iflib_request_reset(if_ctx_t ctx)
6719 ctx->ifc_flags |= IFC_DO_RESET;
6723 #ifndef __NO_STRICT_ALIGNMENT
6724 static struct mbuf *
6725 iflib_fixup_rx(struct mbuf *m)
6729 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6730 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6731 m->m_data += ETHER_HDR_LEN;
6734 MGETHDR(n, M_NOWAIT, MT_DATA);
6739 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6740 m->m_data += ETHER_HDR_LEN;
6741 m->m_len -= ETHER_HDR_LEN;
6742 n->m_len = ETHER_HDR_LEN;
6743 M_MOVE_PKTHDR(n, m);
6752 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6756 ctx = if_getsoftc(ifp);
6758 *nrxr = NRXQSETS(ctx);
6759 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6760 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6765 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6768 if_softc_ctx_t scctx;
6773 ctx = if_getsoftc(ifp);
6774 scctx = &ctx->ifc_softc_ctx;
6777 case DEBUGNET_START:
6778 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6779 rxq = &ctx->ifc_rxqs[i];
6780 for (j = 0; j < rxq->ifr_nfl; j++) {
6782 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6785 iflib_no_tx_batch = 1;
6793 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6799 ctx = if_getsoftc(ifp);
6800 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6804 txq = &ctx->ifc_txqs[0];
6805 error = iflib_encap(txq, &m);
6807 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6812 iflib_debugnet_poll(if_t ifp, int count)
6815 if_softc_ctx_t scctx;
6819 ctx = if_getsoftc(ifp);
6820 scctx = &ctx->ifc_softc_ctx;
6822 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6826 txq = &ctx->ifc_txqs[0];
6827 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6829 for (i = 0; i < scctx->isc_nrxqsets; i++)
6830 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6833 #endif /* DEBUGNET */