2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
96 #include <dev/pci/pci_iov.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
177 int ifc_watchdog_events;
178 struct cdev *ifc_led_dev;
179 struct resource *ifc_msix_mem;
181 struct if_irq ifc_legacy_irq;
182 struct grouptask ifc_admin_task;
183 struct grouptask ifc_vflr_task;
184 struct iflib_filter_info ifc_filter_info;
185 struct ifmedia ifc_media;
187 struct sysctl_oid *ifc_sysctl_node;
188 uint16_t ifc_sysctl_ntxqs;
189 uint16_t ifc_sysctl_nrxqs;
190 uint16_t ifc_sysctl_qs_eq_override;
191 uint16_t ifc_sysctl_rx_budget;
192 uint16_t ifc_sysctl_tx_abdicate;
194 qidx_t ifc_sysctl_ntxds[8];
195 qidx_t ifc_sysctl_nrxds[8];
196 struct if_txrx ifc_txrx;
197 #define isc_txd_encap ifc_txrx.ift_txd_encap
198 #define isc_txd_flush ifc_txrx.ift_txd_flush
199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
200 #define isc_rxd_available ifc_txrx.ift_rxd_available
201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
207 eventhandler_tag ifc_vlan_attach_event;
208 eventhandler_tag ifc_vlan_detach_event;
209 uint8_t ifc_mac[ETHER_ADDR_LEN];
210 char ifc_mtx_name[16];
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (&ctx->ifc_media);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
309 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
310 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
311 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_desc_tag;
357 bus_dma_tag_t ift_tso_desc_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 16
360 char ift_mtx_name[MTX_NAME_LEN];
361 char ift_db_mtx_name[MTX_NAME_LEN];
362 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
363 #ifdef IFLIB_DIAGNOSTICS
364 uint64_t ift_cpu_exec_count[256];
366 } __aligned(CACHE_LINE_SIZE);
373 uint8_t ifl_rxd_size;
375 uint64_t ifl_m_enqueued;
376 uint64_t ifl_m_dequeued;
377 uint64_t ifl_cl_enqueued;
378 uint64_t ifl_cl_dequeued;
382 bitstr_t *ifl_rx_bitmap;
386 uint16_t ifl_buf_size;
389 iflib_rxsd_array_t ifl_sds;
392 bus_dma_tag_t ifl_desc_tag;
393 iflib_dma_info_t ifl_ifdi;
394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 } __aligned(CACHE_LINE_SIZE);
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
406 else if (pidx < cidx)
407 used = size - cidx + pidx;
408 else if (gen == 0 && pidx == cidx)
410 else if (gen == 1 && pidx == cidx)
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
420 #define IDXDIFF(head, tail, wrap) \
421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 /* If there is a separate completion queue -
425 * these are the cq cidx and pidx. Otherwise
432 uint8_t ifr_fl_offset;
438 uint8_t ifr_lro_enabled;
441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
442 struct lro_ctrl ifr_lc;
443 struct grouptask ifr_task;
444 struct iflib_filter_info ifr_filter_info;
445 iflib_dma_info_t ifr_ifdi;
447 /* dynamically allocate if any drivers need a value substantially larger than this */
448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
449 #ifdef IFLIB_DIAGNOSTICS
450 uint64_t ifr_cpu_exec_count[256];
452 } __aligned(CACHE_LINE_SIZE);
454 typedef struct if_rxsd {
456 struct mbuf **ifsd_m;
461 /* multiple of word size */
463 #define PKT_INFO_SIZE 6
464 #define RXD_INFO_SIZE 5
465 #define PKT_TYPE uint64_t
467 #define PKT_INFO_SIZE 11
468 #define RXD_INFO_SIZE 8
469 #define PKT_TYPE uint32_t
471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
474 typedef struct if_pkt_info_pad {
475 PKT_TYPE pkt_val[PKT_INFO_SIZE];
476 } *if_pkt_info_pad_t;
477 typedef struct if_rxd_info_pad {
478 PKT_TYPE rxd_val[RXD_INFO_SIZE];
479 } *if_rxd_info_pad_t;
481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
486 pkt_info_zero(if_pkt_info_t pi)
488 if_pkt_info_pad_t pi_pad;
490 pi_pad = (if_pkt_info_pad_t)pi;
491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
499 static device_method_t iflib_pseudo_methods[] = {
500 DEVMETHOD(device_attach, noop_attach),
501 DEVMETHOD(device_detach, iflib_pseudo_detach),
505 driver_t iflib_pseudodriver = {
506 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
510 rxd_info_zero(if_rxd_info_t ri)
512 if_rxd_info_pad_t ri_pad;
515 ri_pad = (if_rxd_info_pad_t)ri;
516 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
517 ri_pad->rxd_val[i] = 0;
518 ri_pad->rxd_val[i+1] = 0;
519 ri_pad->rxd_val[i+2] = 0;
520 ri_pad->rxd_val[i+3] = 0;
523 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
528 * Only allow a single packet to take up most 1/nth of the tx ring
530 #define MAX_SINGLE_PACKET_FRACTION 12
531 #define IF_BAD_DMA (bus_addr_t)-1
533 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
535 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
536 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
537 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
538 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
541 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
542 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
543 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
544 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
548 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
549 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
552 iflib_set_detach(if_ctx_t ctx)
555 ctx->ifc_flags |= IFC_IN_DETACH;
559 /* Our boot-time initialization hook */
560 static int iflib_module_event_handler(module_t, int, void *);
562 static moduledata_t iflib_moduledata = {
564 iflib_module_event_handler,
568 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
569 MODULE_VERSION(iflib, 1);
571 MODULE_DEPEND(iflib, pci, 1, 1, 1);
572 MODULE_DEPEND(iflib, ether, 1, 1, 1);
574 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
575 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
577 #ifndef IFLIB_DEBUG_COUNTERS
579 #define IFLIB_DEBUG_COUNTERS 1
581 #define IFLIB_DEBUG_COUNTERS 0
582 #endif /* !INVARIANTS */
585 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
586 "iflib driver parameters");
589 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
591 static int iflib_min_tx_latency = 0;
592 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
593 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
594 static int iflib_no_tx_batch = 0;
595 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
596 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
599 #if IFLIB_DEBUG_COUNTERS
601 static int iflib_tx_seen;
602 static int iflib_tx_sent;
603 static int iflib_tx_encap;
604 static int iflib_rx_allocs;
605 static int iflib_fl_refills;
606 static int iflib_fl_refills_large;
607 static int iflib_tx_frees;
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
610 &iflib_tx_seen, 0, "# tx mbufs seen");
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
612 &iflib_tx_sent, 0, "# tx mbufs sent");
613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
614 &iflib_tx_encap, 0, "# tx mbufs encapped");
615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
616 &iflib_tx_frees, 0, "# tx frees");
617 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
618 &iflib_rx_allocs, 0, "# rx allocations");
619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
620 &iflib_fl_refills, 0, "# refills");
621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
622 &iflib_fl_refills_large, 0, "# large refills");
625 static int iflib_txq_drain_flushing;
626 static int iflib_txq_drain_oactive;
627 static int iflib_txq_drain_notready;
629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
630 &iflib_txq_drain_flushing, 0, "# drain flushes");
631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
632 &iflib_txq_drain_oactive, 0, "# drain oactives");
633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
634 &iflib_txq_drain_notready, 0, "# drain notready");
637 static int iflib_encap_load_mbuf_fail;
638 static int iflib_encap_pad_mbuf_fail;
639 static int iflib_encap_txq_avail_fail;
640 static int iflib_encap_txd_encap_fail;
642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
643 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
645 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
647 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
649 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
651 static int iflib_task_fn_rxs;
652 static int iflib_rx_intr_enables;
653 static int iflib_fast_intrs;
654 static int iflib_rx_unavail;
655 static int iflib_rx_ctx_inactive;
656 static int iflib_rx_if_input;
657 static int iflib_rx_mbuf_null;
658 static int iflib_rxd_flush;
660 static int iflib_verbose_debug;
662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
665 &iflib_rx_intr_enables, 0, "# rx intr enables");
666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
667 &iflib_fast_intrs, 0, "# fast_intr calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
669 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
673 &iflib_rx_if_input, 0, "# times rxeof called if_input");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
675 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
677 &iflib_rxd_flush, 0, "# times rxd_flush called");
678 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
679 &iflib_verbose_debug, 0, "enable verbose debugging");
681 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
683 iflib_debug_reset(void)
685 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
686 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
687 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
688 iflib_txq_drain_notready =
689 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
690 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
691 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
693 iflib_rx_ctx_inactive = iflib_rx_if_input =
694 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
698 #define DBG_COUNTER_INC(name)
699 static void iflib_debug_reset(void) {}
702 #define IFLIB_DEBUG 0
704 static void iflib_tx_structures_free(if_ctx_t ctx);
705 static void iflib_rx_structures_free(if_ctx_t ctx);
706 static int iflib_queues_alloc(if_ctx_t ctx);
707 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
708 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
709 static int iflib_qset_structures_setup(if_ctx_t ctx);
710 static int iflib_msix_init(if_ctx_t ctx);
711 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
712 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
713 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
715 static void iflib_altq_if_start(if_t ifp);
716 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
718 static int iflib_register(if_ctx_t);
719 static void iflib_init_locked(if_ctx_t ctx);
720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
721 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
722 static void iflib_ifmp_purge(iflib_txq_t txq);
723 static void _iflib_pre_assert(if_softc_ctx_t scctx);
724 static void iflib_if_init_locked(if_ctx_t ctx);
725 static void iflib_free_intr_mem(if_ctx_t ctx);
726 #ifndef __NO_STRICT_ALIGNMENT
727 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
730 NETDUMP_DEFINE(iflib);
733 #include <sys/selinfo.h>
734 #include <net/netmap.h>
735 #include <dev/netmap/netmap_kern.h>
737 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
742 * device-specific sysctl variables:
744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
745 * During regular operations the CRC is stripped, but on some
746 * hardware reception of frames not multiple of 64 is slower,
747 * so using crcstrip=0 helps in benchmarks.
749 * iflib_rx_miss, iflib_rx_miss_bufs:
750 * count packets that might be missed due to lost interrupts.
752 SYSCTL_DECL(_dev_netmap);
754 * The xl driver by default strips CRCs and we do not override it.
757 int iflib_crcstrip = 1;
758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
761 int iflib_rx_miss, iflib_rx_miss_bufs;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
768 * Register/unregister. We are already under netmap lock.
769 * Only called on the first register or the last unregister.
772 iflib_netmap_register(struct netmap_adapter *na, int onoff)
774 struct ifnet *ifp = na->ifp;
775 if_ctx_t ctx = ifp->if_softc;
779 IFDI_INTR_DISABLE(ctx);
781 /* Tell the stack that the interface is no longer active */
782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
787 /* enable or disable flags and callbacks in na and ifp */
789 nm_set_native_flags(na);
791 nm_clear_native_flags(na);
794 iflib_init_locked(ctx);
795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
798 nm_clear_native_flags(na);
804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
806 struct netmap_adapter *na = kring->na;
807 u_int const lim = kring->nkr_num_slots - 1;
808 u_int head = kring->rhead;
809 struct netmap_ring *ring = kring->ring;
811 struct if_rxd_update iru;
812 if_ctx_t ctx = rxq->ifr_ctx;
813 iflib_fl_t fl = &rxq->ifr_fl[0];
814 uint32_t refill_pidx, nic_i;
815 #if IFLIB_DEBUG_COUNTERS
819 if (nm_i == head && __predict_true(!init))
821 iru_init(&iru, rxq, 0 /* flid */);
822 map = fl->ifl_sds.ifsd_map;
823 refill_pidx = netmap_idx_k2n(kring, nm_i);
825 * IMPORTANT: we must leave one free slot in the ring,
826 * so move head back by one unit
828 head = nm_prev(head, lim);
830 DBG_COUNTER_INC(fl_refills);
831 while (nm_i != head) {
832 #if IFLIB_DEBUG_COUNTERS
834 DBG_COUNTER_INC(fl_refills_large);
836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
837 struct netmap_slot *slot = &ring->slot[nm_i];
838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
839 uint32_t nic_i_dma = refill_pidx;
840 nic_i = netmap_idx_k2n(kring, nm_i);
842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
845 return netmap_ring_reinit(kring);
847 fl->ifl_vm_addrs[tmp_pidx] = addr;
848 if (__predict_false(init) && map) {
849 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
850 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
851 /* buffer has changed, reload map */
852 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
854 slot->flags &= ~NS_BUF_CHANGED;
856 nm_i = nm_next(nm_i, lim);
857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
861 iru.iru_pidx = refill_pidx;
862 iru.iru_count = tmp_pidx+1;
863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
869 for (int n = 0; n < iru.iru_count; n++) {
870 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
871 BUS_DMASYNC_PREREAD);
872 /* XXX - change this to not use the netmap func*/
873 nic_i_dma = nm_next(nic_i_dma, lim);
877 kring->nr_hwcur = head;
880 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
882 if (__predict_true(nic_i != UINT_MAX)) {
883 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
884 DBG_COUNTER_INC(rxd_flush);
890 * Reconcile kernel and user view of the transmit ring.
892 * All information is in the kring.
893 * Userspace wants to send packets up to the one before kring->rhead,
894 * kernel knows kring->nr_hwcur is the first unsent packet.
896 * Here we push packets out (as many as possible), and possibly
897 * reclaim buffers from previously completed transmission.
899 * The caller (netmap) guarantees that there is only one instance
900 * running at any time. Any interference with other driver
901 * methods should be handled by the individual drivers.
904 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
906 struct netmap_adapter *na = kring->na;
907 struct ifnet *ifp = na->ifp;
908 struct netmap_ring *ring = kring->ring;
909 u_int nm_i; /* index into the netmap kring */
910 u_int nic_i; /* index into the NIC ring */
912 u_int const lim = kring->nkr_num_slots - 1;
913 u_int const head = kring->rhead;
914 struct if_pkt_info pi;
917 * interrupts on every tx packet are expensive so request
918 * them every half ring, or where NS_REPORT is set
920 u_int report_frequency = kring->nkr_num_slots >> 1;
921 /* device-specific */
922 if_ctx_t ctx = ifp->if_softc;
923 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
925 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
926 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
930 * First part: process new packets to send.
931 * nm_i is the current index in the netmap kring,
932 * nic_i is the corresponding index in the NIC ring.
934 * If we have packets to send (nm_i != head)
935 * iterate over the netmap ring, fetch length and update
936 * the corresponding slot in the NIC ring. Some drivers also
937 * need to update the buffer's physical address in the NIC slot
938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
940 * The netmap_reload_map() calls is especially expensive,
941 * even when (as in this case) the tag is 0, so do only
942 * when the buffer has actually changed.
944 * If possible do not set the report/intr bit on all slots,
945 * but only a few times per ring or when NS_REPORT is set.
947 * Finally, on 10G and faster drivers, it might be useful
948 * to prefetch the next slot and txr entry.
951 nm_i = kring->nr_hwcur;
952 if (nm_i != head) { /* we have new packets to send */
954 pi.ipi_segs = txq->ift_segs;
955 pi.ipi_qsidx = kring->ring_id;
956 nic_i = netmap_idx_k2n(kring, nm_i);
958 __builtin_prefetch(&ring->slot[nm_i]);
959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
960 if (txq->ift_sds.ifsd_map)
961 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
963 for (n = 0; nm_i != head; n++) {
964 struct netmap_slot *slot = &ring->slot[nm_i];
965 u_int len = slot->len;
967 void *addr = PNMB(na, slot, &paddr);
968 int flags = (slot->flags & NS_REPORT ||
969 nic_i == 0 || nic_i == report_frequency) ?
972 /* device-specific */
974 pi.ipi_segs[0].ds_addr = paddr;
975 pi.ipi_segs[0].ds_len = len;
979 pi.ipi_flags = flags;
981 /* Fill the slot in the NIC ring. */
982 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
983 DBG_COUNTER_INC(tx_encap);
985 /* prefetch for next round */
986 __builtin_prefetch(&ring->slot[nm_i + 1]);
987 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
988 if (txq->ift_sds.ifsd_map) {
989 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
991 NM_CHECK_ADDR_LEN(na, addr, len);
993 if (slot->flags & NS_BUF_CHANGED) {
994 /* buffer has changed, reload map */
995 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
997 /* make sure changes to the buffer are synced */
998 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
999 BUS_DMASYNC_PREWRITE);
1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1002 nm_i = nm_next(nm_i, lim);
1003 nic_i = nm_next(nic_i, lim);
1005 kring->nr_hwcur = nm_i;
1007 /* synchronize the NIC ring */
1008 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1011 /* (re)start the tx unit up to slot nic_i (excluded) */
1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1016 * Second part: reclaim buffers for completed transmissions.
1018 * If there are unclaimed buffers, attempt to reclaim them.
1019 * If none are reclaimed, and TX IRQs are not in use, do an initial
1020 * minimal delay, then trigger the tx handler which will spin in the
1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1024 if (iflib_tx_credits_update(ctx, txq)) {
1025 /* some tx completed, increment avail */
1026 nic_i = txq->ift_cidx_processed;
1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1033 iflib_timer, txq, txq->ift_timer.c_cpu);
1039 * Reconcile kernel and user view of the receive ring.
1040 * Same as for the txsync, this routine must be efficient.
1041 * The caller guarantees a single invocations, but races against
1042 * the rest of the driver should be handled here.
1044 * On call, kring->rhead is the first packet that userspace wants
1045 * to keep, and kring->rcur is the wakeup point.
1046 * The kernel has previously reported packets up to kring->rtail.
1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1049 * of whether or not we received an interrupt.
1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1054 struct netmap_adapter *na = kring->na;
1055 struct netmap_ring *ring = kring->ring;
1056 uint32_t nm_i; /* index into the netmap ring */
1057 uint32_t nic_i; /* index into the NIC ring */
1059 u_int const lim = kring->nkr_num_slots - 1;
1060 u_int const head = kring->rhead;
1061 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1062 struct if_rxd_info ri;
1064 struct ifnet *ifp = na->ifp;
1065 if_ctx_t ctx = ifp->if_softc;
1066 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1067 iflib_fl_t fl = rxq->ifr_fl;
1069 return netmap_ring_reinit(kring);
1071 /* XXX check sync modes */
1072 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1073 if (fl->ifl_sds.ifsd_map == NULL)
1075 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1076 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1079 * First part: import newly received packets.
1081 * nm_i is the index of the next free slot in the netmap ring,
1082 * nic_i is the index of the next received packet in the NIC ring,
1083 * and they may differ in case if_init() has been called while
1084 * in netmap mode. For the receive ring we have
1086 * nic_i = rxr->next_check;
1087 * nm_i = kring->nr_hwtail (previous)
1089 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1091 * rxr->next_check is set to 0 on a ring reinit
1093 if (netmap_no_pendintr || force_update) {
1094 int crclen = iflib_crcstrip ? 0 : 4;
1097 for (i = 0; i < rxq->ifr_nfl; i++) {
1098 fl = &rxq->ifr_fl[i];
1099 nic_i = fl->ifl_cidx;
1100 nm_i = netmap_idx_n2k(kring, nic_i);
1101 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1102 for (n = 0; avail > 0; n++, avail--) {
1104 ri.iri_frags = rxq->ifr_frags;
1105 ri.iri_qsidx = kring->ring_id;
1106 ri.iri_ifp = ctx->ifc_ifp;
1107 ri.iri_cidx = nic_i;
1109 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1110 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1111 ring->slot[nm_i].flags = 0;
1112 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1113 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1114 nm_i = nm_next(nm_i, lim);
1115 nic_i = nm_next(nic_i, lim);
1117 if (n) { /* update the state variables */
1118 if (netmap_no_pendintr && !force_update) {
1121 iflib_rx_miss_bufs += n;
1123 fl->ifl_cidx = nic_i;
1124 kring->nr_hwtail = nm_i;
1126 kring->nr_kflags &= ~NKR_PENDINTR;
1130 * Second part: skip past packets that userspace has released.
1131 * (kring->nr_hwcur to head excluded),
1132 * and make the buffers available for reception.
1133 * As usual nm_i is the index in the netmap ring,
1134 * nic_i is the index in the NIC ring, and
1135 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1137 /* XXX not sure how this will work with multiple free lists */
1138 nm_i = kring->nr_hwcur;
1140 return (netmap_fl_refill(rxq, kring, nm_i, false));
1144 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1146 struct ifnet *ifp = na->ifp;
1147 if_ctx_t ctx = ifp->if_softc;
1151 IFDI_INTR_ENABLE(ctx);
1153 IFDI_INTR_DISABLE(ctx);
1160 iflib_netmap_attach(if_ctx_t ctx)
1162 struct netmap_adapter na;
1163 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1165 bzero(&na, sizeof(na));
1167 na.ifp = ctx->ifc_ifp;
1168 na.na_flags = NAF_BDG_MAYSLEEP;
1169 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1170 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1172 na.num_tx_desc = scctx->isc_ntxd[0];
1173 na.num_rx_desc = scctx->isc_nrxd[0];
1174 na.nm_txsync = iflib_netmap_txsync;
1175 na.nm_rxsync = iflib_netmap_rxsync;
1176 na.nm_register = iflib_netmap_register;
1177 na.nm_intr = iflib_netmap_intr;
1178 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1179 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1180 return (netmap_attach(&na));
1184 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1186 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1187 struct netmap_slot *slot;
1189 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1192 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1195 * In netmap mode, set the map for the packet buffer.
1196 * NOTE: Some drivers (not this one) also need to set
1197 * the physical buffer address in the NIC ring.
1198 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1199 * netmap slot index, si
1201 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1202 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1207 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1209 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1210 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1211 struct netmap_slot *slot;
1214 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1217 nm_i = netmap_idx_n2k(kring, 0);
1218 netmap_fl_refill(rxq, kring, nm_i, true);
1222 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1224 struct netmap_kring *kring;
1226 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1228 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1229 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1230 netmap_tx_irq(ctx->ifc_ifp, txqid);
1231 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1235 *reset_on = hz / 1000;
1240 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1243 #define iflib_netmap_txq_init(ctx, txq)
1244 #define iflib_netmap_rxq_init(ctx, rxq)
1245 #define iflib_netmap_detach(ifp)
1247 #define iflib_netmap_attach(ctx) (0)
1248 #define netmap_rx_irq(ifp, qid, budget) (0)
1249 #define netmap_tx_irq(ifp, qid) do {} while (0)
1250 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1254 #if defined(__i386__) || defined(__amd64__)
1255 static __inline void
1258 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1260 static __inline void
1261 prefetch2cachelines(void *x)
1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1264 #if (CACHE_LINE_SIZE < 128)
1265 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1270 #define prefetch2cachelines(x)
1274 iflib_gen_mac(if_ctx_t ctx)
1278 char uuid[HOSTUUIDLEN+1];
1279 char buf[HOSTUUIDLEN+16];
1281 unsigned char digest[16];
1285 uuid[HOSTUUIDLEN] = 0;
1286 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1287 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1289 * Generate a pseudo-random, deterministic MAC
1290 * address based on the UUID and unit number.
1291 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1294 MD5Update(&mdctx, buf, strlen(buf));
1295 MD5Final(digest, &mdctx);
1306 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1310 fl = &rxq->ifr_fl[flid];
1311 iru->iru_paddrs = fl->ifl_bus_addrs;
1312 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1313 iru->iru_idxs = fl->ifl_rxd_idxs;
1314 iru->iru_qsidx = rxq->ifr_id;
1315 iru->iru_buf_size = fl->ifl_buf_size;
1316 iru->iru_flidx = fl->ifl_id;
1320 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1324 *(bus_addr_t *) arg = segs[0].ds_addr;
1328 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1331 device_t dev = ctx->ifc_dev;
1333 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1334 align, 0, /* alignment, bounds */
1335 BUS_SPACE_MAXADDR, /* lowaddr */
1336 BUS_SPACE_MAXADDR, /* highaddr */
1337 NULL, NULL, /* filter, filterarg */
1340 size, /* maxsegsize */
1341 BUS_DMA_ALLOCNOW, /* flags */
1342 NULL, /* lockfunc */
1347 "%s: bus_dma_tag_create failed: %d\n",
1352 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1353 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1356 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1357 __func__, (uintmax_t)size, err);
1361 dma->idi_paddr = IF_BAD_DMA;
1362 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1363 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1364 if (err || dma->idi_paddr == IF_BAD_DMA) {
1366 "%s: bus_dmamap_load failed: %d\n",
1371 dma->idi_size = size;
1375 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1377 bus_dma_tag_destroy(dma->idi_tag);
1379 dma->idi_tag = NULL;
1385 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1387 if_shared_ctx_t sctx = ctx->ifc_sctx;
1389 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1391 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1395 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1398 iflib_dma_info_t *dmaiter;
1401 for (i = 0; i < count; i++, dmaiter++) {
1402 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1406 iflib_dma_free_multi(dmalist, i);
1411 iflib_dma_free(iflib_dma_info_t dma)
1413 if (dma->idi_tag == NULL)
1415 if (dma->idi_paddr != IF_BAD_DMA) {
1416 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1417 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1418 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1419 dma->idi_paddr = IF_BAD_DMA;
1421 if (dma->idi_vaddr != NULL) {
1422 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1423 dma->idi_vaddr = NULL;
1425 bus_dma_tag_destroy(dma->idi_tag);
1426 dma->idi_tag = NULL;
1430 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1433 iflib_dma_info_t *dmaiter = dmalist;
1435 for (i = 0; i < count; i++, dmaiter++)
1436 iflib_dma_free(*dmaiter);
1439 #ifdef EARLY_AP_STARTUP
1440 static const int iflib_started = 1;
1443 * We used to abuse the smp_started flag to decide if the queues have been
1444 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1445 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1446 * is set. Run a SYSINIT() strictly after that to just set a usable
1450 static int iflib_started;
1453 iflib_record_started(void *arg)
1458 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1459 iflib_record_started, NULL);
1463 iflib_fast_intr(void *arg)
1465 iflib_filter_info_t info = arg;
1466 struct grouptask *gtask = info->ifi_task;
1468 return (FILTER_HANDLED);
1470 DBG_COUNTER_INC(fast_intrs);
1471 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1472 return (FILTER_HANDLED);
1474 GROUPTASK_ENQUEUE(gtask);
1475 return (FILTER_HANDLED);
1479 iflib_fast_intr_rxtx(void *arg)
1481 iflib_filter_info_t info = arg;
1482 struct grouptask *gtask = info->ifi_task;
1483 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1484 if_ctx_t ctx = NULL;;
1488 return (FILTER_HANDLED);
1490 DBG_COUNTER_INC(fast_intrs);
1491 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1492 return (FILTER_HANDLED);
1494 MPASS(rxq->ifr_ntxqirq);
1495 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1496 qidx_t txqid = rxq->ifr_txqid[i];
1500 bus_dmamap_sync(rxq->ifr_ifdi->idi_tag, rxq->ifr_ifdi->idi_map,
1501 BUS_DMASYNC_POSTREAD);
1502 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1503 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1506 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1508 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1509 cidx = rxq->ifr_cq_cidx;
1511 cidx = rxq->ifr_fl[0].ifl_cidx;
1512 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1513 GROUPTASK_ENQUEUE(gtask);
1515 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1516 DBG_COUNTER_INC(rx_intr_enables);
1518 return (FILTER_HANDLED);
1523 iflib_fast_intr_ctx(void *arg)
1525 iflib_filter_info_t info = arg;
1526 struct grouptask *gtask = info->ifi_task;
1529 return (FILTER_HANDLED);
1531 DBG_COUNTER_INC(fast_intrs);
1532 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1533 return (FILTER_HANDLED);
1535 GROUPTASK_ENQUEUE(gtask);
1536 return (FILTER_HANDLED);
1540 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1541 driver_filter_t filter, driver_intr_t handler, void *arg,
1545 struct resource *res;
1547 device_t dev = ctx->ifc_dev;
1550 if (ctx->ifc_flags & IFC_LEGACY)
1551 flags |= RF_SHAREABLE;
1554 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1557 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1561 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1562 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1563 filter, handler, arg, &tag);
1566 "failed to setup interrupt for rid %d, name %s: %d\n",
1567 rid, name ? name : "unknown", rc);
1570 bus_describe_intr(dev, res, tag, "%s", name);
1577 /*********************************************************************
1579 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1580 * the information needed to transmit a packet on the wire. This is
1581 * called only once at attach, setup is done every reset.
1583 **********************************************************************/
1586 iflib_txsd_alloc(iflib_txq_t txq)
1588 if_ctx_t ctx = txq->ift_ctx;
1589 if_shared_ctx_t sctx = ctx->ifc_sctx;
1590 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1591 device_t dev = ctx->ifc_dev;
1592 bus_size_t tsomaxsize;
1593 int err, nsegments, ntsosegments;
1596 nsegments = scctx->isc_tx_nsegments;
1597 ntsosegments = scctx->isc_tx_tso_segments_max;
1598 tsomaxsize = scctx->isc_tx_tso_size_max;
1599 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1600 tsomaxsize += sizeof(struct ether_vlan_header);
1601 MPASS(scctx->isc_ntxd[0] > 0);
1602 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1603 MPASS(nsegments > 0);
1604 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1605 MPASS(ntsosegments > 0);
1606 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1610 * Setup DMA descriptor areas.
1612 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1613 1, 0, /* alignment, bounds */
1614 BUS_SPACE_MAXADDR, /* lowaddr */
1615 BUS_SPACE_MAXADDR, /* highaddr */
1616 NULL, NULL, /* filter, filterarg */
1617 sctx->isc_tx_maxsize, /* maxsize */
1618 nsegments, /* nsegments */
1619 sctx->isc_tx_maxsegsize, /* maxsegsize */
1621 NULL, /* lockfunc */
1622 NULL, /* lockfuncarg */
1623 &txq->ift_desc_tag))) {
1624 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1625 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1626 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1629 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1630 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1631 1, 0, /* alignment, bounds */
1632 BUS_SPACE_MAXADDR, /* lowaddr */
1633 BUS_SPACE_MAXADDR, /* highaddr */
1634 NULL, NULL, /* filter, filterarg */
1635 tsomaxsize, /* maxsize */
1636 ntsosegments, /* nsegments */
1637 sctx->isc_tso_maxsegsize,/* maxsegsize */
1639 NULL, /* lockfunc */
1640 NULL, /* lockfuncarg */
1641 &txq->ift_tso_desc_tag))) {
1642 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1645 if (!(txq->ift_sds.ifsd_m =
1646 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1647 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1648 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1653 /* Create the descriptor buffer dma maps */
1654 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1655 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1656 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1657 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1662 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1663 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1664 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1665 device_printf(dev, "Unable to allocate TSO tx_buffer "
1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1672 err = bus_dmamap_create(txq->ift_desc_tag, 0,
1673 &txq->ift_sds.ifsd_map[i]);
1675 device_printf(dev, "Unable to create TX DMA map\n");
1680 err = bus_dmamap_create(txq->ift_tso_desc_tag, 0,
1681 &txq->ift_sds.ifsd_tso_map[i]);
1683 device_printf(dev, "Unable to create TSO TX DMA map\n");
1689 /* We free all, it handles case where we are in the middle */
1690 iflib_tx_structures_free(ctx);
1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1700 if (txq->ift_sds.ifsd_map != NULL)
1701 map = txq->ift_sds.ifsd_map[i];
1703 bus_dmamap_sync(txq->ift_desc_tag, map, BUS_DMASYNC_POSTWRITE);
1704 bus_dmamap_unload(txq->ift_desc_tag, map);
1705 bus_dmamap_destroy(txq->ift_desc_tag, map);
1706 txq->ift_sds.ifsd_map[i] = NULL;
1710 if (txq->ift_sds.ifsd_tso_map != NULL)
1711 map = txq->ift_sds.ifsd_tso_map[i];
1713 bus_dmamap_sync(txq->ift_tso_desc_tag, map,
1714 BUS_DMASYNC_POSTWRITE);
1715 bus_dmamap_unload(txq->ift_tso_desc_tag, map);
1716 bus_dmamap_destroy(txq->ift_tso_desc_tag, map);
1717 txq->ift_sds.ifsd_tso_map[i] = NULL;
1722 iflib_txq_destroy(iflib_txq_t txq)
1724 if_ctx_t ctx = txq->ift_ctx;
1726 for (int i = 0; i < txq->ift_size; i++)
1727 iflib_txsd_destroy(ctx, txq, i);
1728 if (txq->ift_sds.ifsd_map != NULL) {
1729 free(txq->ift_sds.ifsd_map, M_IFLIB);
1730 txq->ift_sds.ifsd_map = NULL;
1732 if (txq->ift_sds.ifsd_tso_map != NULL) {
1733 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1734 txq->ift_sds.ifsd_tso_map = NULL;
1736 if (txq->ift_sds.ifsd_m != NULL) {
1737 free(txq->ift_sds.ifsd_m, M_IFLIB);
1738 txq->ift_sds.ifsd_m = NULL;
1740 if (txq->ift_desc_tag != NULL) {
1741 bus_dma_tag_destroy(txq->ift_desc_tag);
1742 txq->ift_desc_tag = NULL;
1744 if (txq->ift_tso_desc_tag != NULL) {
1745 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1746 txq->ift_tso_desc_tag = NULL;
1751 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1755 mp = &txq->ift_sds.ifsd_m[i];
1759 if (txq->ift_sds.ifsd_map != NULL) {
1760 bus_dmamap_sync(txq->ift_desc_tag,
1761 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1762 bus_dmamap_unload(txq->ift_desc_tag, txq->ift_sds.ifsd_map[i]);
1764 if (txq->ift_sds.ifsd_tso_map != NULL) {
1765 bus_dmamap_sync(txq->ift_tso_desc_tag,
1766 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1767 bus_dmamap_unload(txq->ift_tso_desc_tag,
1768 txq->ift_sds.ifsd_tso_map[i]);
1771 DBG_COUNTER_INC(tx_frees);
1776 iflib_txq_setup(iflib_txq_t txq)
1778 if_ctx_t ctx = txq->ift_ctx;
1779 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1780 if_shared_ctx_t sctx = ctx->ifc_sctx;
1781 iflib_dma_info_t di;
1784 /* Set number of descriptors available */
1785 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1786 /* XXX make configurable */
1787 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1790 txq->ift_cidx_processed = 0;
1791 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1792 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1794 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1795 bzero((void *)di->idi_vaddr, di->idi_size);
1797 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1798 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1799 bus_dmamap_sync(di->idi_tag, di->idi_map,
1800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1804 /*********************************************************************
1806 * Allocate memory for rx_buffer structures. Since we use one
1807 * rx_buffer per received packet, the maximum number of rx_buffer's
1808 * that we'll need is equal to the number of receive descriptors
1809 * that we've allocated.
1811 **********************************************************************/
1813 iflib_rxsd_alloc(iflib_rxq_t rxq)
1815 if_ctx_t ctx = rxq->ifr_ctx;
1816 if_shared_ctx_t sctx = ctx->ifc_sctx;
1817 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1818 device_t dev = ctx->ifc_dev;
1822 MPASS(scctx->isc_nrxd[0] > 0);
1823 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1826 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1827 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1828 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1829 1, 0, /* alignment, bounds */
1830 BUS_SPACE_MAXADDR, /* lowaddr */
1831 BUS_SPACE_MAXADDR, /* highaddr */
1832 NULL, NULL, /* filter, filterarg */
1833 sctx->isc_rx_maxsize, /* maxsize */
1834 sctx->isc_rx_nsegments, /* nsegments */
1835 sctx->isc_rx_maxsegsize, /* maxsegsize */
1837 NULL, /* lockfunc */
1841 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1845 if (!(fl->ifl_sds.ifsd_m =
1846 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1847 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1848 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1852 if (!(fl->ifl_sds.ifsd_cl =
1853 (caddr_t *) malloc(sizeof(caddr_t) *
1854 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1855 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1860 if (!(fl->ifl_sds.ifsd_ba =
1861 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1862 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1863 device_printf(dev, "Unable to allocate rx bus addr memory\n");
1868 /* Create the descriptor buffer dma maps */
1869 if (!(fl->ifl_sds.ifsd_map =
1870 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1871 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1876 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1877 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1879 device_printf(dev, "Unable to create RX buffer DMA map\n");
1887 iflib_rx_structures_free(ctx);
1893 * Internal service routines
1896 struct rxq_refill_cb_arg {
1898 bus_dma_segment_t seg;
1903 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1905 struct rxq_refill_cb_arg *cb_arg = arg;
1907 cb_arg->error = error;
1908 cb_arg->seg = segs[0];
1909 cb_arg->nseg = nseg;
1913 * rxq_refill - refill an rxq free-buffer list
1914 * @ctx: the iflib context
1915 * @rxq: the free-list to refill
1916 * @n: the number of new buffers to allocate
1918 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1919 * The caller must assure that @n does not exceed the queue's capacity.
1922 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1924 struct if_rxd_update iru;
1925 struct rxq_refill_cb_arg cb_arg;
1929 bus_dmamap_t *sd_map;
1930 bus_addr_t bus_addr, *sd_ba;
1931 int err, frag_idx, i, idx, n, pidx;
1934 sd_m = fl->ifl_sds.ifsd_m;
1935 sd_map = fl->ifl_sds.ifsd_map;
1936 sd_cl = fl->ifl_sds.ifsd_cl;
1937 sd_ba = fl->ifl_sds.ifsd_ba;
1938 pidx = fl->ifl_pidx;
1940 frag_idx = fl->ifl_fragidx;
1941 credits = fl->ifl_credits;
1946 MPASS(credits + n <= fl->ifl_size);
1948 if (pidx < fl->ifl_cidx)
1949 MPASS(pidx + n <= fl->ifl_cidx);
1950 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1951 MPASS(fl->ifl_gen == 0);
1952 if (pidx > fl->ifl_cidx)
1953 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1955 DBG_COUNTER_INC(fl_refills);
1957 DBG_COUNTER_INC(fl_refills_large);
1958 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1961 * We allocate an uninitialized mbuf + cluster, mbuf is
1962 * initialized after rx.
1964 * If the cluster is still set then we know a minimum sized packet was received
1966 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1969 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1970 MPASS(frag_idx >= 0);
1971 if ((cl = sd_cl[frag_idx]) == NULL) {
1972 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1976 MPASS(sd_map != NULL);
1977 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1978 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1980 if (err != 0 || cb_arg.error) {
1984 if (fl->ifl_zone == zone_pack)
1985 uma_zfree(fl->ifl_zone, cl);
1989 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1990 BUS_DMASYNC_PREREAD);
1991 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
1992 sd_cl[frag_idx] = cl;
1994 fl->ifl_cl_enqueued++;
1997 bus_addr = sd_ba[frag_idx];
2000 MPASS(sd_m[frag_idx] == NULL);
2001 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2005 bit_set(fl->ifl_rx_bitmap, frag_idx);
2007 fl->ifl_m_enqueued++;
2010 DBG_COUNTER_INC(rx_allocs);
2011 fl->ifl_rxd_idxs[i] = frag_idx;
2012 fl->ifl_bus_addrs[i] = bus_addr;
2013 fl->ifl_vm_addrs[i] = cl;
2016 MPASS(credits <= fl->ifl_size);
2017 if (++idx == fl->ifl_size) {
2021 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2022 iru.iru_pidx = pidx;
2024 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2028 fl->ifl_credits = credits;
2033 iru.iru_pidx = pidx;
2035 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2037 fl->ifl_credits = credits;
2039 DBG_COUNTER_INC(rxd_flush);
2040 if (fl->ifl_pidx == 0)
2041 pidx = fl->ifl_size - 1;
2043 pidx = fl->ifl_pidx - 1;
2045 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2047 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2048 fl->ifl_fragidx = frag_idx;
2051 static __inline void
2052 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2054 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2055 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2057 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2060 MPASS(fl->ifl_credits <= fl->ifl_size);
2061 MPASS(reclaimable == delta);
2063 if (reclaimable > 0)
2064 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2068 iflib_in_detach(if_ctx_t ctx)
2072 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2078 iflib_fl_bufs_free(iflib_fl_t fl)
2080 iflib_dma_info_t idi = fl->ifl_ifdi;
2081 bus_dmamap_t sd_map;
2084 for (i = 0; i < fl->ifl_size; i++) {
2085 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2086 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2088 if (*sd_cl != NULL) {
2089 sd_map = fl->ifl_sds.ifsd_map[i];
2090 bus_dmamap_sync(fl->ifl_desc_tag, sd_map,
2091 BUS_DMASYNC_POSTREAD);
2092 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2094 uma_zfree(fl->ifl_zone, *sd_cl);
2095 // XXX: Should this get moved out?
2096 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2097 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2098 if (*sd_m != NULL) {
2099 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2100 uma_zfree(zone_mbuf, *sd_m);
2103 MPASS(*sd_cl == NULL);
2104 MPASS(*sd_m == NULL);
2107 fl->ifl_m_dequeued++;
2108 fl->ifl_cl_dequeued++;
2114 for (i = 0; i < fl->ifl_size; i++) {
2115 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2116 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2120 * Reset free list values
2122 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2123 bzero(idi->idi_vaddr, idi->idi_size);
2126 /*********************************************************************
2128 * Initialize a receive ring and its buffers.
2130 **********************************************************************/
2132 iflib_fl_setup(iflib_fl_t fl)
2134 iflib_rxq_t rxq = fl->ifl_rxq;
2135 if_ctx_t ctx = rxq->ifr_ctx;
2136 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2138 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2140 ** Free current RX buffer structs and their mbufs
2142 iflib_fl_bufs_free(fl);
2143 /* Now replenish the mbufs */
2144 MPASS(fl->ifl_credits == 0);
2146 * XXX don't set the max_frame_size to larger
2147 * than the hardware can handle
2149 if (sctx->isc_max_frame_size <= 2048)
2150 fl->ifl_buf_size = MCLBYTES;
2151 #ifndef CONTIGMALLOC_WORKS
2153 fl->ifl_buf_size = MJUMPAGESIZE;
2155 else if (sctx->isc_max_frame_size <= 4096)
2156 fl->ifl_buf_size = MJUMPAGESIZE;
2157 else if (sctx->isc_max_frame_size <= 9216)
2158 fl->ifl_buf_size = MJUM9BYTES;
2160 fl->ifl_buf_size = MJUM16BYTES;
2162 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2163 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2164 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2165 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2168 /* avoid pre-allocating zillions of clusters to an idle card
2169 * potentially speeding up attach
2171 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2172 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2173 if (min(128, fl->ifl_size) != fl->ifl_credits)
2179 MPASS(fl->ifl_ifdi != NULL);
2180 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2181 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2185 /*********************************************************************
2187 * Free receive ring data structures
2189 **********************************************************************/
2191 iflib_rx_sds_free(iflib_rxq_t rxq)
2196 if (rxq->ifr_fl != NULL) {
2197 for (i = 0; i < rxq->ifr_nfl; i++) {
2198 fl = &rxq->ifr_fl[i];
2199 if (fl->ifl_desc_tag != NULL) {
2200 if (fl->ifl_sds.ifsd_map != NULL) {
2201 for (j = 0; j < fl->ifl_size; j++) {
2202 if (fl->ifl_sds.ifsd_map[j] ==
2207 fl->ifl_sds.ifsd_map[j],
2208 BUS_DMASYNC_POSTREAD);
2211 fl->ifl_sds.ifsd_map[j]);
2214 bus_dma_tag_destroy(fl->ifl_desc_tag);
2215 fl->ifl_desc_tag = NULL;
2217 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2218 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2219 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2220 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2221 fl->ifl_sds.ifsd_m = NULL;
2222 fl->ifl_sds.ifsd_cl = NULL;
2223 fl->ifl_sds.ifsd_ba = NULL;
2224 fl->ifl_sds.ifsd_map = NULL;
2226 free(rxq->ifr_fl, M_IFLIB);
2228 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2233 * MI independent logic
2237 iflib_timer(void *arg)
2239 iflib_txq_t txq = arg;
2240 if_ctx_t ctx = txq->ift_ctx;
2241 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2242 uint64_t this_tick = ticks;
2243 uint32_t reset_on = hz / 2;
2245 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2248 ** Check on the state of the TX queue(s), this
2249 ** can be done without the lock because its RO
2250 ** and the HUNG state will be static if set.
2252 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2253 txq->ift_last_timer_tick = this_tick;
2254 IFDI_TIMER(ctx, txq->ift_id);
2255 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2256 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2257 (sctx->isc_pause_frames == 0)))
2260 if (ifmp_ring_is_stalled(txq->ift_br))
2261 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2262 txq->ift_cleaned_prev = txq->ift_cleaned;
2265 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2266 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2268 /* handle any laggards */
2269 if (txq->ift_db_pending)
2270 GROUPTASK_ENQUEUE(&txq->ift_task);
2272 sctx->isc_pause_frames = 0;
2273 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2274 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2277 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2278 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2280 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2281 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2282 iflib_admin_intr_deferred(ctx);
2287 iflib_init_locked(if_ctx_t ctx)
2289 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2290 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2291 if_t ifp = ctx->ifc_ifp;
2295 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2298 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2299 IFDI_INTR_DISABLE(ctx);
2301 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2302 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2303 /* Set hardware offload abilities */
2304 if_clearhwassist(ifp);
2305 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2306 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2307 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2308 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2309 if (if_getcapenable(ifp) & IFCAP_TSO4)
2310 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2311 if (if_getcapenable(ifp) & IFCAP_TSO6)
2312 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2314 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2316 callout_stop(&txq->ift_timer);
2317 CALLOUT_UNLOCK(txq);
2318 iflib_netmap_txq_init(ctx, txq);
2321 i = if_getdrvflags(ifp);
2324 MPASS(if_getdrvflags(ifp) == i);
2325 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2326 /* XXX this should really be done on a per-queue basis */
2327 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2328 MPASS(rxq->ifr_id == i);
2329 iflib_netmap_rxq_init(ctx, rxq);
2332 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2333 if (iflib_fl_setup(fl)) {
2334 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2340 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2341 IFDI_INTR_ENABLE(ctx);
2342 txq = ctx->ifc_txqs;
2343 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2344 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2345 txq->ift_timer.c_cpu);
2349 iflib_media_change(if_t ifp)
2351 if_ctx_t ctx = if_getsoftc(ifp);
2355 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2356 iflib_init_locked(ctx);
2362 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2364 if_ctx_t ctx = if_getsoftc(ifp);
2367 IFDI_UPDATE_ADMIN_STATUS(ctx);
2368 IFDI_MEDIA_STATUS(ctx, ifmr);
2373 iflib_stop(if_ctx_t ctx)
2375 iflib_txq_t txq = ctx->ifc_txqs;
2376 iflib_rxq_t rxq = ctx->ifc_rxqs;
2377 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2378 if_shared_ctx_t sctx = ctx->ifc_sctx;
2379 iflib_dma_info_t di;
2383 /* Tell the stack that the interface is no longer active */
2384 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2386 IFDI_INTR_DISABLE(ctx);
2391 iflib_debug_reset();
2392 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2393 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2394 /* make sure all transmitters have completed before proceeding XXX */
2397 callout_stop(&txq->ift_timer);
2398 CALLOUT_UNLOCK(txq);
2400 /* clean any enqueued buffers */
2401 iflib_ifmp_purge(txq);
2402 /* Free any existing tx buffers. */
2403 for (j = 0; j < txq->ift_size; j++) {
2404 iflib_txsd_free(ctx, txq, j);
2406 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2407 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2408 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2409 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2410 txq->ift_pullups = 0;
2411 ifmp_ring_reset_stats(txq->ift_br);
2412 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2413 bzero((void *)di->idi_vaddr, di->idi_size);
2415 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2416 /* make sure all transmitters have completed before proceeding XXX */
2418 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2419 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2420 bzero((void *)di->idi_vaddr, di->idi_size);
2421 /* also resets the free lists pidx/cidx */
2422 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2423 iflib_fl_bufs_free(fl);
2427 static inline caddr_t
2428 calc_next_rxd(iflib_fl_t fl, int cidx)
2432 caddr_t start, end, cur, next;
2434 nrxd = fl->ifl_size;
2435 size = fl->ifl_rxd_size;
2436 start = fl->ifl_ifdi->idi_vaddr;
2438 if (__predict_false(size == 0))
2440 cur = start + size*cidx;
2441 end = start + size*nrxd;
2442 next = CACHE_PTR_NEXT(cur);
2443 return (next < end ? next : start);
2447 prefetch_pkts(iflib_fl_t fl, int cidx)
2450 int nrxd = fl->ifl_size;
2454 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2455 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2456 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2457 next_rxd = calc_next_rxd(fl, cidx);
2459 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2460 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2461 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2462 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2463 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2464 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2465 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2466 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2470 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2475 iflib_dma_info_t di;
2479 flid = irf->irf_flid;
2480 cidx = irf->irf_idx;
2481 fl = &rxq->ifr_fl[flid];
2483 sd->ifsd_cidx = cidx;
2484 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2485 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2488 fl->ifl_m_dequeued++;
2490 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2491 prefetch_pkts(fl, cidx);
2492 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2493 prefetch(&fl->ifl_sds.ifsd_map[next]);
2494 map = fl->ifl_sds.ifsd_map[cidx];
2496 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2498 /* not valid assert if bxe really does SGE from non-contiguous elements */
2499 MPASS(fl->ifl_cidx == cidx);
2500 bus_dmamap_sync(fl->ifl_desc_tag, map, BUS_DMASYNC_POSTREAD);
2502 bus_dmamap_unload(fl->ifl_desc_tag, map);
2503 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2504 if (__predict_false(fl->ifl_cidx == 0))
2506 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2508 bit_clear(fl->ifl_rx_bitmap, cidx);
2511 static struct mbuf *
2512 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2514 int i, padlen , flags;
2515 struct mbuf *m, *mh, *mt;
2521 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2523 MPASS(*sd->ifsd_cl != NULL);
2524 MPASS(*sd->ifsd_m != NULL);
2526 /* Don't include zero-length frags */
2527 if (ri->iri_frags[i].irf_len == 0) {
2528 /* XXX we can save the cluster here, but not the mbuf */
2529 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2530 m_free(*sd->ifsd_m);
2537 flags = M_PKTHDR|M_EXT;
2539 padlen = ri->iri_pad;
2544 /* assuming padding is only on the first fragment */
2548 *sd->ifsd_cl = NULL;
2550 /* Can these two be made one ? */
2551 m_init(m, M_NOWAIT, MT_DATA, flags);
2552 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2554 * These must follow m_init and m_cljset
2556 m->m_data += padlen;
2557 ri->iri_len -= padlen;
2558 m->m_len = ri->iri_frags[i].irf_len;
2559 } while (++i < ri->iri_nfrags);
2565 * Process one software descriptor
2567 static struct mbuf *
2568 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2573 /* should I merge this back in now that the two paths are basically duplicated? */
2574 if (ri->iri_nfrags == 1 &&
2575 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2576 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2579 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2580 #ifndef __NO_STRICT_ALIGNMENT
2584 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2585 bus_dmamap_sync(rxq->ifr_fl->ifl_desc_tag,
2586 rxq->ifr_fl->ifl_sds.ifsd_map[ri->iri_frags[0].irf_idx],
2587 BUS_DMASYNC_PREREAD);
2588 m->m_len = ri->iri_frags[0].irf_len;
2590 m = assemble_segments(rxq, ri, &sd);
2592 m->m_pkthdr.len = ri->iri_len;
2593 m->m_pkthdr.rcvif = ri->iri_ifp;
2594 m->m_flags |= ri->iri_flags;
2595 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2596 m->m_pkthdr.flowid = ri->iri_flowid;
2597 M_HASHTYPE_SET(m, ri->iri_rsstype);
2598 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2599 m->m_pkthdr.csum_data = ri->iri_csum_data;
2603 #if defined(INET6) || defined(INET)
2605 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2607 CURVNET_SET(lc->ifp->if_vnet);
2609 *v6 = VNET(ip6_forwarding);
2612 *v4 = VNET(ipforwarding);
2618 * Returns true if it's possible this packet could be LROed.
2619 * if it returns false, it is guaranteed that tcp_lro_rx()
2620 * would not return zero.
2623 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2625 struct ether_header *eh;
2628 eh = mtod(m, struct ether_header *);
2629 eh_type = ntohs(eh->ether_type);
2632 case ETHERTYPE_IPV6:
2633 return !v6_forwarding;
2637 return !v4_forwarding;
2645 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2651 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2653 if_ctx_t ctx = rxq->ifr_ctx;
2654 if_shared_ctx_t sctx = ctx->ifc_sctx;
2655 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2656 iflib_dma_info_t di;
2659 struct if_rxd_info ri;
2660 int err, budget_left, rx_bytes, rx_pkts;
2664 bool v4_forwarding, v6_forwarding, lro_possible;
2667 * XXX early demux data packets so that if_input processing only handles
2668 * acks in interrupt context
2670 struct mbuf *m, *mh, *mt, *mf;
2672 lro_possible = v4_forwarding = v6_forwarding = false;
2676 rx_pkts = rx_bytes = 0;
2677 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2678 cidxp = &rxq->ifr_cq_cidx;
2680 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2681 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2682 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2683 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2684 DBG_COUNTER_INC(rx_unavail);
2688 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2689 if (__predict_false(!CTX_ACTIVE(ctx))) {
2690 DBG_COUNTER_INC(rx_ctx_inactive);
2694 * Reset client set fields to their default values
2697 ri.iri_qsidx = rxq->ifr_id;
2698 ri.iri_cidx = *cidxp;
2700 ri.iri_frags = rxq->ifr_frags;
2701 di = rxq->ifr_fl[rxq->ifr_frags[0].irf_flid].ifl_ifdi;
2702 bus_dmamap_sync(di->idi_tag, di->idi_map,
2703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2704 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2708 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2709 *cidxp = ri.iri_cidx;
2710 /* Update our consumer index */
2711 /* XXX NB: shurd - check if this is still safe */
2712 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2713 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2714 rxq->ifr_cq_gen = 0;
2716 /* was this only a completion queue message? */
2717 if (__predict_false(ri.iri_nfrags == 0))
2720 MPASS(ri.iri_nfrags != 0);
2721 MPASS(ri.iri_len != 0);
2723 /* will advance the cidx on the corresponding free lists */
2724 m = iflib_rxd_pkt_get(rxq, &ri);
2727 if (avail == 0 && budget_left)
2728 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2730 if (__predict_false(m == NULL)) {
2731 DBG_COUNTER_INC(rx_mbuf_null);
2734 /* imm_pkt: -- cxgb */
2742 /* make sure that we can refill faster than drain */
2743 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2744 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2746 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2748 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2750 while (mh != NULL) {
2753 m->m_nextpkt = NULL;
2754 #ifndef __NO_STRICT_ALIGNMENT
2755 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2758 rx_bytes += m->m_pkthdr.len;
2760 #if defined(INET6) || defined(INET)
2762 if (!lro_possible) {
2763 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2764 if (lro_possible && mf != NULL) {
2765 ifp->if_input(ifp, mf);
2766 DBG_COUNTER_INC(rx_if_input);
2770 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2771 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2772 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2778 ifp->if_input(ifp, m);
2779 DBG_COUNTER_INC(rx_if_input);
2790 ifp->if_input(ifp, mf);
2791 DBG_COUNTER_INC(rx_if_input);
2794 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2795 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2798 * Flush any outstanding LRO work
2800 #if defined(INET6) || defined(INET)
2801 tcp_lro_flush_all(&rxq->ifr_lc);
2805 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2808 ctx->ifc_flags |= IFC_DO_RESET;
2809 iflib_admin_intr_deferred(ctx);
2814 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2815 static inline qidx_t
2816 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2818 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2819 qidx_t minthresh = txq->ift_size / 8;
2820 if (in_use > 4*minthresh)
2821 return (notify_count);
2822 if (in_use > 2*minthresh)
2823 return (notify_count >> 1);
2824 if (in_use > minthresh)
2825 return (notify_count >> 3);
2829 static inline qidx_t
2830 txq_max_rs_deferred(iflib_txq_t txq)
2832 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2833 qidx_t minthresh = txq->ift_size / 8;
2834 if (txq->ift_in_use > 4*minthresh)
2835 return (notify_count);
2836 if (txq->ift_in_use > 2*minthresh)
2837 return (notify_count >> 1);
2838 if (txq->ift_in_use > minthresh)
2839 return (notify_count >> 2);
2843 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2844 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2846 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2847 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2848 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2850 /* forward compatibility for cxgb */
2851 #define FIRST_QSET(ctx) 0
2852 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2853 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2854 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2855 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2857 /* XXX we should be setting this to something other than zero */
2858 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2859 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2860 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2863 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2869 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2870 if (ring || txq->ift_db_pending >= max) {
2871 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2872 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2873 txq->ift_db_pending = txq->ift_npending = 0;
2881 print_pkt(if_pkt_info_t pi)
2883 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2884 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2885 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2886 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2887 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2888 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2892 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2893 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2894 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2895 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2898 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2900 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2901 struct ether_vlan_header *eh;
2905 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2906 M_WRITABLE(m) == 0) {
2907 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2911 DBG_COUNTER_INC(tx_frees);
2917 * Determine where frame payload starts.
2918 * Jump over vlan headers if already present,
2919 * helpful for QinQ too.
2921 if (__predict_false(m->m_len < sizeof(*eh))) {
2923 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2926 eh = mtod(m, struct ether_vlan_header *);
2927 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2928 pi->ipi_etype = ntohs(eh->evl_proto);
2929 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2931 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2932 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2935 switch (pi->ipi_etype) {
2940 struct ip *ip = NULL;
2941 struct tcphdr *th = NULL;
2944 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2945 if (__predict_false(m->m_len < minthlen)) {
2947 * if this code bloat is causing too much of a hit
2948 * move it to a separate function and mark it noinline
2950 if (m->m_len == pi->ipi_ehdrlen) {
2953 if (n->m_len >= sizeof(*ip)) {
2954 ip = (struct ip *)n->m_data;
2955 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2956 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2959 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2961 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2965 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2967 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2968 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2969 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2972 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2973 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2974 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2976 pi->ipi_ip_hlen = ip->ip_hl << 2;
2977 pi->ipi_ipproto = ip->ip_p;
2978 pi->ipi_flags |= IPI_TX_IPV4;
2980 /* TCP checksum offload may require TCP header length */
2981 if (IS_TX_OFFLOAD4(pi)) {
2982 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2983 if (__predict_false(th == NULL)) {
2985 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2987 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2989 pi->ipi_tcp_hflags = th->th_flags;
2990 pi->ipi_tcp_hlen = th->th_off << 2;
2991 pi->ipi_tcp_seq = th->th_seq;
2994 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2997 * TSO always requires hardware checksum offload.
2999 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3000 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3001 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3002 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3003 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3005 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3009 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3016 case ETHERTYPE_IPV6:
3018 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3020 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3022 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3024 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3027 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3029 /* XXX-BZ this will go badly in case of ext hdrs. */
3030 pi->ipi_ipproto = ip6->ip6_nxt;
3031 pi->ipi_flags |= IPI_TX_IPV6;
3033 /* TCP checksum offload may require TCP header length */
3034 if (IS_TX_OFFLOAD6(pi)) {
3035 if (pi->ipi_ipproto == IPPROTO_TCP) {
3036 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3038 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3041 pi->ipi_tcp_hflags = th->th_flags;
3042 pi->ipi_tcp_hlen = th->th_off << 2;
3043 pi->ipi_tcp_seq = th->th_seq;
3046 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3049 * TSO always requires hardware checksum offload.
3051 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3052 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3053 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3060 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3061 pi->ipi_ip_hlen = 0;
3070 * If dodgy hardware rejects the scatter gather chain we've handed it
3071 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3074 static __noinline struct mbuf *
3075 iflib_remove_mbuf(iflib_txq_t txq)
3078 struct mbuf *m, **ifsd_m;
3080 ifsd_m = txq->ift_sds.ifsd_m;
3081 ntxd = txq->ift_size;
3082 pidx = txq->ift_pidx & (ntxd - 1);
3083 ifsd_m = txq->ift_sds.ifsd_m;
3085 ifsd_m[pidx] = NULL;
3086 bus_dmamap_unload(txq->ift_desc_tag, txq->ift_sds.ifsd_map[pidx]);
3087 if (txq->ift_sds.ifsd_tso_map != NULL)
3088 bus_dmamap_unload(txq->ift_tso_desc_tag,
3089 txq->ift_sds.ifsd_tso_map[pidx]);
3091 txq->ift_dequeued++;
3096 static inline caddr_t
3097 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3101 caddr_t start, end, cur, next;
3103 ntxd = txq->ift_size;
3104 size = txq->ift_txd_size[qid];
3105 start = txq->ift_ifdi[qid].idi_vaddr;
3107 if (__predict_false(size == 0))
3109 cur = start + size*cidx;
3110 end = start + size*ntxd;
3111 next = CACHE_PTR_NEXT(cur);
3112 return (next < end ? next : start);
3116 * Pad an mbuf to ensure a minimum ethernet frame size.
3117 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3119 static __noinline int
3120 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3123 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3124 * and ARP message is the smallest common payload I can think of
3126 static char pad[18]; /* just zeros */
3128 struct mbuf *new_head;
3130 if (!M_WRITABLE(*m_head)) {
3131 new_head = m_dup(*m_head, M_NOWAIT);
3132 if (new_head == NULL) {
3134 device_printf(dev, "cannot pad short frame, m_dup() failed");
3135 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3136 DBG_COUNTER_INC(tx_frees);
3143 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3144 n > 0; n -= sizeof(pad))
3145 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3150 device_printf(dev, "cannot pad short frame\n");
3151 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3152 DBG_COUNTER_INC(tx_frees);
3160 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3163 if_shared_ctx_t sctx;
3164 if_softc_ctx_t scctx;
3165 bus_dma_segment_t *segs;
3166 struct mbuf *m_head, **ifsd_m;
3169 struct if_pkt_info pi;
3171 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3172 bus_dma_tag_t desc_tag;
3175 sctx = ctx->ifc_sctx;
3176 scctx = &ctx->ifc_softc_ctx;
3177 segs = txq->ift_segs;
3178 ntxd = txq->ift_size;
3183 * If we're doing TSO the next descriptor to clean may be quite far ahead
3185 cidx = txq->ift_cidx;
3186 pidx = txq->ift_pidx;
3187 if (ctx->ifc_flags & IFC_PREFETCH) {
3188 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3189 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3190 next_txd = calc_next_txd(txq, cidx, 0);
3194 /* prefetch the next cache line of mbuf pointers and flags */
3195 prefetch(&txq->ift_sds.ifsd_m[next]);
3196 prefetch(&txq->ift_sds.ifsd_map[next]);
3197 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3199 map = txq->ift_sds.ifsd_map[pidx];
3200 ifsd_m = txq->ift_sds.ifsd_m;
3202 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3203 desc_tag = txq->ift_tso_desc_tag;
3204 max_segs = scctx->isc_tx_tso_segments_max;
3205 map = txq->ift_sds.ifsd_tso_map[pidx];
3206 MPASS(desc_tag != NULL);
3207 MPASS(max_segs > 0);
3209 desc_tag = txq->ift_desc_tag;
3210 max_segs = scctx->isc_tx_nsegments;
3211 map = txq->ift_sds.ifsd_map[pidx];
3213 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3214 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3215 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3217 DBG_COUNTER_INC(encap_txd_encap_fail);
3224 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3226 pi.ipi_qsidx = txq->ift_id;
3227 pi.ipi_len = m_head->m_pkthdr.len;
3228 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3229 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3231 /* deliberate bitwise OR to make one condition */
3232 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3233 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3234 DBG_COUNTER_INC(encap_txd_encap_fail);
3241 err = bus_dmamap_load_mbuf_sg(desc_tag, map, m_head, segs, &nsegs,
3244 if (__predict_false(err)) {
3247 /* try collapse once and defrag once */
3249 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3250 /* try defrag if collapsing fails */
3255 txq->ift_mbuf_defrag++;
3256 m_head = m_defrag(*m_headp, M_NOWAIT);
3259 if (__predict_false(m_head == NULL))
3265 txq->ift_no_tx_dma_setup++;
3268 txq->ift_no_tx_dma_setup++;
3270 DBG_COUNTER_INC(tx_frees);
3274 txq->ift_map_failed++;
3275 DBG_COUNTER_INC(encap_load_mbuf_fail);
3276 DBG_COUNTER_INC(encap_txd_encap_fail);
3279 ifsd_m[pidx] = m_head;
3281 * XXX assumes a 1 to 1 relationship between segments and
3282 * descriptors - this does not hold true on all drivers, e.g.
3285 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3286 txq->ift_no_desc_avail++;
3287 bus_dmamap_unload(desc_tag, map);
3288 DBG_COUNTER_INC(encap_txq_avail_fail);
3289 DBG_COUNTER_INC(encap_txd_encap_fail);
3290 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3291 GROUPTASK_ENQUEUE(&txq->ift_task);
3295 * On Intel cards we can greatly reduce the number of TX interrupts
3296 * we see by only setting report status on every Nth descriptor.
3297 * However, this also means that the driver will need to keep track
3298 * of the descriptors that RS was set on to check them for the DD bit.
3300 txq->ift_rs_pending += nsegs + 1;
3301 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3302 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3303 pi.ipi_flags |= IPI_TX_INTR;
3304 txq->ift_rs_pending = 0;
3308 pi.ipi_nsegs = nsegs;
3310 MPASS(pidx >= 0 && pidx < txq->ift_size);
3314 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3315 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3316 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3317 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3318 DBG_COUNTER_INC(tx_encap);
3319 MPASS(pi.ipi_new_pidx < txq->ift_size);
3321 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3322 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3323 ndesc += txq->ift_size;
3327 * drivers can need as many as
3330 MPASS(ndesc <= pi.ipi_nsegs + 2);
3331 MPASS(pi.ipi_new_pidx != pidx);
3333 txq->ift_in_use += ndesc;
3336 * We update the last software descriptor again here because there may
3337 * be a sentinel and/or there may be more mbufs than segments
3339 txq->ift_pidx = pi.ipi_new_pidx;
3340 txq->ift_npending += pi.ipi_ndescs;
3342 *m_headp = m_head = iflib_remove_mbuf(txq);
3344 txq->ift_txd_encap_efbig++;
3353 * err can't possibly be non-zero here, so we don't neet to test it
3354 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3359 txq->ift_mbuf_defrag_failed++;
3360 txq->ift_map_failed++;
3362 DBG_COUNTER_INC(tx_frees);
3364 DBG_COUNTER_INC(encap_txd_encap_fail);
3369 iflib_tx_desc_free(iflib_txq_t txq, int n)
3371 uint32_t qsize, cidx, mask, gen;
3372 struct mbuf *m, **ifsd_m;
3375 cidx = txq->ift_cidx;
3377 qsize = txq->ift_size;
3379 ifsd_m = txq->ift_sds.ifsd_m;
3380 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3384 prefetch(ifsd_m[(cidx + 3) & mask]);
3385 prefetch(ifsd_m[(cidx + 4) & mask]);
3387 if ((m = ifsd_m[cidx]) != NULL) {
3388 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3389 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3390 bus_dmamap_sync(txq->ift_tso_desc_tag,
3391 txq->ift_sds.ifsd_tso_map[cidx],
3392 BUS_DMASYNC_POSTWRITE);
3393 bus_dmamap_unload(txq->ift_tso_desc_tag,
3394 txq->ift_sds.ifsd_tso_map[cidx]);
3396 bus_dmamap_sync(txq->ift_desc_tag,
3397 txq->ift_sds.ifsd_map[cidx],
3398 BUS_DMASYNC_POSTWRITE);
3399 bus_dmamap_unload(txq->ift_desc_tag,
3400 txq->ift_sds.ifsd_map[cidx]);
3402 /* XXX we don't support any drivers that batch packets yet */
3403 MPASS(m->m_nextpkt == NULL);
3405 ifsd_m[cidx] = NULL;
3407 txq->ift_dequeued++;
3409 DBG_COUNTER_INC(tx_frees);
3411 if (__predict_false(++cidx == qsize)) {
3416 txq->ift_cidx = cidx;
3421 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3424 if_ctx_t ctx = txq->ift_ctx;
3426 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3427 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3430 * Need a rate-limiting check so that this isn't called every time
3432 iflib_tx_credits_update(ctx, txq);
3433 reclaim = DESC_RECLAIMABLE(txq);
3435 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3437 if (iflib_verbose_debug) {
3438 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3439 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3446 iflib_tx_desc_free(txq, reclaim);
3447 txq->ift_cleaned += reclaim;
3448 txq->ift_in_use -= reclaim;
3453 static struct mbuf **
3454 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3457 struct mbuf **items;
3460 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3461 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3463 prefetch(items[(cidx + offset) & (size-1)]);
3464 if (remaining > 1) {
3465 prefetch2cachelines(&items[next]);
3466 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3467 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3468 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3470 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3474 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3477 ifmp_ring_check_drainage(txq->ift_br, budget);
3481 iflib_txq_can_drain(struct ifmp_ring *r)
3483 iflib_txq_t txq = r->cookie;
3484 if_ctx_t ctx = txq->ift_ctx;
3486 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3487 BUS_DMASYNC_POSTREAD);
3488 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3489 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3493 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3495 iflib_txq_t txq = r->cookie;
3496 if_ctx_t ctx = txq->ift_ctx;
3497 struct ifnet *ifp = ctx->ifc_ifp;
3498 struct mbuf **mp, *m;
3499 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3500 int reclaimed, err, in_use_prev, desc_used;
3501 bool do_prefetch, ring, rang;
3503 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3504 !LINK_ACTIVE(ctx))) {
3505 DBG_COUNTER_INC(txq_drain_notready);
3508 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3509 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3510 avail = IDXDIFF(pidx, cidx, r->size);
3511 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3512 DBG_COUNTER_INC(txq_drain_flushing);
3513 for (i = 0; i < avail; i++) {
3514 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3515 m_free(r->items[(cidx + i) & (r->size-1)]);
3516 r->items[(cidx + i) & (r->size-1)] = NULL;
3521 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3522 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3524 callout_stop(&txq->ift_timer);
3525 CALLOUT_UNLOCK(txq);
3526 DBG_COUNTER_INC(txq_drain_oactive);
3530 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3531 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3532 count = MIN(avail, TX_BATCH_SIZE);
3534 if (iflib_verbose_debug)
3535 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3536 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3538 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3539 avail = TXQ_AVAIL(txq);
3541 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3542 int rem = do_prefetch ? count - i : 0;
3544 mp = _ring_peek_one(r, cidx, i, rem);
3545 MPASS(mp != NULL && *mp != NULL);
3546 if (__predict_false(*mp == (struct mbuf *)txq)) {
3551 in_use_prev = txq->ift_in_use;
3552 err = iflib_encap(txq, mp);
3553 if (__predict_false(err)) {
3554 /* no room - bail out */
3558 /* we can't send this packet - skip it */
3564 DBG_COUNTER_INC(tx_sent);
3565 bytes_sent += m->m_pkthdr.len;
3566 mcast_sent += !!(m->m_flags & M_MCAST);
3567 avail = TXQ_AVAIL(txq);
3569 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3570 desc_used += (txq->ift_in_use - in_use_prev);
3571 ETHER_BPF_MTAP(ifp, m);
3572 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3574 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3577 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3578 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3579 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3580 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3581 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3583 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3585 if (iflib_verbose_debug)
3586 printf("consumed=%d\n", consumed);
3592 iflib_txq_drain_always(struct ifmp_ring *r)
3598 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3606 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3608 callout_stop(&txq->ift_timer);
3609 CALLOUT_UNLOCK(txq);
3611 avail = IDXDIFF(pidx, cidx, r->size);
3612 for (i = 0; i < avail; i++) {
3613 mp = _ring_peek_one(r, cidx, i, avail - i);
3614 if (__predict_false(*mp == (struct mbuf *)txq))
3617 DBG_COUNTER_INC(tx_frees);
3619 MPASS(ifmp_ring_is_stalled(r) == 0);
3624 iflib_ifmp_purge(iflib_txq_t txq)
3626 struct ifmp_ring *r;
3629 r->drain = iflib_txq_drain_free;
3630 r->can_drain = iflib_txq_drain_always;
3632 ifmp_ring_check_drainage(r, r->size);
3634 r->drain = iflib_txq_drain;
3635 r->can_drain = iflib_txq_can_drain;
3639 _task_fn_tx(void *context)
3641 iflib_txq_t txq = context;
3642 if_ctx_t ctx = txq->ift_ctx;
3643 struct ifnet *ifp = ctx->ifc_ifp;
3644 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3646 #ifdef IFLIB_DIAGNOSTICS
3647 txq->ift_cpu_exec_count[curcpu]++;
3649 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3651 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3652 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3653 BUS_DMASYNC_POSTREAD);
3654 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3655 netmap_tx_irq(ifp, txq->ift_id);
3656 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3660 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3661 iflib_altq_if_start(ifp);
3663 if (txq->ift_db_pending)
3664 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3666 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3668 * When abdicating, we always need to check drainage, not just when we don't enqueue
3671 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3672 if (ctx->ifc_flags & IFC_LEGACY)
3673 IFDI_INTR_ENABLE(ctx);
3678 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3679 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3684 _task_fn_rx(void *context)
3686 iflib_rxq_t rxq = context;
3687 if_ctx_t ctx = rxq->ifr_ctx;
3691 #ifdef IFLIB_DIAGNOSTICS
3692 rxq->ifr_cpu_exec_count[curcpu]++;
3694 DBG_COUNTER_INC(task_fn_rxs);
3695 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3699 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3701 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3706 budget = ctx->ifc_sysctl_rx_budget;
3708 budget = 16; /* XXX */
3709 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3710 if (ctx->ifc_flags & IFC_LEGACY)
3711 IFDI_INTR_ENABLE(ctx);
3716 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3717 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3718 DBG_COUNTER_INC(rx_intr_enables);
3721 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3724 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3728 _task_fn_admin(void *context)
3730 if_ctx_t ctx = context;
3731 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3734 bool oactive, running, do_reset, do_watchdog, in_detach;
3735 uint32_t reset_on = hz / 2;
3738 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3739 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3740 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3741 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3742 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3743 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3746 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3752 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3754 callout_stop(&txq->ift_timer);
3755 CALLOUT_UNLOCK(txq);
3758 ctx->ifc_watchdog_events++;
3759 IFDI_WATCHDOG_RESET(ctx);
3761 IFDI_UPDATE_ADMIN_STATUS(ctx);
3762 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3765 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3766 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3768 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3770 IFDI_LINK_INTR_ENABLE(ctx);
3772 iflib_if_init_locked(ctx);
3775 if (LINK_ACTIVE(ctx) == 0)
3777 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3778 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3783 _task_fn_iov(void *context)
3785 if_ctx_t ctx = context;
3787 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3788 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3792 IFDI_VFLR_HANDLE(ctx);
3797 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3800 if_int_delay_info_t info;
3803 info = (if_int_delay_info_t)arg1;
3804 ctx = info->iidi_ctx;
3805 info->iidi_req = req;
3806 info->iidi_oidp = oidp;
3808 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3813 /*********************************************************************
3817 **********************************************************************/
3820 iflib_if_init_locked(if_ctx_t ctx)
3823 iflib_init_locked(ctx);
3828 iflib_if_init(void *arg)
3833 iflib_if_init_locked(ctx);
3838 iflib_if_transmit(if_t ifp, struct mbuf *m)
3840 if_ctx_t ctx = if_getsoftc(ifp);
3844 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3846 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3847 DBG_COUNTER_INC(tx_frees);
3852 MPASS(m->m_nextpkt == NULL);
3853 /* ALTQ-enabled interfaces always use queue 0. */
3855 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3856 qidx = QIDX(ctx, m);
3858 * XXX calculate buf_ring based on flowid (divvy up bits?)
3860 txq = &ctx->ifc_txqs[qidx];
3862 #ifdef DRIVER_BACKPRESSURE
3863 if (txq->ift_closed) {
3865 next = m->m_nextpkt;
3866 m->m_nextpkt = NULL;
3868 DBG_COUNTER_INC(tx_frees);
3880 next = next->m_nextpkt;
3881 } while (next != NULL);
3883 if (count > nitems(marr))
3884 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3885 /* XXX check nextpkt */
3887 /* XXX simplify for now */
3888 DBG_COUNTER_INC(tx_frees);
3891 for (next = m, i = 0; next != NULL; i++) {
3893 next = next->m_nextpkt;
3894 mp[i]->m_nextpkt = NULL;
3897 DBG_COUNTER_INC(tx_seen);
3898 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3901 GROUPTASK_ENQUEUE(&txq->ift_task);
3904 GROUPTASK_ENQUEUE(&txq->ift_task);
3905 /* support forthcoming later */
3906 #ifdef DRIVER_BACKPRESSURE
3907 txq->ift_closed = TRUE;
3909 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3911 DBG_COUNTER_INC(tx_frees);
3919 * The overall approach to integrating iflib with ALTQ is to continue to use
3920 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3921 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
3922 * is redundant/unnecessary, but doing so minimizes the amount of
3923 * ALTQ-specific code required in iflib. It is assumed that the overhead of
3924 * redundantly queueing to an intermediate mp_ring is swamped by the
3925 * performance limitations inherent in using ALTQ.
3927 * When ALTQ support is compiled in, all iflib drivers will use a transmit
3928 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
3929 * given interface. If ALTQ is enabled for an interface, then all
3930 * transmitted packets for that interface will be submitted to the ALTQ
3931 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
3932 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
3933 * update stats that the iflib machinery handles, and which is sensitve to
3934 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
3935 * will be installed as the start routine for use by ALTQ facilities that
3936 * need to trigger queue drains on a scheduled basis.
3940 iflib_altq_if_start(if_t ifp)
3942 struct ifaltq *ifq = &ifp->if_snd;
3946 IFQ_DEQUEUE_NOLOCK(ifq, m);
3948 iflib_if_transmit(ifp, m);
3949 IFQ_DEQUEUE_NOLOCK(ifq, m);
3955 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
3959 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
3960 IFQ_ENQUEUE(&ifp->if_snd, m, err);
3962 iflib_altq_if_start(ifp);
3964 err = iflib_if_transmit(ifp, m);
3971 iflib_if_qflush(if_t ifp)
3973 if_ctx_t ctx = if_getsoftc(ifp);
3974 iflib_txq_t txq = ctx->ifc_txqs;
3978 ctx->ifc_flags |= IFC_QFLUSH;
3980 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3981 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3982 iflib_txq_check_drain(txq, 0);
3984 ctx->ifc_flags &= ~IFC_QFLUSH;
3988 * When ALTQ is enabled, this will also take care of purging the
3995 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3996 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3997 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
3998 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4001 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4003 if_ctx_t ctx = if_getsoftc(ifp);
4004 struct ifreq *ifr = (struct ifreq *)data;
4005 #if defined(INET) || defined(INET6)
4006 struct ifaddr *ifa = (struct ifaddr *)data;
4008 bool avoid_reset = FALSE;
4009 int err = 0, reinit = 0, bits;
4014 if (ifa->ifa_addr->sa_family == AF_INET)
4018 if (ifa->ifa_addr->sa_family == AF_INET6)
4022 ** Calling init results in link renegotiation,
4023 ** so we avoid doing it when possible.
4026 if_setflagbits(ifp, IFF_UP,0);
4027 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4030 if (!(if_getflags(ifp) & IFF_NOARP))
4031 arp_ifinit(ifp, ifa);
4034 err = ether_ioctl(ifp, command, data);
4038 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4042 bits = if_getdrvflags(ifp);
4043 /* stop the driver and free any clusters before proceeding */
4046 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4048 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4049 ctx->ifc_flags |= IFC_MULTISEG;
4051 ctx->ifc_flags &= ~IFC_MULTISEG;
4053 err = if_setmtu(ifp, ifr->ifr_mtu);
4055 iflib_init_locked(ctx);
4057 if_setdrvflags(ifp, bits);
4063 if (if_getflags(ifp) & IFF_UP) {
4064 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4065 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4066 (IFF_PROMISC | IFF_ALLMULTI)) {
4067 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4071 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4074 ctx->ifc_if_flags = if_getflags(ifp);
4079 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4081 IFDI_INTR_DISABLE(ctx);
4082 IFDI_MULTI_SET(ctx);
4083 IFDI_INTR_ENABLE(ctx);
4089 IFDI_MEDIA_SET(ctx);
4094 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4098 struct ifi2creq i2c;
4100 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4103 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4107 if (i2c.len > sizeof(i2c.data)) {
4112 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4113 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4119 int mask, setmask, oldmask;
4121 oldmask = if_getcapenable(ifp);
4122 mask = ifr->ifr_reqcap ^ oldmask;
4123 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4126 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4128 setmask |= (mask & IFCAP_FLAGS);
4129 setmask |= (mask & IFCAP_WOL);
4132 * If any RX csum has changed, change all the ones that
4133 * are supported by the driver.
4135 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4136 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4137 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4141 * want to ensure that traffic has stopped before we change any of the flags
4145 bits = if_getdrvflags(ifp);
4146 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4149 if_togglecapenable(ifp, setmask);
4151 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4152 iflib_init_locked(ctx);
4154 if_setdrvflags(ifp, bits);
4161 case SIOCGPRIVATE_0:
4165 err = IFDI_PRIV_IOCTL(ctx, command, data);
4169 err = ether_ioctl(ifp, command, data);
4178 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4180 if_ctx_t ctx = if_getsoftc(ifp);
4182 return (IFDI_GET_COUNTER(ctx, cnt));
4185 /*********************************************************************
4187 * OTHER FUNCTIONS EXPORTED TO THE STACK
4189 **********************************************************************/
4192 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4194 if_ctx_t ctx = if_getsoftc(ifp);
4196 if ((void *)ctx != arg)
4199 if ((vtag == 0) || (vtag > 4095))
4203 IFDI_VLAN_REGISTER(ctx, vtag);
4204 /* Re-init to load the changes */
4205 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4206 iflib_if_init_locked(ctx);
4211 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4213 if_ctx_t ctx = if_getsoftc(ifp);
4215 if ((void *)ctx != arg)
4218 if ((vtag == 0) || (vtag > 4095))
4222 IFDI_VLAN_UNREGISTER(ctx, vtag);
4223 /* Re-init to load the changes */
4224 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4225 iflib_if_init_locked(ctx);
4230 iflib_led_func(void *arg, int onoff)
4235 IFDI_LED_FUNC(ctx, onoff);
4239 /*********************************************************************
4241 * BUS FUNCTION DEFINITIONS
4243 **********************************************************************/
4246 iflib_device_probe(device_t dev)
4248 pci_vendor_info_t *ent;
4250 uint16_t pci_vendor_id, pci_device_id;
4251 uint16_t pci_subvendor_id, pci_subdevice_id;
4252 uint16_t pci_rev_id;
4253 if_shared_ctx_t sctx;
4255 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4258 pci_vendor_id = pci_get_vendor(dev);
4259 pci_device_id = pci_get_device(dev);
4260 pci_subvendor_id = pci_get_subvendor(dev);
4261 pci_subdevice_id = pci_get_subdevice(dev);
4262 pci_rev_id = pci_get_revid(dev);
4263 if (sctx->isc_parse_devinfo != NULL)
4264 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4266 ent = sctx->isc_vendor_info;
4267 while (ent->pvi_vendor_id != 0) {
4268 if (pci_vendor_id != ent->pvi_vendor_id) {
4272 if ((pci_device_id == ent->pvi_device_id) &&
4273 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4274 (ent->pvi_subvendor_id == 0)) &&
4275 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4276 (ent->pvi_subdevice_id == 0)) &&
4277 ((pci_rev_id == ent->pvi_rev_id) ||
4278 (ent->pvi_rev_id == 0))) {
4280 device_set_desc_copy(dev, ent->pvi_name);
4281 /* this needs to be changed to zero if the bus probing code
4282 * ever stops re-probing on best match because the sctx
4283 * may have its values over written by register calls
4284 * in subsequent probes
4286 return (BUS_PROBE_DEFAULT);
4294 iflib_reset_qvalues(if_ctx_t ctx)
4296 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4297 if_shared_ctx_t sctx = ctx->ifc_sctx;
4298 device_t dev = ctx->ifc_dev;
4301 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4302 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4304 * XXX sanity check that ntxd & nrxd are a power of 2
4306 if (ctx->ifc_sysctl_ntxqs != 0)
4307 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4308 if (ctx->ifc_sysctl_nrxqs != 0)
4309 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4311 for (i = 0; i < sctx->isc_ntxqs; i++) {
4312 if (ctx->ifc_sysctl_ntxds[i] != 0)
4313 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4315 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4318 for (i = 0; i < sctx->isc_nrxqs; i++) {
4319 if (ctx->ifc_sysctl_nrxds[i] != 0)
4320 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4322 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4325 for (i = 0; i < sctx->isc_nrxqs; i++) {
4326 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4327 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4328 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4329 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4331 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4332 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4333 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4334 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4338 for (i = 0; i < sctx->isc_ntxqs; i++) {
4339 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4340 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4341 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4342 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4344 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4345 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4346 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4347 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4353 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4358 if_softc_ctx_t scctx;
4364 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4367 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4368 device_set_softc(dev, ctx);
4369 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4372 ctx->ifc_sctx = sctx;
4374 ctx->ifc_softc = sc;
4376 if ((err = iflib_register(ctx)) != 0) {
4377 device_printf(dev, "iflib_register failed %d\n", err);
4380 iflib_add_device_sysctl_pre(ctx);
4382 scctx = &ctx->ifc_softc_ctx;
4385 iflib_reset_qvalues(ctx);
4387 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4388 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4391 _iflib_pre_assert(scctx);
4392 ctx->ifc_txrx = *scctx->isc_txrx;
4395 MPASS(scctx->isc_capabilities);
4396 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4397 MPASS(scctx->isc_tx_csum_flags);
4400 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4401 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4403 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4404 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4405 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4406 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4408 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4409 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4411 /* XXX change for per-queue sizes */
4412 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4413 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4414 for (i = 0; i < sctx->isc_nrxqs; i++) {
4415 if (!powerof2(scctx->isc_nrxd[i])) {
4416 /* round down instead? */
4417 device_printf(dev, "# rx descriptors must be a power of 2\n");
4419 goto fail_iflib_detach;
4422 for (i = 0; i < sctx->isc_ntxqs; i++) {
4423 if (!powerof2(scctx->isc_ntxd[i])) {
4425 "# tx descriptors must be a power of 2");
4427 goto fail_iflib_detach;
4431 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4432 MAX_SINGLE_PACKET_FRACTION)
4433 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4434 MAX_SINGLE_PACKET_FRACTION);
4435 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4436 MAX_SINGLE_PACKET_FRACTION)
4437 scctx->isc_tx_tso_segments_max = max(1,
4438 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4440 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4441 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4443 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4446 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4449 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4450 * into account. In the worst case, each of these calls will
4451 * add another mbuf and, thus, the requirement for another DMA
4452 * segment. So for best performance, it doesn't make sense to
4453 * advertize a maximum of TSO segments that typically will
4454 * require defragmentation in iflib_encap().
4456 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4457 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4459 if (scctx->isc_rss_table_size == 0)
4460 scctx->isc_rss_table_size = 64;
4461 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4463 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4464 /* XXX format name */
4465 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4467 /* Set up cpu set. If it fails, use the set of all CPUs. */
4468 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4469 device_printf(dev, "Unable to fetch CPU list\n");
4470 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4472 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4475 ** Now setup MSI or MSI/X, should
4476 ** return us the number of supported
4477 ** vectors. (Will be 1 for MSI)
4479 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4480 msix = scctx->isc_vectors;
4481 } else if (scctx->isc_msix_bar != 0)
4483 * The simple fact that isc_msix_bar is not 0 does not mean we
4484 * we have a good value there that is known to work.
4486 msix = iflib_msix_init(ctx);
4488 scctx->isc_vectors = 1;
4489 scctx->isc_ntxqsets = 1;
4490 scctx->isc_nrxqsets = 1;
4491 scctx->isc_intr = IFLIB_INTR_LEGACY;
4494 /* Get memory for the station queues */
4495 if ((err = iflib_queues_alloc(ctx))) {
4496 device_printf(dev, "Unable to allocate queue memory\n");
4497 goto fail_intr_free;
4500 if ((err = iflib_qset_structures_setup(ctx)))
4504 * Group taskqueues aren't properly set up until SMP is started,
4505 * so we disable interrupts until we can handle them post
4508 * XXX: disabling interrupts doesn't actually work, at least for
4509 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4510 * we do null handling and depend on this not causing too large an
4513 IFDI_INTR_DISABLE(ctx);
4514 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4515 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4520 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4524 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4525 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4530 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4532 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4533 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4538 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4539 * This must appear after the call to ether_ifattach() because
4540 * ether_ifattach() sets if_hdrlen to the default value.
4542 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4543 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4545 if ((err = iflib_netmap_attach(ctx))) {
4546 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4551 NETDUMP_SET(ctx->ifc_ifp, iflib);
4553 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4554 iflib_add_device_sysctl_post(ctx);
4555 ctx->ifc_flags |= IFC_INIT_DONE;
4560 ether_ifdetach(ctx->ifc_ifp);
4562 iflib_free_intr_mem(ctx);
4564 iflib_tx_structures_free(ctx);
4565 iflib_rx_structures_free(ctx);
4571 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4572 free(ctx->ifc_softc, M_IFLIB);
4578 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4579 struct iflib_cloneattach_ctx *clctx)
4584 if_softc_ctx_t scctx;
4590 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4591 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4592 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4593 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4594 ctx->ifc_flags |= IFC_PSEUDO;
4596 ctx->ifc_sctx = sctx;
4597 ctx->ifc_softc = sc;
4600 if ((err = iflib_register(ctx)) != 0) {
4601 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4604 iflib_add_device_sysctl_pre(ctx);
4606 scctx = &ctx->ifc_softc_ctx;
4610 * XXX sanity check that ntxd & nrxd are a power of 2
4612 iflib_reset_qvalues(ctx);
4614 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4615 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4618 if (sctx->isc_flags & IFLIB_GEN_MAC)
4620 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4621 clctx->cc_params)) != 0) {
4622 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4625 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4626 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4627 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4630 MPASS(scctx->isc_capabilities);
4631 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4632 MPASS(scctx->isc_tx_csum_flags);
4635 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4636 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4638 ifp->if_flags |= IFF_NOGROUP;
4639 if (sctx->isc_flags & IFLIB_PSEUDO) {
4640 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4642 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4643 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4649 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4650 * This must appear after the call to ether_ifattach() because
4651 * ether_ifattach() sets if_hdrlen to the default value.
4653 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4654 if_setifheaderlen(ifp,
4655 sizeof(struct ether_vlan_header));
4657 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4658 iflib_add_device_sysctl_post(ctx);
4659 ctx->ifc_flags |= IFC_INIT_DONE;
4662 _iflib_pre_assert(scctx);
4663 ctx->ifc_txrx = *scctx->isc_txrx;
4665 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4666 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4667 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4668 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4670 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4671 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4673 /* XXX change for per-queue sizes */
4674 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4675 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4676 for (i = 0; i < sctx->isc_nrxqs; i++) {
4677 if (!powerof2(scctx->isc_nrxd[i])) {
4678 /* round down instead? */
4679 device_printf(dev, "# rx descriptors must be a power of 2\n");
4681 goto fail_iflib_detach;
4684 for (i = 0; i < sctx->isc_ntxqs; i++) {
4685 if (!powerof2(scctx->isc_ntxd[i])) {
4687 "# tx descriptors must be a power of 2");
4689 goto fail_iflib_detach;
4693 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4694 MAX_SINGLE_PACKET_FRACTION)
4695 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4696 MAX_SINGLE_PACKET_FRACTION);
4697 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4698 MAX_SINGLE_PACKET_FRACTION)
4699 scctx->isc_tx_tso_segments_max = max(1,
4700 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4702 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4703 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4705 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4708 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4711 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4712 * into account. In the worst case, each of these calls will
4713 * add another mbuf and, thus, the requirement for another DMA
4714 * segment. So for best performance, it doesn't make sense to
4715 * advertize a maximum of TSO segments that typically will
4716 * require defragmentation in iflib_encap().
4718 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4719 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4721 if (scctx->isc_rss_table_size == 0)
4722 scctx->isc_rss_table_size = 64;
4723 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4725 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4726 /* XXX format name */
4727 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4729 /* XXX --- can support > 1 -- but keep it simple for now */
4730 scctx->isc_intr = IFLIB_INTR_LEGACY;
4732 /* Get memory for the station queues */
4733 if ((err = iflib_queues_alloc(ctx))) {
4734 device_printf(dev, "Unable to allocate queue memory\n");
4735 goto fail_iflib_detach;
4738 if ((err = iflib_qset_structures_setup(ctx))) {
4739 device_printf(dev, "qset structure setup failed %d\n", err);
4744 * XXX What if anything do we want to do about interrupts?
4746 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4747 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4748 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4753 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4754 * This must appear after the call to ether_ifattach() because
4755 * ether_ifattach() sets if_hdrlen to the default value.
4757 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4758 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4760 /* XXX handle more than one queue */
4761 for (i = 0; i < scctx->isc_nrxqsets; i++)
4762 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4766 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4767 iflib_add_device_sysctl_post(ctx);
4768 ctx->ifc_flags |= IFC_INIT_DONE;
4771 ether_ifdetach(ctx->ifc_ifp);
4773 iflib_tx_structures_free(ctx);
4774 iflib_rx_structures_free(ctx);
4778 free(ctx->ifc_softc, M_IFLIB);
4784 iflib_pseudo_deregister(if_ctx_t ctx)
4786 if_t ifp = ctx->ifc_ifp;
4790 struct taskqgroup *tqg;
4793 /* Unregister VLAN events */
4794 if (ctx->ifc_vlan_attach_event != NULL)
4795 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4796 if (ctx->ifc_vlan_detach_event != NULL)
4797 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4799 ether_ifdetach(ifp);
4800 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4801 CTX_LOCK_DESTROY(ctx);
4802 /* XXX drain any dependent tasks */
4803 tqg = qgroup_if_io_tqg;
4804 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4805 callout_drain(&txq->ift_timer);
4806 if (txq->ift_task.gt_uniq != NULL)
4807 taskqgroup_detach(tqg, &txq->ift_task);
4809 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4810 if (rxq->ifr_task.gt_uniq != NULL)
4811 taskqgroup_detach(tqg, &rxq->ifr_task);
4813 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4814 free(fl->ifl_rx_bitmap, M_IFLIB);
4816 tqg = qgroup_if_config_tqg;
4817 if (ctx->ifc_admin_task.gt_uniq != NULL)
4818 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4819 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4820 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4824 iflib_tx_structures_free(ctx);
4825 iflib_rx_structures_free(ctx);
4826 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4827 free(ctx->ifc_softc, M_IFLIB);
4833 iflib_device_attach(device_t dev)
4836 if_shared_ctx_t sctx;
4838 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4841 pci_enable_busmaster(dev);
4843 return (iflib_device_register(dev, NULL, sctx, &ctx));
4847 iflib_device_deregister(if_ctx_t ctx)
4849 if_t ifp = ctx->ifc_ifp;
4852 device_t dev = ctx->ifc_dev;
4854 struct taskqgroup *tqg;
4857 /* Make sure VLANS are not using driver */
4858 if (if_vlantrunkinuse(ifp)) {
4859 device_printf(dev, "Vlan in use, detach first\n");
4863 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
4864 device_printf(dev, "SR-IOV in use; detach first.\n");
4870 ctx->ifc_flags |= IFC_IN_DETACH;
4877 /* Unregister VLAN events */
4878 if (ctx->ifc_vlan_attach_event != NULL)
4879 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4880 if (ctx->ifc_vlan_detach_event != NULL)
4881 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4883 iflib_netmap_detach(ifp);
4884 ether_ifdetach(ifp);
4885 if (ctx->ifc_led_dev != NULL)
4886 led_destroy(ctx->ifc_led_dev);
4887 /* XXX drain any dependent tasks */
4888 tqg = qgroup_if_io_tqg;
4889 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4890 callout_drain(&txq->ift_timer);
4891 if (txq->ift_task.gt_uniq != NULL)
4892 taskqgroup_detach(tqg, &txq->ift_task);
4894 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4895 if (rxq->ifr_task.gt_uniq != NULL)
4896 taskqgroup_detach(tqg, &rxq->ifr_task);
4898 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4899 free(fl->ifl_rx_bitmap, M_IFLIB);
4901 tqg = qgroup_if_config_tqg;
4902 if (ctx->ifc_admin_task.gt_uniq != NULL)
4903 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4904 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4905 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4910 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4911 CTX_LOCK_DESTROY(ctx);
4912 device_set_softc(ctx->ifc_dev, NULL);
4913 iflib_free_intr_mem(ctx);
4915 bus_generic_detach(dev);
4918 iflib_tx_structures_free(ctx);
4919 iflib_rx_structures_free(ctx);
4920 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4921 free(ctx->ifc_softc, M_IFLIB);
4922 STATE_LOCK_DESTROY(ctx);
4928 iflib_free_intr_mem(if_ctx_t ctx)
4931 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4932 pci_release_msi(ctx->ifc_dev);
4934 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4935 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4937 if (ctx->ifc_msix_mem != NULL) {
4938 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4939 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4940 ctx->ifc_msix_mem = NULL;
4945 iflib_device_detach(device_t dev)
4947 if_ctx_t ctx = device_get_softc(dev);
4949 return (iflib_device_deregister(ctx));
4953 iflib_device_suspend(device_t dev)
4955 if_ctx_t ctx = device_get_softc(dev);
4961 return bus_generic_suspend(dev);
4964 iflib_device_shutdown(device_t dev)
4966 if_ctx_t ctx = device_get_softc(dev);
4972 return bus_generic_suspend(dev);
4977 iflib_device_resume(device_t dev)
4979 if_ctx_t ctx = device_get_softc(dev);
4980 iflib_txq_t txq = ctx->ifc_txqs;
4984 iflib_if_init_locked(ctx);
4986 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4987 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4989 return (bus_generic_resume(dev));
4993 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4996 if_ctx_t ctx = device_get_softc(dev);
4999 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5006 iflib_device_iov_uninit(device_t dev)
5008 if_ctx_t ctx = device_get_softc(dev);
5011 IFDI_IOV_UNINIT(ctx);
5016 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5019 if_ctx_t ctx = device_get_softc(dev);
5022 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5028 /*********************************************************************
5030 * MODULE FUNCTION DEFINITIONS
5032 **********************************************************************/
5035 * - Start a fast taskqueue thread for each core
5036 * - Start a taskqueue for control operations
5039 iflib_module_init(void)
5045 iflib_module_event_handler(module_t mod, int what, void *arg)
5051 if ((err = iflib_module_init()) != 0)
5057 return (EOPNOTSUPP);
5063 /*********************************************************************
5065 * PUBLIC FUNCTION DEFINITIONS
5066 * ordered as in iflib.h
5068 **********************************************************************/
5072 _iflib_assert(if_shared_ctx_t sctx)
5074 MPASS(sctx->isc_tx_maxsize);
5075 MPASS(sctx->isc_tx_maxsegsize);
5077 MPASS(sctx->isc_rx_maxsize);
5078 MPASS(sctx->isc_rx_nsegments);
5079 MPASS(sctx->isc_rx_maxsegsize);
5081 MPASS(sctx->isc_nrxd_min[0]);
5082 MPASS(sctx->isc_nrxd_max[0]);
5083 MPASS(sctx->isc_nrxd_default[0]);
5084 MPASS(sctx->isc_ntxd_min[0]);
5085 MPASS(sctx->isc_ntxd_max[0]);
5086 MPASS(sctx->isc_ntxd_default[0]);
5090 _iflib_pre_assert(if_softc_ctx_t scctx)
5093 MPASS(scctx->isc_txrx->ift_txd_encap);
5094 MPASS(scctx->isc_txrx->ift_txd_flush);
5095 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5096 MPASS(scctx->isc_txrx->ift_rxd_available);
5097 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5098 MPASS(scctx->isc_txrx->ift_rxd_refill);
5099 MPASS(scctx->isc_txrx->ift_rxd_flush);
5103 iflib_register(if_ctx_t ctx)
5105 if_shared_ctx_t sctx = ctx->ifc_sctx;
5106 driver_t *driver = sctx->isc_driver;
5107 device_t dev = ctx->ifc_dev;
5110 _iflib_assert(sctx);
5113 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5114 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5116 device_printf(dev, "can not allocate ifnet structure\n");
5121 * Initialize our context's device specific methods
5123 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5124 kobj_class_compile((kobj_class_t) driver);
5127 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5128 if_setsoftc(ifp, ctx);
5129 if_setdev(ifp, dev);
5130 if_setinitfn(ifp, iflib_if_init);
5131 if_setioctlfn(ifp, iflib_if_ioctl);
5133 if_setstartfn(ifp, iflib_altq_if_start);
5134 if_settransmitfn(ifp, iflib_altq_if_transmit);
5135 if_setsendqready(ifp);
5137 if_settransmitfn(ifp, iflib_if_transmit);
5139 if_setqflushfn(ifp, iflib_if_qflush);
5140 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5142 ctx->ifc_vlan_attach_event =
5143 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5144 EVENTHANDLER_PRI_FIRST);
5145 ctx->ifc_vlan_detach_event =
5146 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5147 EVENTHANDLER_PRI_FIRST);
5149 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5150 iflib_media_change, iflib_media_status);
5157 iflib_queues_alloc(if_ctx_t ctx)
5159 if_shared_ctx_t sctx = ctx->ifc_sctx;
5160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5161 device_t dev = ctx->ifc_dev;
5162 int nrxqsets = scctx->isc_nrxqsets;
5163 int ntxqsets = scctx->isc_ntxqsets;
5166 iflib_fl_t fl = NULL;
5167 int i, j, cpu, err, txconf, rxconf;
5168 iflib_dma_info_t ifdip;
5169 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5170 uint32_t *txqsizes = scctx->isc_txqsizes;
5171 uint8_t nrxqs = sctx->isc_nrxqs;
5172 uint8_t ntxqs = sctx->isc_ntxqs;
5173 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5177 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5178 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5180 /* Allocate the TX ring struct memory */
5181 if (!(ctx->ifc_txqs =
5182 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5183 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5184 device_printf(dev, "Unable to allocate TX ring memory\n");
5189 /* Now allocate the RX */
5190 if (!(ctx->ifc_rxqs =
5191 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5192 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5193 device_printf(dev, "Unable to allocate RX ring memory\n");
5198 txq = ctx->ifc_txqs;
5199 rxq = ctx->ifc_rxqs;
5202 * XXX handle allocation failure
5204 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5205 /* Set up some basics */
5207 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5208 device_printf(dev, "failed to allocate iflib_dma_info\n");
5212 txq->ift_ifdi = ifdip;
5213 for (j = 0; j < ntxqs; j++, ifdip++) {
5214 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5215 device_printf(dev, "Unable to allocate Descriptor memory\n");
5219 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5220 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5224 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5225 txq->ift_br_offset = 1;
5227 txq->ift_br_offset = 0;
5230 txq->ift_timer.c_cpu = cpu;
5232 if (iflib_txsd_alloc(txq)) {
5233 device_printf(dev, "Critical Failure setting up TX buffers\n");
5238 /* Initialize the TX lock */
5239 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5240 device_get_nameunit(dev), txq->ift_id);
5241 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5242 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5244 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5245 device_get_nameunit(dev), txq->ift_id);
5247 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5248 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5250 /* XXX free any allocated rings */
5251 device_printf(dev, "Unable to allocate buf_ring\n");
5256 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5257 /* Set up some basics */
5259 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5260 device_printf(dev, "failed to allocate iflib_dma_info\n");
5265 rxq->ifr_ifdi = ifdip;
5266 /* XXX this needs to be changed if #rx queues != #tx queues */
5267 rxq->ifr_ntxqirq = 1;
5268 rxq->ifr_txqid[0] = i;
5269 for (j = 0; j < nrxqs; j++, ifdip++) {
5270 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5271 device_printf(dev, "Unable to allocate Descriptor memory\n");
5275 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5279 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5280 rxq->ifr_fl_offset = 1;
5282 rxq->ifr_fl_offset = 0;
5284 rxq->ifr_nfl = nfree_lists;
5286 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5287 device_printf(dev, "Unable to allocate free list memory\n");
5292 for (j = 0; j < nfree_lists; j++) {
5293 fl[j].ifl_rxq = rxq;
5295 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5296 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5298 /* Allocate receive buffers for the ring */
5299 if (iflib_rxsd_alloc(rxq)) {
5301 "Critical Failure setting up receive buffers\n");
5306 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5307 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5312 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5313 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5314 for (i = 0; i < ntxqsets; i++) {
5315 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5317 for (j = 0; j < ntxqs; j++, di++) {
5318 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5319 paddrs[i*ntxqs + j] = di->idi_paddr;
5322 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5323 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5324 iflib_tx_structures_free(ctx);
5325 free(vaddrs, M_IFLIB);
5326 free(paddrs, M_IFLIB);
5329 free(vaddrs, M_IFLIB);
5330 free(paddrs, M_IFLIB);
5333 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5334 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5335 for (i = 0; i < nrxqsets; i++) {
5336 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5338 for (j = 0; j < nrxqs; j++, di++) {
5339 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5340 paddrs[i*nrxqs + j] = di->idi_paddr;
5343 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5344 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5345 iflib_tx_structures_free(ctx);
5346 free(vaddrs, M_IFLIB);
5347 free(paddrs, M_IFLIB);
5350 free(vaddrs, M_IFLIB);
5351 free(paddrs, M_IFLIB);
5355 /* XXX handle allocation failure changes */
5359 if (ctx->ifc_rxqs != NULL)
5360 free(ctx->ifc_rxqs, M_IFLIB);
5361 ctx->ifc_rxqs = NULL;
5362 if (ctx->ifc_txqs != NULL)
5363 free(ctx->ifc_txqs, M_IFLIB);
5364 ctx->ifc_txqs = NULL;
5370 iflib_tx_structures_setup(if_ctx_t ctx)
5372 iflib_txq_t txq = ctx->ifc_txqs;
5375 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5376 iflib_txq_setup(txq);
5382 iflib_tx_structures_free(if_ctx_t ctx)
5384 iflib_txq_t txq = ctx->ifc_txqs;
5385 if_shared_ctx_t sctx = ctx->ifc_sctx;
5388 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5389 iflib_txq_destroy(txq);
5390 for (j = 0; j < sctx->isc_ntxqs; j++)
5391 iflib_dma_free(&txq->ift_ifdi[j]);
5393 free(ctx->ifc_txqs, M_IFLIB);
5394 ctx->ifc_txqs = NULL;
5395 IFDI_QUEUES_FREE(ctx);
5398 /*********************************************************************
5400 * Initialize all receive rings.
5402 **********************************************************************/
5404 iflib_rx_structures_setup(if_ctx_t ctx)
5406 iflib_rxq_t rxq = ctx->ifc_rxqs;
5408 #if defined(INET6) || defined(INET)
5412 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5413 #if defined(INET6) || defined(INET)
5414 tcp_lro_free(&rxq->ifr_lc);
5415 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5416 TCP_LRO_ENTRIES, min(1024,
5417 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5418 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5421 rxq->ifr_lro_enabled = TRUE;
5423 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5426 #if defined(INET6) || defined(INET)
5429 * Free RX software descriptors allocated so far, we will only handle
5430 * the rings that completed, the failing case will have
5431 * cleaned up for itself. 'q' failed, so its the terminus.
5433 rxq = ctx->ifc_rxqs;
5434 for (i = 0; i < q; ++i, rxq++) {
5435 iflib_rx_sds_free(rxq);
5436 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5442 /*********************************************************************
5444 * Free all receive rings.
5446 **********************************************************************/
5448 iflib_rx_structures_free(if_ctx_t ctx)
5450 iflib_rxq_t rxq = ctx->ifc_rxqs;
5452 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5453 iflib_rx_sds_free(rxq);
5455 free(ctx->ifc_rxqs, M_IFLIB);
5456 ctx->ifc_rxqs = NULL;
5460 iflib_qset_structures_setup(if_ctx_t ctx)
5465 * It is expected that the caller takes care of freeing queues if this
5468 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5469 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5473 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5474 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5480 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5481 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5484 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5489 find_nth(if_ctx_t ctx, int qid)
5492 int i, cpuid, eqid, count;
5494 CPU_COPY(&ctx->ifc_cpus, &cpus);
5495 count = CPU_COUNT(&cpus);
5497 /* clear up to the qid'th bit */
5498 for (i = 0; i < eqid; i++) {
5499 cpuid = CPU_FFS(&cpus);
5501 CPU_CLR(cpuid-1, &cpus);
5503 cpuid = CPU_FFS(&cpus);
5509 extern struct cpu_group *cpu_top; /* CPU topology */
5512 find_child_with_core(int cpu, struct cpu_group *grp)
5516 if (grp->cg_children == 0)
5519 MPASS(grp->cg_child);
5520 for (i = 0; i < grp->cg_children; i++) {
5521 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5529 * Find the nth "close" core to the specified core
5530 * "close" is defined as the deepest level that shares
5531 * at least an L2 cache. With threads, this will be
5532 * threads on the same core. If the sahred cache is L3
5533 * or higher, simply returns the same core.
5536 find_close_core(int cpu, int core_offset)
5538 struct cpu_group *grp;
5547 while ((i = find_child_with_core(cpu, grp)) != -1) {
5548 /* If the child only has one cpu, don't descend */
5549 if (grp->cg_child[i].cg_count <= 1)
5551 grp = &grp->cg_child[i];
5554 /* If they don't share at least an L2 cache, use the same CPU */
5555 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5559 CPU_COPY(&grp->cg_mask, &cs);
5561 /* Add the selected CPU offset to core offset. */
5562 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5563 if (fcpu - 1 == cpu)
5565 CPU_CLR(fcpu - 1, &cs);
5571 CPU_COPY(&grp->cg_mask, &cs);
5572 for (i = core_offset % grp->cg_count; i > 0; i--) {
5573 MPASS(CPU_FFS(&cs));
5574 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5576 MPASS(CPU_FFS(&cs));
5577 return CPU_FFS(&cs) - 1;
5581 find_close_core(int cpu, int core_offset __unused)
5588 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5592 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5593 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5594 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5596 case IFLIB_INTR_RXTX:
5597 /* RX queues get the specified core */
5598 return qid / CPU_COUNT(&ctx->ifc_cpus);
5604 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5605 #define find_close_core(cpuid, tid) CPU_FIRST()
5606 #define find_nth(ctx, gid) CPU_FIRST()
5609 /* Just to avoid copy/paste */
5611 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5612 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5617 cpuid = find_nth(ctx, qid);
5618 tid = get_core_offset(ctx, type, qid);
5620 cpuid = find_close_core(cpuid, tid);
5621 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5623 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5627 if (cpuid > ctx->ifc_cpuid_highest)
5628 ctx->ifc_cpuid_highest = cpuid;
5634 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5635 iflib_intr_type_t type, driver_filter_t *filter,
5636 void *filter_arg, int qid, const char *name)
5638 struct grouptask *gtask;
5639 struct taskqgroup *tqg;
5640 iflib_filter_info_t info;
5643 driver_filter_t *intr_fast;
5646 info = &ctx->ifc_filter_info;
5650 /* XXX merge tx/rx for netmap? */
5652 q = &ctx->ifc_txqs[qid];
5653 info = &ctx->ifc_txqs[qid].ift_filter_info;
5654 gtask = &ctx->ifc_txqs[qid].ift_task;
5655 tqg = qgroup_if_io_tqg;
5657 intr_fast = iflib_fast_intr;
5658 GROUPTASK_INIT(gtask, 0, fn, q);
5659 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5662 q = &ctx->ifc_rxqs[qid];
5663 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5664 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5665 tqg = qgroup_if_io_tqg;
5667 intr_fast = iflib_fast_intr;
5668 GROUPTASK_INIT(gtask, 0, fn, q);
5670 case IFLIB_INTR_RXTX:
5671 q = &ctx->ifc_rxqs[qid];
5672 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5673 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5674 tqg = qgroup_if_io_tqg;
5676 intr_fast = iflib_fast_intr_rxtx;
5677 GROUPTASK_INIT(gtask, 0, fn, q);
5679 case IFLIB_INTR_ADMIN:
5682 info = &ctx->ifc_filter_info;
5683 gtask = &ctx->ifc_admin_task;
5684 tqg = qgroup_if_config_tqg;
5685 fn = _task_fn_admin;
5686 intr_fast = iflib_fast_intr_ctx;
5689 panic("unknown net intr type");
5692 info->ifi_filter = filter;
5693 info->ifi_filter_arg = filter_arg;
5694 info->ifi_task = gtask;
5697 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5699 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5702 if (type == IFLIB_INTR_ADMIN)
5706 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5710 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5717 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5719 struct grouptask *gtask;
5720 struct taskqgroup *tqg;
5728 q = &ctx->ifc_txqs[qid];
5729 gtask = &ctx->ifc_txqs[qid].ift_task;
5730 tqg = qgroup_if_io_tqg;
5733 irq_num = rman_get_start(irq->ii_res);
5736 q = &ctx->ifc_rxqs[qid];
5737 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5738 tqg = qgroup_if_io_tqg;
5741 irq_num = rman_get_start(irq->ii_res);
5743 case IFLIB_INTR_IOV:
5745 gtask = &ctx->ifc_vflr_task;
5746 tqg = qgroup_if_config_tqg;
5750 panic("unknown net intr type");
5752 GROUPTASK_INIT(gtask, 0, fn, q);
5753 if (irq_num != -1) {
5754 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5756 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5759 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5764 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5767 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5770 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5774 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5776 iflib_txq_t txq = ctx->ifc_txqs;
5777 iflib_rxq_t rxq = ctx->ifc_rxqs;
5778 if_irq_t irq = &ctx->ifc_legacy_irq;
5779 iflib_filter_info_t info;
5780 struct grouptask *gtask;
5781 struct taskqgroup *tqg;
5787 q = &ctx->ifc_rxqs[0];
5788 info = &rxq[0].ifr_filter_info;
5789 gtask = &rxq[0].ifr_task;
5790 tqg = qgroup_if_io_tqg;
5791 tqrid = irq->ii_rid = *rid;
5794 ctx->ifc_flags |= IFC_LEGACY;
5795 info->ifi_filter = filter;
5796 info->ifi_filter_arg = filter_arg;
5797 info->ifi_task = gtask;
5798 info->ifi_ctx = ctx;
5800 /* We allocate a single interrupt resource */
5801 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5803 GROUPTASK_INIT(gtask, 0, fn, q);
5804 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5806 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5807 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5812 iflib_led_create(if_ctx_t ctx)
5815 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5816 device_get_nameunit(ctx->ifc_dev));
5820 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5823 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5827 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5830 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5834 iflib_admin_intr_deferred(if_ctx_t ctx)
5837 struct grouptask *gtask;
5839 gtask = &ctx->ifc_admin_task;
5840 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5843 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5847 iflib_iov_intr_deferred(if_ctx_t ctx)
5850 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5854 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5857 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5861 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5865 GROUPTASK_INIT(gtask, 0, fn, ctx);
5866 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5870 iflib_config_gtask_deinit(struct grouptask *gtask)
5873 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5877 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5879 if_t ifp = ctx->ifc_ifp;
5880 iflib_txq_t txq = ctx->ifc_txqs;
5882 if_setbaudrate(ifp, baudrate);
5883 if (baudrate >= IF_Gbps(10)) {
5885 ctx->ifc_flags |= IFC_PREFETCH;
5888 /* If link down, disable watchdog */
5889 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5890 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5891 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5893 ctx->ifc_link_state = link_state;
5894 if_link_state_change(ifp, link_state);
5898 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5902 int credits_pre = txq->ift_cidx_processed;
5905 if (ctx->isc_txd_credits_update == NULL)
5908 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
5909 BUS_DMASYNC_POSTREAD);
5910 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5913 txq->ift_processed += credits;
5914 txq->ift_cidx_processed += credits;
5916 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5917 if (txq->ift_cidx_processed >= txq->ift_size)
5918 txq->ift_cidx_processed -= txq->ift_size;
5923 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5926 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5931 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5932 const char *description, if_int_delay_info_t info,
5933 int offset, int value)
5935 info->iidi_ctx = ctx;
5936 info->iidi_offset = offset;
5937 info->iidi_value = value;
5938 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5939 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5940 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5941 info, 0, iflib_sysctl_int_delay, "I", description);
5945 iflib_ctx_lock_get(if_ctx_t ctx)
5948 return (&ctx->ifc_ctx_sx);
5952 iflib_msix_init(if_ctx_t ctx)
5954 device_t dev = ctx->ifc_dev;
5955 if_shared_ctx_t sctx = ctx->ifc_sctx;
5956 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5957 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5958 int iflib_num_tx_queues, iflib_num_rx_queues;
5959 int err, admincnt, bar;
5961 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5962 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5964 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5966 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5967 admincnt = sctx->isc_admin_intrcnt;
5968 /* Override by tuneable */
5969 if (scctx->isc_disable_msix)
5973 * bar == -1 => "trust me I know what I'm doing"
5974 * Some drivers are for hardware that is so shoddily
5975 * documented that no one knows which bars are which
5976 * so the developer has to map all bars. This hack
5977 * allows shoddy garbage to use msix in this framework.
5980 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5981 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5982 if (ctx->ifc_msix_mem == NULL) {
5983 /* May not be enabled */
5984 device_printf(dev, "Unable to map MSIX table \n");
5988 /* First try MSI/X */
5989 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5990 device_printf(dev, "System has MSIX disabled \n");
5991 bus_release_resource(dev, SYS_RES_MEMORY,
5992 bar, ctx->ifc_msix_mem);
5993 ctx->ifc_msix_mem = NULL;
5997 /* use only 1 qset in debug mode */
5998 queuemsgs = min(msgs - admincnt, 1);
6000 queuemsgs = msgs - admincnt;
6003 queues = imin(queuemsgs, rss_getnumbuckets());
6007 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6008 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
6009 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6011 /* If we're doing RSS, clamp at the number of RSS buckets */
6012 if (queues > rss_getnumbuckets())
6013 queues = rss_getnumbuckets();
6015 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6016 rx_queues = iflib_num_rx_queues;
6020 if (rx_queues > scctx->isc_nrxqsets)
6021 rx_queues = scctx->isc_nrxqsets;
6024 * We want this to be all logical CPUs by default
6026 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6027 tx_queues = iflib_num_tx_queues;
6029 tx_queues = mp_ncpus;
6031 if (tx_queues > scctx->isc_ntxqsets)
6032 tx_queues = scctx->isc_ntxqsets;
6034 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6036 if (tx_queues != rx_queues)
6038 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6039 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6041 tx_queues = min(rx_queues, tx_queues);
6042 rx_queues = min(rx_queues, tx_queues);
6045 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
6047 vectors = rx_queues + admincnt;
6048 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6049 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors);
6050 scctx->isc_vectors = vectors;
6051 scctx->isc_nrxqsets = rx_queues;
6052 scctx->isc_ntxqsets = tx_queues;
6053 scctx->isc_intr = IFLIB_INTR_MSIX;
6058 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
6059 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6061 ctx->ifc_msix_mem = NULL;
6064 vectors = pci_msi_count(dev);
6065 scctx->isc_nrxqsets = 1;
6066 scctx->isc_ntxqsets = 1;
6067 scctx->isc_vectors = vectors;
6068 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6069 device_printf(dev,"Using an MSI interrupt\n");
6070 scctx->isc_intr = IFLIB_INTR_MSI;
6072 scctx->isc_vectors = 1;
6073 device_printf(dev,"Using a Legacy interrupt\n");
6074 scctx->isc_intr = IFLIB_INTR_LEGACY;
6080 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6083 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6086 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6088 const char *ring_state = "UNKNOWN";
6091 rc = sysctl_wire_old_buffer(req, 0);
6095 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6100 ring_state = ring_states[state[3]];
6102 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6103 state[0], state[1], state[2], ring_state);
6104 rc = sbuf_finish(sb);
6109 enum iflib_ndesc_handler {
6115 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6117 if_ctx_t ctx = (void *)arg1;
6118 enum iflib_ndesc_handler type = arg2;
6119 char buf[256] = {0};
6124 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6128 case IFLIB_NTXD_HANDLER:
6129 ndesc = ctx->ifc_sysctl_ntxds;
6131 nqs = ctx->ifc_sctx->isc_ntxqs;
6133 case IFLIB_NRXD_HANDLER:
6134 ndesc = ctx->ifc_sysctl_nrxds;
6136 nqs = ctx->ifc_sctx->isc_nrxqs;
6139 panic("unhandled type");
6144 for (i=0; i<8; i++) {
6149 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6152 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6153 if (rc || req->newptr == NULL)
6156 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6157 i++, p = strsep(&next, " ,")) {
6158 ndesc[i] = strtoul(p, NULL, 10);
6164 #define NAME_BUFLEN 32
6166 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6168 device_t dev = iflib_get_dev(ctx);
6169 struct sysctl_oid_list *child, *oid_list;
6170 struct sysctl_ctx_list *ctx_list;
6171 struct sysctl_oid *node;
6173 ctx_list = device_get_sysctl_ctx(dev);
6174 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6175 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6176 CTLFLAG_RD, NULL, "IFLIB fields");
6177 oid_list = SYSCTL_CHILDREN(node);
6179 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6180 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6183 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6184 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6185 "# of txqs to use, 0 => use default #");
6186 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6187 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6188 "# of rxqs to use, 0 => use default #");
6189 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6190 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6191 "permit #txq != #rxq");
6192 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6193 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6194 "disable MSIX (default 0)");
6195 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6196 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6197 "set the rx budget");
6198 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6199 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6200 "cause tx to abdicate instead of running to completion");
6202 /* XXX change for per-queue sizes */
6203 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6204 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6205 mp_ndesc_handler, "A",
6206 "list of # of tx descriptors to use, 0 = use default #");
6207 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6208 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6209 mp_ndesc_handler, "A",
6210 "list of # of rx descriptors to use, 0 = use default #");
6214 iflib_add_device_sysctl_post(if_ctx_t ctx)
6216 if_shared_ctx_t sctx = ctx->ifc_sctx;
6217 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6218 device_t dev = iflib_get_dev(ctx);
6219 struct sysctl_oid_list *child;
6220 struct sysctl_ctx_list *ctx_list;
6225 char namebuf[NAME_BUFLEN];
6227 struct sysctl_oid *queue_node, *fl_node, *node;
6228 struct sysctl_oid_list *queue_list, *fl_list;
6229 ctx_list = device_get_sysctl_ctx(dev);
6231 node = ctx->ifc_sysctl_node;
6232 child = SYSCTL_CHILDREN(node);
6234 if (scctx->isc_ntxqsets > 100)
6236 else if (scctx->isc_ntxqsets > 10)
6240 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6241 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6242 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6243 CTLFLAG_RD, NULL, "Queue Name");
6244 queue_list = SYSCTL_CHILDREN(queue_node);
6246 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6248 &txq->ift_dequeued, "total mbufs freed");
6249 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6251 &txq->ift_enqueued, "total mbufs enqueued");
6253 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6255 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6256 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6258 &txq->ift_pullups, "# of times m_pullup was called");
6259 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6261 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6262 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6264 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6265 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6267 &txq->ift_map_failed, "# of times dma map failed");
6268 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6270 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6271 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6273 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6274 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6276 &txq->ift_pidx, 1, "Producer Index");
6277 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6279 &txq->ift_cidx, 1, "Consumer Index");
6280 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6282 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6283 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6285 &txq->ift_in_use, 1, "descriptors in use");
6286 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6288 &txq->ift_processed, "descriptors procesed for clean");
6289 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6291 &txq->ift_cleaned, "total cleaned");
6292 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6293 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6294 0, mp_ring_state_handler, "A", "soft ring state");
6295 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6296 CTLFLAG_RD, &txq->ift_br->enqueues,
6297 "# of enqueues to the mp_ring for this queue");
6298 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6299 CTLFLAG_RD, &txq->ift_br->drops,
6300 "# of drops in the mp_ring for this queue");
6301 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6302 CTLFLAG_RD, &txq->ift_br->starts,
6303 "# of normal consumer starts in the mp_ring for this queue");
6304 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6305 CTLFLAG_RD, &txq->ift_br->stalls,
6306 "# of consumer stalls in the mp_ring for this queue");
6307 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6308 CTLFLAG_RD, &txq->ift_br->restarts,
6309 "# of consumer restarts in the mp_ring for this queue");
6310 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6311 CTLFLAG_RD, &txq->ift_br->abdications,
6312 "# of consumer abdications in the mp_ring for this queue");
6315 if (scctx->isc_nrxqsets > 100)
6317 else if (scctx->isc_nrxqsets > 10)
6321 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6322 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6323 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6324 CTLFLAG_RD, NULL, "Queue Name");
6325 queue_list = SYSCTL_CHILDREN(queue_node);
6326 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6327 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6329 &rxq->ifr_cq_pidx, 1, "Producer Index");
6330 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6332 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6335 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6336 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6337 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6338 CTLFLAG_RD, NULL, "freelist Name");
6339 fl_list = SYSCTL_CHILDREN(fl_node);
6340 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6342 &fl->ifl_pidx, 1, "Producer Index");
6343 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6345 &fl->ifl_cidx, 1, "Consumer Index");
6346 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6348 &fl->ifl_credits, 1, "credits available");
6350 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6352 &fl->ifl_m_enqueued, "mbufs allocated");
6353 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6355 &fl->ifl_m_dequeued, "mbufs freed");
6356 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6358 &fl->ifl_cl_enqueued, "clusters allocated");
6359 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6361 &fl->ifl_cl_dequeued, "clusters freed");
6370 iflib_request_reset(if_ctx_t ctx)
6374 ctx->ifc_flags |= IFC_DO_RESET;
6378 #ifndef __NO_STRICT_ALIGNMENT
6379 static struct mbuf *
6380 iflib_fixup_rx(struct mbuf *m)
6384 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6385 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6386 m->m_data += ETHER_HDR_LEN;
6389 MGETHDR(n, M_NOWAIT, MT_DATA);
6394 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6395 m->m_data += ETHER_HDR_LEN;
6396 m->m_len -= ETHER_HDR_LEN;
6397 n->m_len = ETHER_HDR_LEN;
6398 M_MOVE_PKTHDR(n, m);
6407 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6411 ctx = if_getsoftc(ifp);
6413 *nrxr = NRXQSETS(ctx);
6414 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6415 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6420 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6423 if_softc_ctx_t scctx;
6428 ctx = if_getsoftc(ifp);
6429 scctx = &ctx->ifc_softc_ctx;
6433 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6434 rxq = &ctx->ifc_rxqs[i];
6435 for (j = 0; j < rxq->ifr_nfl; j++) {
6437 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6440 iflib_no_tx_batch = 1;
6448 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6454 ctx = if_getsoftc(ifp);
6455 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6459 txq = &ctx->ifc_txqs[0];
6460 error = iflib_encap(txq, &m);
6462 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6467 iflib_netdump_poll(struct ifnet *ifp, int count)
6470 if_softc_ctx_t scctx;
6474 ctx = if_getsoftc(ifp);
6475 scctx = &ctx->ifc_softc_ctx;
6477 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6481 txq = &ctx->ifc_txqs[0];
6482 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6484 for (i = 0; i < scctx->isc_nrxqsets; i++)
6485 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6488 #endif /* NETDUMP */