2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
64 #include <netinet/in.h>
65 #include <netinet/in_pcb.h>
66 #include <netinet/tcp_lro.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/if_ether.h>
69 #include <netinet/ip.h>
70 #include <netinet/ip6.h>
71 #include <netinet/tcp.h>
72 #include <netinet/ip_var.h>
73 #include <netinet6/ip6_var.h>
75 #include <machine/bus.h>
76 #include <machine/in_cksum.h>
81 #include <dev/led/led.h>
82 #include <dev/pci/pcireg.h>
83 #include <dev/pci/pcivar.h>
84 #include <dev/pci/pci_private.h>
86 #include <net/iflib.h>
90 #if defined(__i386__) || defined(__amd64__)
91 #include <sys/memdesc.h>
92 #include <machine/bus.h>
93 #include <machine/md_var.h>
94 #include <machine/specialreg.h>
95 #include <x86/include/busdma_impl.h>
96 #include <x86/iommu/busdma_dmar.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 typedef struct iflib_filter_info {
146 driver_filter_t *ifi_filter;
147 void *ifi_filter_arg;
148 struct grouptask *ifi_task;
150 } *iflib_filter_info_t;
155 * Pointer to hardware driver's softc
162 if_shared_ctx_t ifc_sctx;
163 struct if_softc_ctx ifc_softc_ctx;
167 uint16_t ifc_nhwtxqs;
168 uint16_t ifc_nhwrxqs;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
179 int ifc_watchdog_events;
180 struct cdev *ifc_led_dev;
181 struct resource *ifc_msix_mem;
183 struct if_irq ifc_legacy_irq;
184 struct grouptask ifc_admin_task;
185 struct grouptask ifc_vflr_task;
186 struct iflib_filter_info ifc_filter_info;
187 struct ifmedia ifc_media;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
195 qidx_t ifc_sysctl_ntxds[8];
196 qidx_t ifc_sysctl_nrxds[8];
197 struct if_txrx ifc_txrx;
198 #define isc_txd_encap ifc_txrx.ift_txd_encap
199 #define isc_txd_flush ifc_txrx.ift_txd_flush
200 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
201 #define isc_rxd_available ifc_txrx.ift_rxd_available
202 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
203 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
204 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
208 eventhandler_tag ifc_vlan_attach_event;
209 eventhandler_tag ifc_vlan_detach_event;
210 uint8_t ifc_mac[ETHER_ADDR_LEN];
211 char ifc_mtx_name[16];
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (&ctx->ifc_media);
244 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
247 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
251 iflib_get_softc_ctx(if_ctx_t ctx)
254 return (&ctx->ifc_softc_ctx);
258 iflib_get_sctx(if_ctx_t ctx)
261 return (ctx->ifc_sctx);
264 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
265 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
266 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
268 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
269 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
271 #define RX_SW_DESC_MAP_CREATED (1 << 0)
272 #define TX_SW_DESC_MAP_CREATED (1 << 1)
273 #define RX_SW_DESC_INUSE (1 << 3)
274 #define TX_SW_DESC_MAPPED (1 << 4)
276 #define M_TOOBIG M_PROTO1
278 typedef struct iflib_sw_rx_desc_array {
279 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
280 struct mbuf **ifsd_m; /* pkthdr mbufs */
281 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
283 } iflib_rxsd_array_t;
285 typedef struct iflib_sw_tx_desc_array {
286 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
292 /* magic number that should be high enough for any hardware */
293 #define IFLIB_MAX_TX_SEGS 128
294 /* bnxt supports 64 with hardware LRO enabled */
295 #define IFLIB_MAX_RX_SEGS 64
296 #define IFLIB_RX_COPY_THRESH 128
297 #define IFLIB_MAX_RX_REFRESH 32
298 /* The minimum descriptors per second before we start coalescing */
299 #define IFLIB_MIN_DESC_SEC 16384
300 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
301 #define IFLIB_QUEUE_IDLE 0
302 #define IFLIB_QUEUE_HUNG 1
303 #define IFLIB_QUEUE_WORKING 2
304 /* maximum number of txqs that can share an rx interrupt */
305 #define IFLIB_MAX_TX_SHARED_INTR 4
307 /* this should really scale with ring size - this is a fairly arbitrary value */
308 #define TX_BATCH_SIZE 32
310 #define IFLIB_RESTART_BUDGET 8
312 #define IFC_LEGACY 0x001
313 #define IFC_QFLUSH 0x002
314 #define IFC_MULTISEG 0x004
315 #define IFC_DMAR 0x008
316 #define IFC_SC_ALLOCATED 0x010
317 #define IFC_INIT_DONE 0x020
318 #define IFC_PREFETCH 0x040
319 #define IFC_DO_RESET 0x080
320 #define IFC_CHECK_HUNG 0x100
322 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
323 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
324 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
328 qidx_t ift_cidx_processed;
331 uint8_t ift_br_offset;
332 uint16_t ift_npending;
333 uint16_t ift_db_pending;
334 uint16_t ift_rs_pending;
336 uint8_t ift_txd_size[8];
337 uint64_t ift_processed;
338 uint64_t ift_cleaned;
339 uint64_t ift_cleaned_prev;
341 uint64_t ift_enqueued;
342 uint64_t ift_dequeued;
344 uint64_t ift_no_tx_dma_setup;
345 uint64_t ift_no_desc_avail;
346 uint64_t ift_mbuf_defrag_failed;
347 uint64_t ift_mbuf_defrag;
348 uint64_t ift_map_failed;
349 uint64_t ift_txd_encap_efbig;
350 uint64_t ift_pullups;
353 struct mtx ift_db_mtx;
355 /* constant values */
357 struct ifmp_ring *ift_br;
358 struct grouptask ift_task;
361 struct callout ift_timer;
363 if_txsd_vec_t ift_sds;
366 uint8_t ift_update_freq;
367 struct iflib_filter_info ift_filter_info;
368 bus_dma_tag_t ift_desc_tag;
369 bus_dma_tag_t ift_tso_desc_tag;
370 iflib_dma_info_t ift_ifdi;
371 #define MTX_NAME_LEN 16
372 char ift_mtx_name[MTX_NAME_LEN];
373 char ift_db_mtx_name[MTX_NAME_LEN];
374 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
375 #ifdef IFLIB_DIAGNOSTICS
376 uint64_t ift_cpu_exec_count[256];
378 } __aligned(CACHE_LINE_SIZE);
385 uint8_t ifl_rxd_size;
387 uint64_t ifl_m_enqueued;
388 uint64_t ifl_m_dequeued;
389 uint64_t ifl_cl_enqueued;
390 uint64_t ifl_cl_dequeued;
394 bitstr_t *ifl_rx_bitmap;
398 uint16_t ifl_buf_size;
401 iflib_rxsd_array_t ifl_sds;
404 bus_dma_tag_t ifl_desc_tag;
405 iflib_dma_info_t ifl_ifdi;
406 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
407 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
408 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
409 } __aligned(CACHE_LINE_SIZE);
412 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
418 else if (pidx < cidx)
419 used = size - cidx + pidx;
420 else if (gen == 0 && pidx == cidx)
422 else if (gen == 1 && pidx == cidx)
430 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
432 #define IDXDIFF(head, tail, wrap) \
433 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
436 /* If there is a separate completion queue -
437 * these are the cq cidx and pidx. Otherwise
444 uint8_t ifr_fl_offset;
450 uint8_t ifr_lro_enabled;
453 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
454 struct lro_ctrl ifr_lc;
455 struct grouptask ifr_task;
456 struct iflib_filter_info ifr_filter_info;
457 iflib_dma_info_t ifr_ifdi;
459 /* dynamically allocate if any drivers need a value substantially larger than this */
460 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
461 #ifdef IFLIB_DIAGNOSTICS
462 uint64_t ifr_cpu_exec_count[256];
464 } __aligned(CACHE_LINE_SIZE);
466 typedef struct if_rxsd {
468 struct mbuf **ifsd_m;
473 /* multiple of word size */
475 #define PKT_INFO_SIZE 6
476 #define RXD_INFO_SIZE 5
477 #define PKT_TYPE uint64_t
479 #define PKT_INFO_SIZE 11
480 #define RXD_INFO_SIZE 8
481 #define PKT_TYPE uint32_t
483 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
484 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
486 typedef struct if_pkt_info_pad {
487 PKT_TYPE pkt_val[PKT_INFO_SIZE];
488 } *if_pkt_info_pad_t;
489 typedef struct if_rxd_info_pad {
490 PKT_TYPE rxd_val[RXD_INFO_SIZE];
491 } *if_rxd_info_pad_t;
493 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
494 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
498 pkt_info_zero(if_pkt_info_t pi)
500 if_pkt_info_pad_t pi_pad;
502 pi_pad = (if_pkt_info_pad_t)pi;
503 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
504 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
506 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
507 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
512 rxd_info_zero(if_rxd_info_t ri)
514 if_rxd_info_pad_t ri_pad;
517 ri_pad = (if_rxd_info_pad_t)ri;
518 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
519 ri_pad->rxd_val[i] = 0;
520 ri_pad->rxd_val[i+1] = 0;
521 ri_pad->rxd_val[i+2] = 0;
522 ri_pad->rxd_val[i+3] = 0;
525 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
530 * Only allow a single packet to take up most 1/nth of the tx ring
532 #define MAX_SINGLE_PACKET_FRACTION 12
533 #define IF_BAD_DMA (bus_addr_t)-1
535 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
537 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
539 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
540 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
541 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
544 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
545 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# tx mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# tx mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# tx mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# tx frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# rx allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
617 static int iflib_txq_drain_encapfail;
619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
620 &iflib_txq_drain_flushing, 0, "# drain flushes");
621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
622 &iflib_txq_drain_oactive, 0, "# drain oactives");
623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
624 &iflib_txq_drain_notready, 0, "# drain notready");
625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
626 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
629 static int iflib_encap_load_mbuf_fail;
630 static int iflib_encap_txq_avail_fail;
631 static int iflib_encap_txd_encap_fail;
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_intr_link;
644 static int iflib_intr_msix;
645 static int iflib_rx_unavail;
646 static int iflib_rx_ctx_inactive;
647 static int iflib_rx_zero_len;
648 static int iflib_rx_if_input;
649 static int iflib_rx_mbuf_null;
650 static int iflib_rxd_flush;
652 static int iflib_verbose_debug;
654 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
655 &iflib_intr_link, 0, "# intr link calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
657 &iflib_intr_msix, 0, "# intr msix calls");
658 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
659 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
661 &iflib_rx_intr_enables, 0, "# rx intr enables");
662 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
663 &iflib_fast_intrs, 0, "# fast_intr calls");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
665 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
667 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
669 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
671 &iflib_rx_if_input, 0, "# times rxeof called if_input");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
673 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
675 &iflib_rxd_flush, 0, "# times rxd_flush called");
676 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
677 &iflib_verbose_debug, 0, "enable verbose debugging");
679 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
681 iflib_debug_reset(void)
683 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
684 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
685 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
686 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
687 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail =
688 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables =
689 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
690 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
691 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
695 #define DBG_COUNTER_INC(name)
696 static void iflib_debug_reset(void) {}
701 #define IFLIB_DEBUG 0
703 static void iflib_tx_structures_free(if_ctx_t ctx);
704 static void iflib_rx_structures_free(if_ctx_t ctx);
705 static int iflib_queues_alloc(if_ctx_t ctx);
706 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
707 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
708 static int iflib_qset_structures_setup(if_ctx_t ctx);
709 static int iflib_msix_init(if_ctx_t ctx);
710 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
711 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
712 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
713 static int iflib_register(if_ctx_t);
714 static void iflib_init_locked(if_ctx_t ctx);
715 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
716 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
717 static void iflib_ifmp_purge(iflib_txq_t txq);
718 static void _iflib_pre_assert(if_softc_ctx_t scctx);
719 static void iflib_stop(if_ctx_t ctx);
720 static void iflib_if_init_locked(if_ctx_t ctx);
721 #ifndef __NO_STRICT_ALIGNMENT
722 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
726 #include <sys/selinfo.h>
727 #include <net/netmap.h>
728 #include <dev/netmap/netmap_kern.h>
730 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
732 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
735 * device-specific sysctl variables:
737 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
738 * During regular operations the CRC is stripped, but on some
739 * hardware reception of frames not multiple of 64 is slower,
740 * so using crcstrip=0 helps in benchmarks.
742 * iflib_rx_miss, iflib_rx_miss_bufs:
743 * count packets that might be missed due to lost interrupts.
745 SYSCTL_DECL(_dev_netmap);
747 * The xl driver by default strips CRCs and we do not override it.
750 int iflib_crcstrip = 1;
751 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
752 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
754 int iflib_rx_miss, iflib_rx_miss_bufs;
755 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
756 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
757 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
758 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
761 * Register/unregister. We are already under netmap lock.
762 * Only called on the first register or the last unregister.
765 iflib_netmap_register(struct netmap_adapter *na, int onoff)
767 struct ifnet *ifp = na->ifp;
768 if_ctx_t ctx = ifp->if_softc;
772 IFDI_INTR_DISABLE(ctx);
774 /* Tell the stack that the interface is no longer active */
775 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
778 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
780 /* enable or disable flags and callbacks in na and ifp */
782 nm_set_native_flags(na);
784 nm_clear_native_flags(na);
787 iflib_init_locked(ctx);
788 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
789 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
791 nm_clear_native_flags(na);
797 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
799 struct netmap_adapter *na = kring->na;
800 u_int const lim = kring->nkr_num_slots - 1;
801 u_int head = kring->rhead;
802 struct netmap_ring *ring = kring->ring;
804 struct if_rxd_update iru;
805 if_ctx_t ctx = rxq->ifr_ctx;
806 iflib_fl_t fl = &rxq->ifr_fl[0];
807 uint32_t refill_pidx, nic_i;
809 if (nm_i == head && __predict_true(!init))
811 iru_init(&iru, rxq, 0 /* flid */);
812 map = fl->ifl_sds.ifsd_map;
813 refill_pidx = netmap_idx_k2n(kring, nm_i);
815 * IMPORTANT: we must leave one free slot in the ring,
816 * so move head back by one unit
818 head = nm_prev(head, lim);
819 while (nm_i != head) {
820 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
821 struct netmap_slot *slot = &ring->slot[nm_i];
822 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
823 uint32_t nic_i_dma = refill_pidx;
824 nic_i = netmap_idx_k2n(kring, nm_i);
826 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
828 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
829 return netmap_ring_reinit(kring);
831 fl->ifl_vm_addrs[tmp_pidx] = addr;
832 if (__predict_false(init) && map) {
833 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
834 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
835 /* buffer has changed, reload map */
836 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
838 slot->flags &= ~NS_BUF_CHANGED;
840 nm_i = nm_next(nm_i, lim);
841 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
842 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
845 iru.iru_pidx = refill_pidx;
846 iru.iru_count = tmp_pidx+1;
847 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
853 for (int n = 0; n < iru.iru_count; n++) {
854 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
855 BUS_DMASYNC_PREREAD);
856 /* XXX - change this to not use the netmap func*/
857 nic_i_dma = nm_next(nic_i_dma, lim);
861 kring->nr_hwcur = head;
864 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
865 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
866 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
871 * Reconcile kernel and user view of the transmit ring.
873 * All information is in the kring.
874 * Userspace wants to send packets up to the one before kring->rhead,
875 * kernel knows kring->nr_hwcur is the first unsent packet.
877 * Here we push packets out (as many as possible), and possibly
878 * reclaim buffers from previously completed transmission.
880 * The caller (netmap) guarantees that there is only one instance
881 * running at any time. Any interference with other driver
882 * methods should be handled by the individual drivers.
885 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
887 struct netmap_adapter *na = kring->na;
888 struct ifnet *ifp = na->ifp;
889 struct netmap_ring *ring = kring->ring;
890 u_int nm_i; /* index into the netmap ring */
891 u_int nic_i; /* index into the NIC ring */
893 u_int const lim = kring->nkr_num_slots - 1;
894 u_int const head = kring->rhead;
895 struct if_pkt_info pi;
898 * interrupts on every tx packet are expensive so request
899 * them every half ring, or where NS_REPORT is set
901 u_int report_frequency = kring->nkr_num_slots >> 1;
902 /* device-specific */
903 if_ctx_t ctx = ifp->if_softc;
904 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
906 if (txq->ift_sds.ifsd_map)
907 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
908 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
912 * First part: process new packets to send.
913 * nm_i is the current index in the netmap ring,
914 * nic_i is the corresponding index in the NIC ring.
916 * If we have packets to send (nm_i != head)
917 * iterate over the netmap ring, fetch length and update
918 * the corresponding slot in the NIC ring. Some drivers also
919 * need to update the buffer's physical address in the NIC slot
920 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
922 * The netmap_reload_map() calls is especially expensive,
923 * even when (as in this case) the tag is 0, so do only
924 * when the buffer has actually changed.
926 * If possible do not set the report/intr bit on all slots,
927 * but only a few times per ring or when NS_REPORT is set.
929 * Finally, on 10G and faster drivers, it might be useful
930 * to prefetch the next slot and txr entry.
933 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
935 pi.ipi_segs = txq->ift_segs;
936 pi.ipi_qsidx = kring->ring_id;
937 if (nm_i != head) { /* we have new packets to send */
938 nic_i = netmap_idx_k2n(kring, nm_i);
940 __builtin_prefetch(&ring->slot[nm_i]);
941 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
942 if (txq->ift_sds.ifsd_map)
943 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
945 for (n = 0; nm_i != head; n++) {
946 struct netmap_slot *slot = &ring->slot[nm_i];
947 u_int len = slot->len;
949 void *addr = PNMB(na, slot, &paddr);
950 int flags = (slot->flags & NS_REPORT ||
951 nic_i == 0 || nic_i == report_frequency) ?
954 /* device-specific */
956 pi.ipi_segs[0].ds_addr = paddr;
957 pi.ipi_segs[0].ds_len = len;
961 pi.ipi_flags = flags;
963 /* Fill the slot in the NIC ring. */
964 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
966 /* prefetch for next round */
967 __builtin_prefetch(&ring->slot[nm_i + 1]);
968 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
969 if (txq->ift_sds.ifsd_map) {
970 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
972 NM_CHECK_ADDR_LEN(na, addr, len);
974 if (slot->flags & NS_BUF_CHANGED) {
975 /* buffer has changed, reload map */
976 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
978 /* make sure changes to the buffer are synced */
979 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
980 BUS_DMASYNC_PREWRITE);
982 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
983 nm_i = nm_next(nm_i, lim);
984 nic_i = nm_next(nic_i, lim);
986 kring->nr_hwcur = head;
988 /* synchronize the NIC ring */
989 if (txq->ift_sds.ifsd_map)
990 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
993 /* (re)start the tx unit up to slot nic_i (excluded) */
994 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
998 * Second part: reclaim buffers for completed transmissions.
1000 if (iflib_tx_credits_update(ctx, txq)) {
1001 /* some tx completed, increment avail */
1002 nic_i = txq->ift_cidx_processed;
1003 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1009 * Reconcile kernel and user view of the receive ring.
1010 * Same as for the txsync, this routine must be efficient.
1011 * The caller guarantees a single invocations, but races against
1012 * the rest of the driver should be handled here.
1014 * On call, kring->rhead is the first packet that userspace wants
1015 * to keep, and kring->rcur is the wakeup point.
1016 * The kernel has previously reported packets up to kring->rtail.
1018 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1019 * of whether or not we received an interrupt.
1022 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1024 struct netmap_adapter *na = kring->na;
1025 struct netmap_ring *ring = kring->ring;
1026 uint32_t nm_i; /* index into the netmap ring */
1027 uint32_t nic_i; /* index into the NIC ring */
1029 u_int const lim = kring->nkr_num_slots - 1;
1030 u_int const head = netmap_idx_n2k(kring, kring->rhead);
1031 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1032 struct if_rxd_info ri;
1034 struct ifnet *ifp = na->ifp;
1035 if_ctx_t ctx = ifp->if_softc;
1036 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1037 iflib_fl_t fl = rxq->ifr_fl;
1039 return netmap_ring_reinit(kring);
1041 /* XXX check sync modes */
1042 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1043 if (fl->ifl_sds.ifsd_map == NULL)
1045 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1046 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1049 * First part: import newly received packets.
1051 * nm_i is the index of the next free slot in the netmap ring,
1052 * nic_i is the index of the next received packet in the NIC ring,
1053 * and they may differ in case if_init() has been called while
1054 * in netmap mode. For the receive ring we have
1056 * nic_i = rxr->next_check;
1057 * nm_i = kring->nr_hwtail (previous)
1059 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1061 * rxr->next_check is set to 0 on a ring reinit
1063 if (netmap_no_pendintr || force_update) {
1064 int crclen = iflib_crcstrip ? 0 : 4;
1066 uint16_t slot_flags = kring->nkr_slot_flags;
1068 for (i = 0; i < rxq->ifr_nfl; i++) {
1069 fl = &rxq->ifr_fl[i];
1070 nic_i = fl->ifl_cidx;
1071 nm_i = netmap_idx_n2k(kring, nic_i);
1072 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1073 for (n = 0; avail > 0; n++, avail--) {
1075 ri.iri_frags = rxq->ifr_frags;
1076 ri.iri_qsidx = kring->ring_id;
1077 ri.iri_ifp = ctx->ifc_ifp;
1078 ri.iri_cidx = nic_i;
1080 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1081 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1082 ring->slot[nm_i].flags = slot_flags;
1083 if (fl->ifl_sds.ifsd_map)
1084 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1085 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1086 nm_i = nm_next(nm_i, lim);
1087 nic_i = nm_next(nic_i, lim);
1089 if (n) { /* update the state variables */
1090 if (netmap_no_pendintr && !force_update) {
1093 iflib_rx_miss_bufs += n;
1095 fl->ifl_cidx = nic_i;
1096 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i);
1098 kring->nr_kflags &= ~NKR_PENDINTR;
1102 * Second part: skip past packets that userspace has released.
1103 * (kring->nr_hwcur to head excluded),
1104 * and make the buffers available for reception.
1105 * As usual nm_i is the index in the netmap ring,
1106 * nic_i is the index in the NIC ring, and
1107 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1109 /* XXX not sure how this will work with multiple free lists */
1110 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
1112 return (netmap_fl_refill(rxq, kring, nm_i, false));
1116 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1118 struct ifnet *ifp = na->ifp;
1119 if_ctx_t ctx = ifp->if_softc;
1123 IFDI_INTR_ENABLE(ctx);
1125 IFDI_INTR_DISABLE(ctx);
1132 iflib_netmap_attach(if_ctx_t ctx)
1134 struct netmap_adapter na;
1135 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1137 bzero(&na, sizeof(na));
1139 na.ifp = ctx->ifc_ifp;
1140 na.na_flags = NAF_BDG_MAYSLEEP;
1141 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1142 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1144 na.num_tx_desc = scctx->isc_ntxd[0];
1145 na.num_rx_desc = scctx->isc_nrxd[0];
1146 na.nm_txsync = iflib_netmap_txsync;
1147 na.nm_rxsync = iflib_netmap_rxsync;
1148 na.nm_register = iflib_netmap_register;
1149 na.nm_intr = iflib_netmap_intr;
1150 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1151 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1152 return (netmap_attach(&na));
1156 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1158 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1159 struct netmap_slot *slot;
1161 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1164 if (txq->ift_sds.ifsd_map == NULL)
1167 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1170 * In netmap mode, set the map for the packet buffer.
1171 * NOTE: Some drivers (not this one) also need to set
1172 * the physical buffer address in the NIC ring.
1173 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1174 * netmap slot index, si
1176 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1177 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1182 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1184 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1185 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1186 struct netmap_slot *slot;
1189 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1192 nm_i = netmap_idx_n2k(kring, 0);
1193 netmap_fl_refill(rxq, kring, nm_i, true);
1196 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1199 #define iflib_netmap_txq_init(ctx, txq)
1200 #define iflib_netmap_rxq_init(ctx, rxq)
1201 #define iflib_netmap_detach(ifp)
1203 #define iflib_netmap_attach(ctx) (0)
1204 #define netmap_rx_irq(ifp, qid, budget) (0)
1205 #define netmap_tx_irq(ifp, qid) do {} while (0)
1209 #if defined(__i386__) || defined(__amd64__)
1210 static __inline void
1213 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1215 static __inline void
1216 prefetch2cachelines(void *x)
1218 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1219 #if (CACHE_LINE_SIZE < 128)
1220 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1225 #define prefetch2cachelines(x)
1229 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1233 fl = &rxq->ifr_fl[flid];
1234 iru->iru_paddrs = fl->ifl_bus_addrs;
1235 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1236 iru->iru_idxs = fl->ifl_rxd_idxs;
1237 iru->iru_qsidx = rxq->ifr_id;
1238 iru->iru_buf_size = fl->ifl_buf_size;
1239 iru->iru_flidx = fl->ifl_id;
1243 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1247 *(bus_addr_t *) arg = segs[0].ds_addr;
1251 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1254 if_shared_ctx_t sctx = ctx->ifc_sctx;
1255 device_t dev = ctx->ifc_dev;
1257 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1259 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1260 sctx->isc_q_align, 0, /* alignment, bounds */
1261 BUS_SPACE_MAXADDR, /* lowaddr */
1262 BUS_SPACE_MAXADDR, /* highaddr */
1263 NULL, NULL, /* filter, filterarg */
1266 size, /* maxsegsize */
1267 BUS_DMA_ALLOCNOW, /* flags */
1268 NULL, /* lockfunc */
1273 "%s: bus_dma_tag_create failed: %d\n",
1278 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1279 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1282 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1283 __func__, (uintmax_t)size, err);
1287 dma->idi_paddr = IF_BAD_DMA;
1288 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1289 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1290 if (err || dma->idi_paddr == IF_BAD_DMA) {
1292 "%s: bus_dmamap_load failed: %d\n",
1297 dma->idi_size = size;
1301 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1303 bus_dma_tag_destroy(dma->idi_tag);
1305 dma->idi_tag = NULL;
1311 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1314 iflib_dma_info_t *dmaiter;
1317 for (i = 0; i < count; i++, dmaiter++) {
1318 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1322 iflib_dma_free_multi(dmalist, i);
1327 iflib_dma_free(iflib_dma_info_t dma)
1329 if (dma->idi_tag == NULL)
1331 if (dma->idi_paddr != IF_BAD_DMA) {
1332 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1333 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1334 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1335 dma->idi_paddr = IF_BAD_DMA;
1337 if (dma->idi_vaddr != NULL) {
1338 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1339 dma->idi_vaddr = NULL;
1341 bus_dma_tag_destroy(dma->idi_tag);
1342 dma->idi_tag = NULL;
1346 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1349 iflib_dma_info_t *dmaiter = dmalist;
1351 for (i = 0; i < count; i++, dmaiter++)
1352 iflib_dma_free(*dmaiter);
1355 #ifdef EARLY_AP_STARTUP
1356 static const int iflib_started = 1;
1359 * We used to abuse the smp_started flag to decide if the queues have been
1360 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1361 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1362 * is set. Run a SYSINIT() strictly after that to just set a usable
1366 static int iflib_started;
1369 iflib_record_started(void *arg)
1374 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1375 iflib_record_started, NULL);
1379 iflib_fast_intr(void *arg)
1381 iflib_filter_info_t info = arg;
1382 struct grouptask *gtask = info->ifi_task;
1384 return (FILTER_HANDLED);
1386 DBG_COUNTER_INC(fast_intrs);
1387 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1388 return (FILTER_HANDLED);
1390 GROUPTASK_ENQUEUE(gtask);
1391 return (FILTER_HANDLED);
1395 iflib_fast_intr_rxtx(void *arg)
1397 iflib_filter_info_t info = arg;
1398 struct grouptask *gtask = info->ifi_task;
1399 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1404 return (FILTER_HANDLED);
1406 DBG_COUNTER_INC(fast_intrs);
1407 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1408 return (FILTER_HANDLED);
1410 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1411 qidx_t txqid = rxq->ifr_txqid[i];
1415 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1416 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1419 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1421 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1422 cidx = rxq->ifr_cq_cidx;
1424 cidx = rxq->ifr_fl[0].ifl_cidx;
1425 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1426 GROUPTASK_ENQUEUE(gtask);
1428 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1429 return (FILTER_HANDLED);
1434 iflib_fast_intr_ctx(void *arg)
1436 iflib_filter_info_t info = arg;
1437 struct grouptask *gtask = info->ifi_task;
1440 return (FILTER_HANDLED);
1442 DBG_COUNTER_INC(fast_intrs);
1443 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1444 return (FILTER_HANDLED);
1446 GROUPTASK_ENQUEUE(gtask);
1447 return (FILTER_HANDLED);
1451 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1452 driver_filter_t filter, driver_intr_t handler, void *arg,
1456 struct resource *res;
1458 device_t dev = ctx->ifc_dev;
1461 if (ctx->ifc_flags & IFC_LEGACY)
1462 flags |= RF_SHAREABLE;
1465 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1468 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1472 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1473 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1474 filter, handler, arg, &tag);
1477 "failed to setup interrupt for rid %d, name %s: %d\n",
1478 rid, name ? name : "unknown", rc);
1481 bus_describe_intr(dev, res, tag, "%s", name);
1488 /*********************************************************************
1490 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1491 * the information needed to transmit a packet on the wire. This is
1492 * called only once at attach, setup is done every reset.
1494 **********************************************************************/
1497 iflib_txsd_alloc(iflib_txq_t txq)
1499 if_ctx_t ctx = txq->ift_ctx;
1500 if_shared_ctx_t sctx = ctx->ifc_sctx;
1501 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1502 device_t dev = ctx->ifc_dev;
1503 int err, nsegments, ntsosegments;
1505 nsegments = scctx->isc_tx_nsegments;
1506 ntsosegments = scctx->isc_tx_tso_segments_max;
1507 MPASS(scctx->isc_ntxd[0] > 0);
1508 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1509 MPASS(nsegments > 0);
1510 MPASS(ntsosegments > 0);
1512 * Setup DMA descriptor areas.
1514 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1515 1, 0, /* alignment, bounds */
1516 BUS_SPACE_MAXADDR, /* lowaddr */
1517 BUS_SPACE_MAXADDR, /* highaddr */
1518 NULL, NULL, /* filter, filterarg */
1519 sctx->isc_tx_maxsize, /* maxsize */
1520 nsegments, /* nsegments */
1521 sctx->isc_tx_maxsegsize, /* maxsegsize */
1523 NULL, /* lockfunc */
1524 NULL, /* lockfuncarg */
1525 &txq->ift_desc_tag))) {
1526 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1527 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1528 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1531 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1532 1, 0, /* alignment, bounds */
1533 BUS_SPACE_MAXADDR, /* lowaddr */
1534 BUS_SPACE_MAXADDR, /* highaddr */
1535 NULL, NULL, /* filter, filterarg */
1536 scctx->isc_tx_tso_size_max, /* maxsize */
1537 ntsosegments, /* nsegments */
1538 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1540 NULL, /* lockfunc */
1541 NULL, /* lockfuncarg */
1542 &txq->ift_tso_desc_tag))) {
1543 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1547 if (!(txq->ift_sds.ifsd_flags =
1548 (uint8_t *) malloc(sizeof(uint8_t) *
1549 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1550 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1554 if (!(txq->ift_sds.ifsd_m =
1555 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1556 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1557 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1562 /* Create the descriptor buffer dma maps */
1563 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1564 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1567 if (!(txq->ift_sds.ifsd_map =
1568 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1569 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1574 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1575 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1577 device_printf(dev, "Unable to create TX DMA map\n");
1584 /* We free all, it handles case where we are in the middle */
1585 iflib_tx_structures_free(ctx);
1590 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1595 if (txq->ift_sds.ifsd_map != NULL)
1596 map = txq->ift_sds.ifsd_map[i];
1598 bus_dmamap_unload(txq->ift_desc_tag, map);
1599 bus_dmamap_destroy(txq->ift_desc_tag, map);
1600 txq->ift_sds.ifsd_map[i] = NULL;
1605 iflib_txq_destroy(iflib_txq_t txq)
1607 if_ctx_t ctx = txq->ift_ctx;
1609 for (int i = 0; i < txq->ift_size; i++)
1610 iflib_txsd_destroy(ctx, txq, i);
1611 if (txq->ift_sds.ifsd_map != NULL) {
1612 free(txq->ift_sds.ifsd_map, M_IFLIB);
1613 txq->ift_sds.ifsd_map = NULL;
1615 if (txq->ift_sds.ifsd_m != NULL) {
1616 free(txq->ift_sds.ifsd_m, M_IFLIB);
1617 txq->ift_sds.ifsd_m = NULL;
1619 if (txq->ift_sds.ifsd_flags != NULL) {
1620 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1621 txq->ift_sds.ifsd_flags = NULL;
1623 if (txq->ift_desc_tag != NULL) {
1624 bus_dma_tag_destroy(txq->ift_desc_tag);
1625 txq->ift_desc_tag = NULL;
1627 if (txq->ift_tso_desc_tag != NULL) {
1628 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1629 txq->ift_tso_desc_tag = NULL;
1634 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1638 mp = &txq->ift_sds.ifsd_m[i];
1642 if (txq->ift_sds.ifsd_map != NULL) {
1643 bus_dmamap_sync(txq->ift_desc_tag,
1644 txq->ift_sds.ifsd_map[i],
1645 BUS_DMASYNC_POSTWRITE);
1646 bus_dmamap_unload(txq->ift_desc_tag,
1647 txq->ift_sds.ifsd_map[i]);
1650 DBG_COUNTER_INC(tx_frees);
1655 iflib_txq_setup(iflib_txq_t txq)
1657 if_ctx_t ctx = txq->ift_ctx;
1658 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1659 iflib_dma_info_t di;
1662 /* Set number of descriptors available */
1663 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1664 /* XXX make configurable */
1665 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1668 txq->ift_cidx_processed = 0;
1669 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1670 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1672 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1673 bzero((void *)di->idi_vaddr, di->idi_size);
1675 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1676 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1677 bus_dmamap_sync(di->idi_tag, di->idi_map,
1678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1682 /*********************************************************************
1684 * Allocate memory for rx_buffer structures. Since we use one
1685 * rx_buffer per received packet, the maximum number of rx_buffer's
1686 * that we'll need is equal to the number of receive descriptors
1687 * that we've allocated.
1689 **********************************************************************/
1691 iflib_rxsd_alloc(iflib_rxq_t rxq)
1693 if_ctx_t ctx = rxq->ifr_ctx;
1694 if_shared_ctx_t sctx = ctx->ifc_sctx;
1695 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1696 device_t dev = ctx->ifc_dev;
1700 MPASS(scctx->isc_nrxd[0] > 0);
1701 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1704 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1705 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1706 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1707 1, 0, /* alignment, bounds */
1708 BUS_SPACE_MAXADDR, /* lowaddr */
1709 BUS_SPACE_MAXADDR, /* highaddr */
1710 NULL, NULL, /* filter, filterarg */
1711 sctx->isc_rx_maxsize, /* maxsize */
1712 sctx->isc_rx_nsegments, /* nsegments */
1713 sctx->isc_rx_maxsegsize, /* maxsegsize */
1715 NULL, /* lockfunc */
1719 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1723 if (!(fl->ifl_sds.ifsd_flags =
1724 (uint8_t *) malloc(sizeof(uint8_t) *
1725 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1726 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1730 if (!(fl->ifl_sds.ifsd_m =
1731 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1732 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1733 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1737 if (!(fl->ifl_sds.ifsd_cl =
1738 (caddr_t *) malloc(sizeof(caddr_t) *
1739 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1740 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1745 /* Create the descriptor buffer dma maps */
1746 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1747 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1750 if (!(fl->ifl_sds.ifsd_map =
1751 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1752 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1757 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1758 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1760 device_printf(dev, "Unable to create RX buffer DMA map\n");
1769 iflib_rx_structures_free(ctx);
1775 * Internal service routines
1778 struct rxq_refill_cb_arg {
1780 bus_dma_segment_t seg;
1785 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1787 struct rxq_refill_cb_arg *cb_arg = arg;
1789 cb_arg->error = error;
1790 cb_arg->seg = segs[0];
1791 cb_arg->nseg = nseg;
1796 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1798 #define IS_DMAR(ctx) (0)
1802 * rxq_refill - refill an rxq free-buffer list
1803 * @ctx: the iflib context
1804 * @rxq: the free-list to refill
1805 * @n: the number of new buffers to allocate
1807 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1808 * The caller must assure that @n does not exceed the queue's capacity.
1811 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1814 int idx, frag_idx = fl->ifl_fragidx;
1815 int pidx = fl->ifl_pidx;
1819 struct if_rxd_update iru;
1820 bus_dmamap_t *sd_map;
1826 sd_m = fl->ifl_sds.ifsd_m;
1827 sd_map = fl->ifl_sds.ifsd_map;
1828 sd_cl = fl->ifl_sds.ifsd_cl;
1829 sd_flags = fl->ifl_sds.ifsd_flags;
1831 credits = fl->ifl_credits;
1835 MPASS(credits + n <= fl->ifl_size);
1837 if (pidx < fl->ifl_cidx)
1838 MPASS(pidx + n <= fl->ifl_cidx);
1839 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1840 MPASS(fl->ifl_gen == 0);
1841 if (pidx > fl->ifl_cidx)
1842 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1844 DBG_COUNTER_INC(fl_refills);
1846 DBG_COUNTER_INC(fl_refills_large);
1847 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1850 * We allocate an uninitialized mbuf + cluster, mbuf is
1851 * initialized after rx.
1853 * If the cluster is still set then we know a minimum sized packet was received
1855 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1856 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1857 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1858 if ((cl = sd_cl[frag_idx]) == NULL) {
1859 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1862 fl->ifl_cl_enqueued++;
1865 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1869 fl->ifl_m_enqueued++;
1872 DBG_COUNTER_INC(rx_allocs);
1873 #if defined(__i386__) || defined(__amd64__)
1874 if (!IS_DMAR(ctx)) {
1875 bus_addr = pmap_kextract((vm_offset_t)cl);
1879 struct rxq_refill_cb_arg cb_arg;
1884 MPASS(sd_map != NULL);
1885 MPASS(sd_map[frag_idx] != NULL);
1886 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1887 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1888 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1889 BUS_DMASYNC_PREREAD);
1891 if (err != 0 || cb_arg.error) {
1895 if (fl->ifl_zone == zone_pack)
1896 uma_zfree(fl->ifl_zone, cl);
1901 bus_addr = cb_arg.seg.ds_addr;
1903 bit_set(fl->ifl_rx_bitmap, frag_idx);
1904 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1906 MPASS(sd_m[frag_idx] == NULL);
1907 sd_cl[frag_idx] = cl;
1909 fl->ifl_rxd_idxs[i] = frag_idx;
1910 fl->ifl_bus_addrs[i] = bus_addr;
1911 fl->ifl_vm_addrs[i] = cl;
1914 MPASS(credits <= fl->ifl_size);
1915 if (++idx == fl->ifl_size) {
1919 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1920 iru.iru_pidx = pidx;
1922 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1926 fl->ifl_credits = credits;
1932 iru.iru_pidx = pidx;
1934 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1936 fl->ifl_credits = credits;
1938 DBG_COUNTER_INC(rxd_flush);
1939 if (fl->ifl_pidx == 0)
1940 pidx = fl->ifl_size - 1;
1942 pidx = fl->ifl_pidx - 1;
1945 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1947 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1948 fl->ifl_fragidx = frag_idx;
1951 static __inline void
1952 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1954 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1955 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1957 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1960 MPASS(fl->ifl_credits <= fl->ifl_size);
1961 MPASS(reclaimable == delta);
1963 if (reclaimable > 0)
1964 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1968 iflib_fl_bufs_free(iflib_fl_t fl)
1970 iflib_dma_info_t idi = fl->ifl_ifdi;
1973 for (i = 0; i < fl->ifl_size; i++) {
1974 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1975 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1976 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1978 if (*sd_flags & RX_SW_DESC_INUSE) {
1979 if (fl->ifl_sds.ifsd_map != NULL) {
1980 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1981 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1982 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1984 if (*sd_m != NULL) {
1985 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1986 uma_zfree(zone_mbuf, *sd_m);
1989 uma_zfree(fl->ifl_zone, *sd_cl);
1992 MPASS(*sd_cl == NULL);
1993 MPASS(*sd_m == NULL);
1996 fl->ifl_m_dequeued++;
1997 fl->ifl_cl_dequeued++;
2003 for (i = 0; i < fl->ifl_size; i++) {
2004 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2005 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2006 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2010 * Reset free list values
2012 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2013 bzero(idi->idi_vaddr, idi->idi_size);
2016 /*********************************************************************
2018 * Initialize a receive ring and its buffers.
2020 **********************************************************************/
2022 iflib_fl_setup(iflib_fl_t fl)
2024 iflib_rxq_t rxq = fl->ifl_rxq;
2025 if_ctx_t ctx = rxq->ifr_ctx;
2026 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2028 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2030 ** Free current RX buffer structs and their mbufs
2032 iflib_fl_bufs_free(fl);
2033 /* Now replenish the mbufs */
2034 MPASS(fl->ifl_credits == 0);
2036 * XXX don't set the max_frame_size to larger
2037 * than the hardware can handle
2039 if (sctx->isc_max_frame_size <= 2048)
2040 fl->ifl_buf_size = MCLBYTES;
2041 #ifndef CONTIGMALLOC_WORKS
2043 fl->ifl_buf_size = MJUMPAGESIZE;
2045 else if (sctx->isc_max_frame_size <= 4096)
2046 fl->ifl_buf_size = MJUMPAGESIZE;
2047 else if (sctx->isc_max_frame_size <= 9216)
2048 fl->ifl_buf_size = MJUM9BYTES;
2050 fl->ifl_buf_size = MJUM16BYTES;
2052 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2053 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2054 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2055 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2058 /* avoid pre-allocating zillions of clusters to an idle card
2059 * potentially speeding up attach
2061 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2062 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2063 if (min(128, fl->ifl_size) != fl->ifl_credits)
2069 MPASS(fl->ifl_ifdi != NULL);
2070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2075 /*********************************************************************
2077 * Free receive ring data structures
2079 **********************************************************************/
2081 iflib_rx_sds_free(iflib_rxq_t rxq)
2086 if (rxq->ifr_fl != NULL) {
2087 for (i = 0; i < rxq->ifr_nfl; i++) {
2088 fl = &rxq->ifr_fl[i];
2089 if (fl->ifl_desc_tag != NULL) {
2090 bus_dma_tag_destroy(fl->ifl_desc_tag);
2091 fl->ifl_desc_tag = NULL;
2093 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2094 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2095 /* XXX destroy maps first */
2096 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2097 fl->ifl_sds.ifsd_m = NULL;
2098 fl->ifl_sds.ifsd_cl = NULL;
2099 fl->ifl_sds.ifsd_map = NULL;
2101 free(rxq->ifr_fl, M_IFLIB);
2103 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2108 * MI independent logic
2112 iflib_timer(void *arg)
2114 iflib_txq_t txq = arg;
2115 if_ctx_t ctx = txq->ift_ctx;
2116 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2118 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2121 ** Check on the state of the TX queue(s), this
2122 ** can be done without the lock because its RO
2123 ** and the HUNG state will be static if set.
2125 IFDI_TIMER(ctx, txq->ift_id);
2126 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2127 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2128 (sctx->isc_pause_frames == 0)))
2131 if (ifmp_ring_is_stalled(txq->ift_br))
2132 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2133 txq->ift_cleaned_prev = txq->ift_cleaned;
2134 /* handle any laggards */
2135 if (txq->ift_db_pending)
2136 GROUPTASK_ENQUEUE(&txq->ift_task);
2138 sctx->isc_pause_frames = 0;
2139 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2140 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2144 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2145 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2146 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2148 IFDI_WATCHDOG_RESET(ctx);
2149 ctx->ifc_watchdog_events++;
2151 ctx->ifc_flags |= IFC_DO_RESET;
2152 iflib_admin_intr_deferred(ctx);
2157 iflib_init_locked(if_ctx_t ctx)
2159 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2161 if_t ifp = ctx->ifc_ifp;
2165 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2168 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2169 IFDI_INTR_DISABLE(ctx);
2171 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2172 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2173 /* Set hardware offload abilities */
2174 if_clearhwassist(ifp);
2175 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2176 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2177 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2178 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2179 if (if_getcapenable(ifp) & IFCAP_TSO4)
2180 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2181 if (if_getcapenable(ifp) & IFCAP_TSO6)
2182 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2184 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2186 callout_stop(&txq->ift_timer);
2187 CALLOUT_UNLOCK(txq);
2188 iflib_netmap_txq_init(ctx, txq);
2191 i = if_getdrvflags(ifp);
2194 MPASS(if_getdrvflags(ifp) == i);
2195 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2196 /* XXX this should really be done on a per-queue basis */
2197 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2198 MPASS(rxq->ifr_id == i);
2199 iflib_netmap_rxq_init(ctx, rxq);
2202 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2203 if (iflib_fl_setup(fl)) {
2204 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2210 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2211 IFDI_INTR_ENABLE(ctx);
2212 txq = ctx->ifc_txqs;
2213 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2214 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2215 txq->ift_timer.c_cpu);
2219 iflib_media_change(if_t ifp)
2221 if_ctx_t ctx = if_getsoftc(ifp);
2225 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2226 iflib_init_locked(ctx);
2232 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2234 if_ctx_t ctx = if_getsoftc(ifp);
2237 IFDI_UPDATE_ADMIN_STATUS(ctx);
2238 IFDI_MEDIA_STATUS(ctx, ifmr);
2243 iflib_stop(if_ctx_t ctx)
2245 iflib_txq_t txq = ctx->ifc_txqs;
2246 iflib_rxq_t rxq = ctx->ifc_rxqs;
2247 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2248 iflib_dma_info_t di;
2252 /* Tell the stack that the interface is no longer active */
2253 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2255 IFDI_INTR_DISABLE(ctx);
2260 iflib_debug_reset();
2261 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2262 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2263 /* make sure all transmitters have completed before proceeding XXX */
2265 /* clean any enqueued buffers */
2266 iflib_ifmp_purge(txq);
2267 /* Free any existing tx buffers. */
2268 for (j = 0; j < txq->ift_size; j++) {
2269 iflib_txsd_free(ctx, txq, j);
2271 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2272 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2273 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2274 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2275 txq->ift_pullups = 0;
2276 ifmp_ring_reset_stats(txq->ift_br);
2277 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2278 bzero((void *)di->idi_vaddr, di->idi_size);
2280 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2281 /* make sure all transmitters have completed before proceeding XXX */
2283 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2284 bzero((void *)di->idi_vaddr, di->idi_size);
2285 /* also resets the free lists pidx/cidx */
2286 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2287 iflib_fl_bufs_free(fl);
2291 static inline caddr_t
2292 calc_next_rxd(iflib_fl_t fl, int cidx)
2296 caddr_t start, end, cur, next;
2298 nrxd = fl->ifl_size;
2299 size = fl->ifl_rxd_size;
2300 start = fl->ifl_ifdi->idi_vaddr;
2302 if (__predict_false(size == 0))
2304 cur = start + size*cidx;
2305 end = start + size*nrxd;
2306 next = CACHE_PTR_NEXT(cur);
2307 return (next < end ? next : start);
2311 prefetch_pkts(iflib_fl_t fl, int cidx)
2314 int nrxd = fl->ifl_size;
2318 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2319 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2320 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2321 next_rxd = calc_next_rxd(fl, cidx);
2323 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2324 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2325 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2326 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2327 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2328 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2329 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2330 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2334 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2339 iflib_dma_info_t di;
2343 flid = irf->irf_flid;
2344 cidx = irf->irf_idx;
2345 fl = &rxq->ifr_fl[flid];
2347 sd->ifsd_cidx = cidx;
2348 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2349 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2352 fl->ifl_m_dequeued++;
2354 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2355 prefetch_pkts(fl, cidx);
2356 if (fl->ifl_sds.ifsd_map != NULL) {
2357 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2358 prefetch(&fl->ifl_sds.ifsd_map[next]);
2359 map = fl->ifl_sds.ifsd_map[cidx];
2361 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2362 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2363 bus_dmamap_sync(di->idi_tag, di->idi_map,
2364 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2366 /* not valid assert if bxe really does SGE from non-contiguous elements */
2367 MPASS(fl->ifl_cidx == cidx);
2369 bus_dmamap_unload(fl->ifl_desc_tag, map);
2371 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2372 if (__predict_false(fl->ifl_cidx == 0))
2375 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2376 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2377 bit_clear(fl->ifl_rx_bitmap, cidx);
2380 static struct mbuf *
2381 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2383 int i, padlen , flags;
2384 struct mbuf *m, *mh, *mt;
2390 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2392 MPASS(*sd->ifsd_cl != NULL);
2393 MPASS(*sd->ifsd_m != NULL);
2395 /* Don't include zero-length frags */
2396 if (ri->iri_frags[i].irf_len == 0) {
2397 /* XXX we can save the cluster here, but not the mbuf */
2398 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2399 m_free(*sd->ifsd_m);
2406 flags = M_PKTHDR|M_EXT;
2408 padlen = ri->iri_pad;
2413 /* assuming padding is only on the first fragment */
2417 *sd->ifsd_cl = NULL;
2419 /* Can these two be made one ? */
2420 m_init(m, M_NOWAIT, MT_DATA, flags);
2421 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2423 * These must follow m_init and m_cljset
2425 m->m_data += padlen;
2426 ri->iri_len -= padlen;
2427 m->m_len = ri->iri_frags[i].irf_len;
2428 } while (++i < ri->iri_nfrags);
2434 * Process one software descriptor
2436 static struct mbuf *
2437 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2442 /* should I merge this back in now that the two paths are basically duplicated? */
2443 if (ri->iri_nfrags == 1 &&
2444 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2445 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2448 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2449 #ifndef __NO_STRICT_ALIGNMENT
2453 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2454 m->m_len = ri->iri_frags[0].irf_len;
2456 m = assemble_segments(rxq, ri, &sd);
2458 m->m_pkthdr.len = ri->iri_len;
2459 m->m_pkthdr.rcvif = ri->iri_ifp;
2460 m->m_flags |= ri->iri_flags;
2461 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2462 m->m_pkthdr.flowid = ri->iri_flowid;
2463 M_HASHTYPE_SET(m, ri->iri_rsstype);
2464 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2465 m->m_pkthdr.csum_data = ri->iri_csum_data;
2469 #if defined(INET6) || defined(INET)
2471 * Returns true if it's possible this packet could be LROed.
2472 * if it returns false, it is guaranteed that tcp_lro_rx()
2473 * would not return zero.
2476 iflib_check_lro_possible(struct lro_ctrl *lc, struct mbuf *m)
2478 struct ether_header *eh;
2481 eh = mtod(m, struct ether_header *);
2482 eh_type = ntohs(eh->ether_type);
2485 case ETHERTYPE_IPV6:
2487 CURVNET_SET(lc->ifp->if_vnet);
2488 if (VNET(ip6_forwarding) == 0) {
2499 CURVNET_SET(lc->ifp->if_vnet);
2500 if (VNET(ipforwarding) == 0) {
2515 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2517 if_ctx_t ctx = rxq->ifr_ctx;
2518 if_shared_ctx_t sctx = ctx->ifc_sctx;
2519 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2522 struct if_rxd_info ri;
2523 int err, budget_left, rx_bytes, rx_pkts;
2527 bool lro_possible = false;
2530 * XXX early demux data packets so that if_input processing only handles
2531 * acks in interrupt context
2533 struct mbuf *m, *mh, *mt, *mf;
2538 rx_pkts = rx_bytes = 0;
2539 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2540 cidxp = &rxq->ifr_cq_cidx;
2542 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2543 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2544 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2545 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2546 DBG_COUNTER_INC(rx_unavail);
2550 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2551 if (__predict_false(!CTX_ACTIVE(ctx))) {
2552 DBG_COUNTER_INC(rx_ctx_inactive);
2556 * Reset client set fields to their default values
2559 ri.iri_qsidx = rxq->ifr_id;
2560 ri.iri_cidx = *cidxp;
2562 ri.iri_frags = rxq->ifr_frags;
2563 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2567 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2568 *cidxp = ri.iri_cidx;
2569 /* Update our consumer index */
2570 /* XXX NB: shurd - check if this is still safe */
2571 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2572 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2573 rxq->ifr_cq_gen = 0;
2575 /* was this only a completion queue message? */
2576 if (__predict_false(ri.iri_nfrags == 0))
2579 MPASS(ri.iri_nfrags != 0);
2580 MPASS(ri.iri_len != 0);
2582 /* will advance the cidx on the corresponding free lists */
2583 m = iflib_rxd_pkt_get(rxq, &ri);
2584 if (avail == 0 && budget_left)
2585 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2587 if (__predict_false(m == NULL)) {
2588 DBG_COUNTER_INC(rx_mbuf_null);
2591 /* imm_pkt: -- cxgb */
2599 /* make sure that we can refill faster than drain */
2600 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2601 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2603 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2605 while (mh != NULL) {
2608 m->m_nextpkt = NULL;
2609 #ifndef __NO_STRICT_ALIGNMENT
2610 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2613 rx_bytes += m->m_pkthdr.len;
2615 #if defined(INET6) || defined(INET)
2617 if (!lro_possible) {
2618 lro_possible = iflib_check_lro_possible(&rxq->ifr_lc, m);
2619 if (lro_possible && mf != NULL) {
2620 ifp->if_input(ifp, mf);
2621 DBG_COUNTER_INC(rx_if_input);
2625 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2630 ifp->if_input(ifp, m);
2631 DBG_COUNTER_INC(rx_if_input);
2642 ifp->if_input(ifp, mf);
2643 DBG_COUNTER_INC(rx_if_input);
2646 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2647 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2650 * Flush any outstanding LRO work
2652 #if defined(INET6) || defined(INET)
2653 tcp_lro_flush_all(&rxq->ifr_lc);
2657 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2660 ctx->ifc_flags |= IFC_DO_RESET;
2661 iflib_admin_intr_deferred(ctx);
2666 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2667 static inline qidx_t
2668 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2670 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2671 qidx_t minthresh = txq->ift_size / 8;
2672 if (in_use > 4*minthresh)
2673 return (notify_count);
2674 if (in_use > 2*minthresh)
2675 return (notify_count >> 1);
2676 if (in_use > minthresh)
2677 return (notify_count >> 3);
2681 static inline qidx_t
2682 txq_max_rs_deferred(iflib_txq_t txq)
2684 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2685 qidx_t minthresh = txq->ift_size / 8;
2686 if (txq->ift_in_use > 4*minthresh)
2687 return (notify_count);
2688 if (txq->ift_in_use > 2*minthresh)
2689 return (notify_count >> 1);
2690 if (txq->ift_in_use > minthresh)
2691 return (notify_count >> 2);
2695 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2696 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2698 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2699 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2700 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2702 /* forward compatibility for cxgb */
2703 #define FIRST_QSET(ctx) 0
2704 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2705 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2706 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2707 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2709 /* XXX we should be setting this to something other than zero */
2710 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2711 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2714 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2720 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2721 if (ring || txq->ift_db_pending >= max) {
2722 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2723 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2724 txq->ift_db_pending = txq->ift_npending = 0;
2732 print_pkt(if_pkt_info_t pi)
2734 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2735 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2736 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2737 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2738 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2739 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2743 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2744 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2747 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2749 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2750 struct ether_vlan_header *eh;
2754 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2755 M_WRITABLE(m) == 0) {
2756 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2765 * Determine where frame payload starts.
2766 * Jump over vlan headers if already present,
2767 * helpful for QinQ too.
2769 if (__predict_false(m->m_len < sizeof(*eh))) {
2771 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2774 eh = mtod(m, struct ether_vlan_header *);
2775 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2776 pi->ipi_etype = ntohs(eh->evl_proto);
2777 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2779 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2780 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2783 switch (pi->ipi_etype) {
2787 struct ip *ip = NULL;
2788 struct tcphdr *th = NULL;
2791 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2792 if (__predict_false(m->m_len < minthlen)) {
2794 * if this code bloat is causing too much of a hit
2795 * move it to a separate function and mark it noinline
2797 if (m->m_len == pi->ipi_ehdrlen) {
2800 if (n->m_len >= sizeof(*ip)) {
2801 ip = (struct ip *)n->m_data;
2802 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2803 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2806 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2808 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2812 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2814 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2815 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2816 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2819 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2820 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2821 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2823 pi->ipi_ip_hlen = ip->ip_hl << 2;
2824 pi->ipi_ipproto = ip->ip_p;
2825 pi->ipi_flags |= IPI_TX_IPV4;
2827 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2831 if (pi->ipi_ipproto == IPPROTO_TCP) {
2832 if (__predict_false(th == NULL)) {
2834 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2836 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2838 pi->ipi_tcp_hflags = th->th_flags;
2839 pi->ipi_tcp_hlen = th->th_off << 2;
2840 pi->ipi_tcp_seq = th->th_seq;
2842 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2844 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2845 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2846 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2847 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2849 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2856 case ETHERTYPE_IPV6:
2858 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2860 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2862 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2863 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2866 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2868 /* XXX-BZ this will go badly in case of ext hdrs. */
2869 pi->ipi_ipproto = ip6->ip6_nxt;
2870 pi->ipi_flags |= IPI_TX_IPV6;
2873 if (pi->ipi_ipproto == IPPROTO_TCP) {
2874 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2875 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2878 pi->ipi_tcp_hflags = th->th_flags;
2879 pi->ipi_tcp_hlen = th->th_off << 2;
2882 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2885 * The corresponding flag is set by the stack in the IPv4
2886 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2887 * So, set it here because the rest of the flow requires it.
2889 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2890 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2891 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2897 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2898 pi->ipi_ip_hlen = 0;
2906 static __noinline struct mbuf *
2907 collapse_pkthdr(struct mbuf *m0)
2909 struct mbuf *m, *m_next, *tmp;
2913 while (m_next != NULL && m_next->m_len == 0) {
2917 m_next = m_next->m_next;
2921 if ((m_next->m_flags & M_EXT) == 0) {
2922 m = m_defrag(m, M_NOWAIT);
2924 tmp = m_next->m_next;
2925 memcpy(m_next, m, MPKTHSIZE);
2933 * If dodgy hardware rejects the scatter gather chain we've handed it
2934 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2937 static __noinline struct mbuf *
2938 iflib_remove_mbuf(iflib_txq_t txq)
2941 struct mbuf *m, *mh, **ifsd_m;
2943 pidx = txq->ift_pidx;
2944 ifsd_m = txq->ift_sds.ifsd_m;
2945 ntxd = txq->ift_size;
2946 mh = m = ifsd_m[pidx];
2947 ifsd_m[pidx] = NULL;
2949 txq->ift_dequeued++;
2954 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2956 txq->ift_dequeued++;
2965 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2966 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2967 int max_segs, int flags)
2970 if_shared_ctx_t sctx;
2971 if_softc_ctx_t scctx;
2972 int i, next, pidx, err, ntxd, count;
2973 struct mbuf *m, *tmp, **ifsd_m;
2978 * Please don't ever do this
2980 if (__predict_false(m->m_len == 0))
2981 *m0 = m = collapse_pkthdr(m);
2984 sctx = ctx->ifc_sctx;
2985 scctx = &ctx->ifc_softc_ctx;
2986 ifsd_m = txq->ift_sds.ifsd_m;
2987 ntxd = txq->ift_size;
2988 pidx = txq->ift_pidx;
2990 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2992 err = bus_dmamap_load_mbuf_sg(tag, map,
2993 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2996 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3000 if (__predict_false(m->m_len <= 0)) {
3009 } while (m != NULL);
3010 if (count > *nsegs) {
3012 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3018 next = (pidx + count) & (ntxd-1);
3019 MPASS(ifsd_m[next] == NULL);
3024 } while (m != NULL);
3026 int buflen, sgsize, maxsegsz, max_sgsize;
3032 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3033 maxsegsz = scctx->isc_tx_tso_segsize_max;
3035 maxsegsz = sctx->isc_tx_maxsegsize;
3038 if (__predict_false(m->m_len <= 0)) {
3046 vaddr = (vm_offset_t)m->m_data;
3048 * see if we can't be smarter about physically
3049 * contiguous mappings
3051 next = (pidx + count) & (ntxd-1);
3052 MPASS(ifsd_m[next] == NULL);
3054 txq->ift_enqueued++;
3057 while (buflen > 0) {
3060 max_sgsize = MIN(buflen, maxsegsz);
3061 curaddr = pmap_kextract(vaddr);
3062 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3063 sgsize = MIN(sgsize, max_sgsize);
3064 segs[i].ds_addr = curaddr;
3065 segs[i].ds_len = sgsize;
3073 } while (m != NULL);
3078 *m0 = iflib_remove_mbuf(txq);
3082 static inline caddr_t
3083 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3087 caddr_t start, end, cur, next;
3089 ntxd = txq->ift_size;
3090 size = txq->ift_txd_size[qid];
3091 start = txq->ift_ifdi[qid].idi_vaddr;
3093 if (__predict_false(size == 0))
3095 cur = start + size*cidx;
3096 end = start + size*ntxd;
3097 next = CACHE_PTR_NEXT(cur);
3098 return (next < end ? next : start);
3102 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3105 if_shared_ctx_t sctx;
3106 if_softc_ctx_t scctx;
3107 bus_dma_segment_t *segs;
3108 struct mbuf *m_head;
3111 struct if_pkt_info pi;
3113 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3114 bus_dma_tag_t desc_tag;
3116 segs = txq->ift_segs;
3118 sctx = ctx->ifc_sctx;
3119 scctx = &ctx->ifc_softc_ctx;
3120 segs = txq->ift_segs;
3121 ntxd = txq->ift_size;
3126 * If we're doing TSO the next descriptor to clean may be quite far ahead
3128 cidx = txq->ift_cidx;
3129 pidx = txq->ift_pidx;
3130 if (ctx->ifc_flags & IFC_PREFETCH) {
3131 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3132 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3133 next_txd = calc_next_txd(txq, cidx, 0);
3137 /* prefetch the next cache line of mbuf pointers and flags */
3138 prefetch(&txq->ift_sds.ifsd_m[next]);
3139 if (txq->ift_sds.ifsd_map != NULL) {
3140 prefetch(&txq->ift_sds.ifsd_map[next]);
3141 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3142 prefetch(&txq->ift_sds.ifsd_flags[next]);
3144 } else if (txq->ift_sds.ifsd_map != NULL)
3145 map = txq->ift_sds.ifsd_map[pidx];
3147 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3148 desc_tag = txq->ift_tso_desc_tag;
3149 max_segs = scctx->isc_tx_tso_segments_max;
3151 desc_tag = txq->ift_desc_tag;
3152 max_segs = scctx->isc_tx_nsegments;
3157 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3159 pi.ipi_qsidx = txq->ift_id;
3160 pi.ipi_len = m_head->m_pkthdr.len;
3161 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3162 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3164 /* deliberate bitwise OR to make one condition */
3165 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3166 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3172 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3174 if (__predict_false(err)) {
3177 /* try collapse once and defrag once */
3179 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3181 m_head = m_defrag(*m_headp, M_NOWAIT);
3183 if (__predict_false(m_head == NULL))
3185 txq->ift_mbuf_defrag++;
3190 txq->ift_no_tx_dma_setup++;
3193 txq->ift_no_tx_dma_setup++;
3195 DBG_COUNTER_INC(tx_frees);
3199 txq->ift_map_failed++;
3200 DBG_COUNTER_INC(encap_load_mbuf_fail);
3205 * XXX assumes a 1 to 1 relationship between segments and
3206 * descriptors - this does not hold true on all drivers, e.g.
3209 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3210 txq->ift_no_desc_avail++;
3212 bus_dmamap_unload(desc_tag, map);
3213 DBG_COUNTER_INC(encap_txq_avail_fail);
3214 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3215 GROUPTASK_ENQUEUE(&txq->ift_task);
3219 * On Intel cards we can greatly reduce the number of TX interrupts
3220 * we see by only setting report status on every Nth descriptor.
3221 * However, this also means that the driver will need to keep track
3222 * of the descriptors that RS was set on to check them for the DD bit.
3224 txq->ift_rs_pending += nsegs + 1;
3225 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3226 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3227 pi.ipi_flags |= IPI_TX_INTR;
3228 txq->ift_rs_pending = 0;
3232 pi.ipi_nsegs = nsegs;
3234 MPASS(pidx >= 0 && pidx < txq->ift_size);
3239 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3240 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3242 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3243 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3244 DBG_COUNTER_INC(tx_encap);
3245 MPASS(pi.ipi_new_pidx < txq->ift_size);
3247 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3248 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3249 ndesc += txq->ift_size;
3253 * drivers can need as many as
3256 MPASS(ndesc <= pi.ipi_nsegs + 2);
3257 MPASS(pi.ipi_new_pidx != pidx);
3259 txq->ift_in_use += ndesc;
3262 * We update the last software descriptor again here because there may
3263 * be a sentinel and/or there may be more mbufs than segments
3265 txq->ift_pidx = pi.ipi_new_pidx;
3266 txq->ift_npending += pi.ipi_ndescs;
3267 } else if (__predict_false(err == EFBIG && remap < 2)) {
3268 *m_headp = m_head = iflib_remove_mbuf(txq);
3270 txq->ift_txd_encap_efbig++;
3273 DBG_COUNTER_INC(encap_txd_encap_fail);
3277 txq->ift_mbuf_defrag_failed++;
3278 txq->ift_map_failed++;
3280 DBG_COUNTER_INC(tx_frees);
3286 iflib_tx_desc_free(iflib_txq_t txq, int n)
3289 uint32_t qsize, cidx, mask, gen;
3290 struct mbuf *m, **ifsd_m;
3291 uint8_t *ifsd_flags;
3292 bus_dmamap_t *ifsd_map;
3295 cidx = txq->ift_cidx;
3297 qsize = txq->ift_size;
3299 hasmap = txq->ift_sds.ifsd_map != NULL;
3300 ifsd_flags = txq->ift_sds.ifsd_flags;
3301 ifsd_m = txq->ift_sds.ifsd_m;
3302 ifsd_map = txq->ift_sds.ifsd_map;
3303 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3307 prefetch(ifsd_m[(cidx + 3) & mask]);
3308 prefetch(ifsd_m[(cidx + 4) & mask]);
3310 if (ifsd_m[cidx] != NULL) {
3311 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3312 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3313 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3315 * does it matter if it's not the TSO tag? If so we'll
3316 * have to add the type to flags
3318 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3319 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3321 if ((m = ifsd_m[cidx]) != NULL) {
3322 /* XXX we don't support any drivers that batch packets yet */
3323 MPASS(m->m_nextpkt == NULL);
3324 /* if the number of clusters exceeds the number of segments
3325 * there won't be space on the ring to save a pointer to each
3326 * cluster so we simply free the list here
3328 if (m->m_flags & M_TOOBIG) {
3333 ifsd_m[cidx] = NULL;
3335 txq->ift_dequeued++;
3337 DBG_COUNTER_INC(tx_frees);
3340 if (__predict_false(++cidx == qsize)) {
3345 txq->ift_cidx = cidx;
3350 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3353 if_ctx_t ctx = txq->ift_ctx;
3355 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3356 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3359 * Need a rate-limiting check so that this isn't called every time
3361 iflib_tx_credits_update(ctx, txq);
3362 reclaim = DESC_RECLAIMABLE(txq);
3364 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3366 if (iflib_verbose_debug) {
3367 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3368 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3375 iflib_tx_desc_free(txq, reclaim);
3376 txq->ift_cleaned += reclaim;
3377 txq->ift_in_use -= reclaim;
3382 static struct mbuf **
3383 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3386 struct mbuf **items;
3389 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3390 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3392 prefetch(items[(cidx + offset) & (size-1)]);
3393 if (remaining > 1) {
3394 prefetch2cachelines(&items[next]);
3395 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3396 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3397 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3399 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3403 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3406 ifmp_ring_check_drainage(txq->ift_br, budget);
3410 iflib_txq_can_drain(struct ifmp_ring *r)
3412 iflib_txq_t txq = r->cookie;
3413 if_ctx_t ctx = txq->ift_ctx;
3415 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3416 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3420 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3422 iflib_txq_t txq = r->cookie;
3423 if_ctx_t ctx = txq->ift_ctx;
3424 struct ifnet *ifp = ctx->ifc_ifp;
3425 struct mbuf **mp, *m;
3426 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3427 int reclaimed, err, in_use_prev, desc_used;
3428 bool do_prefetch, ring, rang;
3430 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3431 !LINK_ACTIVE(ctx))) {
3432 DBG_COUNTER_INC(txq_drain_notready);
3435 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3436 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3437 avail = IDXDIFF(pidx, cidx, r->size);
3438 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3439 DBG_COUNTER_INC(txq_drain_flushing);
3440 for (i = 0; i < avail; i++) {
3441 m_free(r->items[(cidx + i) & (r->size-1)]);
3442 r->items[(cidx + i) & (r->size-1)] = NULL;
3447 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3448 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3450 callout_stop(&txq->ift_timer);
3451 CALLOUT_UNLOCK(txq);
3452 DBG_COUNTER_INC(txq_drain_oactive);
3456 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3457 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3458 count = MIN(avail, TX_BATCH_SIZE);
3460 if (iflib_verbose_debug)
3461 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3462 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3464 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3465 avail = TXQ_AVAIL(txq);
3466 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3467 int pidx_prev, rem = do_prefetch ? count - i : 0;
3469 mp = _ring_peek_one(r, cidx, i, rem);
3470 MPASS(mp != NULL && *mp != NULL);
3471 if (__predict_false(*mp == (struct mbuf *)txq)) {
3476 in_use_prev = txq->ift_in_use;
3477 pidx_prev = txq->ift_pidx;
3478 err = iflib_encap(txq, mp);
3479 if (__predict_false(err)) {
3480 DBG_COUNTER_INC(txq_drain_encapfail);
3481 /* no room - bail out */
3485 DBG_COUNTER_INC(txq_drain_encapfail);
3486 /* we can't send this packet - skip it */
3492 DBG_COUNTER_INC(tx_sent);
3493 bytes_sent += m->m_pkthdr.len;
3494 mcast_sent += !!(m->m_flags & M_MCAST);
3495 avail = TXQ_AVAIL(txq);
3497 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3498 desc_used += (txq->ift_in_use - in_use_prev);
3499 ETHER_BPF_MTAP(ifp, m);
3500 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3502 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3505 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3506 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3507 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3508 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3509 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3511 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3513 if (iflib_verbose_debug)
3514 printf("consumed=%d\n", consumed);
3520 iflib_txq_drain_always(struct ifmp_ring *r)
3526 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3534 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3536 callout_stop(&txq->ift_timer);
3537 CALLOUT_UNLOCK(txq);
3539 avail = IDXDIFF(pidx, cidx, r->size);
3540 for (i = 0; i < avail; i++) {
3541 mp = _ring_peek_one(r, cidx, i, avail - i);
3542 if (__predict_false(*mp == (struct mbuf *)txq))
3546 MPASS(ifmp_ring_is_stalled(r) == 0);
3551 iflib_ifmp_purge(iflib_txq_t txq)
3553 struct ifmp_ring *r;
3556 r->drain = iflib_txq_drain_free;
3557 r->can_drain = iflib_txq_drain_always;
3559 ifmp_ring_check_drainage(r, r->size);
3561 r->drain = iflib_txq_drain;
3562 r->can_drain = iflib_txq_can_drain;
3566 _task_fn_tx(void *context)
3568 iflib_txq_t txq = context;
3569 if_ctx_t ctx = txq->ift_ctx;
3570 struct ifnet *ifp = ctx->ifc_ifp;
3573 #ifdef IFLIB_DIAGNOSTICS
3574 txq->ift_cpu_exec_count[curcpu]++;
3576 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3578 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3579 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3580 netmap_tx_irq(ifp, txq->ift_id);
3581 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3584 if (txq->ift_db_pending)
3585 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3586 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3587 if (ctx->ifc_flags & IFC_LEGACY)
3588 IFDI_INTR_ENABLE(ctx);
3590 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3591 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3596 _task_fn_rx(void *context)
3598 iflib_rxq_t rxq = context;
3599 if_ctx_t ctx = rxq->ifr_ctx;
3604 #ifdef IFLIB_DIAGNOSTICS
3605 rxq->ifr_cpu_exec_count[curcpu]++;
3607 DBG_COUNTER_INC(task_fn_rxs);
3608 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3612 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3614 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3619 budget = ctx->ifc_sysctl_rx_budget;
3621 budget = 16; /* XXX */
3622 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3623 if (ctx->ifc_flags & IFC_LEGACY)
3624 IFDI_INTR_ENABLE(ctx);
3626 DBG_COUNTER_INC(rx_intr_enables);
3627 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3628 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3631 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3634 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3638 _task_fn_admin(void *context)
3640 if_ctx_t ctx = context;
3641 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3645 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) {
3646 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3652 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3654 callout_stop(&txq->ift_timer);
3655 CALLOUT_UNLOCK(txq);
3657 IFDI_UPDATE_ADMIN_STATUS(ctx);
3658 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3659 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3660 IFDI_LINK_INTR_ENABLE(ctx);
3661 if (ctx->ifc_flags & IFC_DO_RESET) {
3662 ctx->ifc_flags &= ~IFC_DO_RESET;
3663 iflib_if_init_locked(ctx);
3667 if (LINK_ACTIVE(ctx) == 0)
3669 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3670 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3675 _task_fn_iov(void *context)
3677 if_ctx_t ctx = context;
3679 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3683 IFDI_VFLR_HANDLE(ctx);
3688 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3691 if_int_delay_info_t info;
3694 info = (if_int_delay_info_t)arg1;
3695 ctx = info->iidi_ctx;
3696 info->iidi_req = req;
3697 info->iidi_oidp = oidp;
3699 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3704 /*********************************************************************
3708 **********************************************************************/
3711 iflib_if_init_locked(if_ctx_t ctx)
3714 iflib_init_locked(ctx);
3719 iflib_if_init(void *arg)
3724 iflib_if_init_locked(ctx);
3729 iflib_if_transmit(if_t ifp, struct mbuf *m)
3731 if_ctx_t ctx = if_getsoftc(ifp);
3736 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3737 DBG_COUNTER_INC(tx_frees);
3742 MPASS(m->m_nextpkt == NULL);
3744 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3745 qidx = QIDX(ctx, m);
3747 * XXX calculate buf_ring based on flowid (divvy up bits?)
3749 txq = &ctx->ifc_txqs[qidx];
3751 #ifdef DRIVER_BACKPRESSURE
3752 if (txq->ift_closed) {
3754 next = m->m_nextpkt;
3755 m->m_nextpkt = NULL;
3768 next = next->m_nextpkt;
3769 } while (next != NULL);
3771 if (count > nitems(marr))
3772 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3773 /* XXX check nextpkt */
3775 /* XXX simplify for now */
3776 DBG_COUNTER_INC(tx_frees);
3779 for (next = m, i = 0; next != NULL; i++) {
3781 next = next->m_nextpkt;
3782 mp[i]->m_nextpkt = NULL;
3785 DBG_COUNTER_INC(tx_seen);
3786 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3788 GROUPTASK_ENQUEUE(&txq->ift_task);
3790 /* support forthcoming later */
3791 #ifdef DRIVER_BACKPRESSURE
3792 txq->ift_closed = TRUE;
3794 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3802 iflib_if_qflush(if_t ifp)
3804 if_ctx_t ctx = if_getsoftc(ifp);
3805 iflib_txq_t txq = ctx->ifc_txqs;
3809 ctx->ifc_flags |= IFC_QFLUSH;
3811 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3812 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3813 iflib_txq_check_drain(txq, 0);
3815 ctx->ifc_flags &= ~IFC_QFLUSH;
3822 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3823 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3824 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3827 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3829 if_ctx_t ctx = if_getsoftc(ifp);
3830 struct ifreq *ifr = (struct ifreq *)data;
3831 #if defined(INET) || defined(INET6)
3832 struct ifaddr *ifa = (struct ifaddr *)data;
3834 bool avoid_reset = FALSE;
3835 int err = 0, reinit = 0, bits;
3840 if (ifa->ifa_addr->sa_family == AF_INET)
3844 if (ifa->ifa_addr->sa_family == AF_INET6)
3848 ** Calling init results in link renegotiation,
3849 ** so we avoid doing it when possible.
3852 if_setflagbits(ifp, IFF_UP,0);
3853 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3856 if (!(if_getflags(ifp) & IFF_NOARP))
3857 arp_ifinit(ifp, ifa);
3860 err = ether_ioctl(ifp, command, data);
3864 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3868 bits = if_getdrvflags(ifp);
3869 /* stop the driver and free any clusters before proceeding */
3872 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3873 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3874 ctx->ifc_flags |= IFC_MULTISEG;
3876 ctx->ifc_flags &= ~IFC_MULTISEG;
3877 err = if_setmtu(ifp, ifr->ifr_mtu);
3879 iflib_init_locked(ctx);
3880 if_setdrvflags(ifp, bits);
3885 if (if_getflags(ifp) & IFF_UP) {
3886 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3887 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3888 (IFF_PROMISC | IFF_ALLMULTI)) {
3889 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3893 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3896 ctx->ifc_if_flags = if_getflags(ifp);
3901 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3903 IFDI_INTR_DISABLE(ctx);
3904 IFDI_MULTI_SET(ctx);
3905 IFDI_INTR_ENABLE(ctx);
3911 IFDI_MEDIA_SET(ctx);
3915 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3919 struct ifi2creq i2c;
3921 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3924 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3928 if (i2c.len > sizeof(i2c.data)) {
3933 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3934 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3941 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3944 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3946 setmask |= (mask & IFCAP_FLAGS);
3948 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
3949 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
3950 if ((mask & IFCAP_WOL) &&
3951 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3952 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3955 * want to ensure that traffic has stopped before we change any of the flags
3959 bits = if_getdrvflags(ifp);
3960 if (bits & IFF_DRV_RUNNING)
3962 if_togglecapenable(ifp, setmask);
3963 if (bits & IFF_DRV_RUNNING)
3964 iflib_init_locked(ctx);
3965 if_setdrvflags(ifp, bits);
3970 case SIOCGPRIVATE_0:
3974 err = IFDI_PRIV_IOCTL(ctx, command, data);
3978 err = ether_ioctl(ifp, command, data);
3987 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3989 if_ctx_t ctx = if_getsoftc(ifp);
3991 return (IFDI_GET_COUNTER(ctx, cnt));
3994 /*********************************************************************
3996 * OTHER FUNCTIONS EXPORTED TO THE STACK
3998 **********************************************************************/
4001 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4003 if_ctx_t ctx = if_getsoftc(ifp);
4005 if ((void *)ctx != arg)
4008 if ((vtag == 0) || (vtag > 4095))
4012 IFDI_VLAN_REGISTER(ctx, vtag);
4013 /* Re-init to load the changes */
4014 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4015 iflib_if_init_locked(ctx);
4020 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4022 if_ctx_t ctx = if_getsoftc(ifp);
4024 if ((void *)ctx != arg)
4027 if ((vtag == 0) || (vtag > 4095))
4031 IFDI_VLAN_UNREGISTER(ctx, vtag);
4032 /* Re-init to load the changes */
4033 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4034 iflib_if_init_locked(ctx);
4039 iflib_led_func(void *arg, int onoff)
4044 IFDI_LED_FUNC(ctx, onoff);
4048 /*********************************************************************
4050 * BUS FUNCTION DEFINITIONS
4052 **********************************************************************/
4055 iflib_device_probe(device_t dev)
4057 pci_vendor_info_t *ent;
4059 uint16_t pci_vendor_id, pci_device_id;
4060 uint16_t pci_subvendor_id, pci_subdevice_id;
4061 uint16_t pci_rev_id;
4062 if_shared_ctx_t sctx;
4064 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4067 pci_vendor_id = pci_get_vendor(dev);
4068 pci_device_id = pci_get_device(dev);
4069 pci_subvendor_id = pci_get_subvendor(dev);
4070 pci_subdevice_id = pci_get_subdevice(dev);
4071 pci_rev_id = pci_get_revid(dev);
4072 if (sctx->isc_parse_devinfo != NULL)
4073 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4075 ent = sctx->isc_vendor_info;
4076 while (ent->pvi_vendor_id != 0) {
4077 if (pci_vendor_id != ent->pvi_vendor_id) {
4081 if ((pci_device_id == ent->pvi_device_id) &&
4082 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4083 (ent->pvi_subvendor_id == 0)) &&
4084 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4085 (ent->pvi_subdevice_id == 0)) &&
4086 ((pci_rev_id == ent->pvi_rev_id) ||
4087 (ent->pvi_rev_id == 0))) {
4089 device_set_desc_copy(dev, ent->pvi_name);
4090 /* this needs to be changed to zero if the bus probing code
4091 * ever stops re-probing on best match because the sctx
4092 * may have its values over written by register calls
4093 * in subsequent probes
4095 return (BUS_PROBE_DEFAULT);
4103 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4105 int err, rid, msix, msix_bar;
4108 if_softc_ctx_t scctx;
4114 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4117 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4118 device_set_softc(dev, ctx);
4119 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4122 ctx->ifc_sctx = sctx;
4124 ctx->ifc_softc = sc;
4126 if ((err = iflib_register(ctx)) != 0) {
4127 device_printf(dev, "iflib_register failed %d\n", err);
4130 iflib_add_device_sysctl_pre(ctx);
4132 scctx = &ctx->ifc_softc_ctx;
4136 * XXX sanity check that ntxd & nrxd are a power of 2
4138 if (ctx->ifc_sysctl_ntxqs != 0)
4139 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4140 if (ctx->ifc_sysctl_nrxqs != 0)
4141 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4143 for (i = 0; i < sctx->isc_ntxqs; i++) {
4144 if (ctx->ifc_sysctl_ntxds[i] != 0)
4145 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4147 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4150 for (i = 0; i < sctx->isc_nrxqs; i++) {
4151 if (ctx->ifc_sysctl_nrxds[i] != 0)
4152 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4154 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4157 for (i = 0; i < sctx->isc_nrxqs; i++) {
4158 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4159 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4160 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4161 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4163 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4164 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4165 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4166 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4170 for (i = 0; i < sctx->isc_ntxqs; i++) {
4171 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4172 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4173 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4174 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4176 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4177 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4178 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4179 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4183 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4184 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4187 _iflib_pre_assert(scctx);
4188 ctx->ifc_txrx = *scctx->isc_txrx;
4191 MPASS(scctx->isc_capenable);
4192 if (scctx->isc_capenable & IFCAP_TXCSUM)
4193 MPASS(scctx->isc_tx_csum_flags);
4196 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4197 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4199 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4200 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4201 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4202 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4205 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4206 ctx->ifc_flags |= IFC_DMAR;
4207 #elif !(defined(__i386__) || defined(__amd64__))
4208 /* set unconditionally for !x86 */
4209 ctx->ifc_flags |= IFC_DMAR;
4212 msix_bar = scctx->isc_msix_bar;
4213 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4214 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4216 /* XXX change for per-queue sizes */
4217 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4218 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4219 for (i = 0; i < sctx->isc_nrxqs; i++) {
4220 if (!powerof2(scctx->isc_nrxd[i])) {
4221 /* round down instead? */
4222 device_printf(dev, "# rx descriptors must be a power of 2\n");
4227 for (i = 0; i < sctx->isc_ntxqs; i++) {
4228 if (!powerof2(scctx->isc_ntxd[i])) {
4230 "# tx descriptors must be a power of 2");
4236 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4237 MAX_SINGLE_PACKET_FRACTION)
4238 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4239 MAX_SINGLE_PACKET_FRACTION);
4240 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4241 MAX_SINGLE_PACKET_FRACTION)
4242 scctx->isc_tx_tso_segments_max = max(1,
4243 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4246 * Protect the stack against modern hardware
4248 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4249 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4251 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4252 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4253 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4254 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4255 if (scctx->isc_rss_table_size == 0)
4256 scctx->isc_rss_table_size = 64;
4257 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4259 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4260 /* XXX format name */
4261 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4263 ** Now setup MSI or MSI/X, should
4264 ** return us the number of supported
4265 ** vectors. (Will be 1 for MSI)
4267 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4268 msix = scctx->isc_vectors;
4269 } else if (scctx->isc_msix_bar != 0)
4271 * The simple fact that isc_msix_bar is not 0 does not mean we
4272 * we have a good value there that is known to work.
4274 msix = iflib_msix_init(ctx);
4276 scctx->isc_vectors = 1;
4277 scctx->isc_ntxqsets = 1;
4278 scctx->isc_nrxqsets = 1;
4279 scctx->isc_intr = IFLIB_INTR_LEGACY;
4282 /* Get memory for the station queues */
4283 if ((err = iflib_queues_alloc(ctx))) {
4284 device_printf(dev, "Unable to allocate queue memory\n");
4288 if ((err = iflib_qset_structures_setup(ctx))) {
4289 device_printf(dev, "qset structure setup failed %d\n", err);
4294 * Group taskqueues aren't properly set up until SMP is started,
4295 * so we disable interrupts until we can handle them post
4298 * XXX: disabling interrupts doesn't actually work, at least for
4299 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4300 * we do null handling and depend on this not causing too large an
4303 IFDI_INTR_DISABLE(ctx);
4304 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4305 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4306 goto fail_intr_free;
4310 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4314 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4315 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4316 goto fail_intr_free;
4319 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4320 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4321 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4324 if ((err = iflib_netmap_attach(ctx))) {
4325 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4330 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4331 iflib_add_device_sysctl_post(ctx);
4332 ctx->ifc_flags |= IFC_INIT_DONE;
4335 ether_ifdetach(ctx->ifc_ifp);
4337 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4338 pci_release_msi(ctx->ifc_dev);
4340 /* XXX free queues */
4347 iflib_device_attach(device_t dev)
4350 if_shared_ctx_t sctx;
4352 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4355 pci_enable_busmaster(dev);
4357 return (iflib_device_register(dev, NULL, sctx, &ctx));
4361 iflib_device_deregister(if_ctx_t ctx)
4363 if_t ifp = ctx->ifc_ifp;
4366 device_t dev = ctx->ifc_dev;
4368 struct taskqgroup *tqg;
4371 /* Make sure VLANS are not using driver */
4372 if (if_vlantrunkinuse(ifp)) {
4373 device_printf(dev,"Vlan in use, detach first\n");
4378 ctx->ifc_in_detach = 1;
4382 /* Unregister VLAN events */
4383 if (ctx->ifc_vlan_attach_event != NULL)
4384 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4385 if (ctx->ifc_vlan_detach_event != NULL)
4386 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4388 iflib_netmap_detach(ifp);
4389 ether_ifdetach(ifp);
4390 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4391 CTX_LOCK_DESTROY(ctx);
4392 if (ctx->ifc_led_dev != NULL)
4393 led_destroy(ctx->ifc_led_dev);
4394 /* XXX drain any dependent tasks */
4395 tqg = qgroup_if_io_tqg;
4396 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4397 callout_drain(&txq->ift_timer);
4398 if (txq->ift_task.gt_uniq != NULL)
4399 taskqgroup_detach(tqg, &txq->ift_task);
4401 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4402 if (rxq->ifr_task.gt_uniq != NULL)
4403 taskqgroup_detach(tqg, &rxq->ifr_task);
4405 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4406 free(fl->ifl_rx_bitmap, M_IFLIB);
4409 tqg = qgroup_if_config_tqg;
4410 if (ctx->ifc_admin_task.gt_uniq != NULL)
4411 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4412 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4413 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4416 device_set_softc(ctx->ifc_dev, NULL);
4417 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4418 pci_release_msi(dev);
4420 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4421 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4423 if (ctx->ifc_msix_mem != NULL) {
4424 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4425 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4426 ctx->ifc_msix_mem = NULL;
4429 bus_generic_detach(dev);
4432 iflib_tx_structures_free(ctx);
4433 iflib_rx_structures_free(ctx);
4434 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4435 free(ctx->ifc_softc, M_IFLIB);
4442 iflib_device_detach(device_t dev)
4444 if_ctx_t ctx = device_get_softc(dev);
4446 return (iflib_device_deregister(ctx));
4450 iflib_device_suspend(device_t dev)
4452 if_ctx_t ctx = device_get_softc(dev);
4458 return bus_generic_suspend(dev);
4461 iflib_device_shutdown(device_t dev)
4463 if_ctx_t ctx = device_get_softc(dev);
4469 return bus_generic_suspend(dev);
4474 iflib_device_resume(device_t dev)
4476 if_ctx_t ctx = device_get_softc(dev);
4477 iflib_txq_t txq = ctx->ifc_txqs;
4481 iflib_init_locked(ctx);
4483 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4484 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4486 return (bus_generic_resume(dev));
4490 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4493 if_ctx_t ctx = device_get_softc(dev);
4496 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4503 iflib_device_iov_uninit(device_t dev)
4505 if_ctx_t ctx = device_get_softc(dev);
4508 IFDI_IOV_UNINIT(ctx);
4513 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4516 if_ctx_t ctx = device_get_softc(dev);
4519 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4525 /*********************************************************************
4527 * MODULE FUNCTION DEFINITIONS
4529 **********************************************************************/
4532 * - Start a fast taskqueue thread for each core
4533 * - Start a taskqueue for control operations
4536 iflib_module_init(void)
4542 iflib_module_event_handler(module_t mod, int what, void *arg)
4548 if ((err = iflib_module_init()) != 0)
4554 return (EOPNOTSUPP);
4560 /*********************************************************************
4562 * PUBLIC FUNCTION DEFINITIONS
4563 * ordered as in iflib.h
4565 **********************************************************************/
4569 _iflib_assert(if_shared_ctx_t sctx)
4571 MPASS(sctx->isc_tx_maxsize);
4572 MPASS(sctx->isc_tx_maxsegsize);
4574 MPASS(sctx->isc_rx_maxsize);
4575 MPASS(sctx->isc_rx_nsegments);
4576 MPASS(sctx->isc_rx_maxsegsize);
4578 MPASS(sctx->isc_nrxd_min[0]);
4579 MPASS(sctx->isc_nrxd_max[0]);
4580 MPASS(sctx->isc_nrxd_default[0]);
4581 MPASS(sctx->isc_ntxd_min[0]);
4582 MPASS(sctx->isc_ntxd_max[0]);
4583 MPASS(sctx->isc_ntxd_default[0]);
4587 _iflib_pre_assert(if_softc_ctx_t scctx)
4590 MPASS(scctx->isc_txrx->ift_txd_encap);
4591 MPASS(scctx->isc_txrx->ift_txd_flush);
4592 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4593 MPASS(scctx->isc_txrx->ift_rxd_available);
4594 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4595 MPASS(scctx->isc_txrx->ift_rxd_refill);
4596 MPASS(scctx->isc_txrx->ift_rxd_flush);
4600 iflib_register(if_ctx_t ctx)
4602 if_shared_ctx_t sctx = ctx->ifc_sctx;
4603 driver_t *driver = sctx->isc_driver;
4604 device_t dev = ctx->ifc_dev;
4607 _iflib_assert(sctx);
4609 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4611 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4613 device_printf(dev, "can not allocate ifnet structure\n");
4618 * Initialize our context's device specific methods
4620 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4621 kobj_class_compile((kobj_class_t) driver);
4624 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4625 if_setsoftc(ifp, ctx);
4626 if_setdev(ifp, dev);
4627 if_setinitfn(ifp, iflib_if_init);
4628 if_setioctlfn(ifp, iflib_if_ioctl);
4629 if_settransmitfn(ifp, iflib_if_transmit);
4630 if_setqflushfn(ifp, iflib_if_qflush);
4631 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4633 ctx->ifc_vlan_attach_event =
4634 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4635 EVENTHANDLER_PRI_FIRST);
4636 ctx->ifc_vlan_detach_event =
4637 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4638 EVENTHANDLER_PRI_FIRST);
4640 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4641 iflib_media_change, iflib_media_status);
4648 iflib_queues_alloc(if_ctx_t ctx)
4650 if_shared_ctx_t sctx = ctx->ifc_sctx;
4651 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4652 device_t dev = ctx->ifc_dev;
4653 int nrxqsets = scctx->isc_nrxqsets;
4654 int ntxqsets = scctx->isc_ntxqsets;
4657 iflib_fl_t fl = NULL;
4658 int i, j, cpu, err, txconf, rxconf;
4659 iflib_dma_info_t ifdip;
4660 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4661 uint32_t *txqsizes = scctx->isc_txqsizes;
4662 uint8_t nrxqs = sctx->isc_nrxqs;
4663 uint8_t ntxqs = sctx->isc_ntxqs;
4664 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4667 struct ifmp_ring **brscp;
4669 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4670 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4676 /* Allocate the TX ring struct memory */
4678 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4679 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4680 device_printf(dev, "Unable to allocate TX ring memory\n");
4685 /* Now allocate the RX */
4687 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4688 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4689 device_printf(dev, "Unable to allocate RX ring memory\n");
4694 ctx->ifc_txqs = txq;
4695 ctx->ifc_rxqs = rxq;
4698 * XXX handle allocation failure
4700 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4701 /* Set up some basics */
4703 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4704 device_printf(dev, "failed to allocate iflib_dma_info\n");
4708 txq->ift_ifdi = ifdip;
4709 for (j = 0; j < ntxqs; j++, ifdip++) {
4710 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4711 device_printf(dev, "Unable to allocate Descriptor memory\n");
4715 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4716 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4720 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4721 txq->ift_br_offset = 1;
4723 txq->ift_br_offset = 0;
4726 txq->ift_timer.c_cpu = cpu;
4728 if (iflib_txsd_alloc(txq)) {
4729 device_printf(dev, "Critical Failure setting up TX buffers\n");
4734 /* Initialize the TX lock */
4735 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4736 device_get_nameunit(dev), txq->ift_id);
4737 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4738 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4740 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4741 device_get_nameunit(dev), txq->ift_id);
4743 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4744 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4746 /* XXX free any allocated rings */
4747 device_printf(dev, "Unable to allocate buf_ring\n");
4752 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4753 /* Set up some basics */
4755 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4756 device_printf(dev, "failed to allocate iflib_dma_info\n");
4761 rxq->ifr_ifdi = ifdip;
4762 /* XXX this needs to be changed if #rx queues != #tx queues */
4763 rxq->ifr_ntxqirq = 1;
4764 rxq->ifr_txqid[0] = i;
4765 for (j = 0; j < nrxqs; j++, ifdip++) {
4766 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4767 device_printf(dev, "Unable to allocate Descriptor memory\n");
4771 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4775 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4776 rxq->ifr_fl_offset = 1;
4778 rxq->ifr_fl_offset = 0;
4780 rxq->ifr_nfl = nfree_lists;
4782 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4783 device_printf(dev, "Unable to allocate free list memory\n");
4788 for (j = 0; j < nfree_lists; j++) {
4789 fl[j].ifl_rxq = rxq;
4791 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4792 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4794 /* Allocate receive buffers for the ring*/
4795 if (iflib_rxsd_alloc(rxq)) {
4797 "Critical Failure setting up receive buffers\n");
4802 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4803 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4807 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4808 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4809 for (i = 0; i < ntxqsets; i++) {
4810 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4812 for (j = 0; j < ntxqs; j++, di++) {
4813 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4814 paddrs[i*ntxqs + j] = di->idi_paddr;
4817 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4818 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4819 iflib_tx_structures_free(ctx);
4820 free(vaddrs, M_IFLIB);
4821 free(paddrs, M_IFLIB);
4824 free(vaddrs, M_IFLIB);
4825 free(paddrs, M_IFLIB);
4828 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4829 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4830 for (i = 0; i < nrxqsets; i++) {
4831 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4833 for (j = 0; j < nrxqs; j++, di++) {
4834 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4835 paddrs[i*nrxqs + j] = di->idi_paddr;
4838 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4839 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4840 iflib_tx_structures_free(ctx);
4841 free(vaddrs, M_IFLIB);
4842 free(paddrs, M_IFLIB);
4845 free(vaddrs, M_IFLIB);
4846 free(paddrs, M_IFLIB);
4850 /* XXX handle allocation failure changes */
4853 if (ctx->ifc_rxqs != NULL)
4854 free(ctx->ifc_rxqs, M_IFLIB);
4855 ctx->ifc_rxqs = NULL;
4856 if (ctx->ifc_txqs != NULL)
4857 free(ctx->ifc_txqs, M_IFLIB);
4858 ctx->ifc_txqs = NULL;
4861 free(brscp, M_IFLIB);
4871 iflib_tx_structures_setup(if_ctx_t ctx)
4873 iflib_txq_t txq = ctx->ifc_txqs;
4876 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4877 iflib_txq_setup(txq);
4883 iflib_tx_structures_free(if_ctx_t ctx)
4885 iflib_txq_t txq = ctx->ifc_txqs;
4888 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4889 iflib_txq_destroy(txq);
4890 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4891 iflib_dma_free(&txq->ift_ifdi[j]);
4893 free(ctx->ifc_txqs, M_IFLIB);
4894 ctx->ifc_txqs = NULL;
4895 IFDI_QUEUES_FREE(ctx);
4898 /*********************************************************************
4900 * Initialize all receive rings.
4902 **********************************************************************/
4904 iflib_rx_structures_setup(if_ctx_t ctx)
4906 iflib_rxq_t rxq = ctx->ifc_rxqs;
4908 #if defined(INET6) || defined(INET)
4912 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4913 #if defined(INET6) || defined(INET)
4914 tcp_lro_free(&rxq->ifr_lc);
4915 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4916 TCP_LRO_ENTRIES, min(1024,
4917 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4918 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4921 rxq->ifr_lro_enabled = TRUE;
4923 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4926 #if defined(INET6) || defined(INET)
4929 * Free RX software descriptors allocated so far, we will only handle
4930 * the rings that completed, the failing case will have
4931 * cleaned up for itself. 'q' failed, so its the terminus.
4933 rxq = ctx->ifc_rxqs;
4934 for (i = 0; i < q; ++i, rxq++) {
4935 iflib_rx_sds_free(rxq);
4936 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4942 /*********************************************************************
4944 * Free all receive rings.
4946 **********************************************************************/
4948 iflib_rx_structures_free(if_ctx_t ctx)
4950 iflib_rxq_t rxq = ctx->ifc_rxqs;
4952 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4953 iflib_rx_sds_free(rxq);
4958 iflib_qset_structures_setup(if_ctx_t ctx)
4962 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4965 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4966 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4967 iflib_tx_structures_free(ctx);
4968 iflib_rx_structures_free(ctx);
4974 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4975 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4978 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4982 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4984 int i, cpuid, eqid, count;
4986 CPU_COPY(&ctx->ifc_cpus, cpus);
4987 count = CPU_COUNT(&ctx->ifc_cpus);
4989 /* clear up to the qid'th bit */
4990 for (i = 0; i < eqid; i++) {
4991 cpuid = CPU_FFS(cpus);
4993 CPU_CLR(cpuid-1, cpus);
4995 cpuid = CPU_FFS(cpus);
5001 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5002 iflib_intr_type_t type, driver_filter_t *filter,
5003 void *filter_arg, int qid, char *name)
5005 struct grouptask *gtask;
5006 struct taskqgroup *tqg;
5007 iflib_filter_info_t info;
5010 int tqrid, err, cpuid;
5011 driver_filter_t *intr_fast;
5014 info = &ctx->ifc_filter_info;
5018 /* XXX merge tx/rx for netmap? */
5020 q = &ctx->ifc_txqs[qid];
5021 info = &ctx->ifc_txqs[qid].ift_filter_info;
5022 gtask = &ctx->ifc_txqs[qid].ift_task;
5023 tqg = qgroup_if_io_tqg;
5025 intr_fast = iflib_fast_intr;
5026 GROUPTASK_INIT(gtask, 0, fn, q);
5029 q = &ctx->ifc_rxqs[qid];
5030 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5031 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5032 tqg = qgroup_if_io_tqg;
5034 intr_fast = iflib_fast_intr;
5035 GROUPTASK_INIT(gtask, 0, fn, q);
5037 case IFLIB_INTR_RXTX:
5038 q = &ctx->ifc_rxqs[qid];
5039 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5040 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5041 tqg = qgroup_if_io_tqg;
5043 intr_fast = iflib_fast_intr_rxtx;
5044 GROUPTASK_INIT(gtask, 0, fn, q);
5046 case IFLIB_INTR_ADMIN:
5049 info = &ctx->ifc_filter_info;
5050 gtask = &ctx->ifc_admin_task;
5051 tqg = qgroup_if_config_tqg;
5052 fn = _task_fn_admin;
5053 intr_fast = iflib_fast_intr_ctx;
5056 panic("unknown net intr type");
5059 info->ifi_filter = filter;
5060 info->ifi_filter_arg = filter_arg;
5061 info->ifi_task = gtask;
5064 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5066 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5069 if (type == IFLIB_INTR_ADMIN)
5073 cpuid = find_nth(ctx, &cpus, qid);
5074 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, rman_get_start(irq->ii_res), name);
5076 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5083 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name)
5085 struct grouptask *gtask;
5086 struct taskqgroup *tqg;
5093 q = &ctx->ifc_txqs[qid];
5094 gtask = &ctx->ifc_txqs[qid].ift_task;
5095 tqg = qgroup_if_io_tqg;
5098 irq_num = rman_get_start(irq->ii_res);
5101 q = &ctx->ifc_rxqs[qid];
5102 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5103 tqg = qgroup_if_io_tqg;
5106 irq_num = rman_get_start(irq->ii_res);
5108 case IFLIB_INTR_IOV:
5110 gtask = &ctx->ifc_vflr_task;
5111 tqg = qgroup_if_config_tqg;
5115 panic("unknown net intr type");
5117 GROUPTASK_INIT(gtask, 0, fn, q);
5118 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5122 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5125 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5128 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5132 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5134 iflib_txq_t txq = ctx->ifc_txqs;
5135 iflib_rxq_t rxq = ctx->ifc_rxqs;
5136 if_irq_t irq = &ctx->ifc_legacy_irq;
5137 iflib_filter_info_t info;
5138 struct grouptask *gtask;
5139 struct taskqgroup *tqg;
5145 q = &ctx->ifc_rxqs[0];
5146 info = &rxq[0].ifr_filter_info;
5147 gtask = &rxq[0].ifr_task;
5148 tqg = qgroup_if_io_tqg;
5149 tqrid = irq->ii_rid = *rid;
5152 ctx->ifc_flags |= IFC_LEGACY;
5153 info->ifi_filter = filter;
5154 info->ifi_filter_arg = filter_arg;
5155 info->ifi_task = gtask;
5156 info->ifi_ctx = ctx;
5158 /* We allocate a single interrupt resource */
5159 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5161 GROUPTASK_INIT(gtask, 0, fn, q);
5162 taskqgroup_attach(tqg, gtask, q, tqrid, name);
5164 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5165 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx");
5170 iflib_led_create(if_ctx_t ctx)
5173 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5174 device_get_nameunit(ctx->ifc_dev));
5178 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5181 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5185 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5188 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5192 iflib_admin_intr_deferred(if_ctx_t ctx)
5195 struct grouptask *gtask;
5197 gtask = &ctx->ifc_admin_task;
5198 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5201 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5205 iflib_iov_intr_deferred(if_ctx_t ctx)
5208 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5212 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5215 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5219 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
5223 GROUPTASK_INIT(gtask, 0, fn, ctx);
5224 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5228 iflib_config_gtask_deinit(struct grouptask *gtask)
5231 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5235 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5237 if_t ifp = ctx->ifc_ifp;
5238 iflib_txq_t txq = ctx->ifc_txqs;
5240 if_setbaudrate(ifp, baudrate);
5241 if (baudrate >= IF_Gbps(10))
5242 ctx->ifc_flags |= IFC_PREFETCH;
5244 /* If link down, disable watchdog */
5245 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5246 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5247 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5249 ctx->ifc_link_state = link_state;
5250 if_link_state_change(ifp, link_state);
5254 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5258 int credits_pre = txq->ift_cidx_processed;
5261 if (ctx->isc_txd_credits_update == NULL)
5264 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5267 txq->ift_processed += credits;
5268 txq->ift_cidx_processed += credits;
5270 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5271 if (txq->ift_cidx_processed >= txq->ift_size)
5272 txq->ift_cidx_processed -= txq->ift_size;
5277 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5280 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5285 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5286 const char *description, if_int_delay_info_t info,
5287 int offset, int value)
5289 info->iidi_ctx = ctx;
5290 info->iidi_offset = offset;
5291 info->iidi_value = value;
5292 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5293 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5294 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5295 info, 0, iflib_sysctl_int_delay, "I", description);
5299 iflib_ctx_lock_get(if_ctx_t ctx)
5302 return (&ctx->ifc_mtx);
5306 iflib_msix_init(if_ctx_t ctx)
5308 device_t dev = ctx->ifc_dev;
5309 if_shared_ctx_t sctx = ctx->ifc_sctx;
5310 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5311 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5312 int iflib_num_tx_queues, iflib_num_rx_queues;
5313 int err, admincnt, bar;
5315 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5316 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5318 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5320 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5321 admincnt = sctx->isc_admin_intrcnt;
5322 /* Override by global tuneable */
5325 size_t len = sizeof(i);
5326 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0);
5332 device_printf(dev, "unable to read hw.pci.enable_msix.");
5335 /* Override by tuneable */
5336 if (scctx->isc_disable_msix)
5340 ** When used in a virtualized environment
5341 ** PCI BUSMASTER capability may not be set
5342 ** so explicity set it here and rewrite
5343 ** the ENABLE in the MSIX control register
5344 ** at this point to cause the host to
5345 ** successfully initialize us.
5350 pci_enable_busmaster(dev);
5352 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5353 rid += PCIR_MSIX_CTRL;
5354 msix_ctrl = pci_read_config(dev, rid, 2);
5355 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5356 pci_write_config(dev, rid, msix_ctrl, 2);
5358 device_printf(dev, "PCIY_MSIX capability not found; "
5359 "or rid %d == 0.\n", rid);
5365 * bar == -1 => "trust me I know what I'm doing"
5366 * Some drivers are for hardware that is so shoddily
5367 * documented that no one knows which bars are which
5368 * so the developer has to map all bars. This hack
5369 * allows shoddy garbage to use msix in this framework.
5372 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5373 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5374 if (ctx->ifc_msix_mem == NULL) {
5375 /* May not be enabled */
5376 device_printf(dev, "Unable to map MSIX table \n");
5380 /* First try MSI/X */
5381 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5382 device_printf(dev, "System has MSIX disabled \n");
5383 bus_release_resource(dev, SYS_RES_MEMORY,
5384 bar, ctx->ifc_msix_mem);
5385 ctx->ifc_msix_mem = NULL;
5389 /* use only 1 qset in debug mode */
5390 queuemsgs = min(msgs - admincnt, 1);
5392 queuemsgs = msgs - admincnt;
5394 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
5396 queues = imin(queuemsgs, rss_getnumbuckets());
5400 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5401 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5402 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5404 device_printf(dev, "Unable to fetch CPU list\n");
5405 /* Figure out a reasonable auto config value */
5406 queues = min(queuemsgs, mp_ncpus);
5409 /* If we're doing RSS, clamp at the number of RSS buckets */
5410 if (queues > rss_getnumbuckets())
5411 queues = rss_getnumbuckets();
5413 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5414 rx_queues = iflib_num_rx_queues;
5418 if (rx_queues > scctx->isc_nrxqsets)
5419 rx_queues = scctx->isc_nrxqsets;
5422 * We want this to be all logical CPUs by default
5424 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5425 tx_queues = iflib_num_tx_queues;
5427 tx_queues = mp_ncpus;
5429 if (tx_queues > scctx->isc_ntxqsets)
5430 tx_queues = scctx->isc_ntxqsets;
5432 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5434 if (tx_queues != rx_queues)
5435 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5436 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5438 tx_queues = min(rx_queues, tx_queues);
5439 rx_queues = min(rx_queues, tx_queues);
5442 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5444 vectors = rx_queues + admincnt;
5445 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5447 "Using MSIX interrupts with %d vectors\n", vectors);
5448 scctx->isc_vectors = vectors;
5449 scctx->isc_nrxqsets = rx_queues;
5450 scctx->isc_ntxqsets = tx_queues;
5451 scctx->isc_intr = IFLIB_INTR_MSIX;
5455 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5458 vectors = pci_msi_count(dev);
5459 scctx->isc_nrxqsets = 1;
5460 scctx->isc_ntxqsets = 1;
5461 scctx->isc_vectors = vectors;
5462 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5463 device_printf(dev,"Using an MSI interrupt\n");
5464 scctx->isc_intr = IFLIB_INTR_MSI;
5466 device_printf(dev,"Using a Legacy interrupt\n");
5467 scctx->isc_intr = IFLIB_INTR_LEGACY;
5473 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5476 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5479 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5481 char *ring_state = "UNKNOWN";
5484 rc = sysctl_wire_old_buffer(req, 0);
5488 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5493 ring_state = ring_states[state[3]];
5495 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5496 state[0], state[1], state[2], ring_state);
5497 rc = sbuf_finish(sb);
5502 enum iflib_ndesc_handler {
5508 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5510 if_ctx_t ctx = (void *)arg1;
5511 enum iflib_ndesc_handler type = arg2;
5512 char buf[256] = {0};
5517 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5521 case IFLIB_NTXD_HANDLER:
5522 ndesc = ctx->ifc_sysctl_ntxds;
5524 nqs = ctx->ifc_sctx->isc_ntxqs;
5526 case IFLIB_NRXD_HANDLER:
5527 ndesc = ctx->ifc_sysctl_nrxds;
5529 nqs = ctx->ifc_sctx->isc_nrxqs;
5535 for (i=0; i<8; i++) {
5540 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5543 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5544 if (rc || req->newptr == NULL)
5547 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5548 i++, p = strsep(&next, " ,")) {
5549 ndesc[i] = strtoul(p, NULL, 10);
5555 #define NAME_BUFLEN 32
5557 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5559 device_t dev = iflib_get_dev(ctx);
5560 struct sysctl_oid_list *child, *oid_list;
5561 struct sysctl_ctx_list *ctx_list;
5562 struct sysctl_oid *node;
5564 ctx_list = device_get_sysctl_ctx(dev);
5565 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5566 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5567 CTLFLAG_RD, NULL, "IFLIB fields");
5568 oid_list = SYSCTL_CHILDREN(node);
5570 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5571 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5574 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5575 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5576 "# of txqs to use, 0 => use default #");
5577 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5578 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5579 "# of rxqs to use, 0 => use default #");
5580 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5581 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5582 "permit #txq != #rxq");
5583 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5584 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5585 "disable MSIX (default 0)");
5586 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
5587 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
5588 "set the rx budget");
5590 /* XXX change for per-queue sizes */
5591 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5592 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5593 mp_ndesc_handler, "A",
5594 "list of # of tx descriptors to use, 0 = use default #");
5595 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5596 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5597 mp_ndesc_handler, "A",
5598 "list of # of rx descriptors to use, 0 = use default #");
5602 iflib_add_device_sysctl_post(if_ctx_t ctx)
5604 if_shared_ctx_t sctx = ctx->ifc_sctx;
5605 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5606 device_t dev = iflib_get_dev(ctx);
5607 struct sysctl_oid_list *child;
5608 struct sysctl_ctx_list *ctx_list;
5613 char namebuf[NAME_BUFLEN];
5615 struct sysctl_oid *queue_node, *fl_node, *node;
5616 struct sysctl_oid_list *queue_list, *fl_list;
5617 ctx_list = device_get_sysctl_ctx(dev);
5619 node = ctx->ifc_sysctl_node;
5620 child = SYSCTL_CHILDREN(node);
5622 if (scctx->isc_ntxqsets > 100)
5624 else if (scctx->isc_ntxqsets > 10)
5628 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5629 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5630 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5631 CTLFLAG_RD, NULL, "Queue Name");
5632 queue_list = SYSCTL_CHILDREN(queue_node);
5634 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5636 &txq->ift_dequeued, "total mbufs freed");
5637 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5639 &txq->ift_enqueued, "total mbufs enqueued");
5641 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5643 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5644 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5646 &txq->ift_pullups, "# of times m_pullup was called");
5647 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5649 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5650 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5652 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5653 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5655 &txq->ift_map_failed, "# of times dma map failed");
5656 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5658 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5659 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5661 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5662 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5664 &txq->ift_pidx, 1, "Producer Index");
5665 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5667 &txq->ift_cidx, 1, "Consumer Index");
5668 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5670 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5671 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5673 &txq->ift_in_use, 1, "descriptors in use");
5674 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5676 &txq->ift_processed, "descriptors procesed for clean");
5677 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5679 &txq->ift_cleaned, "total cleaned");
5680 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5681 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5682 0, mp_ring_state_handler, "A", "soft ring state");
5683 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5684 CTLFLAG_RD, &txq->ift_br->enqueues,
5685 "# of enqueues to the mp_ring for this queue");
5686 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5687 CTLFLAG_RD, &txq->ift_br->drops,
5688 "# of drops in the mp_ring for this queue");
5689 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5690 CTLFLAG_RD, &txq->ift_br->starts,
5691 "# of normal consumer starts in the mp_ring for this queue");
5692 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5693 CTLFLAG_RD, &txq->ift_br->stalls,
5694 "# of consumer stalls in the mp_ring for this queue");
5695 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5696 CTLFLAG_RD, &txq->ift_br->restarts,
5697 "# of consumer restarts in the mp_ring for this queue");
5698 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5699 CTLFLAG_RD, &txq->ift_br->abdications,
5700 "# of consumer abdications in the mp_ring for this queue");
5703 if (scctx->isc_nrxqsets > 100)
5705 else if (scctx->isc_nrxqsets > 10)
5709 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5710 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5711 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5712 CTLFLAG_RD, NULL, "Queue Name");
5713 queue_list = SYSCTL_CHILDREN(queue_node);
5714 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5715 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5717 &rxq->ifr_cq_pidx, 1, "Producer Index");
5718 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5720 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5723 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5724 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5725 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5726 CTLFLAG_RD, NULL, "freelist Name");
5727 fl_list = SYSCTL_CHILDREN(fl_node);
5728 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5730 &fl->ifl_pidx, 1, "Producer Index");
5731 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5733 &fl->ifl_cidx, 1, "Consumer Index");
5734 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5736 &fl->ifl_credits, 1, "credits available");
5738 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5740 &fl->ifl_m_enqueued, "mbufs allocated");
5741 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5743 &fl->ifl_m_dequeued, "mbufs freed");
5744 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5746 &fl->ifl_cl_enqueued, "clusters allocated");
5747 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5749 &fl->ifl_cl_dequeued, "clusters freed");
5757 #ifndef __NO_STRICT_ALIGNMENT
5758 static struct mbuf *
5759 iflib_fixup_rx(struct mbuf *m)
5763 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5764 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5765 m->m_data += ETHER_HDR_LEN;
5768 MGETHDR(n, M_NOWAIT, MT_DATA);
5773 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
5774 m->m_data += ETHER_HDR_LEN;
5775 m->m_len -= ETHER_HDR_LEN;
5776 n->m_len = ETHER_HDR_LEN;
5777 M_MOVE_PKTHDR(n, m);