2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
95 #if defined(__i386__) || defined(__amd64__)
96 #include <sys/memdesc.h>
97 #include <machine/bus.h>
98 #include <machine/md_var.h>
99 #include <machine/specialreg.h>
100 #include <x86/include/busdma_impl.h>
101 #include <x86/iommu/busdma_dmar.h>
105 #include <dev/pci/pci_iov.h>
108 #include <sys/bitstring.h>
110 * enable accounting of every mbuf as it comes in to and goes out of
111 * iflib's software descriptor references
113 #define MEMORY_LOGGING 0
115 * Enable mbuf vectors for compressing long mbuf chains
120 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
121 * we prefetch needs to be determined by the time spent in m_free vis a vis
122 * the cost of a prefetch. This will of course vary based on the workload:
123 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
124 * is quite expensive, thus suggesting very little prefetch.
125 * - small packet forwarding which is just returning a single mbuf to
126 * UMA will typically be very fast vis a vis the cost of a memory
133 * - private structures
134 * - iflib private utility functions
136 * - vlan registry and other exported functions
137 * - iflib public core functions
141 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
144 typedef struct iflib_txq *iflib_txq_t;
146 typedef struct iflib_rxq *iflib_rxq_t;
148 typedef struct iflib_fl *iflib_fl_t;
152 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
153 static void iflib_timer(void *arg);
155 typedef struct iflib_filter_info {
156 driver_filter_t *ifi_filter;
157 void *ifi_filter_arg;
158 struct grouptask *ifi_task;
160 } *iflib_filter_info_t;
165 * Pointer to hardware driver's softc
172 if_shared_ctx_t ifc_sctx;
173 struct if_softc_ctx ifc_softc_ctx;
175 struct sx ifc_ctx_sx;
176 struct mtx ifc_state_mtx;
178 uint16_t ifc_nhwtxqs;
180 iflib_txq_t ifc_txqs;
181 iflib_rxq_t ifc_rxqs;
182 uint32_t ifc_if_flags;
184 uint32_t ifc_max_fl_buf_size;
188 int ifc_watchdog_events;
189 struct cdev *ifc_led_dev;
190 struct resource *ifc_msix_mem;
192 struct if_irq ifc_legacy_irq;
193 struct grouptask ifc_admin_task;
194 struct grouptask ifc_vflr_task;
195 struct iflib_filter_info ifc_filter_info;
196 struct ifmedia ifc_media;
198 struct sysctl_oid *ifc_sysctl_node;
199 uint16_t ifc_sysctl_ntxqs;
200 uint16_t ifc_sysctl_nrxqs;
201 uint16_t ifc_sysctl_qs_eq_override;
202 uint16_t ifc_sysctl_rx_budget;
203 uint16_t ifc_sysctl_tx_abdicate;
205 qidx_t ifc_sysctl_ntxds[8];
206 qidx_t ifc_sysctl_nrxds[8];
207 struct if_txrx ifc_txrx;
208 #define isc_txd_encap ifc_txrx.ift_txd_encap
209 #define isc_txd_flush ifc_txrx.ift_txd_flush
210 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
211 #define isc_rxd_available ifc_txrx.ift_rxd_available
212 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
213 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
214 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
215 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
216 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
217 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
218 eventhandler_tag ifc_vlan_attach_event;
219 eventhandler_tag ifc_vlan_detach_event;
220 uint8_t ifc_mac[ETHER_ADDR_LEN];
221 char ifc_mtx_name[16];
226 iflib_get_softc(if_ctx_t ctx)
229 return (ctx->ifc_softc);
233 iflib_get_dev(if_ctx_t ctx)
236 return (ctx->ifc_dev);
240 iflib_get_ifp(if_ctx_t ctx)
243 return (ctx->ifc_ifp);
247 iflib_get_media(if_ctx_t ctx)
250 return (&ctx->ifc_media);
254 iflib_get_flags(if_ctx_t ctx)
256 return (ctx->ifc_flags);
260 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
263 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
267 iflib_get_softc_ctx(if_ctx_t ctx)
270 return (&ctx->ifc_softc_ctx);
274 iflib_get_sctx(if_ctx_t ctx)
277 return (ctx->ifc_sctx);
280 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
281 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
282 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
284 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
285 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
287 #define RX_SW_DESC_MAP_CREATED (1 << 0)
288 #define TX_SW_DESC_MAP_CREATED (1 << 1)
289 #define RX_SW_DESC_INUSE (1 << 3)
290 #define TX_SW_DESC_MAPPED (1 << 4)
292 #define M_TOOBIG M_PROTO1
294 typedef struct iflib_sw_rx_desc_array {
295 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
296 struct mbuf **ifsd_m; /* pkthdr mbufs */
297 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
299 } iflib_rxsd_array_t;
301 typedef struct iflib_sw_tx_desc_array {
302 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
303 struct mbuf **ifsd_m; /* pkthdr mbufs */
308 /* magic number that should be high enough for any hardware */
309 #define IFLIB_MAX_TX_SEGS 128
310 /* bnxt supports 64 with hardware LRO enabled */
311 #define IFLIB_MAX_RX_SEGS 64
312 #define IFLIB_RX_COPY_THRESH 128
313 #define IFLIB_MAX_RX_REFRESH 32
314 /* The minimum descriptors per second before we start coalescing */
315 #define IFLIB_MIN_DESC_SEC 16384
316 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
317 #define IFLIB_QUEUE_IDLE 0
318 #define IFLIB_QUEUE_HUNG 1
319 #define IFLIB_QUEUE_WORKING 2
320 /* maximum number of txqs that can share an rx interrupt */
321 #define IFLIB_MAX_TX_SHARED_INTR 4
323 /* this should really scale with ring size - this is a fairly arbitrary value */
324 #define TX_BATCH_SIZE 32
326 #define IFLIB_RESTART_BUDGET 8
329 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
330 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
331 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
335 qidx_t ift_cidx_processed;
338 uint8_t ift_br_offset;
339 uint16_t ift_npending;
340 uint16_t ift_db_pending;
341 uint16_t ift_rs_pending;
343 uint8_t ift_txd_size[8];
344 uint64_t ift_processed;
345 uint64_t ift_cleaned;
346 uint64_t ift_cleaned_prev;
348 uint64_t ift_enqueued;
349 uint64_t ift_dequeued;
351 uint64_t ift_no_tx_dma_setup;
352 uint64_t ift_no_desc_avail;
353 uint64_t ift_mbuf_defrag_failed;
354 uint64_t ift_mbuf_defrag;
355 uint64_t ift_map_failed;
356 uint64_t ift_txd_encap_efbig;
357 uint64_t ift_pullups;
358 uint64_t ift_last_timer_tick;
361 struct mtx ift_db_mtx;
363 /* constant values */
365 struct ifmp_ring *ift_br;
366 struct grouptask ift_task;
369 struct callout ift_timer;
371 if_txsd_vec_t ift_sds;
374 uint8_t ift_update_freq;
375 struct iflib_filter_info ift_filter_info;
376 bus_dma_tag_t ift_desc_tag;
377 bus_dma_tag_t ift_tso_desc_tag;
378 iflib_dma_info_t ift_ifdi;
379 #define MTX_NAME_LEN 16
380 char ift_mtx_name[MTX_NAME_LEN];
381 char ift_db_mtx_name[MTX_NAME_LEN];
382 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
383 #ifdef IFLIB_DIAGNOSTICS
384 uint64_t ift_cpu_exec_count[256];
386 } __aligned(CACHE_LINE_SIZE);
393 uint8_t ifl_rxd_size;
395 uint64_t ifl_m_enqueued;
396 uint64_t ifl_m_dequeued;
397 uint64_t ifl_cl_enqueued;
398 uint64_t ifl_cl_dequeued;
402 bitstr_t *ifl_rx_bitmap;
406 uint16_t ifl_buf_size;
409 iflib_rxsd_array_t ifl_sds;
412 bus_dma_tag_t ifl_desc_tag;
413 iflib_dma_info_t ifl_ifdi;
414 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
415 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
417 } __aligned(CACHE_LINE_SIZE);
420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
426 else if (pidx < cidx)
427 used = size - cidx + pidx;
428 else if (gen == 0 && pidx == cidx)
430 else if (gen == 1 && pidx == cidx)
438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
440 #define IDXDIFF(head, tail, wrap) \
441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
444 /* If there is a separate completion queue -
445 * these are the cq cidx and pidx. Otherwise
452 uint8_t ifr_fl_offset;
458 uint8_t ifr_lro_enabled;
461 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
462 struct lro_ctrl ifr_lc;
463 struct grouptask ifr_task;
464 struct iflib_filter_info ifr_filter_info;
465 iflib_dma_info_t ifr_ifdi;
467 /* dynamically allocate if any drivers need a value substantially larger than this */
468 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
469 #ifdef IFLIB_DIAGNOSTICS
470 uint64_t ifr_cpu_exec_count[256];
472 } __aligned(CACHE_LINE_SIZE);
474 typedef struct if_rxsd {
476 struct mbuf **ifsd_m;
481 /* multiple of word size */
483 #define PKT_INFO_SIZE 6
484 #define RXD_INFO_SIZE 5
485 #define PKT_TYPE uint64_t
487 #define PKT_INFO_SIZE 11
488 #define RXD_INFO_SIZE 8
489 #define PKT_TYPE uint32_t
491 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
492 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
494 typedef struct if_pkt_info_pad {
495 PKT_TYPE pkt_val[PKT_INFO_SIZE];
496 } *if_pkt_info_pad_t;
497 typedef struct if_rxd_info_pad {
498 PKT_TYPE rxd_val[RXD_INFO_SIZE];
499 } *if_rxd_info_pad_t;
501 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
502 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
506 pkt_info_zero(if_pkt_info_t pi)
508 if_pkt_info_pad_t pi_pad;
510 pi_pad = (if_pkt_info_pad_t)pi;
511 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
512 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
514 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
515 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
519 static device_method_t iflib_pseudo_methods[] = {
520 DEVMETHOD(device_attach, noop_attach),
521 DEVMETHOD(device_detach, iflib_pseudo_detach),
525 driver_t iflib_pseudodriver = {
526 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
530 rxd_info_zero(if_rxd_info_t ri)
532 if_rxd_info_pad_t ri_pad;
535 ri_pad = (if_rxd_info_pad_t)ri;
536 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
537 ri_pad->rxd_val[i] = 0;
538 ri_pad->rxd_val[i+1] = 0;
539 ri_pad->rxd_val[i+2] = 0;
540 ri_pad->rxd_val[i+3] = 0;
543 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
548 * Only allow a single packet to take up most 1/nth of the tx ring
550 #define MAX_SINGLE_PACKET_FRACTION 12
551 #define IF_BAD_DMA (bus_addr_t)-1
553 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
555 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
556 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
557 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
558 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
561 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
562 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
563 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
564 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
568 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
569 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
572 iflib_set_detach(if_ctx_t ctx)
575 ctx->ifc_flags |= IFC_IN_DETACH;
579 /* Our boot-time initialization hook */
580 static int iflib_module_event_handler(module_t, int, void *);
582 static moduledata_t iflib_moduledata = {
584 iflib_module_event_handler,
588 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
589 MODULE_VERSION(iflib, 1);
591 MODULE_DEPEND(iflib, pci, 1, 1, 1);
592 MODULE_DEPEND(iflib, ether, 1, 1, 1);
594 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
595 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
597 #ifndef IFLIB_DEBUG_COUNTERS
599 #define IFLIB_DEBUG_COUNTERS 1
601 #define IFLIB_DEBUG_COUNTERS 0
602 #endif /* !INVARIANTS */
605 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
606 "iflib driver parameters");
609 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
611 static int iflib_min_tx_latency = 0;
612 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
613 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
614 static int iflib_no_tx_batch = 0;
615 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
616 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
619 #if IFLIB_DEBUG_COUNTERS
621 static int iflib_tx_seen;
622 static int iflib_tx_sent;
623 static int iflib_tx_encap;
624 static int iflib_rx_allocs;
625 static int iflib_fl_refills;
626 static int iflib_fl_refills_large;
627 static int iflib_tx_frees;
629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
630 &iflib_tx_seen, 0, "# tx mbufs seen");
631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
632 &iflib_tx_sent, 0, "# tx mbufs sent");
633 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
634 &iflib_tx_encap, 0, "# tx mbufs encapped");
635 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
636 &iflib_tx_frees, 0, "# tx frees");
637 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
638 &iflib_rx_allocs, 0, "# rx allocations");
639 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
640 &iflib_fl_refills, 0, "# refills");
641 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
642 &iflib_fl_refills_large, 0, "# large refills");
645 static int iflib_txq_drain_flushing;
646 static int iflib_txq_drain_oactive;
647 static int iflib_txq_drain_notready;
649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
650 &iflib_txq_drain_flushing, 0, "# drain flushes");
651 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
652 &iflib_txq_drain_oactive, 0, "# drain oactives");
653 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
654 &iflib_txq_drain_notready, 0, "# drain notready");
657 static int iflib_encap_load_mbuf_fail;
658 static int iflib_encap_pad_mbuf_fail;
659 static int iflib_encap_txq_avail_fail;
660 static int iflib_encap_txd_encap_fail;
662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
663 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
665 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
666 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
667 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
668 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
669 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
671 static int iflib_task_fn_rxs;
672 static int iflib_rx_intr_enables;
673 static int iflib_fast_intrs;
674 static int iflib_rx_unavail;
675 static int iflib_rx_ctx_inactive;
676 static int iflib_rx_if_input;
677 static int iflib_rx_mbuf_null;
678 static int iflib_rxd_flush;
680 static int iflib_verbose_debug;
682 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
683 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
685 &iflib_rx_intr_enables, 0, "# rx intr enables");
686 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
687 &iflib_fast_intrs, 0, "# fast_intr calls");
688 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
689 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
691 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
692 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
693 &iflib_rx_if_input, 0, "# times rxeof called if_input");
694 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
695 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
696 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
697 &iflib_rxd_flush, 0, "# times rxd_flush called");
698 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
699 &iflib_verbose_debug, 0, "enable verbose debugging");
701 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
703 iflib_debug_reset(void)
705 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
706 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
707 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
708 iflib_txq_drain_notready =
709 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
710 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
711 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
713 iflib_rx_ctx_inactive = iflib_rx_if_input =
714 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
718 #define DBG_COUNTER_INC(name)
719 static void iflib_debug_reset(void) {}
722 #define IFLIB_DEBUG 0
724 static void iflib_tx_structures_free(if_ctx_t ctx);
725 static void iflib_rx_structures_free(if_ctx_t ctx);
726 static int iflib_queues_alloc(if_ctx_t ctx);
727 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
728 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
729 static int iflib_qset_structures_setup(if_ctx_t ctx);
730 static int iflib_msix_init(if_ctx_t ctx);
731 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
732 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
733 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
735 static void iflib_altq_if_start(if_t ifp);
736 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
738 static int iflib_register(if_ctx_t);
739 static void iflib_init_locked(if_ctx_t ctx);
740 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
741 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
742 static void iflib_ifmp_purge(iflib_txq_t txq);
743 static void _iflib_pre_assert(if_softc_ctx_t scctx);
744 static void iflib_if_init_locked(if_ctx_t ctx);
745 static void iflib_free_intr_mem(if_ctx_t ctx);
746 #ifndef __NO_STRICT_ALIGNMENT
747 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
750 NETDUMP_DEFINE(iflib);
753 #include <sys/selinfo.h>
754 #include <net/netmap.h>
755 #include <dev/netmap/netmap_kern.h>
757 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
762 * device-specific sysctl variables:
764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
765 * During regular operations the CRC is stripped, but on some
766 * hardware reception of frames not multiple of 64 is slower,
767 * so using crcstrip=0 helps in benchmarks.
769 * iflib_rx_miss, iflib_rx_miss_bufs:
770 * count packets that might be missed due to lost interrupts.
772 SYSCTL_DECL(_dev_netmap);
774 * The xl driver by default strips CRCs and we do not override it.
777 int iflib_crcstrip = 1;
778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
781 int iflib_rx_miss, iflib_rx_miss_bufs;
782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
788 * Register/unregister. We are already under netmap lock.
789 * Only called on the first register or the last unregister.
792 iflib_netmap_register(struct netmap_adapter *na, int onoff)
794 struct ifnet *ifp = na->ifp;
795 if_ctx_t ctx = ifp->if_softc;
799 IFDI_INTR_DISABLE(ctx);
801 /* Tell the stack that the interface is no longer active */
802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
807 /* enable or disable flags and callbacks in na and ifp */
809 nm_set_native_flags(na);
811 nm_clear_native_flags(na);
814 iflib_init_locked(ctx);
815 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
816 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
818 nm_clear_native_flags(na);
824 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
826 struct netmap_adapter *na = kring->na;
827 u_int const lim = kring->nkr_num_slots - 1;
828 u_int head = kring->rhead;
829 struct netmap_ring *ring = kring->ring;
831 struct if_rxd_update iru;
832 if_ctx_t ctx = rxq->ifr_ctx;
833 iflib_fl_t fl = &rxq->ifr_fl[0];
834 uint32_t refill_pidx, nic_i;
835 #if IFLIB_DEBUG_COUNTERS
839 if (nm_i == head && __predict_true(!init))
841 iru_init(&iru, rxq, 0 /* flid */);
842 map = fl->ifl_sds.ifsd_map;
843 refill_pidx = netmap_idx_k2n(kring, nm_i);
845 * IMPORTANT: we must leave one free slot in the ring,
846 * so move head back by one unit
848 head = nm_prev(head, lim);
850 DBG_COUNTER_INC(fl_refills);
851 while (nm_i != head) {
852 #if IFLIB_DEBUG_COUNTERS
854 DBG_COUNTER_INC(fl_refills_large);
856 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
857 struct netmap_slot *slot = &ring->slot[nm_i];
858 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
859 uint32_t nic_i_dma = refill_pidx;
860 nic_i = netmap_idx_k2n(kring, nm_i);
862 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
864 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
865 return netmap_ring_reinit(kring);
867 fl->ifl_vm_addrs[tmp_pidx] = addr;
868 if (__predict_false(init) && map) {
869 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
870 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
871 /* buffer has changed, reload map */
872 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
874 slot->flags &= ~NS_BUF_CHANGED;
876 nm_i = nm_next(nm_i, lim);
877 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
878 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
881 iru.iru_pidx = refill_pidx;
882 iru.iru_count = tmp_pidx+1;
883 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
889 for (int n = 0; n < iru.iru_count; n++) {
890 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
891 BUS_DMASYNC_PREREAD);
892 /* XXX - change this to not use the netmap func*/
893 nic_i_dma = nm_next(nic_i_dma, lim);
897 kring->nr_hwcur = head;
900 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
902 if (__predict_true(nic_i != UINT_MAX)) {
903 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
904 DBG_COUNTER_INC(rxd_flush);
910 * Reconcile kernel and user view of the transmit ring.
912 * All information is in the kring.
913 * Userspace wants to send packets up to the one before kring->rhead,
914 * kernel knows kring->nr_hwcur is the first unsent packet.
916 * Here we push packets out (as many as possible), and possibly
917 * reclaim buffers from previously completed transmission.
919 * The caller (netmap) guarantees that there is only one instance
920 * running at any time. Any interference with other driver
921 * methods should be handled by the individual drivers.
924 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
926 struct netmap_adapter *na = kring->na;
927 struct ifnet *ifp = na->ifp;
928 struct netmap_ring *ring = kring->ring;
929 u_int nm_i; /* index into the netmap kring */
930 u_int nic_i; /* index into the NIC ring */
932 u_int const lim = kring->nkr_num_slots - 1;
933 u_int const head = kring->rhead;
934 struct if_pkt_info pi;
937 * interrupts on every tx packet are expensive so request
938 * them every half ring, or where NS_REPORT is set
940 u_int report_frequency = kring->nkr_num_slots >> 1;
941 /* device-specific */
942 if_ctx_t ctx = ifp->if_softc;
943 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
945 if (txq->ift_sds.ifsd_map)
946 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
951 * First part: process new packets to send.
952 * nm_i is the current index in the netmap kring,
953 * nic_i is the corresponding index in the NIC ring.
955 * If we have packets to send (nm_i != head)
956 * iterate over the netmap ring, fetch length and update
957 * the corresponding slot in the NIC ring. Some drivers also
958 * need to update the buffer's physical address in the NIC slot
959 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
961 * The netmap_reload_map() calls is especially expensive,
962 * even when (as in this case) the tag is 0, so do only
963 * when the buffer has actually changed.
965 * If possible do not set the report/intr bit on all slots,
966 * but only a few times per ring or when NS_REPORT is set.
968 * Finally, on 10G and faster drivers, it might be useful
969 * to prefetch the next slot and txr entry.
972 nm_i = kring->nr_hwcur;
973 if (nm_i != head) { /* we have new packets to send */
975 pi.ipi_segs = txq->ift_segs;
976 pi.ipi_qsidx = kring->ring_id;
977 nic_i = netmap_idx_k2n(kring, nm_i);
979 __builtin_prefetch(&ring->slot[nm_i]);
980 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
981 if (txq->ift_sds.ifsd_map)
982 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
984 for (n = 0; nm_i != head; n++) {
985 struct netmap_slot *slot = &ring->slot[nm_i];
986 u_int len = slot->len;
988 void *addr = PNMB(na, slot, &paddr);
989 int flags = (slot->flags & NS_REPORT ||
990 nic_i == 0 || nic_i == report_frequency) ?
993 /* device-specific */
995 pi.ipi_segs[0].ds_addr = paddr;
996 pi.ipi_segs[0].ds_len = len;
1000 pi.ipi_flags = flags;
1002 /* Fill the slot in the NIC ring. */
1003 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1004 DBG_COUNTER_INC(tx_encap);
1006 /* prefetch for next round */
1007 __builtin_prefetch(&ring->slot[nm_i + 1]);
1008 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1009 if (txq->ift_sds.ifsd_map) {
1010 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1012 NM_CHECK_ADDR_LEN(na, addr, len);
1014 if (slot->flags & NS_BUF_CHANGED) {
1015 /* buffer has changed, reload map */
1016 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
1018 /* make sure changes to the buffer are synced */
1019 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1020 BUS_DMASYNC_PREWRITE);
1022 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1023 nm_i = nm_next(nm_i, lim);
1024 nic_i = nm_next(nic_i, lim);
1026 kring->nr_hwcur = nm_i;
1028 /* synchronize the NIC ring */
1029 if (txq->ift_sds.ifsd_map)
1030 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1031 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1033 /* (re)start the tx unit up to slot nic_i (excluded) */
1034 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1038 * Second part: reclaim buffers for completed transmissions.
1040 * If there are unclaimed buffers, attempt to reclaim them.
1041 * If none are reclaimed, and TX IRQs are not in use, do an initial
1042 * minimal delay, then trigger the tx handler which will spin in the
1045 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1046 if (iflib_tx_credits_update(ctx, txq)) {
1047 /* some tx completed, increment avail */
1048 nic_i = txq->ift_cidx_processed;
1049 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1052 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1053 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1054 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1055 iflib_timer, txq, txq->ift_timer.c_cpu);
1061 * Reconcile kernel and user view of the receive ring.
1062 * Same as for the txsync, this routine must be efficient.
1063 * The caller guarantees a single invocations, but races against
1064 * the rest of the driver should be handled here.
1066 * On call, kring->rhead is the first packet that userspace wants
1067 * to keep, and kring->rcur is the wakeup point.
1068 * The kernel has previously reported packets up to kring->rtail.
1070 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1071 * of whether or not we received an interrupt.
1074 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1076 struct netmap_adapter *na = kring->na;
1077 struct netmap_ring *ring = kring->ring;
1078 uint32_t nm_i; /* index into the netmap ring */
1079 uint32_t nic_i; /* index into the NIC ring */
1081 u_int const lim = kring->nkr_num_slots - 1;
1082 u_int const head = kring->rhead;
1083 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1084 struct if_rxd_info ri;
1086 struct ifnet *ifp = na->ifp;
1087 if_ctx_t ctx = ifp->if_softc;
1088 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1089 iflib_fl_t fl = rxq->ifr_fl;
1091 return netmap_ring_reinit(kring);
1093 /* XXX check sync modes */
1094 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1095 if (fl->ifl_sds.ifsd_map == NULL)
1097 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1098 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1101 * First part: import newly received packets.
1103 * nm_i is the index of the next free slot in the netmap ring,
1104 * nic_i is the index of the next received packet in the NIC ring,
1105 * and they may differ in case if_init() has been called while
1106 * in netmap mode. For the receive ring we have
1108 * nic_i = rxr->next_check;
1109 * nm_i = kring->nr_hwtail (previous)
1111 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1113 * rxr->next_check is set to 0 on a ring reinit
1115 if (netmap_no_pendintr || force_update) {
1116 int crclen = iflib_crcstrip ? 0 : 4;
1119 for (i = 0; i < rxq->ifr_nfl; i++) {
1120 fl = &rxq->ifr_fl[i];
1121 nic_i = fl->ifl_cidx;
1122 nm_i = netmap_idx_n2k(kring, nic_i);
1123 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1124 for (n = 0; avail > 0; n++, avail--) {
1126 ri.iri_frags = rxq->ifr_frags;
1127 ri.iri_qsidx = kring->ring_id;
1128 ri.iri_ifp = ctx->ifc_ifp;
1129 ri.iri_cidx = nic_i;
1131 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1132 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1133 ring->slot[nm_i].flags = 0;
1134 if (fl->ifl_sds.ifsd_map)
1135 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1136 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1137 nm_i = nm_next(nm_i, lim);
1138 nic_i = nm_next(nic_i, lim);
1140 if (n) { /* update the state variables */
1141 if (netmap_no_pendintr && !force_update) {
1144 iflib_rx_miss_bufs += n;
1146 fl->ifl_cidx = nic_i;
1147 kring->nr_hwtail = nm_i;
1149 kring->nr_kflags &= ~NKR_PENDINTR;
1153 * Second part: skip past packets that userspace has released.
1154 * (kring->nr_hwcur to head excluded),
1155 * and make the buffers available for reception.
1156 * As usual nm_i is the index in the netmap ring,
1157 * nic_i is the index in the NIC ring, and
1158 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1160 /* XXX not sure how this will work with multiple free lists */
1161 nm_i = kring->nr_hwcur;
1163 return (netmap_fl_refill(rxq, kring, nm_i, false));
1167 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1169 struct ifnet *ifp = na->ifp;
1170 if_ctx_t ctx = ifp->if_softc;
1174 IFDI_INTR_ENABLE(ctx);
1176 IFDI_INTR_DISABLE(ctx);
1183 iflib_netmap_attach(if_ctx_t ctx)
1185 struct netmap_adapter na;
1186 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1188 bzero(&na, sizeof(na));
1190 na.ifp = ctx->ifc_ifp;
1191 na.na_flags = NAF_BDG_MAYSLEEP;
1192 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1193 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1195 na.num_tx_desc = scctx->isc_ntxd[0];
1196 na.num_rx_desc = scctx->isc_nrxd[0];
1197 na.nm_txsync = iflib_netmap_txsync;
1198 na.nm_rxsync = iflib_netmap_rxsync;
1199 na.nm_register = iflib_netmap_register;
1200 na.nm_intr = iflib_netmap_intr;
1201 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1202 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1203 return (netmap_attach(&na));
1207 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1209 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1210 struct netmap_slot *slot;
1212 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1215 if (txq->ift_sds.ifsd_map == NULL)
1218 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1221 * In netmap mode, set the map for the packet buffer.
1222 * NOTE: Some drivers (not this one) also need to set
1223 * the physical buffer address in the NIC ring.
1224 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1225 * netmap slot index, si
1227 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1228 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1233 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1235 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1236 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1237 struct netmap_slot *slot;
1240 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1243 nm_i = netmap_idx_n2k(kring, 0);
1244 netmap_fl_refill(rxq, kring, nm_i, true);
1248 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1250 struct netmap_kring *kring;
1252 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1254 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1255 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1256 netmap_tx_irq(ctx->ifc_ifp, txqid);
1257 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1261 *reset_on = hz / 1000;
1266 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1269 #define iflib_netmap_txq_init(ctx, txq)
1270 #define iflib_netmap_rxq_init(ctx, rxq)
1271 #define iflib_netmap_detach(ifp)
1273 #define iflib_netmap_attach(ctx) (0)
1274 #define netmap_rx_irq(ifp, qid, budget) (0)
1275 #define netmap_tx_irq(ifp, qid) do {} while (0)
1276 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1280 #if defined(__i386__) || defined(__amd64__)
1281 static __inline void
1284 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1286 static __inline void
1287 prefetch2cachelines(void *x)
1289 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1290 #if (CACHE_LINE_SIZE < 128)
1291 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1296 #define prefetch2cachelines(x)
1300 iflib_gen_mac(if_ctx_t ctx)
1304 char uuid[HOSTUUIDLEN+1];
1305 char buf[HOSTUUIDLEN+16];
1307 unsigned char digest[16];
1311 uuid[HOSTUUIDLEN] = 0;
1312 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1313 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1315 * Generate a pseudo-random, deterministic MAC
1316 * address based on the UUID and unit number.
1317 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1320 MD5Update(&mdctx, buf, strlen(buf));
1321 MD5Final(digest, &mdctx);
1332 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1336 fl = &rxq->ifr_fl[flid];
1337 iru->iru_paddrs = fl->ifl_bus_addrs;
1338 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1339 iru->iru_idxs = fl->ifl_rxd_idxs;
1340 iru->iru_qsidx = rxq->ifr_id;
1341 iru->iru_buf_size = fl->ifl_buf_size;
1342 iru->iru_flidx = fl->ifl_id;
1346 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1350 *(bus_addr_t *) arg = segs[0].ds_addr;
1354 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1357 if_shared_ctx_t sctx = ctx->ifc_sctx;
1358 device_t dev = ctx->ifc_dev;
1360 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1362 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1363 sctx->isc_q_align, 0, /* alignment, bounds */
1364 BUS_SPACE_MAXADDR, /* lowaddr */
1365 BUS_SPACE_MAXADDR, /* highaddr */
1366 NULL, NULL, /* filter, filterarg */
1369 size, /* maxsegsize */
1370 BUS_DMA_ALLOCNOW, /* flags */
1371 NULL, /* lockfunc */
1376 "%s: bus_dma_tag_create failed: %d\n",
1381 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1382 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1385 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1386 __func__, (uintmax_t)size, err);
1390 dma->idi_paddr = IF_BAD_DMA;
1391 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1392 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1393 if (err || dma->idi_paddr == IF_BAD_DMA) {
1395 "%s: bus_dmamap_load failed: %d\n",
1400 dma->idi_size = size;
1404 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1406 bus_dma_tag_destroy(dma->idi_tag);
1408 dma->idi_tag = NULL;
1414 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1417 iflib_dma_info_t *dmaiter;
1420 for (i = 0; i < count; i++, dmaiter++) {
1421 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1425 iflib_dma_free_multi(dmalist, i);
1430 iflib_dma_free(iflib_dma_info_t dma)
1432 if (dma->idi_tag == NULL)
1434 if (dma->idi_paddr != IF_BAD_DMA) {
1435 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1436 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1437 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1438 dma->idi_paddr = IF_BAD_DMA;
1440 if (dma->idi_vaddr != NULL) {
1441 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1442 dma->idi_vaddr = NULL;
1444 bus_dma_tag_destroy(dma->idi_tag);
1445 dma->idi_tag = NULL;
1449 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1452 iflib_dma_info_t *dmaiter = dmalist;
1454 for (i = 0; i < count; i++, dmaiter++)
1455 iflib_dma_free(*dmaiter);
1458 #ifdef EARLY_AP_STARTUP
1459 static const int iflib_started = 1;
1462 * We used to abuse the smp_started flag to decide if the queues have been
1463 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1464 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1465 * is set. Run a SYSINIT() strictly after that to just set a usable
1469 static int iflib_started;
1472 iflib_record_started(void *arg)
1477 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1478 iflib_record_started, NULL);
1482 iflib_fast_intr(void *arg)
1484 iflib_filter_info_t info = arg;
1485 struct grouptask *gtask = info->ifi_task;
1487 return (FILTER_HANDLED);
1489 DBG_COUNTER_INC(fast_intrs);
1490 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1491 return (FILTER_HANDLED);
1493 GROUPTASK_ENQUEUE(gtask);
1494 return (FILTER_HANDLED);
1498 iflib_fast_intr_rxtx(void *arg)
1500 iflib_filter_info_t info = arg;
1501 struct grouptask *gtask = info->ifi_task;
1502 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1503 if_ctx_t ctx = NULL;;
1507 return (FILTER_HANDLED);
1509 DBG_COUNTER_INC(fast_intrs);
1510 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1511 return (FILTER_HANDLED);
1513 MPASS(rxq->ifr_ntxqirq);
1514 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1515 qidx_t txqid = rxq->ifr_txqid[i];
1519 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1520 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1523 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1525 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1526 cidx = rxq->ifr_cq_cidx;
1528 cidx = rxq->ifr_fl[0].ifl_cidx;
1529 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1530 GROUPTASK_ENQUEUE(gtask);
1532 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1533 DBG_COUNTER_INC(rx_intr_enables);
1535 return (FILTER_HANDLED);
1540 iflib_fast_intr_ctx(void *arg)
1542 iflib_filter_info_t info = arg;
1543 struct grouptask *gtask = info->ifi_task;
1546 return (FILTER_HANDLED);
1548 DBG_COUNTER_INC(fast_intrs);
1549 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1550 return (FILTER_HANDLED);
1552 GROUPTASK_ENQUEUE(gtask);
1553 return (FILTER_HANDLED);
1557 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1558 driver_filter_t filter, driver_intr_t handler, void *arg,
1562 struct resource *res;
1564 device_t dev = ctx->ifc_dev;
1567 if (ctx->ifc_flags & IFC_LEGACY)
1568 flags |= RF_SHAREABLE;
1571 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1574 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1578 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1579 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1580 filter, handler, arg, &tag);
1583 "failed to setup interrupt for rid %d, name %s: %d\n",
1584 rid, name ? name : "unknown", rc);
1587 bus_describe_intr(dev, res, tag, "%s", name);
1594 /*********************************************************************
1596 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1597 * the information needed to transmit a packet on the wire. This is
1598 * called only once at attach, setup is done every reset.
1600 **********************************************************************/
1603 iflib_txsd_alloc(iflib_txq_t txq)
1605 if_ctx_t ctx = txq->ift_ctx;
1606 if_shared_ctx_t sctx = ctx->ifc_sctx;
1607 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1608 device_t dev = ctx->ifc_dev;
1609 bus_size_t tsomaxsize;
1610 int err, nsegments, ntsosegments;
1612 nsegments = scctx->isc_tx_nsegments;
1613 ntsosegments = scctx->isc_tx_tso_segments_max;
1614 tsomaxsize = scctx->isc_tx_tso_size_max;
1615 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1616 tsomaxsize += sizeof(struct ether_vlan_header);
1617 MPASS(scctx->isc_ntxd[0] > 0);
1618 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1619 MPASS(nsegments > 0);
1620 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1621 MPASS(ntsosegments > 0);
1622 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1626 * Setup DMA descriptor areas.
1628 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1629 1, 0, /* alignment, bounds */
1630 BUS_SPACE_MAXADDR, /* lowaddr */
1631 BUS_SPACE_MAXADDR, /* highaddr */
1632 NULL, NULL, /* filter, filterarg */
1633 sctx->isc_tx_maxsize, /* maxsize */
1634 nsegments, /* nsegments */
1635 sctx->isc_tx_maxsegsize, /* maxsegsize */
1637 NULL, /* lockfunc */
1638 NULL, /* lockfuncarg */
1639 &txq->ift_desc_tag))) {
1640 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1641 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1642 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1645 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) &
1646 (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1647 1, 0, /* alignment, bounds */
1648 BUS_SPACE_MAXADDR, /* lowaddr */
1649 BUS_SPACE_MAXADDR, /* highaddr */
1650 NULL, NULL, /* filter, filterarg */
1651 tsomaxsize, /* maxsize */
1652 ntsosegments, /* nsegments */
1653 sctx->isc_tso_maxsegsize,/* maxsegsize */
1655 NULL, /* lockfunc */
1656 NULL, /* lockfuncarg */
1657 &txq->ift_tso_desc_tag))) {
1658 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1662 if (!(txq->ift_sds.ifsd_flags =
1663 (uint8_t *) malloc(sizeof(uint8_t) *
1664 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1665 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1669 if (!(txq->ift_sds.ifsd_m =
1670 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1671 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1672 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1677 /* Create the descriptor buffer dma maps */
1678 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1679 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1682 if (!(txq->ift_sds.ifsd_map =
1683 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1684 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1689 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1690 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1692 device_printf(dev, "Unable to create TX DMA map\n");
1699 /* We free all, it handles case where we are in the middle */
1700 iflib_tx_structures_free(ctx);
1705 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1710 if (txq->ift_sds.ifsd_map != NULL)
1711 map = txq->ift_sds.ifsd_map[i];
1713 bus_dmamap_unload(txq->ift_desc_tag, map);
1714 bus_dmamap_destroy(txq->ift_desc_tag, map);
1715 txq->ift_sds.ifsd_map[i] = NULL;
1720 iflib_txq_destroy(iflib_txq_t txq)
1722 if_ctx_t ctx = txq->ift_ctx;
1724 for (int i = 0; i < txq->ift_size; i++)
1725 iflib_txsd_destroy(ctx, txq, i);
1726 if (txq->ift_sds.ifsd_map != NULL) {
1727 free(txq->ift_sds.ifsd_map, M_IFLIB);
1728 txq->ift_sds.ifsd_map = NULL;
1730 if (txq->ift_sds.ifsd_m != NULL) {
1731 free(txq->ift_sds.ifsd_m, M_IFLIB);
1732 txq->ift_sds.ifsd_m = NULL;
1734 if (txq->ift_sds.ifsd_flags != NULL) {
1735 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1736 txq->ift_sds.ifsd_flags = NULL;
1738 if (txq->ift_desc_tag != NULL) {
1739 bus_dma_tag_destroy(txq->ift_desc_tag);
1740 txq->ift_desc_tag = NULL;
1742 if (txq->ift_tso_desc_tag != NULL) {
1743 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1744 txq->ift_tso_desc_tag = NULL;
1749 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1753 mp = &txq->ift_sds.ifsd_m[i];
1757 if (txq->ift_sds.ifsd_map != NULL) {
1758 bus_dmamap_sync(txq->ift_desc_tag,
1759 txq->ift_sds.ifsd_map[i],
1760 BUS_DMASYNC_POSTWRITE);
1761 bus_dmamap_unload(txq->ift_desc_tag,
1762 txq->ift_sds.ifsd_map[i]);
1765 DBG_COUNTER_INC(tx_frees);
1770 iflib_txq_setup(iflib_txq_t txq)
1772 if_ctx_t ctx = txq->ift_ctx;
1773 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1774 iflib_dma_info_t di;
1777 /* Set number of descriptors available */
1778 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1779 /* XXX make configurable */
1780 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1783 txq->ift_cidx_processed = 0;
1784 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1785 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1787 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1788 bzero((void *)di->idi_vaddr, di->idi_size);
1790 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1791 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1792 bus_dmamap_sync(di->idi_tag, di->idi_map,
1793 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1797 /*********************************************************************
1799 * Allocate memory for rx_buffer structures. Since we use one
1800 * rx_buffer per received packet, the maximum number of rx_buffer's
1801 * that we'll need is equal to the number of receive descriptors
1802 * that we've allocated.
1804 **********************************************************************/
1806 iflib_rxsd_alloc(iflib_rxq_t rxq)
1808 if_ctx_t ctx = rxq->ifr_ctx;
1809 if_shared_ctx_t sctx = ctx->ifc_sctx;
1810 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1811 device_t dev = ctx->ifc_dev;
1815 MPASS(scctx->isc_nrxd[0] > 0);
1816 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1819 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1820 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1821 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1822 1, 0, /* alignment, bounds */
1823 BUS_SPACE_MAXADDR, /* lowaddr */
1824 BUS_SPACE_MAXADDR, /* highaddr */
1825 NULL, NULL, /* filter, filterarg */
1826 sctx->isc_rx_maxsize, /* maxsize */
1827 sctx->isc_rx_nsegments, /* nsegments */
1828 sctx->isc_rx_maxsegsize, /* maxsegsize */
1830 NULL, /* lockfunc */
1834 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1838 if (!(fl->ifl_sds.ifsd_flags =
1839 (uint8_t *) malloc(sizeof(uint8_t) *
1840 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1841 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1845 if (!(fl->ifl_sds.ifsd_m =
1846 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1847 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1848 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1852 if (!(fl->ifl_sds.ifsd_cl =
1853 (caddr_t *) malloc(sizeof(caddr_t) *
1854 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1855 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1860 /* Create the descriptor buffer dma maps */
1861 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1862 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1865 if (!(fl->ifl_sds.ifsd_map =
1866 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1867 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1872 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1873 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1875 device_printf(dev, "Unable to create RX buffer DMA map\n");
1884 iflib_rx_structures_free(ctx);
1890 * Internal service routines
1893 struct rxq_refill_cb_arg {
1895 bus_dma_segment_t seg;
1900 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1902 struct rxq_refill_cb_arg *cb_arg = arg;
1904 cb_arg->error = error;
1905 cb_arg->seg = segs[0];
1906 cb_arg->nseg = nseg;
1911 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1913 #define IS_DMAR(ctx) (0)
1917 * rxq_refill - refill an rxq free-buffer list
1918 * @ctx: the iflib context
1919 * @rxq: the free-list to refill
1920 * @n: the number of new buffers to allocate
1922 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1923 * The caller must assure that @n does not exceed the queue's capacity.
1926 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1929 int idx, frag_idx = fl->ifl_fragidx;
1930 int pidx = fl->ifl_pidx;
1934 struct if_rxd_update iru;
1935 bus_dmamap_t *sd_map;
1941 sd_m = fl->ifl_sds.ifsd_m;
1942 sd_map = fl->ifl_sds.ifsd_map;
1943 sd_cl = fl->ifl_sds.ifsd_cl;
1944 sd_flags = fl->ifl_sds.ifsd_flags;
1946 credits = fl->ifl_credits;
1950 MPASS(credits + n <= fl->ifl_size);
1952 if (pidx < fl->ifl_cidx)
1953 MPASS(pidx + n <= fl->ifl_cidx);
1954 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1955 MPASS(fl->ifl_gen == 0);
1956 if (pidx > fl->ifl_cidx)
1957 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1959 DBG_COUNTER_INC(fl_refills);
1961 DBG_COUNTER_INC(fl_refills_large);
1962 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1965 * We allocate an uninitialized mbuf + cluster, mbuf is
1966 * initialized after rx.
1968 * If the cluster is still set then we know a minimum sized packet was received
1970 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1971 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1972 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1973 if ((cl = sd_cl[frag_idx]) == NULL) {
1974 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1977 fl->ifl_cl_enqueued++;
1980 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1984 fl->ifl_m_enqueued++;
1987 DBG_COUNTER_INC(rx_allocs);
1988 #if defined(__i386__) || defined(__amd64__)
1989 if (!IS_DMAR(ctx)) {
1990 bus_addr = pmap_kextract((vm_offset_t)cl);
1994 struct rxq_refill_cb_arg cb_arg;
1997 MPASS(sd_map != NULL);
1998 MPASS(sd_map[frag_idx] != NULL);
1999 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
2000 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
2001 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
2002 BUS_DMASYNC_PREREAD);
2004 if (err != 0 || cb_arg.error) {
2008 if (fl->ifl_zone == zone_pack)
2009 uma_zfree(fl->ifl_zone, cl);
2014 bus_addr = cb_arg.seg.ds_addr;
2016 bit_set(fl->ifl_rx_bitmap, frag_idx);
2017 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
2019 MPASS(sd_m[frag_idx] == NULL);
2020 sd_cl[frag_idx] = cl;
2022 fl->ifl_rxd_idxs[i] = frag_idx;
2023 fl->ifl_bus_addrs[i] = bus_addr;
2024 fl->ifl_vm_addrs[i] = cl;
2027 MPASS(credits <= fl->ifl_size);
2028 if (++idx == fl->ifl_size) {
2032 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2033 iru.iru_pidx = pidx;
2035 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2039 fl->ifl_credits = credits;
2045 iru.iru_pidx = pidx;
2047 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2049 fl->ifl_credits = credits;
2051 DBG_COUNTER_INC(rxd_flush);
2052 if (fl->ifl_pidx == 0)
2053 pidx = fl->ifl_size - 1;
2055 pidx = fl->ifl_pidx - 1;
2058 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2059 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2060 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2061 fl->ifl_fragidx = frag_idx;
2064 static __inline void
2065 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2067 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2068 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2070 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2073 MPASS(fl->ifl_credits <= fl->ifl_size);
2074 MPASS(reclaimable == delta);
2076 if (reclaimable > 0)
2077 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2081 iflib_in_detach(if_ctx_t ctx)
2085 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2091 iflib_fl_bufs_free(iflib_fl_t fl)
2093 iflib_dma_info_t idi = fl->ifl_ifdi;
2096 for (i = 0; i < fl->ifl_size; i++) {
2097 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2098 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
2099 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2101 if (*sd_flags & RX_SW_DESC_INUSE) {
2102 if (fl->ifl_sds.ifsd_map != NULL) {
2103 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
2104 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2105 // XXX: Should this get moved out?
2106 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2107 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2109 if (*sd_m != NULL) {
2110 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2111 uma_zfree(zone_mbuf, *sd_m);
2114 uma_zfree(fl->ifl_zone, *sd_cl);
2117 MPASS(*sd_cl == NULL);
2118 MPASS(*sd_m == NULL);
2121 fl->ifl_m_dequeued++;
2122 fl->ifl_cl_dequeued++;
2128 for (i = 0; i < fl->ifl_size; i++) {
2129 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2130 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2131 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2135 * Reset free list values
2137 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2138 bzero(idi->idi_vaddr, idi->idi_size);
2141 /*********************************************************************
2143 * Initialize a receive ring and its buffers.
2145 **********************************************************************/
2147 iflib_fl_setup(iflib_fl_t fl)
2149 iflib_rxq_t rxq = fl->ifl_rxq;
2150 if_ctx_t ctx = rxq->ifr_ctx;
2151 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2153 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2155 ** Free current RX buffer structs and their mbufs
2157 iflib_fl_bufs_free(fl);
2158 /* Now replenish the mbufs */
2159 MPASS(fl->ifl_credits == 0);
2161 * XXX don't set the max_frame_size to larger
2162 * than the hardware can handle
2164 if (sctx->isc_max_frame_size <= 2048)
2165 fl->ifl_buf_size = MCLBYTES;
2166 #ifndef CONTIGMALLOC_WORKS
2168 fl->ifl_buf_size = MJUMPAGESIZE;
2170 else if (sctx->isc_max_frame_size <= 4096)
2171 fl->ifl_buf_size = MJUMPAGESIZE;
2172 else if (sctx->isc_max_frame_size <= 9216)
2173 fl->ifl_buf_size = MJUM9BYTES;
2175 fl->ifl_buf_size = MJUM16BYTES;
2177 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2178 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2179 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2180 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2183 /* avoid pre-allocating zillions of clusters to an idle card
2184 * potentially speeding up attach
2186 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2187 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2188 if (min(128, fl->ifl_size) != fl->ifl_credits)
2194 MPASS(fl->ifl_ifdi != NULL);
2195 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2196 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2200 /*********************************************************************
2202 * Free receive ring data structures
2204 **********************************************************************/
2206 iflib_rx_sds_free(iflib_rxq_t rxq)
2211 if (rxq->ifr_fl != NULL) {
2212 for (i = 0; i < rxq->ifr_nfl; i++) {
2213 fl = &rxq->ifr_fl[i];
2214 if (fl->ifl_desc_tag != NULL) {
2215 bus_dma_tag_destroy(fl->ifl_desc_tag);
2216 fl->ifl_desc_tag = NULL;
2218 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2219 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2220 /* XXX destroy maps first */
2221 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2222 fl->ifl_sds.ifsd_m = NULL;
2223 fl->ifl_sds.ifsd_cl = NULL;
2224 fl->ifl_sds.ifsd_map = NULL;
2226 free(rxq->ifr_fl, M_IFLIB);
2228 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2233 * MI independent logic
2237 iflib_timer(void *arg)
2239 iflib_txq_t txq = arg;
2240 if_ctx_t ctx = txq->ift_ctx;
2241 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2242 uint64_t this_tick = ticks;
2243 uint32_t reset_on = hz / 2;
2245 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2248 ** Check on the state of the TX queue(s), this
2249 ** can be done without the lock because its RO
2250 ** and the HUNG state will be static if set.
2252 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2253 txq->ift_last_timer_tick = this_tick;
2254 IFDI_TIMER(ctx, txq->ift_id);
2255 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2256 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2257 (sctx->isc_pause_frames == 0)))
2260 if (ifmp_ring_is_stalled(txq->ift_br))
2261 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2262 txq->ift_cleaned_prev = txq->ift_cleaned;
2265 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2266 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2268 /* handle any laggards */
2269 if (txq->ift_db_pending)
2270 GROUPTASK_ENQUEUE(&txq->ift_task);
2272 sctx->isc_pause_frames = 0;
2273 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2274 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2277 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2278 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2280 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2281 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2282 iflib_admin_intr_deferred(ctx);
2287 iflib_init_locked(if_ctx_t ctx)
2289 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2290 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2291 if_t ifp = ctx->ifc_ifp;
2295 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2298 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2299 IFDI_INTR_DISABLE(ctx);
2301 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2302 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2303 /* Set hardware offload abilities */
2304 if_clearhwassist(ifp);
2305 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2306 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2307 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2308 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2309 if (if_getcapenable(ifp) & IFCAP_TSO4)
2310 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2311 if (if_getcapenable(ifp) & IFCAP_TSO6)
2312 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2314 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2316 callout_stop(&txq->ift_timer);
2317 CALLOUT_UNLOCK(txq);
2318 iflib_netmap_txq_init(ctx, txq);
2321 i = if_getdrvflags(ifp);
2324 MPASS(if_getdrvflags(ifp) == i);
2325 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2326 /* XXX this should really be done on a per-queue basis */
2327 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2328 MPASS(rxq->ifr_id == i);
2329 iflib_netmap_rxq_init(ctx, rxq);
2332 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2333 if (iflib_fl_setup(fl)) {
2334 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2340 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2341 IFDI_INTR_ENABLE(ctx);
2342 txq = ctx->ifc_txqs;
2343 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2344 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2345 txq->ift_timer.c_cpu);
2349 iflib_media_change(if_t ifp)
2351 if_ctx_t ctx = if_getsoftc(ifp);
2355 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2356 iflib_init_locked(ctx);
2362 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2364 if_ctx_t ctx = if_getsoftc(ifp);
2367 IFDI_UPDATE_ADMIN_STATUS(ctx);
2368 IFDI_MEDIA_STATUS(ctx, ifmr);
2373 iflib_stop(if_ctx_t ctx)
2375 iflib_txq_t txq = ctx->ifc_txqs;
2376 iflib_rxq_t rxq = ctx->ifc_rxqs;
2377 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2378 iflib_dma_info_t di;
2382 /* Tell the stack that the interface is no longer active */
2383 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2385 IFDI_INTR_DISABLE(ctx);
2390 iflib_debug_reset();
2391 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2392 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2393 /* make sure all transmitters have completed before proceeding XXX */
2396 callout_stop(&txq->ift_timer);
2397 CALLOUT_UNLOCK(txq);
2399 /* clean any enqueued buffers */
2400 iflib_ifmp_purge(txq);
2401 /* Free any existing tx buffers. */
2402 for (j = 0; j < txq->ift_size; j++) {
2403 iflib_txsd_free(ctx, txq, j);
2405 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2406 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2407 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2408 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2409 txq->ift_pullups = 0;
2410 ifmp_ring_reset_stats(txq->ift_br);
2411 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2412 bzero((void *)di->idi_vaddr, di->idi_size);
2414 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2415 /* make sure all transmitters have completed before proceeding XXX */
2417 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++)
2418 bzero((void *)di->idi_vaddr, di->idi_size);
2419 /* also resets the free lists pidx/cidx */
2420 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2421 iflib_fl_bufs_free(fl);
2425 static inline caddr_t
2426 calc_next_rxd(iflib_fl_t fl, int cidx)
2430 caddr_t start, end, cur, next;
2432 nrxd = fl->ifl_size;
2433 size = fl->ifl_rxd_size;
2434 start = fl->ifl_ifdi->idi_vaddr;
2436 if (__predict_false(size == 0))
2438 cur = start + size*cidx;
2439 end = start + size*nrxd;
2440 next = CACHE_PTR_NEXT(cur);
2441 return (next < end ? next : start);
2445 prefetch_pkts(iflib_fl_t fl, int cidx)
2448 int nrxd = fl->ifl_size;
2452 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2453 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2454 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2455 next_rxd = calc_next_rxd(fl, cidx);
2457 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2458 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2459 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2460 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2461 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2462 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2463 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2464 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2468 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2473 iflib_dma_info_t di;
2477 flid = irf->irf_flid;
2478 cidx = irf->irf_idx;
2479 fl = &rxq->ifr_fl[flid];
2481 sd->ifsd_cidx = cidx;
2482 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2483 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2486 fl->ifl_m_dequeued++;
2488 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2489 prefetch_pkts(fl, cidx);
2490 if (fl->ifl_sds.ifsd_map != NULL) {
2491 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2492 prefetch(&fl->ifl_sds.ifsd_map[next]);
2493 map = fl->ifl_sds.ifsd_map[cidx];
2495 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2496 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2497 bus_dmamap_sync(di->idi_tag, di->idi_map,
2498 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2500 /* not valid assert if bxe really does SGE from non-contiguous elements */
2501 MPASS(fl->ifl_cidx == cidx);
2503 bus_dmamap_unload(fl->ifl_desc_tag, map);
2505 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2506 if (__predict_false(fl->ifl_cidx == 0))
2509 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2511 bit_clear(fl->ifl_rx_bitmap, cidx);
2514 static struct mbuf *
2515 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2517 int i, padlen , flags;
2518 struct mbuf *m, *mh, *mt;
2524 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2526 MPASS(*sd->ifsd_cl != NULL);
2527 MPASS(*sd->ifsd_m != NULL);
2529 /* Don't include zero-length frags */
2530 if (ri->iri_frags[i].irf_len == 0) {
2531 /* XXX we can save the cluster here, but not the mbuf */
2532 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2533 m_free(*sd->ifsd_m);
2540 flags = M_PKTHDR|M_EXT;
2542 padlen = ri->iri_pad;
2547 /* assuming padding is only on the first fragment */
2551 *sd->ifsd_cl = NULL;
2553 /* Can these two be made one ? */
2554 m_init(m, M_NOWAIT, MT_DATA, flags);
2555 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2557 * These must follow m_init and m_cljset
2559 m->m_data += padlen;
2560 ri->iri_len -= padlen;
2561 m->m_len = ri->iri_frags[i].irf_len;
2562 } while (++i < ri->iri_nfrags);
2568 * Process one software descriptor
2570 static struct mbuf *
2571 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2576 /* should I merge this back in now that the two paths are basically duplicated? */
2577 if (ri->iri_nfrags == 1 &&
2578 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2579 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2582 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2583 #ifndef __NO_STRICT_ALIGNMENT
2587 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2588 m->m_len = ri->iri_frags[0].irf_len;
2590 m = assemble_segments(rxq, ri, &sd);
2592 m->m_pkthdr.len = ri->iri_len;
2593 m->m_pkthdr.rcvif = ri->iri_ifp;
2594 m->m_flags |= ri->iri_flags;
2595 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2596 m->m_pkthdr.flowid = ri->iri_flowid;
2597 M_HASHTYPE_SET(m, ri->iri_rsstype);
2598 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2599 m->m_pkthdr.csum_data = ri->iri_csum_data;
2603 #if defined(INET6) || defined(INET)
2605 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2607 CURVNET_SET(lc->ifp->if_vnet);
2609 *v6 = VNET(ip6_forwarding);
2612 *v4 = VNET(ipforwarding);
2618 * Returns true if it's possible this packet could be LROed.
2619 * if it returns false, it is guaranteed that tcp_lro_rx()
2620 * would not return zero.
2623 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2625 struct ether_header *eh;
2628 eh = mtod(m, struct ether_header *);
2629 eh_type = ntohs(eh->ether_type);
2632 case ETHERTYPE_IPV6:
2633 return !v6_forwarding;
2637 return !v4_forwarding;
2645 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2651 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2653 if_ctx_t ctx = rxq->ifr_ctx;
2654 if_shared_ctx_t sctx = ctx->ifc_sctx;
2655 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2658 struct if_rxd_info ri;
2659 int err, budget_left, rx_bytes, rx_pkts;
2663 bool v4_forwarding, v6_forwarding, lro_possible;
2666 * XXX early demux data packets so that if_input processing only handles
2667 * acks in interrupt context
2669 struct mbuf *m, *mh, *mt, *mf;
2671 lro_possible = v4_forwarding = v6_forwarding = false;
2675 rx_pkts = rx_bytes = 0;
2676 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2677 cidxp = &rxq->ifr_cq_cidx;
2679 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2680 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2681 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2682 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2683 DBG_COUNTER_INC(rx_unavail);
2687 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2688 if (__predict_false(!CTX_ACTIVE(ctx))) {
2689 DBG_COUNTER_INC(rx_ctx_inactive);
2693 * Reset client set fields to their default values
2696 ri.iri_qsidx = rxq->ifr_id;
2697 ri.iri_cidx = *cidxp;
2699 ri.iri_frags = rxq->ifr_frags;
2700 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2704 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2705 *cidxp = ri.iri_cidx;
2706 /* Update our consumer index */
2707 /* XXX NB: shurd - check if this is still safe */
2708 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2709 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2710 rxq->ifr_cq_gen = 0;
2712 /* was this only a completion queue message? */
2713 if (__predict_false(ri.iri_nfrags == 0))
2716 MPASS(ri.iri_nfrags != 0);
2717 MPASS(ri.iri_len != 0);
2719 /* will advance the cidx on the corresponding free lists */
2720 m = iflib_rxd_pkt_get(rxq, &ri);
2723 if (avail == 0 && budget_left)
2724 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2726 if (__predict_false(m == NULL)) {
2727 DBG_COUNTER_INC(rx_mbuf_null);
2730 /* imm_pkt: -- cxgb */
2738 /* make sure that we can refill faster than drain */
2739 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2740 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2742 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2744 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2746 while (mh != NULL) {
2749 m->m_nextpkt = NULL;
2750 #ifndef __NO_STRICT_ALIGNMENT
2751 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2754 rx_bytes += m->m_pkthdr.len;
2756 #if defined(INET6) || defined(INET)
2758 if (!lro_possible) {
2759 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2760 if (lro_possible && mf != NULL) {
2761 ifp->if_input(ifp, mf);
2762 DBG_COUNTER_INC(rx_if_input);
2766 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2767 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2768 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2774 ifp->if_input(ifp, m);
2775 DBG_COUNTER_INC(rx_if_input);
2786 ifp->if_input(ifp, mf);
2787 DBG_COUNTER_INC(rx_if_input);
2790 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2791 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2794 * Flush any outstanding LRO work
2796 #if defined(INET6) || defined(INET)
2797 tcp_lro_flush_all(&rxq->ifr_lc);
2801 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2804 ctx->ifc_flags |= IFC_DO_RESET;
2805 iflib_admin_intr_deferred(ctx);
2810 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2811 static inline qidx_t
2812 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2814 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2815 qidx_t minthresh = txq->ift_size / 8;
2816 if (in_use > 4*minthresh)
2817 return (notify_count);
2818 if (in_use > 2*minthresh)
2819 return (notify_count >> 1);
2820 if (in_use > minthresh)
2821 return (notify_count >> 3);
2825 static inline qidx_t
2826 txq_max_rs_deferred(iflib_txq_t txq)
2828 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2829 qidx_t minthresh = txq->ift_size / 8;
2830 if (txq->ift_in_use > 4*minthresh)
2831 return (notify_count);
2832 if (txq->ift_in_use > 2*minthresh)
2833 return (notify_count >> 1);
2834 if (txq->ift_in_use > minthresh)
2835 return (notify_count >> 2);
2839 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2840 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2842 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2843 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2844 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2846 /* forward compatibility for cxgb */
2847 #define FIRST_QSET(ctx) 0
2848 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2849 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2850 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2851 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2853 /* XXX we should be setting this to something other than zero */
2854 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2855 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2856 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2859 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2865 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2866 if (ring || txq->ift_db_pending >= max) {
2867 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2868 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2869 txq->ift_db_pending = txq->ift_npending = 0;
2877 print_pkt(if_pkt_info_t pi)
2879 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2880 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2881 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2882 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2883 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2884 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2888 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2889 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2890 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2891 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2894 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2896 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2897 struct ether_vlan_header *eh;
2901 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2902 M_WRITABLE(m) == 0) {
2903 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2907 DBG_COUNTER_INC(tx_frees);
2913 * Determine where frame payload starts.
2914 * Jump over vlan headers if already present,
2915 * helpful for QinQ too.
2917 if (__predict_false(m->m_len < sizeof(*eh))) {
2919 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2922 eh = mtod(m, struct ether_vlan_header *);
2923 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2924 pi->ipi_etype = ntohs(eh->evl_proto);
2925 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2927 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2928 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2931 switch (pi->ipi_etype) {
2936 struct ip *ip = NULL;
2937 struct tcphdr *th = NULL;
2940 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2941 if (__predict_false(m->m_len < minthlen)) {
2943 * if this code bloat is causing too much of a hit
2944 * move it to a separate function and mark it noinline
2946 if (m->m_len == pi->ipi_ehdrlen) {
2949 if (n->m_len >= sizeof(*ip)) {
2950 ip = (struct ip *)n->m_data;
2951 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2952 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2955 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2957 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2961 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2963 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2964 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2965 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2968 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2969 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2970 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2972 pi->ipi_ip_hlen = ip->ip_hl << 2;
2973 pi->ipi_ipproto = ip->ip_p;
2974 pi->ipi_flags |= IPI_TX_IPV4;
2976 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2979 /* TCP checksum offload may require TCP header length */
2980 if (IS_TX_OFFLOAD4(pi)) {
2981 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2982 if (__predict_false(th == NULL)) {
2984 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2986 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2988 pi->ipi_tcp_hflags = th->th_flags;
2989 pi->ipi_tcp_hlen = th->th_off << 2;
2990 pi->ipi_tcp_seq = th->th_seq;
2993 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2995 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2996 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2997 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2998 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3000 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3008 case ETHERTYPE_IPV6:
3010 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3012 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3014 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3016 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3019 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3021 /* XXX-BZ this will go badly in case of ext hdrs. */
3022 pi->ipi_ipproto = ip6->ip6_nxt;
3023 pi->ipi_flags |= IPI_TX_IPV6;
3025 /* TCP checksum offload may require TCP header length */
3026 if (IS_TX_OFFLOAD6(pi)) {
3027 if (pi->ipi_ipproto == IPPROTO_TCP) {
3028 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3030 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3033 pi->ipi_tcp_hflags = th->th_flags;
3034 pi->ipi_tcp_hlen = th->th_off << 2;
3035 pi->ipi_tcp_seq = th->th_seq;
3038 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3041 * The corresponding flag is set by the stack in the IPv4
3042 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
3043 * So, set it here because the rest of the flow requires it.
3045 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3046 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3047 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3054 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3055 pi->ipi_ip_hlen = 0;
3064 * If dodgy hardware rejects the scatter gather chain we've handed it
3065 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3068 static __noinline struct mbuf *
3069 iflib_remove_mbuf(iflib_txq_t txq)
3072 struct mbuf *m, *mh, **ifsd_m;
3074 pidx = txq->ift_pidx;
3075 ifsd_m = txq->ift_sds.ifsd_m;
3076 ntxd = txq->ift_size;
3077 mh = m = ifsd_m[pidx];
3078 ifsd_m[pidx] = NULL;
3080 txq->ift_dequeued++;
3085 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
3087 txq->ift_dequeued++;
3096 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
3097 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
3098 int max_segs, int flags)
3101 if_shared_ctx_t sctx;
3102 if_softc_ctx_t scctx;
3103 int i, next, pidx, err, ntxd, count;
3104 struct mbuf *m, *tmp, **ifsd_m;
3109 * Please don't ever do this
3111 MPASS(__predict_true(m->m_len > 0));
3114 sctx = ctx->ifc_sctx;
3115 scctx = &ctx->ifc_softc_ctx;
3116 ifsd_m = txq->ift_sds.ifsd_m;
3117 ntxd = txq->ift_size;
3118 pidx = txq->ift_pidx;
3120 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3122 err = bus_dmamap_load_mbuf_sg(tag, map,
3123 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3126 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3130 if (__predict_false(m->m_len <= 0)) {
3139 } while (m != NULL);
3140 if (count > *nsegs) {
3142 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3148 next = (pidx + count) & (ntxd-1);
3149 MPASS(ifsd_m[next] == NULL);
3154 } while (m != NULL);
3156 int buflen, sgsize, maxsegsz, max_sgsize;
3162 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3163 maxsegsz = scctx->isc_tx_tso_segsize_max;
3165 maxsegsz = sctx->isc_tx_maxsegsize;
3168 if (__predict_false(m->m_len <= 0)) {
3176 vaddr = (vm_offset_t)m->m_data;
3178 * see if we can't be smarter about physically
3179 * contiguous mappings
3181 next = (pidx + count) & (ntxd-1);
3182 MPASS(ifsd_m[next] == NULL);
3184 txq->ift_enqueued++;
3187 while (buflen > 0) {
3190 max_sgsize = MIN(buflen, maxsegsz);
3191 curaddr = pmap_kextract(vaddr);
3192 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3193 sgsize = MIN(sgsize, max_sgsize);
3194 segs[i].ds_addr = curaddr;
3195 segs[i].ds_len = sgsize;
3203 } while (m != NULL);
3208 *m0 = iflib_remove_mbuf(txq);
3212 static inline caddr_t
3213 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3217 caddr_t start, end, cur, next;
3219 ntxd = txq->ift_size;
3220 size = txq->ift_txd_size[qid];
3221 start = txq->ift_ifdi[qid].idi_vaddr;
3223 if (__predict_false(size == 0))
3225 cur = start + size*cidx;
3226 end = start + size*ntxd;
3227 next = CACHE_PTR_NEXT(cur);
3228 return (next < end ? next : start);
3232 * Pad an mbuf to ensure a minimum ethernet frame size.
3233 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3235 static __noinline int
3236 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3239 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3240 * and ARP message is the smallest common payload I can think of
3242 static char pad[18]; /* just zeros */
3244 struct mbuf *new_head;
3246 if (!M_WRITABLE(*m_head)) {
3247 new_head = m_dup(*m_head, M_NOWAIT);
3248 if (new_head == NULL) {
3250 device_printf(dev, "cannot pad short frame, m_dup() failed");
3251 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3252 DBG_COUNTER_INC(tx_frees);
3259 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3260 n > 0; n -= sizeof(pad))
3261 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3266 device_printf(dev, "cannot pad short frame\n");
3267 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3268 DBG_COUNTER_INC(tx_frees);
3276 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3279 if_shared_ctx_t sctx;
3280 if_softc_ctx_t scctx;
3281 bus_dma_segment_t *segs;
3282 struct mbuf *m_head;
3285 struct if_pkt_info pi;
3287 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3288 bus_dma_tag_t desc_tag;
3291 sctx = ctx->ifc_sctx;
3292 scctx = &ctx->ifc_softc_ctx;
3293 segs = txq->ift_segs;
3294 ntxd = txq->ift_size;
3299 * If we're doing TSO the next descriptor to clean may be quite far ahead
3301 cidx = txq->ift_cidx;
3302 pidx = txq->ift_pidx;
3303 if (ctx->ifc_flags & IFC_PREFETCH) {
3304 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3305 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3306 next_txd = calc_next_txd(txq, cidx, 0);
3310 /* prefetch the next cache line of mbuf pointers and flags */
3311 prefetch(&txq->ift_sds.ifsd_m[next]);
3312 if (txq->ift_sds.ifsd_map != NULL) {
3313 prefetch(&txq->ift_sds.ifsd_map[next]);
3314 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3315 prefetch(&txq->ift_sds.ifsd_flags[next]);
3317 } else if (txq->ift_sds.ifsd_map != NULL)
3318 map = txq->ift_sds.ifsd_map[pidx];
3320 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3321 desc_tag = txq->ift_tso_desc_tag;
3322 max_segs = scctx->isc_tx_tso_segments_max;
3323 MPASS(desc_tag != NULL);
3324 MPASS(max_segs > 0);
3326 desc_tag = txq->ift_desc_tag;
3327 max_segs = scctx->isc_tx_nsegments;
3329 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3330 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3331 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3333 DBG_COUNTER_INC(encap_txd_encap_fail);
3340 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3342 pi.ipi_qsidx = txq->ift_id;
3343 pi.ipi_len = m_head->m_pkthdr.len;
3344 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3345 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3347 /* deliberate bitwise OR to make one condition */
3348 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3349 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3350 DBG_COUNTER_INC(encap_txd_encap_fail);
3357 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3359 if (__predict_false(err)) {
3362 /* try collapse once and defrag once */
3364 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3365 /* try defrag if collapsing fails */
3370 txq->ift_mbuf_defrag++;
3371 m_head = m_defrag(*m_headp, M_NOWAIT);
3374 if (__predict_false(m_head == NULL))
3380 txq->ift_no_tx_dma_setup++;
3383 txq->ift_no_tx_dma_setup++;
3385 DBG_COUNTER_INC(tx_frees);
3389 txq->ift_map_failed++;
3390 DBG_COUNTER_INC(encap_load_mbuf_fail);
3391 DBG_COUNTER_INC(encap_txd_encap_fail);
3396 * XXX assumes a 1 to 1 relationship between segments and
3397 * descriptors - this does not hold true on all drivers, e.g.
3400 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3401 txq->ift_no_desc_avail++;
3403 bus_dmamap_unload(desc_tag, map);
3404 DBG_COUNTER_INC(encap_txq_avail_fail);
3405 DBG_COUNTER_INC(encap_txd_encap_fail);
3406 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3407 GROUPTASK_ENQUEUE(&txq->ift_task);
3411 * On Intel cards we can greatly reduce the number of TX interrupts
3412 * we see by only setting report status on every Nth descriptor.
3413 * However, this also means that the driver will need to keep track
3414 * of the descriptors that RS was set on to check them for the DD bit.
3416 txq->ift_rs_pending += nsegs + 1;
3417 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3418 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3419 pi.ipi_flags |= IPI_TX_INTR;
3420 txq->ift_rs_pending = 0;
3424 pi.ipi_nsegs = nsegs;
3426 MPASS(pidx >= 0 && pidx < txq->ift_size);
3431 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3432 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3434 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3435 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3436 DBG_COUNTER_INC(tx_encap);
3437 MPASS(pi.ipi_new_pidx < txq->ift_size);
3439 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3440 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3441 ndesc += txq->ift_size;
3445 * drivers can need as many as
3448 MPASS(ndesc <= pi.ipi_nsegs + 2);
3449 MPASS(pi.ipi_new_pidx != pidx);
3451 txq->ift_in_use += ndesc;
3454 * We update the last software descriptor again here because there may
3455 * be a sentinel and/or there may be more mbufs than segments
3457 txq->ift_pidx = pi.ipi_new_pidx;
3458 txq->ift_npending += pi.ipi_ndescs;
3460 *m_headp = m_head = iflib_remove_mbuf(txq);
3462 txq->ift_txd_encap_efbig++;
3471 * err can't possibly be non-zero here, so we don't neet to test it
3472 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3477 txq->ift_mbuf_defrag_failed++;
3478 txq->ift_map_failed++;
3480 DBG_COUNTER_INC(tx_frees);
3482 DBG_COUNTER_INC(encap_txd_encap_fail);
3487 iflib_tx_desc_free(iflib_txq_t txq, int n)
3490 uint32_t qsize, cidx, mask, gen;
3491 struct mbuf *m, **ifsd_m;
3492 uint8_t *ifsd_flags;
3493 bus_dmamap_t *ifsd_map;
3496 cidx = txq->ift_cidx;
3498 qsize = txq->ift_size;
3500 hasmap = txq->ift_sds.ifsd_map != NULL;
3501 ifsd_flags = txq->ift_sds.ifsd_flags;
3502 ifsd_m = txq->ift_sds.ifsd_m;
3503 ifsd_map = txq->ift_sds.ifsd_map;
3504 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3508 prefetch(ifsd_m[(cidx + 3) & mask]);
3509 prefetch(ifsd_m[(cidx + 4) & mask]);
3511 if (ifsd_m[cidx] != NULL) {
3512 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3513 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3514 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3516 * does it matter if it's not the TSO tag? If so we'll
3517 * have to add the type to flags
3519 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3520 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3522 if ((m = ifsd_m[cidx]) != NULL) {
3523 /* XXX we don't support any drivers that batch packets yet */
3524 MPASS(m->m_nextpkt == NULL);
3525 /* if the number of clusters exceeds the number of segments
3526 * there won't be space on the ring to save a pointer to each
3527 * cluster so we simply free the list here
3529 if (m->m_flags & M_TOOBIG) {
3534 ifsd_m[cidx] = NULL;
3536 txq->ift_dequeued++;
3538 DBG_COUNTER_INC(tx_frees);
3541 if (__predict_false(++cidx == qsize)) {
3546 txq->ift_cidx = cidx;
3551 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3554 if_ctx_t ctx = txq->ift_ctx;
3556 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3557 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3560 * Need a rate-limiting check so that this isn't called every time
3562 iflib_tx_credits_update(ctx, txq);
3563 reclaim = DESC_RECLAIMABLE(txq);
3565 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3567 if (iflib_verbose_debug) {
3568 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3569 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3576 iflib_tx_desc_free(txq, reclaim);
3577 txq->ift_cleaned += reclaim;
3578 txq->ift_in_use -= reclaim;
3583 static struct mbuf **
3584 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3587 struct mbuf **items;
3590 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3591 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3593 prefetch(items[(cidx + offset) & (size-1)]);
3594 if (remaining > 1) {
3595 prefetch2cachelines(&items[next]);
3596 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3597 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3598 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3600 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3604 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3607 ifmp_ring_check_drainage(txq->ift_br, budget);
3611 iflib_txq_can_drain(struct ifmp_ring *r)
3613 iflib_txq_t txq = r->cookie;
3614 if_ctx_t ctx = txq->ift_ctx;
3616 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3617 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3621 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3623 iflib_txq_t txq = r->cookie;
3624 if_ctx_t ctx = txq->ift_ctx;
3625 struct ifnet *ifp = ctx->ifc_ifp;
3626 struct mbuf **mp, *m;
3627 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3628 int reclaimed, err, in_use_prev, desc_used;
3629 bool do_prefetch, ring, rang;
3631 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3632 !LINK_ACTIVE(ctx))) {
3633 DBG_COUNTER_INC(txq_drain_notready);
3636 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3637 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3638 avail = IDXDIFF(pidx, cidx, r->size);
3639 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3640 DBG_COUNTER_INC(txq_drain_flushing);
3641 for (i = 0; i < avail; i++) {
3642 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3643 m_free(r->items[(cidx + i) & (r->size-1)]);
3644 r->items[(cidx + i) & (r->size-1)] = NULL;
3649 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3650 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3652 callout_stop(&txq->ift_timer);
3653 CALLOUT_UNLOCK(txq);
3654 DBG_COUNTER_INC(txq_drain_oactive);
3658 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3659 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3660 count = MIN(avail, TX_BATCH_SIZE);
3662 if (iflib_verbose_debug)
3663 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3664 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3666 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3667 avail = TXQ_AVAIL(txq);
3669 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3670 int rem = do_prefetch ? count - i : 0;
3672 mp = _ring_peek_one(r, cidx, i, rem);
3673 MPASS(mp != NULL && *mp != NULL);
3674 if (__predict_false(*mp == (struct mbuf *)txq)) {
3679 in_use_prev = txq->ift_in_use;
3680 err = iflib_encap(txq, mp);
3681 if (__predict_false(err)) {
3682 /* no room - bail out */
3686 /* we can't send this packet - skip it */
3692 DBG_COUNTER_INC(tx_sent);
3693 bytes_sent += m->m_pkthdr.len;
3694 mcast_sent += !!(m->m_flags & M_MCAST);
3695 avail = TXQ_AVAIL(txq);
3697 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3698 desc_used += (txq->ift_in_use - in_use_prev);
3699 ETHER_BPF_MTAP(ifp, m);
3700 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3702 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3705 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3706 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3707 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3708 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3709 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3711 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3713 if (iflib_verbose_debug)
3714 printf("consumed=%d\n", consumed);
3720 iflib_txq_drain_always(struct ifmp_ring *r)
3726 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3734 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3736 callout_stop(&txq->ift_timer);
3737 CALLOUT_UNLOCK(txq);
3739 avail = IDXDIFF(pidx, cidx, r->size);
3740 for (i = 0; i < avail; i++) {
3741 mp = _ring_peek_one(r, cidx, i, avail - i);
3742 if (__predict_false(*mp == (struct mbuf *)txq))
3745 DBG_COUNTER_INC(tx_frees);
3747 MPASS(ifmp_ring_is_stalled(r) == 0);
3752 iflib_ifmp_purge(iflib_txq_t txq)
3754 struct ifmp_ring *r;
3757 r->drain = iflib_txq_drain_free;
3758 r->can_drain = iflib_txq_drain_always;
3760 ifmp_ring_check_drainage(r, r->size);
3762 r->drain = iflib_txq_drain;
3763 r->can_drain = iflib_txq_can_drain;
3767 _task_fn_tx(void *context)
3769 iflib_txq_t txq = context;
3770 if_ctx_t ctx = txq->ift_ctx;
3771 struct ifnet *ifp = ctx->ifc_ifp;
3772 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3774 #ifdef IFLIB_DIAGNOSTICS
3775 txq->ift_cpu_exec_count[curcpu]++;
3777 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3779 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3780 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3781 netmap_tx_irq(ifp, txq->ift_id);
3782 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3786 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3787 iflib_altq_if_start(ifp);
3789 if (txq->ift_db_pending)
3790 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3792 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3794 * When abdicating, we always need to check drainage, not just when we don't enqueue
3797 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3798 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3799 if (ctx->ifc_flags & IFC_LEGACY)
3800 IFDI_INTR_ENABLE(ctx);
3805 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3806 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3811 _task_fn_rx(void *context)
3813 iflib_rxq_t rxq = context;
3814 if_ctx_t ctx = rxq->ifr_ctx;
3818 #ifdef IFLIB_DIAGNOSTICS
3819 rxq->ifr_cpu_exec_count[curcpu]++;
3821 DBG_COUNTER_INC(task_fn_rxs);
3822 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3826 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3828 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3833 budget = ctx->ifc_sysctl_rx_budget;
3835 budget = 16; /* XXX */
3836 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3837 if (ctx->ifc_flags & IFC_LEGACY)
3838 IFDI_INTR_ENABLE(ctx);
3843 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3844 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3845 DBG_COUNTER_INC(rx_intr_enables);
3848 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3851 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3855 _task_fn_admin(void *context)
3857 if_ctx_t ctx = context;
3858 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3861 bool oactive, running, do_reset, do_watchdog, in_detach;
3862 uint32_t reset_on = hz / 2;
3865 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3866 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3867 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3868 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3869 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3870 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3873 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3879 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3881 callout_stop(&txq->ift_timer);
3882 CALLOUT_UNLOCK(txq);
3885 ctx->ifc_watchdog_events++;
3886 IFDI_WATCHDOG_RESET(ctx);
3888 IFDI_UPDATE_ADMIN_STATUS(ctx);
3889 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3892 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3893 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3895 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3897 IFDI_LINK_INTR_ENABLE(ctx);
3899 iflib_if_init_locked(ctx);
3902 if (LINK_ACTIVE(ctx) == 0)
3904 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3905 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3910 _task_fn_iov(void *context)
3912 if_ctx_t ctx = context;
3914 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3915 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3919 IFDI_VFLR_HANDLE(ctx);
3924 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3927 if_int_delay_info_t info;
3930 info = (if_int_delay_info_t)arg1;
3931 ctx = info->iidi_ctx;
3932 info->iidi_req = req;
3933 info->iidi_oidp = oidp;
3935 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3940 /*********************************************************************
3944 **********************************************************************/
3947 iflib_if_init_locked(if_ctx_t ctx)
3950 iflib_init_locked(ctx);
3955 iflib_if_init(void *arg)
3960 iflib_if_init_locked(ctx);
3965 iflib_if_transmit(if_t ifp, struct mbuf *m)
3967 if_ctx_t ctx = if_getsoftc(ifp);
3971 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3973 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3974 DBG_COUNTER_INC(tx_frees);
3979 MPASS(m->m_nextpkt == NULL);
3980 /* ALTQ-enabled interfaces always use queue 0. */
3982 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3983 qidx = QIDX(ctx, m);
3985 * XXX calculate buf_ring based on flowid (divvy up bits?)
3987 txq = &ctx->ifc_txqs[qidx];
3989 #ifdef DRIVER_BACKPRESSURE
3990 if (txq->ift_closed) {
3992 next = m->m_nextpkt;
3993 m->m_nextpkt = NULL;
3995 DBG_COUNTER_INC(tx_frees);
4007 next = next->m_nextpkt;
4008 } while (next != NULL);
4010 if (count > nitems(marr))
4011 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4012 /* XXX check nextpkt */
4014 /* XXX simplify for now */
4015 DBG_COUNTER_INC(tx_frees);
4018 for (next = m, i = 0; next != NULL; i++) {
4020 next = next->m_nextpkt;
4021 mp[i]->m_nextpkt = NULL;
4024 DBG_COUNTER_INC(tx_seen);
4025 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4028 GROUPTASK_ENQUEUE(&txq->ift_task);
4031 GROUPTASK_ENQUEUE(&txq->ift_task);
4032 /* support forthcoming later */
4033 #ifdef DRIVER_BACKPRESSURE
4034 txq->ift_closed = TRUE;
4036 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4038 DBG_COUNTER_INC(tx_frees);
4046 * The overall approach to integrating iflib with ALTQ is to continue to use
4047 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4048 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4049 * is redundant/unnecessary, but doing so minimizes the amount of
4050 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4051 * redundantly queueing to an intermediate mp_ring is swamped by the
4052 * performance limitations inherent in using ALTQ.
4054 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4055 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4056 * given interface. If ALTQ is enabled for an interface, then all
4057 * transmitted packets for that interface will be submitted to the ALTQ
4058 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4059 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4060 * update stats that the iflib machinery handles, and which is sensitve to
4061 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4062 * will be installed as the start routine for use by ALTQ facilities that
4063 * need to trigger queue drains on a scheduled basis.
4067 iflib_altq_if_start(if_t ifp)
4069 struct ifaltq *ifq = &ifp->if_snd;
4073 IFQ_DEQUEUE_NOLOCK(ifq, m);
4075 iflib_if_transmit(ifp, m);
4076 IFQ_DEQUEUE_NOLOCK(ifq, m);
4082 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4086 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4087 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4089 iflib_altq_if_start(ifp);
4091 err = iflib_if_transmit(ifp, m);
4098 iflib_if_qflush(if_t ifp)
4100 if_ctx_t ctx = if_getsoftc(ifp);
4101 iflib_txq_t txq = ctx->ifc_txqs;
4105 ctx->ifc_flags |= IFC_QFLUSH;
4107 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4108 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4109 iflib_txq_check_drain(txq, 0);
4111 ctx->ifc_flags &= ~IFC_QFLUSH;
4115 * When ALTQ is enabled, this will also take care of purging the
4122 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4123 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4124 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4125 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4128 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4130 if_ctx_t ctx = if_getsoftc(ifp);
4131 struct ifreq *ifr = (struct ifreq *)data;
4132 #if defined(INET) || defined(INET6)
4133 struct ifaddr *ifa = (struct ifaddr *)data;
4135 bool avoid_reset = FALSE;
4136 int err = 0, reinit = 0, bits;
4141 if (ifa->ifa_addr->sa_family == AF_INET)
4145 if (ifa->ifa_addr->sa_family == AF_INET6)
4149 ** Calling init results in link renegotiation,
4150 ** so we avoid doing it when possible.
4153 if_setflagbits(ifp, IFF_UP,0);
4154 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4157 if (!(if_getflags(ifp) & IFF_NOARP))
4158 arp_ifinit(ifp, ifa);
4161 err = ether_ioctl(ifp, command, data);
4165 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4169 bits = if_getdrvflags(ifp);
4170 /* stop the driver and free any clusters before proceeding */
4173 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4175 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4176 ctx->ifc_flags |= IFC_MULTISEG;
4178 ctx->ifc_flags &= ~IFC_MULTISEG;
4180 err = if_setmtu(ifp, ifr->ifr_mtu);
4182 iflib_init_locked(ctx);
4184 if_setdrvflags(ifp, bits);
4190 if (if_getflags(ifp) & IFF_UP) {
4191 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4192 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4193 (IFF_PROMISC | IFF_ALLMULTI)) {
4194 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4198 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4201 ctx->ifc_if_flags = if_getflags(ifp);
4206 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4208 IFDI_INTR_DISABLE(ctx);
4209 IFDI_MULTI_SET(ctx);
4210 IFDI_INTR_ENABLE(ctx);
4216 IFDI_MEDIA_SET(ctx);
4221 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4225 struct ifi2creq i2c;
4227 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4230 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4234 if (i2c.len > sizeof(i2c.data)) {
4239 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4240 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4246 int mask, setmask, oldmask;
4248 oldmask = if_getcapenable(ifp);
4249 mask = ifr->ifr_reqcap ^ oldmask;
4250 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4253 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4255 setmask |= (mask & IFCAP_FLAGS);
4256 setmask |= (mask & IFCAP_WOL);
4259 * If we're disabling any RX csum, disable all the ones
4260 * the driver supports. This assumes all supported are
4263 * Otherwise, if they've changed, enable all of them.
4265 if ((setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) <
4266 (oldmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)))
4267 setmask &= ~(IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4268 else if ((setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) !=
4269 (oldmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)))
4270 setmask |= (mask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6));
4273 * want to ensure that traffic has stopped before we change any of the flags
4277 bits = if_getdrvflags(ifp);
4278 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4281 if_togglecapenable(ifp, setmask);
4283 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4284 iflib_init_locked(ctx);
4286 if_setdrvflags(ifp, bits);
4293 case SIOCGPRIVATE_0:
4297 err = IFDI_PRIV_IOCTL(ctx, command, data);
4301 err = ether_ioctl(ifp, command, data);
4310 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4312 if_ctx_t ctx = if_getsoftc(ifp);
4314 return (IFDI_GET_COUNTER(ctx, cnt));
4317 /*********************************************************************
4319 * OTHER FUNCTIONS EXPORTED TO THE STACK
4321 **********************************************************************/
4324 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4326 if_ctx_t ctx = if_getsoftc(ifp);
4328 if ((void *)ctx != arg)
4331 if ((vtag == 0) || (vtag > 4095))
4335 IFDI_VLAN_REGISTER(ctx, vtag);
4336 /* Re-init to load the changes */
4337 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4338 iflib_if_init_locked(ctx);
4343 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4345 if_ctx_t ctx = if_getsoftc(ifp);
4347 if ((void *)ctx != arg)
4350 if ((vtag == 0) || (vtag > 4095))
4354 IFDI_VLAN_UNREGISTER(ctx, vtag);
4355 /* Re-init to load the changes */
4356 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4357 iflib_if_init_locked(ctx);
4362 iflib_led_func(void *arg, int onoff)
4367 IFDI_LED_FUNC(ctx, onoff);
4371 /*********************************************************************
4373 * BUS FUNCTION DEFINITIONS
4375 **********************************************************************/
4378 iflib_device_probe(device_t dev)
4380 pci_vendor_info_t *ent;
4382 uint16_t pci_vendor_id, pci_device_id;
4383 uint16_t pci_subvendor_id, pci_subdevice_id;
4384 uint16_t pci_rev_id;
4385 if_shared_ctx_t sctx;
4387 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4390 pci_vendor_id = pci_get_vendor(dev);
4391 pci_device_id = pci_get_device(dev);
4392 pci_subvendor_id = pci_get_subvendor(dev);
4393 pci_subdevice_id = pci_get_subdevice(dev);
4394 pci_rev_id = pci_get_revid(dev);
4395 if (sctx->isc_parse_devinfo != NULL)
4396 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4398 ent = sctx->isc_vendor_info;
4399 while (ent->pvi_vendor_id != 0) {
4400 if (pci_vendor_id != ent->pvi_vendor_id) {
4404 if ((pci_device_id == ent->pvi_device_id) &&
4405 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4406 (ent->pvi_subvendor_id == 0)) &&
4407 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4408 (ent->pvi_subdevice_id == 0)) &&
4409 ((pci_rev_id == ent->pvi_rev_id) ||
4410 (ent->pvi_rev_id == 0))) {
4412 device_set_desc_copy(dev, ent->pvi_name);
4413 /* this needs to be changed to zero if the bus probing code
4414 * ever stops re-probing on best match because the sctx
4415 * may have its values over written by register calls
4416 * in subsequent probes
4418 return (BUS_PROBE_DEFAULT);
4426 iflib_reset_qvalues(if_ctx_t ctx)
4428 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4429 if_shared_ctx_t sctx = ctx->ifc_sctx;
4430 device_t dev = ctx->ifc_dev;
4433 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4434 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4436 * XXX sanity check that ntxd & nrxd are a power of 2
4438 if (ctx->ifc_sysctl_ntxqs != 0)
4439 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4440 if (ctx->ifc_sysctl_nrxqs != 0)
4441 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4443 for (i = 0; i < sctx->isc_ntxqs; i++) {
4444 if (ctx->ifc_sysctl_ntxds[i] != 0)
4445 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4447 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4450 for (i = 0; i < sctx->isc_nrxqs; i++) {
4451 if (ctx->ifc_sysctl_nrxds[i] != 0)
4452 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4454 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4457 for (i = 0; i < sctx->isc_nrxqs; i++) {
4458 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4459 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4460 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4461 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4463 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4464 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4465 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4466 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4470 for (i = 0; i < sctx->isc_ntxqs; i++) {
4471 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4472 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4473 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4474 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4476 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4477 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4478 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4479 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4485 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4490 if_softc_ctx_t scctx;
4496 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4499 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4500 device_set_softc(dev, ctx);
4501 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4504 ctx->ifc_sctx = sctx;
4506 ctx->ifc_softc = sc;
4508 if ((err = iflib_register(ctx)) != 0) {
4509 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4512 device_printf(dev, "iflib_register failed %d\n", err);
4515 iflib_add_device_sysctl_pre(ctx);
4517 scctx = &ctx->ifc_softc_ctx;
4520 iflib_reset_qvalues(ctx);
4522 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4524 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4527 _iflib_pre_assert(scctx);
4528 ctx->ifc_txrx = *scctx->isc_txrx;
4531 MPASS(scctx->isc_capabilities);
4532 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4533 MPASS(scctx->isc_tx_csum_flags);
4536 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4537 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4539 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4540 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4541 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4542 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4545 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4546 ctx->ifc_flags |= IFC_DMAR;
4547 #elif !(defined(__i386__) || defined(__amd64__))
4548 /* set unconditionally for !x86 */
4549 ctx->ifc_flags |= IFC_DMAR;
4552 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4553 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4555 /* XXX change for per-queue sizes */
4556 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4557 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4558 for (i = 0; i < sctx->isc_nrxqs; i++) {
4559 if (!powerof2(scctx->isc_nrxd[i])) {
4560 /* round down instead? */
4561 device_printf(dev, "# rx descriptors must be a power of 2\n");
4566 for (i = 0; i < sctx->isc_ntxqs; i++) {
4567 if (!powerof2(scctx->isc_ntxd[i])) {
4569 "# tx descriptors must be a power of 2");
4575 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4576 MAX_SINGLE_PACKET_FRACTION)
4577 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4578 MAX_SINGLE_PACKET_FRACTION);
4579 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4580 MAX_SINGLE_PACKET_FRACTION)
4581 scctx->isc_tx_tso_segments_max = max(1,
4582 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4584 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4585 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4587 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4590 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4593 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4594 * into account. In the worst case, each of these calls will
4595 * add another mbuf and, thus, the requirement for another DMA
4596 * segment. So for best performance, it doesn't make sense to
4597 * advertize a maximum of TSO segments that typically will
4598 * require defragmentation in iflib_encap().
4600 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4601 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4603 if (scctx->isc_rss_table_size == 0)
4604 scctx->isc_rss_table_size = 64;
4605 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4607 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4608 /* XXX format name */
4609 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4611 /* Set up cpu set. If it fails, use the set of all CPUs. */
4612 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4613 device_printf(dev, "Unable to fetch CPU list\n");
4614 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4616 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4619 ** Now setup MSI or MSI/X, should
4620 ** return us the number of supported
4621 ** vectors. (Will be 1 for MSI)
4623 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4624 msix = scctx->isc_vectors;
4625 } else if (scctx->isc_msix_bar != 0)
4627 * The simple fact that isc_msix_bar is not 0 does not mean we
4628 * we have a good value there that is known to work.
4630 msix = iflib_msix_init(ctx);
4632 scctx->isc_vectors = 1;
4633 scctx->isc_ntxqsets = 1;
4634 scctx->isc_nrxqsets = 1;
4635 scctx->isc_intr = IFLIB_INTR_LEGACY;
4638 /* Get memory for the station queues */
4639 if ((err = iflib_queues_alloc(ctx))) {
4640 device_printf(dev, "Unable to allocate queue memory\n");
4644 if ((err = iflib_qset_structures_setup(ctx)))
4648 * Group taskqueues aren't properly set up until SMP is started,
4649 * so we disable interrupts until we can handle them post
4652 * XXX: disabling interrupts doesn't actually work, at least for
4653 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4654 * we do null handling and depend on this not causing too large an
4657 IFDI_INTR_DISABLE(ctx);
4658 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4659 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4660 goto fail_intr_free;
4664 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4668 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4669 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4670 goto fail_intr_free;
4674 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4676 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4677 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4682 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4683 * This must appear after the call to ether_ifattach() because
4684 * ether_ifattach() sets if_hdrlen to the default value.
4686 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4687 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4689 if ((err = iflib_netmap_attach(ctx))) {
4690 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4695 NETDUMP_SET(ctx->ifc_ifp, iflib);
4697 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4698 iflib_add_device_sysctl_post(ctx);
4699 ctx->ifc_flags |= IFC_INIT_DONE;
4704 ether_ifdetach(ctx->ifc_ifp);
4707 iflib_tx_structures_free(ctx);
4708 iflib_rx_structures_free(ctx);
4710 iflib_free_intr_mem(ctx);
4718 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4719 struct iflib_cloneattach_ctx *clctx)
4724 if_softc_ctx_t scctx;
4730 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4731 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4732 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4733 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4734 ctx->ifc_flags |= IFC_PSEUDO;
4736 ctx->ifc_sctx = sctx;
4737 ctx->ifc_softc = sc;
4740 if ((err = iflib_register(ctx)) != 0) {
4741 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4746 iflib_add_device_sysctl_pre(ctx);
4748 scctx = &ctx->ifc_softc_ctx;
4752 * XXX sanity check that ntxd & nrxd are a power of 2
4754 iflib_reset_qvalues(ctx);
4756 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4757 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4760 if (sctx->isc_flags & IFLIB_GEN_MAC)
4762 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4763 clctx->cc_params)) != 0) {
4764 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4767 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4768 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4769 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4772 MPASS(scctx->isc_capabilities);
4773 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4774 MPASS(scctx->isc_tx_csum_flags);
4777 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4778 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4780 ifp->if_flags |= IFF_NOGROUP;
4781 if (sctx->isc_flags & IFLIB_PSEUDO) {
4782 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4784 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4785 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4791 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4792 * This must appear after the call to ether_ifattach() because
4793 * ether_ifattach() sets if_hdrlen to the default value.
4795 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4796 if_setifheaderlen(ifp,
4797 sizeof(struct ether_vlan_header));
4799 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4800 iflib_add_device_sysctl_post(ctx);
4801 ctx->ifc_flags |= IFC_INIT_DONE;
4804 _iflib_pre_assert(scctx);
4805 ctx->ifc_txrx = *scctx->isc_txrx;
4807 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4808 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4809 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4810 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4812 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4813 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4815 /* XXX change for per-queue sizes */
4816 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4817 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4818 for (i = 0; i < sctx->isc_nrxqs; i++) {
4819 if (!powerof2(scctx->isc_nrxd[i])) {
4820 /* round down instead? */
4821 device_printf(dev, "# rx descriptors must be a power of 2\n");
4826 for (i = 0; i < sctx->isc_ntxqs; i++) {
4827 if (!powerof2(scctx->isc_ntxd[i])) {
4829 "# tx descriptors must be a power of 2");
4835 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4836 MAX_SINGLE_PACKET_FRACTION)
4837 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4838 MAX_SINGLE_PACKET_FRACTION);
4839 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4840 MAX_SINGLE_PACKET_FRACTION)
4841 scctx->isc_tx_tso_segments_max = max(1,
4842 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4844 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4845 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4847 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4850 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4853 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4854 * into account. In the worst case, each of these calls will
4855 * add another mbuf and, thus, the requirement for another DMA
4856 * segment. So for best performance, it doesn't make sense to
4857 * advertize a maximum of TSO segments that typically will
4858 * require defragmentation in iflib_encap().
4860 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4861 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4863 if (scctx->isc_rss_table_size == 0)
4864 scctx->isc_rss_table_size = 64;
4865 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4867 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4868 /* XXX format name */
4869 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4871 /* XXX --- can support > 1 -- but keep it simple for now */
4872 scctx->isc_intr = IFLIB_INTR_LEGACY;
4874 /* Get memory for the station queues */
4875 if ((err = iflib_queues_alloc(ctx))) {
4876 device_printf(dev, "Unable to allocate queue memory\n");
4880 if ((err = iflib_qset_structures_setup(ctx))) {
4881 device_printf(dev, "qset structure setup failed %d\n", err);
4886 * XXX What if anything do we want to do about interrupts?
4888 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4889 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4890 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4895 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4896 * This must appear after the call to ether_ifattach() because
4897 * ether_ifattach() sets if_hdrlen to the default value.
4899 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4900 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4902 /* XXX handle more than one queue */
4903 for (i = 0; i < scctx->isc_nrxqsets; i++)
4904 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4908 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4909 iflib_add_device_sysctl_post(ctx);
4910 ctx->ifc_flags |= IFC_INIT_DONE;
4913 ether_ifdetach(ctx->ifc_ifp);
4915 iflib_tx_structures_free(ctx);
4916 iflib_rx_structures_free(ctx);
4923 iflib_pseudo_deregister(if_ctx_t ctx)
4925 if_t ifp = ctx->ifc_ifp;
4929 struct taskqgroup *tqg;
4932 /* Unregister VLAN events */
4933 if (ctx->ifc_vlan_attach_event != NULL)
4934 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4935 if (ctx->ifc_vlan_detach_event != NULL)
4936 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4938 ether_ifdetach(ifp);
4939 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4940 CTX_LOCK_DESTROY(ctx);
4941 /* XXX drain any dependent tasks */
4942 tqg = qgroup_if_io_tqg;
4943 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4944 callout_drain(&txq->ift_timer);
4945 if (txq->ift_task.gt_uniq != NULL)
4946 taskqgroup_detach(tqg, &txq->ift_task);
4948 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4949 if (rxq->ifr_task.gt_uniq != NULL)
4950 taskqgroup_detach(tqg, &rxq->ifr_task);
4952 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4953 free(fl->ifl_rx_bitmap, M_IFLIB);
4955 tqg = qgroup_if_config_tqg;
4956 if (ctx->ifc_admin_task.gt_uniq != NULL)
4957 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4958 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4959 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4963 iflib_tx_structures_free(ctx);
4964 iflib_rx_structures_free(ctx);
4965 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4966 free(ctx->ifc_softc, M_IFLIB);
4972 iflib_device_attach(device_t dev)
4975 if_shared_ctx_t sctx;
4977 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4980 pci_enable_busmaster(dev);
4982 return (iflib_device_register(dev, NULL, sctx, &ctx));
4986 iflib_device_deregister(if_ctx_t ctx)
4988 if_t ifp = ctx->ifc_ifp;
4991 device_t dev = ctx->ifc_dev;
4993 struct taskqgroup *tqg;
4996 /* Make sure VLANS are not using driver */
4997 if (if_vlantrunkinuse(ifp)) {
4998 device_printf(dev, "Vlan in use, detach first\n");
5002 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5003 device_printf(dev, "SR-IOV in use; detach first.\n");
5009 ctx->ifc_flags |= IFC_IN_DETACH;
5016 /* Unregister VLAN events */
5017 if (ctx->ifc_vlan_attach_event != NULL)
5018 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5019 if (ctx->ifc_vlan_detach_event != NULL)
5020 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5022 iflib_netmap_detach(ifp);
5023 ether_ifdetach(ifp);
5024 if (ctx->ifc_led_dev != NULL)
5025 led_destroy(ctx->ifc_led_dev);
5026 /* XXX drain any dependent tasks */
5027 tqg = qgroup_if_io_tqg;
5028 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5029 callout_drain(&txq->ift_timer);
5030 if (txq->ift_task.gt_uniq != NULL)
5031 taskqgroup_detach(tqg, &txq->ift_task);
5033 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5034 if (rxq->ifr_task.gt_uniq != NULL)
5035 taskqgroup_detach(tqg, &rxq->ifr_task);
5037 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5038 free(fl->ifl_rx_bitmap, M_IFLIB);
5041 tqg = qgroup_if_config_tqg;
5042 if (ctx->ifc_admin_task.gt_uniq != NULL)
5043 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5044 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5045 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5050 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5051 CTX_LOCK_DESTROY(ctx);
5052 device_set_softc(ctx->ifc_dev, NULL);
5053 iflib_free_intr_mem(ctx);
5055 bus_generic_detach(dev);
5058 iflib_tx_structures_free(ctx);
5059 iflib_rx_structures_free(ctx);
5060 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5061 free(ctx->ifc_softc, M_IFLIB);
5062 STATE_LOCK_DESTROY(ctx);
5068 iflib_free_intr_mem(if_ctx_t ctx)
5071 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5072 pci_release_msi(ctx->ifc_dev);
5074 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5075 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5077 if (ctx->ifc_msix_mem != NULL) {
5078 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5079 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
5080 ctx->ifc_msix_mem = NULL;
5085 iflib_device_detach(device_t dev)
5087 if_ctx_t ctx = device_get_softc(dev);
5089 return (iflib_device_deregister(ctx));
5093 iflib_device_suspend(device_t dev)
5095 if_ctx_t ctx = device_get_softc(dev);
5101 return bus_generic_suspend(dev);
5104 iflib_device_shutdown(device_t dev)
5106 if_ctx_t ctx = device_get_softc(dev);
5112 return bus_generic_suspend(dev);
5117 iflib_device_resume(device_t dev)
5119 if_ctx_t ctx = device_get_softc(dev);
5120 iflib_txq_t txq = ctx->ifc_txqs;
5124 iflib_init_locked(ctx);
5126 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5127 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5129 return (bus_generic_resume(dev));
5133 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5136 if_ctx_t ctx = device_get_softc(dev);
5139 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5146 iflib_device_iov_uninit(device_t dev)
5148 if_ctx_t ctx = device_get_softc(dev);
5151 IFDI_IOV_UNINIT(ctx);
5156 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5159 if_ctx_t ctx = device_get_softc(dev);
5162 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5168 /*********************************************************************
5170 * MODULE FUNCTION DEFINITIONS
5172 **********************************************************************/
5175 * - Start a fast taskqueue thread for each core
5176 * - Start a taskqueue for control operations
5179 iflib_module_init(void)
5185 iflib_module_event_handler(module_t mod, int what, void *arg)
5191 if ((err = iflib_module_init()) != 0)
5197 return (EOPNOTSUPP);
5203 /*********************************************************************
5205 * PUBLIC FUNCTION DEFINITIONS
5206 * ordered as in iflib.h
5208 **********************************************************************/
5212 _iflib_assert(if_shared_ctx_t sctx)
5214 MPASS(sctx->isc_tx_maxsize);
5215 MPASS(sctx->isc_tx_maxsegsize);
5217 MPASS(sctx->isc_rx_maxsize);
5218 MPASS(sctx->isc_rx_nsegments);
5219 MPASS(sctx->isc_rx_maxsegsize);
5221 MPASS(sctx->isc_nrxd_min[0]);
5222 MPASS(sctx->isc_nrxd_max[0]);
5223 MPASS(sctx->isc_nrxd_default[0]);
5224 MPASS(sctx->isc_ntxd_min[0]);
5225 MPASS(sctx->isc_ntxd_max[0]);
5226 MPASS(sctx->isc_ntxd_default[0]);
5230 _iflib_pre_assert(if_softc_ctx_t scctx)
5233 MPASS(scctx->isc_txrx->ift_txd_encap);
5234 MPASS(scctx->isc_txrx->ift_txd_flush);
5235 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5236 MPASS(scctx->isc_txrx->ift_rxd_available);
5237 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5238 MPASS(scctx->isc_txrx->ift_rxd_refill);
5239 MPASS(scctx->isc_txrx->ift_rxd_flush);
5243 iflib_register(if_ctx_t ctx)
5245 if_shared_ctx_t sctx = ctx->ifc_sctx;
5246 driver_t *driver = sctx->isc_driver;
5247 device_t dev = ctx->ifc_dev;
5250 _iflib_assert(sctx);
5253 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5254 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5256 device_printf(dev, "can not allocate ifnet structure\n");
5261 * Initialize our context's device specific methods
5263 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5264 kobj_class_compile((kobj_class_t) driver);
5267 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5268 if_setsoftc(ifp, ctx);
5269 if_setdev(ifp, dev);
5270 if_setinitfn(ifp, iflib_if_init);
5271 if_setioctlfn(ifp, iflib_if_ioctl);
5273 if_setstartfn(ifp, iflib_altq_if_start);
5274 if_settransmitfn(ifp, iflib_altq_if_transmit);
5275 if_setsendqready(ifp);
5277 if_settransmitfn(ifp, iflib_if_transmit);
5279 if_setqflushfn(ifp, iflib_if_qflush);
5280 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5282 ctx->ifc_vlan_attach_event =
5283 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5284 EVENTHANDLER_PRI_FIRST);
5285 ctx->ifc_vlan_detach_event =
5286 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5287 EVENTHANDLER_PRI_FIRST);
5289 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5290 iflib_media_change, iflib_media_status);
5297 iflib_queues_alloc(if_ctx_t ctx)
5299 if_shared_ctx_t sctx = ctx->ifc_sctx;
5300 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5301 device_t dev = ctx->ifc_dev;
5302 int nrxqsets = scctx->isc_nrxqsets;
5303 int ntxqsets = scctx->isc_ntxqsets;
5306 iflib_fl_t fl = NULL;
5307 int i, j, cpu, err, txconf, rxconf;
5308 iflib_dma_info_t ifdip;
5309 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5310 uint32_t *txqsizes = scctx->isc_txqsizes;
5311 uint8_t nrxqs = sctx->isc_nrxqs;
5312 uint8_t ntxqs = sctx->isc_ntxqs;
5313 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5317 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5318 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5320 /* Allocate the TX ring struct memory */
5321 if (!(ctx->ifc_txqs =
5322 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5323 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5324 device_printf(dev, "Unable to allocate TX ring memory\n");
5329 /* Now allocate the RX */
5330 if (!(ctx->ifc_rxqs =
5331 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5332 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5333 device_printf(dev, "Unable to allocate RX ring memory\n");
5338 txq = ctx->ifc_txqs;
5339 rxq = ctx->ifc_rxqs;
5342 * XXX handle allocation failure
5344 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5345 /* Set up some basics */
5347 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5348 device_printf(dev, "failed to allocate iflib_dma_info\n");
5352 txq->ift_ifdi = ifdip;
5353 for (j = 0; j < ntxqs; j++, ifdip++) {
5354 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5355 device_printf(dev, "Unable to allocate Descriptor memory\n");
5359 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5360 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5364 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5365 txq->ift_br_offset = 1;
5367 txq->ift_br_offset = 0;
5370 txq->ift_timer.c_cpu = cpu;
5372 if (iflib_txsd_alloc(txq)) {
5373 device_printf(dev, "Critical Failure setting up TX buffers\n");
5378 /* Initialize the TX lock */
5379 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5380 device_get_nameunit(dev), txq->ift_id);
5381 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5382 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5384 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5385 device_get_nameunit(dev), txq->ift_id);
5387 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5388 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5390 /* XXX free any allocated rings */
5391 device_printf(dev, "Unable to allocate buf_ring\n");
5396 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5397 /* Set up some basics */
5399 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5400 device_printf(dev, "failed to allocate iflib_dma_info\n");
5405 rxq->ifr_ifdi = ifdip;
5406 /* XXX this needs to be changed if #rx queues != #tx queues */
5407 rxq->ifr_ntxqirq = 1;
5408 rxq->ifr_txqid[0] = i;
5409 for (j = 0; j < nrxqs; j++, ifdip++) {
5410 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5411 device_printf(dev, "Unable to allocate Descriptor memory\n");
5415 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5419 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5420 rxq->ifr_fl_offset = 1;
5422 rxq->ifr_fl_offset = 0;
5424 rxq->ifr_nfl = nfree_lists;
5426 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5427 device_printf(dev, "Unable to allocate free list memory\n");
5432 for (j = 0; j < nfree_lists; j++) {
5433 fl[j].ifl_rxq = rxq;
5435 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5436 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5438 /* Allocate receive buffers for the ring */
5439 if (iflib_rxsd_alloc(rxq)) {
5441 "Critical Failure setting up receive buffers\n");
5446 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5447 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
5451 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5452 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5453 for (i = 0; i < ntxqsets; i++) {
5454 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5456 for (j = 0; j < ntxqs; j++, di++) {
5457 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5458 paddrs[i*ntxqs + j] = di->idi_paddr;
5461 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5462 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5463 iflib_tx_structures_free(ctx);
5464 free(vaddrs, M_IFLIB);
5465 free(paddrs, M_IFLIB);
5468 free(vaddrs, M_IFLIB);
5469 free(paddrs, M_IFLIB);
5472 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5473 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5474 for (i = 0; i < nrxqsets; i++) {
5475 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5477 for (j = 0; j < nrxqs; j++, di++) {
5478 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5479 paddrs[i*nrxqs + j] = di->idi_paddr;
5482 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5483 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5484 iflib_tx_structures_free(ctx);
5485 free(vaddrs, M_IFLIB);
5486 free(paddrs, M_IFLIB);
5489 free(vaddrs, M_IFLIB);
5490 free(paddrs, M_IFLIB);
5494 /* XXX handle allocation failure changes */
5498 if (ctx->ifc_rxqs != NULL)
5499 free(ctx->ifc_rxqs, M_IFLIB);
5500 ctx->ifc_rxqs = NULL;
5501 if (ctx->ifc_txqs != NULL)
5502 free(ctx->ifc_txqs, M_IFLIB);
5503 ctx->ifc_txqs = NULL;
5509 iflib_tx_structures_setup(if_ctx_t ctx)
5511 iflib_txq_t txq = ctx->ifc_txqs;
5514 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5515 iflib_txq_setup(txq);
5521 iflib_tx_structures_free(if_ctx_t ctx)
5523 iflib_txq_t txq = ctx->ifc_txqs;
5526 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5527 iflib_txq_destroy(txq);
5528 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
5529 iflib_dma_free(&txq->ift_ifdi[j]);
5531 free(ctx->ifc_txqs, M_IFLIB);
5532 ctx->ifc_txqs = NULL;
5533 IFDI_QUEUES_FREE(ctx);
5536 /*********************************************************************
5538 * Initialize all receive rings.
5540 **********************************************************************/
5542 iflib_rx_structures_setup(if_ctx_t ctx)
5544 iflib_rxq_t rxq = ctx->ifc_rxqs;
5546 #if defined(INET6) || defined(INET)
5550 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5551 #if defined(INET6) || defined(INET)
5552 tcp_lro_free(&rxq->ifr_lc);
5553 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5554 TCP_LRO_ENTRIES, min(1024,
5555 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5556 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5559 rxq->ifr_lro_enabled = TRUE;
5561 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5564 #if defined(INET6) || defined(INET)
5567 * Free RX software descriptors allocated so far, we will only handle
5568 * the rings that completed, the failing case will have
5569 * cleaned up for itself. 'q' failed, so its the terminus.
5571 rxq = ctx->ifc_rxqs;
5572 for (i = 0; i < q; ++i, rxq++) {
5573 iflib_rx_sds_free(rxq);
5574 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5580 /*********************************************************************
5582 * Free all receive rings.
5584 **********************************************************************/
5586 iflib_rx_structures_free(if_ctx_t ctx)
5588 iflib_rxq_t rxq = ctx->ifc_rxqs;
5590 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5591 iflib_rx_sds_free(rxq);
5593 free(ctx->ifc_rxqs, M_IFLIB);
5594 ctx->ifc_rxqs = NULL;
5598 iflib_qset_structures_setup(if_ctx_t ctx)
5603 * It is expected that the caller takes care of freeing queues if this
5606 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5607 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5611 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5612 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5618 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5619 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5622 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5627 find_nth(if_ctx_t ctx, int qid)
5630 int i, cpuid, eqid, count;
5632 CPU_COPY(&ctx->ifc_cpus, &cpus);
5633 count = CPU_COUNT(&cpus);
5635 /* clear up to the qid'th bit */
5636 for (i = 0; i < eqid; i++) {
5637 cpuid = CPU_FFS(&cpus);
5639 CPU_CLR(cpuid-1, &cpus);
5641 cpuid = CPU_FFS(&cpus);
5647 extern struct cpu_group *cpu_top; /* CPU topology */
5650 find_child_with_core(int cpu, struct cpu_group *grp)
5654 if (grp->cg_children == 0)
5657 MPASS(grp->cg_child);
5658 for (i = 0; i < grp->cg_children; i++) {
5659 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5667 * Find the nth "close" core to the specified core
5668 * "close" is defined as the deepest level that shares
5669 * at least an L2 cache. With threads, this will be
5670 * threads on the same core. If the sahred cache is L3
5671 * or higher, simply returns the same core.
5674 find_close_core(int cpu, int core_offset)
5676 struct cpu_group *grp;
5685 while ((i = find_child_with_core(cpu, grp)) != -1) {
5686 /* If the child only has one cpu, don't descend */
5687 if (grp->cg_child[i].cg_count <= 1)
5689 grp = &grp->cg_child[i];
5692 /* If they don't share at least an L2 cache, use the same CPU */
5693 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5697 CPU_COPY(&grp->cg_mask, &cs);
5699 /* Add the selected CPU offset to core offset. */
5700 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5701 if (fcpu - 1 == cpu)
5703 CPU_CLR(fcpu - 1, &cs);
5709 CPU_COPY(&grp->cg_mask, &cs);
5710 for (i = core_offset % grp->cg_count; i > 0; i--) {
5711 MPASS(CPU_FFS(&cs));
5712 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5714 MPASS(CPU_FFS(&cs));
5715 return CPU_FFS(&cs) - 1;
5719 find_close_core(int cpu, int core_offset __unused)
5726 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5730 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5731 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5732 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5734 case IFLIB_INTR_RXTX:
5735 /* RX queues get the specified core */
5736 return qid / CPU_COUNT(&ctx->ifc_cpus);
5742 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5743 #define find_close_core(cpuid, tid) CPU_FIRST()
5744 #define find_nth(ctx, gid) CPU_FIRST()
5747 /* Just to avoid copy/paste */
5749 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5750 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5755 cpuid = find_nth(ctx, qid);
5756 tid = get_core_offset(ctx, type, qid);
5758 cpuid = find_close_core(cpuid, tid);
5759 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5761 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5765 if (cpuid > ctx->ifc_cpuid_highest)
5766 ctx->ifc_cpuid_highest = cpuid;
5772 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5773 iflib_intr_type_t type, driver_filter_t *filter,
5774 void *filter_arg, int qid, const char *name)
5776 struct grouptask *gtask;
5777 struct taskqgroup *tqg;
5778 iflib_filter_info_t info;
5781 driver_filter_t *intr_fast;
5784 info = &ctx->ifc_filter_info;
5788 /* XXX merge tx/rx for netmap? */
5790 q = &ctx->ifc_txqs[qid];
5791 info = &ctx->ifc_txqs[qid].ift_filter_info;
5792 gtask = &ctx->ifc_txqs[qid].ift_task;
5793 tqg = qgroup_if_io_tqg;
5795 intr_fast = iflib_fast_intr;
5796 GROUPTASK_INIT(gtask, 0, fn, q);
5797 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5800 q = &ctx->ifc_rxqs[qid];
5801 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5802 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5803 tqg = qgroup_if_io_tqg;
5805 intr_fast = iflib_fast_intr;
5806 GROUPTASK_INIT(gtask, 0, fn, q);
5808 case IFLIB_INTR_RXTX:
5809 q = &ctx->ifc_rxqs[qid];
5810 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5811 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5812 tqg = qgroup_if_io_tqg;
5814 intr_fast = iflib_fast_intr_rxtx;
5815 GROUPTASK_INIT(gtask, 0, fn, q);
5817 case IFLIB_INTR_ADMIN:
5820 info = &ctx->ifc_filter_info;
5821 gtask = &ctx->ifc_admin_task;
5822 tqg = qgroup_if_config_tqg;
5823 fn = _task_fn_admin;
5824 intr_fast = iflib_fast_intr_ctx;
5827 panic("unknown net intr type");
5830 info->ifi_filter = filter;
5831 info->ifi_filter_arg = filter_arg;
5832 info->ifi_task = gtask;
5835 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5837 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5840 if (type == IFLIB_INTR_ADMIN)
5844 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5848 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5855 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5857 struct grouptask *gtask;
5858 struct taskqgroup *tqg;
5866 q = &ctx->ifc_txqs[qid];
5867 gtask = &ctx->ifc_txqs[qid].ift_task;
5868 tqg = qgroup_if_io_tqg;
5871 irq_num = rman_get_start(irq->ii_res);
5874 q = &ctx->ifc_rxqs[qid];
5875 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5876 tqg = qgroup_if_io_tqg;
5879 irq_num = rman_get_start(irq->ii_res);
5881 case IFLIB_INTR_IOV:
5883 gtask = &ctx->ifc_vflr_task;
5884 tqg = qgroup_if_config_tqg;
5888 panic("unknown net intr type");
5890 GROUPTASK_INIT(gtask, 0, fn, q);
5891 if (irq_num != -1) {
5892 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5894 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5897 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5902 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5905 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5908 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5912 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5914 iflib_txq_t txq = ctx->ifc_txqs;
5915 iflib_rxq_t rxq = ctx->ifc_rxqs;
5916 if_irq_t irq = &ctx->ifc_legacy_irq;
5917 iflib_filter_info_t info;
5918 struct grouptask *gtask;
5919 struct taskqgroup *tqg;
5925 q = &ctx->ifc_rxqs[0];
5926 info = &rxq[0].ifr_filter_info;
5927 gtask = &rxq[0].ifr_task;
5928 tqg = qgroup_if_io_tqg;
5929 tqrid = irq->ii_rid = *rid;
5932 ctx->ifc_flags |= IFC_LEGACY;
5933 info->ifi_filter = filter;
5934 info->ifi_filter_arg = filter_arg;
5935 info->ifi_task = gtask;
5936 info->ifi_ctx = ctx;
5938 /* We allocate a single interrupt resource */
5939 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5941 GROUPTASK_INIT(gtask, 0, fn, q);
5942 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5944 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5945 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5950 iflib_led_create(if_ctx_t ctx)
5953 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5954 device_get_nameunit(ctx->ifc_dev));
5958 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5961 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5965 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5968 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5972 iflib_admin_intr_deferred(if_ctx_t ctx)
5975 struct grouptask *gtask;
5977 gtask = &ctx->ifc_admin_task;
5978 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5981 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5985 iflib_iov_intr_deferred(if_ctx_t ctx)
5988 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5992 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5995 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5999 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6003 GROUPTASK_INIT(gtask, 0, fn, ctx);
6004 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
6008 iflib_config_gtask_deinit(struct grouptask *gtask)
6011 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6015 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6017 if_t ifp = ctx->ifc_ifp;
6018 iflib_txq_t txq = ctx->ifc_txqs;
6020 if_setbaudrate(ifp, baudrate);
6021 if (baudrate >= IF_Gbps(10)) {
6023 ctx->ifc_flags |= IFC_PREFETCH;
6026 /* If link down, disable watchdog */
6027 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6028 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6029 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6031 ctx->ifc_link_state = link_state;
6032 if_link_state_change(ifp, link_state);
6036 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6040 int credits_pre = txq->ift_cidx_processed;
6043 if (ctx->isc_txd_credits_update == NULL)
6046 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6049 txq->ift_processed += credits;
6050 txq->ift_cidx_processed += credits;
6052 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6053 if (txq->ift_cidx_processed >= txq->ift_size)
6054 txq->ift_cidx_processed -= txq->ift_size;
6059 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6062 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6067 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6068 const char *description, if_int_delay_info_t info,
6069 int offset, int value)
6071 info->iidi_ctx = ctx;
6072 info->iidi_offset = offset;
6073 info->iidi_value = value;
6074 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6075 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6076 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6077 info, 0, iflib_sysctl_int_delay, "I", description);
6081 iflib_ctx_lock_get(if_ctx_t ctx)
6084 return (&ctx->ifc_ctx_sx);
6088 iflib_msix_init(if_ctx_t ctx)
6090 device_t dev = ctx->ifc_dev;
6091 if_shared_ctx_t sctx = ctx->ifc_sctx;
6092 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6093 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
6094 int iflib_num_tx_queues, iflib_num_rx_queues;
6095 int err, admincnt, bar;
6097 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6098 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6100 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6102 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6103 admincnt = sctx->isc_admin_intrcnt;
6104 /* Override by tuneable */
6105 if (scctx->isc_disable_msix)
6109 * bar == -1 => "trust me I know what I'm doing"
6110 * Some drivers are for hardware that is so shoddily
6111 * documented that no one knows which bars are which
6112 * so the developer has to map all bars. This hack
6113 * allows shoddy garbage to use msix in this framework.
6116 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6117 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6118 if (ctx->ifc_msix_mem == NULL) {
6119 /* May not be enabled */
6120 device_printf(dev, "Unable to map MSIX table \n");
6124 /* First try MSI/X */
6125 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
6126 device_printf(dev, "System has MSIX disabled \n");
6127 bus_release_resource(dev, SYS_RES_MEMORY,
6128 bar, ctx->ifc_msix_mem);
6129 ctx->ifc_msix_mem = NULL;
6133 /* use only 1 qset in debug mode */
6134 queuemsgs = min(msgs - admincnt, 1);
6136 queuemsgs = msgs - admincnt;
6139 queues = imin(queuemsgs, rss_getnumbuckets());
6143 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6144 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
6145 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6147 /* If we're doing RSS, clamp at the number of RSS buckets */
6148 if (queues > rss_getnumbuckets())
6149 queues = rss_getnumbuckets();
6151 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6152 rx_queues = iflib_num_rx_queues;
6156 if (rx_queues > scctx->isc_nrxqsets)
6157 rx_queues = scctx->isc_nrxqsets;
6160 * We want this to be all logical CPUs by default
6162 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6163 tx_queues = iflib_num_tx_queues;
6165 tx_queues = mp_ncpus;
6167 if (tx_queues > scctx->isc_ntxqsets)
6168 tx_queues = scctx->isc_ntxqsets;
6170 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6172 if (tx_queues != rx_queues)
6174 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6175 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6177 tx_queues = min(rx_queues, tx_queues);
6178 rx_queues = min(rx_queues, tx_queues);
6181 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
6183 vectors = rx_queues + admincnt;
6184 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6185 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors);
6186 scctx->isc_vectors = vectors;
6187 scctx->isc_nrxqsets = rx_queues;
6188 scctx->isc_ntxqsets = tx_queues;
6189 scctx->isc_intr = IFLIB_INTR_MSIX;
6194 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
6195 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6197 ctx->ifc_msix_mem = NULL;
6200 vectors = pci_msi_count(dev);
6201 scctx->isc_nrxqsets = 1;
6202 scctx->isc_ntxqsets = 1;
6203 scctx->isc_vectors = vectors;
6204 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6205 device_printf(dev,"Using an MSI interrupt\n");
6206 scctx->isc_intr = IFLIB_INTR_MSI;
6208 scctx->isc_vectors = 1;
6209 device_printf(dev,"Using a Legacy interrupt\n");
6210 scctx->isc_intr = IFLIB_INTR_LEGACY;
6216 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6219 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6222 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6224 const char *ring_state = "UNKNOWN";
6227 rc = sysctl_wire_old_buffer(req, 0);
6231 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6236 ring_state = ring_states[state[3]];
6238 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6239 state[0], state[1], state[2], ring_state);
6240 rc = sbuf_finish(sb);
6245 enum iflib_ndesc_handler {
6251 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6253 if_ctx_t ctx = (void *)arg1;
6254 enum iflib_ndesc_handler type = arg2;
6255 char buf[256] = {0};
6260 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6264 case IFLIB_NTXD_HANDLER:
6265 ndesc = ctx->ifc_sysctl_ntxds;
6267 nqs = ctx->ifc_sctx->isc_ntxqs;
6269 case IFLIB_NRXD_HANDLER:
6270 ndesc = ctx->ifc_sysctl_nrxds;
6272 nqs = ctx->ifc_sctx->isc_nrxqs;
6275 panic("unhandled type");
6280 for (i=0; i<8; i++) {
6285 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6288 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6289 if (rc || req->newptr == NULL)
6292 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6293 i++, p = strsep(&next, " ,")) {
6294 ndesc[i] = strtoul(p, NULL, 10);
6300 #define NAME_BUFLEN 32
6302 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6304 device_t dev = iflib_get_dev(ctx);
6305 struct sysctl_oid_list *child, *oid_list;
6306 struct sysctl_ctx_list *ctx_list;
6307 struct sysctl_oid *node;
6309 ctx_list = device_get_sysctl_ctx(dev);
6310 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6311 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6312 CTLFLAG_RD, NULL, "IFLIB fields");
6313 oid_list = SYSCTL_CHILDREN(node);
6315 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6316 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6319 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6320 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6321 "# of txqs to use, 0 => use default #");
6322 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6323 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6324 "# of rxqs to use, 0 => use default #");
6325 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6326 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6327 "permit #txq != #rxq");
6328 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6329 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6330 "disable MSIX (default 0)");
6331 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6332 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6333 "set the rx budget");
6334 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6335 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6336 "cause tx to abdicate instead of running to completion");
6338 /* XXX change for per-queue sizes */
6339 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6340 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6341 mp_ndesc_handler, "A",
6342 "list of # of tx descriptors to use, 0 = use default #");
6343 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6344 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6345 mp_ndesc_handler, "A",
6346 "list of # of rx descriptors to use, 0 = use default #");
6350 iflib_add_device_sysctl_post(if_ctx_t ctx)
6352 if_shared_ctx_t sctx = ctx->ifc_sctx;
6353 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6354 device_t dev = iflib_get_dev(ctx);
6355 struct sysctl_oid_list *child;
6356 struct sysctl_ctx_list *ctx_list;
6361 char namebuf[NAME_BUFLEN];
6363 struct sysctl_oid *queue_node, *fl_node, *node;
6364 struct sysctl_oid_list *queue_list, *fl_list;
6365 ctx_list = device_get_sysctl_ctx(dev);
6367 node = ctx->ifc_sysctl_node;
6368 child = SYSCTL_CHILDREN(node);
6370 if (scctx->isc_ntxqsets > 100)
6372 else if (scctx->isc_ntxqsets > 10)
6376 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6377 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6378 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6379 CTLFLAG_RD, NULL, "Queue Name");
6380 queue_list = SYSCTL_CHILDREN(queue_node);
6382 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6384 &txq->ift_dequeued, "total mbufs freed");
6385 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6387 &txq->ift_enqueued, "total mbufs enqueued");
6389 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6391 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6392 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6394 &txq->ift_pullups, "# of times m_pullup was called");
6395 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6397 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6398 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6400 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6401 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6403 &txq->ift_map_failed, "# of times dma map failed");
6404 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6406 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6407 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6409 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6410 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6412 &txq->ift_pidx, 1, "Producer Index");
6413 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6415 &txq->ift_cidx, 1, "Consumer Index");
6416 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6418 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6419 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6421 &txq->ift_in_use, 1, "descriptors in use");
6422 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6424 &txq->ift_processed, "descriptors procesed for clean");
6425 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6427 &txq->ift_cleaned, "total cleaned");
6428 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6429 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6430 0, mp_ring_state_handler, "A", "soft ring state");
6431 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6432 CTLFLAG_RD, &txq->ift_br->enqueues,
6433 "# of enqueues to the mp_ring for this queue");
6434 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6435 CTLFLAG_RD, &txq->ift_br->drops,
6436 "# of drops in the mp_ring for this queue");
6437 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6438 CTLFLAG_RD, &txq->ift_br->starts,
6439 "# of normal consumer starts in the mp_ring for this queue");
6440 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6441 CTLFLAG_RD, &txq->ift_br->stalls,
6442 "# of consumer stalls in the mp_ring for this queue");
6443 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6444 CTLFLAG_RD, &txq->ift_br->restarts,
6445 "# of consumer restarts in the mp_ring for this queue");
6446 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6447 CTLFLAG_RD, &txq->ift_br->abdications,
6448 "# of consumer abdications in the mp_ring for this queue");
6451 if (scctx->isc_nrxqsets > 100)
6453 else if (scctx->isc_nrxqsets > 10)
6457 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6458 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6459 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6460 CTLFLAG_RD, NULL, "Queue Name");
6461 queue_list = SYSCTL_CHILDREN(queue_node);
6462 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6463 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6465 &rxq->ifr_cq_pidx, 1, "Producer Index");
6466 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6468 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6471 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6472 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6473 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6474 CTLFLAG_RD, NULL, "freelist Name");
6475 fl_list = SYSCTL_CHILDREN(fl_node);
6476 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6478 &fl->ifl_pidx, 1, "Producer Index");
6479 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6481 &fl->ifl_cidx, 1, "Consumer Index");
6482 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6484 &fl->ifl_credits, 1, "credits available");
6486 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6488 &fl->ifl_m_enqueued, "mbufs allocated");
6489 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6491 &fl->ifl_m_dequeued, "mbufs freed");
6492 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6494 &fl->ifl_cl_enqueued, "clusters allocated");
6495 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6497 &fl->ifl_cl_dequeued, "clusters freed");
6506 iflib_request_reset(if_ctx_t ctx)
6510 ctx->ifc_flags |= IFC_DO_RESET;
6514 #ifndef __NO_STRICT_ALIGNMENT
6515 static struct mbuf *
6516 iflib_fixup_rx(struct mbuf *m)
6520 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6521 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6522 m->m_data += ETHER_HDR_LEN;
6525 MGETHDR(n, M_NOWAIT, MT_DATA);
6530 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6531 m->m_data += ETHER_HDR_LEN;
6532 m->m_len -= ETHER_HDR_LEN;
6533 n->m_len = ETHER_HDR_LEN;
6534 M_MOVE_PKTHDR(n, m);
6543 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6547 ctx = if_getsoftc(ifp);
6549 *nrxr = NRXQSETS(ctx);
6550 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6551 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6556 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6559 if_softc_ctx_t scctx;
6564 ctx = if_getsoftc(ifp);
6565 scctx = &ctx->ifc_softc_ctx;
6569 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6570 rxq = &ctx->ifc_rxqs[i];
6571 for (j = 0; j < rxq->ifr_nfl; j++) {
6573 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6576 iflib_no_tx_batch = 1;
6584 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6590 ctx = if_getsoftc(ifp);
6591 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6595 txq = &ctx->ifc_txqs[0];
6596 error = iflib_encap(txq, &m);
6598 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6603 iflib_netdump_poll(struct ifnet *ifp, int count)
6606 if_softc_ctx_t scctx;
6610 ctx = if_getsoftc(ifp);
6611 scctx = &ctx->ifc_softc_ctx;
6613 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6617 txq = &ctx->ifc_txqs[0];
6618 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6620 for (i = 0; i < scctx->isc_nrxqsets; i++)
6621 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6624 #endif /* NETDUMP */