2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet/netdump/netdump.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
133 typedef struct iflib_txq *iflib_txq_t;
135 typedef struct iflib_rxq *iflib_rxq_t;
137 typedef struct iflib_fl *iflib_fl_t;
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
144 typedef struct iflib_filter_info {
145 driver_filter_t *ifi_filter;
146 void *ifi_filter_arg;
147 struct grouptask *ifi_task;
149 } *iflib_filter_info_t;
154 * Pointer to hardware driver's softc
161 if_shared_ctx_t ifc_sctx;
162 struct if_softc_ctx ifc_softc_ctx;
164 struct sx ifc_ctx_sx;
165 struct mtx ifc_state_mtx;
167 iflib_txq_t ifc_txqs;
168 iflib_rxq_t ifc_rxqs;
169 uint32_t ifc_if_flags;
171 uint32_t ifc_max_fl_buf_size;
172 uint32_t ifc_rx_mbuf_sz;
176 int ifc_watchdog_events;
177 struct cdev *ifc_led_dev;
178 struct resource *ifc_msix_mem;
180 struct if_irq ifc_legacy_irq;
181 struct grouptask ifc_admin_task;
182 struct grouptask ifc_vflr_task;
183 struct iflib_filter_info ifc_filter_info;
184 struct ifmedia ifc_media;
186 struct sysctl_oid *ifc_sysctl_node;
187 uint16_t ifc_sysctl_ntxqs;
188 uint16_t ifc_sysctl_nrxqs;
189 uint16_t ifc_sysctl_qs_eq_override;
190 uint16_t ifc_sysctl_rx_budget;
191 uint16_t ifc_sysctl_tx_abdicate;
193 qidx_t ifc_sysctl_ntxds[8];
194 qidx_t ifc_sysctl_nrxds[8];
195 struct if_txrx ifc_txrx;
196 #define isc_txd_encap ifc_txrx.ift_txd_encap
197 #define isc_txd_flush ifc_txrx.ift_txd_flush
198 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
199 #define isc_rxd_available ifc_txrx.ift_rxd_available
200 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
201 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
202 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
203 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
206 eventhandler_tag ifc_vlan_attach_event;
207 eventhandler_tag ifc_vlan_detach_event;
208 struct ether_addr ifc_mac;
209 char ifc_mtx_name[16];
214 iflib_get_softc(if_ctx_t ctx)
217 return (ctx->ifc_softc);
221 iflib_get_dev(if_ctx_t ctx)
224 return (ctx->ifc_dev);
228 iflib_get_ifp(if_ctx_t ctx)
231 return (ctx->ifc_ifp);
235 iflib_get_media(if_ctx_t ctx)
238 return (&ctx->ifc_media);
242 iflib_get_flags(if_ctx_t ctx)
244 return (ctx->ifc_flags);
248 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
251 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
255 iflib_get_softc_ctx(if_ctx_t ctx)
258 return (&ctx->ifc_softc_ctx);
262 iflib_get_sctx(if_ctx_t ctx)
265 return (ctx->ifc_sctx);
268 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
269 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
270 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
272 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
273 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
275 typedef struct iflib_sw_rx_desc_array {
276 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
277 struct mbuf **ifsd_m; /* pkthdr mbufs */
278 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
279 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
280 } iflib_rxsd_array_t;
282 typedef struct iflib_sw_tx_desc_array {
283 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
284 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
285 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 #define IFLIB_RX_COPY_THRESH 128
292 #define IFLIB_MAX_RX_REFRESH 32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC 16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
296 #define IFLIB_QUEUE_IDLE 0
297 #define IFLIB_QUEUE_HUNG 1
298 #define IFLIB_QUEUE_WORKING 2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR 4
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE 32
305 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
314 qidx_t ift_cidx_processed;
317 uint8_t ift_br_offset;
318 uint16_t ift_npending;
319 uint16_t ift_db_pending;
320 uint16_t ift_rs_pending;
322 uint8_t ift_txd_size[8];
323 uint64_t ift_processed;
324 uint64_t ift_cleaned;
325 uint64_t ift_cleaned_prev;
327 uint64_t ift_enqueued;
328 uint64_t ift_dequeued;
330 uint64_t ift_no_tx_dma_setup;
331 uint64_t ift_no_desc_avail;
332 uint64_t ift_mbuf_defrag_failed;
333 uint64_t ift_mbuf_defrag;
334 uint64_t ift_map_failed;
335 uint64_t ift_txd_encap_efbig;
336 uint64_t ift_pullups;
337 uint64_t ift_last_timer_tick;
340 struct mtx ift_db_mtx;
342 /* constant values */
344 struct ifmp_ring *ift_br;
345 struct grouptask ift_task;
348 struct callout ift_timer;
350 if_txsd_vec_t ift_sds;
353 uint8_t ift_update_freq;
354 struct iflib_filter_info ift_filter_info;
355 bus_dma_tag_t ift_buf_tag;
356 bus_dma_tag_t ift_tso_buf_tag;
357 iflib_dma_info_t ift_ifdi;
358 #define MTX_NAME_LEN 16
359 char ift_mtx_name[MTX_NAME_LEN];
360 char ift_db_mtx_name[MTX_NAME_LEN];
361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 uint64_t ift_cpu_exec_count[256];
365 } __aligned(CACHE_LINE_SIZE);
372 uint8_t ifl_rxd_size;
374 uint64_t ifl_m_enqueued;
375 uint64_t ifl_m_dequeued;
376 uint64_t ifl_cl_enqueued;
377 uint64_t ifl_cl_dequeued;
381 bitstr_t *ifl_rx_bitmap;
385 uint16_t ifl_buf_size;
388 iflib_rxsd_array_t ifl_sds;
391 bus_dma_tag_t ifl_buf_tag;
392 iflib_dma_info_t ifl_ifdi;
393 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
394 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
395 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
396 } __aligned(CACHE_LINE_SIZE);
399 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
405 else if (pidx < cidx)
406 used = size - cidx + pidx;
407 else if (gen == 0 && pidx == cidx)
409 else if (gen == 1 && pidx == cidx)
417 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
419 #define IDXDIFF(head, tail, wrap) \
420 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
423 /* If there is a separate completion queue -
424 * these are the cq cidx and pidx. Otherwise
431 uint8_t ifr_fl_offset;
436 struct pfil_head *pfil;
438 uint8_t ifr_lro_enabled;
441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
442 struct lro_ctrl ifr_lc;
443 struct grouptask ifr_task;
444 struct iflib_filter_info ifr_filter_info;
445 iflib_dma_info_t ifr_ifdi;
447 /* dynamically allocate if any drivers need a value substantially larger than this */
448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
449 #ifdef IFLIB_DIAGNOSTICS
450 uint64_t ifr_cpu_exec_count[256];
452 } __aligned(CACHE_LINE_SIZE);
454 typedef struct if_rxsd {
460 /* multiple of word size */
462 #define PKT_INFO_SIZE 6
463 #define RXD_INFO_SIZE 5
464 #define PKT_TYPE uint64_t
466 #define PKT_INFO_SIZE 11
467 #define RXD_INFO_SIZE 8
468 #define PKT_TYPE uint32_t
470 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
471 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
473 typedef struct if_pkt_info_pad {
474 PKT_TYPE pkt_val[PKT_INFO_SIZE];
475 } *if_pkt_info_pad_t;
476 typedef struct if_rxd_info_pad {
477 PKT_TYPE rxd_val[RXD_INFO_SIZE];
478 } *if_rxd_info_pad_t;
480 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
481 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
485 pkt_info_zero(if_pkt_info_t pi)
487 if_pkt_info_pad_t pi_pad;
489 pi_pad = (if_pkt_info_pad_t)pi;
490 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
491 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
493 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
494 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
498 static device_method_t iflib_pseudo_methods[] = {
499 DEVMETHOD(device_attach, noop_attach),
500 DEVMETHOD(device_detach, iflib_pseudo_detach),
504 driver_t iflib_pseudodriver = {
505 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
509 rxd_info_zero(if_rxd_info_t ri)
511 if_rxd_info_pad_t ri_pad;
514 ri_pad = (if_rxd_info_pad_t)ri;
515 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
516 ri_pad->rxd_val[i] = 0;
517 ri_pad->rxd_val[i+1] = 0;
518 ri_pad->rxd_val[i+2] = 0;
519 ri_pad->rxd_val[i+3] = 0;
522 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
527 * Only allow a single packet to take up most 1/nth of the tx ring
529 #define MAX_SINGLE_PACKET_FRACTION 12
530 #define IF_BAD_DMA (bus_addr_t)-1
532 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
534 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
535 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
536 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
537 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
540 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
541 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
542 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
543 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
547 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
548 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
551 iflib_set_detach(if_ctx_t ctx)
554 ctx->ifc_flags |= IFC_IN_DETACH;
558 /* Our boot-time initialization hook */
559 static int iflib_module_event_handler(module_t, int, void *);
561 static moduledata_t iflib_moduledata = {
563 iflib_module_event_handler,
567 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
568 MODULE_VERSION(iflib, 1);
570 MODULE_DEPEND(iflib, pci, 1, 1, 1);
571 MODULE_DEPEND(iflib, ether, 1, 1, 1);
573 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
574 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
576 #ifndef IFLIB_DEBUG_COUNTERS
578 #define IFLIB_DEBUG_COUNTERS 1
580 #define IFLIB_DEBUG_COUNTERS 0
581 #endif /* !INVARIANTS */
584 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
585 "iflib driver parameters");
588 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
590 static int iflib_min_tx_latency = 0;
591 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
592 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
593 static int iflib_no_tx_batch = 0;
594 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
595 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
598 #if IFLIB_DEBUG_COUNTERS
600 static int iflib_tx_seen;
601 static int iflib_tx_sent;
602 static int iflib_tx_encap;
603 static int iflib_rx_allocs;
604 static int iflib_fl_refills;
605 static int iflib_fl_refills_large;
606 static int iflib_tx_frees;
608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
609 &iflib_tx_seen, 0, "# tx mbufs seen");
610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
611 &iflib_tx_sent, 0, "# tx mbufs sent");
612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
613 &iflib_tx_encap, 0, "# tx mbufs encapped");
614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
615 &iflib_tx_frees, 0, "# tx frees");
616 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
617 &iflib_rx_allocs, 0, "# rx allocations");
618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
619 &iflib_fl_refills, 0, "# refills");
620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
621 &iflib_fl_refills_large, 0, "# large refills");
624 static int iflib_txq_drain_flushing;
625 static int iflib_txq_drain_oactive;
626 static int iflib_txq_drain_notready;
628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
629 &iflib_txq_drain_flushing, 0, "# drain flushes");
630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
631 &iflib_txq_drain_oactive, 0, "# drain oactives");
632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
633 &iflib_txq_drain_notready, 0, "# drain notready");
636 static int iflib_encap_load_mbuf_fail;
637 static int iflib_encap_pad_mbuf_fail;
638 static int iflib_encap_txq_avail_fail;
639 static int iflib_encap_txd_encap_fail;
641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
642 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
644 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
646 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
648 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
650 static int iflib_task_fn_rxs;
651 static int iflib_rx_intr_enables;
652 static int iflib_fast_intrs;
653 static int iflib_rx_unavail;
654 static int iflib_rx_ctx_inactive;
655 static int iflib_rx_if_input;
656 static int iflib_rxd_flush;
658 static int iflib_verbose_debug;
660 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
661 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
663 &iflib_rx_intr_enables, 0, "# rx intr enables");
664 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
665 &iflib_fast_intrs, 0, "# fast_intr calls");
666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
667 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
669 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
671 &iflib_rx_if_input, 0, "# times rxeof called if_input");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
673 &iflib_rxd_flush, 0, "# times rxd_flush called");
674 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
675 &iflib_verbose_debug, 0, "enable verbose debugging");
677 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
679 iflib_debug_reset(void)
681 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
682 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
683 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
684 iflib_txq_drain_notready =
685 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
686 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
687 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
689 iflib_rx_ctx_inactive = iflib_rx_if_input =
694 #define DBG_COUNTER_INC(name)
695 static void iflib_debug_reset(void) {}
698 #define IFLIB_DEBUG 0
700 static void iflib_tx_structures_free(if_ctx_t ctx);
701 static void iflib_rx_structures_free(if_ctx_t ctx);
702 static int iflib_queues_alloc(if_ctx_t ctx);
703 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
704 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
705 static int iflib_qset_structures_setup(if_ctx_t ctx);
706 static int iflib_msix_init(if_ctx_t ctx);
707 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
708 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
709 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
711 static void iflib_altq_if_start(if_t ifp);
712 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
714 static int iflib_register(if_ctx_t);
715 static void iflib_init_locked(if_ctx_t ctx);
716 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
717 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
718 static void iflib_ifmp_purge(iflib_txq_t txq);
719 static void _iflib_pre_assert(if_softc_ctx_t scctx);
720 static void iflib_if_init_locked(if_ctx_t ctx);
721 static void iflib_free_intr_mem(if_ctx_t ctx);
722 #ifndef __NO_STRICT_ALIGNMENT
723 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
726 NETDUMP_DEFINE(iflib);
729 #include <sys/selinfo.h>
730 #include <net/netmap.h>
731 #include <dev/netmap/netmap_kern.h>
733 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
735 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
738 * device-specific sysctl variables:
740 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
741 * During regular operations the CRC is stripped, but on some
742 * hardware reception of frames not multiple of 64 is slower,
743 * so using crcstrip=0 helps in benchmarks.
745 * iflib_rx_miss, iflib_rx_miss_bufs:
746 * count packets that might be missed due to lost interrupts.
748 SYSCTL_DECL(_dev_netmap);
750 * The xl driver by default strips CRCs and we do not override it.
753 int iflib_crcstrip = 1;
754 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
755 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
757 int iflib_rx_miss, iflib_rx_miss_bufs;
758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
759 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
761 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
764 * Register/unregister. We are already under netmap lock.
765 * Only called on the first register or the last unregister.
768 iflib_netmap_register(struct netmap_adapter *na, int onoff)
770 struct ifnet *ifp = na->ifp;
771 if_ctx_t ctx = ifp->if_softc;
775 IFDI_INTR_DISABLE(ctx);
777 /* Tell the stack that the interface is no longer active */
778 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
781 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
783 /* enable or disable flags and callbacks in na and ifp */
785 nm_set_native_flags(na);
787 nm_clear_native_flags(na);
790 iflib_init_locked(ctx);
791 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
792 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
794 nm_clear_native_flags(na);
800 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
802 struct netmap_adapter *na = kring->na;
803 u_int const lim = kring->nkr_num_slots - 1;
804 u_int head = kring->rhead;
805 struct netmap_ring *ring = kring->ring;
807 struct if_rxd_update iru;
808 if_ctx_t ctx = rxq->ifr_ctx;
809 iflib_fl_t fl = &rxq->ifr_fl[0];
810 uint32_t refill_pidx, nic_i;
811 #if IFLIB_DEBUG_COUNTERS
815 if (nm_i == head && __predict_true(!init))
817 iru_init(&iru, rxq, 0 /* flid */);
818 map = fl->ifl_sds.ifsd_map;
819 refill_pidx = netmap_idx_k2n(kring, nm_i);
821 * IMPORTANT: we must leave one free slot in the ring,
822 * so move head back by one unit
824 head = nm_prev(head, lim);
826 DBG_COUNTER_INC(fl_refills);
827 while (nm_i != head) {
828 #if IFLIB_DEBUG_COUNTERS
830 DBG_COUNTER_INC(fl_refills_large);
832 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
833 struct netmap_slot *slot = &ring->slot[nm_i];
834 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
835 uint32_t nic_i_dma = refill_pidx;
836 nic_i = netmap_idx_k2n(kring, nm_i);
838 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
840 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
841 return netmap_ring_reinit(kring);
843 fl->ifl_vm_addrs[tmp_pidx] = addr;
844 if (__predict_false(init)) {
845 netmap_load_map(na, fl->ifl_buf_tag,
847 } else if (slot->flags & NS_BUF_CHANGED) {
848 /* buffer has changed, reload map */
849 netmap_reload_map(na, fl->ifl_buf_tag,
852 slot->flags &= ~NS_BUF_CHANGED;
854 nm_i = nm_next(nm_i, lim);
855 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
856 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
859 iru.iru_pidx = refill_pidx;
860 iru.iru_count = tmp_pidx+1;
861 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
863 for (int n = 0; n < iru.iru_count; n++) {
864 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
865 BUS_DMASYNC_PREREAD);
866 /* XXX - change this to not use the netmap func*/
867 nic_i_dma = nm_next(nic_i_dma, lim);
871 kring->nr_hwcur = head;
873 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
874 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
875 if (__predict_true(nic_i != UINT_MAX)) {
876 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
877 DBG_COUNTER_INC(rxd_flush);
883 * Reconcile kernel and user view of the transmit ring.
885 * All information is in the kring.
886 * Userspace wants to send packets up to the one before kring->rhead,
887 * kernel knows kring->nr_hwcur is the first unsent packet.
889 * Here we push packets out (as many as possible), and possibly
890 * reclaim buffers from previously completed transmission.
892 * The caller (netmap) guarantees that there is only one instance
893 * running at any time. Any interference with other driver
894 * methods should be handled by the individual drivers.
897 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
899 struct netmap_adapter *na = kring->na;
900 struct ifnet *ifp = na->ifp;
901 struct netmap_ring *ring = kring->ring;
902 u_int nm_i; /* index into the netmap kring */
903 u_int nic_i; /* index into the NIC ring */
905 u_int const lim = kring->nkr_num_slots - 1;
906 u_int const head = kring->rhead;
907 struct if_pkt_info pi;
910 * interrupts on every tx packet are expensive so request
911 * them every half ring, or where NS_REPORT is set
913 u_int report_frequency = kring->nkr_num_slots >> 1;
914 /* device-specific */
915 if_ctx_t ctx = ifp->if_softc;
916 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
918 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
919 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
922 * First part: process new packets to send.
923 * nm_i is the current index in the netmap kring,
924 * nic_i is the corresponding index in the NIC ring.
926 * If we have packets to send (nm_i != head)
927 * iterate over the netmap ring, fetch length and update
928 * the corresponding slot in the NIC ring. Some drivers also
929 * need to update the buffer's physical address in the NIC slot
930 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
932 * The netmap_reload_map() calls is especially expensive,
933 * even when (as in this case) the tag is 0, so do only
934 * when the buffer has actually changed.
936 * If possible do not set the report/intr bit on all slots,
937 * but only a few times per ring or when NS_REPORT is set.
939 * Finally, on 10G and faster drivers, it might be useful
940 * to prefetch the next slot and txr entry.
943 nm_i = kring->nr_hwcur;
944 if (nm_i != head) { /* we have new packets to send */
946 pi.ipi_segs = txq->ift_segs;
947 pi.ipi_qsidx = kring->ring_id;
948 nic_i = netmap_idx_k2n(kring, nm_i);
950 __builtin_prefetch(&ring->slot[nm_i]);
951 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
952 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
954 for (n = 0; nm_i != head; n++) {
955 struct netmap_slot *slot = &ring->slot[nm_i];
956 u_int len = slot->len;
958 void *addr = PNMB(na, slot, &paddr);
959 int flags = (slot->flags & NS_REPORT ||
960 nic_i == 0 || nic_i == report_frequency) ?
963 /* device-specific */
965 pi.ipi_segs[0].ds_addr = paddr;
966 pi.ipi_segs[0].ds_len = len;
970 pi.ipi_flags = flags;
972 /* Fill the slot in the NIC ring. */
973 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
974 DBG_COUNTER_INC(tx_encap);
976 /* prefetch for next round */
977 __builtin_prefetch(&ring->slot[nm_i + 1]);
978 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
979 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
981 NM_CHECK_ADDR_LEN(na, addr, len);
983 if (slot->flags & NS_BUF_CHANGED) {
984 /* buffer has changed, reload map */
985 netmap_reload_map(na, txq->ift_buf_tag,
986 txq->ift_sds.ifsd_map[nic_i], addr);
988 /* make sure changes to the buffer are synced */
989 bus_dmamap_sync(txq->ift_buf_tag,
990 txq->ift_sds.ifsd_map[nic_i],
991 BUS_DMASYNC_PREWRITE);
993 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
994 nm_i = nm_next(nm_i, lim);
995 nic_i = nm_next(nic_i, lim);
997 kring->nr_hwcur = nm_i;
999 /* synchronize the NIC ring */
1000 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1001 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1003 /* (re)start the tx unit up to slot nic_i (excluded) */
1004 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1008 * Second part: reclaim buffers for completed transmissions.
1010 * If there are unclaimed buffers, attempt to reclaim them.
1011 * If none are reclaimed, and TX IRQs are not in use, do an initial
1012 * minimal delay, then trigger the tx handler which will spin in the
1015 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1016 if (iflib_tx_credits_update(ctx, txq)) {
1017 /* some tx completed, increment avail */
1018 nic_i = txq->ift_cidx_processed;
1019 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1022 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1024 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1025 iflib_timer, txq, txq->ift_timer.c_cpu);
1031 * Reconcile kernel and user view of the receive ring.
1032 * Same as for the txsync, this routine must be efficient.
1033 * The caller guarantees a single invocations, but races against
1034 * the rest of the driver should be handled here.
1036 * On call, kring->rhead is the first packet that userspace wants
1037 * to keep, and kring->rcur is the wakeup point.
1038 * The kernel has previously reported packets up to kring->rtail.
1040 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1041 * of whether or not we received an interrupt.
1044 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1046 struct netmap_adapter *na = kring->na;
1047 struct netmap_ring *ring = kring->ring;
1049 uint32_t nm_i; /* index into the netmap ring */
1050 uint32_t nic_i; /* index into the NIC ring */
1052 u_int const lim = kring->nkr_num_slots - 1;
1053 u_int const head = kring->rhead;
1054 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1055 struct if_rxd_info ri;
1057 struct ifnet *ifp = na->ifp;
1058 if_ctx_t ctx = ifp->if_softc;
1059 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1061 return netmap_ring_reinit(kring);
1064 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1067 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1068 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1069 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1073 * First part: import newly received packets.
1075 * nm_i is the index of the next free slot in the netmap ring,
1076 * nic_i is the index of the next received packet in the NIC ring,
1077 * and they may differ in case if_init() has been called while
1078 * in netmap mode. For the receive ring we have
1080 * nic_i = rxr->next_check;
1081 * nm_i = kring->nr_hwtail (previous)
1083 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1085 * rxr->next_check is set to 0 on a ring reinit
1087 if (netmap_no_pendintr || force_update) {
1088 int crclen = iflib_crcstrip ? 0 : 4;
1091 for (i = 0; i < rxq->ifr_nfl; i++) {
1092 fl = &rxq->ifr_fl[i];
1093 nic_i = fl->ifl_cidx;
1094 nm_i = netmap_idx_n2k(kring, nic_i);
1095 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1096 rxq->ifr_id, nic_i, USHRT_MAX);
1097 for (n = 0; avail > 0; n++, avail--) {
1099 ri.iri_frags = rxq->ifr_frags;
1100 ri.iri_qsidx = kring->ring_id;
1101 ri.iri_ifp = ctx->ifc_ifp;
1102 ri.iri_cidx = nic_i;
1104 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1105 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1106 ring->slot[nm_i].flags = 0;
1107 bus_dmamap_sync(fl->ifl_buf_tag,
1108 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1109 nm_i = nm_next(nm_i, lim);
1110 nic_i = nm_next(nic_i, lim);
1112 if (n) { /* update the state variables */
1113 if (netmap_no_pendintr && !force_update) {
1116 iflib_rx_miss_bufs += n;
1118 fl->ifl_cidx = nic_i;
1119 kring->nr_hwtail = nm_i;
1121 kring->nr_kflags &= ~NKR_PENDINTR;
1125 * Second part: skip past packets that userspace has released.
1126 * (kring->nr_hwcur to head excluded),
1127 * and make the buffers available for reception.
1128 * As usual nm_i is the index in the netmap ring,
1129 * nic_i is the index in the NIC ring, and
1130 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1132 /* XXX not sure how this will work with multiple free lists */
1133 nm_i = kring->nr_hwcur;
1135 return (netmap_fl_refill(rxq, kring, nm_i, false));
1139 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1141 struct ifnet *ifp = na->ifp;
1142 if_ctx_t ctx = ifp->if_softc;
1146 IFDI_INTR_ENABLE(ctx);
1148 IFDI_INTR_DISABLE(ctx);
1155 iflib_netmap_attach(if_ctx_t ctx)
1157 struct netmap_adapter na;
1158 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1160 bzero(&na, sizeof(na));
1162 na.ifp = ctx->ifc_ifp;
1163 na.na_flags = NAF_BDG_MAYSLEEP;
1164 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1165 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1167 na.num_tx_desc = scctx->isc_ntxd[0];
1168 na.num_rx_desc = scctx->isc_nrxd[0];
1169 na.nm_txsync = iflib_netmap_txsync;
1170 na.nm_rxsync = iflib_netmap_rxsync;
1171 na.nm_register = iflib_netmap_register;
1172 na.nm_intr = iflib_netmap_intr;
1173 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1174 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1175 return (netmap_attach(&na));
1179 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1181 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1182 struct netmap_slot *slot;
1184 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1187 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1190 * In netmap mode, set the map for the packet buffer.
1191 * NOTE: Some drivers (not this one) also need to set
1192 * the physical buffer address in the NIC ring.
1193 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1194 * netmap slot index, si
1196 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1197 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1198 NMB(na, slot + si));
1203 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1205 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1206 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1207 struct netmap_slot *slot;
1210 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1213 nm_i = netmap_idx_n2k(kring, 0);
1214 netmap_fl_refill(rxq, kring, nm_i, true);
1218 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1220 struct netmap_kring *kring;
1223 txqid = txq->ift_id;
1224 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1226 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1227 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1228 BUS_DMASYNC_POSTREAD);
1229 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1230 netmap_tx_irq(ctx->ifc_ifp, txqid);
1231 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1235 *reset_on = hz / 1000;
1240 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1243 #define iflib_netmap_txq_init(ctx, txq)
1244 #define iflib_netmap_rxq_init(ctx, rxq)
1245 #define iflib_netmap_detach(ifp)
1247 #define iflib_netmap_attach(ctx) (0)
1248 #define netmap_rx_irq(ifp, qid, budget) (0)
1249 #define netmap_tx_irq(ifp, qid) do {} while (0)
1250 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1254 #if defined(__i386__) || defined(__amd64__)
1255 static __inline void
1258 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1260 static __inline void
1261 prefetch2cachelines(void *x)
1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1264 #if (CACHE_LINE_SIZE < 128)
1265 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1270 #define prefetch2cachelines(x)
1274 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1278 fl = &rxq->ifr_fl[flid];
1279 iru->iru_paddrs = fl->ifl_bus_addrs;
1280 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1281 iru->iru_idxs = fl->ifl_rxd_idxs;
1282 iru->iru_qsidx = rxq->ifr_id;
1283 iru->iru_buf_size = fl->ifl_buf_size;
1284 iru->iru_flidx = fl->ifl_id;
1288 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1292 *(bus_addr_t *) arg = segs[0].ds_addr;
1296 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1299 device_t dev = ctx->ifc_dev;
1301 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1302 align, 0, /* alignment, bounds */
1303 BUS_SPACE_MAXADDR, /* lowaddr */
1304 BUS_SPACE_MAXADDR, /* highaddr */
1305 NULL, NULL, /* filter, filterarg */
1308 size, /* maxsegsize */
1309 BUS_DMA_ALLOCNOW, /* flags */
1310 NULL, /* lockfunc */
1315 "%s: bus_dma_tag_create failed: %d\n",
1320 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1321 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1324 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1325 __func__, (uintmax_t)size, err);
1329 dma->idi_paddr = IF_BAD_DMA;
1330 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1331 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1332 if (err || dma->idi_paddr == IF_BAD_DMA) {
1334 "%s: bus_dmamap_load failed: %d\n",
1339 dma->idi_size = size;
1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1345 bus_dma_tag_destroy(dma->idi_tag);
1347 dma->idi_tag = NULL;
1353 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1355 if_shared_ctx_t sctx = ctx->ifc_sctx;
1357 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1359 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1363 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1366 iflib_dma_info_t *dmaiter;
1369 for (i = 0; i < count; i++, dmaiter++) {
1370 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1374 iflib_dma_free_multi(dmalist, i);
1379 iflib_dma_free(iflib_dma_info_t dma)
1381 if (dma->idi_tag == NULL)
1383 if (dma->idi_paddr != IF_BAD_DMA) {
1384 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1385 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1386 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1387 dma->idi_paddr = IF_BAD_DMA;
1389 if (dma->idi_vaddr != NULL) {
1390 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1391 dma->idi_vaddr = NULL;
1393 bus_dma_tag_destroy(dma->idi_tag);
1394 dma->idi_tag = NULL;
1398 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1401 iflib_dma_info_t *dmaiter = dmalist;
1403 for (i = 0; i < count; i++, dmaiter++)
1404 iflib_dma_free(*dmaiter);
1407 #ifdef EARLY_AP_STARTUP
1408 static const int iflib_started = 1;
1411 * We used to abuse the smp_started flag to decide if the queues have been
1412 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1413 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1414 * is set. Run a SYSINIT() strictly after that to just set a usable
1418 static int iflib_started;
1421 iflib_record_started(void *arg)
1426 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1427 iflib_record_started, NULL);
1431 iflib_fast_intr(void *arg)
1433 iflib_filter_info_t info = arg;
1434 struct grouptask *gtask = info->ifi_task;
1438 return (FILTER_STRAY);
1440 DBG_COUNTER_INC(fast_intrs);
1441 if (info->ifi_filter != NULL) {
1442 result = info->ifi_filter(info->ifi_filter_arg);
1443 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1447 GROUPTASK_ENQUEUE(gtask);
1448 return (FILTER_HANDLED);
1452 iflib_fast_intr_rxtx(void *arg)
1454 iflib_filter_info_t info = arg;
1455 struct grouptask *gtask = info->ifi_task;
1457 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1460 int i, cidx, result;
1464 return (FILTER_STRAY);
1466 DBG_COUNTER_INC(fast_intrs);
1467 if (info->ifi_filter != NULL) {
1468 result = info->ifi_filter(info->ifi_filter_arg);
1469 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1474 sc = ctx->ifc_softc;
1475 MPASS(rxq->ifr_ntxqirq);
1476 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1477 txqid = rxq->ifr_txqid[i];
1478 txq = &ctx->ifc_txqs[txqid];
1479 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1480 BUS_DMASYNC_POSTREAD);
1481 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1482 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1485 GROUPTASK_ENQUEUE(&txq->ift_task);
1487 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1488 cidx = rxq->ifr_cq_cidx;
1490 cidx = rxq->ifr_fl[0].ifl_cidx;
1491 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1492 GROUPTASK_ENQUEUE(gtask);
1494 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1495 DBG_COUNTER_INC(rx_intr_enables);
1497 return (FILTER_HANDLED);
1502 iflib_fast_intr_ctx(void *arg)
1504 iflib_filter_info_t info = arg;
1505 struct grouptask *gtask = info->ifi_task;
1509 return (FILTER_STRAY);
1511 DBG_COUNTER_INC(fast_intrs);
1512 if (info->ifi_filter != NULL) {
1513 result = info->ifi_filter(info->ifi_filter_arg);
1514 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1518 GROUPTASK_ENQUEUE(gtask);
1519 return (FILTER_HANDLED);
1523 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1524 driver_filter_t filter, driver_intr_t handler, void *arg,
1528 struct resource *res;
1530 device_t dev = ctx->ifc_dev;
1533 if (ctx->ifc_flags & IFC_LEGACY)
1534 flags |= RF_SHAREABLE;
1537 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1540 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1544 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1545 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1546 filter, handler, arg, &tag);
1549 "failed to setup interrupt for rid %d, name %s: %d\n",
1550 rid, name ? name : "unknown", rc);
1553 bus_describe_intr(dev, res, tag, "%s", name);
1560 /*********************************************************************
1562 * Allocate DMA resources for TX buffers as well as memory for the TX
1563 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1564 * iflib_sw_tx_desc_array structure, storing all the information that
1565 * is needed to transmit a packet on the wire. This is called only
1566 * once at attach, setup is done every reset.
1568 **********************************************************************/
1570 iflib_txsd_alloc(iflib_txq_t txq)
1572 if_ctx_t ctx = txq->ift_ctx;
1573 if_shared_ctx_t sctx = ctx->ifc_sctx;
1574 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1575 device_t dev = ctx->ifc_dev;
1576 bus_size_t tsomaxsize;
1577 int err, nsegments, ntsosegments;
1580 nsegments = scctx->isc_tx_nsegments;
1581 ntsosegments = scctx->isc_tx_tso_segments_max;
1582 tsomaxsize = scctx->isc_tx_tso_size_max;
1583 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1584 tsomaxsize += sizeof(struct ether_vlan_header);
1585 MPASS(scctx->isc_ntxd[0] > 0);
1586 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1587 MPASS(nsegments > 0);
1588 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1589 MPASS(ntsosegments > 0);
1590 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1594 * Set up DMA tags for TX buffers.
1596 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1597 1, 0, /* alignment, bounds */
1598 BUS_SPACE_MAXADDR, /* lowaddr */
1599 BUS_SPACE_MAXADDR, /* highaddr */
1600 NULL, NULL, /* filter, filterarg */
1601 sctx->isc_tx_maxsize, /* maxsize */
1602 nsegments, /* nsegments */
1603 sctx->isc_tx_maxsegsize, /* maxsegsize */
1605 NULL, /* lockfunc */
1606 NULL, /* lockfuncarg */
1607 &txq->ift_buf_tag))) {
1608 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1609 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1610 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1613 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1614 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1615 1, 0, /* alignment, bounds */
1616 BUS_SPACE_MAXADDR, /* lowaddr */
1617 BUS_SPACE_MAXADDR, /* highaddr */
1618 NULL, NULL, /* filter, filterarg */
1619 tsomaxsize, /* maxsize */
1620 ntsosegments, /* nsegments */
1621 sctx->isc_tso_maxsegsize,/* maxsegsize */
1623 NULL, /* lockfunc */
1624 NULL, /* lockfuncarg */
1625 &txq->ift_tso_buf_tag))) {
1626 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1631 /* Allocate memory for the TX mbuf map. */
1632 if (!(txq->ift_sds.ifsd_m =
1633 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1634 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1635 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1641 * Create the DMA maps for TX buffers.
1643 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1644 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1645 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1647 "Unable to allocate TX buffer DMA map memory\n");
1651 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1652 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1653 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1655 "Unable to allocate TSO TX buffer map memory\n");
1659 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1660 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1661 &txq->ift_sds.ifsd_map[i]);
1663 device_printf(dev, "Unable to create TX DMA map\n");
1668 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1669 &txq->ift_sds.ifsd_tso_map[i]);
1671 device_printf(dev, "Unable to create TSO TX DMA map\n");
1677 /* We free all, it handles case where we are in the middle */
1678 iflib_tx_structures_free(ctx);
1683 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1688 if (txq->ift_sds.ifsd_map != NULL)
1689 map = txq->ift_sds.ifsd_map[i];
1691 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1692 bus_dmamap_unload(txq->ift_buf_tag, map);
1693 bus_dmamap_destroy(txq->ift_buf_tag, map);
1694 txq->ift_sds.ifsd_map[i] = NULL;
1698 if (txq->ift_sds.ifsd_tso_map != NULL)
1699 map = txq->ift_sds.ifsd_tso_map[i];
1701 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1702 BUS_DMASYNC_POSTWRITE);
1703 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1704 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1705 txq->ift_sds.ifsd_tso_map[i] = NULL;
1710 iflib_txq_destroy(iflib_txq_t txq)
1712 if_ctx_t ctx = txq->ift_ctx;
1714 for (int i = 0; i < txq->ift_size; i++)
1715 iflib_txsd_destroy(ctx, txq, i);
1716 if (txq->ift_sds.ifsd_map != NULL) {
1717 free(txq->ift_sds.ifsd_map, M_IFLIB);
1718 txq->ift_sds.ifsd_map = NULL;
1720 if (txq->ift_sds.ifsd_tso_map != NULL) {
1721 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1722 txq->ift_sds.ifsd_tso_map = NULL;
1724 if (txq->ift_sds.ifsd_m != NULL) {
1725 free(txq->ift_sds.ifsd_m, M_IFLIB);
1726 txq->ift_sds.ifsd_m = NULL;
1728 if (txq->ift_buf_tag != NULL) {
1729 bus_dma_tag_destroy(txq->ift_buf_tag);
1730 txq->ift_buf_tag = NULL;
1732 if (txq->ift_tso_buf_tag != NULL) {
1733 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1734 txq->ift_tso_buf_tag = NULL;
1739 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1743 mp = &txq->ift_sds.ifsd_m[i];
1747 if (txq->ift_sds.ifsd_map != NULL) {
1748 bus_dmamap_sync(txq->ift_buf_tag,
1749 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1750 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1752 if (txq->ift_sds.ifsd_tso_map != NULL) {
1753 bus_dmamap_sync(txq->ift_tso_buf_tag,
1754 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1755 bus_dmamap_unload(txq->ift_tso_buf_tag,
1756 txq->ift_sds.ifsd_tso_map[i]);
1759 DBG_COUNTER_INC(tx_frees);
1764 iflib_txq_setup(iflib_txq_t txq)
1766 if_ctx_t ctx = txq->ift_ctx;
1767 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1768 if_shared_ctx_t sctx = ctx->ifc_sctx;
1769 iflib_dma_info_t di;
1772 /* Set number of descriptors available */
1773 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1774 /* XXX make configurable */
1775 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1778 txq->ift_cidx_processed = 0;
1779 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1780 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1782 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1783 bzero((void *)di->idi_vaddr, di->idi_size);
1785 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1786 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1787 bus_dmamap_sync(di->idi_tag, di->idi_map,
1788 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1792 /*********************************************************************
1794 * Allocate DMA resources for RX buffers as well as memory for the RX
1795 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1796 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1797 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1798 * Since we use use one entry in iflib_sw_rx_desc_array per received
1799 * packet, the maximum number of entries we'll need is equal to the
1800 * number of hardware receive descriptors that we've allocated.
1802 **********************************************************************/
1804 iflib_rxsd_alloc(iflib_rxq_t rxq)
1806 if_ctx_t ctx = rxq->ifr_ctx;
1807 if_shared_ctx_t sctx = ctx->ifc_sctx;
1808 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1809 device_t dev = ctx->ifc_dev;
1813 MPASS(scctx->isc_nrxd[0] > 0);
1814 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1817 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1818 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1819 /* Set up DMA tag for RX buffers. */
1820 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1821 1, 0, /* alignment, bounds */
1822 BUS_SPACE_MAXADDR, /* lowaddr */
1823 BUS_SPACE_MAXADDR, /* highaddr */
1824 NULL, NULL, /* filter, filterarg */
1825 sctx->isc_rx_maxsize, /* maxsize */
1826 sctx->isc_rx_nsegments, /* nsegments */
1827 sctx->isc_rx_maxsegsize, /* maxsegsize */
1829 NULL, /* lockfunc */
1834 "Unable to allocate RX DMA tag: %d\n", err);
1838 /* Allocate memory for the RX mbuf map. */
1839 if (!(fl->ifl_sds.ifsd_m =
1840 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1841 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1843 "Unable to allocate RX mbuf map memory\n");
1848 /* Allocate memory for the direct RX cluster pointer map. */
1849 if (!(fl->ifl_sds.ifsd_cl =
1850 (caddr_t *) malloc(sizeof(caddr_t) *
1851 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1853 "Unable to allocate RX cluster map memory\n");
1858 /* Allocate memory for the RX cluster bus address map. */
1859 if (!(fl->ifl_sds.ifsd_ba =
1860 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1861 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1863 "Unable to allocate RX bus address map memory\n");
1869 * Create the DMA maps for RX buffers.
1871 if (!(fl->ifl_sds.ifsd_map =
1872 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1874 "Unable to allocate RX buffer DMA map memory\n");
1878 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1879 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1880 &fl->ifl_sds.ifsd_map[i]);
1882 device_printf(dev, "Unable to create RX buffer DMA map\n");
1890 iflib_rx_structures_free(ctx);
1896 * Internal service routines
1899 struct rxq_refill_cb_arg {
1901 bus_dma_segment_t seg;
1906 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1908 struct rxq_refill_cb_arg *cb_arg = arg;
1910 cb_arg->error = error;
1911 cb_arg->seg = segs[0];
1912 cb_arg->nseg = nseg;
1916 * rxq_refill - refill an rxq free-buffer list
1917 * @ctx: the iflib context
1918 * @rxq: the free-list to refill
1919 * @n: the number of new buffers to allocate
1921 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1922 * The caller must assure that @n does not exceed the queue's capacity.
1925 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1927 struct if_rxd_update iru;
1928 struct rxq_refill_cb_arg cb_arg;
1932 bus_dmamap_t *sd_map;
1933 bus_addr_t bus_addr, *sd_ba;
1934 int err, frag_idx, i, idx, n, pidx;
1937 sd_m = fl->ifl_sds.ifsd_m;
1938 sd_map = fl->ifl_sds.ifsd_map;
1939 sd_cl = fl->ifl_sds.ifsd_cl;
1940 sd_ba = fl->ifl_sds.ifsd_ba;
1941 pidx = fl->ifl_pidx;
1943 frag_idx = fl->ifl_fragidx;
1944 credits = fl->ifl_credits;
1949 MPASS(credits + n <= fl->ifl_size);
1951 if (pidx < fl->ifl_cidx)
1952 MPASS(pidx + n <= fl->ifl_cidx);
1953 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1954 MPASS(fl->ifl_gen == 0);
1955 if (pidx > fl->ifl_cidx)
1956 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1958 DBG_COUNTER_INC(fl_refills);
1960 DBG_COUNTER_INC(fl_refills_large);
1961 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1964 * We allocate an uninitialized mbuf + cluster, mbuf is
1965 * initialized after rx.
1967 * If the cluster is still set then we know a minimum sized packet was received
1969 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1972 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1973 MPASS(frag_idx >= 0);
1974 if ((cl = sd_cl[frag_idx]) == NULL) {
1975 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1979 MPASS(sd_map != NULL);
1980 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1981 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1983 if (err != 0 || cb_arg.error) {
1987 if (fl->ifl_zone == zone_pack)
1988 uma_zfree(fl->ifl_zone, cl);
1992 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
1993 sd_cl[frag_idx] = cl;
1995 fl->ifl_cl_enqueued++;
1998 bus_addr = sd_ba[frag_idx];
2000 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2001 BUS_DMASYNC_PREREAD);
2003 if (sd_m[frag_idx] == NULL) {
2004 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2009 bit_set(fl->ifl_rx_bitmap, frag_idx);
2011 fl->ifl_m_enqueued++;
2014 DBG_COUNTER_INC(rx_allocs);
2015 fl->ifl_rxd_idxs[i] = frag_idx;
2016 fl->ifl_bus_addrs[i] = bus_addr;
2017 fl->ifl_vm_addrs[i] = cl;
2020 MPASS(credits <= fl->ifl_size);
2021 if (++idx == fl->ifl_size) {
2025 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2026 iru.iru_pidx = pidx;
2028 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2032 fl->ifl_credits = credits;
2037 iru.iru_pidx = pidx;
2039 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2041 fl->ifl_credits = credits;
2043 DBG_COUNTER_INC(rxd_flush);
2044 if (fl->ifl_pidx == 0)
2045 pidx = fl->ifl_size - 1;
2047 pidx = fl->ifl_pidx - 1;
2049 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2050 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2051 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2052 fl->ifl_fragidx = frag_idx;
2055 static __inline void
2056 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2058 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2059 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2061 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2064 MPASS(fl->ifl_credits <= fl->ifl_size);
2065 MPASS(reclaimable == delta);
2067 if (reclaimable > 0)
2068 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2072 iflib_in_detach(if_ctx_t ctx)
2076 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2082 iflib_fl_bufs_free(iflib_fl_t fl)
2084 iflib_dma_info_t idi = fl->ifl_ifdi;
2085 bus_dmamap_t sd_map;
2088 for (i = 0; i < fl->ifl_size; i++) {
2089 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2090 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2092 if (*sd_cl != NULL) {
2093 sd_map = fl->ifl_sds.ifsd_map[i];
2094 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2095 BUS_DMASYNC_POSTREAD);
2096 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2098 uma_zfree(fl->ifl_zone, *sd_cl);
2099 // XXX: Should this get moved out?
2100 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2101 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2102 if (*sd_m != NULL) {
2103 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2104 uma_zfree(zone_mbuf, *sd_m);
2107 MPASS(*sd_cl == NULL);
2108 MPASS(*sd_m == NULL);
2111 fl->ifl_m_dequeued++;
2112 fl->ifl_cl_dequeued++;
2118 for (i = 0; i < fl->ifl_size; i++) {
2119 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2120 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2124 * Reset free list values
2126 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2127 bzero(idi->idi_vaddr, idi->idi_size);
2130 /*********************************************************************
2132 * Initialize a receive ring and its buffers.
2134 **********************************************************************/
2136 iflib_fl_setup(iflib_fl_t fl)
2138 iflib_rxq_t rxq = fl->ifl_rxq;
2139 if_ctx_t ctx = rxq->ifr_ctx;
2141 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2143 ** Free current RX buffer structs and their mbufs
2145 iflib_fl_bufs_free(fl);
2146 /* Now replenish the mbufs */
2147 MPASS(fl->ifl_credits == 0);
2148 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2149 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2150 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2151 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2152 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2155 /* avoid pre-allocating zillions of clusters to an idle card
2156 * potentially speeding up attach
2158 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2159 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2160 if (min(128, fl->ifl_size) != fl->ifl_credits)
2166 MPASS(fl->ifl_ifdi != NULL);
2167 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2172 /*********************************************************************
2174 * Free receive ring data structures
2176 **********************************************************************/
2178 iflib_rx_sds_free(iflib_rxq_t rxq)
2183 if (rxq->ifr_fl != NULL) {
2184 for (i = 0; i < rxq->ifr_nfl; i++) {
2185 fl = &rxq->ifr_fl[i];
2186 if (fl->ifl_buf_tag != NULL) {
2187 if (fl->ifl_sds.ifsd_map != NULL) {
2188 for (j = 0; j < fl->ifl_size; j++) {
2189 if (fl->ifl_sds.ifsd_map[j] ==
2194 fl->ifl_sds.ifsd_map[j],
2195 BUS_DMASYNC_POSTREAD);
2198 fl->ifl_sds.ifsd_map[j]);
2201 bus_dma_tag_destroy(fl->ifl_buf_tag);
2202 fl->ifl_buf_tag = NULL;
2204 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2205 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2206 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2207 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2208 fl->ifl_sds.ifsd_m = NULL;
2209 fl->ifl_sds.ifsd_cl = NULL;
2210 fl->ifl_sds.ifsd_ba = NULL;
2211 fl->ifl_sds.ifsd_map = NULL;
2213 free(rxq->ifr_fl, M_IFLIB);
2215 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2220 * MI independent logic
2224 iflib_timer(void *arg)
2226 iflib_txq_t txq = arg;
2227 if_ctx_t ctx = txq->ift_ctx;
2228 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2229 uint64_t this_tick = ticks;
2230 uint32_t reset_on = hz / 2;
2232 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2235 ** Check on the state of the TX queue(s), this
2236 ** can be done without the lock because its RO
2237 ** and the HUNG state will be static if set.
2239 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2240 txq->ift_last_timer_tick = this_tick;
2241 IFDI_TIMER(ctx, txq->ift_id);
2242 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2243 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2244 (sctx->isc_pause_frames == 0)))
2247 if (ifmp_ring_is_stalled(txq->ift_br))
2248 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2249 txq->ift_cleaned_prev = txq->ift_cleaned;
2252 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2253 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2255 /* handle any laggards */
2256 if (txq->ift_db_pending)
2257 GROUPTASK_ENQUEUE(&txq->ift_task);
2259 sctx->isc_pause_frames = 0;
2260 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2261 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2264 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2265 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2267 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2268 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2269 iflib_admin_intr_deferred(ctx);
2274 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2276 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2279 * XXX don't set the max_frame_size to larger
2280 * than the hardware can handle
2282 if (sctx->isc_max_frame_size <= MCLBYTES)
2283 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2285 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2289 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2291 return (ctx->ifc_rx_mbuf_sz);
2295 iflib_init_locked(if_ctx_t ctx)
2297 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2298 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2299 if_t ifp = ctx->ifc_ifp;
2303 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2306 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2307 IFDI_INTR_DISABLE(ctx);
2309 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2310 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2311 /* Set hardware offload abilities */
2312 if_clearhwassist(ifp);
2313 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2314 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2315 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2316 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2317 if (if_getcapenable(ifp) & IFCAP_TSO4)
2318 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2319 if (if_getcapenable(ifp) & IFCAP_TSO6)
2320 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2322 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2324 callout_stop(&txq->ift_timer);
2325 CALLOUT_UNLOCK(txq);
2326 iflib_netmap_txq_init(ctx, txq);
2330 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2331 * that drivers can use the value when setting up the hardware receive
2334 iflib_calc_rx_mbuf_sz(ctx);
2337 i = if_getdrvflags(ifp);
2340 MPASS(if_getdrvflags(ifp) == i);
2341 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2342 /* XXX this should really be done on a per-queue basis */
2343 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2344 MPASS(rxq->ifr_id == i);
2345 iflib_netmap_rxq_init(ctx, rxq);
2348 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2349 if (iflib_fl_setup(fl)) {
2350 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2356 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2357 IFDI_INTR_ENABLE(ctx);
2358 txq = ctx->ifc_txqs;
2359 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2360 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2361 txq->ift_timer.c_cpu);
2365 iflib_media_change(if_t ifp)
2367 if_ctx_t ctx = if_getsoftc(ifp);
2371 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2372 iflib_init_locked(ctx);
2378 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2380 if_ctx_t ctx = if_getsoftc(ifp);
2383 IFDI_UPDATE_ADMIN_STATUS(ctx);
2384 IFDI_MEDIA_STATUS(ctx, ifmr);
2389 iflib_stop(if_ctx_t ctx)
2391 iflib_txq_t txq = ctx->ifc_txqs;
2392 iflib_rxq_t rxq = ctx->ifc_rxqs;
2393 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2394 if_shared_ctx_t sctx = ctx->ifc_sctx;
2395 iflib_dma_info_t di;
2399 /* Tell the stack that the interface is no longer active */
2400 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2402 IFDI_INTR_DISABLE(ctx);
2407 iflib_debug_reset();
2408 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2409 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2410 /* make sure all transmitters have completed before proceeding XXX */
2413 callout_stop(&txq->ift_timer);
2414 CALLOUT_UNLOCK(txq);
2416 /* clean any enqueued buffers */
2417 iflib_ifmp_purge(txq);
2418 /* Free any existing tx buffers. */
2419 for (j = 0; j < txq->ift_size; j++) {
2420 iflib_txsd_free(ctx, txq, j);
2422 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2423 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2424 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2425 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2426 txq->ift_pullups = 0;
2427 ifmp_ring_reset_stats(txq->ift_br);
2428 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2429 bzero((void *)di->idi_vaddr, di->idi_size);
2431 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2432 /* make sure all transmitters have completed before proceeding XXX */
2434 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2435 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2436 bzero((void *)di->idi_vaddr, di->idi_size);
2437 /* also resets the free lists pidx/cidx */
2438 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2439 iflib_fl_bufs_free(fl);
2443 static inline caddr_t
2444 calc_next_rxd(iflib_fl_t fl, int cidx)
2448 caddr_t start, end, cur, next;
2450 nrxd = fl->ifl_size;
2451 size = fl->ifl_rxd_size;
2452 start = fl->ifl_ifdi->idi_vaddr;
2454 if (__predict_false(size == 0))
2456 cur = start + size*cidx;
2457 end = start + size*nrxd;
2458 next = CACHE_PTR_NEXT(cur);
2459 return (next < end ? next : start);
2463 prefetch_pkts(iflib_fl_t fl, int cidx)
2466 int nrxd = fl->ifl_size;
2470 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2471 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2472 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2473 next_rxd = calc_next_rxd(fl, cidx);
2475 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2476 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2477 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2478 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2479 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2480 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2481 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2482 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2485 static struct mbuf *
2486 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2487 int *pf_rv, if_rxd_info_t ri)
2493 int flid, cidx, len, next;
2496 flid = irf->irf_flid;
2497 cidx = irf->irf_idx;
2498 fl = &rxq->ifr_fl[flid];
2500 sd->ifsd_cidx = cidx;
2501 m = fl->ifl_sds.ifsd_m[cidx];
2502 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2505 fl->ifl_m_dequeued++;
2507 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2508 prefetch_pkts(fl, cidx);
2509 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2510 prefetch(&fl->ifl_sds.ifsd_map[next]);
2511 map = fl->ifl_sds.ifsd_map[cidx];
2512 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2514 /* not valid assert if bxe really does SGE from non-contiguous elements */
2515 MPASS(fl->ifl_cidx == cidx);
2516 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2518 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2519 payload = *sd->ifsd_cl;
2520 payload += ri->iri_pad;
2521 len = ri->iri_len - ri->iri_pad;
2522 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2523 len | PFIL_MEMPTR | PFIL_IN, NULL);
2528 * The filter ate it. Everything is recycled.
2533 case PFIL_REALLOCED:
2535 * The filter copied it. Everything is recycled.
2537 m = pfil_mem2mbuf(payload);
2542 * Filter said it was OK, so receive like
2545 fl->ifl_sds.ifsd_m[cidx] = NULL;
2551 fl->ifl_sds.ifsd_m[cidx] = NULL;
2556 bus_dmamap_unload(fl->ifl_buf_tag, map);
2557 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2558 if (__predict_false(fl->ifl_cidx == 0))
2560 bit_clear(fl->ifl_rx_bitmap, cidx);
2564 static struct mbuf *
2565 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2567 struct mbuf *m, *mh, *mt;
2569 int *pf_rv_ptr, flags, i, padlen;
2578 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2581 MPASS(*sd->ifsd_cl != NULL);
2584 * Exclude zero-length frags & frags from
2585 * packets the filter has consumed or dropped
2587 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2588 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2590 /* everything saved here */
2595 /* XXX we can save the cluster here, but not the mbuf */
2596 m_init(m, M_NOWAIT, MT_DATA, 0);
2601 flags = M_PKTHDR|M_EXT;
2603 padlen = ri->iri_pad;
2608 /* assuming padding is only on the first fragment */
2612 *sd->ifsd_cl = NULL;
2614 /* Can these two be made one ? */
2615 m_init(m, M_NOWAIT, MT_DATA, flags);
2616 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2618 * These must follow m_init and m_cljset
2620 m->m_data += padlen;
2621 ri->iri_len -= padlen;
2622 m->m_len = ri->iri_frags[i].irf_len;
2623 } while (++i < ri->iri_nfrags);
2629 * Process one software descriptor
2631 static struct mbuf *
2632 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2638 /* should I merge this back in now that the two paths are basically duplicated? */
2639 if (ri->iri_nfrags == 1 &&
2640 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2641 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2643 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2645 if (pf_rv == PFIL_PASS) {
2646 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2647 #ifndef __NO_STRICT_ALIGNMENT
2651 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2652 m->m_len = ri->iri_frags[0].irf_len;
2655 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2656 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2659 m->m_pkthdr.len = ri->iri_len;
2660 m->m_pkthdr.rcvif = ri->iri_ifp;
2661 m->m_flags |= ri->iri_flags;
2662 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2663 m->m_pkthdr.flowid = ri->iri_flowid;
2664 M_HASHTYPE_SET(m, ri->iri_rsstype);
2665 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2666 m->m_pkthdr.csum_data = ri->iri_csum_data;
2670 #if defined(INET6) || defined(INET)
2672 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2674 CURVNET_SET(lc->ifp->if_vnet);
2676 *v6 = VNET(ip6_forwarding);
2679 *v4 = VNET(ipforwarding);
2685 * Returns true if it's possible this packet could be LROed.
2686 * if it returns false, it is guaranteed that tcp_lro_rx()
2687 * would not return zero.
2690 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2692 struct ether_header *eh;
2695 eh = mtod(m, struct ether_header *);
2696 eh_type = ntohs(eh->ether_type);
2699 case ETHERTYPE_IPV6:
2700 return !v6_forwarding;
2704 return !v4_forwarding;
2712 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2718 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2720 if_ctx_t ctx = rxq->ifr_ctx;
2721 if_shared_ctx_t sctx = ctx->ifc_sctx;
2722 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2725 struct if_rxd_info ri;
2726 int err, budget_left, rx_bytes, rx_pkts;
2730 bool v4_forwarding, v6_forwarding, lro_possible;
2733 * XXX early demux data packets so that if_input processing only handles
2734 * acks in interrupt context
2736 struct mbuf *m, *mh, *mt, *mf;
2738 lro_possible = v4_forwarding = v6_forwarding = false;
2742 rx_pkts = rx_bytes = 0;
2743 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2744 cidxp = &rxq->ifr_cq_cidx;
2746 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2747 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2748 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2749 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2750 DBG_COUNTER_INC(rx_unavail);
2754 /* pfil needs the vnet to be set */
2755 CURVNET_SET_QUIET(ifp->if_vnet);
2756 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2757 if (__predict_false(!CTX_ACTIVE(ctx))) {
2758 DBG_COUNTER_INC(rx_ctx_inactive);
2762 * Reset client set fields to their default values
2765 ri.iri_qsidx = rxq->ifr_id;
2766 ri.iri_cidx = *cidxp;
2768 ri.iri_frags = rxq->ifr_frags;
2769 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2774 rx_bytes += ri.iri_len;
2775 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2776 *cidxp = ri.iri_cidx;
2777 /* Update our consumer index */
2778 /* XXX NB: shurd - check if this is still safe */
2779 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2780 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2781 rxq->ifr_cq_gen = 0;
2783 /* was this only a completion queue message? */
2784 if (__predict_false(ri.iri_nfrags == 0))
2787 MPASS(ri.iri_nfrags != 0);
2788 MPASS(ri.iri_len != 0);
2790 /* will advance the cidx on the corresponding free lists */
2791 m = iflib_rxd_pkt_get(rxq, &ri);
2794 if (avail == 0 && budget_left)
2795 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2797 if (__predict_false(m == NULL))
2800 /* imm_pkt: -- cxgb */
2809 /* make sure that we can refill faster than drain */
2810 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2811 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2813 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2815 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2817 while (mh != NULL) {
2820 m->m_nextpkt = NULL;
2821 #ifndef __NO_STRICT_ALIGNMENT
2822 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2825 rx_bytes += m->m_pkthdr.len;
2827 #if defined(INET6) || defined(INET)
2829 if (!lro_possible) {
2830 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2831 if (lro_possible && mf != NULL) {
2832 ifp->if_input(ifp, mf);
2833 DBG_COUNTER_INC(rx_if_input);
2837 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2838 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2839 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2845 ifp->if_input(ifp, m);
2846 DBG_COUNTER_INC(rx_if_input);
2857 ifp->if_input(ifp, mf);
2858 DBG_COUNTER_INC(rx_if_input);
2861 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2862 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2865 * Flush any outstanding LRO work
2867 #if defined(INET6) || defined(INET)
2868 tcp_lro_flush_all(&rxq->ifr_lc);
2872 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2875 ctx->ifc_flags |= IFC_DO_RESET;
2876 iflib_admin_intr_deferred(ctx);
2881 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2882 static inline qidx_t
2883 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2885 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2886 qidx_t minthresh = txq->ift_size / 8;
2887 if (in_use > 4*minthresh)
2888 return (notify_count);
2889 if (in_use > 2*minthresh)
2890 return (notify_count >> 1);
2891 if (in_use > minthresh)
2892 return (notify_count >> 3);
2896 static inline qidx_t
2897 txq_max_rs_deferred(iflib_txq_t txq)
2899 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2900 qidx_t minthresh = txq->ift_size / 8;
2901 if (txq->ift_in_use > 4*minthresh)
2902 return (notify_count);
2903 if (txq->ift_in_use > 2*minthresh)
2904 return (notify_count >> 1);
2905 if (txq->ift_in_use > minthresh)
2906 return (notify_count >> 2);
2910 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2911 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2913 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2914 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2915 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2917 /* forward compatibility for cxgb */
2918 #define FIRST_QSET(ctx) 0
2919 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2920 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2921 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2922 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2924 /* XXX we should be setting this to something other than zero */
2925 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2926 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2927 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2930 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2936 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2937 if (ring || txq->ift_db_pending >= max) {
2938 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2939 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2941 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2942 txq->ift_db_pending = txq->ift_npending = 0;
2950 print_pkt(if_pkt_info_t pi)
2952 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2953 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2954 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2955 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2956 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2957 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2961 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2962 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2963 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2964 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2967 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2969 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2970 struct ether_vlan_header *eh;
2974 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2975 M_WRITABLE(m) == 0) {
2976 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2980 DBG_COUNTER_INC(tx_frees);
2986 * Determine where frame payload starts.
2987 * Jump over vlan headers if already present,
2988 * helpful for QinQ too.
2990 if (__predict_false(m->m_len < sizeof(*eh))) {
2992 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2995 eh = mtod(m, struct ether_vlan_header *);
2996 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2997 pi->ipi_etype = ntohs(eh->evl_proto);
2998 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3000 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3001 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3004 switch (pi->ipi_etype) {
3009 struct ip *ip = NULL;
3010 struct tcphdr *th = NULL;
3013 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3014 if (__predict_false(m->m_len < minthlen)) {
3016 * if this code bloat is causing too much of a hit
3017 * move it to a separate function and mark it noinline
3019 if (m->m_len == pi->ipi_ehdrlen) {
3022 if (n->m_len >= sizeof(*ip)) {
3023 ip = (struct ip *)n->m_data;
3024 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3025 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3028 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3030 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3034 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3036 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3037 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3038 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3041 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3042 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3043 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3045 pi->ipi_ip_hlen = ip->ip_hl << 2;
3046 pi->ipi_ipproto = ip->ip_p;
3047 pi->ipi_flags |= IPI_TX_IPV4;
3049 /* TCP checksum offload may require TCP header length */
3050 if (IS_TX_OFFLOAD4(pi)) {
3051 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3052 if (__predict_false(th == NULL)) {
3054 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3056 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3058 pi->ipi_tcp_hflags = th->th_flags;
3059 pi->ipi_tcp_hlen = th->th_off << 2;
3060 pi->ipi_tcp_seq = th->th_seq;
3063 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3066 * TSO always requires hardware checksum offload.
3068 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3069 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3070 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3071 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3072 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3074 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3078 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3085 case ETHERTYPE_IPV6:
3087 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3089 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3091 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3093 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3096 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3098 /* XXX-BZ this will go badly in case of ext hdrs. */
3099 pi->ipi_ipproto = ip6->ip6_nxt;
3100 pi->ipi_flags |= IPI_TX_IPV6;
3102 /* TCP checksum offload may require TCP header length */
3103 if (IS_TX_OFFLOAD6(pi)) {
3104 if (pi->ipi_ipproto == IPPROTO_TCP) {
3105 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3107 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3110 pi->ipi_tcp_hflags = th->th_flags;
3111 pi->ipi_tcp_hlen = th->th_off << 2;
3112 pi->ipi_tcp_seq = th->th_seq;
3115 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3118 * TSO always requires hardware checksum offload.
3120 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3121 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3122 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3129 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3130 pi->ipi_ip_hlen = 0;
3139 * If dodgy hardware rejects the scatter gather chain we've handed it
3140 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3143 static __noinline struct mbuf *
3144 iflib_remove_mbuf(iflib_txq_t txq)
3147 struct mbuf *m, **ifsd_m;
3149 ifsd_m = txq->ift_sds.ifsd_m;
3150 ntxd = txq->ift_size;
3151 pidx = txq->ift_pidx & (ntxd - 1);
3152 ifsd_m = txq->ift_sds.ifsd_m;
3154 ifsd_m[pidx] = NULL;
3155 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3156 if (txq->ift_sds.ifsd_tso_map != NULL)
3157 bus_dmamap_unload(txq->ift_tso_buf_tag,
3158 txq->ift_sds.ifsd_tso_map[pidx]);
3160 txq->ift_dequeued++;
3165 static inline caddr_t
3166 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3170 caddr_t start, end, cur, next;
3172 ntxd = txq->ift_size;
3173 size = txq->ift_txd_size[qid];
3174 start = txq->ift_ifdi[qid].idi_vaddr;
3176 if (__predict_false(size == 0))
3178 cur = start + size*cidx;
3179 end = start + size*ntxd;
3180 next = CACHE_PTR_NEXT(cur);
3181 return (next < end ? next : start);
3185 * Pad an mbuf to ensure a minimum ethernet frame size.
3186 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3188 static __noinline int
3189 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3192 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3193 * and ARP message is the smallest common payload I can think of
3195 static char pad[18]; /* just zeros */
3197 struct mbuf *new_head;
3199 if (!M_WRITABLE(*m_head)) {
3200 new_head = m_dup(*m_head, M_NOWAIT);
3201 if (new_head == NULL) {
3203 device_printf(dev, "cannot pad short frame, m_dup() failed");
3204 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3205 DBG_COUNTER_INC(tx_frees);
3212 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3213 n > 0; n -= sizeof(pad))
3214 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3219 device_printf(dev, "cannot pad short frame\n");
3220 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3221 DBG_COUNTER_INC(tx_frees);
3229 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3232 if_shared_ctx_t sctx;
3233 if_softc_ctx_t scctx;
3234 bus_dma_tag_t buf_tag;
3235 bus_dma_segment_t *segs;
3236 struct mbuf *m_head, **ifsd_m;
3239 struct if_pkt_info pi;
3241 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3244 sctx = ctx->ifc_sctx;
3245 scctx = &ctx->ifc_softc_ctx;
3246 segs = txq->ift_segs;
3247 ntxd = txq->ift_size;
3252 * If we're doing TSO the next descriptor to clean may be quite far ahead
3254 cidx = txq->ift_cidx;
3255 pidx = txq->ift_pidx;
3256 if (ctx->ifc_flags & IFC_PREFETCH) {
3257 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3258 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3259 next_txd = calc_next_txd(txq, cidx, 0);
3263 /* prefetch the next cache line of mbuf pointers and flags */
3264 prefetch(&txq->ift_sds.ifsd_m[next]);
3265 prefetch(&txq->ift_sds.ifsd_map[next]);
3266 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3268 map = txq->ift_sds.ifsd_map[pidx];
3269 ifsd_m = txq->ift_sds.ifsd_m;
3271 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3272 buf_tag = txq->ift_tso_buf_tag;
3273 max_segs = scctx->isc_tx_tso_segments_max;
3274 map = txq->ift_sds.ifsd_tso_map[pidx];
3275 MPASS(buf_tag != NULL);
3276 MPASS(max_segs > 0);
3278 buf_tag = txq->ift_buf_tag;
3279 max_segs = scctx->isc_tx_nsegments;
3280 map = txq->ift_sds.ifsd_map[pidx];
3282 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3283 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3284 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3286 DBG_COUNTER_INC(encap_txd_encap_fail);
3293 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3295 pi.ipi_qsidx = txq->ift_id;
3296 pi.ipi_len = m_head->m_pkthdr.len;
3297 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3298 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3300 /* deliberate bitwise OR to make one condition */
3301 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3302 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3303 DBG_COUNTER_INC(encap_txd_encap_fail);
3310 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3313 if (__predict_false(err)) {
3316 /* try collapse once and defrag once */
3318 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3319 /* try defrag if collapsing fails */
3324 txq->ift_mbuf_defrag++;
3325 m_head = m_defrag(*m_headp, M_NOWAIT);
3328 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3329 * failed to map an mbuf that was run through m_defrag
3332 if (__predict_false(m_head == NULL || remap > 1))
3339 txq->ift_no_tx_dma_setup++;
3342 txq->ift_no_tx_dma_setup++;
3344 DBG_COUNTER_INC(tx_frees);
3348 txq->ift_map_failed++;
3349 DBG_COUNTER_INC(encap_load_mbuf_fail);
3350 DBG_COUNTER_INC(encap_txd_encap_fail);
3353 ifsd_m[pidx] = m_head;
3355 * XXX assumes a 1 to 1 relationship between segments and
3356 * descriptors - this does not hold true on all drivers, e.g.
3359 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3360 txq->ift_no_desc_avail++;
3361 bus_dmamap_unload(buf_tag, map);
3362 DBG_COUNTER_INC(encap_txq_avail_fail);
3363 DBG_COUNTER_INC(encap_txd_encap_fail);
3364 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3365 GROUPTASK_ENQUEUE(&txq->ift_task);
3369 * On Intel cards we can greatly reduce the number of TX interrupts
3370 * we see by only setting report status on every Nth descriptor.
3371 * However, this also means that the driver will need to keep track
3372 * of the descriptors that RS was set on to check them for the DD bit.
3374 txq->ift_rs_pending += nsegs + 1;
3375 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3376 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3377 pi.ipi_flags |= IPI_TX_INTR;
3378 txq->ift_rs_pending = 0;
3382 pi.ipi_nsegs = nsegs;
3384 MPASS(pidx >= 0 && pidx < txq->ift_size);
3388 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3389 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3390 DBG_COUNTER_INC(tx_encap);
3391 MPASS(pi.ipi_new_pidx < txq->ift_size);
3393 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3394 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3395 ndesc += txq->ift_size;
3399 * drivers can need as many as
3402 MPASS(ndesc <= pi.ipi_nsegs + 2);
3403 MPASS(pi.ipi_new_pidx != pidx);
3405 txq->ift_in_use += ndesc;
3408 * We update the last software descriptor again here because there may
3409 * be a sentinel and/or there may be more mbufs than segments
3411 txq->ift_pidx = pi.ipi_new_pidx;
3412 txq->ift_npending += pi.ipi_ndescs;
3414 *m_headp = m_head = iflib_remove_mbuf(txq);
3416 txq->ift_txd_encap_efbig++;
3425 * err can't possibly be non-zero here, so we don't neet to test it
3426 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3431 txq->ift_mbuf_defrag_failed++;
3432 txq->ift_map_failed++;
3434 DBG_COUNTER_INC(tx_frees);
3436 DBG_COUNTER_INC(encap_txd_encap_fail);
3441 iflib_tx_desc_free(iflib_txq_t txq, int n)
3443 uint32_t qsize, cidx, mask, gen;
3444 struct mbuf *m, **ifsd_m;
3447 cidx = txq->ift_cidx;
3449 qsize = txq->ift_size;
3451 ifsd_m = txq->ift_sds.ifsd_m;
3452 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3456 prefetch(ifsd_m[(cidx + 3) & mask]);
3457 prefetch(ifsd_m[(cidx + 4) & mask]);
3459 if ((m = ifsd_m[cidx]) != NULL) {
3460 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3461 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3462 bus_dmamap_sync(txq->ift_tso_buf_tag,
3463 txq->ift_sds.ifsd_tso_map[cidx],
3464 BUS_DMASYNC_POSTWRITE);
3465 bus_dmamap_unload(txq->ift_tso_buf_tag,
3466 txq->ift_sds.ifsd_tso_map[cidx]);
3468 bus_dmamap_sync(txq->ift_buf_tag,
3469 txq->ift_sds.ifsd_map[cidx],
3470 BUS_DMASYNC_POSTWRITE);
3471 bus_dmamap_unload(txq->ift_buf_tag,
3472 txq->ift_sds.ifsd_map[cidx]);
3474 /* XXX we don't support any drivers that batch packets yet */
3475 MPASS(m->m_nextpkt == NULL);
3477 ifsd_m[cidx] = NULL;
3479 txq->ift_dequeued++;
3481 DBG_COUNTER_INC(tx_frees);
3483 if (__predict_false(++cidx == qsize)) {
3488 txq->ift_cidx = cidx;
3493 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3496 if_ctx_t ctx = txq->ift_ctx;
3498 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3499 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3502 * Need a rate-limiting check so that this isn't called every time
3504 iflib_tx_credits_update(ctx, txq);
3505 reclaim = DESC_RECLAIMABLE(txq);
3507 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3509 if (iflib_verbose_debug) {
3510 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3511 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3518 iflib_tx_desc_free(txq, reclaim);
3519 txq->ift_cleaned += reclaim;
3520 txq->ift_in_use -= reclaim;
3525 static struct mbuf **
3526 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3529 struct mbuf **items;
3532 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3533 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3535 prefetch(items[(cidx + offset) & (size-1)]);
3536 if (remaining > 1) {
3537 prefetch2cachelines(&items[next]);
3538 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3539 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3540 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3542 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3546 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3549 ifmp_ring_check_drainage(txq->ift_br, budget);
3553 iflib_txq_can_drain(struct ifmp_ring *r)
3555 iflib_txq_t txq = r->cookie;
3556 if_ctx_t ctx = txq->ift_ctx;
3558 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3560 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3561 BUS_DMASYNC_POSTREAD);
3562 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3567 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3569 iflib_txq_t txq = r->cookie;
3570 if_ctx_t ctx = txq->ift_ctx;
3571 struct ifnet *ifp = ctx->ifc_ifp;
3572 struct mbuf **mp, *m;
3573 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3574 int reclaimed, err, in_use_prev, desc_used;
3575 bool do_prefetch, ring, rang;
3577 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3578 !LINK_ACTIVE(ctx))) {
3579 DBG_COUNTER_INC(txq_drain_notready);
3582 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3583 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3584 avail = IDXDIFF(pidx, cidx, r->size);
3585 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3586 DBG_COUNTER_INC(txq_drain_flushing);
3587 for (i = 0; i < avail; i++) {
3588 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3589 m_free(r->items[(cidx + i) & (r->size-1)]);
3590 r->items[(cidx + i) & (r->size-1)] = NULL;
3595 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3596 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3598 callout_stop(&txq->ift_timer);
3599 CALLOUT_UNLOCK(txq);
3600 DBG_COUNTER_INC(txq_drain_oactive);
3604 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3605 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3606 count = MIN(avail, TX_BATCH_SIZE);
3608 if (iflib_verbose_debug)
3609 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3610 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3612 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3613 avail = TXQ_AVAIL(txq);
3615 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3616 int rem = do_prefetch ? count - i : 0;
3618 mp = _ring_peek_one(r, cidx, i, rem);
3619 MPASS(mp != NULL && *mp != NULL);
3620 if (__predict_false(*mp == (struct mbuf *)txq)) {
3625 in_use_prev = txq->ift_in_use;
3626 err = iflib_encap(txq, mp);
3627 if (__predict_false(err)) {
3628 /* no room - bail out */
3632 /* we can't send this packet - skip it */
3638 DBG_COUNTER_INC(tx_sent);
3639 bytes_sent += m->m_pkthdr.len;
3640 mcast_sent += !!(m->m_flags & M_MCAST);
3641 avail = TXQ_AVAIL(txq);
3643 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3644 desc_used += (txq->ift_in_use - in_use_prev);
3645 ETHER_BPF_MTAP(ifp, m);
3646 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3648 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3651 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3652 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3653 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3654 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3655 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3657 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3659 if (iflib_verbose_debug)
3660 printf("consumed=%d\n", consumed);
3666 iflib_txq_drain_always(struct ifmp_ring *r)
3672 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3680 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3682 callout_stop(&txq->ift_timer);
3683 CALLOUT_UNLOCK(txq);
3685 avail = IDXDIFF(pidx, cidx, r->size);
3686 for (i = 0; i < avail; i++) {
3687 mp = _ring_peek_one(r, cidx, i, avail - i);
3688 if (__predict_false(*mp == (struct mbuf *)txq))
3691 DBG_COUNTER_INC(tx_frees);
3693 MPASS(ifmp_ring_is_stalled(r) == 0);
3698 iflib_ifmp_purge(iflib_txq_t txq)
3700 struct ifmp_ring *r;
3703 r->drain = iflib_txq_drain_free;
3704 r->can_drain = iflib_txq_drain_always;
3706 ifmp_ring_check_drainage(r, r->size);
3708 r->drain = iflib_txq_drain;
3709 r->can_drain = iflib_txq_can_drain;
3713 _task_fn_tx(void *context)
3715 iflib_txq_t txq = context;
3716 if_ctx_t ctx = txq->ift_ctx;
3717 #if defined(ALTQ) || defined(DEV_NETMAP)
3718 if_t ifp = ctx->ifc_ifp;
3720 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3722 #ifdef IFLIB_DIAGNOSTICS
3723 txq->ift_cpu_exec_count[curcpu]++;
3725 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3728 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3729 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3730 BUS_DMASYNC_POSTREAD);
3731 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3732 netmap_tx_irq(ifp, txq->ift_id);
3733 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3738 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3739 iflib_altq_if_start(ifp);
3741 if (txq->ift_db_pending)
3742 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3744 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3746 * When abdicating, we always need to check drainage, not just when we don't enqueue
3749 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3750 if (ctx->ifc_flags & IFC_LEGACY)
3751 IFDI_INTR_ENABLE(ctx);
3756 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3757 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3762 _task_fn_rx(void *context)
3764 iflib_rxq_t rxq = context;
3765 if_ctx_t ctx = rxq->ifr_ctx;
3769 #ifdef IFLIB_DIAGNOSTICS
3770 rxq->ifr_cpu_exec_count[curcpu]++;
3772 DBG_COUNTER_INC(task_fn_rxs);
3773 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3777 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3779 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3784 budget = ctx->ifc_sysctl_rx_budget;
3786 budget = 16; /* XXX */
3787 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3788 if (ctx->ifc_flags & IFC_LEGACY)
3789 IFDI_INTR_ENABLE(ctx);
3794 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3795 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3796 DBG_COUNTER_INC(rx_intr_enables);
3799 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3802 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3806 _task_fn_admin(void *context)
3808 if_ctx_t ctx = context;
3809 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3812 bool oactive, running, do_reset, do_watchdog, in_detach;
3813 uint32_t reset_on = hz / 2;
3816 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3817 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3818 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3819 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3820 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3821 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3824 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3830 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3832 callout_stop(&txq->ift_timer);
3833 CALLOUT_UNLOCK(txq);
3836 ctx->ifc_watchdog_events++;
3837 IFDI_WATCHDOG_RESET(ctx);
3839 IFDI_UPDATE_ADMIN_STATUS(ctx);
3840 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3843 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3844 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3846 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3848 IFDI_LINK_INTR_ENABLE(ctx);
3850 iflib_if_init_locked(ctx);
3853 if (LINK_ACTIVE(ctx) == 0)
3855 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3856 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3861 _task_fn_iov(void *context)
3863 if_ctx_t ctx = context;
3865 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3866 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3870 IFDI_VFLR_HANDLE(ctx);
3875 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3878 if_int_delay_info_t info;
3881 info = (if_int_delay_info_t)arg1;
3882 ctx = info->iidi_ctx;
3883 info->iidi_req = req;
3884 info->iidi_oidp = oidp;
3886 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3891 /*********************************************************************
3895 **********************************************************************/
3898 iflib_if_init_locked(if_ctx_t ctx)
3901 iflib_init_locked(ctx);
3906 iflib_if_init(void *arg)
3911 iflib_if_init_locked(ctx);
3916 iflib_if_transmit(if_t ifp, struct mbuf *m)
3918 if_ctx_t ctx = if_getsoftc(ifp);
3922 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3924 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3925 DBG_COUNTER_INC(tx_frees);
3930 MPASS(m->m_nextpkt == NULL);
3931 /* ALTQ-enabled interfaces always use queue 0. */
3933 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3934 qidx = QIDX(ctx, m);
3936 * XXX calculate buf_ring based on flowid (divvy up bits?)
3938 txq = &ctx->ifc_txqs[qidx];
3940 #ifdef DRIVER_BACKPRESSURE
3941 if (txq->ift_closed) {
3943 next = m->m_nextpkt;
3944 m->m_nextpkt = NULL;
3946 DBG_COUNTER_INC(tx_frees);
3958 next = next->m_nextpkt;
3959 } while (next != NULL);
3961 if (count > nitems(marr))
3962 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3963 /* XXX check nextpkt */
3965 /* XXX simplify for now */
3966 DBG_COUNTER_INC(tx_frees);
3969 for (next = m, i = 0; next != NULL; i++) {
3971 next = next->m_nextpkt;
3972 mp[i]->m_nextpkt = NULL;
3975 DBG_COUNTER_INC(tx_seen);
3976 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3979 GROUPTASK_ENQUEUE(&txq->ift_task);
3982 GROUPTASK_ENQUEUE(&txq->ift_task);
3983 /* support forthcoming later */
3984 #ifdef DRIVER_BACKPRESSURE
3985 txq->ift_closed = TRUE;
3987 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3989 DBG_COUNTER_INC(tx_frees);
3997 * The overall approach to integrating iflib with ALTQ is to continue to use
3998 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3999 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4000 * is redundant/unnecessary, but doing so minimizes the amount of
4001 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4002 * redundantly queueing to an intermediate mp_ring is swamped by the
4003 * performance limitations inherent in using ALTQ.
4005 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4006 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4007 * given interface. If ALTQ is enabled for an interface, then all
4008 * transmitted packets for that interface will be submitted to the ALTQ
4009 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4010 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4011 * update stats that the iflib machinery handles, and which is sensitve to
4012 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4013 * will be installed as the start routine for use by ALTQ facilities that
4014 * need to trigger queue drains on a scheduled basis.
4018 iflib_altq_if_start(if_t ifp)
4020 struct ifaltq *ifq = &ifp->if_snd;
4024 IFQ_DEQUEUE_NOLOCK(ifq, m);
4026 iflib_if_transmit(ifp, m);
4027 IFQ_DEQUEUE_NOLOCK(ifq, m);
4033 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4037 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4038 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4040 iflib_altq_if_start(ifp);
4042 err = iflib_if_transmit(ifp, m);
4049 iflib_if_qflush(if_t ifp)
4051 if_ctx_t ctx = if_getsoftc(ifp);
4052 iflib_txq_t txq = ctx->ifc_txqs;
4056 ctx->ifc_flags |= IFC_QFLUSH;
4058 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4059 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4060 iflib_txq_check_drain(txq, 0);
4062 ctx->ifc_flags &= ~IFC_QFLUSH;
4066 * When ALTQ is enabled, this will also take care of purging the
4073 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4074 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4075 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4076 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4079 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4081 if_ctx_t ctx = if_getsoftc(ifp);
4082 struct ifreq *ifr = (struct ifreq *)data;
4083 #if defined(INET) || defined(INET6)
4084 struct ifaddr *ifa = (struct ifaddr *)data;
4086 bool avoid_reset = FALSE;
4087 int err = 0, reinit = 0, bits;
4092 if (ifa->ifa_addr->sa_family == AF_INET)
4096 if (ifa->ifa_addr->sa_family == AF_INET6)
4100 ** Calling init results in link renegotiation,
4101 ** so we avoid doing it when possible.
4104 if_setflagbits(ifp, IFF_UP,0);
4105 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4108 if (!(if_getflags(ifp) & IFF_NOARP))
4109 arp_ifinit(ifp, ifa);
4112 err = ether_ioctl(ifp, command, data);
4116 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4120 bits = if_getdrvflags(ifp);
4121 /* stop the driver and free any clusters before proceeding */
4124 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4126 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4127 ctx->ifc_flags |= IFC_MULTISEG;
4129 ctx->ifc_flags &= ~IFC_MULTISEG;
4131 err = if_setmtu(ifp, ifr->ifr_mtu);
4133 iflib_init_locked(ctx);
4135 if_setdrvflags(ifp, bits);
4141 if (if_getflags(ifp) & IFF_UP) {
4142 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4143 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4144 (IFF_PROMISC | IFF_ALLMULTI)) {
4145 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4149 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4152 ctx->ifc_if_flags = if_getflags(ifp);
4157 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4159 IFDI_INTR_DISABLE(ctx);
4160 IFDI_MULTI_SET(ctx);
4161 IFDI_INTR_ENABLE(ctx);
4167 IFDI_MEDIA_SET(ctx);
4172 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4176 struct ifi2creq i2c;
4178 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4181 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4185 if (i2c.len > sizeof(i2c.data)) {
4190 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4191 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4197 int mask, setmask, oldmask;
4199 oldmask = if_getcapenable(ifp);
4200 mask = ifr->ifr_reqcap ^ oldmask;
4201 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4204 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4206 setmask |= (mask & IFCAP_FLAGS);
4207 setmask |= (mask & IFCAP_WOL);
4210 * If any RX csum has changed, change all the ones that
4211 * are supported by the driver.
4213 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4214 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4215 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4219 * want to ensure that traffic has stopped before we change any of the flags
4223 bits = if_getdrvflags(ifp);
4224 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4227 if_togglecapenable(ifp, setmask);
4229 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4230 iflib_init_locked(ctx);
4232 if_setdrvflags(ifp, bits);
4239 case SIOCGPRIVATE_0:
4243 err = IFDI_PRIV_IOCTL(ctx, command, data);
4247 err = ether_ioctl(ifp, command, data);
4256 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4258 if_ctx_t ctx = if_getsoftc(ifp);
4260 return (IFDI_GET_COUNTER(ctx, cnt));
4263 /*********************************************************************
4265 * OTHER FUNCTIONS EXPORTED TO THE STACK
4267 **********************************************************************/
4270 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4272 if_ctx_t ctx = if_getsoftc(ifp);
4274 if ((void *)ctx != arg)
4277 if ((vtag == 0) || (vtag > 4095))
4281 IFDI_VLAN_REGISTER(ctx, vtag);
4282 /* Re-init to load the changes */
4283 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4284 iflib_if_init_locked(ctx);
4289 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4291 if_ctx_t ctx = if_getsoftc(ifp);
4293 if ((void *)ctx != arg)
4296 if ((vtag == 0) || (vtag > 4095))
4300 IFDI_VLAN_UNREGISTER(ctx, vtag);
4301 /* Re-init to load the changes */
4302 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4303 iflib_if_init_locked(ctx);
4308 iflib_led_func(void *arg, int onoff)
4313 IFDI_LED_FUNC(ctx, onoff);
4317 /*********************************************************************
4319 * BUS FUNCTION DEFINITIONS
4321 **********************************************************************/
4324 iflib_device_probe(device_t dev)
4326 pci_vendor_info_t *ent;
4328 uint16_t pci_vendor_id, pci_device_id;
4329 uint16_t pci_subvendor_id, pci_subdevice_id;
4330 uint16_t pci_rev_id;
4331 if_shared_ctx_t sctx;
4333 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4336 pci_vendor_id = pci_get_vendor(dev);
4337 pci_device_id = pci_get_device(dev);
4338 pci_subvendor_id = pci_get_subvendor(dev);
4339 pci_subdevice_id = pci_get_subdevice(dev);
4340 pci_rev_id = pci_get_revid(dev);
4341 if (sctx->isc_parse_devinfo != NULL)
4342 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4344 ent = sctx->isc_vendor_info;
4345 while (ent->pvi_vendor_id != 0) {
4346 if (pci_vendor_id != ent->pvi_vendor_id) {
4350 if ((pci_device_id == ent->pvi_device_id) &&
4351 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4352 (ent->pvi_subvendor_id == 0)) &&
4353 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4354 (ent->pvi_subdevice_id == 0)) &&
4355 ((pci_rev_id == ent->pvi_rev_id) ||
4356 (ent->pvi_rev_id == 0))) {
4358 device_set_desc_copy(dev, ent->pvi_name);
4359 /* this needs to be changed to zero if the bus probing code
4360 * ever stops re-probing on best match because the sctx
4361 * may have its values over written by register calls
4362 * in subsequent probes
4364 return (BUS_PROBE_DEFAULT);
4372 iflib_reset_qvalues(if_ctx_t ctx)
4374 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4375 if_shared_ctx_t sctx = ctx->ifc_sctx;
4376 device_t dev = ctx->ifc_dev;
4379 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4380 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4382 * XXX sanity check that ntxd & nrxd are a power of 2
4384 if (ctx->ifc_sysctl_ntxqs != 0)
4385 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4386 if (ctx->ifc_sysctl_nrxqs != 0)
4387 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4389 for (i = 0; i < sctx->isc_ntxqs; i++) {
4390 if (ctx->ifc_sysctl_ntxds[i] != 0)
4391 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4393 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4396 for (i = 0; i < sctx->isc_nrxqs; i++) {
4397 if (ctx->ifc_sysctl_nrxds[i] != 0)
4398 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4400 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4403 for (i = 0; i < sctx->isc_nrxqs; i++) {
4404 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4405 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4406 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4407 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4409 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4410 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4411 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4412 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4416 for (i = 0; i < sctx->isc_ntxqs; i++) {
4417 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4418 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4419 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4420 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4422 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4423 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4424 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4425 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4431 iflib_add_pfil(if_ctx_t ctx)
4433 struct pfil_head *pfil;
4434 struct pfil_head_args pa;
4438 pa.pa_version = PFIL_VERSION;
4439 pa.pa_flags = PFIL_IN;
4440 pa.pa_type = PFIL_TYPE_ETHERNET;
4441 pa.pa_headname = ctx->ifc_ifp->if_xname;
4442 pfil = pfil_head_register(&pa);
4444 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4450 iflib_rem_pfil(if_ctx_t ctx)
4452 struct pfil_head *pfil;
4456 rxq = ctx->ifc_rxqs;
4458 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4461 pfil_head_unregister(pfil);
4465 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4470 if_softc_ctx_t scctx;
4476 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4479 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4480 device_set_softc(dev, ctx);
4481 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4484 ctx->ifc_sctx = sctx;
4486 ctx->ifc_softc = sc;
4488 if ((err = iflib_register(ctx)) != 0) {
4489 device_printf(dev, "iflib_register failed %d\n", err);
4492 iflib_add_device_sysctl_pre(ctx);
4494 scctx = &ctx->ifc_softc_ctx;
4497 iflib_reset_qvalues(ctx);
4499 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4500 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4503 _iflib_pre_assert(scctx);
4504 ctx->ifc_txrx = *scctx->isc_txrx;
4507 MPASS(scctx->isc_capabilities);
4508 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4509 MPASS(scctx->isc_tx_csum_flags);
4512 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4513 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4515 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4516 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4517 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4518 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4520 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4521 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4523 /* XXX change for per-queue sizes */
4524 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4525 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4526 for (i = 0; i < sctx->isc_nrxqs; i++) {
4527 if (!powerof2(scctx->isc_nrxd[i])) {
4528 /* round down instead? */
4529 device_printf(dev, "# rx descriptors must be a power of 2\n");
4531 goto fail_iflib_detach;
4534 for (i = 0; i < sctx->isc_ntxqs; i++) {
4535 if (!powerof2(scctx->isc_ntxd[i])) {
4537 "# tx descriptors must be a power of 2");
4539 goto fail_iflib_detach;
4543 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4544 MAX_SINGLE_PACKET_FRACTION)
4545 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4546 MAX_SINGLE_PACKET_FRACTION);
4547 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4548 MAX_SINGLE_PACKET_FRACTION)
4549 scctx->isc_tx_tso_segments_max = max(1,
4550 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4552 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4553 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4555 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4558 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4561 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4562 * into account. In the worst case, each of these calls will
4563 * add another mbuf and, thus, the requirement for another DMA
4564 * segment. So for best performance, it doesn't make sense to
4565 * advertize a maximum of TSO segments that typically will
4566 * require defragmentation in iflib_encap().
4568 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4569 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4571 if (scctx->isc_rss_table_size == 0)
4572 scctx->isc_rss_table_size = 64;
4573 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4575 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4576 /* XXX format name */
4577 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4578 NULL, NULL, "admin");
4580 /* Set up cpu set. If it fails, use the set of all CPUs. */
4581 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4582 device_printf(dev, "Unable to fetch CPU list\n");
4583 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4585 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4588 ** Now set up MSI or MSI-X, should return us the number of supported
4589 ** vectors (will be 1 for a legacy interrupt and MSI).
4591 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4592 msix = scctx->isc_vectors;
4593 } else if (scctx->isc_msix_bar != 0)
4595 * The simple fact that isc_msix_bar is not 0 does not mean we
4596 * we have a good value there that is known to work.
4598 msix = iflib_msix_init(ctx);
4600 scctx->isc_vectors = 1;
4601 scctx->isc_ntxqsets = 1;
4602 scctx->isc_nrxqsets = 1;
4603 scctx->isc_intr = IFLIB_INTR_LEGACY;
4606 /* Get memory for the station queues */
4607 if ((err = iflib_queues_alloc(ctx))) {
4608 device_printf(dev, "Unable to allocate queue memory\n");
4609 goto fail_intr_free;
4612 if ((err = iflib_qset_structures_setup(ctx)))
4616 * Group taskqueues aren't properly set up until SMP is started,
4617 * so we disable interrupts until we can handle them post
4620 * XXX: disabling interrupts doesn't actually work, at least for
4621 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4622 * we do null handling and depend on this not causing too large an
4625 IFDI_INTR_DISABLE(ctx);
4626 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4627 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4632 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4636 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4637 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4642 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4644 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4645 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4650 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4651 * This must appear after the call to ether_ifattach() because
4652 * ether_ifattach() sets if_hdrlen to the default value.
4654 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4655 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4657 if ((err = iflib_netmap_attach(ctx))) {
4658 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4663 NETDUMP_SET(ctx->ifc_ifp, iflib);
4665 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4666 iflib_add_device_sysctl_post(ctx);
4667 iflib_add_pfil(ctx);
4668 ctx->ifc_flags |= IFC_INIT_DONE;
4673 ether_ifdetach(ctx->ifc_ifp);
4675 iflib_free_intr_mem(ctx);
4677 iflib_tx_structures_free(ctx);
4678 iflib_rx_structures_free(ctx);
4684 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4685 free(ctx->ifc_softc, M_IFLIB);
4691 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4692 struct iflib_cloneattach_ctx *clctx)
4697 if_softc_ctx_t scctx;
4703 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4704 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4705 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4706 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4707 ctx->ifc_flags |= IFC_PSEUDO;
4709 ctx->ifc_sctx = sctx;
4710 ctx->ifc_softc = sc;
4713 if ((err = iflib_register(ctx)) != 0) {
4714 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4717 iflib_add_device_sysctl_pre(ctx);
4719 scctx = &ctx->ifc_softc_ctx;
4723 * XXX sanity check that ntxd & nrxd are a power of 2
4725 iflib_reset_qvalues(ctx);
4727 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4728 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4731 if (sctx->isc_flags & IFLIB_GEN_MAC)
4732 ether_gen_addr(ifp, &ctx->ifc_mac);
4733 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4734 clctx->cc_params)) != 0) {
4735 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4738 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4739 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4740 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4743 MPASS(scctx->isc_capabilities);
4744 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4745 MPASS(scctx->isc_tx_csum_flags);
4748 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4749 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4751 ifp->if_flags |= IFF_NOGROUP;
4752 if (sctx->isc_flags & IFLIB_PSEUDO) {
4753 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4755 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4756 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4762 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4763 * This must appear after the call to ether_ifattach() because
4764 * ether_ifattach() sets if_hdrlen to the default value.
4766 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4767 if_setifheaderlen(ifp,
4768 sizeof(struct ether_vlan_header));
4770 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4771 iflib_add_device_sysctl_post(ctx);
4772 ctx->ifc_flags |= IFC_INIT_DONE;
4775 _iflib_pre_assert(scctx);
4776 ctx->ifc_txrx = *scctx->isc_txrx;
4778 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4779 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4780 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4781 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4783 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4784 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4786 /* XXX change for per-queue sizes */
4787 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4788 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4789 for (i = 0; i < sctx->isc_nrxqs; i++) {
4790 if (!powerof2(scctx->isc_nrxd[i])) {
4791 /* round down instead? */
4792 device_printf(dev, "# rx descriptors must be a power of 2\n");
4794 goto fail_iflib_detach;
4797 for (i = 0; i < sctx->isc_ntxqs; i++) {
4798 if (!powerof2(scctx->isc_ntxd[i])) {
4800 "# tx descriptors must be a power of 2");
4802 goto fail_iflib_detach;
4806 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4807 MAX_SINGLE_PACKET_FRACTION)
4808 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4809 MAX_SINGLE_PACKET_FRACTION);
4810 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4811 MAX_SINGLE_PACKET_FRACTION)
4812 scctx->isc_tx_tso_segments_max = max(1,
4813 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4815 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4816 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4818 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4821 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4824 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4825 * into account. In the worst case, each of these calls will
4826 * add another mbuf and, thus, the requirement for another DMA
4827 * segment. So for best performance, it doesn't make sense to
4828 * advertize a maximum of TSO segments that typically will
4829 * require defragmentation in iflib_encap().
4831 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4832 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4834 if (scctx->isc_rss_table_size == 0)
4835 scctx->isc_rss_table_size = 64;
4836 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4838 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4839 /* XXX format name */
4840 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4841 NULL, NULL, "admin");
4843 /* XXX --- can support > 1 -- but keep it simple for now */
4844 scctx->isc_intr = IFLIB_INTR_LEGACY;
4846 /* Get memory for the station queues */
4847 if ((err = iflib_queues_alloc(ctx))) {
4848 device_printf(dev, "Unable to allocate queue memory\n");
4849 goto fail_iflib_detach;
4852 if ((err = iflib_qset_structures_setup(ctx))) {
4853 device_printf(dev, "qset structure setup failed %d\n", err);
4858 * XXX What if anything do we want to do about interrupts?
4860 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4861 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4862 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4867 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4868 * This must appear after the call to ether_ifattach() because
4869 * ether_ifattach() sets if_hdrlen to the default value.
4871 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4872 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4874 /* XXX handle more than one queue */
4875 for (i = 0; i < scctx->isc_nrxqsets; i++)
4876 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4880 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4881 iflib_add_device_sysctl_post(ctx);
4882 ctx->ifc_flags |= IFC_INIT_DONE;
4886 ether_ifdetach(ctx->ifc_ifp);
4888 iflib_tx_structures_free(ctx);
4889 iflib_rx_structures_free(ctx);
4895 free(ctx->ifc_softc, M_IFLIB);
4901 iflib_pseudo_deregister(if_ctx_t ctx)
4903 if_t ifp = ctx->ifc_ifp;
4907 struct taskqgroup *tqg;
4910 /* Unregister VLAN events */
4911 if (ctx->ifc_vlan_attach_event != NULL)
4912 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4913 if (ctx->ifc_vlan_detach_event != NULL)
4914 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4916 ether_ifdetach(ifp);
4917 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4918 CTX_LOCK_DESTROY(ctx);
4919 /* XXX drain any dependent tasks */
4920 tqg = qgroup_if_io_tqg;
4921 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4922 callout_drain(&txq->ift_timer);
4923 if (txq->ift_task.gt_uniq != NULL)
4924 taskqgroup_detach(tqg, &txq->ift_task);
4926 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4927 if (rxq->ifr_task.gt_uniq != NULL)
4928 taskqgroup_detach(tqg, &rxq->ifr_task);
4930 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4931 free(fl->ifl_rx_bitmap, M_IFLIB);
4933 tqg = qgroup_if_config_tqg;
4934 if (ctx->ifc_admin_task.gt_uniq != NULL)
4935 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4936 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4937 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4941 iflib_tx_structures_free(ctx);
4942 iflib_rx_structures_free(ctx);
4943 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4944 free(ctx->ifc_softc, M_IFLIB);
4950 iflib_device_attach(device_t dev)
4953 if_shared_ctx_t sctx;
4955 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4958 pci_enable_busmaster(dev);
4960 return (iflib_device_register(dev, NULL, sctx, &ctx));
4964 iflib_device_deregister(if_ctx_t ctx)
4966 if_t ifp = ctx->ifc_ifp;
4969 device_t dev = ctx->ifc_dev;
4971 struct taskqgroup *tqg;
4974 /* Make sure VLANS are not using driver */
4975 if (if_vlantrunkinuse(ifp)) {
4976 device_printf(dev, "Vlan in use, detach first\n");
4980 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
4981 device_printf(dev, "SR-IOV in use; detach first.\n");
4987 ctx->ifc_flags |= IFC_IN_DETACH;
4994 /* Unregister VLAN events */
4995 if (ctx->ifc_vlan_attach_event != NULL)
4996 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4997 if (ctx->ifc_vlan_detach_event != NULL)
4998 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5000 iflib_netmap_detach(ifp);
5001 ether_ifdetach(ifp);
5002 iflib_rem_pfil(ctx);
5003 if (ctx->ifc_led_dev != NULL)
5004 led_destroy(ctx->ifc_led_dev);
5005 /* XXX drain any dependent tasks */
5006 tqg = qgroup_if_io_tqg;
5007 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5008 callout_drain(&txq->ift_timer);
5009 if (txq->ift_task.gt_uniq != NULL)
5010 taskqgroup_detach(tqg, &txq->ift_task);
5012 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5013 if (rxq->ifr_task.gt_uniq != NULL)
5014 taskqgroup_detach(tqg, &rxq->ifr_task);
5016 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5017 free(fl->ifl_rx_bitmap, M_IFLIB);
5019 tqg = qgroup_if_config_tqg;
5020 if (ctx->ifc_admin_task.gt_uniq != NULL)
5021 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5022 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5023 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5028 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5029 CTX_LOCK_DESTROY(ctx);
5030 device_set_softc(ctx->ifc_dev, NULL);
5031 iflib_free_intr_mem(ctx);
5033 bus_generic_detach(dev);
5036 iflib_tx_structures_free(ctx);
5037 iflib_rx_structures_free(ctx);
5038 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5039 free(ctx->ifc_softc, M_IFLIB);
5040 STATE_LOCK_DESTROY(ctx);
5046 iflib_free_intr_mem(if_ctx_t ctx)
5049 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5050 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5052 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5053 pci_release_msi(ctx->ifc_dev);
5055 if (ctx->ifc_msix_mem != NULL) {
5056 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5057 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5058 ctx->ifc_msix_mem = NULL;
5063 iflib_device_detach(device_t dev)
5065 if_ctx_t ctx = device_get_softc(dev);
5067 return (iflib_device_deregister(ctx));
5071 iflib_device_suspend(device_t dev)
5073 if_ctx_t ctx = device_get_softc(dev);
5079 return bus_generic_suspend(dev);
5082 iflib_device_shutdown(device_t dev)
5084 if_ctx_t ctx = device_get_softc(dev);
5090 return bus_generic_suspend(dev);
5095 iflib_device_resume(device_t dev)
5097 if_ctx_t ctx = device_get_softc(dev);
5098 iflib_txq_t txq = ctx->ifc_txqs;
5102 iflib_if_init_locked(ctx);
5104 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5105 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5107 return (bus_generic_resume(dev));
5111 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5114 if_ctx_t ctx = device_get_softc(dev);
5117 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5124 iflib_device_iov_uninit(device_t dev)
5126 if_ctx_t ctx = device_get_softc(dev);
5129 IFDI_IOV_UNINIT(ctx);
5134 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5137 if_ctx_t ctx = device_get_softc(dev);
5140 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5146 /*********************************************************************
5148 * MODULE FUNCTION DEFINITIONS
5150 **********************************************************************/
5153 * - Start a fast taskqueue thread for each core
5154 * - Start a taskqueue for control operations
5157 iflib_module_init(void)
5163 iflib_module_event_handler(module_t mod, int what, void *arg)
5169 if ((err = iflib_module_init()) != 0)
5175 return (EOPNOTSUPP);
5181 /*********************************************************************
5183 * PUBLIC FUNCTION DEFINITIONS
5184 * ordered as in iflib.h
5186 **********************************************************************/
5190 _iflib_assert(if_shared_ctx_t sctx)
5192 MPASS(sctx->isc_tx_maxsize);
5193 MPASS(sctx->isc_tx_maxsegsize);
5195 MPASS(sctx->isc_rx_maxsize);
5196 MPASS(sctx->isc_rx_nsegments);
5197 MPASS(sctx->isc_rx_maxsegsize);
5199 MPASS(sctx->isc_nrxd_min[0]);
5200 MPASS(sctx->isc_nrxd_max[0]);
5201 MPASS(sctx->isc_nrxd_default[0]);
5202 MPASS(sctx->isc_ntxd_min[0]);
5203 MPASS(sctx->isc_ntxd_max[0]);
5204 MPASS(sctx->isc_ntxd_default[0]);
5208 _iflib_pre_assert(if_softc_ctx_t scctx)
5211 MPASS(scctx->isc_txrx->ift_txd_encap);
5212 MPASS(scctx->isc_txrx->ift_txd_flush);
5213 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5214 MPASS(scctx->isc_txrx->ift_rxd_available);
5215 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5216 MPASS(scctx->isc_txrx->ift_rxd_refill);
5217 MPASS(scctx->isc_txrx->ift_rxd_flush);
5221 iflib_register(if_ctx_t ctx)
5223 if_shared_ctx_t sctx = ctx->ifc_sctx;
5224 driver_t *driver = sctx->isc_driver;
5225 device_t dev = ctx->ifc_dev;
5228 _iflib_assert(sctx);
5231 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5232 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5234 device_printf(dev, "can not allocate ifnet structure\n");
5239 * Initialize our context's device specific methods
5241 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5242 kobj_class_compile((kobj_class_t) driver);
5245 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5246 if_setsoftc(ifp, ctx);
5247 if_setdev(ifp, dev);
5248 if_setinitfn(ifp, iflib_if_init);
5249 if_setioctlfn(ifp, iflib_if_ioctl);
5251 if_setstartfn(ifp, iflib_altq_if_start);
5252 if_settransmitfn(ifp, iflib_altq_if_transmit);
5253 if_setsendqready(ifp);
5255 if_settransmitfn(ifp, iflib_if_transmit);
5257 if_setqflushfn(ifp, iflib_if_qflush);
5258 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5260 ctx->ifc_vlan_attach_event =
5261 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5262 EVENTHANDLER_PRI_FIRST);
5263 ctx->ifc_vlan_detach_event =
5264 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5265 EVENTHANDLER_PRI_FIRST);
5267 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5268 iflib_media_change, iflib_media_status);
5275 iflib_queues_alloc(if_ctx_t ctx)
5277 if_shared_ctx_t sctx = ctx->ifc_sctx;
5278 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5279 device_t dev = ctx->ifc_dev;
5280 int nrxqsets = scctx->isc_nrxqsets;
5281 int ntxqsets = scctx->isc_ntxqsets;
5284 iflib_fl_t fl = NULL;
5285 int i, j, cpu, err, txconf, rxconf;
5286 iflib_dma_info_t ifdip;
5287 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5288 uint32_t *txqsizes = scctx->isc_txqsizes;
5289 uint8_t nrxqs = sctx->isc_nrxqs;
5290 uint8_t ntxqs = sctx->isc_ntxqs;
5291 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5295 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5296 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5298 /* Allocate the TX ring struct memory */
5299 if (!(ctx->ifc_txqs =
5300 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5301 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5302 device_printf(dev, "Unable to allocate TX ring memory\n");
5307 /* Now allocate the RX */
5308 if (!(ctx->ifc_rxqs =
5309 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5310 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5311 device_printf(dev, "Unable to allocate RX ring memory\n");
5316 txq = ctx->ifc_txqs;
5317 rxq = ctx->ifc_rxqs;
5320 * XXX handle allocation failure
5322 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5323 /* Set up some basics */
5325 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5326 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5328 "Unable to allocate TX DMA info memory\n");
5332 txq->ift_ifdi = ifdip;
5333 for (j = 0; j < ntxqs; j++, ifdip++) {
5334 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5336 "Unable to allocate TX descriptors\n");
5340 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5341 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5345 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5346 txq->ift_br_offset = 1;
5348 txq->ift_br_offset = 0;
5351 txq->ift_timer.c_cpu = cpu;
5353 if (iflib_txsd_alloc(txq)) {
5354 device_printf(dev, "Critical Failure setting up TX buffers\n");
5359 /* Initialize the TX lock */
5360 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5361 device_get_nameunit(dev), txq->ift_id);
5362 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5363 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5365 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5366 device_get_nameunit(dev), txq->ift_id);
5368 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5369 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5371 /* XXX free any allocated rings */
5372 device_printf(dev, "Unable to allocate buf_ring\n");
5377 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5378 /* Set up some basics */
5380 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5381 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5383 "Unable to allocate RX DMA info memory\n");
5388 rxq->ifr_ifdi = ifdip;
5389 /* XXX this needs to be changed if #rx queues != #tx queues */
5390 rxq->ifr_ntxqirq = 1;
5391 rxq->ifr_txqid[0] = i;
5392 for (j = 0; j < nrxqs; j++, ifdip++) {
5393 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5395 "Unable to allocate RX descriptors\n");
5399 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5403 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5404 rxq->ifr_fl_offset = 1;
5406 rxq->ifr_fl_offset = 0;
5408 rxq->ifr_nfl = nfree_lists;
5410 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5411 device_printf(dev, "Unable to allocate free list memory\n");
5416 for (j = 0; j < nfree_lists; j++) {
5417 fl[j].ifl_rxq = rxq;
5419 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5420 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5422 /* Allocate receive buffers for the ring */
5423 if (iflib_rxsd_alloc(rxq)) {
5425 "Critical Failure setting up receive buffers\n");
5430 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5431 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5436 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5437 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5438 for (i = 0; i < ntxqsets; i++) {
5439 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5441 for (j = 0; j < ntxqs; j++, di++) {
5442 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5443 paddrs[i*ntxqs + j] = di->idi_paddr;
5446 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5447 device_printf(ctx->ifc_dev,
5448 "Unable to allocate device TX queue\n");
5449 iflib_tx_structures_free(ctx);
5450 free(vaddrs, M_IFLIB);
5451 free(paddrs, M_IFLIB);
5454 free(vaddrs, M_IFLIB);
5455 free(paddrs, M_IFLIB);
5458 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5459 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5460 for (i = 0; i < nrxqsets; i++) {
5461 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5463 for (j = 0; j < nrxqs; j++, di++) {
5464 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5465 paddrs[i*nrxqs + j] = di->idi_paddr;
5468 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5469 device_printf(ctx->ifc_dev,
5470 "Unable to allocate device RX queue\n");
5471 iflib_tx_structures_free(ctx);
5472 free(vaddrs, M_IFLIB);
5473 free(paddrs, M_IFLIB);
5476 free(vaddrs, M_IFLIB);
5477 free(paddrs, M_IFLIB);
5481 /* XXX handle allocation failure changes */
5485 if (ctx->ifc_rxqs != NULL)
5486 free(ctx->ifc_rxqs, M_IFLIB);
5487 ctx->ifc_rxqs = NULL;
5488 if (ctx->ifc_txqs != NULL)
5489 free(ctx->ifc_txqs, M_IFLIB);
5490 ctx->ifc_txqs = NULL;
5496 iflib_tx_structures_setup(if_ctx_t ctx)
5498 iflib_txq_t txq = ctx->ifc_txqs;
5501 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5502 iflib_txq_setup(txq);
5508 iflib_tx_structures_free(if_ctx_t ctx)
5510 iflib_txq_t txq = ctx->ifc_txqs;
5511 if_shared_ctx_t sctx = ctx->ifc_sctx;
5514 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5515 iflib_txq_destroy(txq);
5516 for (j = 0; j < sctx->isc_ntxqs; j++)
5517 iflib_dma_free(&txq->ift_ifdi[j]);
5519 free(ctx->ifc_txqs, M_IFLIB);
5520 ctx->ifc_txqs = NULL;
5521 IFDI_QUEUES_FREE(ctx);
5524 /*********************************************************************
5526 * Initialize all receive rings.
5528 **********************************************************************/
5530 iflib_rx_structures_setup(if_ctx_t ctx)
5532 iflib_rxq_t rxq = ctx->ifc_rxqs;
5534 #if defined(INET6) || defined(INET)
5538 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5539 #if defined(INET6) || defined(INET)
5540 tcp_lro_free(&rxq->ifr_lc);
5541 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5542 TCP_LRO_ENTRIES, min(1024,
5543 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5544 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5547 rxq->ifr_lro_enabled = TRUE;
5549 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5552 #if defined(INET6) || defined(INET)
5555 * Free RX software descriptors allocated so far, we will only handle
5556 * the rings that completed, the failing case will have
5557 * cleaned up for itself. 'q' failed, so its the terminus.
5559 rxq = ctx->ifc_rxqs;
5560 for (i = 0; i < q; ++i, rxq++) {
5561 iflib_rx_sds_free(rxq);
5562 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5568 /*********************************************************************
5570 * Free all receive rings.
5572 **********************************************************************/
5574 iflib_rx_structures_free(if_ctx_t ctx)
5576 iflib_rxq_t rxq = ctx->ifc_rxqs;
5578 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5579 iflib_rx_sds_free(rxq);
5581 free(ctx->ifc_rxqs, M_IFLIB);
5582 ctx->ifc_rxqs = NULL;
5586 iflib_qset_structures_setup(if_ctx_t ctx)
5591 * It is expected that the caller takes care of freeing queues if this
5594 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5595 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5599 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5600 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5606 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5607 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5610 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5615 find_nth(if_ctx_t ctx, int qid)
5618 int i, cpuid, eqid, count;
5620 CPU_COPY(&ctx->ifc_cpus, &cpus);
5621 count = CPU_COUNT(&cpus);
5623 /* clear up to the qid'th bit */
5624 for (i = 0; i < eqid; i++) {
5625 cpuid = CPU_FFS(&cpus);
5627 CPU_CLR(cpuid-1, &cpus);
5629 cpuid = CPU_FFS(&cpus);
5635 extern struct cpu_group *cpu_top; /* CPU topology */
5638 find_child_with_core(int cpu, struct cpu_group *grp)
5642 if (grp->cg_children == 0)
5645 MPASS(grp->cg_child);
5646 for (i = 0; i < grp->cg_children; i++) {
5647 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5655 * Find the nth "close" core to the specified core
5656 * "close" is defined as the deepest level that shares
5657 * at least an L2 cache. With threads, this will be
5658 * threads on the same core. If the sahred cache is L3
5659 * or higher, simply returns the same core.
5662 find_close_core(int cpu, int core_offset)
5664 struct cpu_group *grp;
5673 while ((i = find_child_with_core(cpu, grp)) != -1) {
5674 /* If the child only has one cpu, don't descend */
5675 if (grp->cg_child[i].cg_count <= 1)
5677 grp = &grp->cg_child[i];
5680 /* If they don't share at least an L2 cache, use the same CPU */
5681 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5685 CPU_COPY(&grp->cg_mask, &cs);
5687 /* Add the selected CPU offset to core offset. */
5688 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5689 if (fcpu - 1 == cpu)
5691 CPU_CLR(fcpu - 1, &cs);
5697 CPU_COPY(&grp->cg_mask, &cs);
5698 for (i = core_offset % grp->cg_count; i > 0; i--) {
5699 MPASS(CPU_FFS(&cs));
5700 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5702 MPASS(CPU_FFS(&cs));
5703 return CPU_FFS(&cs) - 1;
5707 find_close_core(int cpu, int core_offset __unused)
5714 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5718 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5719 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5720 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5722 case IFLIB_INTR_RXTX:
5723 /* RX queues get the specified core */
5724 return qid / CPU_COUNT(&ctx->ifc_cpus);
5730 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5731 #define find_close_core(cpuid, tid) CPU_FIRST()
5732 #define find_nth(ctx, gid) CPU_FIRST()
5735 /* Just to avoid copy/paste */
5737 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5738 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5742 int err, cpuid, tid;
5745 cpuid = find_nth(ctx, qid);
5746 tid = get_core_offset(ctx, type, qid);
5748 cpuid = find_close_core(cpuid, tid);
5749 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5752 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5756 if (cpuid > ctx->ifc_cpuid_highest)
5757 ctx->ifc_cpuid_highest = cpuid;
5763 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5764 iflib_intr_type_t type, driver_filter_t *filter,
5765 void *filter_arg, int qid, const char *name)
5768 struct grouptask *gtask;
5769 struct taskqgroup *tqg;
5770 iflib_filter_info_t info;
5773 driver_filter_t *intr_fast;
5776 info = &ctx->ifc_filter_info;
5780 /* XXX merge tx/rx for netmap? */
5782 q = &ctx->ifc_txqs[qid];
5783 info = &ctx->ifc_txqs[qid].ift_filter_info;
5784 gtask = &ctx->ifc_txqs[qid].ift_task;
5785 tqg = qgroup_if_io_tqg;
5787 intr_fast = iflib_fast_intr;
5788 GROUPTASK_INIT(gtask, 0, fn, q);
5789 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5792 q = &ctx->ifc_rxqs[qid];
5793 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5794 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5795 tqg = qgroup_if_io_tqg;
5797 intr_fast = iflib_fast_intr;
5798 GROUPTASK_INIT(gtask, 0, fn, q);
5800 case IFLIB_INTR_RXTX:
5801 q = &ctx->ifc_rxqs[qid];
5802 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5803 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5804 tqg = qgroup_if_io_tqg;
5806 intr_fast = iflib_fast_intr_rxtx;
5807 GROUPTASK_INIT(gtask, 0, fn, q);
5809 case IFLIB_INTR_ADMIN:
5812 info = &ctx->ifc_filter_info;
5813 gtask = &ctx->ifc_admin_task;
5814 tqg = qgroup_if_config_tqg;
5815 fn = _task_fn_admin;
5816 intr_fast = iflib_fast_intr_ctx;
5819 panic("unknown net intr type");
5822 info->ifi_filter = filter;
5823 info->ifi_filter_arg = filter_arg;
5824 info->ifi_task = gtask;
5828 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5830 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5833 if (type == IFLIB_INTR_ADMIN)
5837 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5842 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
5849 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5851 struct grouptask *gtask;
5852 struct taskqgroup *tqg;
5859 q = &ctx->ifc_txqs[qid];
5860 gtask = &ctx->ifc_txqs[qid].ift_task;
5861 tqg = qgroup_if_io_tqg;
5865 q = &ctx->ifc_rxqs[qid];
5866 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5867 tqg = qgroup_if_io_tqg;
5870 case IFLIB_INTR_IOV:
5872 gtask = &ctx->ifc_vflr_task;
5873 tqg = qgroup_if_config_tqg;
5877 panic("unknown net intr type");
5879 GROUPTASK_INIT(gtask, 0, fn, q);
5881 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5884 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
5887 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
5892 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5896 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5899 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
5900 rman_get_rid(irq->ii_res), irq->ii_res);
5904 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5906 iflib_txq_t txq = ctx->ifc_txqs;
5907 iflib_rxq_t rxq = ctx->ifc_rxqs;
5908 if_irq_t irq = &ctx->ifc_legacy_irq;
5909 iflib_filter_info_t info;
5911 struct grouptask *gtask;
5912 struct resource *res;
5913 struct taskqgroup *tqg;
5919 q = &ctx->ifc_rxqs[0];
5920 info = &rxq[0].ifr_filter_info;
5921 gtask = &rxq[0].ifr_task;
5922 tqg = qgroup_if_io_tqg;
5923 tqrid = irq->ii_rid = *rid;
5926 ctx->ifc_flags |= IFC_LEGACY;
5927 info->ifi_filter = filter;
5928 info->ifi_filter_arg = filter_arg;
5929 info->ifi_task = gtask;
5930 info->ifi_ctx = ctx;
5933 /* We allocate a single interrupt resource */
5934 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5936 GROUPTASK_INIT(gtask, 0, fn, q);
5938 taskqgroup_attach(tqg, gtask, q, dev, res, name);
5940 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5941 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
5947 iflib_led_create(if_ctx_t ctx)
5950 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5951 device_get_nameunit(ctx->ifc_dev));
5955 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5958 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5962 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5965 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5969 iflib_admin_intr_deferred(if_ctx_t ctx)
5972 struct grouptask *gtask;
5974 gtask = &ctx->ifc_admin_task;
5975 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5978 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5982 iflib_iov_intr_deferred(if_ctx_t ctx)
5985 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5989 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5992 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
5997 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6001 GROUPTASK_INIT(gtask, 0, fn, ctx);
6002 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6007 iflib_config_gtask_deinit(struct grouptask *gtask)
6010 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6014 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6016 if_t ifp = ctx->ifc_ifp;
6017 iflib_txq_t txq = ctx->ifc_txqs;
6019 if_setbaudrate(ifp, baudrate);
6020 if (baudrate >= IF_Gbps(10)) {
6022 ctx->ifc_flags |= IFC_PREFETCH;
6025 /* If link down, disable watchdog */
6026 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6027 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6028 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6030 ctx->ifc_link_state = link_state;
6031 if_link_state_change(ifp, link_state);
6035 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6039 int credits_pre = txq->ift_cidx_processed;
6042 if (ctx->isc_txd_credits_update == NULL)
6045 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6046 BUS_DMASYNC_POSTREAD);
6047 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6050 txq->ift_processed += credits;
6051 txq->ift_cidx_processed += credits;
6053 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6054 if (txq->ift_cidx_processed >= txq->ift_size)
6055 txq->ift_cidx_processed -= txq->ift_size;
6060 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6065 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6066 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6067 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6068 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6073 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6074 const char *description, if_int_delay_info_t info,
6075 int offset, int value)
6077 info->iidi_ctx = ctx;
6078 info->iidi_offset = offset;
6079 info->iidi_value = value;
6080 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6081 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6082 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6083 info, 0, iflib_sysctl_int_delay, "I", description);
6087 iflib_ctx_lock_get(if_ctx_t ctx)
6090 return (&ctx->ifc_ctx_sx);
6094 iflib_msix_init(if_ctx_t ctx)
6096 device_t dev = ctx->ifc_dev;
6097 if_shared_ctx_t sctx = ctx->ifc_sctx;
6098 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6099 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
6100 int iflib_num_tx_queues, iflib_num_rx_queues;
6101 int err, admincnt, bar;
6103 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6104 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6107 device_printf(dev, "msix_init qsets capped at %d\n",
6108 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6110 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6111 admincnt = sctx->isc_admin_intrcnt;
6112 /* Override by tuneable */
6113 if (scctx->isc_disable_msix)
6116 /* First try MSI-X */
6117 if ((msgs = pci_msix_count(dev)) == 0) {
6119 device_printf(dev, "MSI-X not supported or disabled\n");
6123 * bar == -1 => "trust me I know what I'm doing"
6124 * Some drivers are for hardware that is so shoddily
6125 * documented that no one knows which bars are which
6126 * so the developer has to map all bars. This hack
6127 * allows shoddy garbage to use MSI-X in this framework.
6130 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6131 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6132 if (ctx->ifc_msix_mem == NULL) {
6133 device_printf(dev, "Unable to map MSI-X table\n");
6138 /* use only 1 qset in debug mode */
6139 queuemsgs = min(msgs - admincnt, 1);
6141 queuemsgs = msgs - admincnt;
6144 queues = imin(queuemsgs, rss_getnumbuckets());
6148 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6151 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6152 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6154 /* If we're doing RSS, clamp at the number of RSS buckets */
6155 if (queues > rss_getnumbuckets())
6156 queues = rss_getnumbuckets();
6158 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6159 rx_queues = iflib_num_rx_queues;
6163 if (rx_queues > scctx->isc_nrxqsets)
6164 rx_queues = scctx->isc_nrxqsets;
6167 * We want this to be all logical CPUs by default
6169 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6170 tx_queues = iflib_num_tx_queues;
6172 tx_queues = mp_ncpus;
6174 if (tx_queues > scctx->isc_ntxqsets)
6175 tx_queues = scctx->isc_ntxqsets;
6177 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6179 if (tx_queues != rx_queues)
6181 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6182 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6184 tx_queues = min(rx_queues, tx_queues);
6185 rx_queues = min(rx_queues, tx_queues);
6188 device_printf(dev, "Using %d rx queues %d tx queues\n",
6189 rx_queues, tx_queues);
6191 vectors = rx_queues + admincnt;
6192 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6193 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6195 scctx->isc_vectors = vectors;
6196 scctx->isc_nrxqsets = rx_queues;
6197 scctx->isc_ntxqsets = tx_queues;
6198 scctx->isc_intr = IFLIB_INTR_MSIX;
6203 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n",
6205 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6207 ctx->ifc_msix_mem = NULL;
6210 vectors = pci_msi_count(dev);
6211 scctx->isc_nrxqsets = 1;
6212 scctx->isc_ntxqsets = 1;
6213 scctx->isc_vectors = vectors;
6214 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6215 device_printf(dev,"Using an MSI interrupt\n");
6216 scctx->isc_intr = IFLIB_INTR_MSI;
6218 scctx->isc_vectors = 1;
6219 device_printf(dev,"Using a Legacy interrupt\n");
6220 scctx->isc_intr = IFLIB_INTR_LEGACY;
6226 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6229 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6232 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6234 const char *ring_state = "UNKNOWN";
6237 rc = sysctl_wire_old_buffer(req, 0);
6241 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6246 ring_state = ring_states[state[3]];
6248 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6249 state[0], state[1], state[2], ring_state);
6250 rc = sbuf_finish(sb);
6255 enum iflib_ndesc_handler {
6261 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6263 if_ctx_t ctx = (void *)arg1;
6264 enum iflib_ndesc_handler type = arg2;
6265 char buf[256] = {0};
6270 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6274 case IFLIB_NTXD_HANDLER:
6275 ndesc = ctx->ifc_sysctl_ntxds;
6277 nqs = ctx->ifc_sctx->isc_ntxqs;
6279 case IFLIB_NRXD_HANDLER:
6280 ndesc = ctx->ifc_sysctl_nrxds;
6282 nqs = ctx->ifc_sctx->isc_nrxqs;
6285 panic("unhandled type");
6290 for (i=0; i<8; i++) {
6295 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6298 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6299 if (rc || req->newptr == NULL)
6302 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6303 i++, p = strsep(&next, " ,")) {
6304 ndesc[i] = strtoul(p, NULL, 10);
6310 #define NAME_BUFLEN 32
6312 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6314 device_t dev = iflib_get_dev(ctx);
6315 struct sysctl_oid_list *child, *oid_list;
6316 struct sysctl_ctx_list *ctx_list;
6317 struct sysctl_oid *node;
6319 ctx_list = device_get_sysctl_ctx(dev);
6320 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6321 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6322 CTLFLAG_RD, NULL, "IFLIB fields");
6323 oid_list = SYSCTL_CHILDREN(node);
6325 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6326 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6329 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6330 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6331 "# of txqs to use, 0 => use default #");
6332 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6333 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6334 "# of rxqs to use, 0 => use default #");
6335 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6336 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6337 "permit #txq != #rxq");
6338 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6339 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6340 "disable MSI-X (default 0)");
6341 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6342 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6343 "set the rx budget");
6344 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6345 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6346 "cause tx to abdicate instead of running to completion");
6348 /* XXX change for per-queue sizes */
6349 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6350 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6351 mp_ndesc_handler, "A",
6352 "list of # of tx descriptors to use, 0 = use default #");
6353 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6354 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6355 mp_ndesc_handler, "A",
6356 "list of # of rx descriptors to use, 0 = use default #");
6360 iflib_add_device_sysctl_post(if_ctx_t ctx)
6362 if_shared_ctx_t sctx = ctx->ifc_sctx;
6363 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6364 device_t dev = iflib_get_dev(ctx);
6365 struct sysctl_oid_list *child;
6366 struct sysctl_ctx_list *ctx_list;
6371 char namebuf[NAME_BUFLEN];
6373 struct sysctl_oid *queue_node, *fl_node, *node;
6374 struct sysctl_oid_list *queue_list, *fl_list;
6375 ctx_list = device_get_sysctl_ctx(dev);
6377 node = ctx->ifc_sysctl_node;
6378 child = SYSCTL_CHILDREN(node);
6380 if (scctx->isc_ntxqsets > 100)
6382 else if (scctx->isc_ntxqsets > 10)
6386 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6387 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6388 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6389 CTLFLAG_RD, NULL, "Queue Name");
6390 queue_list = SYSCTL_CHILDREN(queue_node);
6392 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6394 &txq->ift_dequeued, "total mbufs freed");
6395 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6397 &txq->ift_enqueued, "total mbufs enqueued");
6399 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6401 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6402 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6404 &txq->ift_pullups, "# of times m_pullup was called");
6405 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6407 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6408 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6410 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6411 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6413 &txq->ift_map_failed, "# of times dma map failed");
6414 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6416 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6417 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6419 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6420 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6422 &txq->ift_pidx, 1, "Producer Index");
6423 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6425 &txq->ift_cidx, 1, "Consumer Index");
6426 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6428 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6429 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6431 &txq->ift_in_use, 1, "descriptors in use");
6432 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6434 &txq->ift_processed, "descriptors procesed for clean");
6435 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6437 &txq->ift_cleaned, "total cleaned");
6438 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6439 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6440 0, mp_ring_state_handler, "A", "soft ring state");
6441 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6442 CTLFLAG_RD, &txq->ift_br->enqueues,
6443 "# of enqueues to the mp_ring for this queue");
6444 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6445 CTLFLAG_RD, &txq->ift_br->drops,
6446 "# of drops in the mp_ring for this queue");
6447 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6448 CTLFLAG_RD, &txq->ift_br->starts,
6449 "# of normal consumer starts in the mp_ring for this queue");
6450 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6451 CTLFLAG_RD, &txq->ift_br->stalls,
6452 "# of consumer stalls in the mp_ring for this queue");
6453 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6454 CTLFLAG_RD, &txq->ift_br->restarts,
6455 "# of consumer restarts in the mp_ring for this queue");
6456 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6457 CTLFLAG_RD, &txq->ift_br->abdications,
6458 "# of consumer abdications in the mp_ring for this queue");
6461 if (scctx->isc_nrxqsets > 100)
6463 else if (scctx->isc_nrxqsets > 10)
6467 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6468 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6469 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6470 CTLFLAG_RD, NULL, "Queue Name");
6471 queue_list = SYSCTL_CHILDREN(queue_node);
6472 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6473 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6475 &rxq->ifr_cq_pidx, 1, "Producer Index");
6476 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6478 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6481 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6482 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6483 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6484 CTLFLAG_RD, NULL, "freelist Name");
6485 fl_list = SYSCTL_CHILDREN(fl_node);
6486 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6488 &fl->ifl_pidx, 1, "Producer Index");
6489 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6491 &fl->ifl_cidx, 1, "Consumer Index");
6492 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6494 &fl->ifl_credits, 1, "credits available");
6496 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6498 &fl->ifl_m_enqueued, "mbufs allocated");
6499 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6501 &fl->ifl_m_dequeued, "mbufs freed");
6502 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6504 &fl->ifl_cl_enqueued, "clusters allocated");
6505 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6507 &fl->ifl_cl_dequeued, "clusters freed");
6516 iflib_request_reset(if_ctx_t ctx)
6520 ctx->ifc_flags |= IFC_DO_RESET;
6524 #ifndef __NO_STRICT_ALIGNMENT
6525 static struct mbuf *
6526 iflib_fixup_rx(struct mbuf *m)
6530 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6531 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6532 m->m_data += ETHER_HDR_LEN;
6535 MGETHDR(n, M_NOWAIT, MT_DATA);
6540 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6541 m->m_data += ETHER_HDR_LEN;
6542 m->m_len -= ETHER_HDR_LEN;
6543 n->m_len = ETHER_HDR_LEN;
6544 M_MOVE_PKTHDR(n, m);
6553 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6557 ctx = if_getsoftc(ifp);
6559 *nrxr = NRXQSETS(ctx);
6560 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6561 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6566 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6569 if_softc_ctx_t scctx;
6574 ctx = if_getsoftc(ifp);
6575 scctx = &ctx->ifc_softc_ctx;
6579 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6580 rxq = &ctx->ifc_rxqs[i];
6581 for (j = 0; j < rxq->ifr_nfl; j++) {
6583 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6586 iflib_no_tx_batch = 1;
6594 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6600 ctx = if_getsoftc(ifp);
6601 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6605 txq = &ctx->ifc_txqs[0];
6606 error = iflib_encap(txq, &m);
6608 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6613 iflib_netdump_poll(struct ifnet *ifp, int count)
6616 if_softc_ctx_t scctx;
6620 ctx = if_getsoftc(ifp);
6621 scctx = &ctx->ifc_softc_ctx;
6623 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6627 txq = &ctx->ifc_txqs[0];
6628 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6630 for (i = 0; i < scctx->isc_nrxqsets; i++)
6631 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6634 #endif /* NETDUMP */