2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
63 #include <netinet/in.h>
64 #include <netinet/in_pcb.h>
65 #include <netinet/tcp_lro.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/if_ether.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
78 #include <dev/led/led.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pci_private.h>
83 #include <net/iflib.h>
87 #if defined(__i386__) || defined(__amd64__)
88 #include <sys/memdesc.h>
89 #include <machine/bus.h>
90 #include <machine/md_var.h>
91 #include <machine/specialreg.h>
92 #include <x86/include/busdma_impl.h>
93 #include <x86/iommu/busdma_dmar.h>
96 #include <sys/bitstring.h>
98 * enable accounting of every mbuf as it comes in to and goes out of
99 * iflib's software descriptor references
101 #define MEMORY_LOGGING 0
103 * Enable mbuf vectors for compressing long mbuf chains
108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
109 * we prefetch needs to be determined by the time spent in m_free vis a vis
110 * the cost of a prefetch. This will of course vary based on the workload:
111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
112 * is quite expensive, thus suggesting very little prefetch.
113 * - small packet forwarding which is just returning a single mbuf to
114 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 typedef struct iflib_txq *iflib_txq_t;
134 typedef struct iflib_rxq *iflib_rxq_t;
136 typedef struct iflib_fl *iflib_fl_t;
140 typedef struct iflib_filter_info {
141 driver_filter_t *ifi_filter;
142 void *ifi_filter_arg;
143 struct grouptask *ifi_task;
145 } *iflib_filter_info_t;
150 * Pointer to hardware driver's softc
157 if_shared_ctx_t ifc_sctx;
158 struct if_softc_ctx ifc_softc_ctx;
162 uint16_t ifc_nhwtxqs;
163 uint16_t ifc_nhwrxqs;
165 iflib_txq_t ifc_txqs;
166 iflib_rxq_t ifc_rxqs;
167 uint32_t ifc_if_flags;
169 uint32_t ifc_max_fl_buf_size;
174 int ifc_watchdog_events;
175 struct cdev *ifc_led_dev;
176 struct resource *ifc_msix_mem;
178 struct if_irq ifc_legacy_irq;
179 struct grouptask ifc_admin_task;
180 struct grouptask ifc_vflr_task;
181 struct iflib_filter_info ifc_filter_info;
182 struct ifmedia ifc_media;
184 struct sysctl_oid *ifc_sysctl_node;
185 uint16_t ifc_sysctl_ntxqs;
186 uint16_t ifc_sysctl_nrxqs;
187 uint16_t ifc_sysctl_qs_eq_override;
188 uint16_t ifc_sysctl_rx_budget;
190 qidx_t ifc_sysctl_ntxds[8];
191 qidx_t ifc_sysctl_nrxds[8];
192 struct if_txrx ifc_txrx;
193 #define isc_txd_encap ifc_txrx.ift_txd_encap
194 #define isc_txd_flush ifc_txrx.ift_txd_flush
195 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
196 #define isc_rxd_available ifc_txrx.ift_rxd_available
197 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
198 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
199 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
201 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
202 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
203 eventhandler_tag ifc_vlan_attach_event;
204 eventhandler_tag ifc_vlan_detach_event;
205 uint8_t ifc_mac[ETHER_ADDR_LEN];
206 char ifc_mtx_name[16];
211 iflib_get_softc(if_ctx_t ctx)
214 return (ctx->ifc_softc);
218 iflib_get_dev(if_ctx_t ctx)
221 return (ctx->ifc_dev);
225 iflib_get_ifp(if_ctx_t ctx)
228 return (ctx->ifc_ifp);
232 iflib_get_media(if_ctx_t ctx)
235 return (&ctx->ifc_media);
239 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
242 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
246 iflib_get_softc_ctx(if_ctx_t ctx)
249 return (&ctx->ifc_softc_ctx);
253 iflib_get_sctx(if_ctx_t ctx)
256 return (ctx->ifc_sctx);
259 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
260 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
261 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
263 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
264 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
266 #define RX_SW_DESC_MAP_CREATED (1 << 0)
267 #define TX_SW_DESC_MAP_CREATED (1 << 1)
268 #define RX_SW_DESC_INUSE (1 << 3)
269 #define TX_SW_DESC_MAPPED (1 << 4)
271 #define M_TOOBIG M_PROTO1
273 typedef struct iflib_sw_rx_desc_array {
274 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
275 struct mbuf **ifsd_m; /* pkthdr mbufs */
276 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
278 } iflib_rxsd_array_t;
280 typedef struct iflib_sw_tx_desc_array {
281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
282 struct mbuf **ifsd_m; /* pkthdr mbufs */
287 /* magic number that should be high enough for any hardware */
288 #define IFLIB_MAX_TX_SEGS 128
289 #define IFLIB_MAX_RX_SEGS 32
290 #define IFLIB_RX_COPY_THRESH 128
291 #define IFLIB_MAX_RX_REFRESH 32
292 /* The minimum descriptors per second before we start coalescing */
293 #define IFLIB_MIN_DESC_SEC 16384
294 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
295 #define IFLIB_QUEUE_IDLE 0
296 #define IFLIB_QUEUE_HUNG 1
297 #define IFLIB_QUEUE_WORKING 2
298 /* maximum number of txqs that can share an rx interrupt */
299 #define IFLIB_MAX_TX_SHARED_INTR 4
301 /* this should really scale with ring size - this is a fairly arbitrary value */
302 #define TX_BATCH_SIZE 32
304 #define IFLIB_RESTART_BUDGET 8
306 #define IFC_LEGACY 0x001
307 #define IFC_QFLUSH 0x002
308 #define IFC_MULTISEG 0x004
309 #define IFC_DMAR 0x008
310 #define IFC_SC_ALLOCATED 0x010
311 #define IFC_INIT_DONE 0x020
312 #define IFC_PREFETCH 0x040
313 #define IFC_DO_RESET 0x080
314 #define IFC_CHECK_HUNG 0x100
316 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
317 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
318 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
322 qidx_t ift_cidx_processed;
325 uint8_t ift_br_offset;
326 uint16_t ift_npending;
327 uint16_t ift_db_pending;
328 uint16_t ift_rs_pending;
330 uint8_t ift_txd_size[8];
331 uint64_t ift_processed;
332 uint64_t ift_cleaned;
333 uint64_t ift_cleaned_prev;
335 uint64_t ift_enqueued;
336 uint64_t ift_dequeued;
338 uint64_t ift_no_tx_dma_setup;
339 uint64_t ift_no_desc_avail;
340 uint64_t ift_mbuf_defrag_failed;
341 uint64_t ift_mbuf_defrag;
342 uint64_t ift_map_failed;
343 uint64_t ift_txd_encap_efbig;
344 uint64_t ift_pullups;
347 struct mtx ift_db_mtx;
349 /* constant values */
351 struct ifmp_ring *ift_br;
352 struct grouptask ift_task;
355 struct callout ift_timer;
357 if_txsd_vec_t ift_sds;
360 uint8_t ift_update_freq;
361 struct iflib_filter_info ift_filter_info;
362 bus_dma_tag_t ift_desc_tag;
363 bus_dma_tag_t ift_tso_desc_tag;
364 iflib_dma_info_t ift_ifdi;
365 #define MTX_NAME_LEN 16
366 char ift_mtx_name[MTX_NAME_LEN];
367 char ift_db_mtx_name[MTX_NAME_LEN];
368 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
369 #ifdef IFLIB_DIAGNOSTICS
370 uint64_t ift_cpu_exec_count[256];
372 } __aligned(CACHE_LINE_SIZE);
379 uint8_t ifl_rxd_size;
381 uint64_t ifl_m_enqueued;
382 uint64_t ifl_m_dequeued;
383 uint64_t ifl_cl_enqueued;
384 uint64_t ifl_cl_dequeued;
388 bitstr_t *ifl_rx_bitmap;
392 uint16_t ifl_buf_size;
395 iflib_rxsd_array_t ifl_sds;
398 bus_dma_tag_t ifl_desc_tag;
399 iflib_dma_info_t ifl_ifdi;
400 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
401 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
402 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
403 } __aligned(CACHE_LINE_SIZE);
406 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
412 else if (pidx < cidx)
413 used = size - cidx + pidx;
414 else if (gen == 0 && pidx == cidx)
416 else if (gen == 1 && pidx == cidx)
424 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
426 #define IDXDIFF(head, tail, wrap) \
427 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
430 /* If there is a separate completion queue -
431 * these are the cq cidx and pidx. Otherwise
438 uint8_t ifr_fl_offset;
444 uint8_t ifr_lro_enabled;
447 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
448 struct lro_ctrl ifr_lc;
449 struct grouptask ifr_task;
450 struct iflib_filter_info ifr_filter_info;
451 iflib_dma_info_t ifr_ifdi;
453 /* dynamically allocate if any drivers need a value substantially larger than this */
454 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
455 #ifdef IFLIB_DIAGNOSTICS
456 uint64_t ifr_cpu_exec_count[256];
458 } __aligned(CACHE_LINE_SIZE);
460 typedef struct if_rxsd {
462 struct mbuf **ifsd_m;
467 /* multiple of word size */
469 #define PKT_INFO_SIZE 6
470 #define RXD_INFO_SIZE 5
471 #define PKT_TYPE uint64_t
473 #define PKT_INFO_SIZE 11
474 #define RXD_INFO_SIZE 8
475 #define PKT_TYPE uint32_t
477 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
478 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
480 typedef struct if_pkt_info_pad {
481 PKT_TYPE pkt_val[PKT_INFO_SIZE];
482 } *if_pkt_info_pad_t;
483 typedef struct if_rxd_info_pad {
484 PKT_TYPE rxd_val[RXD_INFO_SIZE];
485 } *if_rxd_info_pad_t;
487 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
488 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
492 pkt_info_zero(if_pkt_info_t pi)
494 if_pkt_info_pad_t pi_pad;
496 pi_pad = (if_pkt_info_pad_t)pi;
497 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
498 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
500 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
501 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
506 rxd_info_zero(if_rxd_info_t ri)
508 if_rxd_info_pad_t ri_pad;
511 ri_pad = (if_rxd_info_pad_t)ri;
512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
513 ri_pad->rxd_val[i] = 0;
514 ri_pad->rxd_val[i+1] = 0;
515 ri_pad->rxd_val[i+2] = 0;
516 ri_pad->rxd_val[i+3] = 0;
519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
524 * Only allow a single packet to take up most 1/nth of the tx ring
526 #define MAX_SINGLE_PACKET_FRACTION 12
527 #define IF_BAD_DMA (bus_addr_t)-1
529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
531 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
533 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
534 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
535 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
538 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
539 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
542 /* Our boot-time initialization hook */
543 static int iflib_module_event_handler(module_t, int, void *);
545 static moduledata_t iflib_moduledata = {
547 iflib_module_event_handler,
551 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
552 MODULE_VERSION(iflib, 1);
554 MODULE_DEPEND(iflib, pci, 1, 1, 1);
555 MODULE_DEPEND(iflib, ether, 1, 1, 1);
557 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
558 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
560 #ifndef IFLIB_DEBUG_COUNTERS
562 #define IFLIB_DEBUG_COUNTERS 1
564 #define IFLIB_DEBUG_COUNTERS 0
565 #endif /* !INVARIANTS */
568 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
569 "iflib driver parameters");
572 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
574 static int iflib_min_tx_latency = 0;
575 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
576 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
577 static int iflib_no_tx_batch = 0;
578 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
579 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
582 #if IFLIB_DEBUG_COUNTERS
584 static int iflib_tx_seen;
585 static int iflib_tx_sent;
586 static int iflib_tx_encap;
587 static int iflib_rx_allocs;
588 static int iflib_fl_refills;
589 static int iflib_fl_refills_large;
590 static int iflib_tx_frees;
592 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
593 &iflib_tx_seen, 0, "# tx mbufs seen");
594 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
595 &iflib_tx_sent, 0, "# tx mbufs sent");
596 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
597 &iflib_tx_encap, 0, "# tx mbufs encapped");
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
599 &iflib_tx_frees, 0, "# tx frees");
600 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
601 &iflib_rx_allocs, 0, "# rx allocations");
602 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
603 &iflib_fl_refills, 0, "# refills");
604 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
605 &iflib_fl_refills_large, 0, "# large refills");
608 static int iflib_txq_drain_flushing;
609 static int iflib_txq_drain_oactive;
610 static int iflib_txq_drain_notready;
611 static int iflib_txq_drain_encapfail;
613 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
614 &iflib_txq_drain_flushing, 0, "# drain flushes");
615 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
616 &iflib_txq_drain_oactive, 0, "# drain oactives");
617 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
618 &iflib_txq_drain_notready, 0, "# drain notready");
619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
620 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
623 static int iflib_encap_load_mbuf_fail;
624 static int iflib_encap_txq_avail_fail;
625 static int iflib_encap_txd_encap_fail;
627 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
628 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
629 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
630 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
632 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
634 static int iflib_task_fn_rxs;
635 static int iflib_rx_intr_enables;
636 static int iflib_fast_intrs;
637 static int iflib_intr_link;
638 static int iflib_intr_msix;
639 static int iflib_rx_unavail;
640 static int iflib_rx_ctx_inactive;
641 static int iflib_rx_zero_len;
642 static int iflib_rx_if_input;
643 static int iflib_rx_mbuf_null;
644 static int iflib_rxd_flush;
646 static int iflib_verbose_debug;
648 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
649 &iflib_intr_link, 0, "# intr link calls");
650 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
651 &iflib_intr_msix, 0, "# intr msix calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
653 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
654 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
655 &iflib_rx_intr_enables, 0, "# rx intr enables");
656 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
657 &iflib_fast_intrs, 0, "# fast_intr calls");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
659 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
661 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
663 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
665 &iflib_rx_if_input, 0, "# times rxeof called if_input");
666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
667 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
669 &iflib_rxd_flush, 0, "# times rxd_flush called");
670 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
671 &iflib_verbose_debug, 0, "enable verbose debugging");
673 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
675 iflib_debug_reset(void)
677 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
678 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
679 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
680 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
681 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail =
682 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables =
683 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
684 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
685 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
689 #define DBG_COUNTER_INC(name)
690 static void iflib_debug_reset(void) {}
695 #define IFLIB_DEBUG 0
697 static void iflib_tx_structures_free(if_ctx_t ctx);
698 static void iflib_rx_structures_free(if_ctx_t ctx);
699 static int iflib_queues_alloc(if_ctx_t ctx);
700 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
701 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
702 static int iflib_qset_structures_setup(if_ctx_t ctx);
703 static int iflib_msix_init(if_ctx_t ctx);
704 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
705 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
706 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
707 static int iflib_register(if_ctx_t);
708 static void iflib_init_locked(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
710 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
711 static void iflib_ifmp_purge(iflib_txq_t txq);
712 static void _iflib_pre_assert(if_softc_ctx_t scctx);
713 static void iflib_stop(if_ctx_t ctx);
714 static void iflib_if_init_locked(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
720 #include <sys/selinfo.h>
721 #include <net/netmap.h>
722 #include <dev/netmap/netmap_kern.h>
724 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
727 * device-specific sysctl variables:
729 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
730 * During regular operations the CRC is stripped, but on some
731 * hardware reception of frames not multiple of 64 is slower,
732 * so using crcstrip=0 helps in benchmarks.
734 * iflib_rx_miss, iflib_rx_miss_bufs:
735 * count packets that might be missed due to lost interrupts.
737 SYSCTL_DECL(_dev_netmap);
739 * The xl driver by default strips CRCs and we do not override it.
742 int iflib_crcstrip = 1;
743 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
744 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
746 int iflib_rx_miss, iflib_rx_miss_bufs;
747 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
748 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
749 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
750 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
753 * Register/unregister. We are already under netmap lock.
754 * Only called on the first register or the last unregister.
757 iflib_netmap_register(struct netmap_adapter *na, int onoff)
759 struct ifnet *ifp = na->ifp;
760 if_ctx_t ctx = ifp->if_softc;
764 IFDI_INTR_DISABLE(ctx);
766 /* Tell the stack that the interface is no longer active */
767 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
770 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
772 /* enable or disable flags and callbacks in na and ifp */
774 nm_set_native_flags(na);
776 nm_clear_native_flags(na);
779 iflib_init_locked(ctx);
780 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
781 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
783 nm_clear_native_flags(na);
789 * Reconcile kernel and user view of the transmit ring.
791 * All information is in the kring.
792 * Userspace wants to send packets up to the one before kring->rhead,
793 * kernel knows kring->nr_hwcur is the first unsent packet.
795 * Here we push packets out (as many as possible), and possibly
796 * reclaim buffers from previously completed transmission.
798 * The caller (netmap) guarantees that there is only one instance
799 * running at any time. Any interference with other driver
800 * methods should be handled by the individual drivers.
803 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
805 struct netmap_adapter *na = kring->na;
806 struct ifnet *ifp = na->ifp;
807 struct netmap_ring *ring = kring->ring;
808 u_int nm_i; /* index into the netmap ring */
809 u_int nic_i; /* index into the NIC ring */
811 u_int const lim = kring->nkr_num_slots - 1;
812 u_int const head = kring->rhead;
813 struct if_pkt_info pi;
816 * interrupts on every tx packet are expensive so request
817 * them every half ring, or where NS_REPORT is set
819 u_int report_frequency = kring->nkr_num_slots >> 1;
820 /* device-specific */
821 if_ctx_t ctx = ifp->if_softc;
822 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
824 if (txq->ift_sds.ifsd_map)
825 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
826 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
830 * First part: process new packets to send.
831 * nm_i is the current index in the netmap ring,
832 * nic_i is the corresponding index in the NIC ring.
834 * If we have packets to send (nm_i != head)
835 * iterate over the netmap ring, fetch length and update
836 * the corresponding slot in the NIC ring. Some drivers also
837 * need to update the buffer's physical address in the NIC slot
838 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
840 * The netmap_reload_map() calls is especially expensive,
841 * even when (as in this case) the tag is 0, so do only
842 * when the buffer has actually changed.
844 * If possible do not set the report/intr bit on all slots,
845 * but only a few times per ring or when NS_REPORT is set.
847 * Finally, on 10G and faster drivers, it might be useful
848 * to prefetch the next slot and txr entry.
851 nm_i = kring->nr_hwcur;
853 pi.ipi_segs = txq->ift_segs;
854 pi.ipi_qsidx = kring->ring_id;
855 if (nm_i != head) { /* we have new packets to send */
856 nic_i = netmap_idx_k2n(kring, nm_i);
858 __builtin_prefetch(&ring->slot[nm_i]);
859 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
860 if (txq->ift_sds.ifsd_map)
861 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
863 for (n = 0; nm_i != head; n++) {
864 struct netmap_slot *slot = &ring->slot[nm_i];
865 u_int len = slot->len;
867 void *addr = PNMB(na, slot, &paddr);
868 int flags = (slot->flags & NS_REPORT ||
869 nic_i == 0 || nic_i == report_frequency) ?
872 /* device-specific */
874 pi.ipi_segs[0].ds_addr = paddr;
875 pi.ipi_segs[0].ds_len = len;
879 pi.ipi_flags = flags;
881 /* Fill the slot in the NIC ring. */
882 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
884 /* prefetch for next round */
885 __builtin_prefetch(&ring->slot[nm_i + 1]);
886 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
887 if (txq->ift_sds.ifsd_map) {
888 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
890 NM_CHECK_ADDR_LEN(na, addr, len);
892 if (slot->flags & NS_BUF_CHANGED) {
893 /* buffer has changed, reload map */
894 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
896 /* make sure changes to the buffer are synced */
897 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
898 BUS_DMASYNC_PREWRITE);
900 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
901 nm_i = nm_next(nm_i, lim);
902 nic_i = nm_next(nic_i, lim);
904 kring->nr_hwcur = head;
906 /* synchronize the NIC ring */
907 if (txq->ift_sds.ifsd_map)
908 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
911 /* (re)start the tx unit up to slot nic_i (excluded) */
912 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
916 * Second part: reclaim buffers for completed transmissions.
918 if (iflib_tx_credits_update(ctx, txq)) {
919 /* some tx completed, increment avail */
920 nic_i = txq->ift_cidx_processed;
921 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
927 * Reconcile kernel and user view of the receive ring.
928 * Same as for the txsync, this routine must be efficient.
929 * The caller guarantees a single invocations, but races against
930 * the rest of the driver should be handled here.
932 * On call, kring->rhead is the first packet that userspace wants
933 * to keep, and kring->rcur is the wakeup point.
934 * The kernel has previously reported packets up to kring->rtail.
936 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
937 * of whether or not we received an interrupt.
940 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
942 struct netmap_adapter *na = kring->na;
943 struct netmap_ring *ring = kring->ring;
944 uint32_t nm_i; /* index into the netmap ring */
945 uint32_t nic_i, nic_i_start; /* index into the NIC ring */
947 u_int const lim = kring->nkr_num_slots - 1;
948 u_int const head = kring->rhead;
949 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
950 struct if_rxd_info ri;
951 struct if_rxd_update iru;
953 struct ifnet *ifp = na->ifp;
954 if_ctx_t ctx = ifp->if_softc;
955 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
956 iflib_fl_t fl = rxq->ifr_fl;
958 return netmap_ring_reinit(kring);
960 /* XXX check sync modes */
961 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
962 if (fl->ifl_sds.ifsd_map == NULL)
964 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
965 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
968 * First part: import newly received packets.
970 * nm_i is the index of the next free slot in the netmap ring,
971 * nic_i is the index of the next received packet in the NIC ring,
972 * and they may differ in case if_init() has been called while
973 * in netmap mode. For the receive ring we have
975 * nic_i = rxr->next_check;
976 * nm_i = kring->nr_hwtail (previous)
978 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
980 * rxr->next_check is set to 0 on a ring reinit
982 if (netmap_no_pendintr || force_update) {
983 int crclen = iflib_crcstrip ? 0 : 4;
985 uint16_t slot_flags = kring->nkr_slot_flags;
987 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) {
988 nic_i = fl->ifl_cidx;
989 nm_i = netmap_idx_n2k(kring, nic_i);
990 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
991 for (n = 0; avail > 0; n++, avail--) {
993 ri.iri_frags = rxq->ifr_frags;
994 ri.iri_qsidx = kring->ring_id;
995 ri.iri_ifp = ctx->ifc_ifp;
998 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
999 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1000 ring->slot[nm_i].flags = slot_flags;
1001 if (fl->ifl_sds.ifsd_map)
1002 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1003 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1004 nm_i = nm_next(nm_i, lim);
1005 nic_i = nm_next(nic_i, lim);
1007 if (n) { /* update the state variables */
1008 if (netmap_no_pendintr && !force_update) {
1011 iflib_rx_miss_bufs += n;
1013 fl->ifl_cidx = nic_i;
1014 kring->nr_hwtail = nm_i;
1016 kring->nr_kflags &= ~NKR_PENDINTR;
1020 * Second part: skip past packets that userspace has released.
1021 * (kring->nr_hwcur to head excluded),
1022 * and make the buffers available for reception.
1023 * As usual nm_i is the index in the netmap ring,
1024 * nic_i is the index in the NIC ring, and
1025 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1027 /* XXX not sure how this will work with multiple free lists */
1028 nm_i = kring->nr_hwcur;
1032 iru.iru_paddrs = fl->ifl_bus_addrs;
1033 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1034 iru.iru_idxs = fl->ifl_rxd_idxs;
1035 iru.iru_qsidx = rxq->ifr_id;
1036 iru.iru_buf_size = fl->ifl_buf_size;
1037 iru.iru_flidx = fl->ifl_id;
1038 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i);
1039 for (i = 0; nm_i != head; i++) {
1040 struct netmap_slot *slot = &ring->slot[nm_i];
1041 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
1043 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
1046 fl->ifl_vm_addrs[i] = addr;
1047 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) {
1048 /* buffer has changed, reload map */
1049 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr);
1051 slot->flags &= ~NS_BUF_CHANGED;
1053 nm_i = nm_next(nm_i, lim);
1054 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim);
1055 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH)
1058 iru.iru_pidx = nic_i_start;
1061 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1062 if (fl->ifl_sds.ifsd_map == NULL) {
1063 nic_i_start = nic_i;
1066 nic_i = nic_i_start;
1067 for (n = 0; n < iru.iru_count; n++) {
1068 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i],
1069 BUS_DMASYNC_PREREAD);
1070 nic_i = nm_next(nic_i, lim);
1072 nic_i_start = nic_i;
1074 kring->nr_hwcur = head;
1076 if (fl->ifl_sds.ifsd_map)
1077 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1080 * IMPORTANT: we must leave one free slot in the ring,
1081 * so move nic_i back by one unit
1083 nic_i = nm_prev(nic_i, lim);
1084 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
1088 return netmap_ring_reinit(kring);
1092 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1094 struct ifnet *ifp = na->ifp;
1095 if_ctx_t ctx = ifp->if_softc;
1099 IFDI_INTR_ENABLE(ctx);
1101 IFDI_INTR_DISABLE(ctx);
1108 iflib_netmap_attach(if_ctx_t ctx)
1110 struct netmap_adapter na;
1111 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1113 bzero(&na, sizeof(na));
1115 na.ifp = ctx->ifc_ifp;
1116 na.na_flags = NAF_BDG_MAYSLEEP;
1117 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1118 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1120 na.num_tx_desc = scctx->isc_ntxd[0];
1121 na.num_rx_desc = scctx->isc_nrxd[0];
1122 na.nm_txsync = iflib_netmap_txsync;
1123 na.nm_rxsync = iflib_netmap_rxsync;
1124 na.nm_register = iflib_netmap_register;
1125 na.nm_intr = iflib_netmap_intr;
1126 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1127 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1128 return (netmap_attach(&na));
1132 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1134 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1135 struct netmap_slot *slot;
1137 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1140 if (txq->ift_sds.ifsd_map == NULL)
1143 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1146 * In netmap mode, set the map for the packet buffer.
1147 * NOTE: Some drivers (not this one) also need to set
1148 * the physical buffer address in the NIC ring.
1149 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1150 * netmap slot index, si
1152 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1153 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1157 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1159 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1160 struct netmap_slot *slot;
1161 struct if_rxd_update iru;
1165 uint32_t i, j, pidx_start;
1167 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1170 fl = &rxq->ifr_fl[0];
1171 map = fl->ifl_sds.ifsd_map;
1172 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0];
1173 iru.iru_paddrs = fl->ifl_bus_addrs;
1174 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1175 iru.iru_idxs = fl->ifl_rxd_idxs;
1176 iru.iru_qsidx = rxq->ifr_id;
1177 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size;
1180 for (pidx_start = i = j = 0; i < nrxd; i++, j++) {
1181 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i);
1184 fl->ifl_rxd_idxs[j] = i;
1185 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]);
1187 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr);
1191 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1)
1194 iru.iru_pidx = pidx_start;
1198 MPASS(pidx_start + j <= nrxd);
1199 /* Update descriptors and the cached value */
1200 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1202 /* preserve queue */
1203 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) {
1204 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1205 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1206 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t);
1208 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1);
1211 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1214 #define iflib_netmap_txq_init(ctx, txq)
1215 #define iflib_netmap_rxq_init(ctx, rxq)
1216 #define iflib_netmap_detach(ifp)
1218 #define iflib_netmap_attach(ctx) (0)
1219 #define netmap_rx_irq(ifp, qid, budget) (0)
1220 #define netmap_tx_irq(ifp, qid) do {} while (0)
1224 #if defined(__i386__) || defined(__amd64__)
1225 static __inline void
1228 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1235 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1239 *(bus_addr_t *) arg = segs[0].ds_addr;
1243 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1246 if_shared_ctx_t sctx = ctx->ifc_sctx;
1247 device_t dev = ctx->ifc_dev;
1249 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1251 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1252 sctx->isc_q_align, 0, /* alignment, bounds */
1253 BUS_SPACE_MAXADDR, /* lowaddr */
1254 BUS_SPACE_MAXADDR, /* highaddr */
1255 NULL, NULL, /* filter, filterarg */
1258 size, /* maxsegsize */
1259 BUS_DMA_ALLOCNOW, /* flags */
1260 NULL, /* lockfunc */
1265 "%s: bus_dma_tag_create failed: %d\n",
1270 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1271 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1274 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1275 __func__, (uintmax_t)size, err);
1279 dma->idi_paddr = IF_BAD_DMA;
1280 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1281 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1282 if (err || dma->idi_paddr == IF_BAD_DMA) {
1284 "%s: bus_dmamap_load failed: %d\n",
1289 dma->idi_size = size;
1293 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1295 bus_dma_tag_destroy(dma->idi_tag);
1297 dma->idi_tag = NULL;
1303 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1306 iflib_dma_info_t *dmaiter;
1309 for (i = 0; i < count; i++, dmaiter++) {
1310 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1314 iflib_dma_free_multi(dmalist, i);
1319 iflib_dma_free(iflib_dma_info_t dma)
1321 if (dma->idi_tag == NULL)
1323 if (dma->idi_paddr != IF_BAD_DMA) {
1324 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1325 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1326 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1327 dma->idi_paddr = IF_BAD_DMA;
1329 if (dma->idi_vaddr != NULL) {
1330 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1331 dma->idi_vaddr = NULL;
1333 bus_dma_tag_destroy(dma->idi_tag);
1334 dma->idi_tag = NULL;
1338 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1341 iflib_dma_info_t *dmaiter = dmalist;
1343 for (i = 0; i < count; i++, dmaiter++)
1344 iflib_dma_free(*dmaiter);
1347 #ifdef EARLY_AP_STARTUP
1348 static const int iflib_started = 1;
1351 * We used to abuse the smp_started flag to decide if the queues have been
1352 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1353 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1354 * is set. Run a SYSINIT() strictly after that to just set a usable
1358 static int iflib_started;
1361 iflib_record_started(void *arg)
1366 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1367 iflib_record_started, NULL);
1371 iflib_fast_intr(void *arg)
1373 iflib_filter_info_t info = arg;
1374 struct grouptask *gtask = info->ifi_task;
1376 return (FILTER_HANDLED);
1378 DBG_COUNTER_INC(fast_intrs);
1379 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1380 return (FILTER_HANDLED);
1382 GROUPTASK_ENQUEUE(gtask);
1383 return (FILTER_HANDLED);
1387 iflib_fast_intr_rxtx(void *arg)
1389 iflib_filter_info_t info = arg;
1390 struct grouptask *gtask = info->ifi_task;
1391 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1396 return (FILTER_HANDLED);
1398 DBG_COUNTER_INC(fast_intrs);
1399 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1400 return (FILTER_HANDLED);
1402 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1403 qidx_t txqid = rxq->ifr_txqid[i];
1407 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1408 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1411 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1413 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1414 cidx = rxq->ifr_cq_cidx;
1416 cidx = rxq->ifr_fl[0].ifl_cidx;
1417 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1418 GROUPTASK_ENQUEUE(gtask);
1420 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1421 return (FILTER_HANDLED);
1426 iflib_fast_intr_ctx(void *arg)
1428 iflib_filter_info_t info = arg;
1429 struct grouptask *gtask = info->ifi_task;
1432 return (FILTER_HANDLED);
1434 DBG_COUNTER_INC(fast_intrs);
1435 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1436 return (FILTER_HANDLED);
1438 GROUPTASK_ENQUEUE(gtask);
1439 return (FILTER_HANDLED);
1443 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1444 driver_filter_t filter, driver_intr_t handler, void *arg,
1448 struct resource *res;
1450 device_t dev = ctx->ifc_dev;
1453 if (ctx->ifc_flags & IFC_LEGACY)
1454 flags |= RF_SHAREABLE;
1457 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1460 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1464 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1465 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1466 filter, handler, arg, &tag);
1469 "failed to setup interrupt for rid %d, name %s: %d\n",
1470 rid, name ? name : "unknown", rc);
1473 bus_describe_intr(dev, res, tag, "%s", name);
1480 /*********************************************************************
1482 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1483 * the information needed to transmit a packet on the wire. This is
1484 * called only once at attach, setup is done every reset.
1486 **********************************************************************/
1489 iflib_txsd_alloc(iflib_txq_t txq)
1491 if_ctx_t ctx = txq->ift_ctx;
1492 if_shared_ctx_t sctx = ctx->ifc_sctx;
1493 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1494 device_t dev = ctx->ifc_dev;
1495 int err, nsegments, ntsosegments;
1497 nsegments = scctx->isc_tx_nsegments;
1498 ntsosegments = scctx->isc_tx_tso_segments_max;
1499 MPASS(scctx->isc_ntxd[0] > 0);
1500 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1501 MPASS(nsegments > 0);
1502 MPASS(ntsosegments > 0);
1504 * Setup DMA descriptor areas.
1506 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1507 1, 0, /* alignment, bounds */
1508 BUS_SPACE_MAXADDR, /* lowaddr */
1509 BUS_SPACE_MAXADDR, /* highaddr */
1510 NULL, NULL, /* filter, filterarg */
1511 sctx->isc_tx_maxsize, /* maxsize */
1512 nsegments, /* nsegments */
1513 sctx->isc_tx_maxsegsize, /* maxsegsize */
1515 NULL, /* lockfunc */
1516 NULL, /* lockfuncarg */
1517 &txq->ift_desc_tag))) {
1518 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1519 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1520 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1523 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1524 1, 0, /* alignment, bounds */
1525 BUS_SPACE_MAXADDR, /* lowaddr */
1526 BUS_SPACE_MAXADDR, /* highaddr */
1527 NULL, NULL, /* filter, filterarg */
1528 scctx->isc_tx_tso_size_max, /* maxsize */
1529 ntsosegments, /* nsegments */
1530 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1532 NULL, /* lockfunc */
1533 NULL, /* lockfuncarg */
1534 &txq->ift_tso_desc_tag))) {
1535 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1539 if (!(txq->ift_sds.ifsd_flags =
1540 (uint8_t *) malloc(sizeof(uint8_t) *
1541 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1542 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1546 if (!(txq->ift_sds.ifsd_m =
1547 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1548 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1549 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1554 /* Create the descriptor buffer dma maps */
1555 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1556 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1559 if (!(txq->ift_sds.ifsd_map =
1560 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1561 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1566 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1567 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1569 device_printf(dev, "Unable to create TX DMA map\n");
1576 /* We free all, it handles case where we are in the middle */
1577 iflib_tx_structures_free(ctx);
1582 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1587 if (txq->ift_sds.ifsd_map != NULL)
1588 map = txq->ift_sds.ifsd_map[i];
1590 bus_dmamap_unload(txq->ift_desc_tag, map);
1591 bus_dmamap_destroy(txq->ift_desc_tag, map);
1592 txq->ift_sds.ifsd_map[i] = NULL;
1597 iflib_txq_destroy(iflib_txq_t txq)
1599 if_ctx_t ctx = txq->ift_ctx;
1601 for (int i = 0; i < txq->ift_size; i++)
1602 iflib_txsd_destroy(ctx, txq, i);
1603 if (txq->ift_sds.ifsd_map != NULL) {
1604 free(txq->ift_sds.ifsd_map, M_IFLIB);
1605 txq->ift_sds.ifsd_map = NULL;
1607 if (txq->ift_sds.ifsd_m != NULL) {
1608 free(txq->ift_sds.ifsd_m, M_IFLIB);
1609 txq->ift_sds.ifsd_m = NULL;
1611 if (txq->ift_sds.ifsd_flags != NULL) {
1612 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1613 txq->ift_sds.ifsd_flags = NULL;
1615 if (txq->ift_desc_tag != NULL) {
1616 bus_dma_tag_destroy(txq->ift_desc_tag);
1617 txq->ift_desc_tag = NULL;
1619 if (txq->ift_tso_desc_tag != NULL) {
1620 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1621 txq->ift_tso_desc_tag = NULL;
1626 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1630 mp = &txq->ift_sds.ifsd_m[i];
1634 if (txq->ift_sds.ifsd_map != NULL) {
1635 bus_dmamap_sync(txq->ift_desc_tag,
1636 txq->ift_sds.ifsd_map[i],
1637 BUS_DMASYNC_POSTWRITE);
1638 bus_dmamap_unload(txq->ift_desc_tag,
1639 txq->ift_sds.ifsd_map[i]);
1642 DBG_COUNTER_INC(tx_frees);
1647 iflib_txq_setup(iflib_txq_t txq)
1649 if_ctx_t ctx = txq->ift_ctx;
1650 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1651 iflib_dma_info_t di;
1654 /* Set number of descriptors available */
1655 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1656 /* XXX make configurable */
1657 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1660 txq->ift_cidx_processed = 0;
1661 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1662 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1664 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1665 bzero((void *)di->idi_vaddr, di->idi_size);
1667 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1668 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1669 bus_dmamap_sync(di->idi_tag, di->idi_map,
1670 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1674 /*********************************************************************
1676 * Allocate memory for rx_buffer structures. Since we use one
1677 * rx_buffer per received packet, the maximum number of rx_buffer's
1678 * that we'll need is equal to the number of receive descriptors
1679 * that we've allocated.
1681 **********************************************************************/
1683 iflib_rxsd_alloc(iflib_rxq_t rxq)
1685 if_ctx_t ctx = rxq->ifr_ctx;
1686 if_shared_ctx_t sctx = ctx->ifc_sctx;
1687 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1688 device_t dev = ctx->ifc_dev;
1692 MPASS(scctx->isc_nrxd[0] > 0);
1693 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1696 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1697 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1698 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1699 1, 0, /* alignment, bounds */
1700 BUS_SPACE_MAXADDR, /* lowaddr */
1701 BUS_SPACE_MAXADDR, /* highaddr */
1702 NULL, NULL, /* filter, filterarg */
1703 sctx->isc_rx_maxsize, /* maxsize */
1704 sctx->isc_rx_nsegments, /* nsegments */
1705 sctx->isc_rx_maxsegsize, /* maxsegsize */
1707 NULL, /* lockfunc */
1711 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1715 if (!(fl->ifl_sds.ifsd_flags =
1716 (uint8_t *) malloc(sizeof(uint8_t) *
1717 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1718 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1722 if (!(fl->ifl_sds.ifsd_m =
1723 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1724 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1725 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1729 if (!(fl->ifl_sds.ifsd_cl =
1730 (caddr_t *) malloc(sizeof(caddr_t) *
1731 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1732 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1737 /* Create the descriptor buffer dma maps */
1738 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1739 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1742 if (!(fl->ifl_sds.ifsd_map =
1743 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1744 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1749 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1750 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1752 device_printf(dev, "Unable to create RX buffer DMA map\n");
1761 iflib_rx_structures_free(ctx);
1767 * Internal service routines
1770 struct rxq_refill_cb_arg {
1772 bus_dma_segment_t seg;
1777 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1779 struct rxq_refill_cb_arg *cb_arg = arg;
1781 cb_arg->error = error;
1782 cb_arg->seg = segs[0];
1783 cb_arg->nseg = nseg;
1788 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1790 #define IS_DMAR(ctx) (0)
1794 * rxq_refill - refill an rxq free-buffer list
1795 * @ctx: the iflib context
1796 * @rxq: the free-list to refill
1797 * @n: the number of new buffers to allocate
1799 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1800 * The caller must assure that @n does not exceed the queue's capacity.
1803 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1806 int idx, frag_idx = fl->ifl_fragidx;
1807 int pidx = fl->ifl_pidx;
1811 struct if_rxd_update iru;
1812 bus_dmamap_t *sd_map;
1817 sd_m = fl->ifl_sds.ifsd_m;
1818 sd_map = fl->ifl_sds.ifsd_map;
1819 sd_cl = fl->ifl_sds.ifsd_cl;
1820 sd_flags = fl->ifl_sds.ifsd_flags;
1825 MPASS(fl->ifl_credits + n <= fl->ifl_size);
1827 if (pidx < fl->ifl_cidx)
1828 MPASS(pidx + n <= fl->ifl_cidx);
1829 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size))
1830 MPASS(fl->ifl_gen == 0);
1831 if (pidx > fl->ifl_cidx)
1832 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1834 DBG_COUNTER_INC(fl_refills);
1836 DBG_COUNTER_INC(fl_refills_large);
1837 iru.iru_paddrs = fl->ifl_bus_addrs;
1838 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1839 iru.iru_idxs = fl->ifl_rxd_idxs;
1840 iru.iru_qsidx = fl->ifl_rxq->ifr_id;
1841 iru.iru_buf_size = fl->ifl_buf_size;
1842 iru.iru_flidx = fl->ifl_id;
1845 * We allocate an uninitialized mbuf + cluster, mbuf is
1846 * initialized after rx.
1848 * If the cluster is still set then we know a minimum sized packet was received
1850 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1851 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1852 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1853 if ((cl = sd_cl[frag_idx]) == NULL) {
1854 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1857 fl->ifl_cl_enqueued++;
1860 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1864 fl->ifl_m_enqueued++;
1867 DBG_COUNTER_INC(rx_allocs);
1868 #if defined(__i386__) || defined(__amd64__)
1869 if (!IS_DMAR(ctx)) {
1870 bus_addr = pmap_kextract((vm_offset_t)cl);
1874 struct rxq_refill_cb_arg cb_arg;
1879 MPASS(sd_map != NULL);
1880 MPASS(sd_map[frag_idx] != NULL);
1881 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1882 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1883 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1884 BUS_DMASYNC_PREREAD);
1886 if (err != 0 || cb_arg.error) {
1890 if (fl->ifl_zone == zone_pack)
1891 uma_zfree(fl->ifl_zone, cl);
1896 bus_addr = cb_arg.seg.ds_addr;
1898 bit_set(fl->ifl_rx_bitmap, frag_idx);
1899 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1901 MPASS(sd_m[frag_idx] == NULL);
1902 sd_cl[frag_idx] = cl;
1904 fl->ifl_rxd_idxs[i] = frag_idx;
1905 fl->ifl_bus_addrs[i] = bus_addr;
1906 fl->ifl_vm_addrs[i] = cl;
1909 MPASS(fl->ifl_credits <= fl->ifl_size);
1910 if (++idx == fl->ifl_size) {
1914 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1915 iru.iru_pidx = pidx;
1917 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1925 DBG_COUNTER_INC(rxd_flush);
1926 if (fl->ifl_pidx == 0)
1927 pidx = fl->ifl_size - 1;
1929 pidx = fl->ifl_pidx - 1;
1932 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1933 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1934 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1935 fl->ifl_fragidx = frag_idx;
1938 static __inline void
1939 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1941 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1942 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1944 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1947 MPASS(fl->ifl_credits <= fl->ifl_size);
1948 MPASS(reclaimable == delta);
1950 if (reclaimable > 0)
1951 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1955 iflib_fl_bufs_free(iflib_fl_t fl)
1957 iflib_dma_info_t idi = fl->ifl_ifdi;
1960 for (i = 0; i < fl->ifl_size; i++) {
1961 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1962 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1963 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1965 if (*sd_flags & RX_SW_DESC_INUSE) {
1966 if (fl->ifl_sds.ifsd_map != NULL) {
1967 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1968 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1969 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1971 if (*sd_m != NULL) {
1972 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1973 uma_zfree(zone_mbuf, *sd_m);
1976 uma_zfree(fl->ifl_zone, *sd_cl);
1979 MPASS(*sd_cl == NULL);
1980 MPASS(*sd_m == NULL);
1983 fl->ifl_m_dequeued++;
1984 fl->ifl_cl_dequeued++;
1990 for (i = 0; i < fl->ifl_size; i++) {
1991 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
1992 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
1993 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
1997 * Reset free list values
1999 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2000 bzero(idi->idi_vaddr, idi->idi_size);
2003 /*********************************************************************
2005 * Initialize a receive ring and its buffers.
2007 **********************************************************************/
2009 iflib_fl_setup(iflib_fl_t fl)
2011 iflib_rxq_t rxq = fl->ifl_rxq;
2012 if_ctx_t ctx = rxq->ifr_ctx;
2013 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2015 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size);
2017 ** Free current RX buffer structs and their mbufs
2019 iflib_fl_bufs_free(fl);
2020 /* Now replenish the mbufs */
2021 MPASS(fl->ifl_credits == 0);
2023 * XXX don't set the max_frame_size to larger
2024 * than the hardware can handle
2026 if (sctx->isc_max_frame_size <= 2048)
2027 fl->ifl_buf_size = MCLBYTES;
2028 #ifndef CONTIGMALLOC_WORKS
2030 fl->ifl_buf_size = MJUMPAGESIZE;
2032 else if (sctx->isc_max_frame_size <= 4096)
2033 fl->ifl_buf_size = MJUMPAGESIZE;
2034 else if (sctx->isc_max_frame_size <= 9216)
2035 fl->ifl_buf_size = MJUM9BYTES;
2037 fl->ifl_buf_size = MJUM16BYTES;
2039 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2040 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2041 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2042 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2045 /* avoid pre-allocating zillions of clusters to an idle card
2046 * potentially speeding up attach
2048 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2049 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2050 if (min(128, fl->ifl_size) != fl->ifl_credits)
2056 MPASS(fl->ifl_ifdi != NULL);
2057 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2058 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2062 /*********************************************************************
2064 * Free receive ring data structures
2066 **********************************************************************/
2068 iflib_rx_sds_free(iflib_rxq_t rxq)
2073 if (rxq->ifr_fl != NULL) {
2074 for (i = 0; i < rxq->ifr_nfl; i++) {
2075 fl = &rxq->ifr_fl[i];
2076 if (fl->ifl_desc_tag != NULL) {
2077 bus_dma_tag_destroy(fl->ifl_desc_tag);
2078 fl->ifl_desc_tag = NULL;
2080 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2081 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2082 /* XXX destroy maps first */
2083 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2084 fl->ifl_sds.ifsd_m = NULL;
2085 fl->ifl_sds.ifsd_cl = NULL;
2086 fl->ifl_sds.ifsd_map = NULL;
2088 free(rxq->ifr_fl, M_IFLIB);
2090 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2095 * MI independent logic
2099 iflib_timer(void *arg)
2101 iflib_txq_t txq = arg;
2102 if_ctx_t ctx = txq->ift_ctx;
2103 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2105 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2108 ** Check on the state of the TX queue(s), this
2109 ** can be done without the lock because its RO
2110 ** and the HUNG state will be static if set.
2112 IFDI_TIMER(ctx, txq->ift_id);
2113 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2114 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2115 (sctx->isc_pause_frames == 0)))
2118 if (ifmp_ring_is_stalled(txq->ift_br))
2119 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2120 txq->ift_cleaned_prev = txq->ift_cleaned;
2121 /* handle any laggards */
2122 if (txq->ift_db_pending)
2123 GROUPTASK_ENQUEUE(&txq->ift_task);
2125 sctx->isc_pause_frames = 0;
2126 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2127 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2131 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2132 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2133 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2135 IFDI_WATCHDOG_RESET(ctx);
2136 ctx->ifc_watchdog_events++;
2138 ctx->ifc_flags |= IFC_DO_RESET;
2139 iflib_admin_intr_deferred(ctx);
2144 iflib_init_locked(if_ctx_t ctx)
2146 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2147 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2148 if_t ifp = ctx->ifc_ifp;
2152 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2155 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2156 IFDI_INTR_DISABLE(ctx);
2158 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2159 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2160 /* Set hardware offload abilities */
2161 if_clearhwassist(ifp);
2162 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2163 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2164 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2165 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2166 if (if_getcapenable(ifp) & IFCAP_TSO4)
2167 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2168 if (if_getcapenable(ifp) & IFCAP_TSO6)
2169 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2171 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2173 callout_stop(&txq->ift_timer);
2174 CALLOUT_UNLOCK(txq);
2175 iflib_netmap_txq_init(ctx, txq);
2178 i = if_getdrvflags(ifp);
2181 MPASS(if_getdrvflags(ifp) == i);
2182 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2183 /* XXX this should really be done on a per-queue basis */
2184 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2185 MPASS(rxq->ifr_id == i);
2186 iflib_netmap_rxq_init(ctx, rxq);
2189 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2190 if (iflib_fl_setup(fl)) {
2191 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2197 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2198 IFDI_INTR_ENABLE(ctx);
2199 txq = ctx->ifc_txqs;
2200 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2201 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2202 txq->ift_timer.c_cpu);
2206 iflib_media_change(if_t ifp)
2208 if_ctx_t ctx = if_getsoftc(ifp);
2212 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2213 iflib_init_locked(ctx);
2219 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2221 if_ctx_t ctx = if_getsoftc(ifp);
2224 IFDI_UPDATE_ADMIN_STATUS(ctx);
2225 IFDI_MEDIA_STATUS(ctx, ifmr);
2230 iflib_stop(if_ctx_t ctx)
2232 iflib_txq_t txq = ctx->ifc_txqs;
2233 iflib_rxq_t rxq = ctx->ifc_rxqs;
2234 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2235 iflib_dma_info_t di;
2239 /* Tell the stack that the interface is no longer active */
2240 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2242 IFDI_INTR_DISABLE(ctx);
2247 iflib_debug_reset();
2248 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2249 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2250 /* make sure all transmitters have completed before proceeding XXX */
2252 /* clean any enqueued buffers */
2253 iflib_ifmp_purge(txq);
2254 /* Free any existing tx buffers. */
2255 for (j = 0; j < txq->ift_size; j++) {
2256 iflib_txsd_free(ctx, txq, j);
2258 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2259 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2260 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2261 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2262 txq->ift_pullups = 0;
2263 ifmp_ring_reset_stats(txq->ift_br);
2264 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2265 bzero((void *)di->idi_vaddr, di->idi_size);
2267 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2268 /* make sure all transmitters have completed before proceeding XXX */
2270 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2271 bzero((void *)di->idi_vaddr, di->idi_size);
2272 /* also resets the free lists pidx/cidx */
2273 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2274 iflib_fl_bufs_free(fl);
2278 static inline caddr_t
2279 calc_next_rxd(iflib_fl_t fl, int cidx)
2283 caddr_t start, end, cur, next;
2285 nrxd = fl->ifl_size;
2286 size = fl->ifl_rxd_size;
2287 start = fl->ifl_ifdi->idi_vaddr;
2289 if (__predict_false(size == 0))
2291 cur = start + size*cidx;
2292 end = start + size*nrxd;
2293 next = CACHE_PTR_NEXT(cur);
2294 return (next < end ? next : start);
2298 prefetch_pkts(iflib_fl_t fl, int cidx)
2301 int nrxd = fl->ifl_size;
2305 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2306 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2307 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2308 next_rxd = calc_next_rxd(fl, cidx);
2310 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2311 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2312 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2313 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2314 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2315 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2316 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2317 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2321 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2326 iflib_dma_info_t di;
2330 flid = irf->irf_flid;
2331 cidx = irf->irf_idx;
2332 fl = &rxq->ifr_fl[flid];
2334 sd->ifsd_cidx = cidx;
2335 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2336 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2339 fl->ifl_m_dequeued++;
2341 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2342 prefetch_pkts(fl, cidx);
2343 if (fl->ifl_sds.ifsd_map != NULL) {
2344 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2345 prefetch(&fl->ifl_sds.ifsd_map[next]);
2346 map = fl->ifl_sds.ifsd_map[cidx];
2348 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2349 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2350 bus_dmamap_sync(di->idi_tag, di->idi_map,
2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2353 /* not valid assert if bxe really does SGE from non-contiguous elements */
2354 MPASS(fl->ifl_cidx == cidx);
2356 bus_dmamap_unload(fl->ifl_desc_tag, map);
2358 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2359 if (__predict_false(fl->ifl_cidx == 0))
2362 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2364 bit_clear(fl->ifl_rx_bitmap, cidx);
2367 static struct mbuf *
2368 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2370 int i, padlen , flags;
2371 struct mbuf *m, *mh, *mt;
2377 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2379 MPASS(*sd->ifsd_cl != NULL);
2380 MPASS(*sd->ifsd_m != NULL);
2382 /* Don't include zero-length frags */
2383 if (ri->iri_frags[i].irf_len == 0) {
2384 /* XXX we can save the cluster here, but not the mbuf */
2385 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2386 m_free(*sd->ifsd_m);
2393 flags = M_PKTHDR|M_EXT;
2395 padlen = ri->iri_pad;
2400 /* assuming padding is only on the first fragment */
2404 *sd->ifsd_cl = NULL;
2406 /* Can these two be made one ? */
2407 m_init(m, M_NOWAIT, MT_DATA, flags);
2408 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2410 * These must follow m_init and m_cljset
2412 m->m_data += padlen;
2413 ri->iri_len -= padlen;
2414 m->m_len = ri->iri_frags[i].irf_len;
2415 } while (++i < ri->iri_nfrags);
2421 * Process one software descriptor
2423 static struct mbuf *
2424 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2429 /* should I merge this back in now that the two paths are basically duplicated? */
2430 if (ri->iri_nfrags == 1 &&
2431 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2432 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2435 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2436 #ifndef __NO_STRICT_ALIGNMENT
2440 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2441 m->m_len = ri->iri_frags[0].irf_len;
2443 m = assemble_segments(rxq, ri, &sd);
2445 m->m_pkthdr.len = ri->iri_len;
2446 m->m_pkthdr.rcvif = ri->iri_ifp;
2447 m->m_flags |= ri->iri_flags;
2448 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2449 m->m_pkthdr.flowid = ri->iri_flowid;
2450 M_HASHTYPE_SET(m, ri->iri_rsstype);
2451 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2452 m->m_pkthdr.csum_data = ri->iri_csum_data;
2457 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2459 if_ctx_t ctx = rxq->ifr_ctx;
2460 if_shared_ctx_t sctx = ctx->ifc_sctx;
2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2464 struct if_rxd_info ri;
2465 int err, budget_left, rx_bytes, rx_pkts;
2471 * XXX early demux data packets so that if_input processing only handles
2472 * acks in interrupt context
2474 struct mbuf *m, *mh, *mt, *mf;
2479 rx_pkts = rx_bytes = 0;
2480 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2481 cidxp = &rxq->ifr_cq_cidx;
2483 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2484 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2485 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2486 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2487 DBG_COUNTER_INC(rx_unavail);
2491 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2492 if (__predict_false(!CTX_ACTIVE(ctx))) {
2493 DBG_COUNTER_INC(rx_ctx_inactive);
2497 * Reset client set fields to their default values
2500 ri.iri_qsidx = rxq->ifr_id;
2501 ri.iri_cidx = *cidxp;
2503 ri.iri_frags = rxq->ifr_frags;
2504 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2508 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2509 *cidxp = ri.iri_cidx;
2510 /* Update our consumer index */
2511 /* XXX NB: shurd - check if this is still safe */
2512 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2513 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2514 rxq->ifr_cq_gen = 0;
2516 /* was this only a completion queue message? */
2517 if (__predict_false(ri.iri_nfrags == 0))
2520 MPASS(ri.iri_nfrags != 0);
2521 MPASS(ri.iri_len != 0);
2523 /* will advance the cidx on the corresponding free lists */
2524 m = iflib_rxd_pkt_get(rxq, &ri);
2525 if (avail == 0 && budget_left)
2526 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2528 if (__predict_false(m == NULL)) {
2529 DBG_COUNTER_INC(rx_mbuf_null);
2532 /* imm_pkt: -- cxgb */
2540 /* make sure that we can refill faster than drain */
2541 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2542 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2544 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2546 while (mh != NULL) {
2551 m->m_nextpkt = NULL;
2552 #ifndef __NO_STRICT_ALIGNMENT
2553 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2556 rx_bytes += m->m_pkthdr.len;
2558 #if defined(INET6) || defined(INET)
2559 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) {
2570 ifp->if_input(ifp, mf);
2571 DBG_COUNTER_INC(rx_if_input);
2574 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2575 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2578 * Flush any outstanding LRO work
2580 #if defined(INET6) || defined(INET)
2581 tcp_lro_flush_all(&rxq->ifr_lc);
2585 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2588 ctx->ifc_flags |= IFC_DO_RESET;
2589 iflib_admin_intr_deferred(ctx);
2594 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2595 static inline qidx_t
2596 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2598 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2599 qidx_t minthresh = txq->ift_size / 8;
2600 if (in_use > 4*minthresh)
2601 return (notify_count);
2602 if (in_use > 2*minthresh)
2603 return (notify_count >> 1);
2604 if (in_use > minthresh)
2605 return (notify_count >> 3);
2609 static inline qidx_t
2610 txq_max_rs_deferred(iflib_txq_t txq)
2612 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2613 qidx_t minthresh = txq->ift_size / 8;
2614 if (txq->ift_in_use > 4*minthresh)
2615 return (notify_count);
2616 if (txq->ift_in_use > 2*minthresh)
2617 return (notify_count >> 1);
2618 if (txq->ift_in_use > minthresh)
2619 return (notify_count >> 2);
2623 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2624 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2626 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2627 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2628 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2630 /* forward compatibility for cxgb */
2631 #define FIRST_QSET(ctx) 0
2632 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2633 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2634 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2635 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2637 /* XXX we should be setting this to something other than zero */
2638 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2639 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2642 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2648 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2649 if (ring || txq->ift_db_pending >= max) {
2650 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2651 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2652 txq->ift_db_pending = txq->ift_npending = 0;
2660 print_pkt(if_pkt_info_t pi)
2662 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2663 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2664 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2665 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2666 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2667 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2671 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2672 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2675 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2677 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2678 struct ether_vlan_header *eh;
2682 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2683 M_WRITABLE(m) == 0) {
2684 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2693 * Determine where frame payload starts.
2694 * Jump over vlan headers if already present,
2695 * helpful for QinQ too.
2697 if (__predict_false(m->m_len < sizeof(*eh))) {
2699 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2702 eh = mtod(m, struct ether_vlan_header *);
2703 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2704 pi->ipi_etype = ntohs(eh->evl_proto);
2705 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2707 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2708 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2711 if (if_getmtu(txq->ift_ctx->ifc_ifp) >= pi->ipi_len) {
2712 pi->ipi_csum_flags &= ~(CSUM_IP_TSO|CSUM_IP6_TSO);
2715 switch (pi->ipi_etype) {
2719 struct ip *ip = NULL;
2720 struct tcphdr *th = NULL;
2723 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2724 if (__predict_false(m->m_len < minthlen)) {
2726 * if this code bloat is causing too much of a hit
2727 * move it to a separate function and mark it noinline
2729 if (m->m_len == pi->ipi_ehdrlen) {
2732 if (n->m_len >= sizeof(*ip)) {
2733 ip = (struct ip *)n->m_data;
2734 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2735 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2738 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2740 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2744 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2746 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2747 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2748 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2751 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2752 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2753 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2755 pi->ipi_ip_hlen = ip->ip_hl << 2;
2756 pi->ipi_ipproto = ip->ip_p;
2757 pi->ipi_flags |= IPI_TX_IPV4;
2759 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2763 if (pi->ipi_ipproto == IPPROTO_TCP) {
2764 if (__predict_false(th == NULL)) {
2766 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2768 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2770 pi->ipi_tcp_hflags = th->th_flags;
2771 pi->ipi_tcp_hlen = th->th_off << 2;
2772 pi->ipi_tcp_seq = th->th_seq;
2774 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2776 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2777 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2778 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2779 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2781 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2788 case ETHERTYPE_IPV6:
2790 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2792 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2794 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2795 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2798 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2800 /* XXX-BZ this will go badly in case of ext hdrs. */
2801 pi->ipi_ipproto = ip6->ip6_nxt;
2802 pi->ipi_flags |= IPI_TX_IPV6;
2805 if (pi->ipi_ipproto == IPPROTO_TCP) {
2806 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2807 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2810 pi->ipi_tcp_hflags = th->th_flags;
2811 pi->ipi_tcp_hlen = th->th_off << 2;
2814 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2817 * The corresponding flag is set by the stack in the IPv4
2818 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2819 * So, set it here because the rest of the flow requires it.
2821 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2822 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2823 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2829 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2830 pi->ipi_ip_hlen = 0;
2838 static __noinline struct mbuf *
2839 collapse_pkthdr(struct mbuf *m0)
2841 struct mbuf *m, *m_next, *tmp;
2845 while (m_next != NULL && m_next->m_len == 0) {
2849 m_next = m_next->m_next;
2853 if ((m_next->m_flags & M_EXT) == 0) {
2854 m = m_defrag(m, M_NOWAIT);
2856 tmp = m_next->m_next;
2857 memcpy(m_next, m, MPKTHSIZE);
2865 * If dodgy hardware rejects the scatter gather chain we've handed it
2866 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2869 static __noinline struct mbuf *
2870 iflib_remove_mbuf(iflib_txq_t txq)
2873 struct mbuf *m, *mh, **ifsd_m;
2875 pidx = txq->ift_pidx;
2876 ifsd_m = txq->ift_sds.ifsd_m;
2877 ntxd = txq->ift_size;
2878 mh = m = ifsd_m[pidx];
2879 ifsd_m[pidx] = NULL;
2881 txq->ift_dequeued++;
2886 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2888 txq->ift_dequeued++;
2897 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2898 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2899 int max_segs, int flags)
2902 if_shared_ctx_t sctx;
2903 if_softc_ctx_t scctx;
2904 int i, next, pidx, err, ntxd, count;
2905 struct mbuf *m, *tmp, **ifsd_m;
2910 * Please don't ever do this
2912 if (__predict_false(m->m_len == 0))
2913 *m0 = m = collapse_pkthdr(m);
2916 sctx = ctx->ifc_sctx;
2917 scctx = &ctx->ifc_softc_ctx;
2918 ifsd_m = txq->ift_sds.ifsd_m;
2919 ntxd = txq->ift_size;
2920 pidx = txq->ift_pidx;
2922 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2924 err = bus_dmamap_load_mbuf_sg(tag, map,
2925 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2928 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
2932 if (__predict_false(m->m_len <= 0)) {
2941 } while (m != NULL);
2942 if (count > *nsegs) {
2944 ifsd_m[pidx]->m_flags |= M_TOOBIG;
2950 next = (pidx + count) & (ntxd-1);
2951 MPASS(ifsd_m[next] == NULL);
2956 } while (m != NULL);
2958 int buflen, sgsize, maxsegsz, max_sgsize;
2964 if (m->m_pkthdr.csum_flags & CSUM_TSO)
2965 maxsegsz = scctx->isc_tx_tso_segsize_max;
2967 maxsegsz = sctx->isc_tx_maxsegsize;
2970 if (__predict_false(m->m_len <= 0)) {
2978 vaddr = (vm_offset_t)m->m_data;
2980 * see if we can't be smarter about physically
2981 * contiguous mappings
2983 next = (pidx + count) & (ntxd-1);
2984 MPASS(ifsd_m[next] == NULL);
2986 txq->ift_enqueued++;
2989 while (buflen > 0) {
2992 max_sgsize = MIN(buflen, maxsegsz);
2993 curaddr = pmap_kextract(vaddr);
2994 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
2995 sgsize = MIN(sgsize, max_sgsize);
2996 segs[i].ds_addr = curaddr;
2997 segs[i].ds_len = sgsize;
3005 } while (m != NULL);
3010 *m0 = iflib_remove_mbuf(txq);
3014 static inline caddr_t
3015 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3019 caddr_t start, end, cur, next;
3021 ntxd = txq->ift_size;
3022 size = txq->ift_txd_size[qid];
3023 start = txq->ift_ifdi[qid].idi_vaddr;
3025 if (__predict_false(size == 0))
3027 cur = start + size*cidx;
3028 end = start + size*ntxd;
3029 next = CACHE_PTR_NEXT(cur);
3030 return (next < end ? next : start);
3034 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3037 if_shared_ctx_t sctx;
3038 if_softc_ctx_t scctx;
3039 bus_dma_segment_t *segs;
3040 struct mbuf *m_head;
3043 struct if_pkt_info pi;
3045 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3046 bus_dma_tag_t desc_tag;
3048 segs = txq->ift_segs;
3050 sctx = ctx->ifc_sctx;
3051 scctx = &ctx->ifc_softc_ctx;
3052 segs = txq->ift_segs;
3053 ntxd = txq->ift_size;
3058 * If we're doing TSO the next descriptor to clean may be quite far ahead
3060 cidx = txq->ift_cidx;
3061 pidx = txq->ift_pidx;
3062 if (ctx->ifc_flags & IFC_PREFETCH) {
3063 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3064 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3065 next_txd = calc_next_txd(txq, cidx, 0);
3069 /* prefetch the next cache line of mbuf pointers and flags */
3070 prefetch(&txq->ift_sds.ifsd_m[next]);
3071 if (txq->ift_sds.ifsd_map != NULL) {
3072 prefetch(&txq->ift_sds.ifsd_map[next]);
3073 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3074 prefetch(&txq->ift_sds.ifsd_flags[next]);
3076 } else if (txq->ift_sds.ifsd_map != NULL)
3077 map = txq->ift_sds.ifsd_map[pidx];
3079 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3080 desc_tag = txq->ift_tso_desc_tag;
3081 max_segs = scctx->isc_tx_tso_segments_max;
3083 desc_tag = txq->ift_desc_tag;
3084 max_segs = scctx->isc_tx_nsegments;
3089 pi.ipi_len = m_head->m_pkthdr.len;
3090 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3091 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3092 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3094 pi.ipi_qsidx = txq->ift_id;
3096 /* deliberate bitwise OR to make one condition */
3097 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3098 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3104 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3106 if (__predict_false(err)) {
3109 /* try collapse once and defrag once */
3111 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3113 m_head = m_defrag(*m_headp, M_NOWAIT);
3115 if (__predict_false(m_head == NULL))
3117 txq->ift_mbuf_defrag++;
3122 txq->ift_no_tx_dma_setup++;
3125 txq->ift_no_tx_dma_setup++;
3127 DBG_COUNTER_INC(tx_frees);
3131 txq->ift_map_failed++;
3132 DBG_COUNTER_INC(encap_load_mbuf_fail);
3137 * XXX assumes a 1 to 1 relationship between segments and
3138 * descriptors - this does not hold true on all drivers, e.g.
3141 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3142 txq->ift_no_desc_avail++;
3144 bus_dmamap_unload(desc_tag, map);
3145 DBG_COUNTER_INC(encap_txq_avail_fail);
3146 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3147 GROUPTASK_ENQUEUE(&txq->ift_task);
3151 * On Intel cards we can greatly reduce the number of TX interrupts
3152 * we see by only setting report status on every Nth descriptor.
3153 * However, this also means that the driver will need to keep track
3154 * of the descriptors that RS was set on to check them for the DD bit.
3156 txq->ift_rs_pending += nsegs + 1;
3157 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3158 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3159 pi.ipi_flags |= IPI_TX_INTR;
3160 txq->ift_rs_pending = 0;
3164 pi.ipi_nsegs = nsegs;
3166 MPASS(pidx >= 0 && pidx < txq->ift_size);
3171 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3172 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3174 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3175 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3176 DBG_COUNTER_INC(tx_encap);
3177 MPASS(pi.ipi_new_pidx < txq->ift_size);
3179 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3180 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3181 ndesc += txq->ift_size;
3185 * drivers can need as many as
3188 MPASS(ndesc <= pi.ipi_nsegs + 2);
3189 MPASS(pi.ipi_new_pidx != pidx);
3191 txq->ift_in_use += ndesc;
3194 * We update the last software descriptor again here because there may
3195 * be a sentinel and/or there may be more mbufs than segments
3197 txq->ift_pidx = pi.ipi_new_pidx;
3198 txq->ift_npending += pi.ipi_ndescs;
3199 } else if (__predict_false(err == EFBIG && remap < 2)) {
3200 *m_headp = m_head = iflib_remove_mbuf(txq);
3202 txq->ift_txd_encap_efbig++;
3205 DBG_COUNTER_INC(encap_txd_encap_fail);
3209 txq->ift_mbuf_defrag_failed++;
3210 txq->ift_map_failed++;
3212 DBG_COUNTER_INC(tx_frees);
3218 iflib_tx_desc_free(iflib_txq_t txq, int n)
3221 uint32_t qsize, cidx, mask, gen;
3222 struct mbuf *m, **ifsd_m;
3223 uint8_t *ifsd_flags;
3224 bus_dmamap_t *ifsd_map;
3227 cidx = txq->ift_cidx;
3229 qsize = txq->ift_size;
3231 hasmap = txq->ift_sds.ifsd_map != NULL;
3232 ifsd_flags = txq->ift_sds.ifsd_flags;
3233 ifsd_m = txq->ift_sds.ifsd_m;
3234 ifsd_map = txq->ift_sds.ifsd_map;
3235 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3239 prefetch(ifsd_m[(cidx + 3) & mask]);
3240 prefetch(ifsd_m[(cidx + 4) & mask]);
3242 if (ifsd_m[cidx] != NULL) {
3243 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3244 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3245 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3247 * does it matter if it's not the TSO tag? If so we'll
3248 * have to add the type to flags
3250 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3251 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3253 if ((m = ifsd_m[cidx]) != NULL) {
3254 /* XXX we don't support any drivers that batch packets yet */
3255 MPASS(m->m_nextpkt == NULL);
3256 /* if the number of clusters exceeds the number of segments
3257 * there won't be space on the ring to save a pointer to each
3258 * cluster so we simply free the list here
3260 if (m->m_flags & M_TOOBIG) {
3265 ifsd_m[cidx] = NULL;
3267 txq->ift_dequeued++;
3269 DBG_COUNTER_INC(tx_frees);
3272 if (__predict_false(++cidx == qsize)) {
3277 txq->ift_cidx = cidx;
3282 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3285 if_ctx_t ctx = txq->ift_ctx;
3287 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3288 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3291 * Need a rate-limiting check so that this isn't called every time
3293 iflib_tx_credits_update(ctx, txq);
3294 reclaim = DESC_RECLAIMABLE(txq);
3296 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3298 if (iflib_verbose_debug) {
3299 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3300 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3307 iflib_tx_desc_free(txq, reclaim);
3308 txq->ift_cleaned += reclaim;
3309 txq->ift_in_use -= reclaim;
3314 static struct mbuf **
3315 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3318 struct mbuf **items;
3321 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3322 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3324 prefetch(items[(cidx + offset) & (size-1)]);
3325 if (remaining > 1) {
3326 prefetch(&items[next]);
3327 prefetch(items[(cidx + offset + 1) & (size-1)]);
3328 prefetch(items[(cidx + offset + 2) & (size-1)]);
3329 prefetch(items[(cidx + offset + 3) & (size-1)]);
3331 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3335 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3338 ifmp_ring_check_drainage(txq->ift_br, budget);
3342 iflib_txq_can_drain(struct ifmp_ring *r)
3344 iflib_txq_t txq = r->cookie;
3345 if_ctx_t ctx = txq->ift_ctx;
3347 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3348 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3352 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3354 iflib_txq_t txq = r->cookie;
3355 if_ctx_t ctx = txq->ift_ctx;
3356 struct ifnet *ifp = ctx->ifc_ifp;
3357 struct mbuf **mp, *m;
3358 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3359 int reclaimed, err, in_use_prev, desc_used;
3360 bool do_prefetch, ring, rang;
3362 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3363 !LINK_ACTIVE(ctx))) {
3364 DBG_COUNTER_INC(txq_drain_notready);
3367 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3368 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3369 avail = IDXDIFF(pidx, cidx, r->size);
3370 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3371 DBG_COUNTER_INC(txq_drain_flushing);
3372 for (i = 0; i < avail; i++) {
3373 m_free(r->items[(cidx + i) & (r->size-1)]);
3374 r->items[(cidx + i) & (r->size-1)] = NULL;
3379 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3380 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3382 callout_stop(&txq->ift_timer);
3383 CALLOUT_UNLOCK(txq);
3384 DBG_COUNTER_INC(txq_drain_oactive);
3388 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3389 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3390 count = MIN(avail, TX_BATCH_SIZE);
3392 if (iflib_verbose_debug)
3393 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3394 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3396 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3397 avail = TXQ_AVAIL(txq);
3398 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3399 int pidx_prev, rem = do_prefetch ? count - i : 0;
3401 mp = _ring_peek_one(r, cidx, i, rem);
3402 MPASS(mp != NULL && *mp != NULL);
3403 if (__predict_false(*mp == (struct mbuf *)txq)) {
3408 in_use_prev = txq->ift_in_use;
3409 pidx_prev = txq->ift_pidx;
3410 err = iflib_encap(txq, mp);
3411 if (__predict_false(err)) {
3412 DBG_COUNTER_INC(txq_drain_encapfail);
3413 /* no room - bail out */
3417 DBG_COUNTER_INC(txq_drain_encapfail);
3418 /* we can't send this packet - skip it */
3424 DBG_COUNTER_INC(tx_sent);
3425 bytes_sent += m->m_pkthdr.len;
3426 mcast_sent += !!(m->m_flags & M_MCAST);
3427 avail = TXQ_AVAIL(txq);
3429 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3430 desc_used += (txq->ift_in_use - in_use_prev);
3431 ETHER_BPF_MTAP(ifp, m);
3432 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3434 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3437 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3438 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3439 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3440 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3441 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3443 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3445 if (iflib_verbose_debug)
3446 printf("consumed=%d\n", consumed);
3452 iflib_txq_drain_always(struct ifmp_ring *r)
3458 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3466 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3468 callout_stop(&txq->ift_timer);
3469 CALLOUT_UNLOCK(txq);
3471 avail = IDXDIFF(pidx, cidx, r->size);
3472 for (i = 0; i < avail; i++) {
3473 mp = _ring_peek_one(r, cidx, i, avail - i);
3474 if (__predict_false(*mp == (struct mbuf *)txq))
3478 MPASS(ifmp_ring_is_stalled(r) == 0);
3483 iflib_ifmp_purge(iflib_txq_t txq)
3485 struct ifmp_ring *r;
3488 r->drain = iflib_txq_drain_free;
3489 r->can_drain = iflib_txq_drain_always;
3491 ifmp_ring_check_drainage(r, r->size);
3493 r->drain = iflib_txq_drain;
3494 r->can_drain = iflib_txq_can_drain;
3498 _task_fn_tx(void *context)
3500 iflib_txq_t txq = context;
3501 if_ctx_t ctx = txq->ift_ctx;
3502 struct ifnet *ifp = ctx->ifc_ifp;
3505 #ifdef IFLIB_DIAGNOSTICS
3506 txq->ift_cpu_exec_count[curcpu]++;
3508 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3510 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3511 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3512 netmap_tx_irq(ifp, txq->ift_id);
3513 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3516 if (txq->ift_db_pending)
3517 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3518 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3519 if (ctx->ifc_flags & IFC_LEGACY)
3520 IFDI_INTR_ENABLE(ctx);
3522 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3523 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3528 _task_fn_rx(void *context)
3530 iflib_rxq_t rxq = context;
3531 if_ctx_t ctx = rxq->ifr_ctx;
3536 #ifdef IFLIB_DIAGNOSTICS
3537 rxq->ifr_cpu_exec_count[curcpu]++;
3539 DBG_COUNTER_INC(task_fn_rxs);
3540 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3544 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3546 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3551 budget = ctx->ifc_sysctl_rx_budget;
3553 budget = 16; /* XXX */
3554 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3555 if (ctx->ifc_flags & IFC_LEGACY)
3556 IFDI_INTR_ENABLE(ctx);
3558 DBG_COUNTER_INC(rx_intr_enables);
3559 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3560 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3563 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3566 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3570 _task_fn_admin(void *context)
3572 if_ctx_t ctx = context;
3573 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3577 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) {
3578 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3584 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3586 callout_stop(&txq->ift_timer);
3587 CALLOUT_UNLOCK(txq);
3589 IFDI_UPDATE_ADMIN_STATUS(ctx);
3590 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3591 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3592 IFDI_LINK_INTR_ENABLE(ctx);
3593 if (ctx->ifc_flags & IFC_DO_RESET) {
3594 ctx->ifc_flags &= ~IFC_DO_RESET;
3595 iflib_if_init_locked(ctx);
3599 if (LINK_ACTIVE(ctx) == 0)
3601 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3602 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3607 _task_fn_iov(void *context)
3609 if_ctx_t ctx = context;
3611 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3615 IFDI_VFLR_HANDLE(ctx);
3620 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3623 if_int_delay_info_t info;
3626 info = (if_int_delay_info_t)arg1;
3627 ctx = info->iidi_ctx;
3628 info->iidi_req = req;
3629 info->iidi_oidp = oidp;
3631 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3636 /*********************************************************************
3640 **********************************************************************/
3643 iflib_if_init_locked(if_ctx_t ctx)
3646 iflib_init_locked(ctx);
3651 iflib_if_init(void *arg)
3656 iflib_if_init_locked(ctx);
3661 iflib_if_transmit(if_t ifp, struct mbuf *m)
3663 if_ctx_t ctx = if_getsoftc(ifp);
3668 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3669 DBG_COUNTER_INC(tx_frees);
3674 MPASS(m->m_nextpkt == NULL);
3676 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3677 qidx = QIDX(ctx, m);
3679 * XXX calculate buf_ring based on flowid (divvy up bits?)
3681 txq = &ctx->ifc_txqs[qidx];
3683 #ifdef DRIVER_BACKPRESSURE
3684 if (txq->ift_closed) {
3686 next = m->m_nextpkt;
3687 m->m_nextpkt = NULL;
3700 next = next->m_nextpkt;
3701 } while (next != NULL);
3703 if (count > nitems(marr))
3704 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3705 /* XXX check nextpkt */
3707 /* XXX simplify for now */
3708 DBG_COUNTER_INC(tx_frees);
3711 for (next = m, i = 0; next != NULL; i++) {
3713 next = next->m_nextpkt;
3714 mp[i]->m_nextpkt = NULL;
3717 DBG_COUNTER_INC(tx_seen);
3718 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3720 GROUPTASK_ENQUEUE(&txq->ift_task);
3722 /* support forthcoming later */
3723 #ifdef DRIVER_BACKPRESSURE
3724 txq->ift_closed = TRUE;
3726 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3734 iflib_if_qflush(if_t ifp)
3736 if_ctx_t ctx = if_getsoftc(ifp);
3737 iflib_txq_t txq = ctx->ifc_txqs;
3741 ctx->ifc_flags |= IFC_QFLUSH;
3743 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3744 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3745 iflib_txq_check_drain(txq, 0);
3747 ctx->ifc_flags &= ~IFC_QFLUSH;
3754 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3755 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3756 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3759 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3761 if_ctx_t ctx = if_getsoftc(ifp);
3762 struct ifreq *ifr = (struct ifreq *)data;
3763 #if defined(INET) || defined(INET6)
3764 struct ifaddr *ifa = (struct ifaddr *)data;
3766 bool avoid_reset = FALSE;
3767 int err = 0, reinit = 0, bits;
3772 if (ifa->ifa_addr->sa_family == AF_INET)
3776 if (ifa->ifa_addr->sa_family == AF_INET6)
3780 ** Calling init results in link renegotiation,
3781 ** so we avoid doing it when possible.
3784 if_setflagbits(ifp, IFF_UP,0);
3785 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3788 if (!(if_getflags(ifp) & IFF_NOARP))
3789 arp_ifinit(ifp, ifa);
3792 err = ether_ioctl(ifp, command, data);
3796 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3800 bits = if_getdrvflags(ifp);
3801 /* stop the driver and free any clusters before proceeding */
3804 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3805 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3806 ctx->ifc_flags |= IFC_MULTISEG;
3808 ctx->ifc_flags &= ~IFC_MULTISEG;
3809 err = if_setmtu(ifp, ifr->ifr_mtu);
3811 iflib_init_locked(ctx);
3812 if_setdrvflags(ifp, bits);
3817 if (if_getflags(ifp) & IFF_UP) {
3818 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3819 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3820 (IFF_PROMISC | IFF_ALLMULTI)) {
3821 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3825 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3828 ctx->ifc_if_flags = if_getflags(ifp);
3833 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3835 IFDI_INTR_DISABLE(ctx);
3836 IFDI_MULTI_SET(ctx);
3837 IFDI_INTR_ENABLE(ctx);
3843 IFDI_MEDIA_SET(ctx);
3847 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3851 struct ifi2creq i2c;
3853 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3856 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3860 if (i2c.len > sizeof(i2c.data)) {
3865 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3866 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3873 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3876 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3878 setmask |= (mask & IFCAP_FLAGS);
3880 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
3881 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
3882 if ((mask & IFCAP_WOL) &&
3883 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3884 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3887 * want to ensure that traffic has stopped before we change any of the flags
3891 bits = if_getdrvflags(ifp);
3892 if (bits & IFF_DRV_RUNNING)
3894 if_togglecapenable(ifp, setmask);
3895 if (bits & IFF_DRV_RUNNING)
3896 iflib_init_locked(ctx);
3897 if_setdrvflags(ifp, bits);
3902 case SIOCGPRIVATE_0:
3906 err = IFDI_PRIV_IOCTL(ctx, command, data);
3910 err = ether_ioctl(ifp, command, data);
3919 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3921 if_ctx_t ctx = if_getsoftc(ifp);
3923 return (IFDI_GET_COUNTER(ctx, cnt));
3926 /*********************************************************************
3928 * OTHER FUNCTIONS EXPORTED TO THE STACK
3930 **********************************************************************/
3933 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
3935 if_ctx_t ctx = if_getsoftc(ifp);
3937 if ((void *)ctx != arg)
3940 if ((vtag == 0) || (vtag > 4095))
3944 IFDI_VLAN_REGISTER(ctx, vtag);
3945 /* Re-init to load the changes */
3946 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3947 iflib_if_init_locked(ctx);
3952 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
3954 if_ctx_t ctx = if_getsoftc(ifp);
3956 if ((void *)ctx != arg)
3959 if ((vtag == 0) || (vtag > 4095))
3963 IFDI_VLAN_UNREGISTER(ctx, vtag);
3964 /* Re-init to load the changes */
3965 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3966 iflib_if_init_locked(ctx);
3971 iflib_led_func(void *arg, int onoff)
3976 IFDI_LED_FUNC(ctx, onoff);
3980 /*********************************************************************
3982 * BUS FUNCTION DEFINITIONS
3984 **********************************************************************/
3987 iflib_device_probe(device_t dev)
3989 pci_vendor_info_t *ent;
3991 uint16_t pci_vendor_id, pci_device_id;
3992 uint16_t pci_subvendor_id, pci_subdevice_id;
3993 uint16_t pci_rev_id;
3994 if_shared_ctx_t sctx;
3996 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3999 pci_vendor_id = pci_get_vendor(dev);
4000 pci_device_id = pci_get_device(dev);
4001 pci_subvendor_id = pci_get_subvendor(dev);
4002 pci_subdevice_id = pci_get_subdevice(dev);
4003 pci_rev_id = pci_get_revid(dev);
4004 if (sctx->isc_parse_devinfo != NULL)
4005 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4007 ent = sctx->isc_vendor_info;
4008 while (ent->pvi_vendor_id != 0) {
4009 if (pci_vendor_id != ent->pvi_vendor_id) {
4013 if ((pci_device_id == ent->pvi_device_id) &&
4014 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4015 (ent->pvi_subvendor_id == 0)) &&
4016 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4017 (ent->pvi_subdevice_id == 0)) &&
4018 ((pci_rev_id == ent->pvi_rev_id) ||
4019 (ent->pvi_rev_id == 0))) {
4021 device_set_desc_copy(dev, ent->pvi_name);
4022 /* this needs to be changed to zero if the bus probing code
4023 * ever stops re-probing on best match because the sctx
4024 * may have its values over written by register calls
4025 * in subsequent probes
4027 return (BUS_PROBE_DEFAULT);
4035 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4037 int err, rid, msix, msix_bar;
4040 if_softc_ctx_t scctx;
4046 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4049 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4050 device_set_softc(dev, ctx);
4051 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4054 ctx->ifc_sctx = sctx;
4056 ctx->ifc_softc = sc;
4058 if ((err = iflib_register(ctx)) != 0) {
4059 device_printf(dev, "iflib_register failed %d\n", err);
4062 iflib_add_device_sysctl_pre(ctx);
4064 scctx = &ctx->ifc_softc_ctx;
4068 * XXX sanity check that ntxd & nrxd are a power of 2
4070 if (ctx->ifc_sysctl_ntxqs != 0)
4071 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4072 if (ctx->ifc_sysctl_nrxqs != 0)
4073 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4075 for (i = 0; i < sctx->isc_ntxqs; i++) {
4076 if (ctx->ifc_sysctl_ntxds[i] != 0)
4077 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4079 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4082 for (i = 0; i < sctx->isc_nrxqs; i++) {
4083 if (ctx->ifc_sysctl_nrxds[i] != 0)
4084 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4086 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4089 for (i = 0; i < sctx->isc_nrxqs; i++) {
4090 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4091 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4092 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4093 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4095 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4096 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4097 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4098 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4102 for (i = 0; i < sctx->isc_ntxqs; i++) {
4103 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4104 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4105 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4106 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4108 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4109 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4110 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4111 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4115 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4116 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4119 _iflib_pre_assert(scctx);
4120 ctx->ifc_txrx = *scctx->isc_txrx;
4123 MPASS(scctx->isc_capenable);
4124 if (scctx->isc_capenable & IFCAP_TXCSUM)
4125 MPASS(scctx->isc_tx_csum_flags);
4128 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4129 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4131 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4132 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4133 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4134 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4137 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4138 ctx->ifc_flags |= IFC_DMAR;
4139 #elif !(defined(__i386__) || defined(__amd64__))
4140 /* set unconditionally for !x86 */
4141 ctx->ifc_flags |= IFC_DMAR;
4144 msix_bar = scctx->isc_msix_bar;
4145 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4146 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4148 /* XXX change for per-queue sizes */
4149 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4150 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4151 for (i = 0; i < sctx->isc_nrxqs; i++) {
4152 if (!powerof2(scctx->isc_nrxd[i])) {
4153 /* round down instead? */
4154 device_printf(dev, "# rx descriptors must be a power of 2\n");
4159 for (i = 0; i < sctx->isc_ntxqs; i++) {
4160 if (!powerof2(scctx->isc_ntxd[i])) {
4162 "# tx descriptors must be a power of 2");
4168 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4169 MAX_SINGLE_PACKET_FRACTION)
4170 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4171 MAX_SINGLE_PACKET_FRACTION);
4172 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4173 MAX_SINGLE_PACKET_FRACTION)
4174 scctx->isc_tx_tso_segments_max = max(1,
4175 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4178 * Protect the stack against modern hardware
4180 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4181 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4183 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4184 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4185 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4186 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4187 if (scctx->isc_rss_table_size == 0)
4188 scctx->isc_rss_table_size = 64;
4189 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4191 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4192 /* XXX format name */
4193 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4195 ** Now setup MSI or MSI/X, should
4196 ** return us the number of supported
4197 ** vectors. (Will be 1 for MSI)
4199 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4200 msix = scctx->isc_vectors;
4201 } else if (scctx->isc_msix_bar != 0)
4203 * The simple fact that isc_msix_bar is not 0 does not mean we
4204 * we have a good value there that is known to work.
4206 msix = iflib_msix_init(ctx);
4208 scctx->isc_vectors = 1;
4209 scctx->isc_ntxqsets = 1;
4210 scctx->isc_nrxqsets = 1;
4211 scctx->isc_intr = IFLIB_INTR_LEGACY;
4214 /* Get memory for the station queues */
4215 if ((err = iflib_queues_alloc(ctx))) {
4216 device_printf(dev, "Unable to allocate queue memory\n");
4220 if ((err = iflib_qset_structures_setup(ctx))) {
4221 device_printf(dev, "qset structure setup failed %d\n", err);
4226 * Group taskqueues aren't properly set up until SMP is started,
4227 * so we disable interrupts until we can handle them post
4230 * XXX: disabling interrupts doesn't actually work, at least for
4231 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4232 * we do null handling and depend on this not causing too large an
4235 IFDI_INTR_DISABLE(ctx);
4236 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4237 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4238 goto fail_intr_free;
4242 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4246 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4247 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4248 goto fail_intr_free;
4251 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4252 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4253 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4256 if ((err = iflib_netmap_attach(ctx))) {
4257 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4262 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4263 iflib_add_device_sysctl_post(ctx);
4264 ctx->ifc_flags |= IFC_INIT_DONE;
4267 ether_ifdetach(ctx->ifc_ifp);
4269 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4270 pci_release_msi(ctx->ifc_dev);
4272 /* XXX free queues */
4279 iflib_device_attach(device_t dev)
4282 if_shared_ctx_t sctx;
4284 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4287 pci_enable_busmaster(dev);
4289 return (iflib_device_register(dev, NULL, sctx, &ctx));
4293 iflib_device_deregister(if_ctx_t ctx)
4295 if_t ifp = ctx->ifc_ifp;
4298 device_t dev = ctx->ifc_dev;
4300 struct taskqgroup *tqg;
4303 /* Make sure VLANS are not using driver */
4304 if (if_vlantrunkinuse(ifp)) {
4305 device_printf(dev,"Vlan in use, detach first\n");
4310 ctx->ifc_in_detach = 1;
4314 /* Unregister VLAN events */
4315 if (ctx->ifc_vlan_attach_event != NULL)
4316 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4317 if (ctx->ifc_vlan_detach_event != NULL)
4318 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4320 iflib_netmap_detach(ifp);
4321 ether_ifdetach(ifp);
4322 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4323 CTX_LOCK_DESTROY(ctx);
4324 if (ctx->ifc_led_dev != NULL)
4325 led_destroy(ctx->ifc_led_dev);
4326 /* XXX drain any dependent tasks */
4327 tqg = qgroup_if_io_tqg;
4328 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4329 callout_drain(&txq->ift_timer);
4330 if (txq->ift_task.gt_uniq != NULL)
4331 taskqgroup_detach(tqg, &txq->ift_task);
4333 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4334 if (rxq->ifr_task.gt_uniq != NULL)
4335 taskqgroup_detach(tqg, &rxq->ifr_task);
4337 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4338 free(fl->ifl_rx_bitmap, M_IFLIB);
4341 tqg = qgroup_if_config_tqg;
4342 if (ctx->ifc_admin_task.gt_uniq != NULL)
4343 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4344 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4345 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4348 device_set_softc(ctx->ifc_dev, NULL);
4349 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4350 pci_release_msi(dev);
4352 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4353 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4355 if (ctx->ifc_msix_mem != NULL) {
4356 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4357 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4358 ctx->ifc_msix_mem = NULL;
4361 bus_generic_detach(dev);
4364 iflib_tx_structures_free(ctx);
4365 iflib_rx_structures_free(ctx);
4366 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4367 free(ctx->ifc_softc, M_IFLIB);
4374 iflib_device_detach(device_t dev)
4376 if_ctx_t ctx = device_get_softc(dev);
4378 return (iflib_device_deregister(ctx));
4382 iflib_device_suspend(device_t dev)
4384 if_ctx_t ctx = device_get_softc(dev);
4390 return bus_generic_suspend(dev);
4393 iflib_device_shutdown(device_t dev)
4395 if_ctx_t ctx = device_get_softc(dev);
4401 return bus_generic_suspend(dev);
4406 iflib_device_resume(device_t dev)
4408 if_ctx_t ctx = device_get_softc(dev);
4409 iflib_txq_t txq = ctx->ifc_txqs;
4413 iflib_init_locked(ctx);
4415 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4416 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4418 return (bus_generic_resume(dev));
4422 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4425 if_ctx_t ctx = device_get_softc(dev);
4428 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4435 iflib_device_iov_uninit(device_t dev)
4437 if_ctx_t ctx = device_get_softc(dev);
4440 IFDI_IOV_UNINIT(ctx);
4445 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4448 if_ctx_t ctx = device_get_softc(dev);
4451 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4457 /*********************************************************************
4459 * MODULE FUNCTION DEFINITIONS
4461 **********************************************************************/
4464 * - Start a fast taskqueue thread for each core
4465 * - Start a taskqueue for control operations
4468 iflib_module_init(void)
4474 iflib_module_event_handler(module_t mod, int what, void *arg)
4480 if ((err = iflib_module_init()) != 0)
4486 return (EOPNOTSUPP);
4492 /*********************************************************************
4494 * PUBLIC FUNCTION DEFINITIONS
4495 * ordered as in iflib.h
4497 **********************************************************************/
4501 _iflib_assert(if_shared_ctx_t sctx)
4503 MPASS(sctx->isc_tx_maxsize);
4504 MPASS(sctx->isc_tx_maxsegsize);
4506 MPASS(sctx->isc_rx_maxsize);
4507 MPASS(sctx->isc_rx_nsegments);
4508 MPASS(sctx->isc_rx_maxsegsize);
4510 MPASS(sctx->isc_nrxd_min[0]);
4511 MPASS(sctx->isc_nrxd_max[0]);
4512 MPASS(sctx->isc_nrxd_default[0]);
4513 MPASS(sctx->isc_ntxd_min[0]);
4514 MPASS(sctx->isc_ntxd_max[0]);
4515 MPASS(sctx->isc_ntxd_default[0]);
4519 _iflib_pre_assert(if_softc_ctx_t scctx)
4522 MPASS(scctx->isc_txrx->ift_txd_encap);
4523 MPASS(scctx->isc_txrx->ift_txd_flush);
4524 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4525 MPASS(scctx->isc_txrx->ift_rxd_available);
4526 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4527 MPASS(scctx->isc_txrx->ift_rxd_refill);
4528 MPASS(scctx->isc_txrx->ift_rxd_flush);
4532 iflib_register(if_ctx_t ctx)
4534 if_shared_ctx_t sctx = ctx->ifc_sctx;
4535 driver_t *driver = sctx->isc_driver;
4536 device_t dev = ctx->ifc_dev;
4539 _iflib_assert(sctx);
4541 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4543 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4545 device_printf(dev, "can not allocate ifnet structure\n");
4550 * Initialize our context's device specific methods
4552 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4553 kobj_class_compile((kobj_class_t) driver);
4556 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4557 if_setsoftc(ifp, ctx);
4558 if_setdev(ifp, dev);
4559 if_setinitfn(ifp, iflib_if_init);
4560 if_setioctlfn(ifp, iflib_if_ioctl);
4561 if_settransmitfn(ifp, iflib_if_transmit);
4562 if_setqflushfn(ifp, iflib_if_qflush);
4563 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4565 ctx->ifc_vlan_attach_event =
4566 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4567 EVENTHANDLER_PRI_FIRST);
4568 ctx->ifc_vlan_detach_event =
4569 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4570 EVENTHANDLER_PRI_FIRST);
4572 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4573 iflib_media_change, iflib_media_status);
4580 iflib_queues_alloc(if_ctx_t ctx)
4582 if_shared_ctx_t sctx = ctx->ifc_sctx;
4583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4584 device_t dev = ctx->ifc_dev;
4585 int nrxqsets = scctx->isc_nrxqsets;
4586 int ntxqsets = scctx->isc_ntxqsets;
4589 iflib_fl_t fl = NULL;
4590 int i, j, cpu, err, txconf, rxconf;
4591 iflib_dma_info_t ifdip;
4592 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4593 uint32_t *txqsizes = scctx->isc_txqsizes;
4594 uint8_t nrxqs = sctx->isc_nrxqs;
4595 uint8_t ntxqs = sctx->isc_ntxqs;
4596 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4599 struct ifmp_ring **brscp;
4601 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4602 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4608 /* Allocate the TX ring struct memory */
4610 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4611 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4612 device_printf(dev, "Unable to allocate TX ring memory\n");
4617 /* Now allocate the RX */
4619 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4620 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4621 device_printf(dev, "Unable to allocate RX ring memory\n");
4626 ctx->ifc_txqs = txq;
4627 ctx->ifc_rxqs = rxq;
4630 * XXX handle allocation failure
4632 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4633 /* Set up some basics */
4635 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4636 device_printf(dev, "failed to allocate iflib_dma_info\n");
4640 txq->ift_ifdi = ifdip;
4641 for (j = 0; j < ntxqs; j++, ifdip++) {
4642 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4643 device_printf(dev, "Unable to allocate Descriptor memory\n");
4647 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4648 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4652 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4653 txq->ift_br_offset = 1;
4655 txq->ift_br_offset = 0;
4658 txq->ift_timer.c_cpu = cpu;
4660 if (iflib_txsd_alloc(txq)) {
4661 device_printf(dev, "Critical Failure setting up TX buffers\n");
4666 /* Initialize the TX lock */
4667 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4668 device_get_nameunit(dev), txq->ift_id);
4669 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4670 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4672 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4673 device_get_nameunit(dev), txq->ift_id);
4675 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4676 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4678 /* XXX free any allocated rings */
4679 device_printf(dev, "Unable to allocate buf_ring\n");
4684 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4685 /* Set up some basics */
4687 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4688 device_printf(dev, "failed to allocate iflib_dma_info\n");
4693 rxq->ifr_ifdi = ifdip;
4694 /* XXX this needs to be changed if #rx queues != #tx queues */
4695 rxq->ifr_ntxqirq = 1;
4696 rxq->ifr_txqid[0] = i;
4697 for (j = 0; j < nrxqs; j++, ifdip++) {
4698 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4699 device_printf(dev, "Unable to allocate Descriptor memory\n");
4703 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4707 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4708 rxq->ifr_fl_offset = 1;
4710 rxq->ifr_fl_offset = 0;
4712 rxq->ifr_nfl = nfree_lists;
4714 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4715 device_printf(dev, "Unable to allocate free list memory\n");
4720 for (j = 0; j < nfree_lists; j++) {
4721 fl[j].ifl_rxq = rxq;
4723 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4724 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4726 /* Allocate receive buffers for the ring*/
4727 if (iflib_rxsd_alloc(rxq)) {
4729 "Critical Failure setting up receive buffers\n");
4734 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4735 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4739 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4740 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4741 for (i = 0; i < ntxqsets; i++) {
4742 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4744 for (j = 0; j < ntxqs; j++, di++) {
4745 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4746 paddrs[i*ntxqs + j] = di->idi_paddr;
4749 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4750 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4751 iflib_tx_structures_free(ctx);
4752 free(vaddrs, M_IFLIB);
4753 free(paddrs, M_IFLIB);
4756 free(vaddrs, M_IFLIB);
4757 free(paddrs, M_IFLIB);
4760 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4761 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4762 for (i = 0; i < nrxqsets; i++) {
4763 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4765 for (j = 0; j < nrxqs; j++, di++) {
4766 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4767 paddrs[i*nrxqs + j] = di->idi_paddr;
4770 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4771 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4772 iflib_tx_structures_free(ctx);
4773 free(vaddrs, M_IFLIB);
4774 free(paddrs, M_IFLIB);
4777 free(vaddrs, M_IFLIB);
4778 free(paddrs, M_IFLIB);
4782 /* XXX handle allocation failure changes */
4785 if (ctx->ifc_rxqs != NULL)
4786 free(ctx->ifc_rxqs, M_IFLIB);
4787 ctx->ifc_rxqs = NULL;
4788 if (ctx->ifc_txqs != NULL)
4789 free(ctx->ifc_txqs, M_IFLIB);
4790 ctx->ifc_txqs = NULL;
4793 free(brscp, M_IFLIB);
4803 iflib_tx_structures_setup(if_ctx_t ctx)
4805 iflib_txq_t txq = ctx->ifc_txqs;
4808 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4809 iflib_txq_setup(txq);
4815 iflib_tx_structures_free(if_ctx_t ctx)
4817 iflib_txq_t txq = ctx->ifc_txqs;
4820 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4821 iflib_txq_destroy(txq);
4822 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4823 iflib_dma_free(&txq->ift_ifdi[j]);
4825 free(ctx->ifc_txqs, M_IFLIB);
4826 ctx->ifc_txqs = NULL;
4827 IFDI_QUEUES_FREE(ctx);
4830 /*********************************************************************
4832 * Initialize all receive rings.
4834 **********************************************************************/
4836 iflib_rx_structures_setup(if_ctx_t ctx)
4838 iflib_rxq_t rxq = ctx->ifc_rxqs;
4840 #if defined(INET6) || defined(INET)
4844 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4845 #if defined(INET6) || defined(INET)
4846 tcp_lro_free(&rxq->ifr_lc);
4847 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4848 TCP_LRO_ENTRIES, min(1024,
4849 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4850 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4853 rxq->ifr_lro_enabled = TRUE;
4855 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4858 #if defined(INET6) || defined(INET)
4861 * Free RX software descriptors allocated so far, we will only handle
4862 * the rings that completed, the failing case will have
4863 * cleaned up for itself. 'q' failed, so its the terminus.
4865 rxq = ctx->ifc_rxqs;
4866 for (i = 0; i < q; ++i, rxq++) {
4867 iflib_rx_sds_free(rxq);
4868 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4874 /*********************************************************************
4876 * Free all receive rings.
4878 **********************************************************************/
4880 iflib_rx_structures_free(if_ctx_t ctx)
4882 iflib_rxq_t rxq = ctx->ifc_rxqs;
4884 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4885 iflib_rx_sds_free(rxq);
4890 iflib_qset_structures_setup(if_ctx_t ctx)
4894 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4897 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4898 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4899 iflib_tx_structures_free(ctx);
4900 iflib_rx_structures_free(ctx);
4906 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4907 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4910 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4914 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4916 int i, cpuid, eqid, count;
4918 CPU_COPY(&ctx->ifc_cpus, cpus);
4919 count = CPU_COUNT(&ctx->ifc_cpus);
4921 /* clear up to the qid'th bit */
4922 for (i = 0; i < eqid; i++) {
4923 cpuid = CPU_FFS(cpus);
4925 CPU_CLR(cpuid-1, cpus);
4927 cpuid = CPU_FFS(cpus);
4933 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
4934 iflib_intr_type_t type, driver_filter_t *filter,
4935 void *filter_arg, int qid, char *name)
4937 struct grouptask *gtask;
4938 struct taskqgroup *tqg;
4939 iflib_filter_info_t info;
4942 int tqrid, err, cpuid;
4943 driver_filter_t *intr_fast;
4946 info = &ctx->ifc_filter_info;
4950 /* XXX merge tx/rx for netmap? */
4952 q = &ctx->ifc_txqs[qid];
4953 info = &ctx->ifc_txqs[qid].ift_filter_info;
4954 gtask = &ctx->ifc_txqs[qid].ift_task;
4955 tqg = qgroup_if_io_tqg;
4957 intr_fast = iflib_fast_intr;
4958 GROUPTASK_INIT(gtask, 0, fn, q);
4961 q = &ctx->ifc_rxqs[qid];
4962 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4963 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4964 tqg = qgroup_if_io_tqg;
4966 intr_fast = iflib_fast_intr;
4967 GROUPTASK_INIT(gtask, 0, fn, q);
4969 case IFLIB_INTR_RXTX:
4970 q = &ctx->ifc_rxqs[qid];
4971 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4972 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4973 tqg = qgroup_if_io_tqg;
4975 intr_fast = iflib_fast_intr_rxtx;
4976 GROUPTASK_INIT(gtask, 0, fn, q);
4978 case IFLIB_INTR_ADMIN:
4981 info = &ctx->ifc_filter_info;
4982 gtask = &ctx->ifc_admin_task;
4983 tqg = qgroup_if_config_tqg;
4984 fn = _task_fn_admin;
4985 intr_fast = iflib_fast_intr_ctx;
4988 panic("unknown net intr type");
4991 info->ifi_filter = filter;
4992 info->ifi_filter_arg = filter_arg;
4993 info->ifi_task = gtask;
4996 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
4998 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5001 if (type == IFLIB_INTR_ADMIN)
5005 cpuid = find_nth(ctx, &cpus, qid);
5006 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name);
5008 taskqgroup_attach(tqg, gtask, q, tqrid, name);
5015 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name)
5017 struct grouptask *gtask;
5018 struct taskqgroup *tqg;
5024 q = &ctx->ifc_txqs[qid];
5025 gtask = &ctx->ifc_txqs[qid].ift_task;
5026 tqg = qgroup_if_io_tqg;
5030 q = &ctx->ifc_rxqs[qid];
5031 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5032 tqg = qgroup_if_io_tqg;
5035 case IFLIB_INTR_IOV:
5037 gtask = &ctx->ifc_vflr_task;
5038 tqg = qgroup_if_config_tqg;
5043 panic("unknown net intr type");
5045 GROUPTASK_INIT(gtask, 0, fn, q);
5046 taskqgroup_attach(tqg, gtask, q, rid, name);
5050 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5053 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5056 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5060 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5062 iflib_txq_t txq = ctx->ifc_txqs;
5063 iflib_rxq_t rxq = ctx->ifc_rxqs;
5064 if_irq_t irq = &ctx->ifc_legacy_irq;
5065 iflib_filter_info_t info;
5066 struct grouptask *gtask;
5067 struct taskqgroup *tqg;
5073 q = &ctx->ifc_rxqs[0];
5074 info = &rxq[0].ifr_filter_info;
5075 gtask = &rxq[0].ifr_task;
5076 tqg = qgroup_if_io_tqg;
5077 tqrid = irq->ii_rid = *rid;
5080 ctx->ifc_flags |= IFC_LEGACY;
5081 info->ifi_filter = filter;
5082 info->ifi_filter_arg = filter_arg;
5083 info->ifi_task = gtask;
5084 info->ifi_ctx = ctx;
5086 /* We allocate a single interrupt resource */
5087 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5089 GROUPTASK_INIT(gtask, 0, fn, q);
5090 taskqgroup_attach(tqg, gtask, q, tqrid, name);
5092 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5093 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx");
5098 iflib_led_create(if_ctx_t ctx)
5101 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5102 device_get_nameunit(ctx->ifc_dev));
5106 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5109 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5113 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5116 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5120 iflib_admin_intr_deferred(if_ctx_t ctx)
5123 struct grouptask *gtask;
5125 gtask = &ctx->ifc_admin_task;
5126 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5129 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5133 iflib_iov_intr_deferred(if_ctx_t ctx)
5136 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5140 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5143 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5147 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
5151 GROUPTASK_INIT(gtask, 0, fn, ctx);
5152 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5156 iflib_config_gtask_deinit(struct grouptask *gtask)
5159 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5163 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5165 if_t ifp = ctx->ifc_ifp;
5166 iflib_txq_t txq = ctx->ifc_txqs;
5168 if_setbaudrate(ifp, baudrate);
5169 if (baudrate >= IF_Gbps(10))
5170 ctx->ifc_flags |= IFC_PREFETCH;
5172 /* If link down, disable watchdog */
5173 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5174 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5175 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5177 ctx->ifc_link_state = link_state;
5178 if_link_state_change(ifp, link_state);
5182 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5186 int credits_pre = txq->ift_cidx_processed;
5189 if (ctx->isc_txd_credits_update == NULL)
5192 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5195 txq->ift_processed += credits;
5196 txq->ift_cidx_processed += credits;
5198 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5199 if (txq->ift_cidx_processed >= txq->ift_size)
5200 txq->ift_cidx_processed -= txq->ift_size;
5205 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5208 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5213 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5214 const char *description, if_int_delay_info_t info,
5215 int offset, int value)
5217 info->iidi_ctx = ctx;
5218 info->iidi_offset = offset;
5219 info->iidi_value = value;
5220 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5221 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5222 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5223 info, 0, iflib_sysctl_int_delay, "I", description);
5227 iflib_ctx_lock_get(if_ctx_t ctx)
5230 return (&ctx->ifc_mtx);
5234 iflib_msix_init(if_ctx_t ctx)
5236 device_t dev = ctx->ifc_dev;
5237 if_shared_ctx_t sctx = ctx->ifc_sctx;
5238 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5239 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5240 int iflib_num_tx_queues, iflib_num_rx_queues;
5241 int err, admincnt, bar;
5243 iflib_num_tx_queues = scctx->isc_ntxqsets;
5244 iflib_num_rx_queues = scctx->isc_nrxqsets;
5246 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues);
5248 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5249 admincnt = sctx->isc_admin_intrcnt;
5250 /* Override by tuneable */
5251 if (scctx->isc_disable_msix)
5255 ** When used in a virtualized environment
5256 ** PCI BUSMASTER capability may not be set
5257 ** so explicity set it here and rewrite
5258 ** the ENABLE in the MSIX control register
5259 ** at this point to cause the host to
5260 ** successfully initialize us.
5265 pci_enable_busmaster(dev);
5267 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5268 rid += PCIR_MSIX_CTRL;
5269 msix_ctrl = pci_read_config(dev, rid, 2);
5270 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5271 pci_write_config(dev, rid, msix_ctrl, 2);
5273 device_printf(dev, "PCIY_MSIX capability not found; "
5274 "or rid %d == 0.\n", rid);
5280 * bar == -1 => "trust me I know what I'm doing"
5281 * Some drivers are for hardware that is so shoddily
5282 * documented that no one knows which bars are which
5283 * so the developer has to map all bars. This hack
5284 * allows shoddy garbage to use msix in this framework.
5287 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5288 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5289 if (ctx->ifc_msix_mem == NULL) {
5290 /* May not be enabled */
5291 device_printf(dev, "Unable to map MSIX table \n");
5295 /* First try MSI/X */
5296 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5297 device_printf(dev, "System has MSIX disabled \n");
5298 bus_release_resource(dev, SYS_RES_MEMORY,
5299 bar, ctx->ifc_msix_mem);
5300 ctx->ifc_msix_mem = NULL;
5304 /* use only 1 qset in debug mode */
5305 queuemsgs = min(msgs - admincnt, 1);
5307 queuemsgs = msgs - admincnt;
5309 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
5311 queues = imin(queuemsgs, rss_getnumbuckets());
5315 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5316 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5317 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5319 device_printf(dev, "Unable to fetch CPU list\n");
5320 /* Figure out a reasonable auto config value */
5321 queues = min(queuemsgs, mp_ncpus);
5324 /* If we're doing RSS, clamp at the number of RSS buckets */
5325 if (queues > rss_getnumbuckets())
5326 queues = rss_getnumbuckets();
5328 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5329 rx_queues = iflib_num_rx_queues;
5333 * We want this to be all logical CPUs by default
5335 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5336 tx_queues = iflib_num_tx_queues;
5338 tx_queues = mp_ncpus;
5340 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5342 if (tx_queues != rx_queues)
5343 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5344 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5346 tx_queues = min(rx_queues, tx_queues);
5347 rx_queues = min(rx_queues, tx_queues);
5350 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5352 vectors = rx_queues + admincnt;
5353 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5355 "Using MSIX interrupts with %d vectors\n", vectors);
5356 scctx->isc_vectors = vectors;
5357 scctx->isc_nrxqsets = rx_queues;
5358 scctx->isc_ntxqsets = tx_queues;
5359 scctx->isc_intr = IFLIB_INTR_MSIX;
5363 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5366 vectors = pci_msi_count(dev);
5367 scctx->isc_nrxqsets = 1;
5368 scctx->isc_ntxqsets = 1;
5369 scctx->isc_vectors = vectors;
5370 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5371 device_printf(dev,"Using an MSI interrupt\n");
5372 scctx->isc_intr = IFLIB_INTR_MSI;
5374 device_printf(dev,"Using a Legacy interrupt\n");
5375 scctx->isc_intr = IFLIB_INTR_LEGACY;
5381 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5384 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5387 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5389 char *ring_state = "UNKNOWN";
5392 rc = sysctl_wire_old_buffer(req, 0);
5396 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5401 ring_state = ring_states[state[3]];
5403 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5404 state[0], state[1], state[2], ring_state);
5405 rc = sbuf_finish(sb);
5410 enum iflib_ndesc_handler {
5416 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5418 if_ctx_t ctx = (void *)arg1;
5419 enum iflib_ndesc_handler type = arg2;
5420 char buf[256] = {0};
5425 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5429 case IFLIB_NTXD_HANDLER:
5430 ndesc = ctx->ifc_sysctl_ntxds;
5432 nqs = ctx->ifc_sctx->isc_ntxqs;
5434 case IFLIB_NRXD_HANDLER:
5435 ndesc = ctx->ifc_sysctl_nrxds;
5437 nqs = ctx->ifc_sctx->isc_nrxqs;
5443 for (i=0; i<8; i++) {
5448 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5451 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5452 if (rc || req->newptr == NULL)
5455 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5456 i++, p = strsep(&next, " ,")) {
5457 ndesc[i] = strtoul(p, NULL, 10);
5463 #define NAME_BUFLEN 32
5465 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5467 device_t dev = iflib_get_dev(ctx);
5468 struct sysctl_oid_list *child, *oid_list;
5469 struct sysctl_ctx_list *ctx_list;
5470 struct sysctl_oid *node;
5472 ctx_list = device_get_sysctl_ctx(dev);
5473 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5474 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5475 CTLFLAG_RD, NULL, "IFLIB fields");
5476 oid_list = SYSCTL_CHILDREN(node);
5478 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5479 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5482 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5483 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5484 "# of txqs to use, 0 => use default #");
5485 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5486 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5487 "# of rxqs to use, 0 => use default #");
5488 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5489 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5490 "permit #txq != #rxq");
5491 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5492 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5493 "disable MSIX (default 0)");
5494 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
5495 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
5496 "set the rx budget");
5498 /* XXX change for per-queue sizes */
5499 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5500 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5501 mp_ndesc_handler, "A",
5502 "list of # of tx descriptors to use, 0 = use default #");
5503 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5504 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5505 mp_ndesc_handler, "A",
5506 "list of # of rx descriptors to use, 0 = use default #");
5510 iflib_add_device_sysctl_post(if_ctx_t ctx)
5512 if_shared_ctx_t sctx = ctx->ifc_sctx;
5513 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5514 device_t dev = iflib_get_dev(ctx);
5515 struct sysctl_oid_list *child;
5516 struct sysctl_ctx_list *ctx_list;
5521 char namebuf[NAME_BUFLEN];
5523 struct sysctl_oid *queue_node, *fl_node, *node;
5524 struct sysctl_oid_list *queue_list, *fl_list;
5525 ctx_list = device_get_sysctl_ctx(dev);
5527 node = ctx->ifc_sysctl_node;
5528 child = SYSCTL_CHILDREN(node);
5530 if (scctx->isc_ntxqsets > 100)
5532 else if (scctx->isc_ntxqsets > 10)
5536 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5537 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5538 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5539 CTLFLAG_RD, NULL, "Queue Name");
5540 queue_list = SYSCTL_CHILDREN(queue_node);
5542 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5544 &txq->ift_dequeued, "total mbufs freed");
5545 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5547 &txq->ift_enqueued, "total mbufs enqueued");
5549 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5551 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5552 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5554 &txq->ift_pullups, "# of times m_pullup was called");
5555 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5557 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5558 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5560 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5561 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5563 &txq->ift_map_failed, "# of times dma map failed");
5564 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5566 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5567 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5569 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5570 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5572 &txq->ift_pidx, 1, "Producer Index");
5573 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5575 &txq->ift_cidx, 1, "Consumer Index");
5576 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5578 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5579 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5581 &txq->ift_in_use, 1, "descriptors in use");
5582 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5584 &txq->ift_processed, "descriptors procesed for clean");
5585 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5587 &txq->ift_cleaned, "total cleaned");
5588 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5589 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5590 0, mp_ring_state_handler, "A", "soft ring state");
5591 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5592 CTLFLAG_RD, &txq->ift_br->enqueues,
5593 "# of enqueues to the mp_ring for this queue");
5594 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5595 CTLFLAG_RD, &txq->ift_br->drops,
5596 "# of drops in the mp_ring for this queue");
5597 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5598 CTLFLAG_RD, &txq->ift_br->starts,
5599 "# of normal consumer starts in the mp_ring for this queue");
5600 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5601 CTLFLAG_RD, &txq->ift_br->stalls,
5602 "# of consumer stalls in the mp_ring for this queue");
5603 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5604 CTLFLAG_RD, &txq->ift_br->restarts,
5605 "# of consumer restarts in the mp_ring for this queue");
5606 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5607 CTLFLAG_RD, &txq->ift_br->abdications,
5608 "# of consumer abdications in the mp_ring for this queue");
5611 if (scctx->isc_nrxqsets > 100)
5613 else if (scctx->isc_nrxqsets > 10)
5617 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5618 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5619 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5620 CTLFLAG_RD, NULL, "Queue Name");
5621 queue_list = SYSCTL_CHILDREN(queue_node);
5622 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5623 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5625 &rxq->ifr_cq_pidx, 1, "Producer Index");
5626 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5628 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5631 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5632 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5633 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5634 CTLFLAG_RD, NULL, "freelist Name");
5635 fl_list = SYSCTL_CHILDREN(fl_node);
5636 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5638 &fl->ifl_pidx, 1, "Producer Index");
5639 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5641 &fl->ifl_cidx, 1, "Consumer Index");
5642 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5644 &fl->ifl_credits, 1, "credits available");
5646 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5648 &fl->ifl_m_enqueued, "mbufs allocated");
5649 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5651 &fl->ifl_m_dequeued, "mbufs freed");
5652 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5654 &fl->ifl_cl_enqueued, "clusters allocated");
5655 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5657 &fl->ifl_cl_dequeued, "clusters freed");
5665 #ifndef __NO_STRICT_ALIGNMENT
5666 static struct mbuf *
5667 iflib_fixup_rx(struct mbuf *m)
5671 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5672 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5673 m->m_data += ETHER_HDR_LEN;
5676 MGETHDR(n, M_NOWAIT, MT_DATA);
5681 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
5682 m->m_data += ETHER_HDR_LEN;
5683 m->m_len -= ETHER_HDR_LEN;
5684 n->m_len = ETHER_HDR_LEN;
5685 M_MOVE_PKTHDR(n, m);