2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 #define IFLIB_RXEOF_MORE (1U << 0)
132 #define IFLIB_RXEOF_EMPTY (2U << 0)
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
145 static void iflib_tqg_detach(if_ctx_t ctx);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 struct ether_addr ifc_mac;
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (ctx->ifc_mediap);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 struct callout ift_netmap_timer;
352 #endif /* DEV_NETMAP */
354 if_txsd_vec_t ift_sds;
357 uint8_t ift_update_freq;
358 struct iflib_filter_info ift_filter_info;
359 bus_dma_tag_t ift_buf_tag;
360 bus_dma_tag_t ift_tso_buf_tag;
361 iflib_dma_info_t ift_ifdi;
362 #define MTX_NAME_LEN 32
363 char ift_mtx_name[MTX_NAME_LEN];
364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
365 #ifdef IFLIB_DIAGNOSTICS
366 uint64_t ift_cpu_exec_count[256];
368 } __aligned(CACHE_LINE_SIZE);
375 uint8_t ifl_rxd_size;
377 uint64_t ifl_m_enqueued;
378 uint64_t ifl_m_dequeued;
379 uint64_t ifl_cl_enqueued;
380 uint64_t ifl_cl_dequeued;
383 bitstr_t *ifl_rx_bitmap;
387 uint16_t ifl_buf_size;
390 iflib_rxsd_array_t ifl_sds;
393 bus_dma_tag_t ifl_buf_tag;
394 iflib_dma_info_t ifl_ifdi;
395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 } __aligned(CACHE_LINE_SIZE);
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
406 else if (pidx < cidx)
407 used = size - cidx + pidx;
408 else if (gen == 0 && pidx == cidx)
410 else if (gen == 1 && pidx == cidx)
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
420 #define IDXDIFF(head, tail, wrap) \
421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
427 struct pfil_head *pfil;
429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
430 * the completion queue consumer index. Otherwise it's unused.
436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
437 uint8_t ifr_fl_offset;
438 struct lro_ctrl ifr_lc;
439 struct grouptask ifr_task;
440 struct callout ifr_watchdog;
441 struct iflib_filter_info ifr_filter_info;
442 iflib_dma_info_t ifr_ifdi;
444 /* dynamically allocate if any drivers need a value substantially larger than this */
445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
446 #ifdef IFLIB_DIAGNOSTICS
447 uint64_t ifr_cpu_exec_count[256];
449 } __aligned(CACHE_LINE_SIZE);
451 typedef struct if_rxsd {
456 /* multiple of word size */
458 #define PKT_INFO_SIZE 6
459 #define RXD_INFO_SIZE 5
460 #define PKT_TYPE uint64_t
462 #define PKT_INFO_SIZE 11
463 #define RXD_INFO_SIZE 8
464 #define PKT_TYPE uint32_t
466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
469 typedef struct if_pkt_info_pad {
470 PKT_TYPE pkt_val[PKT_INFO_SIZE];
471 } *if_pkt_info_pad_t;
472 typedef struct if_rxd_info_pad {
473 PKT_TYPE rxd_val[RXD_INFO_SIZE];
474 } *if_rxd_info_pad_t;
476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
480 pkt_info_zero(if_pkt_info_t pi)
482 if_pkt_info_pad_t pi_pad;
484 pi_pad = (if_pkt_info_pad_t)pi;
485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
493 static device_method_t iflib_pseudo_methods[] = {
494 DEVMETHOD(device_attach, noop_attach),
495 DEVMETHOD(device_detach, iflib_pseudo_detach),
499 driver_t iflib_pseudodriver = {
500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
504 rxd_info_zero(if_rxd_info_t ri)
506 if_rxd_info_pad_t ri_pad;
509 ri_pad = (if_rxd_info_pad_t)ri;
510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
511 ri_pad->rxd_val[i] = 0;
512 ri_pad->rxd_val[i+1] = 0;
513 ri_pad->rxd_val[i+2] = 0;
514 ri_pad->rxd_val[i+3] = 0;
517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
522 * Only allow a single packet to take up most 1/nth of the tx ring
524 #define MAX_SINGLE_PACKET_FRACTION 12
525 #define IF_BAD_DMA (bus_addr_t)-1
527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
543 iflib_set_detach(if_ctx_t ctx)
546 ctx->ifc_flags |= IFC_IN_DETACH;
550 /* Our boot-time initialization hook */
551 static int iflib_module_event_handler(module_t, int, void *);
553 static moduledata_t iflib_moduledata = {
555 iflib_module_event_handler,
559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
560 MODULE_VERSION(iflib, 1);
562 MODULE_DEPEND(iflib, pci, 1, 1, 1);
563 MODULE_DEPEND(iflib, ether, 1, 1, 1);
565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
568 #ifndef IFLIB_DEBUG_COUNTERS
570 #define IFLIB_DEBUG_COUNTERS 1
572 #define IFLIB_DEBUG_COUNTERS 0
573 #endif /* !INVARIANTS */
576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
577 "iflib driver parameters");
580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
582 static int iflib_min_tx_latency = 0;
583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
585 static int iflib_no_tx_batch = 0;
586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 static int iflib_timer_default = 1000;
589 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
590 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
593 #if IFLIB_DEBUG_COUNTERS
595 static int iflib_tx_seen;
596 static int iflib_tx_sent;
597 static int iflib_tx_encap;
598 static int iflib_rx_allocs;
599 static int iflib_fl_refills;
600 static int iflib_fl_refills_large;
601 static int iflib_tx_frees;
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
604 &iflib_tx_seen, 0, "# TX mbufs seen");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
606 &iflib_tx_sent, 0, "# TX mbufs sent");
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
608 &iflib_tx_encap, 0, "# TX mbufs encapped");
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
610 &iflib_tx_frees, 0, "# TX frees");
611 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
612 &iflib_rx_allocs, 0, "# RX allocations");
613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
614 &iflib_fl_refills, 0, "# refills");
615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
616 &iflib_fl_refills_large, 0, "# large refills");
618 static int iflib_txq_drain_flushing;
619 static int iflib_txq_drain_oactive;
620 static int iflib_txq_drain_notready;
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
623 &iflib_txq_drain_flushing, 0, "# drain flushes");
624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
625 &iflib_txq_drain_oactive, 0, "# drain oactives");
626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
627 &iflib_txq_drain_notready, 0, "# drain notready");
629 static int iflib_encap_load_mbuf_fail;
630 static int iflib_encap_pad_mbuf_fail;
631 static int iflib_encap_txq_avail_fail;
632 static int iflib_encap_txd_encap_fail;
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
643 static int iflib_task_fn_rxs;
644 static int iflib_rx_intr_enables;
645 static int iflib_fast_intrs;
646 static int iflib_rx_unavail;
647 static int iflib_rx_ctx_inactive;
648 static int iflib_rx_if_input;
649 static int iflib_rxd_flush;
651 static int iflib_verbose_debug;
653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
656 &iflib_rx_intr_enables, 0, "# RX intr enables");
657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
658 &iflib_fast_intrs, 0, "# fast_intr calls");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
660 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
664 &iflib_rx_if_input, 0, "# times rxeof called if_input");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
666 &iflib_rxd_flush, 0, "# times rxd_flush called");
667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
668 &iflib_verbose_debug, 0, "enable verbose debugging");
670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
672 iflib_debug_reset(void)
674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
676 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
677 iflib_txq_drain_notready =
678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
682 iflib_rx_ctx_inactive = iflib_rx_if_input =
687 #define DBG_COUNTER_INC(name)
688 static void iflib_debug_reset(void) {}
691 #define IFLIB_DEBUG 0
693 static void iflib_tx_structures_free(if_ctx_t ctx);
694 static void iflib_rx_structures_free(if_ctx_t ctx);
695 static int iflib_queues_alloc(if_ctx_t ctx);
696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
698 static int iflib_qset_structures_setup(if_ctx_t ctx);
699 static int iflib_msix_init(if_ctx_t ctx);
700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
704 static void iflib_altq_if_start(if_t ifp);
705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
707 static int iflib_register(if_ctx_t);
708 static void iflib_deregister(if_ctx_t);
709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
710 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
711 static void iflib_init_locked(if_ctx_t ctx);
712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
713 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
714 static void iflib_ifmp_purge(iflib_txq_t txq);
715 static void _iflib_pre_assert(if_softc_ctx_t scctx);
716 static void iflib_if_init_locked(if_ctx_t ctx);
717 static void iflib_free_intr_mem(if_ctx_t ctx);
718 #ifndef __NO_STRICT_ALIGNMENT
719 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
723 SLIST_HEAD_INITIALIZER(cpu_offsets);
725 SLIST_ENTRY(cpu_offset) entries;
727 unsigned int refcount;
730 static struct mtx cpu_offset_mtx;
731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
734 DEBUGNET_DEFINE(iflib);
737 iflib_num_rx_descs(if_ctx_t ctx)
739 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
740 if_shared_ctx_t sctx = ctx->ifc_sctx;
741 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
743 return scctx->isc_nrxd[first_rxq];
747 iflib_num_tx_descs(if_ctx_t ctx)
749 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
750 if_shared_ctx_t sctx = ctx->ifc_sctx;
751 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
753 return scctx->isc_ntxd[first_txq];
757 #include <sys/selinfo.h>
758 #include <net/netmap.h>
759 #include <dev/netmap/netmap_kern.h>
761 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
763 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
764 static void iflib_netmap_timer(void *arg);
767 * device-specific sysctl variables:
769 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
770 * During regular operations the CRC is stripped, but on some
771 * hardware reception of frames not multiple of 64 is slower,
772 * so using crcstrip=0 helps in benchmarks.
774 * iflib_rx_miss, iflib_rx_miss_bufs:
775 * count packets that might be missed due to lost interrupts.
777 SYSCTL_DECL(_dev_netmap);
779 * The xl driver by default strips CRCs and we do not override it.
782 int iflib_crcstrip = 1;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
784 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
786 int iflib_rx_miss, iflib_rx_miss_bufs;
787 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
788 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
790 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
793 * Register/unregister. We are already under netmap lock.
794 * Only called on the first register or the last unregister.
797 iflib_netmap_register(struct netmap_adapter *na, int onoff)
800 if_ctx_t ctx = ifp->if_softc;
805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
810 * Enable (or disable) netmap flags, and intercept (or restore)
811 * ifp->if_transmit. This is done once the device has been stopped
812 * to prevent race conditions. Also, this must be done after
813 * calling netmap_disable_all_rings() and before calling
814 * netmap_enable_all_rings(), so that these two functions see the
815 * updated state of the NAF_NETMAP_ON bit.
818 nm_set_native_flags(na);
820 nm_clear_native_flags(na);
823 iflib_init_locked(ctx);
824 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
825 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
827 nm_clear_native_flags(na);
833 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
836 if_ctx_t ctx = ifp->if_softc;
837 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
838 iflib_fl_t fl = &rxq->ifr_fl[0];
840 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
841 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
842 info->num_tx_descs = iflib_num_tx_descs(ctx);
843 info->num_rx_descs = iflib_num_rx_descs(ctx);
844 info->rx_buf_maxsize = fl->ifl_buf_size;
845 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
846 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
847 info->num_rx_descs, info->rx_buf_maxsize);
853 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
855 struct netmap_adapter *na = kring->na;
856 u_int const lim = kring->nkr_num_slots - 1;
857 struct netmap_ring *ring = kring->ring;
859 struct if_rxd_update iru;
860 if_ctx_t ctx = rxq->ifr_ctx;
861 iflib_fl_t fl = &rxq->ifr_fl[0];
862 u_int nic_i_first, nic_i;
865 #if IFLIB_DEBUG_COUNTERS
870 * This function is used both at initialization and in rxsync.
871 * At initialization we need to prepare (with isc_rxd_refill())
872 * all the netmap buffers currently owned by the kernel, in
873 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
874 * (except for kring->nkr_hwofs). These may be less than
875 * kring->nkr_num_slots if netmap_reset() was called while
876 * an application using the kring that still owned some
878 * At rxsync time, both indexes point to the next buffer to be
880 * In any case we publish (with isc_rxd_flush()) up to
881 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
882 * pointer to overrun the head/cons pointer, although this is
883 * not necessary for some NICs (e.g. vmx).
885 if (__predict_false(init)) {
886 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
888 n = kring->rhead - kring->nr_hwcur;
890 return (0); /* Nothing to do. */
892 n += kring->nkr_num_slots;
895 iru_init(&iru, rxq, 0 /* flid */);
896 map = fl->ifl_sds.ifsd_map;
897 nic_i = fl->ifl_pidx;
898 nm_i = netmap_idx_n2k(kring, nic_i);
899 if (__predict_false(init)) {
901 * On init/reset, nic_i must be 0, and we must
902 * start to refill from hwtail (see netmap_reset()).
905 MPASS(nm_i == kring->nr_hwtail);
907 MPASS(nm_i == kring->nr_hwcur);
908 DBG_COUNTER_INC(fl_refills);
910 #if IFLIB_DEBUG_COUNTERS
912 DBG_COUNTER_INC(fl_refills_large);
915 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
916 struct netmap_slot *slot = &ring->slot[nm_i];
918 void *addr = PNMB(na, slot, &paddr);
920 MPASS(i < IFLIB_MAX_RX_REFRESH);
922 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
923 return netmap_ring_reinit(kring);
925 fl->ifl_bus_addrs[i] = paddr +
926 nm_get_offset(kring, slot);
927 fl->ifl_rxd_idxs[i] = nic_i;
929 if (__predict_false(init)) {
930 netmap_load_map(na, fl->ifl_buf_tag,
932 } else if (slot->flags & NS_BUF_CHANGED) {
933 /* buffer has changed, reload map */
934 netmap_reload_map(na, fl->ifl_buf_tag,
937 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
938 BUS_DMASYNC_PREREAD);
939 slot->flags &= ~NS_BUF_CHANGED;
941 nm_i = nm_next(nm_i, lim);
942 nic_i = nm_next(nic_i, lim);
945 iru.iru_pidx = nic_i_first;
947 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
949 fl->ifl_pidx = nic_i;
951 * At the end of the loop we must have refilled everything
952 * we could possibly refill.
954 MPASS(nm_i == kring->rhead);
955 kring->nr_hwcur = nm_i;
957 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
959 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
960 nm_prev(nic_i, lim));
961 DBG_COUNTER_INC(rxd_flush);
966 #define NETMAP_TX_TIMER_US 90
969 * Reconcile kernel and user view of the transmit ring.
971 * All information is in the kring.
972 * Userspace wants to send packets up to the one before kring->rhead,
973 * kernel knows kring->nr_hwcur is the first unsent packet.
975 * Here we push packets out (as many as possible), and possibly
976 * reclaim buffers from previously completed transmission.
978 * The caller (netmap) guarantees that there is only one instance
979 * running at any time. Any interference with other driver
980 * methods should be handled by the individual drivers.
983 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
985 struct netmap_adapter *na = kring->na;
987 struct netmap_ring *ring = kring->ring;
988 u_int nm_i; /* index into the netmap kring */
989 u_int nic_i; /* index into the NIC ring */
991 u_int const lim = kring->nkr_num_slots - 1;
992 u_int const head = kring->rhead;
993 struct if_pkt_info pi;
996 * interrupts on every tx packet are expensive so request
997 * them every half ring, or where NS_REPORT is set
999 u_int report_frequency = kring->nkr_num_slots >> 1;
1000 /* device-specific */
1001 if_ctx_t ctx = ifp->if_softc;
1002 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1005 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1008 * First part: process new packets to send.
1009 * nm_i is the current index in the netmap kring,
1010 * nic_i is the corresponding index in the NIC ring.
1012 * If we have packets to send (nm_i != head)
1013 * iterate over the netmap ring, fetch length and update
1014 * the corresponding slot in the NIC ring. Some drivers also
1015 * need to update the buffer's physical address in the NIC slot
1016 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1018 * The netmap_reload_map() calls is especially expensive,
1019 * even when (as in this case) the tag is 0, so do only
1020 * when the buffer has actually changed.
1022 * If possible do not set the report/intr bit on all slots,
1023 * but only a few times per ring or when NS_REPORT is set.
1025 * Finally, on 10G and faster drivers, it might be useful
1026 * to prefetch the next slot and txr entry.
1029 nm_i = kring->nr_hwcur;
1030 if (nm_i != head) { /* we have new packets to send */
1031 uint32_t pkt_len = 0, seg_idx = 0;
1032 int nic_i_start = -1, flags = 0;
1034 pi.ipi_segs = txq->ift_segs;
1035 pi.ipi_qsidx = kring->ring_id;
1036 nic_i = netmap_idx_k2n(kring, nm_i);
1038 __builtin_prefetch(&ring->slot[nm_i]);
1039 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1040 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1042 for (n = 0; nm_i != head; n++) {
1043 struct netmap_slot *slot = &ring->slot[nm_i];
1044 uint64_t offset = nm_get_offset(kring, slot);
1045 u_int len = slot->len;
1047 void *addr = PNMB(na, slot, &paddr);
1049 flags |= (slot->flags & NS_REPORT ||
1050 nic_i == 0 || nic_i == report_frequency) ?
1054 * If this is the first packet fragment, save the
1055 * index of the first NIC slot for later.
1057 if (nic_i_start < 0)
1058 nic_i_start = nic_i;
1060 pi.ipi_segs[seg_idx].ds_addr = paddr + offset;
1061 pi.ipi_segs[seg_idx].ds_len = len;
1067 if (!(slot->flags & NS_MOREFRAG)) {
1068 pi.ipi_len = pkt_len;
1069 pi.ipi_nsegs = seg_idx;
1070 pi.ipi_pidx = nic_i_start;
1072 pi.ipi_flags = flags;
1074 /* Prepare the NIC TX ring. */
1075 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1076 DBG_COUNTER_INC(tx_encap);
1078 /* Reinit per-packet info for the next one. */
1079 flags = seg_idx = pkt_len = 0;
1083 /* prefetch for next round */
1084 __builtin_prefetch(&ring->slot[nm_i + 1]);
1085 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1086 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1088 NM_CHECK_ADDR_LEN_OFF(na, len, offset);
1090 if (slot->flags & NS_BUF_CHANGED) {
1091 /* buffer has changed, reload map */
1092 netmap_reload_map(na, txq->ift_buf_tag,
1093 txq->ift_sds.ifsd_map[nic_i], addr);
1095 /* make sure changes to the buffer are synced */
1096 bus_dmamap_sync(txq->ift_buf_tag,
1097 txq->ift_sds.ifsd_map[nic_i],
1098 BUS_DMASYNC_PREWRITE);
1100 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1101 nm_i = nm_next(nm_i, lim);
1102 nic_i = nm_next(nic_i, lim);
1104 kring->nr_hwcur = nm_i;
1106 /* synchronize the NIC ring */
1107 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1108 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1110 /* (re)start the tx unit up to slot nic_i (excluded) */
1111 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1115 * Second part: reclaim buffers for completed transmissions.
1117 * If there are unclaimed buffers, attempt to reclaim them.
1118 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1119 * trigger a per-tx-queue timer to try again later.
1121 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1122 if (iflib_tx_credits_update(ctx, txq)) {
1123 /* some tx completed, increment avail */
1124 nic_i = txq->ift_cidx_processed;
1125 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1129 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1130 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1131 callout_reset_sbt_on(&txq->ift_netmap_timer,
1132 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1133 iflib_netmap_timer, txq,
1134 txq->ift_netmap_timer.c_cpu, 0);
1140 * Reconcile kernel and user view of the receive ring.
1141 * Same as for the txsync, this routine must be efficient.
1142 * The caller guarantees a single invocations, but races against
1143 * the rest of the driver should be handled here.
1145 * On call, kring->rhead is the first packet that userspace wants
1146 * to keep, and kring->rcur is the wakeup point.
1147 * The kernel has previously reported packets up to kring->rtail.
1149 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1150 * of whether or not we received an interrupt.
1153 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1155 struct netmap_adapter *na = kring->na;
1156 struct netmap_ring *ring = kring->ring;
1158 uint32_t nm_i; /* index into the netmap ring */
1159 uint32_t nic_i; /* index into the NIC ring */
1161 u_int const lim = kring->nkr_num_slots - 1;
1162 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1165 if_ctx_t ctx = ifp->if_softc;
1166 if_shared_ctx_t sctx = ctx->ifc_sctx;
1167 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1168 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1169 iflib_fl_t fl = &rxq->ifr_fl[0];
1170 struct if_rxd_info ri;
1174 * netmap only uses free list 0, to avoid out of order consumption
1175 * of receive buffers
1178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1179 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1182 * First part: import newly received packets.
1184 * nm_i is the index of the next free slot in the netmap ring,
1185 * nic_i is the index of the next received packet in the NIC ring
1186 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1187 * differ in case if_init() has been called while
1188 * in netmap mode. For the receive ring we have
1190 * nic_i = fl->ifl_cidx;
1191 * nm_i = kring->nr_hwtail (previous)
1193 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1195 * fl->ifl_cidx is set to 0 on a ring reinit
1197 if (netmap_no_pendintr || force_update) {
1198 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1199 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1200 int crclen = iflib_crcstrip ? 0 : 4;
1204 * For the free list consumer index, we use the same
1205 * logic as in iflib_rxeof().
1208 cidxp = &rxq->ifr_cq_cidx;
1210 cidxp = &fl->ifl_cidx;
1211 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1212 rxq->ifr_id, *cidxp, USHRT_MAX);
1214 nic_i = fl->ifl_cidx;
1215 nm_i = netmap_idx_n2k(kring, nic_i);
1216 MPASS(nm_i == kring->nr_hwtail);
1217 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1219 ri.iri_frags = rxq->ifr_frags;
1220 ri.iri_qsidx = kring->ring_id;
1221 ri.iri_ifp = ctx->ifc_ifp;
1222 ri.iri_cidx = *cidxp;
1224 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1225 for (i = 0; i < ri.iri_nfrags; i++) {
1227 ring->slot[nm_i].len = 0;
1228 ring->slot[nm_i].flags = 0;
1230 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1231 if (i == (ri.iri_nfrags - 1)) {
1232 ring->slot[nm_i].len -= crclen;
1233 ring->slot[nm_i].flags = 0;
1235 ring->slot[nm_i].flags = NS_MOREFRAG;
1238 bus_dmamap_sync(fl->ifl_buf_tag,
1239 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1240 nm_i = nm_next(nm_i, lim);
1241 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1245 *cidxp = ri.iri_cidx;
1246 while (*cidxp >= scctx->isc_nrxd[0])
1247 *cidxp -= scctx->isc_nrxd[0];
1251 if (n) { /* update the state variables */
1252 if (netmap_no_pendintr && !force_update) {
1255 iflib_rx_miss_bufs += n;
1257 kring->nr_hwtail = nm_i;
1259 kring->nr_kflags &= ~NKR_PENDINTR;
1262 * Second part: skip past packets that userspace has released.
1263 * (kring->nr_hwcur to head excluded),
1264 * and make the buffers available for reception.
1265 * As usual nm_i is the index in the netmap ring,
1266 * nic_i is the index in the NIC ring, and
1267 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1269 netmap_fl_refill(rxq, kring, false);
1275 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1277 if_ctx_t ctx = na->ifp->if_softc;
1281 IFDI_INTR_ENABLE(ctx);
1283 IFDI_INTR_DISABLE(ctx);
1289 iflib_netmap_attach(if_ctx_t ctx)
1291 struct netmap_adapter na;
1293 bzero(&na, sizeof(na));
1295 na.ifp = ctx->ifc_ifp;
1296 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS;
1297 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1298 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1300 na.num_tx_desc = iflib_num_tx_descs(ctx);
1301 na.num_rx_desc = iflib_num_rx_descs(ctx);
1302 na.nm_txsync = iflib_netmap_txsync;
1303 na.nm_rxsync = iflib_netmap_rxsync;
1304 na.nm_register = iflib_netmap_register;
1305 na.nm_intr = iflib_netmap_intr;
1306 na.nm_config = iflib_netmap_config;
1307 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1308 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1309 return (netmap_attach(&na));
1313 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1315 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1316 struct netmap_slot *slot;
1318 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1321 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1323 * In netmap mode, set the map for the packet buffer.
1324 * NOTE: Some drivers (not this one) also need to set
1325 * the physical buffer address in the NIC ring.
1326 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1327 * netmap slot index, si
1329 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1330 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1331 NMB(na, slot + si));
1337 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1339 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1340 struct netmap_kring *kring;
1341 struct netmap_slot *slot;
1343 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1346 kring = na->rx_rings[rxq->ifr_id];
1347 netmap_fl_refill(rxq, kring, true);
1352 iflib_netmap_timer(void *arg)
1354 iflib_txq_t txq = arg;
1355 if_ctx_t ctx = txq->ift_ctx;
1358 * Wake up the netmap application, to give it a chance to
1359 * call txsync and reclaim more completed TX buffers.
1361 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1364 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1367 #define iflib_netmap_txq_init(ctx, txq) (0)
1368 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1369 #define iflib_netmap_detach(ifp)
1370 #define netmap_enable_all_rings(ifp)
1371 #define netmap_disable_all_rings(ifp)
1373 #define iflib_netmap_attach(ctx) (0)
1374 #define netmap_rx_irq(ifp, qid, budget) (0)
1377 #if defined(__i386__) || defined(__amd64__)
1378 static __inline void
1381 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1383 static __inline void
1384 prefetch2cachelines(void *x)
1386 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1387 #if (CACHE_LINE_SIZE < 128)
1388 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1393 #define prefetch2cachelines(x)
1397 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1401 fl = &rxq->ifr_fl[flid];
1402 iru->iru_paddrs = fl->ifl_bus_addrs;
1403 iru->iru_idxs = fl->ifl_rxd_idxs;
1404 iru->iru_qsidx = rxq->ifr_id;
1405 iru->iru_buf_size = fl->ifl_buf_size;
1406 iru->iru_flidx = fl->ifl_id;
1410 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1414 *(bus_addr_t *) arg = segs[0].ds_addr;
1417 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \
1418 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \
1419 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL)
1422 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1425 device_t dev = ctx->ifc_dev;
1428 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width);
1430 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1431 align, 0, /* alignment, bounds */
1432 lowaddr, /* lowaddr */
1433 BUS_SPACE_MAXADDR, /* highaddr */
1434 NULL, NULL, /* filter, filterarg */
1437 size, /* maxsegsize */
1438 BUS_DMA_ALLOCNOW, /* flags */
1439 NULL, /* lockfunc */
1444 "%s: bus_dma_tag_create failed: %d\n",
1449 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1450 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1453 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1454 __func__, (uintmax_t)size, err);
1458 dma->idi_paddr = IF_BAD_DMA;
1459 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1460 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1461 if (err || dma->idi_paddr == IF_BAD_DMA) {
1463 "%s: bus_dmamap_load failed: %d\n",
1468 dma->idi_size = size;
1472 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1474 bus_dma_tag_destroy(dma->idi_tag);
1476 dma->idi_tag = NULL;
1482 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1484 if_shared_ctx_t sctx = ctx->ifc_sctx;
1486 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1488 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1492 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1495 iflib_dma_info_t *dmaiter;
1498 for (i = 0; i < count; i++, dmaiter++) {
1499 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1503 iflib_dma_free_multi(dmalist, i);
1508 iflib_dma_free(iflib_dma_info_t dma)
1510 if (dma->idi_tag == NULL)
1512 if (dma->idi_paddr != IF_BAD_DMA) {
1513 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1514 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1515 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1516 dma->idi_paddr = IF_BAD_DMA;
1518 if (dma->idi_vaddr != NULL) {
1519 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1520 dma->idi_vaddr = NULL;
1522 bus_dma_tag_destroy(dma->idi_tag);
1523 dma->idi_tag = NULL;
1527 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1530 iflib_dma_info_t *dmaiter = dmalist;
1532 for (i = 0; i < count; i++, dmaiter++)
1533 iflib_dma_free(*dmaiter);
1537 iflib_fast_intr(void *arg)
1539 iflib_filter_info_t info = arg;
1540 struct grouptask *gtask = info->ifi_task;
1543 DBG_COUNTER_INC(fast_intrs);
1544 if (info->ifi_filter != NULL) {
1545 result = info->ifi_filter(info->ifi_filter_arg);
1546 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1550 GROUPTASK_ENQUEUE(gtask);
1551 return (FILTER_HANDLED);
1555 iflib_fast_intr_rxtx(void *arg)
1557 iflib_filter_info_t info = arg;
1558 struct grouptask *gtask = info->ifi_task;
1560 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1563 int i, cidx, result;
1565 bool intr_enable, intr_legacy;
1567 DBG_COUNTER_INC(fast_intrs);
1568 if (info->ifi_filter != NULL) {
1569 result = info->ifi_filter(info->ifi_filter_arg);
1570 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1575 sc = ctx->ifc_softc;
1576 intr_enable = false;
1577 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1578 MPASS(rxq->ifr_ntxqirq);
1579 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1580 txqid = rxq->ifr_txqid[i];
1581 txq = &ctx->ifc_txqs[txqid];
1582 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1583 BUS_DMASYNC_POSTREAD);
1584 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1588 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1591 GROUPTASK_ENQUEUE(&txq->ift_task);
1593 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1594 cidx = rxq->ifr_cq_cidx;
1596 cidx = rxq->ifr_fl[0].ifl_cidx;
1597 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1598 GROUPTASK_ENQUEUE(gtask);
1603 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1604 DBG_COUNTER_INC(rx_intr_enables);
1607 IFDI_INTR_ENABLE(ctx);
1608 return (FILTER_HANDLED);
1612 iflib_fast_intr_ctx(void *arg)
1614 iflib_filter_info_t info = arg;
1615 struct grouptask *gtask = info->ifi_task;
1618 DBG_COUNTER_INC(fast_intrs);
1619 if (info->ifi_filter != NULL) {
1620 result = info->ifi_filter(info->ifi_filter_arg);
1621 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1625 GROUPTASK_ENQUEUE(gtask);
1626 return (FILTER_HANDLED);
1630 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1631 driver_filter_t filter, driver_intr_t handler, void *arg,
1634 struct resource *res;
1636 device_t dev = ctx->ifc_dev;
1640 if (ctx->ifc_flags & IFC_LEGACY)
1641 flags |= RF_SHAREABLE;
1644 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1647 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1651 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1652 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1653 filter, handler, arg, &tag);
1656 "failed to setup interrupt for rid %d, name %s: %d\n",
1657 rid, name ? name : "unknown", rc);
1660 bus_describe_intr(dev, res, tag, "%s", name);
1666 /*********************************************************************
1668 * Allocate DMA resources for TX buffers as well as memory for the TX
1669 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1670 * iflib_sw_tx_desc_array structure, storing all the information that
1671 * is needed to transmit a packet on the wire. This is called only
1672 * once at attach, setup is done every reset.
1674 **********************************************************************/
1676 iflib_txsd_alloc(iflib_txq_t txq)
1678 if_ctx_t ctx = txq->ift_ctx;
1679 if_shared_ctx_t sctx = ctx->ifc_sctx;
1680 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1681 device_t dev = ctx->ifc_dev;
1682 bus_size_t tsomaxsize;
1684 int err, nsegments, ntsosegments;
1687 nsegments = scctx->isc_tx_nsegments;
1688 ntsosegments = scctx->isc_tx_tso_segments_max;
1689 tsomaxsize = scctx->isc_tx_tso_size_max;
1690 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1691 tsomaxsize += sizeof(struct ether_vlan_header);
1692 MPASS(scctx->isc_ntxd[0] > 0);
1693 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1694 MPASS(nsegments > 0);
1695 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1696 MPASS(ntsosegments > 0);
1697 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1700 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1703 * Set up DMA tags for TX buffers.
1705 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1706 1, 0, /* alignment, bounds */
1707 lowaddr, /* lowaddr */
1708 BUS_SPACE_MAXADDR, /* highaddr */
1709 NULL, NULL, /* filter, filterarg */
1710 sctx->isc_tx_maxsize, /* maxsize */
1711 nsegments, /* nsegments */
1712 sctx->isc_tx_maxsegsize, /* maxsegsize */
1714 NULL, /* lockfunc */
1715 NULL, /* lockfuncarg */
1716 &txq->ift_buf_tag))) {
1717 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1718 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1719 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1722 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1723 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1724 1, 0, /* alignment, bounds */
1725 lowaddr, /* lowaddr */
1726 BUS_SPACE_MAXADDR, /* highaddr */
1727 NULL, NULL, /* filter, filterarg */
1728 tsomaxsize, /* maxsize */
1729 ntsosegments, /* nsegments */
1730 sctx->isc_tso_maxsegsize,/* maxsegsize */
1732 NULL, /* lockfunc */
1733 NULL, /* lockfuncarg */
1734 &txq->ift_tso_buf_tag))) {
1735 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1740 /* Allocate memory for the TX mbuf map. */
1741 if (!(txq->ift_sds.ifsd_m =
1742 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1743 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1744 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1750 * Create the DMA maps for TX buffers.
1752 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1753 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1754 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1756 "Unable to allocate TX buffer DMA map memory\n");
1760 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1761 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1762 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1764 "Unable to allocate TSO TX buffer map memory\n");
1768 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1769 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1770 &txq->ift_sds.ifsd_map[i]);
1772 device_printf(dev, "Unable to create TX DMA map\n");
1777 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1778 &txq->ift_sds.ifsd_tso_map[i]);
1780 device_printf(dev, "Unable to create TSO TX DMA map\n");
1786 /* We free all, it handles case where we are in the middle */
1787 iflib_tx_structures_free(ctx);
1792 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1796 if (txq->ift_sds.ifsd_map != NULL) {
1797 map = txq->ift_sds.ifsd_map[i];
1798 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1799 bus_dmamap_unload(txq->ift_buf_tag, map);
1800 bus_dmamap_destroy(txq->ift_buf_tag, map);
1801 txq->ift_sds.ifsd_map[i] = NULL;
1804 if (txq->ift_sds.ifsd_tso_map != NULL) {
1805 map = txq->ift_sds.ifsd_tso_map[i];
1806 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1807 BUS_DMASYNC_POSTWRITE);
1808 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1809 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1810 txq->ift_sds.ifsd_tso_map[i] = NULL;
1815 iflib_txq_destroy(iflib_txq_t txq)
1817 if_ctx_t ctx = txq->ift_ctx;
1819 for (int i = 0; i < txq->ift_size; i++)
1820 iflib_txsd_destroy(ctx, txq, i);
1822 if (txq->ift_br != NULL) {
1823 ifmp_ring_free(txq->ift_br);
1827 mtx_destroy(&txq->ift_mtx);
1829 if (txq->ift_sds.ifsd_map != NULL) {
1830 free(txq->ift_sds.ifsd_map, M_IFLIB);
1831 txq->ift_sds.ifsd_map = NULL;
1833 if (txq->ift_sds.ifsd_tso_map != NULL) {
1834 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1835 txq->ift_sds.ifsd_tso_map = NULL;
1837 if (txq->ift_sds.ifsd_m != NULL) {
1838 free(txq->ift_sds.ifsd_m, M_IFLIB);
1839 txq->ift_sds.ifsd_m = NULL;
1841 if (txq->ift_buf_tag != NULL) {
1842 bus_dma_tag_destroy(txq->ift_buf_tag);
1843 txq->ift_buf_tag = NULL;
1845 if (txq->ift_tso_buf_tag != NULL) {
1846 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1847 txq->ift_tso_buf_tag = NULL;
1849 if (txq->ift_ifdi != NULL) {
1850 free(txq->ift_ifdi, M_IFLIB);
1855 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1859 mp = &txq->ift_sds.ifsd_m[i];
1863 if (txq->ift_sds.ifsd_map != NULL) {
1864 bus_dmamap_sync(txq->ift_buf_tag,
1865 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1866 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1868 if (txq->ift_sds.ifsd_tso_map != NULL) {
1869 bus_dmamap_sync(txq->ift_tso_buf_tag,
1870 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1871 bus_dmamap_unload(txq->ift_tso_buf_tag,
1872 txq->ift_sds.ifsd_tso_map[i]);
1875 DBG_COUNTER_INC(tx_frees);
1880 iflib_txq_setup(iflib_txq_t txq)
1882 if_ctx_t ctx = txq->ift_ctx;
1883 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1884 if_shared_ctx_t sctx = ctx->ifc_sctx;
1885 iflib_dma_info_t di;
1888 /* Set number of descriptors available */
1889 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1890 /* XXX make configurable */
1891 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1894 txq->ift_cidx_processed = 0;
1895 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1896 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1898 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1899 bzero((void *)di->idi_vaddr, di->idi_size);
1901 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1902 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1903 bus_dmamap_sync(di->idi_tag, di->idi_map,
1904 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1908 /*********************************************************************
1910 * Allocate DMA resources for RX buffers as well as memory for the RX
1911 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1912 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1913 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1914 * Since we use use one entry in iflib_sw_rx_desc_array per received
1915 * packet, the maximum number of entries we'll need is equal to the
1916 * number of hardware receive descriptors that we've allocated.
1918 **********************************************************************/
1920 iflib_rxsd_alloc(iflib_rxq_t rxq)
1922 if_ctx_t ctx = rxq->ifr_ctx;
1923 if_shared_ctx_t sctx = ctx->ifc_sctx;
1924 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1925 device_t dev = ctx->ifc_dev;
1930 MPASS(scctx->isc_nrxd[0] > 0);
1931 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1933 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1936 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1937 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1938 /* Set up DMA tag for RX buffers. */
1939 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1940 1, 0, /* alignment, bounds */
1941 lowaddr, /* lowaddr */
1942 BUS_SPACE_MAXADDR, /* highaddr */
1943 NULL, NULL, /* filter, filterarg */
1944 sctx->isc_rx_maxsize, /* maxsize */
1945 sctx->isc_rx_nsegments, /* nsegments */
1946 sctx->isc_rx_maxsegsize, /* maxsegsize */
1948 NULL, /* lockfunc */
1953 "Unable to allocate RX DMA tag: %d\n", err);
1957 /* Allocate memory for the RX mbuf map. */
1958 if (!(fl->ifl_sds.ifsd_m =
1959 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1960 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1962 "Unable to allocate RX mbuf map memory\n");
1967 /* Allocate memory for the direct RX cluster pointer map. */
1968 if (!(fl->ifl_sds.ifsd_cl =
1969 (caddr_t *) malloc(sizeof(caddr_t) *
1970 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1972 "Unable to allocate RX cluster map memory\n");
1977 /* Allocate memory for the RX cluster bus address map. */
1978 if (!(fl->ifl_sds.ifsd_ba =
1979 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1980 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1982 "Unable to allocate RX bus address map memory\n");
1988 * Create the DMA maps for RX buffers.
1990 if (!(fl->ifl_sds.ifsd_map =
1991 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1993 "Unable to allocate RX buffer DMA map memory\n");
1997 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1998 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1999 &fl->ifl_sds.ifsd_map[i]);
2001 device_printf(dev, "Unable to create RX buffer DMA map\n");
2009 iflib_rx_structures_free(ctx);
2014 * Internal service routines
2017 struct rxq_refill_cb_arg {
2019 bus_dma_segment_t seg;
2024 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2026 struct rxq_refill_cb_arg *cb_arg = arg;
2028 cb_arg->error = error;
2029 cb_arg->seg = segs[0];
2030 cb_arg->nseg = nseg;
2034 * iflib_fl_refill - refill an rxq free-buffer list
2035 * @ctx: the iflib context
2036 * @fl: the free list to refill
2037 * @count: the number of new buffers to allocate
2039 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2040 * The caller must assure that @count does not exceed the queue's capacity
2041 * minus one (since we always leave a descriptor unavailable).
2044 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2046 struct if_rxd_update iru;
2047 struct rxq_refill_cb_arg cb_arg;
2051 bus_dmamap_t *sd_map;
2052 bus_addr_t bus_addr, *sd_ba;
2053 int err, frag_idx, i, idx, n, pidx;
2056 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2058 sd_m = fl->ifl_sds.ifsd_m;
2059 sd_map = fl->ifl_sds.ifsd_map;
2060 sd_cl = fl->ifl_sds.ifsd_cl;
2061 sd_ba = fl->ifl_sds.ifsd_ba;
2062 pidx = fl->ifl_pidx;
2064 frag_idx = fl->ifl_fragidx;
2065 credits = fl->ifl_credits;
2070 MPASS(credits + n <= fl->ifl_size);
2072 if (pidx < fl->ifl_cidx)
2073 MPASS(pidx + n <= fl->ifl_cidx);
2074 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2075 MPASS(fl->ifl_gen == 0);
2076 if (pidx > fl->ifl_cidx)
2077 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2079 DBG_COUNTER_INC(fl_refills);
2081 DBG_COUNTER_INC(fl_refills_large);
2082 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2085 * We allocate an uninitialized mbuf + cluster, mbuf is
2086 * initialized after rx.
2088 * If the cluster is still set then we know a minimum sized
2089 * packet was received
2091 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2094 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2095 MPASS(frag_idx >= 0);
2096 if ((cl = sd_cl[frag_idx]) == NULL) {
2097 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2098 if (__predict_false(cl == NULL))
2102 MPASS(sd_map != NULL);
2103 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2104 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2106 if (__predict_false(err != 0 || cb_arg.error)) {
2107 uma_zfree(fl->ifl_zone, cl);
2111 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2112 sd_cl[frag_idx] = cl;
2114 fl->ifl_cl_enqueued++;
2117 bus_addr = sd_ba[frag_idx];
2119 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2120 BUS_DMASYNC_PREREAD);
2122 if (sd_m[frag_idx] == NULL) {
2123 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2124 if (__predict_false(m == NULL))
2128 bit_set(fl->ifl_rx_bitmap, frag_idx);
2130 fl->ifl_m_enqueued++;
2133 DBG_COUNTER_INC(rx_allocs);
2134 fl->ifl_rxd_idxs[i] = frag_idx;
2135 fl->ifl_bus_addrs[i] = bus_addr;
2138 MPASS(credits <= fl->ifl_size);
2139 if (++idx == fl->ifl_size) {
2145 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2146 iru.iru_pidx = pidx;
2148 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2150 fl->ifl_credits = credits;
2156 if (n < count - 1) {
2158 iru.iru_pidx = pidx;
2160 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2162 fl->ifl_credits = credits;
2164 DBG_COUNTER_INC(rxd_flush);
2165 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2166 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2167 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2168 fl->ifl_id, fl->ifl_pidx);
2169 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2170 fl->ifl_fragidx = frag_idx + 1;
2171 if (fl->ifl_fragidx == fl->ifl_size)
2172 fl->ifl_fragidx = 0;
2174 fl->ifl_fragidx = frag_idx;
2178 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2181 static inline uint8_t
2182 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2185 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2186 * This is important as it confuses most NICs. For instance,
2187 * Intel NICs have (per receive ring) RDH and RDT registers, where
2188 * RDH points to the next receive descriptor to be used by the NIC,
2189 * and RDT for the next receive descriptor to be published by the
2190 * driver to the NIC (RDT - 1 is thus the last valid one).
2191 * The condition RDH == RDT means no descriptors are available to
2192 * the NIC, and thus it would be ambiguous if it also meant that
2193 * all the descriptors are available to the NIC.
2195 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2197 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2200 MPASS(fl->ifl_credits <= fl->ifl_size);
2201 MPASS(reclaimable == delta);
2203 if (reclaimable > 0)
2204 return (iflib_fl_refill(ctx, fl, reclaimable));
2209 iflib_in_detach(if_ctx_t ctx)
2214 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2220 iflib_fl_bufs_free(iflib_fl_t fl)
2222 iflib_dma_info_t idi = fl->ifl_ifdi;
2223 bus_dmamap_t sd_map;
2226 for (i = 0; i < fl->ifl_size; i++) {
2227 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2228 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2230 if (*sd_cl != NULL) {
2231 sd_map = fl->ifl_sds.ifsd_map[i];
2232 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2233 BUS_DMASYNC_POSTREAD);
2234 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2235 uma_zfree(fl->ifl_zone, *sd_cl);
2237 if (*sd_m != NULL) {
2238 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2239 uma_zfree(zone_mbuf, *sd_m);
2243 MPASS(*sd_m == NULL);
2246 fl->ifl_m_dequeued++;
2247 fl->ifl_cl_dequeued++;
2251 for (i = 0; i < fl->ifl_size; i++) {
2252 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2253 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2257 * Reset free list values
2259 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2260 bzero(idi->idi_vaddr, idi->idi_size);
2263 /*********************************************************************
2265 * Initialize a free list and its buffers.
2267 **********************************************************************/
2269 iflib_fl_setup(iflib_fl_t fl)
2271 iflib_rxq_t rxq = fl->ifl_rxq;
2272 if_ctx_t ctx = rxq->ifr_ctx;
2273 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2276 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2278 ** Free current RX buffer structs and their mbufs
2280 iflib_fl_bufs_free(fl);
2281 /* Now replenish the mbufs */
2282 MPASS(fl->ifl_credits == 0);
2283 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2284 if (scctx->isc_rxd_buf_size[qidx] != 0)
2285 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2287 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2289 * ifl_buf_size may be a driver-supplied value, so pull it up
2290 * to the selected mbuf size.
2292 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2293 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2294 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2295 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2296 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2299 * Avoid pre-allocating zillions of clusters to an idle card
2300 * potentially speeding up attach. In any case make sure
2301 * to leave a descriptor unavailable. See the comment in
2302 * iflib_fl_refill_all().
2304 MPASS(fl->ifl_size > 0);
2305 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2306 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2312 MPASS(fl->ifl_ifdi != NULL);
2313 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2318 /*********************************************************************
2320 * Free receive ring data structures
2322 **********************************************************************/
2324 iflib_rx_sds_free(iflib_rxq_t rxq)
2329 if (rxq->ifr_fl != NULL) {
2330 for (i = 0; i < rxq->ifr_nfl; i++) {
2331 fl = &rxq->ifr_fl[i];
2332 if (fl->ifl_buf_tag != NULL) {
2333 if (fl->ifl_sds.ifsd_map != NULL) {
2334 for (j = 0; j < fl->ifl_size; j++) {
2337 fl->ifl_sds.ifsd_map[j],
2338 BUS_DMASYNC_POSTREAD);
2341 fl->ifl_sds.ifsd_map[j]);
2344 fl->ifl_sds.ifsd_map[j]);
2347 bus_dma_tag_destroy(fl->ifl_buf_tag);
2348 fl->ifl_buf_tag = NULL;
2350 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2351 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2352 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2353 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2354 free(fl->ifl_rx_bitmap, M_IFLIB);
2355 fl->ifl_sds.ifsd_m = NULL;
2356 fl->ifl_sds.ifsd_cl = NULL;
2357 fl->ifl_sds.ifsd_ba = NULL;
2358 fl->ifl_sds.ifsd_map = NULL;
2359 fl->ifl_rx_bitmap = NULL;
2361 free(rxq->ifr_fl, M_IFLIB);
2363 free(rxq->ifr_ifdi, M_IFLIB);
2364 rxq->ifr_ifdi = NULL;
2365 rxq->ifr_cq_cidx = 0;
2373 iflib_timer(void *arg)
2375 iflib_txq_t txq = arg;
2376 if_ctx_t ctx = txq->ift_ctx;
2377 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2378 uint64_t this_tick = ticks;
2380 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2384 ** Check on the state of the TX queue(s), this
2385 ** can be done without the lock because its RO
2386 ** and the HUNG state will be static if set.
2388 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2389 txq->ift_last_timer_tick = this_tick;
2390 IFDI_TIMER(ctx, txq->ift_id);
2391 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2392 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2393 (sctx->isc_pause_frames == 0)))
2396 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2397 ifmp_ring_is_stalled(txq->ift_br)) {
2398 KASSERT(ctx->ifc_link_state == LINK_STATE_UP,
2399 ("queue can't be marked as hung if interface is down"));
2400 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2402 txq->ift_cleaned_prev = txq->ift_cleaned;
2404 /* handle any laggards */
2405 if (txq->ift_db_pending)
2406 GROUPTASK_ENQUEUE(&txq->ift_task);
2408 sctx->isc_pause_frames = 0;
2409 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2410 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2411 txq, txq->ift_timer.c_cpu);
2415 device_printf(ctx->ifc_dev,
2416 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2417 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2419 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2420 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2421 iflib_admin_intr_deferred(ctx);
2426 iflib_get_mbuf_size_for(unsigned int size)
2429 if (size <= MCLBYTES)
2432 return (MJUMPAGESIZE);
2436 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2438 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2441 * XXX don't set the max_frame_size to larger
2442 * than the hardware can handle
2444 ctx->ifc_rx_mbuf_sz =
2445 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2449 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2452 return (ctx->ifc_rx_mbuf_sz);
2456 iflib_init_locked(if_ctx_t ctx)
2458 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2459 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2460 if_t ifp = ctx->ifc_ifp;
2464 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2466 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2467 IFDI_INTR_DISABLE(ctx);
2470 * See iflib_stop(). Useful in case iflib_init_locked() is
2471 * called without first calling iflib_stop().
2473 netmap_disable_all_rings(ifp);
2475 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2476 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2477 /* Set hardware offload abilities */
2478 if_clearhwassist(ifp);
2479 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2480 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2481 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2482 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2483 if (if_getcapenable(ifp) & IFCAP_TSO4)
2484 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2485 if (if_getcapenable(ifp) & IFCAP_TSO6)
2486 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2488 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2490 callout_stop(&txq->ift_timer);
2492 callout_stop(&txq->ift_netmap_timer);
2493 #endif /* DEV_NETMAP */
2494 CALLOUT_UNLOCK(txq);
2495 (void)iflib_netmap_txq_init(ctx, txq);
2499 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2500 * that drivers can use the value when setting up the hardware receive
2503 iflib_calc_rx_mbuf_sz(ctx);
2506 i = if_getdrvflags(ifp);
2509 MPASS(if_getdrvflags(ifp) == i);
2510 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2511 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2512 /* This rxq is in netmap mode. Skip normal init. */
2515 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2516 if (iflib_fl_setup(fl)) {
2517 device_printf(ctx->ifc_dev,
2518 "setting up free list %d failed - "
2519 "check cluster settings\n", j);
2525 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2526 IFDI_INTR_ENABLE(ctx);
2527 txq = ctx->ifc_txqs;
2528 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2529 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2530 txq->ift_timer.c_cpu);
2532 /* Re-enable txsync/rxsync. */
2533 netmap_enable_all_rings(ifp);
2537 iflib_media_change(if_t ifp)
2539 if_ctx_t ctx = if_getsoftc(ifp);
2543 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2544 iflib_if_init_locked(ctx);
2550 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2552 if_ctx_t ctx = if_getsoftc(ifp);
2555 IFDI_UPDATE_ADMIN_STATUS(ctx);
2556 IFDI_MEDIA_STATUS(ctx, ifmr);
2561 iflib_stop(if_ctx_t ctx)
2563 iflib_txq_t txq = ctx->ifc_txqs;
2564 iflib_rxq_t rxq = ctx->ifc_rxqs;
2565 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2566 if_shared_ctx_t sctx = ctx->ifc_sctx;
2567 iflib_dma_info_t di;
2571 /* Tell the stack that the interface is no longer active */
2572 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2574 IFDI_INTR_DISABLE(ctx);
2580 * Stop any pending txsync/rxsync and prevent new ones
2581 * form starting. Processes blocked in poll() will get
2584 netmap_disable_all_rings(ctx->ifc_ifp);
2586 iflib_debug_reset();
2587 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2588 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2589 /* make sure all transmitters have completed before proceeding XXX */
2592 callout_stop(&txq->ift_timer);
2594 callout_stop(&txq->ift_netmap_timer);
2595 #endif /* DEV_NETMAP */
2596 CALLOUT_UNLOCK(txq);
2598 /* clean any enqueued buffers */
2599 iflib_ifmp_purge(txq);
2600 /* Free any existing tx buffers. */
2601 for (j = 0; j < txq->ift_size; j++) {
2602 iflib_txsd_free(ctx, txq, j);
2604 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2605 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2606 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2607 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2608 txq->ift_pullups = 0;
2609 ifmp_ring_reset_stats(txq->ift_br);
2610 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2611 bzero((void *)di->idi_vaddr, di->idi_size);
2613 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2614 /* make sure all transmitters have completed before proceeding XXX */
2616 rxq->ifr_cq_cidx = 0;
2617 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2618 bzero((void *)di->idi_vaddr, di->idi_size);
2619 /* also resets the free lists pidx/cidx */
2620 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2621 iflib_fl_bufs_free(fl);
2625 static inline caddr_t
2626 calc_next_rxd(iflib_fl_t fl, int cidx)
2630 caddr_t start, end, cur, next;
2632 nrxd = fl->ifl_size;
2633 size = fl->ifl_rxd_size;
2634 start = fl->ifl_ifdi->idi_vaddr;
2636 if (__predict_false(size == 0))
2638 cur = start + size*cidx;
2639 end = start + size*nrxd;
2640 next = CACHE_PTR_NEXT(cur);
2641 return (next < end ? next : start);
2645 prefetch_pkts(iflib_fl_t fl, int cidx)
2648 int nrxd = fl->ifl_size;
2651 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2652 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2653 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2654 next_rxd = calc_next_rxd(fl, cidx);
2656 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2657 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2658 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2659 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2660 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2661 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2662 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2663 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2666 static struct mbuf *
2667 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2668 int *pf_rv, if_rxd_info_t ri)
2674 int flid, cidx, len, next;
2677 flid = irf->irf_flid;
2678 cidx = irf->irf_idx;
2679 fl = &rxq->ifr_fl[flid];
2681 m = fl->ifl_sds.ifsd_m[cidx];
2682 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2685 fl->ifl_m_dequeued++;
2687 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2688 prefetch_pkts(fl, cidx);
2689 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2690 prefetch(&fl->ifl_sds.ifsd_map[next]);
2691 map = fl->ifl_sds.ifsd_map[cidx];
2693 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2695 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2696 irf->irf_len != 0) {
2697 payload = *sd->ifsd_cl;
2698 payload += ri->iri_pad;
2699 len = ri->iri_len - ri->iri_pad;
2700 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2701 len | PFIL_MEMPTR | PFIL_IN, NULL);
2706 * The filter ate it. Everything is recycled.
2711 case PFIL_REALLOCED:
2713 * The filter copied it. Everything is recycled.
2715 m = pfil_mem2mbuf(payload);
2720 * Filter said it was OK, so receive like
2723 fl->ifl_sds.ifsd_m[cidx] = NULL;
2729 fl->ifl_sds.ifsd_m[cidx] = NULL;
2734 if (unload && irf->irf_len != 0)
2735 bus_dmamap_unload(fl->ifl_buf_tag, map);
2736 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2737 if (__predict_false(fl->ifl_cidx == 0))
2739 bit_clear(fl->ifl_rx_bitmap, cidx);
2743 static struct mbuf *
2744 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2746 struct mbuf *m, *mh, *mt;
2748 int *pf_rv_ptr, flags, i, padlen;
2757 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2760 MPASS(*sd->ifsd_cl != NULL);
2763 * Exclude zero-length frags & frags from
2764 * packets the filter has consumed or dropped
2766 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2767 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2769 /* everything saved here */
2774 /* XXX we can save the cluster here, but not the mbuf */
2775 m_init(m, M_NOWAIT, MT_DATA, 0);
2780 flags = M_PKTHDR|M_EXT;
2782 padlen = ri->iri_pad;
2787 /* assuming padding is only on the first fragment */
2791 *sd->ifsd_cl = NULL;
2793 /* Can these two be made one ? */
2794 m_init(m, M_NOWAIT, MT_DATA, flags);
2795 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2797 * These must follow m_init and m_cljset
2799 m->m_data += padlen;
2800 ri->iri_len -= padlen;
2801 m->m_len = ri->iri_frags[i].irf_len;
2802 } while (++i < ri->iri_nfrags);
2808 * Process one software descriptor
2810 static struct mbuf *
2811 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2817 /* should I merge this back in now that the two paths are basically duplicated? */
2818 if (ri->iri_nfrags == 1 &&
2819 ri->iri_frags[0].irf_len != 0 &&
2820 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2821 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2823 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2825 if (pf_rv == PFIL_PASS) {
2826 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2827 #ifndef __NO_STRICT_ALIGNMENT
2831 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2832 m->m_len = ri->iri_frags[0].irf_len;
2835 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2838 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2841 m->m_pkthdr.len = ri->iri_len;
2842 m->m_pkthdr.rcvif = ri->iri_ifp;
2843 m->m_flags |= ri->iri_flags;
2844 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2845 m->m_pkthdr.flowid = ri->iri_flowid;
2846 M_HASHTYPE_SET(m, ri->iri_rsstype);
2847 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2848 m->m_pkthdr.csum_data = ri->iri_csum_data;
2852 #if defined(INET6) || defined(INET)
2854 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2856 CURVNET_SET(lc->ifp->if_vnet);
2858 *v6 = V_ip6_forwarding;
2861 *v4 = V_ipforwarding;
2867 * Returns true if it's possible this packet could be LROed.
2868 * if it returns false, it is guaranteed that tcp_lro_rx()
2869 * would not return zero.
2872 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2874 struct ether_header *eh;
2876 eh = mtod(m, struct ether_header *);
2877 switch (eh->ether_type) {
2879 case htons(ETHERTYPE_IPV6):
2880 return (!v6_forwarding);
2883 case htons(ETHERTYPE_IP):
2884 return (!v4_forwarding);
2892 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2898 _task_fn_rx_watchdog(void *context)
2900 iflib_rxq_t rxq = context;
2902 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2906 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2909 if_ctx_t ctx = rxq->ifr_ctx;
2910 if_shared_ctx_t sctx = ctx->ifc_sctx;
2911 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2914 struct if_rxd_info ri;
2915 int err, budget_left, rx_bytes, rx_pkts;
2918 bool v4_forwarding, v6_forwarding, lro_possible;
2922 * XXX early demux data packets so that if_input processing only handles
2923 * acks in interrupt context
2925 struct mbuf *m, *mh, *mt, *mf;
2929 lro_possible = v4_forwarding = v6_forwarding = false;
2933 rx_pkts = rx_bytes = 0;
2934 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2935 cidxp = &rxq->ifr_cq_cidx;
2937 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2938 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2939 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2940 retval |= iflib_fl_refill_all(ctx, fl);
2941 DBG_COUNTER_INC(rx_unavail);
2945 /* pfil needs the vnet to be set */
2946 CURVNET_SET_QUIET(ifp->if_vnet);
2947 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2948 if (__predict_false(!CTX_ACTIVE(ctx))) {
2949 DBG_COUNTER_INC(rx_ctx_inactive);
2953 * Reset client set fields to their default values
2956 ri.iri_qsidx = rxq->ifr_id;
2957 ri.iri_cidx = *cidxp;
2959 ri.iri_frags = rxq->ifr_frags;
2960 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2965 rx_bytes += ri.iri_len;
2966 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2967 *cidxp = ri.iri_cidx;
2968 /* Update our consumer index */
2969 /* XXX NB: shurd - check if this is still safe */
2970 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2971 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2972 /* was this only a completion queue message? */
2973 if (__predict_false(ri.iri_nfrags == 0))
2976 MPASS(ri.iri_nfrags != 0);
2977 MPASS(ri.iri_len != 0);
2979 /* will advance the cidx on the corresponding free lists */
2980 m = iflib_rxd_pkt_get(rxq, &ri);
2983 if (avail == 0 && budget_left)
2984 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2986 if (__predict_false(m == NULL))
2989 /* imm_pkt: -- cxgb */
2998 /* make sure that we can refill faster than drain */
2999 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3000 retval |= iflib_fl_refill_all(ctx, fl);
3002 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
3004 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
3006 while (mh != NULL) {
3009 m->m_nextpkt = NULL;
3010 #ifndef __NO_STRICT_ALIGNMENT
3011 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
3014 #if defined(INET6) || defined(INET)
3016 if (!lro_possible) {
3017 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
3018 if (lro_possible && mf != NULL) {
3019 ifp->if_input(ifp, mf);
3020 DBG_COUNTER_INC(rx_if_input);
3024 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
3025 (CSUM_L4_CALC|CSUM_L4_VALID)) {
3026 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
3032 ifp->if_input(ifp, m);
3033 DBG_COUNTER_INC(rx_if_input);
3044 ifp->if_input(ifp, mf);
3045 DBG_COUNTER_INC(rx_if_input);
3048 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3049 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3052 * Flush any outstanding LRO work
3054 #if defined(INET6) || defined(INET)
3055 tcp_lro_flush_all(&rxq->ifr_lc);
3057 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3058 retval |= IFLIB_RXEOF_MORE;
3062 ctx->ifc_flags |= IFC_DO_RESET;
3063 iflib_admin_intr_deferred(ctx);
3068 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
3069 static inline qidx_t
3070 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3072 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3073 qidx_t minthresh = txq->ift_size / 8;
3074 if (in_use > 4*minthresh)
3075 return (notify_count);
3076 if (in_use > 2*minthresh)
3077 return (notify_count >> 1);
3078 if (in_use > minthresh)
3079 return (notify_count >> 3);
3083 static inline qidx_t
3084 txq_max_rs_deferred(iflib_txq_t txq)
3086 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3087 qidx_t minthresh = txq->ift_size / 8;
3088 if (txq->ift_in_use > 4*minthresh)
3089 return (notify_count);
3090 if (txq->ift_in_use > 2*minthresh)
3091 return (notify_count >> 1);
3092 if (txq->ift_in_use > minthresh)
3093 return (notify_count >> 2);
3097 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3098 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3100 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3101 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3102 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3104 /* forward compatibility for cxgb */
3105 #define FIRST_QSET(ctx) 0
3106 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3107 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3108 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3109 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3111 /* XXX we should be setting this to something other than zero */
3112 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3113 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3114 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3117 iflib_txd_db_check(iflib_txq_t txq, int ring)
3119 if_ctx_t ctx = txq->ift_ctx;
3122 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3124 /* force || threshold exceeded || at the edge of the ring */
3125 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) {
3128 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3129 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3130 * producer index explicitly (INTC).
3132 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3133 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3134 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3135 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3138 * Absent bugs there are zero packets pending so reset pending counts to zero.
3140 txq->ift_db_pending = txq->ift_npending = 0;
3148 print_pkt(if_pkt_info_t pi)
3150 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3151 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3152 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3153 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3154 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3155 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3159 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3160 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3161 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3162 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3165 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3167 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3168 struct ether_vlan_header *eh;
3172 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3173 M_WRITABLE(m) == 0) {
3174 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3178 DBG_COUNTER_INC(tx_frees);
3184 * Determine where frame payload starts.
3185 * Jump over vlan headers if already present,
3186 * helpful for QinQ too.
3188 if (__predict_false(m->m_len < sizeof(*eh))) {
3190 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3193 eh = mtod(m, struct ether_vlan_header *);
3194 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3195 pi->ipi_etype = ntohs(eh->evl_proto);
3196 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3198 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3199 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3202 switch (pi->ipi_etype) {
3207 struct ip *ip = NULL;
3208 struct tcphdr *th = NULL;
3211 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3212 if (__predict_false(m->m_len < minthlen)) {
3214 * if this code bloat is causing too much of a hit
3215 * move it to a separate function and mark it noinline
3217 if (m->m_len == pi->ipi_ehdrlen) {
3220 if (n->m_len >= sizeof(*ip)) {
3221 ip = (struct ip *)n->m_data;
3222 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3223 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3226 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3228 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3232 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3234 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3235 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3236 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3239 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3240 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3241 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3243 pi->ipi_ip_hlen = ip->ip_hl << 2;
3244 pi->ipi_ipproto = ip->ip_p;
3245 pi->ipi_flags |= IPI_TX_IPV4;
3247 /* TCP checksum offload may require TCP header length */
3248 if (IS_TX_OFFLOAD4(pi)) {
3249 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3250 if (__predict_false(th == NULL)) {
3252 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3254 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3256 pi->ipi_tcp_hflags = th->th_flags;
3257 pi->ipi_tcp_hlen = th->th_off << 2;
3258 pi->ipi_tcp_seq = th->th_seq;
3261 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3264 * TSO always requires hardware checksum offload.
3266 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3267 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3268 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3269 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3270 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3272 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3276 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3283 case ETHERTYPE_IPV6:
3285 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3287 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3289 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3291 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3294 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3296 /* XXX-BZ this will go badly in case of ext hdrs. */
3297 pi->ipi_ipproto = ip6->ip6_nxt;
3298 pi->ipi_flags |= IPI_TX_IPV6;
3300 /* TCP checksum offload may require TCP header length */
3301 if (IS_TX_OFFLOAD6(pi)) {
3302 if (pi->ipi_ipproto == IPPROTO_TCP) {
3303 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3305 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3308 pi->ipi_tcp_hflags = th->th_flags;
3309 pi->ipi_tcp_hlen = th->th_off << 2;
3310 pi->ipi_tcp_seq = th->th_seq;
3313 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3316 * TSO always requires hardware checksum offload.
3318 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3319 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3320 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3327 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3328 pi->ipi_ip_hlen = 0;
3337 * If dodgy hardware rejects the scatter gather chain we've handed it
3338 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3341 static __noinline struct mbuf *
3342 iflib_remove_mbuf(iflib_txq_t txq)
3345 struct mbuf *m, **ifsd_m;
3347 ifsd_m = txq->ift_sds.ifsd_m;
3348 ntxd = txq->ift_size;
3349 pidx = txq->ift_pidx & (ntxd - 1);
3350 ifsd_m = txq->ift_sds.ifsd_m;
3352 ifsd_m[pidx] = NULL;
3353 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3354 if (txq->ift_sds.ifsd_tso_map != NULL)
3355 bus_dmamap_unload(txq->ift_tso_buf_tag,
3356 txq->ift_sds.ifsd_tso_map[pidx]);
3358 txq->ift_dequeued++;
3363 static inline caddr_t
3364 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3368 caddr_t start, end, cur, next;
3370 ntxd = txq->ift_size;
3371 size = txq->ift_txd_size[qid];
3372 start = txq->ift_ifdi[qid].idi_vaddr;
3374 if (__predict_false(size == 0))
3376 cur = start + size*cidx;
3377 end = start + size*ntxd;
3378 next = CACHE_PTR_NEXT(cur);
3379 return (next < end ? next : start);
3383 * Pad an mbuf to ensure a minimum ethernet frame size.
3384 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3386 static __noinline int
3387 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3390 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3391 * and ARP message is the smallest common payload I can think of
3393 static char pad[18]; /* just zeros */
3395 struct mbuf *new_head;
3397 if (!M_WRITABLE(*m_head)) {
3398 new_head = m_dup(*m_head, M_NOWAIT);
3399 if (new_head == NULL) {
3401 device_printf(dev, "cannot pad short frame, m_dup() failed");
3402 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3403 DBG_COUNTER_INC(tx_frees);
3410 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3411 n > 0; n -= sizeof(pad))
3412 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3417 device_printf(dev, "cannot pad short frame\n");
3418 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3419 DBG_COUNTER_INC(tx_frees);
3427 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3430 if_shared_ctx_t sctx;
3431 if_softc_ctx_t scctx;
3432 bus_dma_tag_t buf_tag;
3433 bus_dma_segment_t *segs;
3434 struct mbuf *m_head, **ifsd_m;
3437 struct if_pkt_info pi;
3439 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3442 sctx = ctx->ifc_sctx;
3443 scctx = &ctx->ifc_softc_ctx;
3444 segs = txq->ift_segs;
3445 ntxd = txq->ift_size;
3450 * If we're doing TSO the next descriptor to clean may be quite far ahead
3452 cidx = txq->ift_cidx;
3453 pidx = txq->ift_pidx;
3454 if (ctx->ifc_flags & IFC_PREFETCH) {
3455 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3456 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3457 next_txd = calc_next_txd(txq, cidx, 0);
3461 /* prefetch the next cache line of mbuf pointers and flags */
3462 prefetch(&txq->ift_sds.ifsd_m[next]);
3463 prefetch(&txq->ift_sds.ifsd_map[next]);
3464 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3466 map = txq->ift_sds.ifsd_map[pidx];
3467 ifsd_m = txq->ift_sds.ifsd_m;
3469 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3470 buf_tag = txq->ift_tso_buf_tag;
3471 max_segs = scctx->isc_tx_tso_segments_max;
3472 map = txq->ift_sds.ifsd_tso_map[pidx];
3473 MPASS(buf_tag != NULL);
3474 MPASS(max_segs > 0);
3476 buf_tag = txq->ift_buf_tag;
3477 max_segs = scctx->isc_tx_nsegments;
3478 map = txq->ift_sds.ifsd_map[pidx];
3480 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3481 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3482 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3484 DBG_COUNTER_INC(encap_txd_encap_fail);
3491 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3493 pi.ipi_qsidx = txq->ift_id;
3494 pi.ipi_len = m_head->m_pkthdr.len;
3495 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3496 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3498 /* deliberate bitwise OR to make one condition */
3499 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3500 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3501 DBG_COUNTER_INC(encap_txd_encap_fail);
3508 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3511 if (__predict_false(err)) {
3514 /* try collapse once and defrag once */
3516 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3517 /* try defrag if collapsing fails */
3522 txq->ift_mbuf_defrag++;
3523 m_head = m_defrag(*m_headp, M_NOWAIT);
3526 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3527 * failed to map an mbuf that was run through m_defrag
3530 if (__predict_false(m_head == NULL || remap > 1))
3537 txq->ift_no_tx_dma_setup++;
3540 txq->ift_no_tx_dma_setup++;
3542 DBG_COUNTER_INC(tx_frees);
3546 txq->ift_map_failed++;
3547 DBG_COUNTER_INC(encap_load_mbuf_fail);
3548 DBG_COUNTER_INC(encap_txd_encap_fail);
3551 ifsd_m[pidx] = m_head;
3553 * XXX assumes a 1 to 1 relationship between segments and
3554 * descriptors - this does not hold true on all drivers, e.g.
3557 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3558 txq->ift_no_desc_avail++;
3559 bus_dmamap_unload(buf_tag, map);
3560 DBG_COUNTER_INC(encap_txq_avail_fail);
3561 DBG_COUNTER_INC(encap_txd_encap_fail);
3562 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3563 GROUPTASK_ENQUEUE(&txq->ift_task);
3567 * On Intel cards we can greatly reduce the number of TX interrupts
3568 * we see by only setting report status on every Nth descriptor.
3569 * However, this also means that the driver will need to keep track
3570 * of the descriptors that RS was set on to check them for the DD bit.
3572 txq->ift_rs_pending += nsegs + 1;
3573 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3574 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3575 pi.ipi_flags |= IPI_TX_INTR;
3576 txq->ift_rs_pending = 0;
3580 pi.ipi_nsegs = nsegs;
3582 MPASS(pidx >= 0 && pidx < txq->ift_size);
3586 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3587 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3588 DBG_COUNTER_INC(tx_encap);
3589 MPASS(pi.ipi_new_pidx < txq->ift_size);
3591 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3592 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3593 ndesc += txq->ift_size;
3597 * drivers can need as many as
3600 MPASS(ndesc <= pi.ipi_nsegs + 2);
3601 MPASS(pi.ipi_new_pidx != pidx);
3603 txq->ift_in_use += ndesc;
3604 txq->ift_db_pending += ndesc;
3607 * We update the last software descriptor again here because there may
3608 * be a sentinel and/or there may be more mbufs than segments
3610 txq->ift_pidx = pi.ipi_new_pidx;
3611 txq->ift_npending += pi.ipi_ndescs;
3613 *m_headp = m_head = iflib_remove_mbuf(txq);
3615 txq->ift_txd_encap_efbig++;
3624 * err can't possibly be non-zero here, so we don't neet to test it
3625 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3630 txq->ift_mbuf_defrag_failed++;
3631 txq->ift_map_failed++;
3633 DBG_COUNTER_INC(tx_frees);
3635 DBG_COUNTER_INC(encap_txd_encap_fail);
3640 iflib_tx_desc_free(iflib_txq_t txq, int n)
3642 uint32_t qsize, cidx, mask, gen;
3643 struct mbuf *m, **ifsd_m;
3646 cidx = txq->ift_cidx;
3648 qsize = txq->ift_size;
3650 ifsd_m = txq->ift_sds.ifsd_m;
3651 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3655 prefetch(ifsd_m[(cidx + 3) & mask]);
3656 prefetch(ifsd_m[(cidx + 4) & mask]);
3658 if ((m = ifsd_m[cidx]) != NULL) {
3659 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3660 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3661 bus_dmamap_sync(txq->ift_tso_buf_tag,
3662 txq->ift_sds.ifsd_tso_map[cidx],
3663 BUS_DMASYNC_POSTWRITE);
3664 bus_dmamap_unload(txq->ift_tso_buf_tag,
3665 txq->ift_sds.ifsd_tso_map[cidx]);
3667 bus_dmamap_sync(txq->ift_buf_tag,
3668 txq->ift_sds.ifsd_map[cidx],
3669 BUS_DMASYNC_POSTWRITE);
3670 bus_dmamap_unload(txq->ift_buf_tag,
3671 txq->ift_sds.ifsd_map[cidx]);
3673 /* XXX we don't support any drivers that batch packets yet */
3674 MPASS(m->m_nextpkt == NULL);
3676 ifsd_m[cidx] = NULL;
3678 txq->ift_dequeued++;
3680 DBG_COUNTER_INC(tx_frees);
3682 if (__predict_false(++cidx == qsize)) {
3687 txq->ift_cidx = cidx;
3692 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3695 if_ctx_t ctx = txq->ift_ctx;
3697 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3698 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3701 * Need a rate-limiting check so that this isn't called every time
3703 iflib_tx_credits_update(ctx, txq);
3704 reclaim = DESC_RECLAIMABLE(txq);
3706 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3708 if (iflib_verbose_debug) {
3709 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3710 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3716 iflib_tx_desc_free(txq, reclaim);
3717 txq->ift_cleaned += reclaim;
3718 txq->ift_in_use -= reclaim;
3723 static struct mbuf **
3724 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3727 struct mbuf **items;
3730 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3731 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3733 prefetch(items[(cidx + offset) & (size-1)]);
3734 if (remaining > 1) {
3735 prefetch2cachelines(&items[next]);
3736 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3737 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3738 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3740 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3744 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3747 ifmp_ring_check_drainage(txq->ift_br, budget);
3751 iflib_txq_can_drain(struct ifmp_ring *r)
3753 iflib_txq_t txq = r->cookie;
3754 if_ctx_t ctx = txq->ift_ctx;
3756 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3758 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3759 BUS_DMASYNC_POSTREAD);
3760 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3765 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3767 iflib_txq_t txq = r->cookie;
3768 if_ctx_t ctx = txq->ift_ctx;
3769 if_t ifp = ctx->ifc_ifp;
3770 struct mbuf *m, **mp;
3771 int avail, bytes_sent, skipped, count, err, i;
3772 int mcast_sent, pkt_sent, reclaimed;
3773 bool do_prefetch, rang, ring;
3775 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3776 !LINK_ACTIVE(ctx))) {
3777 DBG_COUNTER_INC(txq_drain_notready);
3780 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3781 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3782 avail = IDXDIFF(pidx, cidx, r->size);
3784 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3786 * The driver is unloading so we need to free all pending packets.
3788 DBG_COUNTER_INC(txq_drain_flushing);
3789 for (i = 0; i < avail; i++) {
3790 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3791 m_freem(r->items[(cidx + i) & (r->size-1)]);
3792 r->items[(cidx + i) & (r->size-1)] = NULL;
3797 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3798 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3800 callout_stop(&txq->ift_timer);
3801 CALLOUT_UNLOCK(txq);
3802 DBG_COUNTER_INC(txq_drain_oactive);
3807 * If we've reclaimed any packets this queue cannot be hung.
3810 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3811 skipped = mcast_sent = bytes_sent = pkt_sent = 0;
3812 count = MIN(avail, TX_BATCH_SIZE);
3814 if (iflib_verbose_debug)
3815 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3816 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3818 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3820 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) {
3821 int rem = do_prefetch ? count - i : 0;
3823 mp = _ring_peek_one(r, cidx, i, rem);
3824 MPASS(mp != NULL && *mp != NULL);
3827 * Completion interrupts will use the address of the txq
3828 * as a sentinel to enqueue _something_ in order to acquire
3829 * the lock on the mp_ring (there's no direct lock call).
3830 * We obviously whave to check for these sentinel cases
3833 if (__predict_false(*mp == (struct mbuf *)txq)) {
3837 err = iflib_encap(txq, mp);
3838 if (__predict_false(err)) {
3839 /* no room - bail out */
3843 /* we can't send this packet - skip it */
3848 DBG_COUNTER_INC(tx_sent);
3849 bytes_sent += m->m_pkthdr.len;
3850 mcast_sent += !!(m->m_flags & M_MCAST);
3852 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3854 ETHER_BPF_MTAP(ifp, m);
3855 rang = iflib_txd_db_check(txq, false);
3858 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3859 ring = rang ? false : (iflib_min_tx_latency | err);
3860 iflib_txd_db_check(txq, ring);
3861 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3862 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3864 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3866 if (iflib_verbose_debug)
3867 printf("consumed=%d\n", skipped + pkt_sent);
3869 return (skipped + pkt_sent);
3873 iflib_txq_drain_always(struct ifmp_ring *r)
3879 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3887 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3889 callout_stop(&txq->ift_timer);
3890 CALLOUT_UNLOCK(txq);
3892 avail = IDXDIFF(pidx, cidx, r->size);
3893 for (i = 0; i < avail; i++) {
3894 mp = _ring_peek_one(r, cidx, i, avail - i);
3895 if (__predict_false(*mp == (struct mbuf *)txq))
3898 DBG_COUNTER_INC(tx_frees);
3900 MPASS(ifmp_ring_is_stalled(r) == 0);
3905 iflib_ifmp_purge(iflib_txq_t txq)
3907 struct ifmp_ring *r;
3910 r->drain = iflib_txq_drain_free;
3911 r->can_drain = iflib_txq_drain_always;
3913 ifmp_ring_check_drainage(r, r->size);
3915 r->drain = iflib_txq_drain;
3916 r->can_drain = iflib_txq_can_drain;
3920 _task_fn_tx(void *context)
3922 iflib_txq_t txq = context;
3923 if_ctx_t ctx = txq->ift_ctx;
3924 if_t ifp = ctx->ifc_ifp;
3925 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3927 #ifdef IFLIB_DIAGNOSTICS
3928 txq->ift_cpu_exec_count[curcpu]++;
3930 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3933 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3934 netmap_tx_irq(ifp, txq->ift_id))
3938 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3939 iflib_altq_if_start(ifp);
3941 if (txq->ift_db_pending)
3942 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3944 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3946 * When abdicating, we always need to check drainage, not just when we don't enqueue
3949 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3953 if (ctx->ifc_flags & IFC_LEGACY)
3954 IFDI_INTR_ENABLE(ctx);
3956 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3960 _task_fn_rx(void *context)
3962 iflib_rxq_t rxq = context;
3963 if_ctx_t ctx = rxq->ifr_ctx;
3971 #ifdef IFLIB_DIAGNOSTICS
3972 rxq->ifr_cpu_exec_count[curcpu]++;
3974 DBG_COUNTER_INC(task_fn_rxs);
3975 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3978 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3979 if (nmirq != NM_IRQ_PASS) {
3980 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3984 budget = ctx->ifc_sysctl_rx_budget;
3986 budget = 16; /* XXX */
3987 more = iflib_rxeof(rxq, budget);
3991 if ((more & IFLIB_RXEOF_MORE) == 0) {
3992 if (ctx->ifc_flags & IFC_LEGACY)
3993 IFDI_INTR_ENABLE(ctx);
3995 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3996 DBG_COUNTER_INC(rx_intr_enables);
3998 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4001 if (more & IFLIB_RXEOF_MORE)
4002 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4003 else if (more & IFLIB_RXEOF_EMPTY)
4004 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4008 _task_fn_admin(void *context)
4010 if_ctx_t ctx = context;
4011 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4014 bool oactive, running, do_reset, do_watchdog, in_detach;
4017 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4018 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4019 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4020 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4021 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4022 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
4025 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4031 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4033 callout_stop(&txq->ift_timer);
4034 CALLOUT_UNLOCK(txq);
4036 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ)
4037 IFDI_ADMIN_COMPLETION_HANDLE(ctx);
4039 ctx->ifc_watchdog_events++;
4040 IFDI_WATCHDOG_RESET(ctx);
4042 IFDI_UPDATE_ADMIN_STATUS(ctx);
4043 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4044 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4045 txq->ift_timer.c_cpu);
4047 IFDI_LINK_INTR_ENABLE(ctx);
4049 iflib_if_init_locked(ctx);
4052 if (LINK_ACTIVE(ctx) == 0)
4054 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4055 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4059 _task_fn_iov(void *context)
4061 if_ctx_t ctx = context;
4063 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4064 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4068 IFDI_VFLR_HANDLE(ctx);
4073 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4076 if_int_delay_info_t info;
4079 info = (if_int_delay_info_t)arg1;
4080 ctx = info->iidi_ctx;
4081 info->iidi_req = req;
4082 info->iidi_oidp = oidp;
4084 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4089 /*********************************************************************
4093 **********************************************************************/
4096 iflib_if_init_locked(if_ctx_t ctx)
4099 iflib_init_locked(ctx);
4103 iflib_if_init(void *arg)
4108 iflib_if_init_locked(ctx);
4113 iflib_if_transmit(if_t ifp, struct mbuf *m)
4115 if_ctx_t ctx = if_getsoftc(ifp);
4119 int abdicate = ctx->ifc_sysctl_tx_abdicate;
4121 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4122 DBG_COUNTER_INC(tx_frees);
4127 MPASS(m->m_nextpkt == NULL);
4128 /* ALTQ-enabled interfaces always use queue 0. */
4130 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
4131 qidx = QIDX(ctx, m);
4133 * XXX calculate buf_ring based on flowid (divvy up bits?)
4135 txq = &ctx->ifc_txqs[qidx];
4137 #ifdef DRIVER_BACKPRESSURE
4138 if (txq->ift_closed) {
4140 next = m->m_nextpkt;
4141 m->m_nextpkt = NULL;
4143 DBG_COUNTER_INC(tx_frees);
4155 next = next->m_nextpkt;
4156 } while (next != NULL);
4158 if (count > nitems(marr))
4159 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4160 /* XXX check nextpkt */
4162 /* XXX simplify for now */
4163 DBG_COUNTER_INC(tx_frees);
4166 for (next = m, i = 0; next != NULL; i++) {
4168 next = next->m_nextpkt;
4169 mp[i]->m_nextpkt = NULL;
4172 DBG_COUNTER_INC(tx_seen);
4173 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4176 GROUPTASK_ENQUEUE(&txq->ift_task);
4179 GROUPTASK_ENQUEUE(&txq->ift_task);
4180 /* support forthcoming later */
4181 #ifdef DRIVER_BACKPRESSURE
4182 txq->ift_closed = TRUE;
4184 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4186 DBG_COUNTER_INC(tx_frees);
4194 * The overall approach to integrating iflib with ALTQ is to continue to use
4195 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4196 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4197 * is redundant/unnecessary, but doing so minimizes the amount of
4198 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4199 * redundantly queueing to an intermediate mp_ring is swamped by the
4200 * performance limitations inherent in using ALTQ.
4202 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4203 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4204 * given interface. If ALTQ is enabled for an interface, then all
4205 * transmitted packets for that interface will be submitted to the ALTQ
4206 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4207 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4208 * update stats that the iflib machinery handles, and which is sensitve to
4209 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4210 * will be installed as the start routine for use by ALTQ facilities that
4211 * need to trigger queue drains on a scheduled basis.
4215 iflib_altq_if_start(if_t ifp)
4217 struct ifaltq *ifq = &ifp->if_snd;
4221 IFQ_DEQUEUE_NOLOCK(ifq, m);
4223 iflib_if_transmit(ifp, m);
4224 IFQ_DEQUEUE_NOLOCK(ifq, m);
4230 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4234 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4235 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4237 iflib_altq_if_start(ifp);
4239 err = iflib_if_transmit(ifp, m);
4246 iflib_if_qflush(if_t ifp)
4248 if_ctx_t ctx = if_getsoftc(ifp);
4249 iflib_txq_t txq = ctx->ifc_txqs;
4253 ctx->ifc_flags |= IFC_QFLUSH;
4255 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4256 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4257 iflib_txq_check_drain(txq, 0);
4259 ctx->ifc_flags &= ~IFC_QFLUSH;
4263 * When ALTQ is enabled, this will also take care of purging the
4269 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4270 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4271 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4272 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4275 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4277 if_ctx_t ctx = if_getsoftc(ifp);
4278 struct ifreq *ifr = (struct ifreq *)data;
4279 #if defined(INET) || defined(INET6)
4280 struct ifaddr *ifa = (struct ifaddr *)data;
4282 bool avoid_reset = false;
4283 int err = 0, reinit = 0, bits;
4288 if (ifa->ifa_addr->sa_family == AF_INET)
4292 if (ifa->ifa_addr->sa_family == AF_INET6)
4296 ** Calling init results in link renegotiation,
4297 ** so we avoid doing it when possible.
4300 if_setflagbits(ifp, IFF_UP,0);
4301 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4304 if (!(if_getflags(ifp) & IFF_NOARP))
4305 arp_ifinit(ifp, ifa);
4308 err = ether_ioctl(ifp, command, data);
4312 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4316 bits = if_getdrvflags(ifp);
4317 /* stop the driver and free any clusters before proceeding */
4320 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4322 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4323 ctx->ifc_flags |= IFC_MULTISEG;
4325 ctx->ifc_flags &= ~IFC_MULTISEG;
4327 err = if_setmtu(ifp, ifr->ifr_mtu);
4329 iflib_init_locked(ctx);
4331 if_setdrvflags(ifp, bits);
4337 if (if_getflags(ifp) & IFF_UP) {
4338 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4339 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4340 (IFF_PROMISC | IFF_ALLMULTI)) {
4342 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4347 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4350 ctx->ifc_if_flags = if_getflags(ifp);
4355 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4357 IFDI_INTR_DISABLE(ctx);
4358 IFDI_MULTI_SET(ctx);
4359 IFDI_INTR_ENABLE(ctx);
4365 IFDI_MEDIA_SET(ctx);
4370 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4374 struct ifi2creq i2c;
4376 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4379 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4383 if (i2c.len > sizeof(i2c.data)) {
4388 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4389 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4395 int mask, setmask, oldmask;
4397 oldmask = if_getcapenable(ifp);
4398 mask = ifr->ifr_reqcap ^ oldmask;
4399 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4402 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4404 setmask |= (mask & IFCAP_FLAGS);
4405 setmask |= (mask & IFCAP_WOL);
4408 * If any RX csum has changed, change all the ones that
4409 * are supported by the driver.
4411 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4412 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4413 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4417 * want to ensure that traffic has stopped before we change any of the flags
4421 bits = if_getdrvflags(ifp);
4422 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4425 if_togglecapenable(ifp, setmask);
4427 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4428 iflib_init_locked(ctx);
4430 if_setdrvflags(ifp, bits);
4437 case SIOCGPRIVATE_0:
4441 err = IFDI_PRIV_IOCTL(ctx, command, data);
4445 err = ether_ioctl(ifp, command, data);
4454 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4456 if_ctx_t ctx = if_getsoftc(ifp);
4458 return (IFDI_GET_COUNTER(ctx, cnt));
4461 /*********************************************************************
4463 * OTHER FUNCTIONS EXPORTED TO THE STACK
4465 **********************************************************************/
4468 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4470 if_ctx_t ctx = if_getsoftc(ifp);
4472 if ((void *)ctx != arg)
4475 if ((vtag == 0) || (vtag > 4095))
4478 if (iflib_in_detach(ctx))
4482 /* Driver may need all untagged packets to be flushed */
4483 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4485 IFDI_VLAN_REGISTER(ctx, vtag);
4486 /* Re-init to load the changes, if required */
4487 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4488 iflib_init_locked(ctx);
4493 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4495 if_ctx_t ctx = if_getsoftc(ifp);
4497 if ((void *)ctx != arg)
4500 if ((vtag == 0) || (vtag > 4095))
4504 /* Driver may need all tagged packets to be flushed */
4505 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4507 IFDI_VLAN_UNREGISTER(ctx, vtag);
4508 /* Re-init to load the changes, if required */
4509 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4510 iflib_init_locked(ctx);
4515 iflib_led_func(void *arg, int onoff)
4520 IFDI_LED_FUNC(ctx, onoff);
4524 /*********************************************************************
4526 * BUS FUNCTION DEFINITIONS
4528 **********************************************************************/
4531 iflib_device_probe(device_t dev)
4533 const pci_vendor_info_t *ent;
4534 if_shared_ctx_t sctx;
4535 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4536 uint16_t pci_vendor_id;
4538 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4541 pci_vendor_id = pci_get_vendor(dev);
4542 pci_device_id = pci_get_device(dev);
4543 pci_subvendor_id = pci_get_subvendor(dev);
4544 pci_subdevice_id = pci_get_subdevice(dev);
4545 pci_rev_id = pci_get_revid(dev);
4546 if (sctx->isc_parse_devinfo != NULL)
4547 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4549 ent = sctx->isc_vendor_info;
4550 while (ent->pvi_vendor_id != 0) {
4551 if (pci_vendor_id != ent->pvi_vendor_id) {
4555 if ((pci_device_id == ent->pvi_device_id) &&
4556 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4557 (ent->pvi_subvendor_id == 0)) &&
4558 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4559 (ent->pvi_subdevice_id == 0)) &&
4560 ((pci_rev_id == ent->pvi_rev_id) ||
4561 (ent->pvi_rev_id == 0))) {
4562 device_set_desc_copy(dev, ent->pvi_name);
4563 /* this needs to be changed to zero if the bus probing code
4564 * ever stops re-probing on best match because the sctx
4565 * may have its values over written by register calls
4566 * in subsequent probes
4568 return (BUS_PROBE_DEFAULT);
4576 iflib_device_probe_vendor(device_t dev)
4580 probe = iflib_device_probe(dev);
4581 if (probe == BUS_PROBE_DEFAULT)
4582 return (BUS_PROBE_VENDOR);
4588 iflib_reset_qvalues(if_ctx_t ctx)
4590 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4591 if_shared_ctx_t sctx = ctx->ifc_sctx;
4592 device_t dev = ctx->ifc_dev;
4595 if (ctx->ifc_sysctl_ntxqs != 0)
4596 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4597 if (ctx->ifc_sysctl_nrxqs != 0)
4598 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4600 for (i = 0; i < sctx->isc_ntxqs; i++) {
4601 if (ctx->ifc_sysctl_ntxds[i] != 0)
4602 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4604 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4607 for (i = 0; i < sctx->isc_nrxqs; i++) {
4608 if (ctx->ifc_sysctl_nrxds[i] != 0)
4609 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4611 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4614 for (i = 0; i < sctx->isc_nrxqs; i++) {
4615 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4616 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4617 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4618 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4620 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4621 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4622 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4623 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4625 if (!powerof2(scctx->isc_nrxd[i])) {
4626 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4627 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4628 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4632 for (i = 0; i < sctx->isc_ntxqs; i++) {
4633 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4634 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4635 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4636 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4638 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4639 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4640 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4641 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4643 if (!powerof2(scctx->isc_ntxd[i])) {
4644 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4645 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4646 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4652 iflib_add_pfil(if_ctx_t ctx)
4654 struct pfil_head *pfil;
4655 struct pfil_head_args pa;
4659 pa.pa_version = PFIL_VERSION;
4660 pa.pa_flags = PFIL_IN;
4661 pa.pa_type = PFIL_TYPE_ETHERNET;
4662 pa.pa_headname = ctx->ifc_ifp->if_xname;
4663 pfil = pfil_head_register(&pa);
4665 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4671 iflib_rem_pfil(if_ctx_t ctx)
4673 struct pfil_head *pfil;
4677 rxq = ctx->ifc_rxqs;
4679 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4682 pfil_head_unregister(pfil);
4686 get_ctx_core_offset(if_ctx_t ctx)
4688 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4689 struct cpu_offset *op;
4691 uint16_t ret = ctx->ifc_sysctl_core_offset;
4693 if (ret != CORE_OFFSET_UNSPECIFIED)
4696 if (ctx->ifc_sysctl_separate_txrx)
4697 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4699 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4701 mtx_lock(&cpu_offset_mtx);
4702 SLIST_FOREACH(op, &cpu_offsets, entries) {
4703 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4706 MPASS(op->refcount < UINT_MAX);
4711 if (ret == CORE_OFFSET_UNSPECIFIED) {
4713 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4716 device_printf(ctx->ifc_dev,
4717 "allocation for cpu offset failed.\n");
4721 CPU_COPY(&ctx->ifc_cpus, &op->set);
4722 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4725 mtx_unlock(&cpu_offset_mtx);
4731 unref_ctx_core_offset(if_ctx_t ctx)
4733 struct cpu_offset *op, *top;
4735 mtx_lock(&cpu_offset_mtx);
4736 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4737 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4738 MPASS(op->refcount > 0);
4740 if (op->refcount == 0) {
4741 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4747 mtx_unlock(&cpu_offset_mtx);
4751 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4755 if_softc_ctx_t scctx;
4756 kobjop_desc_t kobj_desc;
4757 kobj_method_t *kobj_method;
4759 int num_txd, num_rxd;
4761 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4764 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4765 device_set_softc(dev, ctx);
4766 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4769 ctx->ifc_sctx = sctx;
4771 ctx->ifc_softc = sc;
4773 if ((err = iflib_register(ctx)) != 0) {
4774 device_printf(dev, "iflib_register failed %d\n", err);
4777 iflib_add_device_sysctl_pre(ctx);
4779 scctx = &ctx->ifc_softc_ctx;
4782 iflib_reset_qvalues(ctx);
4784 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4785 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4788 _iflib_pre_assert(scctx);
4789 ctx->ifc_txrx = *scctx->isc_txrx;
4791 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR));
4793 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4794 ctx->ifc_mediap = scctx->isc_media;
4797 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4798 MPASS(scctx->isc_tx_csum_flags);
4801 if_setcapabilities(ifp,
4802 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
4803 if_setcapenable(ifp,
4804 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
4806 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4807 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4808 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4809 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4811 num_txd = iflib_num_tx_descs(ctx);
4812 num_rxd = iflib_num_rx_descs(ctx);
4814 /* XXX change for per-queue sizes */
4815 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4818 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4819 scctx->isc_tx_nsegments = max(1, num_txd /
4820 MAX_SINGLE_PACKET_FRACTION);
4821 if (scctx->isc_tx_tso_segments_max > num_txd /
4822 MAX_SINGLE_PACKET_FRACTION)
4823 scctx->isc_tx_tso_segments_max = max(1,
4824 num_txd / MAX_SINGLE_PACKET_FRACTION);
4826 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4827 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4829 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4832 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4835 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4836 * into account. In the worst case, each of these calls will
4837 * add another mbuf and, thus, the requirement for another DMA
4838 * segment. So for best performance, it doesn't make sense to
4839 * advertize a maximum of TSO segments that typically will
4840 * require defragmentation in iflib_encap().
4842 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4843 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4845 if (scctx->isc_rss_table_size == 0)
4846 scctx->isc_rss_table_size = 64;
4847 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4849 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4850 /* XXX format name */
4851 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4852 NULL, NULL, "admin");
4854 /* Set up cpu set. If it fails, use the set of all CPUs. */
4855 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4856 device_printf(dev, "Unable to fetch CPU list\n");
4857 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4859 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4862 ** Now set up MSI or MSI-X, should return us the number of supported
4863 ** vectors (will be 1 for a legacy interrupt and MSI).
4865 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4866 msix = scctx->isc_vectors;
4867 } else if (scctx->isc_msix_bar != 0)
4869 * The simple fact that isc_msix_bar is not 0 does not mean we
4870 * we have a good value there that is known to work.
4872 msix = iflib_msix_init(ctx);
4874 scctx->isc_vectors = 1;
4875 scctx->isc_ntxqsets = 1;
4876 scctx->isc_nrxqsets = 1;
4877 scctx->isc_intr = IFLIB_INTR_LEGACY;
4880 /* Get memory for the station queues */
4881 if ((err = iflib_queues_alloc(ctx))) {
4882 device_printf(dev, "Unable to allocate queue memory\n");
4883 goto fail_intr_free;
4886 if ((err = iflib_qset_structures_setup(ctx)))
4890 * Now that we know how many queues there are, get the core offset.
4892 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4896 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4897 * aren't the default NULL implementation.
4899 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4900 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4902 if (kobj_method == &kobj_desc->deflt) {
4904 "MSI-X requires ifdi_rx_queue_intr_enable method");
4908 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4909 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4911 if (kobj_method == &kobj_desc->deflt) {
4913 "MSI-X requires ifdi_tx_queue_intr_enable method");
4919 * Assign the MSI-X vectors.
4920 * Note that the default NULL ifdi_msix_intr_assign method will
4923 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4925 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4929 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4931 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4935 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4936 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4941 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4946 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4948 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4949 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4954 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4955 * This must appear after the call to ether_ifattach() because
4956 * ether_ifattach() sets if_hdrlen to the default value.
4958 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4959 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4961 if ((err = iflib_netmap_attach(ctx))) {
4962 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4967 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4969 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4970 iflib_add_device_sysctl_post(ctx);
4971 iflib_add_pfil(ctx);
4972 ctx->ifc_flags |= IFC_INIT_DONE;
4978 ether_ifdetach(ctx->ifc_ifp);
4980 iflib_tqg_detach(ctx);
4981 iflib_tx_structures_free(ctx);
4982 iflib_rx_structures_free(ctx);
4984 IFDI_QUEUES_FREE(ctx);
4986 iflib_free_intr_mem(ctx);
4989 iflib_deregister(ctx);
4991 device_set_softc(ctx->ifc_dev, NULL);
4992 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4993 free(ctx->ifc_softc, M_IFLIB);
4999 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
5000 struct iflib_cloneattach_ctx *clctx)
5002 int num_txd, num_rxd;
5006 if_softc_ctx_t scctx;
5010 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
5011 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5012 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5013 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
5014 ctx->ifc_flags |= IFC_PSEUDO;
5016 ctx->ifc_sctx = sctx;
5017 ctx->ifc_softc = sc;
5020 if ((err = iflib_register(ctx)) != 0) {
5021 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
5024 iflib_add_device_sysctl_pre(ctx);
5026 scctx = &ctx->ifc_softc_ctx;
5029 iflib_reset_qvalues(ctx);
5031 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5032 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5035 if (sctx->isc_flags & IFLIB_GEN_MAC)
5036 ether_gen_addr(ifp, &ctx->ifc_mac);
5037 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
5038 clctx->cc_params)) != 0) {
5039 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
5043 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5044 MPASS(scctx->isc_tx_csum_flags);
5047 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5048 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5050 ifp->if_flags |= IFF_NOGROUP;
5051 if (sctx->isc_flags & IFLIB_PSEUDO) {
5052 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5053 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5054 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
5055 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5057 if_attach(ctx->ifc_ifp);
5058 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
5061 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5062 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5068 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5069 * This must appear after the call to ether_ifattach() because
5070 * ether_ifattach() sets if_hdrlen to the default value.
5072 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5073 if_setifheaderlen(ifp,
5074 sizeof(struct ether_vlan_header));
5076 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5077 iflib_add_device_sysctl_post(ctx);
5078 ctx->ifc_flags |= IFC_INIT_DONE;
5082 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
5083 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5084 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5086 _iflib_pre_assert(scctx);
5087 ctx->ifc_txrx = *scctx->isc_txrx;
5089 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5090 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5091 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5092 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5094 num_txd = iflib_num_tx_descs(ctx);
5095 num_rxd = iflib_num_rx_descs(ctx);
5097 /* XXX change for per-queue sizes */
5098 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5101 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5102 scctx->isc_tx_nsegments = max(1, num_txd /
5103 MAX_SINGLE_PACKET_FRACTION);
5104 if (scctx->isc_tx_tso_segments_max > num_txd /
5105 MAX_SINGLE_PACKET_FRACTION)
5106 scctx->isc_tx_tso_segments_max = max(1,
5107 num_txd / MAX_SINGLE_PACKET_FRACTION);
5109 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5110 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5112 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5115 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5118 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5119 * into account. In the worst case, each of these calls will
5120 * add another mbuf and, thus, the requirement for another DMA
5121 * segment. So for best performance, it doesn't make sense to
5122 * advertize a maximum of TSO segments that typically will
5123 * require defragmentation in iflib_encap().
5125 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5126 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5128 if (scctx->isc_rss_table_size == 0)
5129 scctx->isc_rss_table_size = 64;
5130 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5132 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5133 /* XXX format name */
5134 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5135 NULL, NULL, "admin");
5137 /* XXX --- can support > 1 -- but keep it simple for now */
5138 scctx->isc_intr = IFLIB_INTR_LEGACY;
5140 /* Get memory for the station queues */
5141 if ((err = iflib_queues_alloc(ctx))) {
5142 device_printf(dev, "Unable to allocate queue memory\n");
5143 goto fail_iflib_detach;
5146 if ((err = iflib_qset_structures_setup(ctx))) {
5147 device_printf(dev, "qset structure setup failed %d\n", err);
5152 * XXX What if anything do we want to do about interrupts?
5154 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5155 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5156 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5161 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5162 * This must appear after the call to ether_ifattach() because
5163 * ether_ifattach() sets if_hdrlen to the default value.
5165 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5166 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5168 /* XXX handle more than one queue */
5169 for (i = 0; i < scctx->isc_nrxqsets; i++)
5170 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5174 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5175 iflib_add_device_sysctl_post(ctx);
5176 ctx->ifc_flags |= IFC_INIT_DONE;
5181 ether_ifdetach(ctx->ifc_ifp);
5183 iflib_tqg_detach(ctx);
5184 iflib_tx_structures_free(ctx);
5185 iflib_rx_structures_free(ctx);
5188 IFDI_QUEUES_FREE(ctx);
5191 iflib_deregister(ctx);
5193 free(ctx->ifc_softc, M_IFLIB);
5199 iflib_pseudo_deregister(if_ctx_t ctx)
5201 if_t ifp = ctx->ifc_ifp;
5202 if_shared_ctx_t sctx = ctx->ifc_sctx;
5204 /* Unregister VLAN event handlers early */
5205 iflib_unregister_vlan_handlers(ctx);
5207 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5208 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5212 ether_ifdetach(ifp);
5215 iflib_tqg_detach(ctx);
5216 iflib_tx_structures_free(ctx);
5217 iflib_rx_structures_free(ctx);
5219 IFDI_QUEUES_FREE(ctx);
5221 iflib_deregister(ctx);
5223 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5224 free(ctx->ifc_softc, M_IFLIB);
5230 iflib_device_attach(device_t dev)
5233 if_shared_ctx_t sctx;
5235 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5238 pci_enable_busmaster(dev);
5240 return (iflib_device_register(dev, NULL, sctx, &ctx));
5244 iflib_device_deregister(if_ctx_t ctx)
5246 if_t ifp = ctx->ifc_ifp;
5247 device_t dev = ctx->ifc_dev;
5249 /* Make sure VLANS are not using driver */
5250 if (if_vlantrunkinuse(ifp)) {
5251 device_printf(dev, "Vlan in use, detach first\n");
5255 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5256 device_printf(dev, "SR-IOV in use; detach first.\n");
5262 ctx->ifc_flags |= IFC_IN_DETACH;
5265 /* Unregister VLAN handlers before calling iflib_stop() */
5266 iflib_unregister_vlan_handlers(ctx);
5268 iflib_netmap_detach(ifp);
5269 ether_ifdetach(ifp);
5275 iflib_rem_pfil(ctx);
5276 if (ctx->ifc_led_dev != NULL)
5277 led_destroy(ctx->ifc_led_dev);
5279 iflib_tqg_detach(ctx);
5280 iflib_tx_structures_free(ctx);
5281 iflib_rx_structures_free(ctx);
5285 IFDI_QUEUES_FREE(ctx);
5288 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5289 iflib_free_intr_mem(ctx);
5291 bus_generic_detach(dev);
5293 iflib_deregister(ctx);
5295 device_set_softc(ctx->ifc_dev, NULL);
5296 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5297 free(ctx->ifc_softc, M_IFLIB);
5298 unref_ctx_core_offset(ctx);
5304 iflib_tqg_detach(if_ctx_t ctx)
5309 struct taskqgroup *tqg;
5311 /* XXX drain any dependent tasks */
5312 tqg = qgroup_if_io_tqg;
5313 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5314 callout_drain(&txq->ift_timer);
5316 callout_drain(&txq->ift_netmap_timer);
5317 #endif /* DEV_NETMAP */
5318 if (txq->ift_task.gt_uniq != NULL)
5319 taskqgroup_detach(tqg, &txq->ift_task);
5321 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5322 if (rxq->ifr_task.gt_uniq != NULL)
5323 taskqgroup_detach(tqg, &rxq->ifr_task);
5325 tqg = qgroup_if_config_tqg;
5326 if (ctx->ifc_admin_task.gt_uniq != NULL)
5327 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5328 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5329 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5333 iflib_free_intr_mem(if_ctx_t ctx)
5336 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5337 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5339 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5340 pci_release_msi(ctx->ifc_dev);
5342 if (ctx->ifc_msix_mem != NULL) {
5343 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5344 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5345 ctx->ifc_msix_mem = NULL;
5350 iflib_device_detach(device_t dev)
5352 if_ctx_t ctx = device_get_softc(dev);
5354 return (iflib_device_deregister(ctx));
5358 iflib_device_suspend(device_t dev)
5360 if_ctx_t ctx = device_get_softc(dev);
5366 return bus_generic_suspend(dev);
5369 iflib_device_shutdown(device_t dev)
5371 if_ctx_t ctx = device_get_softc(dev);
5377 return bus_generic_suspend(dev);
5381 iflib_device_resume(device_t dev)
5383 if_ctx_t ctx = device_get_softc(dev);
5384 iflib_txq_t txq = ctx->ifc_txqs;
5388 iflib_if_init_locked(ctx);
5390 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5391 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5393 return (bus_generic_resume(dev));
5397 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5400 if_ctx_t ctx = device_get_softc(dev);
5403 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5410 iflib_device_iov_uninit(device_t dev)
5412 if_ctx_t ctx = device_get_softc(dev);
5415 IFDI_IOV_UNINIT(ctx);
5420 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5423 if_ctx_t ctx = device_get_softc(dev);
5426 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5432 /*********************************************************************
5434 * MODULE FUNCTION DEFINITIONS
5436 **********************************************************************/
5439 * - Start a fast taskqueue thread for each core
5440 * - Start a taskqueue for control operations
5443 iflib_module_init(void)
5445 iflib_timer_default = hz / 2;
5450 iflib_module_event_handler(module_t mod, int what, void *arg)
5456 if ((err = iflib_module_init()) != 0)
5462 return (EOPNOTSUPP);
5468 /*********************************************************************
5470 * PUBLIC FUNCTION DEFINITIONS
5471 * ordered as in iflib.h
5473 **********************************************************************/
5476 _iflib_assert(if_shared_ctx_t sctx)
5480 MPASS(sctx->isc_tx_maxsize);
5481 MPASS(sctx->isc_tx_maxsegsize);
5483 MPASS(sctx->isc_rx_maxsize);
5484 MPASS(sctx->isc_rx_nsegments);
5485 MPASS(sctx->isc_rx_maxsegsize);
5487 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5488 for (i = 0; i < sctx->isc_nrxqs; i++) {
5489 MPASS(sctx->isc_nrxd_min[i]);
5490 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5491 MPASS(sctx->isc_nrxd_max[i]);
5492 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5493 MPASS(sctx->isc_nrxd_default[i]);
5494 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5497 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5498 for (i = 0; i < sctx->isc_ntxqs; i++) {
5499 MPASS(sctx->isc_ntxd_min[i]);
5500 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5501 MPASS(sctx->isc_ntxd_max[i]);
5502 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5503 MPASS(sctx->isc_ntxd_default[i]);
5504 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5509 _iflib_pre_assert(if_softc_ctx_t scctx)
5512 MPASS(scctx->isc_txrx->ift_txd_encap);
5513 MPASS(scctx->isc_txrx->ift_txd_flush);
5514 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5515 MPASS(scctx->isc_txrx->ift_rxd_available);
5516 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5517 MPASS(scctx->isc_txrx->ift_rxd_refill);
5518 MPASS(scctx->isc_txrx->ift_rxd_flush);
5522 iflib_register(if_ctx_t ctx)
5524 if_shared_ctx_t sctx = ctx->ifc_sctx;
5525 driver_t *driver = sctx->isc_driver;
5526 device_t dev = ctx->ifc_dev;
5531 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5532 _iflib_assert(sctx);
5535 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5536 if (sctx->isc_flags & IFLIB_PSEUDO) {
5537 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5543 ifp = ctx->ifc_ifp = if_alloc(type);
5545 device_printf(dev, "can not allocate ifnet structure\n");
5550 * Initialize our context's device specific methods
5552 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5553 kobj_class_compile((kobj_class_t) driver);
5555 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5556 if_setsoftc(ifp, ctx);
5557 if_setdev(ifp, dev);
5558 if_setinitfn(ifp, iflib_if_init);
5559 if_setioctlfn(ifp, iflib_if_ioctl);
5561 if_setstartfn(ifp, iflib_altq_if_start);
5562 if_settransmitfn(ifp, iflib_altq_if_transmit);
5563 if_setsendqready(ifp);
5565 if_settransmitfn(ifp, iflib_if_transmit);
5567 if_setqflushfn(ifp, iflib_if_qflush);
5568 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5570 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5571 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5572 iflags |= IFF_POINTOPOINT;
5574 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5575 if_setflags(ifp, iflags);
5576 ctx->ifc_vlan_attach_event =
5577 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5578 EVENTHANDLER_PRI_FIRST);
5579 ctx->ifc_vlan_detach_event =
5580 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5581 EVENTHANDLER_PRI_FIRST);
5583 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5584 ctx->ifc_mediap = &ctx->ifc_media;
5585 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5586 iflib_media_change, iflib_media_status);
5592 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5594 /* Unregister VLAN events */
5595 if (ctx->ifc_vlan_attach_event != NULL) {
5596 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5597 ctx->ifc_vlan_attach_event = NULL;
5599 if (ctx->ifc_vlan_detach_event != NULL) {
5600 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5601 ctx->ifc_vlan_detach_event = NULL;
5607 iflib_deregister(if_ctx_t ctx)
5609 if_t ifp = ctx->ifc_ifp;
5611 /* Remove all media */
5612 ifmedia_removeall(&ctx->ifc_media);
5614 /* Ensure that VLAN event handlers are unregistered */
5615 iflib_unregister_vlan_handlers(ctx);
5617 /* Release kobject reference */
5618 kobj_delete((kobj_t) ctx, NULL);
5620 /* Free the ifnet structure */
5623 STATE_LOCK_DESTROY(ctx);
5625 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5626 CTX_LOCK_DESTROY(ctx);
5630 iflib_queues_alloc(if_ctx_t ctx)
5632 if_shared_ctx_t sctx = ctx->ifc_sctx;
5633 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5634 device_t dev = ctx->ifc_dev;
5635 int nrxqsets = scctx->isc_nrxqsets;
5636 int ntxqsets = scctx->isc_ntxqsets;
5639 iflib_fl_t fl = NULL;
5640 int i, j, cpu, err, txconf, rxconf;
5641 iflib_dma_info_t ifdip;
5642 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5643 uint32_t *txqsizes = scctx->isc_txqsizes;
5644 uint8_t nrxqs = sctx->isc_nrxqs;
5645 uint8_t ntxqs = sctx->isc_ntxqs;
5646 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5647 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
5651 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5652 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5653 KASSERT(nrxqs >= fl_offset + nfree_lists,
5654 ("there must be at least a rxq for each free list"));
5656 /* Allocate the TX ring struct memory */
5657 if (!(ctx->ifc_txqs =
5658 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5659 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5660 device_printf(dev, "Unable to allocate TX ring memory\n");
5665 /* Now allocate the RX */
5666 if (!(ctx->ifc_rxqs =
5667 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5668 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5669 device_printf(dev, "Unable to allocate RX ring memory\n");
5674 txq = ctx->ifc_txqs;
5675 rxq = ctx->ifc_rxqs;
5678 * XXX handle allocation failure
5680 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5681 /* Set up some basics */
5683 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5684 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5686 "Unable to allocate TX DMA info memory\n");
5690 txq->ift_ifdi = ifdip;
5691 for (j = 0; j < ntxqs; j++, ifdip++) {
5692 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5694 "Unable to allocate TX descriptors\n");
5698 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5699 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5703 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5704 txq->ift_br_offset = 1;
5706 txq->ift_br_offset = 0;
5709 if (iflib_txsd_alloc(txq)) {
5710 device_printf(dev, "Critical Failure setting up TX buffers\n");
5715 /* Initialize the TX lock */
5716 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5717 device_get_nameunit(dev), txq->ift_id);
5718 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5719 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5720 txq->ift_timer.c_cpu = cpu;
5722 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
5723 txq->ift_netmap_timer.c_cpu = cpu;
5724 #endif /* DEV_NETMAP */
5726 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5727 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5729 /* XXX free any allocated rings */
5730 device_printf(dev, "Unable to allocate buf_ring\n");
5735 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5736 /* Set up some basics */
5737 callout_init(&rxq->ifr_watchdog, 1);
5739 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5740 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5742 "Unable to allocate RX DMA info memory\n");
5747 rxq->ifr_ifdi = ifdip;
5748 /* XXX this needs to be changed if #rx queues != #tx queues */
5749 rxq->ifr_ntxqirq = 1;
5750 rxq->ifr_txqid[0] = i;
5751 for (j = 0; j < nrxqs; j++, ifdip++) {
5752 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5754 "Unable to allocate RX descriptors\n");
5758 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5762 rxq->ifr_fl_offset = fl_offset;
5763 rxq->ifr_nfl = nfree_lists;
5765 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5766 device_printf(dev, "Unable to allocate free list memory\n");
5771 for (j = 0; j < nfree_lists; j++) {
5772 fl[j].ifl_rxq = rxq;
5774 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5775 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5777 /* Allocate receive buffers for the ring */
5778 if (iflib_rxsd_alloc(rxq)) {
5780 "Critical Failure setting up receive buffers\n");
5785 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5786 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5791 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5792 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5793 for (i = 0; i < ntxqsets; i++) {
5794 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5796 for (j = 0; j < ntxqs; j++, di++) {
5797 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5798 paddrs[i*ntxqs + j] = di->idi_paddr;
5801 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5802 device_printf(ctx->ifc_dev,
5803 "Unable to allocate device TX queue\n");
5804 iflib_tx_structures_free(ctx);
5805 free(vaddrs, M_IFLIB);
5806 free(paddrs, M_IFLIB);
5809 free(vaddrs, M_IFLIB);
5810 free(paddrs, M_IFLIB);
5813 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5814 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5815 for (i = 0; i < nrxqsets; i++) {
5816 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5818 for (j = 0; j < nrxqs; j++, di++) {
5819 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5820 paddrs[i*nrxqs + j] = di->idi_paddr;
5823 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5824 device_printf(ctx->ifc_dev,
5825 "Unable to allocate device RX queue\n");
5826 iflib_tx_structures_free(ctx);
5827 free(vaddrs, M_IFLIB);
5828 free(paddrs, M_IFLIB);
5831 free(vaddrs, M_IFLIB);
5832 free(paddrs, M_IFLIB);
5836 /* XXX handle allocation failure changes */
5840 if (ctx->ifc_rxqs != NULL)
5841 free(ctx->ifc_rxqs, M_IFLIB);
5842 ctx->ifc_rxqs = NULL;
5843 if (ctx->ifc_txqs != NULL)
5844 free(ctx->ifc_txqs, M_IFLIB);
5845 ctx->ifc_txqs = NULL;
5851 iflib_tx_structures_setup(if_ctx_t ctx)
5853 iflib_txq_t txq = ctx->ifc_txqs;
5856 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5857 iflib_txq_setup(txq);
5863 iflib_tx_structures_free(if_ctx_t ctx)
5865 iflib_txq_t txq = ctx->ifc_txqs;
5866 if_shared_ctx_t sctx = ctx->ifc_sctx;
5869 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5870 for (j = 0; j < sctx->isc_ntxqs; j++)
5871 iflib_dma_free(&txq->ift_ifdi[j]);
5872 iflib_txq_destroy(txq);
5874 free(ctx->ifc_txqs, M_IFLIB);
5875 ctx->ifc_txqs = NULL;
5878 /*********************************************************************
5880 * Initialize all receive rings.
5882 **********************************************************************/
5884 iflib_rx_structures_setup(if_ctx_t ctx)
5886 iflib_rxq_t rxq = ctx->ifc_rxqs;
5888 #if defined(INET6) || defined(INET)
5892 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5893 #if defined(INET6) || defined(INET)
5894 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5895 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5896 TCP_LRO_ENTRIES, min(1024,
5897 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5899 device_printf(ctx->ifc_dev,
5900 "LRO Initialization failed!\n");
5905 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5908 #if defined(INET6) || defined(INET)
5911 * Free LRO resources allocated so far, we will only handle
5912 * the rings that completed, the failing case will have
5913 * cleaned up for itself. 'q' failed, so its the terminus.
5915 rxq = ctx->ifc_rxqs;
5916 for (i = 0; i < q; ++i, rxq++) {
5917 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5918 tcp_lro_free(&rxq->ifr_lc);
5924 /*********************************************************************
5926 * Free all receive rings.
5928 **********************************************************************/
5930 iflib_rx_structures_free(if_ctx_t ctx)
5932 iflib_rxq_t rxq = ctx->ifc_rxqs;
5933 if_shared_ctx_t sctx = ctx->ifc_sctx;
5936 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5937 for (j = 0; j < sctx->isc_nrxqs; j++)
5938 iflib_dma_free(&rxq->ifr_ifdi[j]);
5939 iflib_rx_sds_free(rxq);
5940 #if defined(INET6) || defined(INET)
5941 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5942 tcp_lro_free(&rxq->ifr_lc);
5945 free(ctx->ifc_rxqs, M_IFLIB);
5946 ctx->ifc_rxqs = NULL;
5950 iflib_qset_structures_setup(if_ctx_t ctx)
5955 * It is expected that the caller takes care of freeing queues if this
5958 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5959 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5963 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5964 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5970 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5971 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5974 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5979 find_nth(if_ctx_t ctx, int qid)
5982 int i, cpuid, eqid, count;
5984 CPU_COPY(&ctx->ifc_cpus, &cpus);
5985 count = CPU_COUNT(&cpus);
5987 /* clear up to the qid'th bit */
5988 for (i = 0; i < eqid; i++) {
5989 cpuid = CPU_FFS(&cpus);
5991 CPU_CLR(cpuid-1, &cpus);
5993 cpuid = CPU_FFS(&cpus);
5999 extern struct cpu_group *cpu_top; /* CPU topology */
6002 find_child_with_core(int cpu, struct cpu_group *grp)
6006 if (grp->cg_children == 0)
6009 MPASS(grp->cg_child);
6010 for (i = 0; i < grp->cg_children; i++) {
6011 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
6019 * Find the nth "close" core to the specified core
6020 * "close" is defined as the deepest level that shares
6021 * at least an L2 cache. With threads, this will be
6022 * threads on the same core. If the shared cache is L3
6023 * or higher, simply returns the same core.
6026 find_close_core(int cpu, int core_offset)
6028 struct cpu_group *grp;
6037 while ((i = find_child_with_core(cpu, grp)) != -1) {
6038 /* If the child only has one cpu, don't descend */
6039 if (grp->cg_child[i].cg_count <= 1)
6041 grp = &grp->cg_child[i];
6044 /* If they don't share at least an L2 cache, use the same CPU */
6045 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
6049 CPU_COPY(&grp->cg_mask, &cs);
6051 /* Add the selected CPU offset to core offset. */
6052 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
6053 if (fcpu - 1 == cpu)
6055 CPU_CLR(fcpu - 1, &cs);
6061 CPU_COPY(&grp->cg_mask, &cs);
6062 for (i = core_offset % grp->cg_count; i > 0; i--) {
6063 MPASS(CPU_FFS(&cs));
6064 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
6066 MPASS(CPU_FFS(&cs));
6067 return CPU_FFS(&cs) - 1;
6071 find_close_core(int cpu, int core_offset __unused)
6078 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
6082 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
6083 /* XXX handle multiple RX threads per core and more than two core per L2 group */
6084 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
6086 case IFLIB_INTR_RXTX:
6087 /* RX queues get the specified core */
6088 return qid / CPU_COUNT(&ctx->ifc_cpus);
6094 #define get_core_offset(ctx, type, qid) CPU_FIRST()
6095 #define find_close_core(cpuid, tid) CPU_FIRST()
6096 #define find_nth(ctx, gid) CPU_FIRST()
6099 /* Just to avoid copy/paste */
6101 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6102 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6106 int co, cpuid, err, tid;
6109 co = ctx->ifc_sysctl_core_offset;
6110 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
6111 co += ctx->ifc_softc_ctx.isc_nrxqsets;
6112 cpuid = find_nth(ctx, qid + co);
6113 tid = get_core_offset(ctx, type, qid);
6115 device_printf(dev, "get_core_offset failed\n");
6116 return (EOPNOTSUPP);
6118 cpuid = find_close_core(cpuid, tid);
6119 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
6122 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6126 if (cpuid > ctx->ifc_cpuid_highest)
6127 ctx->ifc_cpuid_highest = cpuid;
6133 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6134 iflib_intr_type_t type, driver_filter_t *filter,
6135 void *filter_arg, int qid, const char *name)
6138 struct grouptask *gtask;
6139 struct taskqgroup *tqg;
6140 iflib_filter_info_t info;
6143 driver_filter_t *intr_fast;
6146 info = &ctx->ifc_filter_info;
6150 /* XXX merge tx/rx for netmap? */
6152 q = &ctx->ifc_txqs[qid];
6153 info = &ctx->ifc_txqs[qid].ift_filter_info;
6154 gtask = &ctx->ifc_txqs[qid].ift_task;
6155 tqg = qgroup_if_io_tqg;
6157 intr_fast = iflib_fast_intr;
6158 GROUPTASK_INIT(gtask, 0, fn, q);
6159 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6162 q = &ctx->ifc_rxqs[qid];
6163 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6164 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6165 tqg = qgroup_if_io_tqg;
6167 intr_fast = iflib_fast_intr;
6168 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6170 case IFLIB_INTR_RXTX:
6171 q = &ctx->ifc_rxqs[qid];
6172 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6173 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6174 tqg = qgroup_if_io_tqg;
6176 intr_fast = iflib_fast_intr_rxtx;
6177 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6179 case IFLIB_INTR_ADMIN:
6182 info = &ctx->ifc_filter_info;
6183 gtask = &ctx->ifc_admin_task;
6184 tqg = qgroup_if_config_tqg;
6185 fn = _task_fn_admin;
6186 intr_fast = iflib_fast_intr_ctx;
6189 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6194 info->ifi_filter = filter;
6195 info->ifi_filter_arg = filter_arg;
6196 info->ifi_task = gtask;
6200 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6202 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6205 if (type == IFLIB_INTR_ADMIN)
6209 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6214 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6221 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6223 struct grouptask *gtask;
6224 struct taskqgroup *tqg;
6231 q = &ctx->ifc_txqs[qid];
6232 gtask = &ctx->ifc_txqs[qid].ift_task;
6233 tqg = qgroup_if_io_tqg;
6235 GROUPTASK_INIT(gtask, 0, fn, q);
6238 q = &ctx->ifc_rxqs[qid];
6239 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6240 tqg = qgroup_if_io_tqg;
6242 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6244 case IFLIB_INTR_IOV:
6246 gtask = &ctx->ifc_vflr_task;
6247 tqg = qgroup_if_config_tqg;
6249 GROUPTASK_INIT(gtask, 0, fn, q);
6252 panic("unknown net intr type");
6255 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6258 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6261 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6266 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6270 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6273 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6274 rman_get_rid(irq->ii_res), irq->ii_res);
6278 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6280 iflib_txq_t txq = ctx->ifc_txqs;
6281 iflib_rxq_t rxq = ctx->ifc_rxqs;
6282 if_irq_t irq = &ctx->ifc_legacy_irq;
6283 iflib_filter_info_t info;
6285 struct grouptask *gtask;
6286 struct resource *res;
6287 struct taskqgroup *tqg;
6292 q = &ctx->ifc_rxqs[0];
6293 info = &rxq[0].ifr_filter_info;
6294 gtask = &rxq[0].ifr_task;
6295 tqg = qgroup_if_io_tqg;
6297 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6299 ctx->ifc_flags |= IFC_LEGACY;
6300 info->ifi_filter = filter;
6301 info->ifi_filter_arg = filter_arg;
6302 info->ifi_task = gtask;
6303 info->ifi_ctx = rx_only ? ctx : q;
6306 /* We allocate a single interrupt resource */
6307 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6308 iflib_fast_intr_rxtx, NULL, info, name);
6311 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6313 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6315 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6316 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6322 iflib_led_create(if_ctx_t ctx)
6325 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6326 device_get_nameunit(ctx->ifc_dev));
6330 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6333 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6337 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6340 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6344 iflib_admin_intr_deferred(if_ctx_t ctx)
6347 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6348 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6352 iflib_iov_intr_deferred(if_ctx_t ctx)
6355 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6359 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6362 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6367 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6371 GROUPTASK_INIT(gtask, 0, fn, ctx);
6372 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6377 iflib_config_gtask_deinit(struct grouptask *gtask)
6380 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6384 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6386 if_t ifp = ctx->ifc_ifp;
6387 iflib_txq_t txq = ctx->ifc_txqs;
6389 if_setbaudrate(ifp, baudrate);
6390 if (baudrate >= IF_Gbps(10)) {
6392 ctx->ifc_flags |= IFC_PREFETCH;
6395 /* If link down, disable watchdog */
6396 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6397 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6398 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6400 ctx->ifc_link_state = link_state;
6401 if_link_state_change(ifp, link_state);
6405 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6409 int credits_pre = txq->ift_cidx_processed;
6412 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6413 BUS_DMASYNC_POSTREAD);
6414 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6417 txq->ift_processed += credits;
6418 txq->ift_cidx_processed += credits;
6420 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6421 if (txq->ift_cidx_processed >= txq->ift_size)
6422 txq->ift_cidx_processed -= txq->ift_size;
6427 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6432 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6433 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6435 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6440 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6441 const char *description, if_int_delay_info_t info,
6442 int offset, int value)
6444 info->iidi_ctx = ctx;
6445 info->iidi_offset = offset;
6446 info->iidi_value = value;
6447 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6448 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6449 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6450 info, 0, iflib_sysctl_int_delay, "I", description);
6454 iflib_ctx_lock_get(if_ctx_t ctx)
6457 return (&ctx->ifc_ctx_sx);
6461 iflib_msix_init(if_ctx_t ctx)
6463 device_t dev = ctx->ifc_dev;
6464 if_shared_ctx_t sctx = ctx->ifc_sctx;
6465 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6466 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6467 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6469 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6470 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6473 device_printf(dev, "msix_init qsets capped at %d\n",
6474 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6476 /* Override by tuneable */
6477 if (scctx->isc_disable_msix)
6480 /* First try MSI-X */
6481 if ((msgs = pci_msix_count(dev)) == 0) {
6483 device_printf(dev, "MSI-X not supported or disabled\n");
6487 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6489 * bar == -1 => "trust me I know what I'm doing"
6490 * Some drivers are for hardware that is so shoddily
6491 * documented that no one knows which bars are which
6492 * so the developer has to map all bars. This hack
6493 * allows shoddy garbage to use MSI-X in this framework.
6496 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6497 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6498 if (ctx->ifc_msix_mem == NULL) {
6499 device_printf(dev, "Unable to map MSI-X table\n");
6504 admincnt = sctx->isc_admin_intrcnt;
6506 /* use only 1 qset in debug mode */
6507 queuemsgs = min(msgs - admincnt, 1);
6509 queuemsgs = msgs - admincnt;
6512 queues = imin(queuemsgs, rss_getnumbuckets());
6516 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6519 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6520 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6522 /* If we're doing RSS, clamp at the number of RSS buckets */
6523 if (queues > rss_getnumbuckets())
6524 queues = rss_getnumbuckets();
6526 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6527 rx_queues = iflib_num_rx_queues;
6531 if (rx_queues > scctx->isc_nrxqsets)
6532 rx_queues = scctx->isc_nrxqsets;
6535 * We want this to be all logical CPUs by default
6537 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6538 tx_queues = iflib_num_tx_queues;
6540 tx_queues = mp_ncpus;
6542 if (tx_queues > scctx->isc_ntxqsets)
6543 tx_queues = scctx->isc_ntxqsets;
6545 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6547 if (tx_queues != rx_queues)
6549 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6550 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6552 tx_queues = min(rx_queues, tx_queues);
6553 rx_queues = min(rx_queues, tx_queues);
6556 vectors = rx_queues + admincnt;
6557 if (msgs < vectors) {
6559 "insufficient number of MSI-X vectors "
6560 "(supported %d, need %d)\n", msgs, vectors);
6564 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6567 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6568 if (vectors != msgs) {
6570 "Unable to allocate sufficient MSI-X vectors "
6571 "(got %d, need %d)\n", vectors, msgs);
6572 pci_release_msi(dev);
6574 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6576 ctx->ifc_msix_mem = NULL;
6580 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6582 scctx->isc_vectors = vectors;
6583 scctx->isc_nrxqsets = rx_queues;
6584 scctx->isc_ntxqsets = tx_queues;
6585 scctx->isc_intr = IFLIB_INTR_MSIX;
6590 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6593 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6595 ctx->ifc_msix_mem = NULL;
6600 vectors = pci_msi_count(dev);
6601 scctx->isc_nrxqsets = 1;
6602 scctx->isc_ntxqsets = 1;
6603 scctx->isc_vectors = vectors;
6604 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6605 device_printf(dev,"Using an MSI interrupt\n");
6606 scctx->isc_intr = IFLIB_INTR_MSI;
6608 scctx->isc_vectors = 1;
6609 device_printf(dev,"Using a Legacy interrupt\n");
6610 scctx->isc_intr = IFLIB_INTR_LEGACY;
6616 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6619 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6622 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6624 const char *ring_state = "UNKNOWN";
6627 rc = sysctl_wire_old_buffer(req, 0);
6631 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6636 ring_state = ring_states[state[3]];
6638 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6639 state[0], state[1], state[2], ring_state);
6640 rc = sbuf_finish(sb);
6645 enum iflib_ndesc_handler {
6651 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6653 if_ctx_t ctx = (void *)arg1;
6654 enum iflib_ndesc_handler type = arg2;
6655 char buf[256] = {0};
6662 case IFLIB_NTXD_HANDLER:
6663 ndesc = ctx->ifc_sysctl_ntxds;
6665 nqs = ctx->ifc_sctx->isc_ntxqs;
6667 case IFLIB_NRXD_HANDLER:
6668 ndesc = ctx->ifc_sysctl_nrxds;
6670 nqs = ctx->ifc_sctx->isc_nrxqs;
6673 printf("%s: unhandled type\n", __func__);
6679 for (i=0; i<8; i++) {
6684 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6687 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6688 if (rc || req->newptr == NULL)
6691 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6692 i++, p = strsep(&next, " ,")) {
6693 ndesc[i] = strtoul(p, NULL, 10);
6699 #define NAME_BUFLEN 32
6701 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6703 device_t dev = iflib_get_dev(ctx);
6704 struct sysctl_oid_list *child, *oid_list;
6705 struct sysctl_ctx_list *ctx_list;
6706 struct sysctl_oid *node;
6708 ctx_list = device_get_sysctl_ctx(dev);
6709 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6710 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6711 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6712 oid_list = SYSCTL_CHILDREN(node);
6714 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6715 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6718 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6719 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6720 "# of txqs to use, 0 => use default #");
6721 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6722 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6723 "# of rxqs to use, 0 => use default #");
6724 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6725 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6726 "permit #txq != #rxq");
6727 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6728 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6729 "disable MSI-X (default 0)");
6730 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6731 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6732 "set the RX budget");
6733 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6734 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6735 "cause TX to abdicate instead of running to completion");
6736 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6737 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6738 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6739 "offset to start using cores at");
6740 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6741 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6742 "use separate cores for TX and RX");
6744 /* XXX change for per-queue sizes */
6745 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6746 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6747 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6748 "list of # of TX descriptors to use, 0 = use default #");
6749 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6750 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6751 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6752 "list of # of RX descriptors to use, 0 = use default #");
6756 iflib_add_device_sysctl_post(if_ctx_t ctx)
6758 if_shared_ctx_t sctx = ctx->ifc_sctx;
6759 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6760 device_t dev = iflib_get_dev(ctx);
6761 struct sysctl_oid_list *child;
6762 struct sysctl_ctx_list *ctx_list;
6767 char namebuf[NAME_BUFLEN];
6769 struct sysctl_oid *queue_node, *fl_node, *node;
6770 struct sysctl_oid_list *queue_list, *fl_list;
6771 ctx_list = device_get_sysctl_ctx(dev);
6773 node = ctx->ifc_sysctl_node;
6774 child = SYSCTL_CHILDREN(node);
6776 if (scctx->isc_ntxqsets > 100)
6778 else if (scctx->isc_ntxqsets > 10)
6782 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6783 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6784 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6785 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6786 queue_list = SYSCTL_CHILDREN(queue_node);
6788 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6790 &txq->ift_dequeued, "total mbufs freed");
6791 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6793 &txq->ift_enqueued, "total mbufs enqueued");
6795 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6797 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6798 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6800 &txq->ift_pullups, "# of times m_pullup was called");
6801 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6803 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6804 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6806 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6807 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6809 &txq->ift_map_failed, "# of times DMA map failed");
6810 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6812 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6813 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6815 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6816 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6818 &txq->ift_pidx, 1, "Producer Index");
6819 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6821 &txq->ift_cidx, 1, "Consumer Index");
6822 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6824 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6825 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6827 &txq->ift_in_use, 1, "descriptors in use");
6828 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6830 &txq->ift_processed, "descriptors procesed for clean");
6831 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6833 &txq->ift_cleaned, "total cleaned");
6834 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6835 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6836 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6837 mp_ring_state_handler, "A", "soft ring state");
6838 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6839 CTLFLAG_RD, &txq->ift_br->enqueues,
6840 "# of enqueues to the mp_ring for this queue");
6841 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6842 CTLFLAG_RD, &txq->ift_br->drops,
6843 "# of drops in the mp_ring for this queue");
6844 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6845 CTLFLAG_RD, &txq->ift_br->starts,
6846 "# of normal consumer starts in the mp_ring for this queue");
6847 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6848 CTLFLAG_RD, &txq->ift_br->stalls,
6849 "# of consumer stalls in the mp_ring for this queue");
6850 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6851 CTLFLAG_RD, &txq->ift_br->restarts,
6852 "# of consumer restarts in the mp_ring for this queue");
6853 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6854 CTLFLAG_RD, &txq->ift_br->abdications,
6855 "# of consumer abdications in the mp_ring for this queue");
6858 if (scctx->isc_nrxqsets > 100)
6860 else if (scctx->isc_nrxqsets > 10)
6864 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6865 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6866 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6867 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6868 queue_list = SYSCTL_CHILDREN(queue_node);
6869 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6870 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6872 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6875 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6876 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6877 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6878 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6879 fl_list = SYSCTL_CHILDREN(fl_node);
6880 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6882 &fl->ifl_pidx, 1, "Producer Index");
6883 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6885 &fl->ifl_cidx, 1, "Consumer Index");
6886 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6888 &fl->ifl_credits, 1, "credits available");
6889 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6891 &fl->ifl_buf_size, 1, "buffer size");
6893 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6895 &fl->ifl_m_enqueued, "mbufs allocated");
6896 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6898 &fl->ifl_m_dequeued, "mbufs freed");
6899 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6901 &fl->ifl_cl_enqueued, "clusters allocated");
6902 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6904 &fl->ifl_cl_dequeued, "clusters freed");
6912 iflib_request_reset(if_ctx_t ctx)
6916 ctx->ifc_flags |= IFC_DO_RESET;
6920 #ifndef __NO_STRICT_ALIGNMENT
6921 static struct mbuf *
6922 iflib_fixup_rx(struct mbuf *m)
6926 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6927 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6928 m->m_data += ETHER_HDR_LEN;
6931 MGETHDR(n, M_NOWAIT, MT_DATA);
6936 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6937 m->m_data += ETHER_HDR_LEN;
6938 m->m_len -= ETHER_HDR_LEN;
6939 n->m_len = ETHER_HDR_LEN;
6940 M_MOVE_PKTHDR(n, m);
6949 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6953 ctx = if_getsoftc(ifp);
6955 *nrxr = NRXQSETS(ctx);
6956 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6957 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6962 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6965 if_softc_ctx_t scctx;
6970 ctx = if_getsoftc(ifp);
6971 scctx = &ctx->ifc_softc_ctx;
6974 case DEBUGNET_START:
6975 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6976 rxq = &ctx->ifc_rxqs[i];
6977 for (j = 0; j < rxq->ifr_nfl; j++) {
6979 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6982 iflib_no_tx_batch = 1;
6990 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6996 ctx = if_getsoftc(ifp);
6997 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7001 txq = &ctx->ifc_txqs[0];
7002 error = iflib_encap(txq, &m);
7004 (void)iflib_txd_db_check(txq, true);
7009 iflib_debugnet_poll(if_t ifp, int count)
7011 struct epoch_tracker et;
7013 if_softc_ctx_t scctx;
7017 ctx = if_getsoftc(ifp);
7018 scctx = &ctx->ifc_softc_ctx;
7020 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7024 txq = &ctx->ifc_txqs[0];
7025 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
7027 NET_EPOCH_ENTER(et);
7028 for (i = 0; i < scctx->isc_nrxqsets; i++)
7029 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7033 #endif /* DEBUGNET */