2 * Copyright (c) 2014-2016, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
63 #include <netinet/in.h>
64 #include <netinet/in_pcb.h>
65 #include <netinet/tcp_lro.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/if_ether.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
78 #include <dev/led/led.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pci_private.h>
83 #include <net/iflib.h>
87 #if defined(__i386__) || defined(__amd64__)
88 #include <sys/memdesc.h>
89 #include <machine/bus.h>
90 #include <machine/md_var.h>
91 #include <machine/specialreg.h>
92 #include <x86/include/busdma_impl.h>
93 #include <x86/iommu/busdma_dmar.h>
97 * enable accounting of every mbuf as it comes in to and goes out of iflib's software descriptor references
99 #define MEMORY_LOGGING 0
101 * Enable mbuf vectors for compressing long mbuf chains
106 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
107 * we prefetch needs to be determined by the time spent in m_free vis a vis
108 * the cost of a prefetch. This will of course vary based on the workload:
109 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
110 * is quite expensive, thus suggesting very little prefetch.
111 * - small packet forwarding which is just returning a single mbuf to
112 * UMA will typically be very fast vis a vis the cost of a memory
119 * - private structures
120 * - iflib private utility functions
122 * - vlan registry and other exported functions
123 * - iflib public core functions
127 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
130 typedef struct iflib_txq *iflib_txq_t;
132 typedef struct iflib_rxq *iflib_rxq_t;
134 typedef struct iflib_fl *iflib_fl_t;
136 typedef struct iflib_filter_info {
137 driver_filter_t *ifi_filter;
138 void *ifi_filter_arg;
139 struct grouptask *ifi_task;
140 } *iflib_filter_info_t;
145 * Pointer to hardware driver's softc
152 if_shared_ctx_t ifc_sctx;
153 struct if_softc_ctx ifc_softc_ctx;
157 uint16_t ifc_nhwtxqs;
158 uint16_t ifc_nhwrxqs;
160 iflib_txq_t ifc_txqs;
161 iflib_rxq_t ifc_rxqs;
162 uint32_t ifc_if_flags;
164 uint32_t ifc_max_fl_buf_size;
169 int ifc_pause_frames;
170 int ifc_watchdog_events;
171 struct cdev *ifc_led_dev;
172 struct resource *ifc_msix_mem;
174 struct if_irq ifc_legacy_irq;
175 struct grouptask ifc_admin_task;
176 struct grouptask ifc_vflr_task;
177 struct iflib_filter_info ifc_filter_info;
178 struct ifmedia ifc_media;
180 struct sysctl_oid *ifc_sysctl_node;
181 uint16_t ifc_sysctl_ntxqs;
182 uint16_t ifc_sysctl_nrxqs;
183 uint16_t ifc_sysctl_qs_eq_override;
185 uint16_t ifc_sysctl_ntxds[8];
186 uint16_t ifc_sysctl_nrxds[8];
187 struct if_txrx ifc_txrx;
188 #define isc_txd_encap ifc_txrx.ift_txd_encap
189 #define isc_txd_flush ifc_txrx.ift_txd_flush
190 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
191 #define isc_rxd_available ifc_txrx.ift_rxd_available
192 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
193 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
194 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
195 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
196 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
197 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
198 eventhandler_tag ifc_vlan_attach_event;
199 eventhandler_tag ifc_vlan_detach_event;
200 uint8_t ifc_mac[ETHER_ADDR_LEN];
201 char ifc_mtx_name[16];
206 iflib_get_softc(if_ctx_t ctx)
209 return (ctx->ifc_softc);
213 iflib_get_dev(if_ctx_t ctx)
216 return (ctx->ifc_dev);
220 iflib_get_ifp(if_ctx_t ctx)
223 return (ctx->ifc_ifp);
227 iflib_get_media(if_ctx_t ctx)
230 return (&ctx->ifc_media);
234 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
237 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
241 iflib_get_softc_ctx(if_ctx_t ctx)
244 return (&ctx->ifc_softc_ctx);
248 iflib_get_sctx(if_ctx_t ctx)
251 return (ctx->ifc_sctx);
254 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
256 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
257 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
259 #define RX_SW_DESC_MAP_CREATED (1 << 0)
260 #define TX_SW_DESC_MAP_CREATED (1 << 1)
261 #define RX_SW_DESC_INUSE (1 << 3)
262 #define TX_SW_DESC_MAPPED (1 << 4)
264 typedef struct iflib_sw_rx_desc {
265 bus_dmamap_t ifsd_map; /* bus_dma map for packet */
266 struct mbuf *ifsd_m; /* rx: uninitialized mbuf */
267 caddr_t ifsd_cl; /* direct cluster pointer for rx */
271 typedef struct iflib_sw_tx_desc_val {
272 bus_dmamap_t ifsd_map; /* bus_dma map for packet */
273 struct mbuf *ifsd_m; /* pkthdr mbuf */
277 typedef struct iflib_sw_tx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
281 } iflib_txsd_array_t;
284 /* magic number that should be high enough for any hardware */
285 #define IFLIB_MAX_TX_SEGS 128
286 #define IFLIB_MAX_RX_SEGS 32
287 #define IFLIB_RX_COPY_THRESH 128
288 #define IFLIB_MAX_RX_REFRESH 32
289 #define IFLIB_QUEUE_IDLE 0
290 #define IFLIB_QUEUE_HUNG 1
291 #define IFLIB_QUEUE_WORKING 2
293 /* this should really scale with ring size - 32 is a fairly arbitrary value for this */
294 #define TX_BATCH_SIZE 16
296 #define IFLIB_RESTART_BUDGET 8
298 #define IFC_LEGACY 0x01
299 #define IFC_QFLUSH 0x02
300 #define IFC_MULTISEG 0x04
301 #define IFC_DMAR 0x08
302 #define IFC_SC_ALLOCATED 0x10
304 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
305 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
306 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
310 uint16_t ift_cidx_processed;
313 uint8_t ift_db_pending;
314 uint8_t ift_db_pending_queued;
315 uint8_t ift_npending;
316 uint8_t ift_br_offset;
318 uint64_t ift_processed;
319 uint64_t ift_cleaned;
321 uint64_t ift_enqueued;
322 uint64_t ift_dequeued;
324 uint64_t ift_no_tx_dma_setup;
325 uint64_t ift_no_desc_avail;
326 uint64_t ift_mbuf_defrag_failed;
327 uint64_t ift_mbuf_defrag;
328 uint64_t ift_map_failed;
329 uint64_t ift_txd_encap_efbig;
330 uint64_t ift_pullups;
333 struct mtx ift_db_mtx;
335 /* constant values */
337 struct ifmp_ring **ift_br;
338 struct grouptask ift_task;
341 struct callout ift_timer;
342 struct callout ift_db_check;
344 iflib_txsd_array_t ift_sds;
349 int ift_watchdog_time;
350 struct iflib_filter_info ift_filter_info;
351 bus_dma_tag_t ift_desc_tag;
352 bus_dma_tag_t ift_tso_desc_tag;
353 iflib_dma_info_t ift_ifdi;
354 #define MTX_NAME_LEN 16
355 char ift_mtx_name[MTX_NAME_LEN];
356 char ift_db_mtx_name[MTX_NAME_LEN];
357 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
358 } __aligned(CACHE_LINE_SIZE);
363 uint16_t ifl_credits;
366 uint64_t ifl_m_enqueued;
367 uint64_t ifl_m_dequeued;
368 uint64_t ifl_cl_enqueued;
369 uint64_t ifl_cl_dequeued;
375 uint16_t ifl_buf_size;
378 iflib_rxsd_t ifl_sds;
381 bus_dma_tag_t ifl_desc_tag;
382 iflib_dma_info_t ifl_ifdi;
383 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
384 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
385 } __aligned(CACHE_LINE_SIZE);
388 get_inuse(int size, int cidx, int pidx, int gen)
394 else if (pidx < cidx)
395 used = size - cidx + pidx;
396 else if (gen == 0 && pidx == cidx)
398 else if (gen == 1 && pidx == cidx)
406 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
408 #define IDXDIFF(head, tail, wrap) \
409 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
412 /* If there is a separate completion queue -
413 * these are the cq cidx and pidx. Otherwise
417 uint16_t ifr_cq_cidx;
418 uint16_t ifr_cq_pidx;
420 uint8_t ifr_fl_offset;
426 uint8_t ifr_lro_enabled;
428 struct lro_ctrl ifr_lc;
429 struct grouptask ifr_task;
430 struct iflib_filter_info ifr_filter_info;
431 iflib_dma_info_t ifr_ifdi;
432 /* dynamically allocate if any drivers need a value substantially larger than this */
433 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
434 } __aligned(CACHE_LINE_SIZE);
437 * Only allow a single packet to take up most 1/nth of the tx ring
439 #define MAX_SINGLE_PACKET_FRACTION 12
440 #define IF_BAD_DMA (bus_addr_t)-1
442 static int enable_msix = 1;
444 #define mtx_held(m) (((m)->mtx_lock & ~MTX_FLAGMASK) != (uintptr_t)0)
448 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
450 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
452 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
453 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
454 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
457 #define TXDB_LOCK_INIT(txq) mtx_init(&(txq)->ift_db_mtx, (txq)->ift_db_mtx_name, NULL, MTX_DEF)
458 #define TXDB_TRYLOCK(txq) mtx_trylock(&(txq)->ift_db_mtx)
459 #define TXDB_LOCK(txq) mtx_lock(&(txq)->ift_db_mtx)
460 #define TXDB_UNLOCK(txq) mtx_unlock(&(txq)->ift_db_mtx)
461 #define TXDB_LOCK_DESTROY(txq) mtx_destroy(&(txq)->ift_db_mtx)
463 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
464 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
467 /* Our boot-time initialization hook */
468 static int iflib_module_event_handler(module_t, int, void *);
470 static moduledata_t iflib_moduledata = {
472 iflib_module_event_handler,
476 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
477 MODULE_VERSION(iflib, 1);
479 MODULE_DEPEND(iflib, pci, 1, 1, 1);
480 MODULE_DEPEND(iflib, ether, 1, 1, 1);
482 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
483 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
485 #ifndef IFLIB_DEBUG_COUNTERS
487 #define IFLIB_DEBUG_COUNTERS 1
489 #define IFLIB_DEBUG_COUNTERS 0
490 #endif /* !INVARIANTS */
493 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
494 "iflib driver parameters");
497 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
499 static int iflib_min_tx_latency = 0;
501 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
502 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
505 #if IFLIB_DEBUG_COUNTERS
507 static int iflib_tx_seen;
508 static int iflib_tx_sent;
509 static int iflib_tx_encap;
510 static int iflib_rx_allocs;
511 static int iflib_fl_refills;
512 static int iflib_fl_refills_large;
513 static int iflib_tx_frees;
515 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
516 &iflib_tx_seen, 0, "# tx mbufs seen");
517 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
518 &iflib_tx_sent, 0, "# tx mbufs sent");
519 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
520 &iflib_tx_encap, 0, "# tx mbufs encapped");
521 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
522 &iflib_tx_frees, 0, "# tx frees");
523 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
524 &iflib_rx_allocs, 0, "# rx allocations");
525 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
526 &iflib_fl_refills, 0, "# refills");
527 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
528 &iflib_fl_refills_large, 0, "# large refills");
531 static int iflib_txq_drain_flushing;
532 static int iflib_txq_drain_oactive;
533 static int iflib_txq_drain_notready;
534 static int iflib_txq_drain_encapfail;
536 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
537 &iflib_txq_drain_flushing, 0, "# drain flushes");
538 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
539 &iflib_txq_drain_oactive, 0, "# drain oactives");
540 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
541 &iflib_txq_drain_notready, 0, "# drain notready");
542 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
543 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
546 static int iflib_encap_load_mbuf_fail;
547 static int iflib_encap_txq_avail_fail;
548 static int iflib_encap_txd_encap_fail;
550 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
551 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
552 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
553 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
554 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
555 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
557 static int iflib_task_fn_rxs;
558 static int iflib_rx_intr_enables;
559 static int iflib_fast_intrs;
560 static int iflib_intr_link;
561 static int iflib_intr_msix;
562 static int iflib_rx_unavail;
563 static int iflib_rx_ctx_inactive;
564 static int iflib_rx_zero_len;
565 static int iflib_rx_if_input;
566 static int iflib_rx_mbuf_null;
567 static int iflib_rxd_flush;
569 static int iflib_verbose_debug;
571 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
572 &iflib_intr_link, 0, "# intr link calls");
573 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
574 &iflib_intr_msix, 0, "# intr msix calls");
575 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
576 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
577 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
578 &iflib_rx_intr_enables, 0, "# rx intr enables");
579 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
580 &iflib_fast_intrs, 0, "# fast_intr calls");
581 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
582 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
583 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
584 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
585 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
586 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
587 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
588 &iflib_rx_if_input, 0, "# times rxeof called if_input");
589 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
590 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
591 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
592 &iflib_rxd_flush, 0, "# times rxd_flush called");
593 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
594 &iflib_verbose_debug, 0, "enable verbose debugging");
596 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
598 iflib_debug_reset(void)
600 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
601 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
602 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
603 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
604 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail =
605 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables =
606 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
607 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
608 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
612 #define DBG_COUNTER_INC(name)
613 static void iflib_debug_reset(void) {}
618 #define IFLIB_DEBUG 0
620 static void iflib_tx_structures_free(if_ctx_t ctx);
621 static void iflib_rx_structures_free(if_ctx_t ctx);
622 static int iflib_queues_alloc(if_ctx_t ctx);
623 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
624 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget);
625 static int iflib_qset_structures_setup(if_ctx_t ctx);
626 static int iflib_msix_init(if_ctx_t ctx);
627 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
628 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
629 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
630 static int iflib_register(if_ctx_t);
631 static void iflib_init_locked(if_ctx_t ctx);
632 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
633 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
634 static void iflib_ifmp_purge(iflib_txq_t txq);
638 #include <sys/selinfo.h>
639 #include <net/netmap.h>
640 #include <dev/netmap/netmap_kern.h>
642 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
645 * device-specific sysctl variables:
647 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
648 * During regular operations the CRC is stripped, but on some
649 * hardware reception of frames not multiple of 64 is slower,
650 * so using crcstrip=0 helps in benchmarks.
652 * iflib_rx_miss, iflib_rx_miss_bufs:
653 * count packets that might be missed due to lost interrupts.
655 SYSCTL_DECL(_dev_netmap);
657 * The xl driver by default strips CRCs and we do not override it.
660 int iflib_crcstrip = 1;
661 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
662 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
664 int iflib_rx_miss, iflib_rx_miss_bufs;
665 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
666 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
667 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
668 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
671 * Register/unregister. We are already under netmap lock.
672 * Only called on the first register or the last unregister.
675 iflib_netmap_register(struct netmap_adapter *na, int onoff)
677 struct ifnet *ifp = na->ifp;
678 if_ctx_t ctx = ifp->if_softc;
681 IFDI_INTR_DISABLE(ctx);
683 /* Tell the stack that the interface is no longer active */
684 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
687 IFDI_CRCSTRIP_SET(ctx, onoff);
689 /* enable or disable flags and callbacks in na and ifp */
691 nm_set_native_flags(na);
693 nm_clear_native_flags(na);
696 IFDI_CRCSTRIP_SET(ctx, onoff); // XXX why twice ?
698 return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1);
702 * Reconcile kernel and user view of the transmit ring.
704 * All information is in the kring.
705 * Userspace wants to send packets up to the one before kring->rhead,
706 * kernel knows kring->nr_hwcur is the first unsent packet.
708 * Here we push packets out (as many as possible), and possibly
709 * reclaim buffers from previously completed transmission.
711 * The caller (netmap) guarantees that there is only one instance
712 * running at any time. Any interference with other driver
713 * methods should be handled by the individual drivers.
716 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
718 struct netmap_adapter *na = kring->na;
719 struct ifnet *ifp = na->ifp;
720 struct netmap_ring *ring = kring->ring;
721 u_int nm_i; /* index into the netmap ring */
722 u_int nic_i; /* index into the NIC ring */
724 u_int const lim = kring->nkr_num_slots - 1;
725 u_int const head = kring->rhead;
726 struct if_pkt_info pi;
729 * interrupts on every tx packet are expensive so request
730 * them every half ring, or where NS_REPORT is set
732 u_int report_frequency = kring->nkr_num_slots >> 1;
733 /* device-specific */
734 if_ctx_t ctx = ifp->if_softc;
735 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
737 pi.ipi_segs = txq->ift_segs;
738 pi.ipi_qsidx = kring->ring_id;
741 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
742 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
746 * First part: process new packets to send.
747 * nm_i is the current index in the netmap ring,
748 * nic_i is the corresponding index in the NIC ring.
750 * If we have packets to send (nm_i != head)
751 * iterate over the netmap ring, fetch length and update
752 * the corresponding slot in the NIC ring. Some drivers also
753 * need to update the buffer's physical address in the NIC slot
754 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
756 * The netmap_reload_map() calls is especially expensive,
757 * even when (as in this case) the tag is 0, so do only
758 * when the buffer has actually changed.
760 * If possible do not set the report/intr bit on all slots,
761 * but only a few times per ring or when NS_REPORT is set.
763 * Finally, on 10G and faster drivers, it might be useful
764 * to prefetch the next slot and txr entry.
767 nm_i = kring->nr_hwcur;
768 if (nm_i != head) { /* we have new packets to send */
769 nic_i = netmap_idx_k2n(kring, nm_i);
771 __builtin_prefetch(&ring->slot[nm_i]);
772 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
773 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
775 for (n = 0; nm_i != head; n++) {
776 struct netmap_slot *slot = &ring->slot[nm_i];
777 u_int len = slot->len;
779 void *addr = PNMB(na, slot, &paddr);
780 int flags = (slot->flags & NS_REPORT ||
781 nic_i == 0 || nic_i == report_frequency) ?
784 /* device-specific */
786 pi.ipi_flags = flags;
788 /* Fill the slot in the NIC ring. */
789 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
791 /* prefetch for next round */
792 __builtin_prefetch(&ring->slot[nm_i + 1]);
793 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
794 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
796 NM_CHECK_ADDR_LEN(na, addr, len);
798 if (slot->flags & NS_BUF_CHANGED) {
799 /* buffer has changed, reload map */
800 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
802 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
804 /* make sure changes to the buffer are synced */
805 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
806 BUS_DMASYNC_PREWRITE);
808 nm_i = nm_next(nm_i, lim);
809 nic_i = nm_next(nic_i, lim);
811 kring->nr_hwcur = head;
813 /* synchronize the NIC ring */
814 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
817 /* (re)start the tx unit up to slot nic_i (excluded) */
818 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
822 * Second part: reclaim buffers for completed transmissions.
824 if (iflib_tx_credits_update(ctx, txq)) {
825 /* some tx completed, increment avail */
826 nic_i = txq->ift_cidx_processed;
827 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
833 * Reconcile kernel and user view of the receive ring.
834 * Same as for the txsync, this routine must be efficient.
835 * The caller guarantees a single invocations, but races against
836 * the rest of the driver should be handled here.
838 * On call, kring->rhead is the first packet that userspace wants
839 * to keep, and kring->rcur is the wakeup point.
840 * The kernel has previously reported packets up to kring->rtail.
842 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
843 * of whether or not we received an interrupt.
846 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
848 struct netmap_adapter *na = kring->na;
849 struct ifnet *ifp = na->ifp;
850 struct netmap_ring *ring = kring->ring;
851 u_int nm_i; /* index into the netmap ring */
852 u_int nic_i; /* index into the NIC ring */
854 u_int const lim = kring->nkr_num_slots - 1;
855 u_int const head = kring->rhead;
856 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
857 struct if_rxd_info ri;
858 /* device-specific */
859 if_ctx_t ctx = ifp->if_softc;
860 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
861 iflib_fl_t fl = rxq->ifr_fl;
863 return netmap_ring_reinit(kring);
865 bzero(&ri, sizeof(ri));
866 ri.iri_qsidx = kring->ring_id;
867 ri.iri_ifp = ctx->ifc_ifp;
868 /* XXX check sync modes */
869 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++)
870 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
871 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
874 * First part: import newly received packets.
876 * nm_i is the index of the next free slot in the netmap ring,
877 * nic_i is the index of the next received packet in the NIC ring,
878 * and they may differ in case if_init() has been called while
879 * in netmap mode. For the receive ring we have
881 * nic_i = rxr->next_check;
882 * nm_i = kring->nr_hwtail (previous)
884 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
886 * rxr->next_check is set to 0 on a ring reinit
888 if (netmap_no_pendintr || force_update) {
889 int crclen = iflib_crcstrip ? 0 : 4;
891 uint16_t slot_flags = kring->nkr_slot_flags;
893 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) {
894 nic_i = fl->ifl_cidx;
895 nm_i = netmap_idx_n2k(kring, nic_i);
896 avail = ctx->isc_rxd_available(ctx->ifc_softc, kring->ring_id, nic_i, INT_MAX);
897 for (n = 0; avail > 0; n++, avail--) {
898 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
900 ring->slot[nm_i].len = 0;
902 ring->slot[nm_i].len = ri.iri_len - crclen;
903 ring->slot[nm_i].flags = slot_flags;
904 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
905 fl->ifl_sds[nic_i].ifsd_map, BUS_DMASYNC_POSTREAD);
906 nm_i = nm_next(nm_i, lim);
907 nic_i = nm_next(nic_i, lim);
909 if (n) { /* update the state variables */
910 if (netmap_no_pendintr && !force_update) {
913 iflib_rx_miss_bufs += n;
915 fl->ifl_cidx = nic_i;
916 kring->nr_hwtail = nm_i;
918 kring->nr_kflags &= ~NKR_PENDINTR;
922 * Second part: skip past packets that userspace has released.
923 * (kring->nr_hwcur to head excluded),
924 * and make the buffers available for reception.
925 * As usual nm_i is the index in the netmap ring,
926 * nic_i is the index in the NIC ring, and
927 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
929 /* XXX not sure how this will work with multiple free lists */
930 nm_i = kring->nr_hwcur;
932 nic_i = netmap_idx_k2n(kring, nm_i);
933 for (n = 0; nm_i != head; n++) {
934 struct netmap_slot *slot = &ring->slot[nm_i];
937 void *addr = PNMB(na, slot, &paddr);
939 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
943 if (slot->flags & NS_BUF_CHANGED) {
944 /* buffer has changed, reload map */
945 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map, addr);
946 slot->flags &= ~NS_BUF_CHANGED;
949 * XXX we should be batching this operation - TODO
951 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i, &paddr, &vaddr, 1, fl->ifl_buf_size);
952 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map,
953 BUS_DMASYNC_PREREAD);
954 nm_i = nm_next(nm_i, lim);
955 nic_i = nm_next(nic_i, lim);
957 kring->nr_hwcur = head;
959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
962 * IMPORTANT: we must leave one free slot in the ring,
963 * so move nic_i back by one unit
965 nic_i = nm_prev(nic_i, lim);
966 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
972 return netmap_ring_reinit(kring);
976 iflib_netmap_attach(if_ctx_t ctx)
978 struct netmap_adapter na;
979 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
981 bzero(&na, sizeof(na));
983 na.ifp = ctx->ifc_ifp;
984 na.na_flags = NAF_BDG_MAYSLEEP;
985 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
986 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
988 na.num_tx_desc = scctx->isc_ntxd[0];
989 na.num_rx_desc = scctx->isc_nrxd[0];
990 na.nm_txsync = iflib_netmap_txsync;
991 na.nm_rxsync = iflib_netmap_rxsync;
992 na.nm_register = iflib_netmap_register;
993 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
994 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
995 return (netmap_attach(&na));
999 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1001 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1002 struct netmap_slot *slot;
1004 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1008 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1011 * In netmap mode, set the map for the packet buffer.
1012 * NOTE: Some drivers (not this one) also need to set
1013 * the physical buffer address in the NIC ring.
1014 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1015 * netmap slot index, si
1017 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1018 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1022 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1024 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1025 struct netmap_slot *slot;
1029 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1032 sd = rxq->ifr_fl[0].ifl_sds;
1033 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0];
1034 for (int i = 0; i < nrxd; i++, sd++) {
1035 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i);
1040 vaddr = addr = PNMB(na, slot + sj, &paddr);
1041 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, sd->ifsd_map, addr);
1042 /* Update descriptor and the cached value */
1043 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, i, &paddr, &vaddr, 1, rxq->ifr_fl[0].ifl_buf_size);
1045 /* preserve queue */
1046 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) {
1047 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1048 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1049 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t);
1051 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1);
1054 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1057 #define iflib_netmap_txq_init(ctx, txq)
1058 #define iflib_netmap_rxq_init(ctx, rxq)
1059 #define iflib_netmap_detach(ifp)
1061 #define iflib_netmap_attach(ctx) (0)
1062 #define netmap_rx_irq(ifp, qid, budget) (0)
1066 #if defined(__i386__) || defined(__amd64__)
1067 static __inline void
1070 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1077 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1081 *(bus_addr_t *) arg = segs[0].ds_addr;
1085 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1088 if_shared_ctx_t sctx = ctx->ifc_sctx;
1089 device_t dev = ctx->ifc_dev;
1091 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1093 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1094 sctx->isc_q_align, 0, /* alignment, bounds */
1095 BUS_SPACE_MAXADDR, /* lowaddr */
1096 BUS_SPACE_MAXADDR, /* highaddr */
1097 NULL, NULL, /* filter, filterarg */
1100 size, /* maxsegsize */
1101 BUS_DMA_ALLOCNOW, /* flags */
1102 NULL, /* lockfunc */
1107 "%s: bus_dma_tag_create failed: %d\n",
1112 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1113 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1116 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1117 __func__, (uintmax_t)size, err);
1121 dma->idi_paddr = IF_BAD_DMA;
1122 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1123 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1124 if (err || dma->idi_paddr == IF_BAD_DMA) {
1126 "%s: bus_dmamap_load failed: %d\n",
1131 dma->idi_size = size;
1135 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1137 bus_dma_tag_destroy(dma->idi_tag);
1139 dma->idi_tag = NULL;
1145 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1148 iflib_dma_info_t *dmaiter;
1151 for (i = 0; i < count; i++, dmaiter++) {
1152 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1156 iflib_dma_free_multi(dmalist, i);
1161 iflib_dma_free(iflib_dma_info_t dma)
1163 if (dma->idi_tag == NULL)
1165 if (dma->idi_paddr != IF_BAD_DMA) {
1166 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1167 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1168 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1169 dma->idi_paddr = IF_BAD_DMA;
1171 if (dma->idi_vaddr != NULL) {
1172 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1173 dma->idi_vaddr = NULL;
1175 bus_dma_tag_destroy(dma->idi_tag);
1176 dma->idi_tag = NULL;
1180 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1183 iflib_dma_info_t *dmaiter = dmalist;
1185 for (i = 0; i < count; i++, dmaiter++)
1186 iflib_dma_free(*dmaiter);
1190 iflib_fast_intr(void *arg)
1192 iflib_filter_info_t info = arg;
1193 struct grouptask *gtask = info->ifi_task;
1195 DBG_COUNTER_INC(fast_intrs);
1196 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1197 return (FILTER_HANDLED);
1199 GROUPTASK_ENQUEUE(gtask);
1200 return (FILTER_HANDLED);
1204 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1205 driver_filter_t filter, driver_intr_t handler, void *arg,
1209 struct resource *res;
1211 device_t dev = ctx->ifc_dev;
1215 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid,
1216 RF_SHAREABLE | RF_ACTIVE);
1219 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1223 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1224 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1225 filter, handler, arg, &tag);
1228 "failed to setup interrupt for rid %d, name %s: %d\n",
1229 rid, name ? name : "unknown", rc);
1232 bus_describe_intr(dev, res, tag, "%s", name);
1239 /*********************************************************************
1241 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1242 * the information needed to transmit a packet on the wire. This is
1243 * called only once at attach, setup is done every reset.
1245 **********************************************************************/
1248 iflib_txsd_alloc(iflib_txq_t txq)
1250 if_ctx_t ctx = txq->ift_ctx;
1251 if_shared_ctx_t sctx = ctx->ifc_sctx;
1252 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1253 device_t dev = ctx->ifc_dev;
1254 int err, nsegments, ntsosegments;
1256 nsegments = scctx->isc_tx_nsegments;
1257 ntsosegments = scctx->isc_tx_tso_segments_max;
1258 MPASS(scctx->isc_ntxd[0] > 0);
1259 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1260 MPASS(nsegments > 0);
1261 MPASS(ntsosegments > 0);
1263 * Setup DMA descriptor areas.
1265 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1266 1, 0, /* alignment, bounds */
1267 BUS_SPACE_MAXADDR, /* lowaddr */
1268 BUS_SPACE_MAXADDR, /* highaddr */
1269 NULL, NULL, /* filter, filterarg */
1270 sctx->isc_tx_maxsize, /* maxsize */
1271 nsegments, /* nsegments */
1272 sctx->isc_tx_maxsegsize, /* maxsegsize */
1274 NULL, /* lockfunc */
1275 NULL, /* lockfuncarg */
1276 &txq->ift_desc_tag))) {
1277 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1278 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n",
1279 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize);
1282 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1283 1, 0, /* alignment, bounds */
1284 BUS_SPACE_MAXADDR, /* lowaddr */
1285 BUS_SPACE_MAXADDR, /* highaddr */
1286 NULL, NULL, /* filter, filterarg */
1287 scctx->isc_tx_tso_size_max, /* maxsize */
1288 ntsosegments, /* nsegments */
1289 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1291 NULL, /* lockfunc */
1292 NULL, /* lockfuncarg */
1293 &txq->ift_tso_desc_tag))) {
1294 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1298 if (!(txq->ift_sds.ifsd_flags =
1299 (uint8_t *) malloc(sizeof(uint8_t) *
1300 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1301 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1305 if (!(txq->ift_sds.ifsd_m =
1306 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1307 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1308 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1313 /* Create the descriptor buffer dma maps */
1314 #if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__)))
1315 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1318 if (!(txq->ift_sds.ifsd_map =
1319 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1320 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1325 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1326 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1328 device_printf(dev, "Unable to create TX DMA map\n");
1335 /* We free all, it handles case where we are in the middle */
1336 iflib_tx_structures_free(ctx);
1341 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1346 if (txq->ift_sds.ifsd_map != NULL)
1347 map = txq->ift_sds.ifsd_map[i];
1349 bus_dmamap_unload(txq->ift_desc_tag, map);
1350 bus_dmamap_destroy(txq->ift_desc_tag, map);
1351 txq->ift_sds.ifsd_map[i] = NULL;
1356 iflib_txq_destroy(iflib_txq_t txq)
1358 if_ctx_t ctx = txq->ift_ctx;
1360 for (int i = 0; i < txq->ift_size; i++)
1361 iflib_txsd_destroy(ctx, txq, i);
1362 if (txq->ift_sds.ifsd_map != NULL) {
1363 free(txq->ift_sds.ifsd_map, M_IFLIB);
1364 txq->ift_sds.ifsd_map = NULL;
1366 if (txq->ift_sds.ifsd_m != NULL) {
1367 free(txq->ift_sds.ifsd_m, M_IFLIB);
1368 txq->ift_sds.ifsd_m = NULL;
1370 if (txq->ift_sds.ifsd_flags != NULL) {
1371 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1372 txq->ift_sds.ifsd_flags = NULL;
1374 if (txq->ift_desc_tag != NULL) {
1375 bus_dma_tag_destroy(txq->ift_desc_tag);
1376 txq->ift_desc_tag = NULL;
1378 if (txq->ift_tso_desc_tag != NULL) {
1379 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1380 txq->ift_tso_desc_tag = NULL;
1385 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1389 mp = &txq->ift_sds.ifsd_m[i];
1393 if (txq->ift_sds.ifsd_map != NULL) {
1394 bus_dmamap_sync(txq->ift_desc_tag,
1395 txq->ift_sds.ifsd_map[i],
1396 BUS_DMASYNC_POSTWRITE);
1397 bus_dmamap_unload(txq->ift_desc_tag,
1398 txq->ift_sds.ifsd_map[i]);
1401 DBG_COUNTER_INC(tx_frees);
1406 iflib_txq_setup(iflib_txq_t txq)
1408 if_ctx_t ctx = txq->ift_ctx;
1409 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1410 iflib_dma_info_t di;
1413 /* Set number of descriptors available */
1414 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1417 txq->ift_cidx_processed = txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1418 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1420 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1421 bzero((void *)di->idi_vaddr, di->idi_size);
1423 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1424 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1425 bus_dmamap_sync(di->idi_tag, di->idi_map,
1426 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1430 /*********************************************************************
1432 * Allocate memory for rx_buffer structures. Since we use one
1433 * rx_buffer per received packet, the maximum number of rx_buffer's
1434 * that we'll need is equal to the number of receive descriptors
1435 * that we've allocated.
1437 **********************************************************************/
1439 iflib_rxsd_alloc(iflib_rxq_t rxq)
1441 if_ctx_t ctx = rxq->ifr_ctx;
1442 if_shared_ctx_t sctx = ctx->ifc_sctx;
1443 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1444 device_t dev = ctx->ifc_dev;
1449 MPASS(scctx->isc_nrxd[0] > 0);
1450 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1453 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1454 fl->ifl_sds = malloc(sizeof(struct iflib_sw_rx_desc) *
1455 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB,
1457 if (fl->ifl_sds == NULL) {
1458 device_printf(dev, "Unable to allocate rx sw desc memory\n");
1461 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1462 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1463 1, 0, /* alignment, bounds */
1464 BUS_SPACE_MAXADDR, /* lowaddr */
1465 BUS_SPACE_MAXADDR, /* highaddr */
1466 NULL, NULL, /* filter, filterarg */
1467 sctx->isc_rx_maxsize, /* maxsize */
1468 sctx->isc_rx_nsegments, /* nsegments */
1469 sctx->isc_rx_maxsegsize, /* maxsegsize */
1471 NULL, /* lockfunc */
1475 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1481 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++, rxsd++) {
1482 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &rxsd->ifsd_map);
1484 device_printf(dev, "%s: bus_dmamap_create failed: %d\n",
1493 iflib_rx_structures_free(ctx);
1499 * Internal service routines
1502 struct rxq_refill_cb_arg {
1504 bus_dma_segment_t seg;
1509 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1511 struct rxq_refill_cb_arg *cb_arg = arg;
1513 cb_arg->error = error;
1514 cb_arg->seg = segs[0];
1515 cb_arg->nseg = nseg;
1520 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1522 #define IS_DMAR(ctx) (0)
1526 * rxq_refill - refill an rxq free-buffer list
1527 * @ctx: the iflib context
1528 * @rxq: the free-list to refill
1529 * @n: the number of new buffers to allocate
1531 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1532 * The caller must assure that @n does not exceed the queue's capacity.
1535 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1538 int pidx = fl->ifl_pidx;
1539 iflib_rxsd_t rxsd = &fl->ifl_sds[pidx];
1547 MPASS(fl->ifl_credits + n <= fl->ifl_size);
1549 if (pidx < fl->ifl_cidx)
1550 MPASS(pidx + n <= fl->ifl_cidx);
1551 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size))
1552 MPASS(fl->ifl_gen == 0);
1553 if (pidx > fl->ifl_cidx)
1554 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1556 DBG_COUNTER_INC(fl_refills);
1558 DBG_COUNTER_INC(fl_refills_large);
1562 * We allocate an uninitialized mbuf + cluster, mbuf is
1563 * initialized after rx.
1565 * If the cluster is still set then we know a minimum sized packet was received
1567 if ((cl = rxsd->ifsd_cl) == NULL) {
1568 if ((cl = rxsd->ifsd_cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1571 fl->ifl_cl_enqueued++;
1574 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1578 fl->ifl_m_enqueued++;
1581 DBG_COUNTER_INC(rx_allocs);
1583 if ((rxsd->ifsd_flags & RX_SW_DESC_MAP_CREATED) == 0) {
1586 if ((err = bus_dmamap_create(fl->ifl_ifdi->idi_tag, 0, &rxsd->ifsd_map))) {
1587 log(LOG_WARNING, "bus_dmamap_create failed %d\n", err);
1588 uma_zfree(fl->ifl_zone, cl);
1592 rxsd->ifsd_flags |= RX_SW_DESC_MAP_CREATED;
1595 #if defined(__i386__) || defined(__amd64__)
1596 if (!IS_DMAR(ctx)) {
1597 bus_addr = pmap_kextract((vm_offset_t)cl);
1601 struct rxq_refill_cb_arg cb_arg;
1606 err = bus_dmamap_load(fl->ifl_desc_tag, rxsd->ifsd_map,
1607 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1609 if (err != 0 || cb_arg.error) {
1613 if (fl->ifl_zone == zone_pack)
1614 uma_zfree(fl->ifl_zone, cl);
1619 bus_addr = cb_arg.seg.ds_addr;
1621 rxsd->ifsd_flags |= RX_SW_DESC_INUSE;
1623 MPASS(rxsd->ifsd_m == NULL);
1626 fl->ifl_bus_addrs[i] = bus_addr;
1627 fl->ifl_vm_addrs[i] = cl;
1631 MPASS(fl->ifl_credits <= fl->ifl_size);
1632 if (++fl->ifl_pidx == fl->ifl_size) {
1637 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1638 ctx->isc_rxd_refill(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx,
1639 fl->ifl_bus_addrs, fl->ifl_vm_addrs, i, fl->ifl_buf_size);
1641 pidx = fl->ifl_pidx;
1645 DBG_COUNTER_INC(rxd_flush);
1646 if (fl->ifl_pidx == 0)
1647 pidx = fl->ifl_size - 1;
1649 pidx = fl->ifl_pidx - 1;
1650 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1653 static __inline void
1654 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1656 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1657 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1659 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1662 MPASS(fl->ifl_credits <= fl->ifl_size);
1663 MPASS(reclaimable == delta);
1665 if (reclaimable > 0)
1666 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1670 iflib_fl_bufs_free(iflib_fl_t fl)
1672 iflib_dma_info_t idi = fl->ifl_ifdi;
1675 for (i = 0; i < fl->ifl_size; i++) {
1676 iflib_rxsd_t d = &fl->ifl_sds[i];
1678 if (d->ifsd_flags & RX_SW_DESC_INUSE) {
1679 bus_dmamap_unload(fl->ifl_desc_tag, d->ifsd_map);
1680 bus_dmamap_destroy(fl->ifl_desc_tag, d->ifsd_map);
1681 if (d->ifsd_m != NULL) {
1682 m_init(d->ifsd_m, M_NOWAIT, MT_DATA, 0);
1683 uma_zfree(zone_mbuf, d->ifsd_m);
1685 if (d->ifsd_cl != NULL)
1686 uma_zfree(fl->ifl_zone, d->ifsd_cl);
1689 MPASS(d->ifsd_cl == NULL);
1690 MPASS(d->ifsd_m == NULL);
1693 fl->ifl_m_dequeued++;
1694 fl->ifl_cl_dequeued++;
1700 * Reset free list values
1702 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;;
1703 bzero(idi->idi_vaddr, idi->idi_size);
1706 /*********************************************************************
1708 * Initialize a receive ring and its buffers.
1710 **********************************************************************/
1712 iflib_fl_setup(iflib_fl_t fl)
1714 iflib_rxq_t rxq = fl->ifl_rxq;
1715 if_ctx_t ctx = rxq->ifr_ctx;
1716 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
1719 ** Free current RX buffer structs and their mbufs
1721 iflib_fl_bufs_free(fl);
1722 /* Now replenish the mbufs */
1723 MPASS(fl->ifl_credits == 0);
1725 * XXX don't set the max_frame_size to larger
1726 * than the hardware can handle
1728 if (sctx->isc_max_frame_size <= 2048)
1729 fl->ifl_buf_size = MCLBYTES;
1730 else if (sctx->isc_max_frame_size <= 4096)
1731 fl->ifl_buf_size = MJUMPAGESIZE;
1732 else if (sctx->isc_max_frame_size <= 9216)
1733 fl->ifl_buf_size = MJUM9BYTES;
1735 fl->ifl_buf_size = MJUM16BYTES;
1736 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
1737 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
1738 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
1739 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
1742 /* avoid pre-allocating zillions of clusters to an idle card
1743 * potentially speeding up attach
1745 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
1746 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
1747 if (min(128, fl->ifl_size) != fl->ifl_credits)
1753 MPASS(fl->ifl_ifdi != NULL);
1754 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1759 /*********************************************************************
1761 * Free receive ring data structures
1763 **********************************************************************/
1765 iflib_rx_sds_free(iflib_rxq_t rxq)
1770 if (rxq->ifr_fl != NULL) {
1771 for (i = 0; i < rxq->ifr_nfl; i++) {
1772 fl = &rxq->ifr_fl[i];
1773 if (fl->ifl_desc_tag != NULL) {
1774 bus_dma_tag_destroy(fl->ifl_desc_tag);
1775 fl->ifl_desc_tag = NULL;
1778 if (rxq->ifr_fl->ifl_sds != NULL)
1779 free(rxq->ifr_fl->ifl_sds, M_IFLIB);
1781 free(rxq->ifr_fl, M_IFLIB);
1783 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
1788 * MI independent logic
1792 iflib_timer(void *arg)
1794 iflib_txq_t txq = arg;
1795 if_ctx_t ctx = txq->ift_ctx;
1796 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1798 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
1801 ** Check on the state of the TX queue(s), this
1802 ** can be done without the lock because its RO
1803 ** and the HUNG state will be static if set.
1805 IFDI_TIMER(ctx, txq->ift_id);
1806 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
1807 (ctx->ifc_pause_frames == 0))
1810 if (TXQ_AVAIL(txq) <= 2*scctx->isc_tx_nsegments ||
1811 ifmp_ring_is_stalled(txq->ift_br[0]))
1812 GROUPTASK_ENQUEUE(&txq->ift_task);
1814 ctx->ifc_pause_frames = 0;
1815 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
1816 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
1820 if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING);
1821 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
1822 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
1824 IFDI_WATCHDOG_RESET(ctx);
1825 ctx->ifc_watchdog_events++;
1826 ctx->ifc_pause_frames = 0;
1828 iflib_init_locked(ctx);
1833 iflib_init_locked(if_ctx_t ctx)
1835 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
1836 if_t ifp = ctx->ifc_ifp;
1843 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
1844 IFDI_INTR_DISABLE(ctx);
1846 /* Set hardware offload abilities */
1847 if_clearhwassist(ifp);
1848 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
1849 if_sethwassistbits(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP, 0);
1850 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
1851 if_sethwassistbits(ifp, (CSUM_TCP_IPV6 | CSUM_UDP_IPV6), 0);
1852 if (if_getcapenable(ifp) & IFCAP_TSO4)
1853 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
1854 if (if_getcapenable(ifp) & IFCAP_TSO6)
1855 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
1857 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
1859 callout_stop(&txq->ift_timer);
1860 callout_stop(&txq->ift_db_check);
1861 CALLOUT_UNLOCK(txq);
1862 iflib_netmap_txq_init(ctx, txq);
1864 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
1865 iflib_netmap_rxq_init(ctx, rxq);
1868 i = if_getdrvflags(ifp);
1871 MPASS(if_getdrvflags(ifp) == i);
1872 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
1873 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
1874 if (iflib_fl_setup(fl)) {
1875 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
1881 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1882 IFDI_INTR_ENABLE(ctx);
1883 txq = ctx->ifc_txqs;
1884 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
1885 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
1886 txq->ift_timer.c_cpu);
1890 iflib_media_change(if_t ifp)
1892 if_ctx_t ctx = if_getsoftc(ifp);
1896 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
1897 iflib_init_locked(ctx);
1903 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
1905 if_ctx_t ctx = if_getsoftc(ifp);
1908 IFDI_UPDATE_ADMIN_STATUS(ctx);
1909 IFDI_MEDIA_STATUS(ctx, ifmr);
1914 iflib_stop(if_ctx_t ctx)
1916 iflib_txq_t txq = ctx->ifc_txqs;
1917 iflib_rxq_t rxq = ctx->ifc_rxqs;
1918 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1919 iflib_dma_info_t di;
1923 /* Tell the stack that the interface is no longer active */
1924 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
1926 IFDI_INTR_DISABLE(ctx);
1931 iflib_debug_reset();
1932 /* Wait for current tx queue users to exit to disarm watchdog timer. */
1933 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
1934 /* make sure all transmitters have completed before proceeding XXX */
1936 /* clean any enqueued buffers */
1937 iflib_ifmp_purge(txq);
1938 /* Free any existing tx buffers. */
1939 for (j = 0; j < txq->ift_size; j++) {
1940 iflib_txsd_free(ctx, txq, j);
1942 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
1943 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
1944 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
1945 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
1946 txq->ift_pullups = 0;
1947 ifmp_ring_reset_stats(txq->ift_br[0]);
1948 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
1949 bzero((void *)di->idi_vaddr, di->idi_size);
1951 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
1952 /* make sure all transmitters have completed before proceeding XXX */
1954 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
1955 bzero((void *)di->idi_vaddr, di->idi_size);
1956 /* also resets the free lists pidx/cidx */
1957 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
1958 iflib_fl_bufs_free(fl);
1963 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int *cltype, int unload)
1968 iflib_dma_info_t di;
1970 flid = irf->irf_flid;
1971 cidx = irf->irf_idx;
1972 fl = &rxq->ifr_fl[flid];
1975 fl->ifl_m_dequeued++;
1977 fl->ifl_cl_dequeued++;
1979 sd = &fl->ifl_sds[cidx];
1981 bus_dmamap_sync(di->idi_tag, di->idi_map,
1982 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1984 /* not valid assert if bxe really does SGE from non-contiguous elements */
1985 MPASS(fl->ifl_cidx == cidx);
1987 bus_dmamap_unload(fl->ifl_desc_tag, sd->ifsd_map);
1989 if (__predict_false(++fl->ifl_cidx == fl->ifl_size)) {
1995 *cltype = fl->ifl_cltype;
1999 static struct mbuf *
2000 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri)
2002 int i, padlen , flags, cltype;
2003 struct mbuf *m, *mh, *mt;
2010 sd = rxd_frag_to_sd(rxq, &ri->iri_frags[i], &cltype, TRUE);
2012 MPASS(sd->ifsd_cl != NULL);
2013 MPASS(sd->ifsd_m != NULL);
2015 /* Don't include zero-length frags */
2016 if (ri->iri_frags[i].irf_len == 0) {
2017 /* XXX we can save the cluster here, but not the mbuf */
2018 m_init(sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2026 flags = M_PKTHDR|M_EXT;
2028 padlen = ri->iri_pad;
2033 /* assuming padding is only on the first fragment */
2040 /* Can these two be made one ? */
2041 m_init(m, M_NOWAIT, MT_DATA, flags);
2042 m_cljset(m, cl, cltype);
2044 * These must follow m_init and m_cljset
2046 m->m_data += padlen;
2047 ri->iri_len -= padlen;
2048 m->m_len = ri->iri_frags[i].irf_len;
2049 } while (++i < ri->iri_nfrags);
2055 * Process one software descriptor
2057 static struct mbuf *
2058 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2063 /* should I merge this back in now that the two paths are basically duplicated? */
2064 if (ri->iri_nfrags == 1 &&
2065 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2066 sd = rxd_frag_to_sd(rxq, &ri->iri_frags[0], NULL, FALSE);
2069 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2070 memcpy(m->m_data, sd->ifsd_cl, ri->iri_len);
2071 m->m_len = ri->iri_frags[0].irf_len;
2073 m = assemble_segments(rxq, ri);
2075 m->m_pkthdr.len = ri->iri_len;
2076 m->m_pkthdr.rcvif = ri->iri_ifp;
2077 m->m_flags |= ri->iri_flags;
2078 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2079 m->m_pkthdr.flowid = ri->iri_flowid;
2080 M_HASHTYPE_SET(m, ri->iri_rsstype);
2081 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2082 m->m_pkthdr.csum_data = ri->iri_csum_data;
2087 iflib_rxeof(iflib_rxq_t rxq, int budget)
2089 if_ctx_t ctx = rxq->ifr_ctx;
2090 if_shared_ctx_t sctx = ctx->ifc_sctx;
2091 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2094 struct if_rxd_info ri;
2095 int err, budget_left, rx_bytes, rx_pkts;
2100 * XXX early demux data packets so that if_input processing only handles
2101 * acks in interrupt context
2103 struct mbuf *m, *mh, *mt;
2105 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &budget)) {
2111 rx_pkts = rx_bytes = 0;
2112 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2113 cidxp = &rxq->ifr_cq_cidx;
2115 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2116 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2117 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2118 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2119 DBG_COUNTER_INC(rx_unavail);
2123 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2124 if (__predict_false(!CTX_ACTIVE(ctx))) {
2125 DBG_COUNTER_INC(rx_ctx_inactive);
2129 * Reset client set fields to their default values
2131 bzero(&ri, sizeof(ri));
2132 ri.iri_qsidx = rxq->ifr_id;
2133 ri.iri_cidx = *cidxp;
2134 ri.iri_ifp = ctx->ifc_ifp;
2135 ri.iri_frags = rxq->ifr_frags;
2136 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2138 /* in lieu of handling correctly - make sure it isn't being unhandled */
2140 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2141 *cidxp = ri.iri_cidx;
2142 /* Update our consumer index */
2143 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2144 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2145 rxq->ifr_cq_gen = 0;
2147 /* was this only a completion queue message? */
2148 if (__predict_false(ri.iri_nfrags == 0))
2151 MPASS(ri.iri_nfrags != 0);
2152 MPASS(ri.iri_len != 0);
2154 /* will advance the cidx on the corresponding free lists */
2155 m = iflib_rxd_pkt_get(rxq, &ri);
2156 if (avail == 0 && budget_left)
2157 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2159 if (__predict_false(m == NULL)) {
2160 DBG_COUNTER_INC(rx_mbuf_null);
2163 /* imm_pkt: -- cxgb */
2171 /* make sure that we can refill faster than drain */
2172 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2173 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2176 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2177 while (mh != NULL) {
2180 m->m_nextpkt = NULL;
2181 rx_bytes += m->m_pkthdr.len;
2183 #if defined(INET6) || defined(INET)
2184 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2187 DBG_COUNTER_INC(rx_if_input);
2188 ifp->if_input(ifp, m);
2191 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2192 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2195 * Flush any outstanding LRO work
2197 #if defined(INET6) || defined(INET)
2198 tcp_lro_flush_all(&rxq->ifr_lc);
2202 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2205 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2206 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2207 #define TXQ_MAX_DB_DEFERRED(size) (size >> 5)
2208 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2210 static __inline void
2211 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring)
2215 if (ring || txq->ift_db_pending >=
2216 TXQ_MAX_DB_DEFERRED(txq->ift_size)) {
2218 /* the lock will only ever be contended in the !min_latency case */
2219 if (!TXDB_TRYLOCK(txq))
2221 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2222 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2223 txq->ift_db_pending = txq->ift_npending = 0;
2229 iflib_txd_deferred_db_check(void * arg)
2231 iflib_txq_t txq = arg;
2233 /* simple non-zero boolean so use bitwise OR */
2234 if ((txq->ift_db_pending | txq->ift_npending) &&
2235 txq->ift_db_pending >= txq->ift_db_pending_queued)
2236 iflib_txd_db_check(txq->ift_ctx, txq, TRUE);
2237 txq->ift_db_pending_queued = 0;
2238 if (ifmp_ring_is_stalled(txq->ift_br[0]))
2239 iflib_txq_check_drain(txq, 4);
2244 print_pkt(if_pkt_info_t pi)
2246 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2247 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2248 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2249 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2250 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2251 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2255 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2256 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2259 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2261 struct ether_vlan_header *eh;
2266 * Determine where frame payload starts.
2267 * Jump over vlan headers if already present,
2268 * helpful for QinQ too.
2270 if (__predict_false(m->m_len < sizeof(*eh))) {
2272 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2275 eh = mtod(m, struct ether_vlan_header *);
2276 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2277 pi->ipi_etype = ntohs(eh->evl_proto);
2278 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2280 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2281 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2284 switch (pi->ipi_etype) {
2288 struct ip *ip = NULL;
2289 struct tcphdr *th = NULL;
2292 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2293 if (__predict_false(m->m_len < minthlen)) {
2295 * if this code bloat is causing too much of a hit
2296 * move it to a separate function and mark it noinline
2298 if (m->m_len == pi->ipi_ehdrlen) {
2301 if (n->m_len >= sizeof(*ip)) {
2302 ip = (struct ip *)n->m_data;
2303 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2304 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2307 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2309 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2313 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2315 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2316 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2317 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2320 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2321 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2322 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2324 pi->ipi_ip_hlen = ip->ip_hl << 2;
2325 pi->ipi_ipproto = ip->ip_p;
2326 pi->ipi_flags |= IPI_TX_IPV4;
2328 if (pi->ipi_csum_flags & CSUM_IP)
2331 if (pi->ipi_ipproto == IPPROTO_TCP) {
2332 if (__predict_false(th == NULL)) {
2334 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2336 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2338 pi->ipi_tcp_hflags = th->th_flags;
2339 pi->ipi_tcp_hlen = th->th_off << 2;
2340 pi->ipi_tcp_seq = th->th_seq;
2343 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2345 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2346 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2347 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2353 case ETHERTYPE_IPV6:
2355 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2357 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2359 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2360 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2363 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2365 /* XXX-BZ this will go badly in case of ext hdrs. */
2366 pi->ipi_ipproto = ip6->ip6_nxt;
2367 pi->ipi_flags |= IPI_TX_IPV6;
2369 if (pi->ipi_ipproto == IPPROTO_TCP) {
2370 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2371 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2374 pi->ipi_tcp_hflags = th->th_flags;
2375 pi->ipi_tcp_hlen = th->th_off << 2;
2379 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2382 * The corresponding flag is set by the stack in the IPv4
2383 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2384 * So, set it here because the rest of the flow requires it.
2386 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2387 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2388 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2394 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2395 pi->ipi_ip_hlen = 0;
2403 static __noinline struct mbuf *
2404 collapse_pkthdr(struct mbuf *m0)
2406 struct mbuf *m, *m_next, *tmp;
2410 while (m_next != NULL && m_next->m_len == 0) {
2414 m_next = m_next->m_next;
2418 if ((m_next->m_flags & M_EXT) == 0) {
2419 m = m_defrag(m, M_NOWAIT);
2421 tmp = m_next->m_next;
2422 memcpy(m_next, m, MPKTHSIZE);
2430 * If dodgy hardware rejects the scatter gather chain we've handed it
2431 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2434 static __noinline struct mbuf *
2435 iflib_remove_mbuf(iflib_txq_t txq)
2438 struct mbuf *m, *mh, **ifsd_m;
2440 pidx = txq->ift_pidx;
2441 ifsd_m = txq->ift_sds.ifsd_m;
2442 ntxd = txq->ift_size;
2443 mh = m = ifsd_m[pidx];
2444 ifsd_m[pidx] = NULL;
2446 txq->ift_dequeued++;
2451 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2453 txq->ift_dequeued++;
2462 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2463 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2464 int max_segs, int flags)
2467 if_shared_ctx_t sctx;
2468 if_softc_ctx_t scctx;
2469 int i, next, pidx, mask, err, maxsegsz, ntxd, count;
2470 struct mbuf *m, *tmp, **ifsd_m, **mp;
2475 * Please don't ever do this
2477 if (__predict_false(m->m_len == 0))
2478 *m0 = m = collapse_pkthdr(m);
2481 sctx = ctx->ifc_sctx;
2482 scctx = &ctx->ifc_softc_ctx;
2483 ifsd_m = txq->ift_sds.ifsd_m;
2484 ntxd = txq->ift_size;
2485 pidx = txq->ift_pidx;
2487 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2489 err = bus_dmamap_load_mbuf_sg(tag, map,
2490 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2493 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
2496 mask = (txq->ift_size-1);
2502 if (__predict_false((*mp)->m_len == 0)) {
2506 next = (pidx + i) & (ntxd-1);
2507 } while (m != NULL);
2509 int buflen, sgsize, max_sgsize;
2514 maxsegsz = sctx->isc_tx_maxsize;
2517 if (__predict_false(m->m_len <= 0)) {
2525 vaddr = (vm_offset_t)m->m_data;
2527 * see if we can't be smarter about physically
2528 * contiguous mappings
2530 next = (pidx + count) & (ntxd-1);
2531 MPASS(ifsd_m[next] == NULL);
2533 txq->ift_enqueued++;
2536 while (buflen > 0) {
2537 max_sgsize = MIN(buflen, maxsegsz);
2538 curaddr = pmap_kextract(vaddr);
2539 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
2540 sgsize = MIN(sgsize, max_sgsize);
2541 segs[i].ds_addr = curaddr;
2542 segs[i].ds_len = sgsize;
2552 } while (m != NULL);
2557 *m0 = iflib_remove_mbuf(txq);
2562 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
2565 if_shared_ctx_t sctx;
2566 if_softc_ctx_t scctx;
2567 bus_dma_segment_t *segs;
2568 struct mbuf *m_head;
2570 struct if_pkt_info pi;
2572 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
2573 bus_dma_tag_t desc_tag;
2575 segs = txq->ift_segs;
2577 sctx = ctx->ifc_sctx;
2578 scctx = &ctx->ifc_softc_ctx;
2579 segs = txq->ift_segs;
2580 ntxd = txq->ift_size;
2585 * If we're doing TSO the next descriptor to clean may be quite far ahead
2587 cidx = txq->ift_cidx;
2588 pidx = txq->ift_pidx;
2589 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
2591 /* prefetch the next cache line of mbuf pointers and flags */
2592 prefetch(&txq->ift_sds.ifsd_m[next]);
2593 if (txq->ift_sds.ifsd_map != NULL) {
2594 prefetch(&txq->ift_sds.ifsd_map[next]);
2595 map = txq->ift_sds.ifsd_map[pidx];
2596 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
2597 prefetch(&txq->ift_sds.ifsd_flags[next]);
2601 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2602 desc_tag = txq->ift_tso_desc_tag;
2603 max_segs = scctx->isc_tx_tso_segments_max;
2605 desc_tag = txq->ift_desc_tag;
2606 max_segs = scctx->isc_tx_nsegments;
2609 bzero(&pi, sizeof(pi));
2610 pi.ipi_len = m_head->m_pkthdr.len;
2611 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
2612 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
2613 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
2615 pi.ipi_qsidx = txq->ift_id;
2617 /* deliberate bitwise OR to make one condition */
2618 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
2619 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
2625 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
2627 if (__predict_false(err)) {
2630 /* try collapse once and defrag once */
2632 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
2634 m_head = m_defrag(*m_headp, M_NOWAIT);
2636 if (__predict_false(m_head == NULL))
2638 txq->ift_mbuf_defrag++;
2643 txq->ift_no_tx_dma_setup++;
2646 txq->ift_no_tx_dma_setup++;
2648 DBG_COUNTER_INC(tx_frees);
2652 txq->ift_map_failed++;
2653 DBG_COUNTER_INC(encap_load_mbuf_fail);
2658 * XXX assumes a 1 to 1 relationship between segments and
2659 * descriptors - this does not hold true on all drivers, e.g.
2662 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
2663 txq->ift_no_desc_avail++;
2665 bus_dmamap_unload(desc_tag, map);
2666 DBG_COUNTER_INC(encap_txq_avail_fail);
2667 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
2668 GROUPTASK_ENQUEUE(&txq->ift_task);
2672 pi.ipi_nsegs = nsegs;
2674 MPASS(pidx >= 0 && pidx < txq->ift_size);
2678 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
2679 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2682 DBG_COUNTER_INC(tx_encap);
2683 MPASS(pi.ipi_new_pidx >= 0 &&
2684 pi.ipi_new_pidx < txq->ift_size);
2686 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
2687 if (pi.ipi_new_pidx < pi.ipi_pidx) {
2688 ndesc += txq->ift_size;
2691 MPASS(pi.ipi_new_pidx != pidx);
2693 txq->ift_in_use += ndesc;
2695 * We update the last software descriptor again here because there may
2696 * be a sentinel and/or there may be more mbufs than segments
2698 txq->ift_pidx = pi.ipi_new_pidx;
2699 txq->ift_npending += pi.ipi_ndescs;
2700 } else if (__predict_false(err == EFBIG && remap < 2)) {
2701 *m_headp = m_head = iflib_remove_mbuf(txq);
2703 txq->ift_txd_encap_efbig++;
2706 DBG_COUNTER_INC(encap_txd_encap_fail);
2710 txq->ift_mbuf_defrag_failed++;
2711 txq->ift_map_failed++;
2713 DBG_COUNTER_INC(tx_frees);
2718 /* forward compatibility for cxgb */
2719 #define FIRST_QSET(ctx) 0
2721 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2722 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2723 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2724 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2725 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2726 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2730 /* if there are more than TXQ_MIN_OCCUPANCY packets pending we consider deferring
2733 * ORing with 2 assures that min occupancy is never less than 2 without any conditional logic
2735 #define TXQ_MIN_OCCUPANCY(size) ((size >> 6)| 0x2)
2738 iflib_txq_min_occupancy(iflib_txq_t txq)
2743 return (get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx,
2744 txq->ift_gen) < TXQ_MIN_OCCUPANCY(txq->ift_size) +
2749 iflib_tx_desc_free(iflib_txq_t txq, int n)
2752 uint32_t qsize, cidx, mask, gen;
2753 struct mbuf *m, **ifsd_m;
2754 uint8_t *ifsd_flags;
2755 bus_dmamap_t *ifsd_map;
2757 cidx = txq->ift_cidx;
2759 qsize = txq->ift_size;
2761 hasmap = txq->ift_sds.ifsd_map != NULL;
2762 ifsd_flags = txq->ift_sds.ifsd_flags;
2763 ifsd_m = txq->ift_sds.ifsd_m;
2764 ifsd_map = txq->ift_sds.ifsd_map;
2767 prefetch(ifsd_m[(cidx + 3) & mask]);
2768 prefetch(ifsd_m[(cidx + 4) & mask]);
2770 if (ifsd_m[cidx] != NULL) {
2771 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
2772 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
2773 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
2775 * does it matter if it's not the TSO tag? If so we'll
2776 * have to add the type to flags
2778 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
2779 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
2781 if ((m = ifsd_m[cidx]) != NULL) {
2782 /* XXX we don't support any drivers that batch packets yet */
2783 MPASS(m->m_nextpkt == NULL);
2786 ifsd_m[cidx] = NULL;
2788 txq->ift_dequeued++;
2790 DBG_COUNTER_INC(tx_frees);
2793 if (__predict_false(++cidx == qsize)) {
2798 txq->ift_cidx = cidx;
2803 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
2806 if_ctx_t ctx = txq->ift_ctx;
2808 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
2809 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
2812 * Need a rate-limiting check so that this isn't called every time
2814 iflib_tx_credits_update(ctx, txq);
2815 reclaim = DESC_RECLAIMABLE(txq);
2817 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
2819 if (iflib_verbose_debug) {
2820 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
2821 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
2828 iflib_tx_desc_free(txq, reclaim);
2829 txq->ift_cleaned += reclaim;
2830 txq->ift_in_use -= reclaim;
2832 if (txq->ift_active == FALSE)
2833 txq->ift_active = TRUE;
2838 static struct mbuf **
2839 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset)
2842 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (r->size-1)]));
2846 iflib_txq_check_drain(iflib_txq_t txq, int budget)
2849 ifmp_ring_check_drainage(txq->ift_br[0], budget);
2853 iflib_txq_can_drain(struct ifmp_ring *r)
2855 iflib_txq_t txq = r->cookie;
2856 if_ctx_t ctx = txq->ift_ctx;
2858 return ((TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx)) ||
2859 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, false));
2863 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
2865 iflib_txq_t txq = r->cookie;
2866 if_ctx_t ctx = txq->ift_ctx;
2867 if_t ifp = ctx->ifc_ifp;
2868 struct mbuf **mp, *m;
2869 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail, err, in_use_prev, desc_used;
2871 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
2872 !LINK_ACTIVE(ctx))) {
2873 DBG_COUNTER_INC(txq_drain_notready);
2877 avail = IDXDIFF(pidx, cidx, r->size);
2878 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
2879 DBG_COUNTER_INC(txq_drain_flushing);
2880 for (i = 0; i < avail; i++) {
2881 m_free(r->items[(cidx + i) & (r->size-1)]);
2882 r->items[(cidx + i) & (r->size-1)] = NULL;
2886 iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
2887 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
2888 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
2890 callout_stop(&txq->ift_timer);
2891 callout_stop(&txq->ift_db_check);
2892 CALLOUT_UNLOCK(txq);
2893 DBG_COUNTER_INC(txq_drain_oactive);
2896 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
2897 count = MIN(avail, TX_BATCH_SIZE);
2899 if (iflib_verbose_debug)
2900 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
2901 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
2904 for (desc_used = i = 0; i < count && TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2; i++) {
2905 mp = _ring_peek_one(r, cidx, i);
2906 MPASS(mp != NULL && *mp != NULL);
2907 in_use_prev = txq->ift_in_use;
2908 if ((err = iflib_encap(txq, mp)) == ENOBUFS) {
2909 DBG_COUNTER_INC(txq_drain_encapfail);
2910 /* no room - bail out */
2915 DBG_COUNTER_INC(txq_drain_encapfail);
2916 /* we can't send this packet - skip it */
2921 DBG_COUNTER_INC(tx_sent);
2922 bytes_sent += m->m_pkthdr.len;
2923 if (m->m_flags & M_MCAST)
2926 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
2927 desc_used += (txq->ift_in_use - in_use_prev);
2928 iflib_txd_db_check(ctx, txq, FALSE);
2929 ETHER_BPF_MTAP(ifp, m);
2930 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
2933 if (desc_used > TXQ_MAX_DB_CONSUMED(txq->ift_size))
2937 if ((iflib_min_tx_latency || iflib_txq_min_occupancy(txq)) && txq->ift_db_pending)
2938 iflib_txd_db_check(ctx, txq, TRUE);
2939 else if ((txq->ift_db_pending || TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)) &&
2940 (callout_pending(&txq->ift_db_check) == 0)) {
2941 txq->ift_db_pending_queued = txq->ift_db_pending;
2942 callout_reset_on(&txq->ift_db_check, 1, iflib_txd_deferred_db_check,
2943 txq, txq->ift_db_check.c_cpu);
2945 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
2946 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
2948 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
2950 if (iflib_verbose_debug)
2951 printf("consumed=%d\n", consumed);
2957 iflib_txq_drain_always(struct ifmp_ring *r)
2963 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
2971 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
2973 callout_stop(&txq->ift_timer);
2974 callout_stop(&txq->ift_db_check);
2975 CALLOUT_UNLOCK(txq);
2977 avail = IDXDIFF(pidx, cidx, r->size);
2978 for (i = 0; i < avail; i++) {
2979 mp = _ring_peek_one(r, cidx, i);
2982 MPASS(ifmp_ring_is_stalled(r) == 0);
2987 iflib_ifmp_purge(iflib_txq_t txq)
2989 struct ifmp_ring *r;
2992 r->drain = iflib_txq_drain_free;
2993 r->can_drain = iflib_txq_drain_always;
2995 ifmp_ring_check_drainage(r, r->size);
2997 r->drain = iflib_txq_drain;
2998 r->can_drain = iflib_txq_can_drain;
3002 _task_fn_tx(void *context)
3004 iflib_txq_t txq = context;
3005 if_ctx_t ctx = txq->ift_ctx;
3007 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3009 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE);
3013 _task_fn_rx(void *context)
3015 iflib_rxq_t rxq = context;
3016 if_ctx_t ctx = rxq->ifr_ctx;
3020 DBG_COUNTER_INC(task_fn_rxs);
3021 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3024 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) {
3025 if (ctx->ifc_flags & IFC_LEGACY)
3026 IFDI_INTR_ENABLE(ctx);
3028 DBG_COUNTER_INC(rx_intr_enables);
3029 rc = IFDI_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3030 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3033 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3036 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3040 _task_fn_admin(void *context)
3042 if_ctx_t ctx = context;
3043 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3047 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3051 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3053 callout_stop(&txq->ift_timer);
3054 CALLOUT_UNLOCK(txq);
3056 IFDI_UPDATE_ADMIN_STATUS(ctx);
3057 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3058 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3059 IFDI_LINK_INTR_ENABLE(ctx);
3062 if (LINK_ACTIVE(ctx) == 0)
3064 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3065 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3070 _task_fn_iov(void *context)
3072 if_ctx_t ctx = context;
3074 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3078 IFDI_VFLR_HANDLE(ctx);
3083 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3086 if_int_delay_info_t info;
3089 info = (if_int_delay_info_t)arg1;
3090 ctx = info->iidi_ctx;
3091 info->iidi_req = req;
3092 info->iidi_oidp = oidp;
3094 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3099 /*********************************************************************
3103 **********************************************************************/
3106 iflib_if_init_locked(if_ctx_t ctx)
3109 iflib_init_locked(ctx);
3114 iflib_if_init(void *arg)
3119 iflib_if_init_locked(ctx);
3124 iflib_if_transmit(if_t ifp, struct mbuf *m)
3126 if_ctx_t ctx = if_getsoftc(ifp);
3131 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3132 DBG_COUNTER_INC(tx_frees);
3137 MPASS(m->m_nextpkt == NULL);
3139 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3140 qidx = QIDX(ctx, m);
3142 * XXX calculate buf_ring based on flowid (divvy up bits?)
3144 txq = &ctx->ifc_txqs[qidx];
3146 #ifdef DRIVER_BACKPRESSURE
3147 if (txq->ift_closed) {
3149 next = m->m_nextpkt;
3150 m->m_nextpkt = NULL;
3163 next = next->m_nextpkt;
3164 } while (next != NULL);
3166 if (count > nitems(marr))
3167 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3168 /* XXX check nextpkt */
3170 /* XXX simplify for now */
3171 DBG_COUNTER_INC(tx_frees);
3174 for (next = m, i = 0; next != NULL; i++) {
3176 next = next->m_nextpkt;
3177 mp[i]->m_nextpkt = NULL;
3180 DBG_COUNTER_INC(tx_seen);
3181 err = ifmp_ring_enqueue(txq->ift_br[0], (void **)&m, 1, TX_BATCH_SIZE);
3184 GROUPTASK_ENQUEUE(&txq->ift_task);
3185 /* support forthcoming later */
3186 #ifdef DRIVER_BACKPRESSURE
3187 txq->ift_closed = TRUE;
3189 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE);
3191 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) {
3192 GROUPTASK_ENQUEUE(&txq->ift_task);
3199 iflib_if_qflush(if_t ifp)
3201 if_ctx_t ctx = if_getsoftc(ifp);
3202 iflib_txq_t txq = ctx->ifc_txqs;
3206 ctx->ifc_flags |= IFC_QFLUSH;
3208 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3209 while (!(ifmp_ring_is_idle(txq->ift_br[0]) || ifmp_ring_is_stalled(txq->ift_br[0])))
3210 iflib_txq_check_drain(txq, 0);
3212 ctx->ifc_flags &= ~IFC_QFLUSH;
3219 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3220 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \
3221 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3224 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3226 if_ctx_t ctx = if_getsoftc(ifp);
3227 struct ifreq *ifr = (struct ifreq *)data;
3228 #if defined(INET) || defined(INET6)
3229 struct ifaddr *ifa = (struct ifaddr *)data;
3231 bool avoid_reset = FALSE;
3232 int err = 0, reinit = 0, bits;
3237 if (ifa->ifa_addr->sa_family == AF_INET)
3241 if (ifa->ifa_addr->sa_family == AF_INET6)
3245 ** Calling init results in link renegotiation,
3246 ** so we avoid doing it when possible.
3249 if_setflagbits(ifp, IFF_UP,0);
3250 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3253 if (!(if_getflags(ifp) & IFF_NOARP))
3254 arp_ifinit(ifp, ifa);
3257 err = ether_ioctl(ifp, command, data);
3261 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3265 bits = if_getdrvflags(ifp);
3266 /* stop the driver and free any clusters before proceeding */
3269 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3270 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3271 ctx->ifc_flags |= IFC_MULTISEG;
3273 ctx->ifc_flags &= ~IFC_MULTISEG;
3274 err = if_setmtu(ifp, ifr->ifr_mtu);
3276 iflib_init_locked(ctx);
3277 if_setdrvflags(ifp, bits);
3282 if (if_getflags(ifp) & IFF_UP) {
3283 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3284 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3285 (IFF_PROMISC | IFF_ALLMULTI)) {
3286 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3290 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3293 ctx->ifc_if_flags = if_getflags(ifp);
3300 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3302 IFDI_INTR_DISABLE(ctx);
3303 IFDI_MULTI_SET(ctx);
3304 IFDI_INTR_ENABLE(ctx);
3310 IFDI_MEDIA_SET(ctx);
3314 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3318 struct ifi2creq i2c;
3320 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3323 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3327 if (i2c.len > sizeof(i2c.data)) {
3332 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3333 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3340 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3343 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3345 setmask |= (mask & IFCAP_FLAGS);
3347 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
3348 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
3349 if ((mask & IFCAP_WOL) &&
3350 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3351 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3354 * want to ensure that traffic has stopped before we change any of the flags
3358 bits = if_getdrvflags(ifp);
3359 if (bits & IFF_DRV_RUNNING)
3361 if_togglecapenable(ifp, setmask);
3362 if (bits & IFF_DRV_RUNNING)
3363 iflib_init_locked(ctx);
3364 if_setdrvflags(ifp, bits);
3369 case SIOCGPRIVATE_0:
3373 err = IFDI_PRIV_IOCTL(ctx, command, data);
3377 err = ether_ioctl(ifp, command, data);
3386 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3388 if_ctx_t ctx = if_getsoftc(ifp);
3390 return (IFDI_GET_COUNTER(ctx, cnt));
3393 /*********************************************************************
3395 * OTHER FUNCTIONS EXPORTED TO THE STACK
3397 **********************************************************************/
3400 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
3402 if_ctx_t ctx = if_getsoftc(ifp);
3404 if ((void *)ctx != arg)
3407 if ((vtag == 0) || (vtag > 4095))
3411 IFDI_VLAN_REGISTER(ctx, vtag);
3412 /* Re-init to load the changes */
3413 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3414 iflib_init_locked(ctx);
3419 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
3421 if_ctx_t ctx = if_getsoftc(ifp);
3423 if ((void *)ctx != arg)
3426 if ((vtag == 0) || (vtag > 4095))
3430 IFDI_VLAN_UNREGISTER(ctx, vtag);
3431 /* Re-init to load the changes */
3432 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3433 iflib_init_locked(ctx);
3438 iflib_led_func(void *arg, int onoff)
3443 IFDI_LED_FUNC(ctx, onoff);
3447 /*********************************************************************
3449 * BUS FUNCTION DEFINITIONS
3451 **********************************************************************/
3454 iflib_device_probe(device_t dev)
3456 pci_vendor_info_t *ent;
3458 uint16_t pci_vendor_id, pci_device_id;
3459 uint16_t pci_subvendor_id, pci_subdevice_id;
3460 uint16_t pci_rev_id;
3461 if_shared_ctx_t sctx;
3463 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3466 pci_vendor_id = pci_get_vendor(dev);
3467 pci_device_id = pci_get_device(dev);
3468 pci_subvendor_id = pci_get_subvendor(dev);
3469 pci_subdevice_id = pci_get_subdevice(dev);
3470 pci_rev_id = pci_get_revid(dev);
3471 if (sctx->isc_parse_devinfo != NULL)
3472 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
3474 ent = sctx->isc_vendor_info;
3475 while (ent->pvi_vendor_id != 0) {
3476 if (pci_vendor_id != ent->pvi_vendor_id) {
3480 if ((pci_device_id == ent->pvi_device_id) &&
3481 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
3482 (ent->pvi_subvendor_id == 0)) &&
3483 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
3484 (ent->pvi_subdevice_id == 0)) &&
3485 ((pci_rev_id == ent->pvi_rev_id) ||
3486 (ent->pvi_rev_id == 0))) {
3488 device_set_desc_copy(dev, ent->pvi_name);
3489 /* this needs to be changed to zero if the bus probing code
3490 * ever stops re-probing on best match because the sctx
3491 * may have its values over written by register calls
3492 * in subsequent probes
3494 return (BUS_PROBE_DEFAULT);
3502 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
3504 int err, rid, msix, msix_bar;
3507 if_softc_ctx_t scctx;
3513 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
3516 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
3517 device_set_softc(dev, ctx);
3518 ctx->ifc_flags |= IFC_SC_ALLOCATED;
3521 ctx->ifc_sctx = sctx;
3523 ctx->ifc_txrx = *sctx->isc_txrx;
3524 ctx->ifc_softc = sc;
3526 if ((err = iflib_register(ctx)) != 0) {
3527 device_printf(dev, "iflib_register failed %d\n", err);
3530 iflib_add_device_sysctl_pre(ctx);
3532 scctx = &ctx->ifc_softc_ctx;
3534 * XXX sanity check that ntxd & nrxd are a power of 2
3536 if (ctx->ifc_sysctl_ntxqs != 0)
3537 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
3538 if (ctx->ifc_sysctl_nrxqs != 0)
3539 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
3541 for (i = 0; i < sctx->isc_ntxqs; i++) {
3542 if (ctx->ifc_sysctl_ntxds[i] != 0)
3543 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
3545 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
3548 for (i = 0; i < sctx->isc_nrxqs; i++) {
3549 if (ctx->ifc_sysctl_nrxds[i] != 0)
3550 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
3552 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
3555 for (i = 0; i < sctx->isc_nrxqs; i++) {
3556 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
3557 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
3558 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
3559 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
3561 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
3562 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
3563 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
3564 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
3568 for (i = 0; i < sctx->isc_ntxqs; i++) {
3569 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
3570 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
3571 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
3572 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
3574 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
3575 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
3576 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
3577 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
3581 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
3582 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
3585 if (scctx->isc_ntxqsets_max)
3586 scctx->isc_ntxqsets = min(scctx->isc_ntxqsets, scctx->isc_ntxqsets_max);
3587 if (scctx->isc_nrxqsets_max)
3588 scctx->isc_nrxqsets = min(scctx->isc_nrxqsets, scctx->isc_nrxqsets_max);
3591 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
3592 ctx->ifc_flags |= IFC_DMAR;
3595 msix_bar = scctx->isc_msix_bar;
3599 if(sctx->isc_flags & IFLIB_HAS_TXCQ)
3604 if(sctx->isc_flags & IFLIB_HAS_RXCQ)
3609 /* XXX change for per-queue sizes */
3610 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
3611 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
3612 for (i = 0; i < sctx->isc_nrxqs; i++) {
3613 if (!powerof2(scctx->isc_nrxd[i])) {
3614 /* round down instead? */
3615 device_printf(dev, "# rx descriptors must be a power of 2\n");
3620 for (i = 0; i < sctx->isc_ntxqs; i++) {
3621 if (!powerof2(scctx->isc_ntxd[i])) {
3623 "# tx descriptors must be a power of 2");
3629 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
3630 MAX_SINGLE_PACKET_FRACTION)
3631 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
3632 MAX_SINGLE_PACKET_FRACTION);
3633 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
3634 MAX_SINGLE_PACKET_FRACTION)
3635 scctx->isc_tx_tso_segments_max = max(1,
3636 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
3639 * Protect the stack against modern hardware
3641 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
3642 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
3644 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
3645 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
3646 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
3647 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
3648 if (scctx->isc_rss_table_size == 0)
3649 scctx->isc_rss_table_size = 64;
3650 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
3652 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
3653 /* XXX format name */
3654 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
3656 ** Now setup MSI or MSI/X, should
3657 ** return us the number of supported
3658 ** vectors. (Will be 1 for MSI)
3660 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
3661 msix = scctx->isc_vectors;
3662 } else if (scctx->isc_msix_bar != 0)
3663 msix = iflib_msix_init(ctx);
3665 scctx->isc_vectors = 1;
3666 scctx->isc_ntxqsets = 1;
3667 scctx->isc_nrxqsets = 1;
3668 scctx->isc_intr = IFLIB_INTR_LEGACY;
3671 /* Get memory for the station queues */
3672 if ((err = iflib_queues_alloc(ctx))) {
3673 device_printf(dev, "Unable to allocate queue memory\n");
3677 if ((err = iflib_qset_structures_setup(ctx))) {
3678 device_printf(dev, "qset structure setup failed %d\n", err);
3682 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
3683 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
3684 goto fail_intr_free;
3688 if (scctx->isc_intr == IFLIB_INTR_MSI) {
3692 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
3693 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
3694 goto fail_intr_free;
3697 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
3698 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
3699 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
3702 if ((err = iflib_netmap_attach(ctx))) {
3703 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
3708 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
3709 iflib_add_device_sysctl_post(ctx);
3712 ether_ifdetach(ctx->ifc_ifp);
3714 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
3715 pci_release_msi(ctx->ifc_dev);
3717 /* XXX free queues */
3724 iflib_device_attach(device_t dev)
3727 if_shared_ctx_t sctx;
3729 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3732 pci_enable_busmaster(dev);
3734 return (iflib_device_register(dev, NULL, sctx, &ctx));
3738 iflib_device_deregister(if_ctx_t ctx)
3740 if_t ifp = ctx->ifc_ifp;
3743 device_t dev = ctx->ifc_dev;
3745 struct taskqgroup *tqg;
3747 /* Make sure VLANS are not using driver */
3748 if (if_vlantrunkinuse(ifp)) {
3749 device_printf(dev,"Vlan in use, detach first\n");
3754 ctx->ifc_in_detach = 1;
3758 /* Unregister VLAN events */
3759 if (ctx->ifc_vlan_attach_event != NULL)
3760 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
3761 if (ctx->ifc_vlan_detach_event != NULL)
3762 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
3764 iflib_netmap_detach(ifp);
3765 ether_ifdetach(ifp);
3766 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
3767 CTX_LOCK_DESTROY(ctx);
3768 if (ctx->ifc_led_dev != NULL)
3769 led_destroy(ctx->ifc_led_dev);
3770 /* XXX drain any dependent tasks */
3771 tqg = qgroup_if_io_tqg;
3772 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
3773 callout_drain(&txq->ift_timer);
3774 callout_drain(&txq->ift_db_check);
3775 if (txq->ift_task.gt_uniq != NULL)
3776 taskqgroup_detach(tqg, &txq->ift_task);
3778 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
3779 if (rxq->ifr_task.gt_uniq != NULL)
3780 taskqgroup_detach(tqg, &rxq->ifr_task);
3782 tqg = qgroup_if_config_tqg;
3783 if (ctx->ifc_admin_task.gt_uniq != NULL)
3784 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
3785 if (ctx->ifc_vflr_task.gt_uniq != NULL)
3786 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
3789 device_set_softc(ctx->ifc_dev, NULL);
3790 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
3791 pci_release_msi(dev);
3793 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
3794 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
3796 if (ctx->ifc_msix_mem != NULL) {
3797 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
3798 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
3799 ctx->ifc_msix_mem = NULL;
3802 bus_generic_detach(dev);
3805 iflib_tx_structures_free(ctx);
3806 iflib_rx_structures_free(ctx);
3807 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
3808 free(ctx->ifc_softc, M_IFLIB);
3815 iflib_device_detach(device_t dev)
3817 if_ctx_t ctx = device_get_softc(dev);
3819 return (iflib_device_deregister(ctx));
3823 iflib_device_suspend(device_t dev)
3825 if_ctx_t ctx = device_get_softc(dev);
3831 return bus_generic_suspend(dev);
3834 iflib_device_shutdown(device_t dev)
3836 if_ctx_t ctx = device_get_softc(dev);
3842 return bus_generic_suspend(dev);
3847 iflib_device_resume(device_t dev)
3849 if_ctx_t ctx = device_get_softc(dev);
3850 iflib_txq_t txq = ctx->ifc_txqs;
3854 iflib_init_locked(ctx);
3856 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
3857 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3859 return (bus_generic_resume(dev));
3863 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
3866 if_ctx_t ctx = device_get_softc(dev);
3869 error = IFDI_IOV_INIT(ctx, num_vfs, params);
3876 iflib_device_iov_uninit(device_t dev)
3878 if_ctx_t ctx = device_get_softc(dev);
3881 IFDI_IOV_UNINIT(ctx);
3886 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
3889 if_ctx_t ctx = device_get_softc(dev);
3892 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
3898 /*********************************************************************
3900 * MODULE FUNCTION DEFINITIONS
3902 **********************************************************************/
3905 * - Start a fast taskqueue thread for each core
3906 * - Start a taskqueue for control operations
3909 iflib_module_init(void)
3915 iflib_module_event_handler(module_t mod, int what, void *arg)
3921 if ((err = iflib_module_init()) != 0)
3927 return (EOPNOTSUPP);
3933 /*********************************************************************
3935 * PUBLIC FUNCTION DEFINITIONS
3936 * ordered as in iflib.h
3938 **********************************************************************/
3942 _iflib_assert(if_shared_ctx_t sctx)
3944 MPASS(sctx->isc_tx_maxsize);
3945 MPASS(sctx->isc_tx_maxsegsize);
3947 MPASS(sctx->isc_rx_maxsize);
3948 MPASS(sctx->isc_rx_nsegments);
3949 MPASS(sctx->isc_rx_maxsegsize);
3952 MPASS(sctx->isc_txrx->ift_txd_encap);
3953 MPASS(sctx->isc_txrx->ift_txd_flush);
3954 MPASS(sctx->isc_txrx->ift_txd_credits_update);
3955 MPASS(sctx->isc_txrx->ift_rxd_available);
3956 MPASS(sctx->isc_txrx->ift_rxd_pkt_get);
3957 MPASS(sctx->isc_txrx->ift_rxd_refill);
3958 MPASS(sctx->isc_txrx->ift_rxd_flush);
3960 MPASS(sctx->isc_nrxd_min[0]);
3961 MPASS(sctx->isc_nrxd_max[0]);
3962 MPASS(sctx->isc_nrxd_default[0]);
3963 MPASS(sctx->isc_ntxd_min[0]);
3964 MPASS(sctx->isc_ntxd_max[0]);
3965 MPASS(sctx->isc_ntxd_default[0]);
3968 #define DEFAULT_CAPS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3969 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \
3970 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO | IFCAP_HWSTATS)
3973 iflib_register(if_ctx_t ctx)
3975 if_shared_ctx_t sctx = ctx->ifc_sctx;
3976 driver_t *driver = sctx->isc_driver;
3977 device_t dev = ctx->ifc_dev;
3980 _iflib_assert(sctx);
3982 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
3984 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
3986 device_printf(dev, "can not allocate ifnet structure\n");
3991 * Initialize our context's device specific methods
3993 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
3994 kobj_class_compile((kobj_class_t) driver);
3997 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3998 if_setsoftc(ifp, ctx);
3999 if_setdev(ifp, dev);
4000 if_setinitfn(ifp, iflib_if_init);
4001 if_setioctlfn(ifp, iflib_if_ioctl);
4002 if_settransmitfn(ifp, iflib_if_transmit);
4003 if_setqflushfn(ifp, iflib_if_qflush);
4004 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4006 /* XXX - move this in to the driver for non-default settings */
4007 if_setcapabilities(ifp, DEFAULT_CAPS);
4008 if_setcapenable(ifp, DEFAULT_CAPS);
4010 ctx->ifc_vlan_attach_event =
4011 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4012 EVENTHANDLER_PRI_FIRST);
4013 ctx->ifc_vlan_detach_event =
4014 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4015 EVENTHANDLER_PRI_FIRST);
4017 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4018 iflib_media_change, iflib_media_status);
4025 iflib_queues_alloc(if_ctx_t ctx)
4027 if_shared_ctx_t sctx = ctx->ifc_sctx;
4028 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4029 device_t dev = ctx->ifc_dev;
4030 int nrxqsets = scctx->isc_nrxqsets;
4031 int ntxqsets = scctx->isc_ntxqsets;
4034 iflib_fl_t fl = NULL;
4035 int i, j, cpu, err, txconf, rxconf;
4036 iflib_dma_info_t ifdip;
4037 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4038 uint32_t *txqsizes = scctx->isc_txqsizes;
4039 uint8_t nrxqs = sctx->isc_nrxqs;
4040 uint8_t ntxqs = sctx->isc_ntxqs;
4041 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4044 struct ifmp_ring **brscp;
4045 int nbuf_rings = 1; /* XXX determine dynamically */
4047 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4048 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4054 /* Allocate the TX ring struct memory */
4056 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4057 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4058 device_printf(dev, "Unable to allocate TX ring memory\n");
4063 /* Now allocate the RX */
4065 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4066 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4067 device_printf(dev, "Unable to allocate RX ring memory\n");
4071 if (!(brscp = malloc(sizeof(void *) * nbuf_rings * nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4072 device_printf(dev, "Unable to buf_ring_sc * memory\n");
4077 ctx->ifc_txqs = txq;
4078 ctx->ifc_rxqs = rxq;
4081 * XXX handle allocation failure
4083 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4084 /* Set up some basics */
4086 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4087 device_printf(dev, "failed to allocate iflib_dma_info\n");
4091 txq->ift_ifdi = ifdip;
4092 for (j = 0; j < ntxqs; j++, ifdip++) {
4093 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4094 device_printf(dev, "Unable to allocate Descriptor memory\n");
4098 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4102 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4103 txq->ift_br_offset = 1;
4105 txq->ift_br_offset = 0;
4108 txq->ift_timer.c_cpu = cpu;
4109 txq->ift_db_check.c_cpu = cpu;
4110 txq->ift_nbr = nbuf_rings;
4112 if (iflib_txsd_alloc(txq)) {
4113 device_printf(dev, "Critical Failure setting up TX buffers\n");
4118 /* Initialize the TX lock */
4119 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4120 device_get_nameunit(dev), txq->ift_id);
4121 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4122 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4123 callout_init_mtx(&txq->ift_db_check, &txq->ift_mtx, 0);
4125 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4126 device_get_nameunit(dev), txq->ift_id);
4127 TXDB_LOCK_INIT(txq);
4129 txq->ift_br = brscp + i*nbuf_rings;
4130 for (j = 0; j < nbuf_rings; j++) {
4131 err = ifmp_ring_alloc(&txq->ift_br[j], 2048, txq, iflib_txq_drain,
4132 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4134 /* XXX free any allocated rings */
4135 device_printf(dev, "Unable to allocate buf_ring\n");
4141 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4142 /* Set up some basics */
4144 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4145 device_printf(dev, "failed to allocate iflib_dma_info\n");
4150 rxq->ifr_ifdi = ifdip;
4151 for (j = 0; j < nrxqs; j++, ifdip++) {
4152 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4153 device_printf(dev, "Unable to allocate Descriptor memory\n");
4157 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4161 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4162 rxq->ifr_fl_offset = 1;
4164 rxq->ifr_fl_offset = 0;
4166 rxq->ifr_nfl = nfree_lists;
4168 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4169 device_printf(dev, "Unable to allocate free list memory\n");
4174 for (j = 0; j < nfree_lists; j++) {
4175 rxq->ifr_fl[j].ifl_rxq = rxq;
4176 rxq->ifr_fl[j].ifl_id = j;
4177 rxq->ifr_fl[j].ifl_ifdi =
4178 &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4180 /* Allocate receive buffers for the ring*/
4181 if (iflib_rxsd_alloc(rxq)) {
4183 "Critical Failure setting up receive buffers\n");
4190 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4191 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4192 for (i = 0; i < ntxqsets; i++) {
4193 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4195 for (j = 0; j < ntxqs; j++, di++) {
4196 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4197 paddrs[i*ntxqs + j] = di->idi_paddr;
4200 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4201 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4202 iflib_tx_structures_free(ctx);
4203 free(vaddrs, M_IFLIB);
4204 free(paddrs, M_IFLIB);
4207 free(vaddrs, M_IFLIB);
4208 free(paddrs, M_IFLIB);
4211 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4212 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4213 for (i = 0; i < nrxqsets; i++) {
4214 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4216 for (j = 0; j < nrxqs; j++, di++) {
4217 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4218 paddrs[i*nrxqs + j] = di->idi_paddr;
4221 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4222 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4223 iflib_tx_structures_free(ctx);
4224 free(vaddrs, M_IFLIB);
4225 free(paddrs, M_IFLIB);
4228 free(vaddrs, M_IFLIB);
4229 free(paddrs, M_IFLIB);
4233 /* XXX handle allocation failure changes */
4236 if (ctx->ifc_rxqs != NULL)
4237 free(ctx->ifc_rxqs, M_IFLIB);
4238 ctx->ifc_rxqs = NULL;
4239 if (ctx->ifc_txqs != NULL)
4240 free(ctx->ifc_txqs, M_IFLIB);
4241 ctx->ifc_txqs = NULL;
4244 free(brscp, M_IFLIB);
4254 iflib_tx_structures_setup(if_ctx_t ctx)
4256 iflib_txq_t txq = ctx->ifc_txqs;
4259 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4260 iflib_txq_setup(txq);
4266 iflib_tx_structures_free(if_ctx_t ctx)
4268 iflib_txq_t txq = ctx->ifc_txqs;
4271 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4272 iflib_txq_destroy(txq);
4273 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4274 iflib_dma_free(&txq->ift_ifdi[j]);
4276 free(ctx->ifc_txqs, M_IFLIB);
4277 ctx->ifc_txqs = NULL;
4278 IFDI_QUEUES_FREE(ctx);
4281 /*********************************************************************
4283 * Initialize all receive rings.
4285 **********************************************************************/
4287 iflib_rx_structures_setup(if_ctx_t ctx)
4289 iflib_rxq_t rxq = ctx->ifc_rxqs;
4291 #if defined(INET6) || defined(INET)
4295 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4296 #if defined(INET6) || defined(INET)
4297 tcp_lro_free(&rxq->ifr_lc);
4298 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4299 TCP_LRO_ENTRIES, min(1024,
4300 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4301 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4304 rxq->ifr_lro_enabled = TRUE;
4306 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4309 #if defined(INET6) || defined(INET)
4312 * Free RX software descriptors allocated so far, we will only handle
4313 * the rings that completed, the failing case will have
4314 * cleaned up for itself. 'q' failed, so its the terminus.
4316 rxq = ctx->ifc_rxqs;
4317 for (i = 0; i < q; ++i, rxq++) {
4318 iflib_rx_sds_free(rxq);
4319 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4325 /*********************************************************************
4327 * Free all receive rings.
4329 **********************************************************************/
4331 iflib_rx_structures_free(if_ctx_t ctx)
4333 iflib_rxq_t rxq = ctx->ifc_rxqs;
4335 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4336 iflib_rx_sds_free(rxq);
4341 iflib_qset_structures_setup(if_ctx_t ctx)
4345 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4348 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4349 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4350 iflib_tx_structures_free(ctx);
4351 iflib_rx_structures_free(ctx);
4357 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4358 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4361 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4365 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4367 int i, cpuid, eqid, count;
4369 CPU_COPY(&ctx->ifc_cpus, cpus);
4370 count = CPU_COUNT(&ctx->ifc_cpus);
4372 /* clear up to the qid'th bit */
4373 for (i = 0; i < eqid; i++) {
4374 cpuid = CPU_FFS(cpus);
4376 CPU_CLR(cpuid-1, cpus);
4378 cpuid = CPU_FFS(cpus);
4384 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
4385 iflib_intr_type_t type, driver_filter_t *filter,
4386 void *filter_arg, int qid, char *name)
4388 struct grouptask *gtask;
4389 struct taskqgroup *tqg;
4390 iflib_filter_info_t info;
4393 int tqrid, err, cpuid;
4396 info = &ctx->ifc_filter_info;
4400 /* XXX merge tx/rx for netmap? */
4402 q = &ctx->ifc_txqs[qid];
4403 info = &ctx->ifc_txqs[qid].ift_filter_info;
4404 gtask = &ctx->ifc_txqs[qid].ift_task;
4405 tqg = qgroup_if_io_tqg;
4407 GROUPTASK_INIT(gtask, 0, fn, q);
4410 q = &ctx->ifc_rxqs[qid];
4411 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4412 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4413 tqg = qgroup_if_io_tqg;
4415 GROUPTASK_INIT(gtask, 0, fn, q);
4417 case IFLIB_INTR_ADMIN:
4420 info = &ctx->ifc_filter_info;
4421 gtask = &ctx->ifc_admin_task;
4422 tqg = qgroup_if_config_tqg;
4423 fn = _task_fn_admin;
4426 panic("unknown net intr type");
4429 info->ifi_filter = filter;
4430 info->ifi_filter_arg = filter_arg;
4431 info->ifi_task = gtask;
4433 err = _iflib_irq_alloc(ctx, irq, rid, iflib_fast_intr, NULL, info, name);
4435 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
4438 if (type == IFLIB_INTR_ADMIN)
4442 cpuid = find_nth(ctx, &cpus, qid);
4443 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name);
4445 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4452 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name)
4454 struct grouptask *gtask;
4455 struct taskqgroup *tqg;
4461 q = &ctx->ifc_txqs[qid];
4462 gtask = &ctx->ifc_txqs[qid].ift_task;
4463 tqg = qgroup_if_io_tqg;
4467 q = &ctx->ifc_rxqs[qid];
4468 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4469 tqg = qgroup_if_io_tqg;
4472 case IFLIB_INTR_IOV:
4474 gtask = &ctx->ifc_vflr_task;
4475 tqg = qgroup_if_config_tqg;
4480 panic("unknown net intr type");
4482 GROUPTASK_INIT(gtask, 0, fn, q);
4483 taskqgroup_attach(tqg, gtask, q, rid, name);
4487 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
4490 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
4493 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
4497 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
4499 iflib_txq_t txq = ctx->ifc_txqs;
4500 iflib_rxq_t rxq = ctx->ifc_rxqs;
4501 if_irq_t irq = &ctx->ifc_legacy_irq;
4502 iflib_filter_info_t info;
4503 struct grouptask *gtask;
4504 struct taskqgroup *tqg;
4510 q = &ctx->ifc_rxqs[0];
4511 info = &rxq[0].ifr_filter_info;
4512 gtask = &rxq[0].ifr_task;
4513 tqg = qgroup_if_io_tqg;
4514 tqrid = irq->ii_rid = *rid;
4517 ctx->ifc_flags |= IFC_LEGACY;
4518 info->ifi_filter = filter;
4519 info->ifi_filter_arg = filter_arg;
4520 info->ifi_task = gtask;
4522 /* We allocate a single interrupt resource */
4523 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr, NULL, info, name)) != 0)
4525 GROUPTASK_INIT(gtask, 0, fn, q);
4526 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4528 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
4529 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx");
4530 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4531 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin/link");
4537 iflib_led_create(if_ctx_t ctx)
4540 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
4541 device_get_nameunit(ctx->ifc_dev));
4545 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
4548 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
4552 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
4555 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
4559 iflib_admin_intr_deferred(if_ctx_t ctx)
4562 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
4566 iflib_iov_intr_deferred(if_ctx_t ctx)
4569 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
4573 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
4576 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
4580 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
4584 GROUPTASK_INIT(gtask, 0, fn, ctx);
4585 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
4589 iflib_config_gtask_deinit(struct grouptask *gtask)
4592 taskqgroup_detach(qgroup_if_config_tqg, gtask);
4596 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
4598 if_t ifp = ctx->ifc_ifp;
4599 iflib_txq_t txq = ctx->ifc_txqs;
4602 if_setbaudrate(ifp, baudrate);
4604 /* If link down, disable watchdog */
4605 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
4606 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
4607 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
4609 ctx->ifc_link_state = link_state;
4610 if_link_state_change(ifp, link_state);
4614 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
4618 if (ctx->isc_txd_credits_update == NULL)
4621 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, true)) == 0)
4624 txq->ift_processed += credits;
4625 txq->ift_cidx_processed += credits;
4627 if (txq->ift_cidx_processed >= txq->ift_size)
4628 txq->ift_cidx_processed -= txq->ift_size;
4633 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget)
4636 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
4641 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
4642 const char *description, if_int_delay_info_t info,
4643 int offset, int value)
4645 info->iidi_ctx = ctx;
4646 info->iidi_offset = offset;
4647 info->iidi_value = value;
4648 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
4649 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
4650 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
4651 info, 0, iflib_sysctl_int_delay, "I", description);
4655 iflib_ctx_lock_get(if_ctx_t ctx)
4658 return (&ctx->ifc_mtx);
4662 iflib_msix_init(if_ctx_t ctx)
4664 device_t dev = ctx->ifc_dev;
4665 if_shared_ctx_t sctx = ctx->ifc_sctx;
4666 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4667 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
4668 int iflib_num_tx_queues, iflib_num_rx_queues;
4669 int err, admincnt, bar;
4671 iflib_num_tx_queues = scctx->isc_ntxqsets;
4672 iflib_num_rx_queues = scctx->isc_nrxqsets;
4674 bar = ctx->ifc_softc_ctx.isc_msix_bar;
4675 admincnt = sctx->isc_admin_intrcnt;
4676 /* Override by tuneable */
4677 if (enable_msix == 0)
4681 ** When used in a virtualized environment
4682 ** PCI BUSMASTER capability may not be set
4683 ** so explicity set it here and rewrite
4684 ** the ENABLE in the MSIX control register
4685 ** at this point to cause the host to
4686 ** successfully initialize us.
4689 uint16_t pci_cmd_word;
4693 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
4694 pci_cmd_word |= PCIM_CMD_BUSMASTEREN;
4695 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2);
4696 pci_find_cap(dev, PCIY_MSIX, &rid);
4697 rid += PCIR_MSIX_CTRL;
4698 msix_ctrl = pci_read_config(dev, rid, 2);
4699 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
4700 pci_write_config(dev, rid, msix_ctrl, 2);
4704 * bar == -1 => "trust me I know what I'm doing"
4705 * https://www.youtube.com/watch?v=nnwWKkNau4I
4706 * Some drivers are for hardware that is so shoddily
4707 * documented that no one knows which bars are which
4708 * so the developer has to map all bars. This hack
4709 * allows shoddy garbage to use msix in this framework.
4712 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
4713 SYS_RES_MEMORY, &bar, RF_ACTIVE);
4714 if (ctx->ifc_msix_mem == NULL) {
4715 /* May not be enabled */
4716 device_printf(dev, "Unable to map MSIX table \n");
4720 /* First try MSI/X */
4721 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
4722 device_printf(dev, "System has MSIX disabled \n");
4723 bus_release_resource(dev, SYS_RES_MEMORY,
4724 bar, ctx->ifc_msix_mem);
4725 ctx->ifc_msix_mem = NULL;
4729 /* use only 1 qset in debug mode */
4730 queuemsgs = min(msgs - admincnt, 1);
4732 queuemsgs = msgs - admincnt;
4734 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
4736 queues = imin(queuemsgs, rss_getnumbuckets());
4740 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
4741 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
4742 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
4744 device_printf(dev, "Unable to fetch CPU list\n");
4745 /* Figure out a reasonable auto config value */
4746 queues = min(queuemsgs, mp_ncpus);
4749 /* If we're doing RSS, clamp at the number of RSS buckets */
4750 if (queues > rss_getnumbuckets())
4751 queues = rss_getnumbuckets();
4753 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
4754 rx_queues = iflib_num_rx_queues;
4758 * We want this to be all logical CPUs by default
4760 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
4761 tx_queues = iflib_num_tx_queues;
4763 tx_queues = mp_ncpus;
4765 if (ctx->ifc_sysctl_qs_eq_override == 0) {
4767 if (tx_queues != rx_queues)
4768 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
4769 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
4771 tx_queues = min(rx_queues, tx_queues);
4772 rx_queues = min(rx_queues, tx_queues);
4775 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
4777 vectors = rx_queues + admincnt;
4778 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
4780 "Using MSIX interrupts with %d vectors\n", vectors);
4781 scctx->isc_vectors = vectors;
4782 scctx->isc_nrxqsets = rx_queues;
4783 scctx->isc_ntxqsets = tx_queues;
4784 scctx->isc_intr = IFLIB_INTR_MSIX;
4788 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
4791 vectors = pci_msi_count(dev);
4792 scctx->isc_nrxqsets = 1;
4793 scctx->isc_ntxqsets = 1;
4794 scctx->isc_vectors = vectors;
4795 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
4796 device_printf(dev,"Using an MSI interrupt\n");
4797 scctx->isc_intr = IFLIB_INTR_MSI;
4799 device_printf(dev,"Using a Legacy interrupt\n");
4800 scctx->isc_intr = IFLIB_INTR_LEGACY;
4806 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
4809 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
4812 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
4814 char *ring_state = "UNKNOWN";
4817 rc = sysctl_wire_old_buffer(req, 0);
4821 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
4826 ring_state = ring_states[state[3]];
4828 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
4829 state[0], state[1], state[2], ring_state);
4830 rc = sbuf_finish(sb);
4835 enum iflib_ndesc_handler {
4841 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
4843 if_ctx_t ctx = (void *)arg1;
4844 enum iflib_ndesc_handler type = arg2;
4845 char buf[256] = {0};
4850 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
4854 case IFLIB_NTXD_HANDLER:
4855 ndesc = ctx->ifc_sysctl_ntxds;
4857 nqs = ctx->ifc_sctx->isc_ntxqs;
4859 case IFLIB_NRXD_HANDLER:
4860 ndesc = ctx->ifc_sysctl_nrxds;
4862 nqs = ctx->ifc_sctx->isc_nrxqs;
4868 for (i=0; i<8; i++) {
4873 sprintf(strchr(buf, 0), "%d", ndesc[i]);
4876 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
4877 if (rc || req->newptr == NULL)
4880 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
4881 i++, p = strsep(&next, " ,")) {
4882 ndesc[i] = strtoul(p, NULL, 10);
4888 #define NAME_BUFLEN 32
4890 iflib_add_device_sysctl_pre(if_ctx_t ctx)
4892 device_t dev = iflib_get_dev(ctx);
4893 struct sysctl_oid_list *child, *oid_list;
4894 struct sysctl_ctx_list *ctx_list;
4895 struct sysctl_oid *node;
4897 ctx_list = device_get_sysctl_ctx(dev);
4898 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
4899 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
4900 CTLFLAG_RD, NULL, "IFLIB fields");
4901 oid_list = SYSCTL_CHILDREN(node);
4903 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
4904 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
4907 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
4908 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
4909 "# of txqs to use, 0 => use default #");
4910 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
4911 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
4912 "# of rxqs to use, 0 => use default #");
4913 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
4914 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
4915 "permit #txq != #rxq");
4917 /* XXX change for per-queue sizes */
4918 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
4919 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
4920 mp_ndesc_handler, "A",
4921 "list of # of tx descriptors to use, 0 = use default #");
4922 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
4923 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
4924 mp_ndesc_handler, "A",
4925 "list of # of rx descriptors to use, 0 = use default #");
4929 iflib_add_device_sysctl_post(if_ctx_t ctx)
4931 if_shared_ctx_t sctx = ctx->ifc_sctx;
4932 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4933 device_t dev = iflib_get_dev(ctx);
4934 struct sysctl_oid_list *child;
4935 struct sysctl_ctx_list *ctx_list;
4940 char namebuf[NAME_BUFLEN];
4942 struct sysctl_oid *queue_node, *fl_node, *node;
4943 struct sysctl_oid_list *queue_list, *fl_list;
4944 ctx_list = device_get_sysctl_ctx(dev);
4946 node = ctx->ifc_sysctl_node;
4947 child = SYSCTL_CHILDREN(node);
4949 if (scctx->isc_ntxqsets > 100)
4951 else if (scctx->isc_ntxqsets > 10)
4955 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
4956 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
4957 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
4958 CTLFLAG_RD, NULL, "Queue Name");
4959 queue_list = SYSCTL_CHILDREN(queue_node);
4961 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
4963 &txq->ift_dequeued, "total mbufs freed");
4964 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
4966 &txq->ift_enqueued, "total mbufs enqueued");
4968 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
4970 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
4971 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
4973 &txq->ift_pullups, "# of times m_pullup was called");
4974 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
4976 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
4977 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
4979 &txq->ift_no_desc_avail, "# of times no descriptors were available");
4980 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
4982 &txq->ift_map_failed, "# of times dma map failed");
4983 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
4985 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
4986 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
4988 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
4989 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
4991 &txq->ift_pidx, 1, "Producer Index");
4992 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
4994 &txq->ift_cidx, 1, "Consumer Index");
4995 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
4997 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
4998 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5000 &txq->ift_in_use, 1, "descriptors in use");
5001 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5003 &txq->ift_processed, "descriptors procesed for clean");
5004 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5006 &txq->ift_cleaned, "total cleaned");
5007 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5008 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br[0]->state),
5009 0, mp_ring_state_handler, "A", "soft ring state");
5010 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5011 CTLFLAG_RD, &txq->ift_br[0]->enqueues,
5012 "# of enqueues to the mp_ring for this queue");
5013 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5014 CTLFLAG_RD, &txq->ift_br[0]->drops,
5015 "# of drops in the mp_ring for this queue");
5016 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5017 CTLFLAG_RD, &txq->ift_br[0]->starts,
5018 "# of normal consumer starts in the mp_ring for this queue");
5019 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5020 CTLFLAG_RD, &txq->ift_br[0]->stalls,
5021 "# of consumer stalls in the mp_ring for this queue");
5022 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5023 CTLFLAG_RD, &txq->ift_br[0]->restarts,
5024 "# of consumer restarts in the mp_ring for this queue");
5025 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5026 CTLFLAG_RD, &txq->ift_br[0]->abdications,
5027 "# of consumer abdications in the mp_ring for this queue");
5030 if (scctx->isc_nrxqsets > 100)
5032 else if (scctx->isc_nrxqsets > 10)
5036 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5037 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5038 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5039 CTLFLAG_RD, NULL, "Queue Name");
5040 queue_list = SYSCTL_CHILDREN(queue_node);
5041 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5042 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5044 &rxq->ifr_cq_pidx, 1, "Producer Index");
5045 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5047 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5050 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5051 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5052 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5053 CTLFLAG_RD, NULL, "freelist Name");
5054 fl_list = SYSCTL_CHILDREN(fl_node);
5055 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5057 &fl->ifl_pidx, 1, "Producer Index");
5058 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5060 &fl->ifl_cidx, 1, "Consumer Index");
5061 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5063 &fl->ifl_credits, 1, "credits available");
5065 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5067 &fl->ifl_m_enqueued, "mbufs allocated");
5068 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5070 &fl->ifl_m_dequeued, "mbufs freed");
5071 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5073 &fl->ifl_cl_enqueued, "clusters allocated");
5074 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5076 &fl->ifl_cl_dequeued, "clusters freed");