2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
95 #if defined(__i386__) || defined(__amd64__)
96 #include <sys/memdesc.h>
97 #include <machine/bus.h>
98 #include <machine/md_var.h>
99 #include <machine/specialreg.h>
100 #include <x86/include/busdma_impl.h>
101 #include <x86/iommu/busdma_dmar.h>
104 #include <sys/bitstring.h>
106 * enable accounting of every mbuf as it comes in to and goes out of
107 * iflib's software descriptor references
109 #define MEMORY_LOGGING 0
111 * Enable mbuf vectors for compressing long mbuf chains
116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
117 * we prefetch needs to be determined by the time spent in m_free vis a vis
118 * the cost of a prefetch. This will of course vary based on the workload:
119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
120 * is quite expensive, thus suggesting very little prefetch.
121 * - small packet forwarding which is just returning a single mbuf to
122 * UMA will typically be very fast vis a vis the cost of a memory
129 * - private structures
130 * - iflib private utility functions
132 * - vlan registry and other exported functions
133 * - iflib public core functions
137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
140 typedef struct iflib_txq *iflib_txq_t;
142 typedef struct iflib_rxq *iflib_rxq_t;
144 typedef struct iflib_fl *iflib_fl_t;
148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
149 static void iflib_timer(void *arg);
151 typedef struct iflib_filter_info {
152 driver_filter_t *ifi_filter;
153 void *ifi_filter_arg;
154 struct grouptask *ifi_task;
156 } *iflib_filter_info_t;
161 * Pointer to hardware driver's softc
168 if_shared_ctx_t ifc_sctx;
169 struct if_softc_ctx ifc_softc_ctx;
171 struct sx ifc_ctx_sx;
172 struct mtx ifc_state_mtx;
174 uint16_t ifc_nhwtxqs;
176 iflib_txq_t ifc_txqs;
177 iflib_rxq_t ifc_rxqs;
178 uint32_t ifc_if_flags;
180 uint32_t ifc_max_fl_buf_size;
185 int ifc_watchdog_events;
186 struct cdev *ifc_led_dev;
187 struct resource *ifc_msix_mem;
189 struct if_irq ifc_legacy_irq;
190 struct grouptask ifc_admin_task;
191 struct grouptask ifc_vflr_task;
192 struct iflib_filter_info ifc_filter_info;
193 struct ifmedia ifc_media;
195 struct sysctl_oid *ifc_sysctl_node;
196 uint16_t ifc_sysctl_ntxqs;
197 uint16_t ifc_sysctl_nrxqs;
198 uint16_t ifc_sysctl_qs_eq_override;
199 uint16_t ifc_sysctl_rx_budget;
200 uint16_t ifc_sysctl_tx_abdicate;
202 qidx_t ifc_sysctl_ntxds[8];
203 qidx_t ifc_sysctl_nrxds[8];
204 struct if_txrx ifc_txrx;
205 #define isc_txd_encap ifc_txrx.ift_txd_encap
206 #define isc_txd_flush ifc_txrx.ift_txd_flush
207 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
208 #define isc_rxd_available ifc_txrx.ift_rxd_available
209 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
212 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
213 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
214 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
215 eventhandler_tag ifc_vlan_attach_event;
216 eventhandler_tag ifc_vlan_detach_event;
217 uint8_t ifc_mac[ETHER_ADDR_LEN];
218 char ifc_mtx_name[16];
223 iflib_get_softc(if_ctx_t ctx)
226 return (ctx->ifc_softc);
230 iflib_get_dev(if_ctx_t ctx)
233 return (ctx->ifc_dev);
237 iflib_get_ifp(if_ctx_t ctx)
240 return (ctx->ifc_ifp);
244 iflib_get_media(if_ctx_t ctx)
247 return (&ctx->ifc_media);
251 iflib_get_flags(if_ctx_t ctx)
253 return (ctx->ifc_flags);
257 iflib_set_detach(if_ctx_t ctx)
259 ctx->ifc_in_detach = 1;
263 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
266 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
270 iflib_get_softc_ctx(if_ctx_t ctx)
273 return (&ctx->ifc_softc_ctx);
277 iflib_get_sctx(if_ctx_t ctx)
280 return (ctx->ifc_sctx);
283 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
284 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
285 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
287 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
288 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
290 #define RX_SW_DESC_MAP_CREATED (1 << 0)
291 #define TX_SW_DESC_MAP_CREATED (1 << 1)
292 #define RX_SW_DESC_INUSE (1 << 3)
293 #define TX_SW_DESC_MAPPED (1 << 4)
295 #define M_TOOBIG M_PROTO1
297 typedef struct iflib_sw_rx_desc_array {
298 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
299 struct mbuf **ifsd_m; /* pkthdr mbufs */
300 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
302 } iflib_rxsd_array_t;
304 typedef struct iflib_sw_tx_desc_array {
305 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
306 struct mbuf **ifsd_m; /* pkthdr mbufs */
311 /* magic number that should be high enough for any hardware */
312 #define IFLIB_MAX_TX_SEGS 128
313 /* bnxt supports 64 with hardware LRO enabled */
314 #define IFLIB_MAX_RX_SEGS 64
315 #define IFLIB_RX_COPY_THRESH 128
316 #define IFLIB_MAX_RX_REFRESH 32
317 /* The minimum descriptors per second before we start coalescing */
318 #define IFLIB_MIN_DESC_SEC 16384
319 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
320 #define IFLIB_QUEUE_IDLE 0
321 #define IFLIB_QUEUE_HUNG 1
322 #define IFLIB_QUEUE_WORKING 2
323 /* maximum number of txqs that can share an rx interrupt */
324 #define IFLIB_MAX_TX_SHARED_INTR 4
326 /* this should really scale with ring size - this is a fairly arbitrary value */
327 #define TX_BATCH_SIZE 32
329 #define IFLIB_RESTART_BUDGET 8
332 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
333 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
334 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
338 qidx_t ift_cidx_processed;
341 uint8_t ift_br_offset;
342 uint16_t ift_npending;
343 uint16_t ift_db_pending;
344 uint16_t ift_rs_pending;
346 uint8_t ift_txd_size[8];
347 uint64_t ift_processed;
348 uint64_t ift_cleaned;
349 uint64_t ift_cleaned_prev;
351 uint64_t ift_enqueued;
352 uint64_t ift_dequeued;
354 uint64_t ift_no_tx_dma_setup;
355 uint64_t ift_no_desc_avail;
356 uint64_t ift_mbuf_defrag_failed;
357 uint64_t ift_mbuf_defrag;
358 uint64_t ift_map_failed;
359 uint64_t ift_txd_encap_efbig;
360 uint64_t ift_pullups;
361 uint64_t ift_last_timer_tick;
364 struct mtx ift_db_mtx;
366 /* constant values */
368 struct ifmp_ring *ift_br;
369 struct grouptask ift_task;
372 struct callout ift_timer;
374 if_txsd_vec_t ift_sds;
377 uint8_t ift_update_freq;
378 struct iflib_filter_info ift_filter_info;
379 bus_dma_tag_t ift_desc_tag;
380 bus_dma_tag_t ift_tso_desc_tag;
381 iflib_dma_info_t ift_ifdi;
382 #define MTX_NAME_LEN 16
383 char ift_mtx_name[MTX_NAME_LEN];
384 char ift_db_mtx_name[MTX_NAME_LEN];
385 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
386 #ifdef IFLIB_DIAGNOSTICS
387 uint64_t ift_cpu_exec_count[256];
389 } __aligned(CACHE_LINE_SIZE);
396 uint8_t ifl_rxd_size;
398 uint64_t ifl_m_enqueued;
399 uint64_t ifl_m_dequeued;
400 uint64_t ifl_cl_enqueued;
401 uint64_t ifl_cl_dequeued;
405 bitstr_t *ifl_rx_bitmap;
409 uint16_t ifl_buf_size;
412 iflib_rxsd_array_t ifl_sds;
415 bus_dma_tag_t ifl_desc_tag;
416 iflib_dma_info_t ifl_ifdi;
417 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
418 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
419 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
420 } __aligned(CACHE_LINE_SIZE);
423 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
429 else if (pidx < cidx)
430 used = size - cidx + pidx;
431 else if (gen == 0 && pidx == cidx)
433 else if (gen == 1 && pidx == cidx)
441 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
443 #define IDXDIFF(head, tail, wrap) \
444 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
447 /* If there is a separate completion queue -
448 * these are the cq cidx and pidx. Otherwise
455 uint8_t ifr_fl_offset;
461 uint8_t ifr_lro_enabled;
464 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
465 struct lro_ctrl ifr_lc;
466 struct grouptask ifr_task;
467 struct iflib_filter_info ifr_filter_info;
468 iflib_dma_info_t ifr_ifdi;
470 /* dynamically allocate if any drivers need a value substantially larger than this */
471 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
472 #ifdef IFLIB_DIAGNOSTICS
473 uint64_t ifr_cpu_exec_count[256];
475 } __aligned(CACHE_LINE_SIZE);
477 typedef struct if_rxsd {
479 struct mbuf **ifsd_m;
484 /* multiple of word size */
486 #define PKT_INFO_SIZE 6
487 #define RXD_INFO_SIZE 5
488 #define PKT_TYPE uint64_t
490 #define PKT_INFO_SIZE 11
491 #define RXD_INFO_SIZE 8
492 #define PKT_TYPE uint32_t
494 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
495 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
497 typedef struct if_pkt_info_pad {
498 PKT_TYPE pkt_val[PKT_INFO_SIZE];
499 } *if_pkt_info_pad_t;
500 typedef struct if_rxd_info_pad {
501 PKT_TYPE rxd_val[RXD_INFO_SIZE];
502 } *if_rxd_info_pad_t;
504 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
505 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
509 pkt_info_zero(if_pkt_info_t pi)
511 if_pkt_info_pad_t pi_pad;
513 pi_pad = (if_pkt_info_pad_t)pi;
514 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
515 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
517 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
518 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
522 static device_method_t iflib_pseudo_methods[] = {
523 DEVMETHOD(device_attach, noop_attach),
524 DEVMETHOD(device_detach, iflib_pseudo_detach),
528 driver_t iflib_pseudodriver = {
529 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
533 rxd_info_zero(if_rxd_info_t ri)
535 if_rxd_info_pad_t ri_pad;
538 ri_pad = (if_rxd_info_pad_t)ri;
539 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
540 ri_pad->rxd_val[i] = 0;
541 ri_pad->rxd_val[i+1] = 0;
542 ri_pad->rxd_val[i+2] = 0;
543 ri_pad->rxd_val[i+3] = 0;
546 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
551 * Only allow a single packet to take up most 1/nth of the tx ring
553 #define MAX_SINGLE_PACKET_FRACTION 12
554 #define IF_BAD_DMA (bus_addr_t)-1
556 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
558 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
559 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
560 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
561 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
564 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
565 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
566 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
567 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
571 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
572 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
575 /* Our boot-time initialization hook */
576 static int iflib_module_event_handler(module_t, int, void *);
578 static moduledata_t iflib_moduledata = {
580 iflib_module_event_handler,
584 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
585 MODULE_VERSION(iflib, 1);
587 MODULE_DEPEND(iflib, pci, 1, 1, 1);
588 MODULE_DEPEND(iflib, ether, 1, 1, 1);
590 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
591 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
593 #ifndef IFLIB_DEBUG_COUNTERS
595 #define IFLIB_DEBUG_COUNTERS 1
597 #define IFLIB_DEBUG_COUNTERS 0
598 #endif /* !INVARIANTS */
601 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
602 "iflib driver parameters");
605 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
607 static int iflib_min_tx_latency = 0;
608 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
609 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
610 static int iflib_no_tx_batch = 0;
611 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
612 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
615 #if IFLIB_DEBUG_COUNTERS
617 static int iflib_tx_seen;
618 static int iflib_tx_sent;
619 static int iflib_tx_encap;
620 static int iflib_rx_allocs;
621 static int iflib_fl_refills;
622 static int iflib_fl_refills_large;
623 static int iflib_tx_frees;
625 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
626 &iflib_tx_seen, 0, "# tx mbufs seen");
627 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
628 &iflib_tx_sent, 0, "# tx mbufs sent");
629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
630 &iflib_tx_encap, 0, "# tx mbufs encapped");
631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
632 &iflib_tx_frees, 0, "# tx frees");
633 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
634 &iflib_rx_allocs, 0, "# rx allocations");
635 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
636 &iflib_fl_refills, 0, "# refills");
637 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
638 &iflib_fl_refills_large, 0, "# large refills");
641 static int iflib_txq_drain_flushing;
642 static int iflib_txq_drain_oactive;
643 static int iflib_txq_drain_notready;
644 static int iflib_txq_drain_encapfail;
646 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
647 &iflib_txq_drain_flushing, 0, "# drain flushes");
648 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
649 &iflib_txq_drain_oactive, 0, "# drain oactives");
650 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
651 &iflib_txq_drain_notready, 0, "# drain notready");
652 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
653 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
656 static int iflib_encap_load_mbuf_fail;
657 static int iflib_encap_pad_mbuf_fail;
658 static int iflib_encap_txq_avail_fail;
659 static int iflib_encap_txd_encap_fail;
661 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
662 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
663 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
664 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
665 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
666 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
667 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
668 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
670 static int iflib_task_fn_rxs;
671 static int iflib_rx_intr_enables;
672 static int iflib_fast_intrs;
673 static int iflib_intr_link;
674 static int iflib_intr_msix;
675 static int iflib_rx_unavail;
676 static int iflib_rx_ctx_inactive;
677 static int iflib_rx_zero_len;
678 static int iflib_rx_if_input;
679 static int iflib_rx_mbuf_null;
680 static int iflib_rxd_flush;
682 static int iflib_verbose_debug;
684 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
685 &iflib_intr_link, 0, "# intr link calls");
686 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
687 &iflib_intr_msix, 0, "# intr msix calls");
688 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
689 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
691 &iflib_rx_intr_enables, 0, "# rx intr enables");
692 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
693 &iflib_fast_intrs, 0, "# fast_intr calls");
694 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
695 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
696 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
697 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
698 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
699 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
700 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
701 &iflib_rx_if_input, 0, "# times rxeof called if_input");
702 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
703 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
704 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
705 &iflib_rxd_flush, 0, "# times rxd_flush called");
706 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
707 &iflib_verbose_debug, 0, "enable verbose debugging");
709 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
711 iflib_debug_reset(void)
713 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
714 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
715 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
716 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
717 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
718 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
719 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
720 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
721 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
722 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
726 #define DBG_COUNTER_INC(name)
727 static void iflib_debug_reset(void) {}
730 #define IFLIB_DEBUG 0
732 static void iflib_tx_structures_free(if_ctx_t ctx);
733 static void iflib_rx_structures_free(if_ctx_t ctx);
734 static int iflib_queues_alloc(if_ctx_t ctx);
735 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
736 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
737 static int iflib_qset_structures_setup(if_ctx_t ctx);
738 static int iflib_msix_init(if_ctx_t ctx);
739 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
740 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
741 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
742 static int iflib_register(if_ctx_t);
743 static void iflib_init_locked(if_ctx_t ctx);
744 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
745 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
746 static void iflib_ifmp_purge(iflib_txq_t txq);
747 static void _iflib_pre_assert(if_softc_ctx_t scctx);
748 static void iflib_if_init_locked(if_ctx_t ctx);
749 #ifndef __NO_STRICT_ALIGNMENT
750 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
753 NETDUMP_DEFINE(iflib);
756 #include <sys/selinfo.h>
757 #include <net/netmap.h>
758 #include <dev/netmap/netmap_kern.h>
760 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
762 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
765 * device-specific sysctl variables:
767 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
768 * During regular operations the CRC is stripped, but on some
769 * hardware reception of frames not multiple of 64 is slower,
770 * so using crcstrip=0 helps in benchmarks.
772 * iflib_rx_miss, iflib_rx_miss_bufs:
773 * count packets that might be missed due to lost interrupts.
775 SYSCTL_DECL(_dev_netmap);
777 * The xl driver by default strips CRCs and we do not override it.
780 int iflib_crcstrip = 1;
781 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
782 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
784 int iflib_rx_miss, iflib_rx_miss_bufs;
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
786 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
787 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
788 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
791 * Register/unregister. We are already under netmap lock.
792 * Only called on the first register or the last unregister.
795 iflib_netmap_register(struct netmap_adapter *na, int onoff)
797 struct ifnet *ifp = na->ifp;
798 if_ctx_t ctx = ifp->if_softc;
802 IFDI_INTR_DISABLE(ctx);
804 /* Tell the stack that the interface is no longer active */
805 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
810 /* enable or disable flags and callbacks in na and ifp */
812 nm_set_native_flags(na);
814 nm_clear_native_flags(na);
817 iflib_init_locked(ctx);
818 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
819 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
821 nm_clear_native_flags(na);
827 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
829 struct netmap_adapter *na = kring->na;
830 u_int const lim = kring->nkr_num_slots - 1;
831 u_int head = kring->rhead;
832 struct netmap_ring *ring = kring->ring;
834 struct if_rxd_update iru;
835 if_ctx_t ctx = rxq->ifr_ctx;
836 iflib_fl_t fl = &rxq->ifr_fl[0];
837 uint32_t refill_pidx, nic_i;
839 if (nm_i == head && __predict_true(!init))
841 iru_init(&iru, rxq, 0 /* flid */);
842 map = fl->ifl_sds.ifsd_map;
843 refill_pidx = netmap_idx_k2n(kring, nm_i);
845 * IMPORTANT: we must leave one free slot in the ring,
846 * so move head back by one unit
848 head = nm_prev(head, lim);
850 while (nm_i != head) {
851 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
852 struct netmap_slot *slot = &ring->slot[nm_i];
853 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
854 uint32_t nic_i_dma = refill_pidx;
855 nic_i = netmap_idx_k2n(kring, nm_i);
857 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
859 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
860 return netmap_ring_reinit(kring);
862 fl->ifl_vm_addrs[tmp_pidx] = addr;
863 if (__predict_false(init) && map) {
864 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
865 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
866 /* buffer has changed, reload map */
867 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
869 slot->flags &= ~NS_BUF_CHANGED;
871 nm_i = nm_next(nm_i, lim);
872 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
873 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
876 iru.iru_pidx = refill_pidx;
877 iru.iru_count = tmp_pidx+1;
878 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
884 for (int n = 0; n < iru.iru_count; n++) {
885 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
886 BUS_DMASYNC_PREREAD);
887 /* XXX - change this to not use the netmap func*/
888 nic_i_dma = nm_next(nic_i_dma, lim);
892 kring->nr_hwcur = head;
895 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
896 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
897 if (__predict_true(nic_i != UINT_MAX))
898 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
903 * Reconcile kernel and user view of the transmit ring.
905 * All information is in the kring.
906 * Userspace wants to send packets up to the one before kring->rhead,
907 * kernel knows kring->nr_hwcur is the first unsent packet.
909 * Here we push packets out (as many as possible), and possibly
910 * reclaim buffers from previously completed transmission.
912 * The caller (netmap) guarantees that there is only one instance
913 * running at any time. Any interference with other driver
914 * methods should be handled by the individual drivers.
917 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
919 struct netmap_adapter *na = kring->na;
920 struct ifnet *ifp = na->ifp;
921 struct netmap_ring *ring = kring->ring;
922 u_int nm_i; /* index into the netmap kring */
923 u_int nic_i; /* index into the NIC ring */
925 u_int const lim = kring->nkr_num_slots - 1;
926 u_int const head = kring->rhead;
927 struct if_pkt_info pi;
930 * interrupts on every tx packet are expensive so request
931 * them every half ring, or where NS_REPORT is set
933 u_int report_frequency = kring->nkr_num_slots >> 1;
934 /* device-specific */
935 if_ctx_t ctx = ifp->if_softc;
936 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
938 if (txq->ift_sds.ifsd_map)
939 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
940 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
944 * First part: process new packets to send.
945 * nm_i is the current index in the netmap kring,
946 * nic_i is the corresponding index in the NIC ring.
948 * If we have packets to send (nm_i != head)
949 * iterate over the netmap ring, fetch length and update
950 * the corresponding slot in the NIC ring. Some drivers also
951 * need to update the buffer's physical address in the NIC slot
952 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
954 * The netmap_reload_map() calls is especially expensive,
955 * even when (as in this case) the tag is 0, so do only
956 * when the buffer has actually changed.
958 * If possible do not set the report/intr bit on all slots,
959 * but only a few times per ring or when NS_REPORT is set.
961 * Finally, on 10G and faster drivers, it might be useful
962 * to prefetch the next slot and txr entry.
965 nm_i = kring->nr_hwcur;
966 if (nm_i != head) { /* we have new packets to send */
968 pi.ipi_segs = txq->ift_segs;
969 pi.ipi_qsidx = kring->ring_id;
970 nic_i = netmap_idx_k2n(kring, nm_i);
972 __builtin_prefetch(&ring->slot[nm_i]);
973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
974 if (txq->ift_sds.ifsd_map)
975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
977 for (n = 0; nm_i != head; n++) {
978 struct netmap_slot *slot = &ring->slot[nm_i];
979 u_int len = slot->len;
981 void *addr = PNMB(na, slot, &paddr);
982 int flags = (slot->flags & NS_REPORT ||
983 nic_i == 0 || nic_i == report_frequency) ?
986 /* device-specific */
988 pi.ipi_segs[0].ds_addr = paddr;
989 pi.ipi_segs[0].ds_len = len;
993 pi.ipi_flags = flags;
995 /* Fill the slot in the NIC ring. */
996 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
998 /* prefetch for next round */
999 __builtin_prefetch(&ring->slot[nm_i + 1]);
1000 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1001 if (txq->ift_sds.ifsd_map) {
1002 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1004 NM_CHECK_ADDR_LEN(na, addr, len);
1006 if (slot->flags & NS_BUF_CHANGED) {
1007 /* buffer has changed, reload map */
1008 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
1010 /* make sure changes to the buffer are synced */
1011 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1012 BUS_DMASYNC_PREWRITE);
1014 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1015 nm_i = nm_next(nm_i, lim);
1016 nic_i = nm_next(nic_i, lim);
1018 kring->nr_hwcur = nm_i;
1020 /* synchronize the NIC ring */
1021 if (txq->ift_sds.ifsd_map)
1022 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1025 /* (re)start the tx unit up to slot nic_i (excluded) */
1026 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1030 * Second part: reclaim buffers for completed transmissions.
1032 * If there are unclaimed buffers, attempt to reclaim them.
1033 * If none are reclaimed, and TX IRQs are not in use, do an initial
1034 * minimal delay, then trigger the tx handler which will spin in the
1037 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1038 if (iflib_tx_credits_update(ctx, txq)) {
1039 /* some tx completed, increment avail */
1040 nic_i = txq->ift_cidx_processed;
1041 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1044 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1045 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1046 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1047 iflib_timer, txq, txq->ift_timer.c_cpu);
1053 * Reconcile kernel and user view of the receive ring.
1054 * Same as for the txsync, this routine must be efficient.
1055 * The caller guarantees a single invocations, but races against
1056 * the rest of the driver should be handled here.
1058 * On call, kring->rhead is the first packet that userspace wants
1059 * to keep, and kring->rcur is the wakeup point.
1060 * The kernel has previously reported packets up to kring->rtail.
1062 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1063 * of whether or not we received an interrupt.
1066 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1068 struct netmap_adapter *na = kring->na;
1069 struct netmap_ring *ring = kring->ring;
1070 uint32_t nm_i; /* index into the netmap ring */
1071 uint32_t nic_i; /* index into the NIC ring */
1073 u_int const lim = kring->nkr_num_slots - 1;
1074 u_int const head = kring->rhead;
1075 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1076 struct if_rxd_info ri;
1078 struct ifnet *ifp = na->ifp;
1079 if_ctx_t ctx = ifp->if_softc;
1080 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1081 iflib_fl_t fl = rxq->ifr_fl;
1083 return netmap_ring_reinit(kring);
1085 /* XXX check sync modes */
1086 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1087 if (fl->ifl_sds.ifsd_map == NULL)
1089 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1090 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1093 * First part: import newly received packets.
1095 * nm_i is the index of the next free slot in the netmap ring,
1096 * nic_i is the index of the next received packet in the NIC ring,
1097 * and they may differ in case if_init() has been called while
1098 * in netmap mode. For the receive ring we have
1100 * nic_i = rxr->next_check;
1101 * nm_i = kring->nr_hwtail (previous)
1103 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1105 * rxr->next_check is set to 0 on a ring reinit
1107 if (netmap_no_pendintr || force_update) {
1108 int crclen = iflib_crcstrip ? 0 : 4;
1111 for (i = 0; i < rxq->ifr_nfl; i++) {
1112 fl = &rxq->ifr_fl[i];
1113 nic_i = fl->ifl_cidx;
1114 nm_i = netmap_idx_n2k(kring, nic_i);
1115 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1116 for (n = 0; avail > 0; n++, avail--) {
1118 ri.iri_frags = rxq->ifr_frags;
1119 ri.iri_qsidx = kring->ring_id;
1120 ri.iri_ifp = ctx->ifc_ifp;
1121 ri.iri_cidx = nic_i;
1123 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1124 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1125 ring->slot[nm_i].flags = 0;
1126 if (fl->ifl_sds.ifsd_map)
1127 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1128 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1129 nm_i = nm_next(nm_i, lim);
1130 nic_i = nm_next(nic_i, lim);
1132 if (n) { /* update the state variables */
1133 if (netmap_no_pendintr && !force_update) {
1136 iflib_rx_miss_bufs += n;
1138 fl->ifl_cidx = nic_i;
1139 kring->nr_hwtail = nm_i;
1141 kring->nr_kflags &= ~NKR_PENDINTR;
1145 * Second part: skip past packets that userspace has released.
1146 * (kring->nr_hwcur to head excluded),
1147 * and make the buffers available for reception.
1148 * As usual nm_i is the index in the netmap ring,
1149 * nic_i is the index in the NIC ring, and
1150 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1152 /* XXX not sure how this will work with multiple free lists */
1153 nm_i = kring->nr_hwcur;
1155 return (netmap_fl_refill(rxq, kring, nm_i, false));
1159 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1161 struct ifnet *ifp = na->ifp;
1162 if_ctx_t ctx = ifp->if_softc;
1166 IFDI_INTR_ENABLE(ctx);
1168 IFDI_INTR_DISABLE(ctx);
1175 iflib_netmap_attach(if_ctx_t ctx)
1177 struct netmap_adapter na;
1178 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1180 bzero(&na, sizeof(na));
1182 na.ifp = ctx->ifc_ifp;
1183 na.na_flags = NAF_BDG_MAYSLEEP;
1184 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1185 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1187 na.num_tx_desc = scctx->isc_ntxd[0];
1188 na.num_rx_desc = scctx->isc_nrxd[0];
1189 na.nm_txsync = iflib_netmap_txsync;
1190 na.nm_rxsync = iflib_netmap_rxsync;
1191 na.nm_register = iflib_netmap_register;
1192 na.nm_intr = iflib_netmap_intr;
1193 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1194 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1195 return (netmap_attach(&na));
1199 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1201 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1202 struct netmap_slot *slot;
1204 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1207 if (txq->ift_sds.ifsd_map == NULL)
1210 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1213 * In netmap mode, set the map for the packet buffer.
1214 * NOTE: Some drivers (not this one) also need to set
1215 * the physical buffer address in the NIC ring.
1216 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1217 * netmap slot index, si
1219 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1220 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1225 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1227 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1228 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1229 struct netmap_slot *slot;
1232 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1235 nm_i = netmap_idx_n2k(kring, 0);
1236 netmap_fl_refill(rxq, kring, nm_i, true);
1240 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1242 struct netmap_kring *kring;
1244 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1246 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1247 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1248 netmap_tx_irq(ctx->ifc_ifp, txqid);
1249 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1253 *reset_on = hz / 1000;
1258 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1261 #define iflib_netmap_txq_init(ctx, txq)
1262 #define iflib_netmap_rxq_init(ctx, rxq)
1263 #define iflib_netmap_detach(ifp)
1265 #define iflib_netmap_attach(ctx) (0)
1266 #define netmap_rx_irq(ifp, qid, budget) (0)
1267 #define netmap_tx_irq(ifp, qid) do {} while (0)
1268 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1272 #if defined(__i386__) || defined(__amd64__)
1273 static __inline void
1276 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1278 static __inline void
1279 prefetch2cachelines(void *x)
1281 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1282 #if (CACHE_LINE_SIZE < 128)
1283 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1288 #define prefetch2cachelines(x)
1292 iflib_gen_mac(if_ctx_t ctx)
1296 char uuid[HOSTUUIDLEN+1];
1297 char buf[HOSTUUIDLEN+16];
1299 unsigned char digest[16];
1303 uuid[HOSTUUIDLEN] = 0;
1304 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1305 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1307 * Generate a pseudo-random, deterministic MAC
1308 * address based on the UUID and unit number.
1309 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1312 MD5Update(&mdctx, buf, strlen(buf));
1313 MD5Final(digest, &mdctx);
1324 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1328 fl = &rxq->ifr_fl[flid];
1329 iru->iru_paddrs = fl->ifl_bus_addrs;
1330 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1331 iru->iru_idxs = fl->ifl_rxd_idxs;
1332 iru->iru_qsidx = rxq->ifr_id;
1333 iru->iru_buf_size = fl->ifl_buf_size;
1334 iru->iru_flidx = fl->ifl_id;
1338 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1342 *(bus_addr_t *) arg = segs[0].ds_addr;
1346 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1349 if_shared_ctx_t sctx = ctx->ifc_sctx;
1350 device_t dev = ctx->ifc_dev;
1352 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1354 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1355 sctx->isc_q_align, 0, /* alignment, bounds */
1356 BUS_SPACE_MAXADDR, /* lowaddr */
1357 BUS_SPACE_MAXADDR, /* highaddr */
1358 NULL, NULL, /* filter, filterarg */
1361 size, /* maxsegsize */
1362 BUS_DMA_ALLOCNOW, /* flags */
1363 NULL, /* lockfunc */
1368 "%s: bus_dma_tag_create failed: %d\n",
1373 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1374 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1377 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1378 __func__, (uintmax_t)size, err);
1382 dma->idi_paddr = IF_BAD_DMA;
1383 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1384 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1385 if (err || dma->idi_paddr == IF_BAD_DMA) {
1387 "%s: bus_dmamap_load failed: %d\n",
1392 dma->idi_size = size;
1396 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1398 bus_dma_tag_destroy(dma->idi_tag);
1400 dma->idi_tag = NULL;
1406 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1409 iflib_dma_info_t *dmaiter;
1412 for (i = 0; i < count; i++, dmaiter++) {
1413 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1417 iflib_dma_free_multi(dmalist, i);
1422 iflib_dma_free(iflib_dma_info_t dma)
1424 if (dma->idi_tag == NULL)
1426 if (dma->idi_paddr != IF_BAD_DMA) {
1427 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1429 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1430 dma->idi_paddr = IF_BAD_DMA;
1432 if (dma->idi_vaddr != NULL) {
1433 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1434 dma->idi_vaddr = NULL;
1436 bus_dma_tag_destroy(dma->idi_tag);
1437 dma->idi_tag = NULL;
1441 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1444 iflib_dma_info_t *dmaiter = dmalist;
1446 for (i = 0; i < count; i++, dmaiter++)
1447 iflib_dma_free(*dmaiter);
1450 #ifdef EARLY_AP_STARTUP
1451 static const int iflib_started = 1;
1454 * We used to abuse the smp_started flag to decide if the queues have been
1455 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1456 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1457 * is set. Run a SYSINIT() strictly after that to just set a usable
1461 static int iflib_started;
1464 iflib_record_started(void *arg)
1469 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1470 iflib_record_started, NULL);
1474 iflib_fast_intr(void *arg)
1476 iflib_filter_info_t info = arg;
1477 struct grouptask *gtask = info->ifi_task;
1479 return (FILTER_HANDLED);
1481 DBG_COUNTER_INC(fast_intrs);
1482 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1483 return (FILTER_HANDLED);
1485 GROUPTASK_ENQUEUE(gtask);
1486 return (FILTER_HANDLED);
1490 iflib_fast_intr_rxtx(void *arg)
1492 iflib_filter_info_t info = arg;
1493 struct grouptask *gtask = info->ifi_task;
1494 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1495 if_ctx_t ctx = NULL;;
1499 return (FILTER_HANDLED);
1501 DBG_COUNTER_INC(fast_intrs);
1502 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1503 return (FILTER_HANDLED);
1505 MPASS(rxq->ifr_ntxqirq);
1506 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1507 qidx_t txqid = rxq->ifr_txqid[i];
1511 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1512 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1515 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1517 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1518 cidx = rxq->ifr_cq_cidx;
1520 cidx = rxq->ifr_fl[0].ifl_cidx;
1521 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1522 GROUPTASK_ENQUEUE(gtask);
1524 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1525 return (FILTER_HANDLED);
1530 iflib_fast_intr_ctx(void *arg)
1532 iflib_filter_info_t info = arg;
1533 struct grouptask *gtask = info->ifi_task;
1536 return (FILTER_HANDLED);
1538 DBG_COUNTER_INC(fast_intrs);
1539 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1540 return (FILTER_HANDLED);
1542 GROUPTASK_ENQUEUE(gtask);
1543 return (FILTER_HANDLED);
1547 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1548 driver_filter_t filter, driver_intr_t handler, void *arg,
1552 struct resource *res;
1554 device_t dev = ctx->ifc_dev;
1557 if (ctx->ifc_flags & IFC_LEGACY)
1558 flags |= RF_SHAREABLE;
1561 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1564 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1568 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1569 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1570 filter, handler, arg, &tag);
1573 "failed to setup interrupt for rid %d, name %s: %d\n",
1574 rid, name ? name : "unknown", rc);
1577 bus_describe_intr(dev, res, tag, "%s", name);
1584 /*********************************************************************
1586 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1587 * the information needed to transmit a packet on the wire. This is
1588 * called only once at attach, setup is done every reset.
1590 **********************************************************************/
1593 iflib_txsd_alloc(iflib_txq_t txq)
1595 if_ctx_t ctx = txq->ift_ctx;
1596 if_shared_ctx_t sctx = ctx->ifc_sctx;
1597 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1598 device_t dev = ctx->ifc_dev;
1599 bus_size_t tsomaxsize;
1600 int err, nsegments, ntsosegments;
1602 nsegments = scctx->isc_tx_nsegments;
1603 ntsosegments = scctx->isc_tx_tso_segments_max;
1604 tsomaxsize = scctx->isc_tx_tso_size_max;
1605 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1606 tsomaxsize += sizeof(struct ether_vlan_header);
1607 MPASS(scctx->isc_ntxd[0] > 0);
1608 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1609 MPASS(nsegments > 0);
1610 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1611 MPASS(ntsosegments > 0);
1612 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1616 * Setup DMA descriptor areas.
1618 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1619 1, 0, /* alignment, bounds */
1620 BUS_SPACE_MAXADDR, /* lowaddr */
1621 BUS_SPACE_MAXADDR, /* highaddr */
1622 NULL, NULL, /* filter, filterarg */
1623 sctx->isc_tx_maxsize, /* maxsize */
1624 nsegments, /* nsegments */
1625 sctx->isc_tx_maxsegsize, /* maxsegsize */
1627 NULL, /* lockfunc */
1628 NULL, /* lockfuncarg */
1629 &txq->ift_desc_tag))) {
1630 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1631 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1632 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1635 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) &
1636 (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1637 1, 0, /* alignment, bounds */
1638 BUS_SPACE_MAXADDR, /* lowaddr */
1639 BUS_SPACE_MAXADDR, /* highaddr */
1640 NULL, NULL, /* filter, filterarg */
1641 tsomaxsize, /* maxsize */
1642 ntsosegments, /* nsegments */
1643 sctx->isc_tso_maxsegsize,/* maxsegsize */
1645 NULL, /* lockfunc */
1646 NULL, /* lockfuncarg */
1647 &txq->ift_tso_desc_tag))) {
1648 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1652 if (!(txq->ift_sds.ifsd_flags =
1653 (uint8_t *) malloc(sizeof(uint8_t) *
1654 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1655 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1659 if (!(txq->ift_sds.ifsd_m =
1660 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1661 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1662 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1667 /* Create the descriptor buffer dma maps */
1668 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1669 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1672 if (!(txq->ift_sds.ifsd_map =
1673 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1674 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1679 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1680 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1682 device_printf(dev, "Unable to create TX DMA map\n");
1689 /* We free all, it handles case where we are in the middle */
1690 iflib_tx_structures_free(ctx);
1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1700 if (txq->ift_sds.ifsd_map != NULL)
1701 map = txq->ift_sds.ifsd_map[i];
1703 bus_dmamap_unload(txq->ift_desc_tag, map);
1704 bus_dmamap_destroy(txq->ift_desc_tag, map);
1705 txq->ift_sds.ifsd_map[i] = NULL;
1710 iflib_txq_destroy(iflib_txq_t txq)
1712 if_ctx_t ctx = txq->ift_ctx;
1714 for (int i = 0; i < txq->ift_size; i++)
1715 iflib_txsd_destroy(ctx, txq, i);
1716 if (txq->ift_sds.ifsd_map != NULL) {
1717 free(txq->ift_sds.ifsd_map, M_IFLIB);
1718 txq->ift_sds.ifsd_map = NULL;
1720 if (txq->ift_sds.ifsd_m != NULL) {
1721 free(txq->ift_sds.ifsd_m, M_IFLIB);
1722 txq->ift_sds.ifsd_m = NULL;
1724 if (txq->ift_sds.ifsd_flags != NULL) {
1725 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1726 txq->ift_sds.ifsd_flags = NULL;
1728 if (txq->ift_desc_tag != NULL) {
1729 bus_dma_tag_destroy(txq->ift_desc_tag);
1730 txq->ift_desc_tag = NULL;
1732 if (txq->ift_tso_desc_tag != NULL) {
1733 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1734 txq->ift_tso_desc_tag = NULL;
1739 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1743 mp = &txq->ift_sds.ifsd_m[i];
1747 if (txq->ift_sds.ifsd_map != NULL) {
1748 bus_dmamap_sync(txq->ift_desc_tag,
1749 txq->ift_sds.ifsd_map[i],
1750 BUS_DMASYNC_POSTWRITE);
1751 bus_dmamap_unload(txq->ift_desc_tag,
1752 txq->ift_sds.ifsd_map[i]);
1755 DBG_COUNTER_INC(tx_frees);
1760 iflib_txq_setup(iflib_txq_t txq)
1762 if_ctx_t ctx = txq->ift_ctx;
1763 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1764 iflib_dma_info_t di;
1767 /* Set number of descriptors available */
1768 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1769 /* XXX make configurable */
1770 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1773 txq->ift_cidx_processed = 0;
1774 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1775 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1777 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1778 bzero((void *)di->idi_vaddr, di->idi_size);
1780 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1781 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1782 bus_dmamap_sync(di->idi_tag, di->idi_map,
1783 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1787 /*********************************************************************
1789 * Allocate memory for rx_buffer structures. Since we use one
1790 * rx_buffer per received packet, the maximum number of rx_buffer's
1791 * that we'll need is equal to the number of receive descriptors
1792 * that we've allocated.
1794 **********************************************************************/
1796 iflib_rxsd_alloc(iflib_rxq_t rxq)
1798 if_ctx_t ctx = rxq->ifr_ctx;
1799 if_shared_ctx_t sctx = ctx->ifc_sctx;
1800 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1801 device_t dev = ctx->ifc_dev;
1805 MPASS(scctx->isc_nrxd[0] > 0);
1806 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1809 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1810 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1811 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1812 1, 0, /* alignment, bounds */
1813 BUS_SPACE_MAXADDR, /* lowaddr */
1814 BUS_SPACE_MAXADDR, /* highaddr */
1815 NULL, NULL, /* filter, filterarg */
1816 sctx->isc_rx_maxsize, /* maxsize */
1817 sctx->isc_rx_nsegments, /* nsegments */
1818 sctx->isc_rx_maxsegsize, /* maxsegsize */
1820 NULL, /* lockfunc */
1824 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1828 if (!(fl->ifl_sds.ifsd_flags =
1829 (uint8_t *) malloc(sizeof(uint8_t) *
1830 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1831 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1835 if (!(fl->ifl_sds.ifsd_m =
1836 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1837 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1838 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1842 if (!(fl->ifl_sds.ifsd_cl =
1843 (caddr_t *) malloc(sizeof(caddr_t) *
1844 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1845 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1850 /* Create the descriptor buffer dma maps */
1851 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1852 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1855 if (!(fl->ifl_sds.ifsd_map =
1856 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1857 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1862 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1863 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1865 device_printf(dev, "Unable to create RX buffer DMA map\n");
1874 iflib_rx_structures_free(ctx);
1880 * Internal service routines
1883 struct rxq_refill_cb_arg {
1885 bus_dma_segment_t seg;
1890 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1892 struct rxq_refill_cb_arg *cb_arg = arg;
1894 cb_arg->error = error;
1895 cb_arg->seg = segs[0];
1896 cb_arg->nseg = nseg;
1901 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1903 #define IS_DMAR(ctx) (0)
1907 * rxq_refill - refill an rxq free-buffer list
1908 * @ctx: the iflib context
1909 * @rxq: the free-list to refill
1910 * @n: the number of new buffers to allocate
1912 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1913 * The caller must assure that @n does not exceed the queue's capacity.
1916 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1919 int idx, frag_idx = fl->ifl_fragidx;
1920 int pidx = fl->ifl_pidx;
1924 struct if_rxd_update iru;
1925 bus_dmamap_t *sd_map;
1931 sd_m = fl->ifl_sds.ifsd_m;
1932 sd_map = fl->ifl_sds.ifsd_map;
1933 sd_cl = fl->ifl_sds.ifsd_cl;
1934 sd_flags = fl->ifl_sds.ifsd_flags;
1936 credits = fl->ifl_credits;
1940 MPASS(credits + n <= fl->ifl_size);
1942 if (pidx < fl->ifl_cidx)
1943 MPASS(pidx + n <= fl->ifl_cidx);
1944 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1945 MPASS(fl->ifl_gen == 0);
1946 if (pidx > fl->ifl_cidx)
1947 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1949 DBG_COUNTER_INC(fl_refills);
1951 DBG_COUNTER_INC(fl_refills_large);
1952 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1955 * We allocate an uninitialized mbuf + cluster, mbuf is
1956 * initialized after rx.
1958 * If the cluster is still set then we know a minimum sized packet was received
1960 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1961 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1962 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1963 if ((cl = sd_cl[frag_idx]) == NULL) {
1964 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1967 fl->ifl_cl_enqueued++;
1970 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1974 fl->ifl_m_enqueued++;
1977 DBG_COUNTER_INC(rx_allocs);
1978 #if defined(__i386__) || defined(__amd64__)
1979 if (!IS_DMAR(ctx)) {
1980 bus_addr = pmap_kextract((vm_offset_t)cl);
1984 struct rxq_refill_cb_arg cb_arg;
1987 MPASS(sd_map != NULL);
1988 MPASS(sd_map[frag_idx] != NULL);
1989 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1990 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1991 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1992 BUS_DMASYNC_PREREAD);
1994 if (err != 0 || cb_arg.error) {
1998 if (fl->ifl_zone == zone_pack)
1999 uma_zfree(fl->ifl_zone, cl);
2004 bus_addr = cb_arg.seg.ds_addr;
2006 bit_set(fl->ifl_rx_bitmap, frag_idx);
2007 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
2009 MPASS(sd_m[frag_idx] == NULL);
2010 sd_cl[frag_idx] = cl;
2012 fl->ifl_rxd_idxs[i] = frag_idx;
2013 fl->ifl_bus_addrs[i] = bus_addr;
2014 fl->ifl_vm_addrs[i] = cl;
2017 MPASS(credits <= fl->ifl_size);
2018 if (++idx == fl->ifl_size) {
2022 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2023 iru.iru_pidx = pidx;
2025 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2029 fl->ifl_credits = credits;
2035 iru.iru_pidx = pidx;
2037 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2039 fl->ifl_credits = credits;
2041 DBG_COUNTER_INC(rxd_flush);
2042 if (fl->ifl_pidx == 0)
2043 pidx = fl->ifl_size - 1;
2045 pidx = fl->ifl_pidx - 1;
2048 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2049 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2050 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2051 fl->ifl_fragidx = frag_idx;
2054 static __inline void
2055 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2057 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2058 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2060 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2063 MPASS(fl->ifl_credits <= fl->ifl_size);
2064 MPASS(reclaimable == delta);
2066 if (reclaimable > 0)
2067 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2071 iflib_fl_bufs_free(iflib_fl_t fl)
2073 iflib_dma_info_t idi = fl->ifl_ifdi;
2076 for (i = 0; i < fl->ifl_size; i++) {
2077 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2078 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
2079 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2081 if (*sd_flags & RX_SW_DESC_INUSE) {
2082 if (fl->ifl_sds.ifsd_map != NULL) {
2083 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
2084 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2085 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
2086 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2088 if (*sd_m != NULL) {
2089 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2090 uma_zfree(zone_mbuf, *sd_m);
2093 uma_zfree(fl->ifl_zone, *sd_cl);
2096 MPASS(*sd_cl == NULL);
2097 MPASS(*sd_m == NULL);
2100 fl->ifl_m_dequeued++;
2101 fl->ifl_cl_dequeued++;
2107 for (i = 0; i < fl->ifl_size; i++) {
2108 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2109 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2110 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2114 * Reset free list values
2116 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2117 bzero(idi->idi_vaddr, idi->idi_size);
2120 /*********************************************************************
2122 * Initialize a receive ring and its buffers.
2124 **********************************************************************/
2126 iflib_fl_setup(iflib_fl_t fl)
2128 iflib_rxq_t rxq = fl->ifl_rxq;
2129 if_ctx_t ctx = rxq->ifr_ctx;
2130 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2132 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2134 ** Free current RX buffer structs and their mbufs
2136 iflib_fl_bufs_free(fl);
2137 /* Now replenish the mbufs */
2138 MPASS(fl->ifl_credits == 0);
2140 * XXX don't set the max_frame_size to larger
2141 * than the hardware can handle
2143 if (sctx->isc_max_frame_size <= 2048)
2144 fl->ifl_buf_size = MCLBYTES;
2145 #ifndef CONTIGMALLOC_WORKS
2147 fl->ifl_buf_size = MJUMPAGESIZE;
2149 else if (sctx->isc_max_frame_size <= 4096)
2150 fl->ifl_buf_size = MJUMPAGESIZE;
2151 else if (sctx->isc_max_frame_size <= 9216)
2152 fl->ifl_buf_size = MJUM9BYTES;
2154 fl->ifl_buf_size = MJUM16BYTES;
2156 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2157 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2158 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2159 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2162 /* avoid pre-allocating zillions of clusters to an idle card
2163 * potentially speeding up attach
2165 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2166 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2167 if (min(128, fl->ifl_size) != fl->ifl_credits)
2173 MPASS(fl->ifl_ifdi != NULL);
2174 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2175 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2179 /*********************************************************************
2181 * Free receive ring data structures
2183 **********************************************************************/
2185 iflib_rx_sds_free(iflib_rxq_t rxq)
2190 if (rxq->ifr_fl != NULL) {
2191 for (i = 0; i < rxq->ifr_nfl; i++) {
2192 fl = &rxq->ifr_fl[i];
2193 if (fl->ifl_desc_tag != NULL) {
2194 bus_dma_tag_destroy(fl->ifl_desc_tag);
2195 fl->ifl_desc_tag = NULL;
2197 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2198 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2199 /* XXX destroy maps first */
2200 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2201 fl->ifl_sds.ifsd_m = NULL;
2202 fl->ifl_sds.ifsd_cl = NULL;
2203 fl->ifl_sds.ifsd_map = NULL;
2205 free(rxq->ifr_fl, M_IFLIB);
2207 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2212 * MI independent logic
2216 iflib_timer(void *arg)
2218 iflib_txq_t txq = arg;
2219 if_ctx_t ctx = txq->ift_ctx;
2220 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2221 uint64_t this_tick = ticks;
2222 uint32_t reset_on = hz / 2;
2224 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2227 ** Check on the state of the TX queue(s), this
2228 ** can be done without the lock because its RO
2229 ** and the HUNG state will be static if set.
2231 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2232 txq->ift_last_timer_tick = this_tick;
2233 IFDI_TIMER(ctx, txq->ift_id);
2234 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2235 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2236 (sctx->isc_pause_frames == 0)))
2239 if (ifmp_ring_is_stalled(txq->ift_br))
2240 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2241 txq->ift_cleaned_prev = txq->ift_cleaned;
2244 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2245 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2247 /* handle any laggards */
2248 if (txq->ift_db_pending)
2249 GROUPTASK_ENQUEUE(&txq->ift_task);
2251 sctx->isc_pause_frames = 0;
2252 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2253 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2256 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2257 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2259 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2260 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2261 iflib_admin_intr_deferred(ctx);
2266 iflib_init_locked(if_ctx_t ctx)
2268 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2269 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2270 if_t ifp = ctx->ifc_ifp;
2274 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2277 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2278 IFDI_INTR_DISABLE(ctx);
2280 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2281 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2282 /* Set hardware offload abilities */
2283 if_clearhwassist(ifp);
2284 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2285 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2286 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2287 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2288 if (if_getcapenable(ifp) & IFCAP_TSO4)
2289 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2290 if (if_getcapenable(ifp) & IFCAP_TSO6)
2291 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2293 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2295 callout_stop(&txq->ift_timer);
2296 CALLOUT_UNLOCK(txq);
2297 iflib_netmap_txq_init(ctx, txq);
2300 i = if_getdrvflags(ifp);
2303 MPASS(if_getdrvflags(ifp) == i);
2304 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2305 /* XXX this should really be done on a per-queue basis */
2306 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2307 MPASS(rxq->ifr_id == i);
2308 iflib_netmap_rxq_init(ctx, rxq);
2311 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2312 if (iflib_fl_setup(fl)) {
2313 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2319 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2320 IFDI_INTR_ENABLE(ctx);
2321 txq = ctx->ifc_txqs;
2322 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2323 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2324 txq->ift_timer.c_cpu);
2328 iflib_media_change(if_t ifp)
2330 if_ctx_t ctx = if_getsoftc(ifp);
2334 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2335 iflib_init_locked(ctx);
2341 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2343 if_ctx_t ctx = if_getsoftc(ifp);
2346 IFDI_UPDATE_ADMIN_STATUS(ctx);
2347 IFDI_MEDIA_STATUS(ctx, ifmr);
2352 iflib_stop(if_ctx_t ctx)
2354 iflib_txq_t txq = ctx->ifc_txqs;
2355 iflib_rxq_t rxq = ctx->ifc_rxqs;
2356 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2357 iflib_dma_info_t di;
2361 /* Tell the stack that the interface is no longer active */
2362 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2364 IFDI_INTR_DISABLE(ctx);
2369 iflib_debug_reset();
2370 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2371 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2372 /* make sure all transmitters have completed before proceeding XXX */
2375 callout_stop(&txq->ift_timer);
2376 CALLOUT_UNLOCK(txq);
2378 /* clean any enqueued buffers */
2379 iflib_ifmp_purge(txq);
2380 /* Free any existing tx buffers. */
2381 for (j = 0; j < txq->ift_size; j++) {
2382 iflib_txsd_free(ctx, txq, j);
2384 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2385 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2386 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2387 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2388 txq->ift_pullups = 0;
2389 ifmp_ring_reset_stats(txq->ift_br);
2390 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2391 bzero((void *)di->idi_vaddr, di->idi_size);
2393 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2394 /* make sure all transmitters have completed before proceeding XXX */
2396 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++)
2397 bzero((void *)di->idi_vaddr, di->idi_size);
2398 /* also resets the free lists pidx/cidx */
2399 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2400 iflib_fl_bufs_free(fl);
2404 static inline caddr_t
2405 calc_next_rxd(iflib_fl_t fl, int cidx)
2409 caddr_t start, end, cur, next;
2411 nrxd = fl->ifl_size;
2412 size = fl->ifl_rxd_size;
2413 start = fl->ifl_ifdi->idi_vaddr;
2415 if (__predict_false(size == 0))
2417 cur = start + size*cidx;
2418 end = start + size*nrxd;
2419 next = CACHE_PTR_NEXT(cur);
2420 return (next < end ? next : start);
2424 prefetch_pkts(iflib_fl_t fl, int cidx)
2427 int nrxd = fl->ifl_size;
2431 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2432 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2433 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2434 next_rxd = calc_next_rxd(fl, cidx);
2436 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2437 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2438 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2439 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2440 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2441 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2442 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2443 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2447 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2452 iflib_dma_info_t di;
2456 flid = irf->irf_flid;
2457 cidx = irf->irf_idx;
2458 fl = &rxq->ifr_fl[flid];
2460 sd->ifsd_cidx = cidx;
2461 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2462 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2465 fl->ifl_m_dequeued++;
2467 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2468 prefetch_pkts(fl, cidx);
2469 if (fl->ifl_sds.ifsd_map != NULL) {
2470 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2471 prefetch(&fl->ifl_sds.ifsd_map[next]);
2472 map = fl->ifl_sds.ifsd_map[cidx];
2474 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2475 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2476 bus_dmamap_sync(di->idi_tag, di->idi_map,
2477 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2479 /* not valid assert if bxe really does SGE from non-contiguous elements */
2480 MPASS(fl->ifl_cidx == cidx);
2482 bus_dmamap_unload(fl->ifl_desc_tag, map);
2484 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2485 if (__predict_false(fl->ifl_cidx == 0))
2488 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2490 bit_clear(fl->ifl_rx_bitmap, cidx);
2493 static struct mbuf *
2494 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2496 int i, padlen , flags;
2497 struct mbuf *m, *mh, *mt;
2503 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2505 MPASS(*sd->ifsd_cl != NULL);
2506 MPASS(*sd->ifsd_m != NULL);
2508 /* Don't include zero-length frags */
2509 if (ri->iri_frags[i].irf_len == 0) {
2510 /* XXX we can save the cluster here, but not the mbuf */
2511 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2512 m_free(*sd->ifsd_m);
2519 flags = M_PKTHDR|M_EXT;
2521 padlen = ri->iri_pad;
2526 /* assuming padding is only on the first fragment */
2530 *sd->ifsd_cl = NULL;
2532 /* Can these two be made one ? */
2533 m_init(m, M_NOWAIT, MT_DATA, flags);
2534 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2536 * These must follow m_init and m_cljset
2538 m->m_data += padlen;
2539 ri->iri_len -= padlen;
2540 m->m_len = ri->iri_frags[i].irf_len;
2541 } while (++i < ri->iri_nfrags);
2547 * Process one software descriptor
2549 static struct mbuf *
2550 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2555 /* should I merge this back in now that the two paths are basically duplicated? */
2556 if (ri->iri_nfrags == 1 &&
2557 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2558 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2561 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2562 #ifndef __NO_STRICT_ALIGNMENT
2566 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2567 m->m_len = ri->iri_frags[0].irf_len;
2569 m = assemble_segments(rxq, ri, &sd);
2571 m->m_pkthdr.len = ri->iri_len;
2572 m->m_pkthdr.rcvif = ri->iri_ifp;
2573 m->m_flags |= ri->iri_flags;
2574 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2575 m->m_pkthdr.flowid = ri->iri_flowid;
2576 M_HASHTYPE_SET(m, ri->iri_rsstype);
2577 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2578 m->m_pkthdr.csum_data = ri->iri_csum_data;
2582 #if defined(INET6) || defined(INET)
2584 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2586 CURVNET_SET(lc->ifp->if_vnet);
2588 *v6 = VNET(ip6_forwarding);
2591 *v4 = VNET(ipforwarding);
2597 * Returns true if it's possible this packet could be LROed.
2598 * if it returns false, it is guaranteed that tcp_lro_rx()
2599 * would not return zero.
2602 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2604 struct ether_header *eh;
2607 eh = mtod(m, struct ether_header *);
2608 eh_type = ntohs(eh->ether_type);
2611 case ETHERTYPE_IPV6:
2612 return !v6_forwarding;
2616 return !v4_forwarding;
2624 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2630 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2632 if_ctx_t ctx = rxq->ifr_ctx;
2633 if_shared_ctx_t sctx = ctx->ifc_sctx;
2634 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2637 struct if_rxd_info ri;
2638 int err, budget_left, rx_bytes, rx_pkts;
2642 bool v4_forwarding, v6_forwarding, lro_possible;
2645 * XXX early demux data packets so that if_input processing only handles
2646 * acks in interrupt context
2648 struct mbuf *m, *mh, *mt, *mf;
2650 lro_possible = v4_forwarding = v6_forwarding = false;
2654 rx_pkts = rx_bytes = 0;
2655 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2656 cidxp = &rxq->ifr_cq_cidx;
2658 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2659 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2660 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2661 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2662 DBG_COUNTER_INC(rx_unavail);
2666 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2667 if (__predict_false(!CTX_ACTIVE(ctx))) {
2668 DBG_COUNTER_INC(rx_ctx_inactive);
2672 * Reset client set fields to their default values
2675 ri.iri_qsidx = rxq->ifr_id;
2676 ri.iri_cidx = *cidxp;
2678 ri.iri_frags = rxq->ifr_frags;
2679 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2683 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2684 *cidxp = ri.iri_cidx;
2685 /* Update our consumer index */
2686 /* XXX NB: shurd - check if this is still safe */
2687 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2688 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2689 rxq->ifr_cq_gen = 0;
2691 /* was this only a completion queue message? */
2692 if (__predict_false(ri.iri_nfrags == 0))
2695 MPASS(ri.iri_nfrags != 0);
2696 MPASS(ri.iri_len != 0);
2698 /* will advance the cidx on the corresponding free lists */
2699 m = iflib_rxd_pkt_get(rxq, &ri);
2702 if (avail == 0 && budget_left)
2703 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2705 if (__predict_false(m == NULL)) {
2706 DBG_COUNTER_INC(rx_mbuf_null);
2709 /* imm_pkt: -- cxgb */
2717 /* make sure that we can refill faster than drain */
2718 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2719 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2721 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2723 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2725 while (mh != NULL) {
2728 m->m_nextpkt = NULL;
2729 #ifndef __NO_STRICT_ALIGNMENT
2730 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2733 rx_bytes += m->m_pkthdr.len;
2735 #if defined(INET6) || defined(INET)
2737 if (!lro_possible) {
2738 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2739 if (lro_possible && mf != NULL) {
2740 ifp->if_input(ifp, mf);
2741 DBG_COUNTER_INC(rx_if_input);
2745 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2746 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2747 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2753 ifp->if_input(ifp, m);
2754 DBG_COUNTER_INC(rx_if_input);
2765 ifp->if_input(ifp, mf);
2766 DBG_COUNTER_INC(rx_if_input);
2769 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2770 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2773 * Flush any outstanding LRO work
2775 #if defined(INET6) || defined(INET)
2776 tcp_lro_flush_all(&rxq->ifr_lc);
2780 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2783 ctx->ifc_flags |= IFC_DO_RESET;
2784 iflib_admin_intr_deferred(ctx);
2789 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2790 static inline qidx_t
2791 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2793 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2794 qidx_t minthresh = txq->ift_size / 8;
2795 if (in_use > 4*minthresh)
2796 return (notify_count);
2797 if (in_use > 2*minthresh)
2798 return (notify_count >> 1);
2799 if (in_use > minthresh)
2800 return (notify_count >> 3);
2804 static inline qidx_t
2805 txq_max_rs_deferred(iflib_txq_t txq)
2807 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2808 qidx_t minthresh = txq->ift_size / 8;
2809 if (txq->ift_in_use > 4*minthresh)
2810 return (notify_count);
2811 if (txq->ift_in_use > 2*minthresh)
2812 return (notify_count >> 1);
2813 if (txq->ift_in_use > minthresh)
2814 return (notify_count >> 2);
2818 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2819 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2821 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2822 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2823 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2825 /* forward compatibility for cxgb */
2826 #define FIRST_QSET(ctx) 0
2827 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2828 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2829 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2830 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2832 /* XXX we should be setting this to something other than zero */
2833 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2834 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2837 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2843 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2844 if (ring || txq->ift_db_pending >= max) {
2845 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2846 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2847 txq->ift_db_pending = txq->ift_npending = 0;
2855 print_pkt(if_pkt_info_t pi)
2857 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2858 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2859 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2860 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2861 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2862 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2866 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2867 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2868 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2869 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2872 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2874 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2875 struct ether_vlan_header *eh;
2879 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2880 M_WRITABLE(m) == 0) {
2881 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2890 * Determine where frame payload starts.
2891 * Jump over vlan headers if already present,
2892 * helpful for QinQ too.
2894 if (__predict_false(m->m_len < sizeof(*eh))) {
2896 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2899 eh = mtod(m, struct ether_vlan_header *);
2900 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2901 pi->ipi_etype = ntohs(eh->evl_proto);
2902 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2904 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2905 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2908 switch (pi->ipi_etype) {
2912 struct ip *ip = NULL;
2913 struct tcphdr *th = NULL;
2916 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2917 if (__predict_false(m->m_len < minthlen)) {
2919 * if this code bloat is causing too much of a hit
2920 * move it to a separate function and mark it noinline
2922 if (m->m_len == pi->ipi_ehdrlen) {
2925 if (n->m_len >= sizeof(*ip)) {
2926 ip = (struct ip *)n->m_data;
2927 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2928 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2931 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2933 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2937 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2939 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2940 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2941 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2944 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2945 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2946 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2948 pi->ipi_ip_hlen = ip->ip_hl << 2;
2949 pi->ipi_ipproto = ip->ip_p;
2950 pi->ipi_flags |= IPI_TX_IPV4;
2952 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2955 /* TCP checksum offload may require TCP header length */
2956 if (IS_TX_OFFLOAD4(pi)) {
2957 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2958 if (__predict_false(th == NULL)) {
2960 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2962 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2964 pi->ipi_tcp_hflags = th->th_flags;
2965 pi->ipi_tcp_hlen = th->th_off << 2;
2966 pi->ipi_tcp_seq = th->th_seq;
2969 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2971 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2972 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2973 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2974 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2976 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2984 case ETHERTYPE_IPV6:
2986 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2988 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2990 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2991 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2994 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2996 /* XXX-BZ this will go badly in case of ext hdrs. */
2997 pi->ipi_ipproto = ip6->ip6_nxt;
2998 pi->ipi_flags |= IPI_TX_IPV6;
3000 /* TCP checksum offload may require TCP header length */
3001 if (IS_TX_OFFLOAD6(pi)) {
3002 if (pi->ipi_ipproto == IPPROTO_TCP) {
3003 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3005 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3008 pi->ipi_tcp_hflags = th->th_flags;
3009 pi->ipi_tcp_hlen = th->th_off << 2;
3010 pi->ipi_tcp_seq = th->th_seq;
3013 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3016 * The corresponding flag is set by the stack in the IPv4
3017 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
3018 * So, set it here because the rest of the flow requires it.
3020 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3021 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3022 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3029 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3030 pi->ipi_ip_hlen = 0;
3038 static __noinline struct mbuf *
3039 collapse_pkthdr(struct mbuf *m0)
3041 struct mbuf *m, *m_next, *tmp;
3045 while (m_next != NULL && m_next->m_len == 0) {
3049 m_next = m_next->m_next;
3055 if ((m_next->m_flags & M_EXT) == 0) {
3056 m = m_defrag(m, M_NOWAIT);
3058 tmp = m_next->m_next;
3059 memcpy(m_next, m, MPKTHSIZE);
3067 * If dodgy hardware rejects the scatter gather chain we've handed it
3068 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3071 static __noinline struct mbuf *
3072 iflib_remove_mbuf(iflib_txq_t txq)
3075 struct mbuf *m, *mh, **ifsd_m;
3077 pidx = txq->ift_pidx;
3078 ifsd_m = txq->ift_sds.ifsd_m;
3079 ntxd = txq->ift_size;
3080 mh = m = ifsd_m[pidx];
3081 ifsd_m[pidx] = NULL;
3083 txq->ift_dequeued++;
3088 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
3090 txq->ift_dequeued++;
3099 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
3100 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
3101 int max_segs, int flags)
3104 if_shared_ctx_t sctx;
3105 if_softc_ctx_t scctx;
3106 int i, next, pidx, err, ntxd, count;
3107 struct mbuf *m, *tmp, **ifsd_m;
3112 * Please don't ever do this
3114 if (__predict_false(m->m_len == 0))
3115 *m0 = collapse_pkthdr(m);
3118 sctx = ctx->ifc_sctx;
3119 scctx = &ctx->ifc_softc_ctx;
3120 ifsd_m = txq->ift_sds.ifsd_m;
3121 ntxd = txq->ift_size;
3122 pidx = txq->ift_pidx;
3124 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3126 err = bus_dmamap_load_mbuf_sg(tag, map,
3127 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3130 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3134 if (__predict_false(m->m_len <= 0)) {
3143 } while (m != NULL);
3144 if (count > *nsegs) {
3146 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3152 next = (pidx + count) & (ntxd-1);
3153 MPASS(ifsd_m[next] == NULL);
3158 } while (m != NULL);
3160 int buflen, sgsize, maxsegsz, max_sgsize;
3166 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3167 maxsegsz = scctx->isc_tx_tso_segsize_max;
3169 maxsegsz = sctx->isc_tx_maxsegsize;
3172 if (__predict_false(m->m_len <= 0)) {
3180 vaddr = (vm_offset_t)m->m_data;
3182 * see if we can't be smarter about physically
3183 * contiguous mappings
3185 next = (pidx + count) & (ntxd-1);
3186 MPASS(ifsd_m[next] == NULL);
3188 txq->ift_enqueued++;
3191 while (buflen > 0) {
3194 max_sgsize = MIN(buflen, maxsegsz);
3195 curaddr = pmap_kextract(vaddr);
3196 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3197 sgsize = MIN(sgsize, max_sgsize);
3198 segs[i].ds_addr = curaddr;
3199 segs[i].ds_len = sgsize;
3207 } while (m != NULL);
3212 *m0 = iflib_remove_mbuf(txq);
3216 static inline caddr_t
3217 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3221 caddr_t start, end, cur, next;
3223 ntxd = txq->ift_size;
3224 size = txq->ift_txd_size[qid];
3225 start = txq->ift_ifdi[qid].idi_vaddr;
3227 if (__predict_false(size == 0))
3229 cur = start + size*cidx;
3230 end = start + size*ntxd;
3231 next = CACHE_PTR_NEXT(cur);
3232 return (next < end ? next : start);
3236 * Pad an mbuf to ensure a minimum ethernet frame size.
3237 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3239 static __noinline int
3240 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3243 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3244 * and ARP message is the smallest common payload I can think of
3246 static char pad[18]; /* just zeros */
3248 struct mbuf *new_head;
3250 if (!M_WRITABLE(*m_head)) {
3251 new_head = m_dup(*m_head, M_NOWAIT);
3252 if (new_head == NULL) {
3254 device_printf(dev, "cannot pad short frame, m_dup() failed");
3255 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3262 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3263 n > 0; n -= sizeof(pad))
3264 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3269 device_printf(dev, "cannot pad short frame\n");
3270 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3278 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3281 if_shared_ctx_t sctx;
3282 if_softc_ctx_t scctx;
3283 bus_dma_segment_t *segs;
3284 struct mbuf *m_head;
3287 struct if_pkt_info pi;
3289 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3290 bus_dma_tag_t desc_tag;
3293 sctx = ctx->ifc_sctx;
3294 scctx = &ctx->ifc_softc_ctx;
3295 segs = txq->ift_segs;
3296 ntxd = txq->ift_size;
3301 * If we're doing TSO the next descriptor to clean may be quite far ahead
3303 cidx = txq->ift_cidx;
3304 pidx = txq->ift_pidx;
3305 if (ctx->ifc_flags & IFC_PREFETCH) {
3306 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3307 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3308 next_txd = calc_next_txd(txq, cidx, 0);
3312 /* prefetch the next cache line of mbuf pointers and flags */
3313 prefetch(&txq->ift_sds.ifsd_m[next]);
3314 if (txq->ift_sds.ifsd_map != NULL) {
3315 prefetch(&txq->ift_sds.ifsd_map[next]);
3316 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3317 prefetch(&txq->ift_sds.ifsd_flags[next]);
3319 } else if (txq->ift_sds.ifsd_map != NULL)
3320 map = txq->ift_sds.ifsd_map[pidx];
3322 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3323 desc_tag = txq->ift_tso_desc_tag;
3324 max_segs = scctx->isc_tx_tso_segments_max;
3325 MPASS(desc_tag != NULL);
3326 MPASS(max_segs > 0);
3328 desc_tag = txq->ift_desc_tag;
3329 max_segs = scctx->isc_tx_nsegments;
3331 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3332 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3333 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3340 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3342 pi.ipi_qsidx = txq->ift_id;
3343 pi.ipi_len = m_head->m_pkthdr.len;
3344 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3345 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3347 /* deliberate bitwise OR to make one condition */
3348 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3349 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3355 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3357 if (__predict_false(err)) {
3360 /* try collapse once and defrag once */
3362 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3363 /* try defrag if collapsing fails */
3368 m_head = m_defrag(*m_headp, M_NOWAIT);
3370 if (__predict_false(m_head == NULL))
3372 txq->ift_mbuf_defrag++;
3377 txq->ift_no_tx_dma_setup++;
3380 txq->ift_no_tx_dma_setup++;
3382 DBG_COUNTER_INC(tx_frees);
3386 txq->ift_map_failed++;
3387 DBG_COUNTER_INC(encap_load_mbuf_fail);
3392 * XXX assumes a 1 to 1 relationship between segments and
3393 * descriptors - this does not hold true on all drivers, e.g.
3396 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3397 txq->ift_no_desc_avail++;
3399 bus_dmamap_unload(desc_tag, map);
3400 DBG_COUNTER_INC(encap_txq_avail_fail);
3401 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3402 GROUPTASK_ENQUEUE(&txq->ift_task);
3406 * On Intel cards we can greatly reduce the number of TX interrupts
3407 * we see by only setting report status on every Nth descriptor.
3408 * However, this also means that the driver will need to keep track
3409 * of the descriptors that RS was set on to check them for the DD bit.
3411 txq->ift_rs_pending += nsegs + 1;
3412 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3413 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3414 pi.ipi_flags |= IPI_TX_INTR;
3415 txq->ift_rs_pending = 0;
3419 pi.ipi_nsegs = nsegs;
3421 MPASS(pidx >= 0 && pidx < txq->ift_size);
3426 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3427 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3429 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3430 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3431 DBG_COUNTER_INC(tx_encap);
3432 MPASS(pi.ipi_new_pidx < txq->ift_size);
3434 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3435 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3436 ndesc += txq->ift_size;
3440 * drivers can need as many as
3443 MPASS(ndesc <= pi.ipi_nsegs + 2);
3444 MPASS(pi.ipi_new_pidx != pidx);
3446 txq->ift_in_use += ndesc;
3449 * We update the last software descriptor again here because there may
3450 * be a sentinel and/or there may be more mbufs than segments
3452 txq->ift_pidx = pi.ipi_new_pidx;
3453 txq->ift_npending += pi.ipi_ndescs;
3455 *m_headp = m_head = iflib_remove_mbuf(txq);
3457 txq->ift_txd_encap_efbig++;
3463 DBG_COUNTER_INC(encap_txd_encap_fail);
3469 txq->ift_mbuf_defrag_failed++;
3470 txq->ift_map_failed++;
3472 DBG_COUNTER_INC(tx_frees);
3478 iflib_tx_desc_free(iflib_txq_t txq, int n)
3481 uint32_t qsize, cidx, mask, gen;
3482 struct mbuf *m, **ifsd_m;
3483 uint8_t *ifsd_flags;
3484 bus_dmamap_t *ifsd_map;
3487 cidx = txq->ift_cidx;
3489 qsize = txq->ift_size;
3491 hasmap = txq->ift_sds.ifsd_map != NULL;
3492 ifsd_flags = txq->ift_sds.ifsd_flags;
3493 ifsd_m = txq->ift_sds.ifsd_m;
3494 ifsd_map = txq->ift_sds.ifsd_map;
3495 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3499 prefetch(ifsd_m[(cidx + 3) & mask]);
3500 prefetch(ifsd_m[(cidx + 4) & mask]);
3502 if (ifsd_m[cidx] != NULL) {
3503 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3504 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3505 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3507 * does it matter if it's not the TSO tag? If so we'll
3508 * have to add the type to flags
3510 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3511 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3513 if ((m = ifsd_m[cidx]) != NULL) {
3514 /* XXX we don't support any drivers that batch packets yet */
3515 MPASS(m->m_nextpkt == NULL);
3516 /* if the number of clusters exceeds the number of segments
3517 * there won't be space on the ring to save a pointer to each
3518 * cluster so we simply free the list here
3520 if (m->m_flags & M_TOOBIG) {
3525 ifsd_m[cidx] = NULL;
3527 txq->ift_dequeued++;
3529 DBG_COUNTER_INC(tx_frees);
3532 if (__predict_false(++cidx == qsize)) {
3537 txq->ift_cidx = cidx;
3542 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3545 if_ctx_t ctx = txq->ift_ctx;
3547 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3548 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3551 * Need a rate-limiting check so that this isn't called every time
3553 iflib_tx_credits_update(ctx, txq);
3554 reclaim = DESC_RECLAIMABLE(txq);
3556 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3558 if (iflib_verbose_debug) {
3559 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3560 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3567 iflib_tx_desc_free(txq, reclaim);
3568 txq->ift_cleaned += reclaim;
3569 txq->ift_in_use -= reclaim;
3574 static struct mbuf **
3575 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3578 struct mbuf **items;
3581 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3582 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3584 prefetch(items[(cidx + offset) & (size-1)]);
3585 if (remaining > 1) {
3586 prefetch2cachelines(&items[next]);
3587 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3588 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3589 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3591 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3595 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3598 ifmp_ring_check_drainage(txq->ift_br, budget);
3602 iflib_txq_can_drain(struct ifmp_ring *r)
3604 iflib_txq_t txq = r->cookie;
3605 if_ctx_t ctx = txq->ift_ctx;
3607 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3608 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3612 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3614 iflib_txq_t txq = r->cookie;
3615 if_ctx_t ctx = txq->ift_ctx;
3616 struct ifnet *ifp = ctx->ifc_ifp;
3617 struct mbuf **mp, *m;
3618 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3619 int reclaimed, err, in_use_prev, desc_used;
3620 bool do_prefetch, ring, rang;
3622 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3623 !LINK_ACTIVE(ctx))) {
3624 DBG_COUNTER_INC(txq_drain_notready);
3627 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3628 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3629 avail = IDXDIFF(pidx, cidx, r->size);
3630 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3631 DBG_COUNTER_INC(txq_drain_flushing);
3632 for (i = 0; i < avail; i++) {
3633 m_free(r->items[(cidx + i) & (r->size-1)]);
3634 r->items[(cidx + i) & (r->size-1)] = NULL;
3639 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3640 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3642 callout_stop(&txq->ift_timer);
3643 CALLOUT_UNLOCK(txq);
3644 DBG_COUNTER_INC(txq_drain_oactive);
3648 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3649 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3650 count = MIN(avail, TX_BATCH_SIZE);
3652 if (iflib_verbose_debug)
3653 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3654 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3656 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3657 avail = TXQ_AVAIL(txq);
3659 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3660 int rem = do_prefetch ? count - i : 0;
3662 mp = _ring_peek_one(r, cidx, i, rem);
3663 MPASS(mp != NULL && *mp != NULL);
3664 if (__predict_false(*mp == (struct mbuf *)txq)) {
3669 in_use_prev = txq->ift_in_use;
3670 err = iflib_encap(txq, mp);
3671 if (__predict_false(err)) {
3672 DBG_COUNTER_INC(txq_drain_encapfail);
3673 /* no room - bail out */
3677 DBG_COUNTER_INC(txq_drain_encapfail);
3678 /* we can't send this packet - skip it */
3684 DBG_COUNTER_INC(tx_sent);
3685 bytes_sent += m->m_pkthdr.len;
3686 mcast_sent += !!(m->m_flags & M_MCAST);
3687 avail = TXQ_AVAIL(txq);
3689 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3690 desc_used += (txq->ift_in_use - in_use_prev);
3691 ETHER_BPF_MTAP(ifp, m);
3692 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3694 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3697 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3698 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3699 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3700 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3701 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3703 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3705 if (iflib_verbose_debug)
3706 printf("consumed=%d\n", consumed);
3712 iflib_txq_drain_always(struct ifmp_ring *r)
3718 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3726 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3728 callout_stop(&txq->ift_timer);
3729 CALLOUT_UNLOCK(txq);
3731 avail = IDXDIFF(pidx, cidx, r->size);
3732 for (i = 0; i < avail; i++) {
3733 mp = _ring_peek_one(r, cidx, i, avail - i);
3734 if (__predict_false(*mp == (struct mbuf *)txq))
3738 MPASS(ifmp_ring_is_stalled(r) == 0);
3743 iflib_ifmp_purge(iflib_txq_t txq)
3745 struct ifmp_ring *r;
3748 r->drain = iflib_txq_drain_free;
3749 r->can_drain = iflib_txq_drain_always;
3751 ifmp_ring_check_drainage(r, r->size);
3753 r->drain = iflib_txq_drain;
3754 r->can_drain = iflib_txq_can_drain;
3758 _task_fn_tx(void *context)
3760 iflib_txq_t txq = context;
3761 if_ctx_t ctx = txq->ift_ctx;
3762 struct ifnet *ifp = ctx->ifc_ifp;
3763 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3765 #ifdef IFLIB_DIAGNOSTICS
3766 txq->ift_cpu_exec_count[curcpu]++;
3768 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3770 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3771 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3772 netmap_tx_irq(ifp, txq->ift_id);
3773 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3776 if (txq->ift_db_pending)
3777 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3779 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3781 * When abdicating, we always need to check drainage, not just when we don't enqueue
3784 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3785 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3786 if (ctx->ifc_flags & IFC_LEGACY)
3787 IFDI_INTR_ENABLE(ctx);
3792 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3793 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3798 _task_fn_rx(void *context)
3800 iflib_rxq_t rxq = context;
3801 if_ctx_t ctx = rxq->ifr_ctx;
3805 #ifdef IFLIB_DIAGNOSTICS
3806 rxq->ifr_cpu_exec_count[curcpu]++;
3808 DBG_COUNTER_INC(task_fn_rxs);
3809 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3813 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3815 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3820 budget = ctx->ifc_sysctl_rx_budget;
3822 budget = 16; /* XXX */
3823 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3824 if (ctx->ifc_flags & IFC_LEGACY)
3825 IFDI_INTR_ENABLE(ctx);
3830 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3831 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3832 DBG_COUNTER_INC(rx_intr_enables);
3835 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3838 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3842 _task_fn_admin(void *context)
3844 if_ctx_t ctx = context;
3845 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3848 bool oactive, running, do_reset, do_watchdog;
3849 uint32_t reset_on = hz / 2;
3852 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3853 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3854 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3855 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3856 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3859 if ((!running & !oactive) &&
3860 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3864 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3866 callout_stop(&txq->ift_timer);
3867 CALLOUT_UNLOCK(txq);
3870 ctx->ifc_watchdog_events++;
3871 IFDI_WATCHDOG_RESET(ctx);
3873 IFDI_UPDATE_ADMIN_STATUS(ctx);
3874 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3877 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3878 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3880 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3882 IFDI_LINK_INTR_ENABLE(ctx);
3884 iflib_if_init_locked(ctx);
3887 if (LINK_ACTIVE(ctx) == 0)
3889 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3890 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3895 _task_fn_iov(void *context)
3897 if_ctx_t ctx = context;
3899 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3903 IFDI_VFLR_HANDLE(ctx);
3908 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3911 if_int_delay_info_t info;
3914 info = (if_int_delay_info_t)arg1;
3915 ctx = info->iidi_ctx;
3916 info->iidi_req = req;
3917 info->iidi_oidp = oidp;
3919 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3924 /*********************************************************************
3928 **********************************************************************/
3931 iflib_if_init_locked(if_ctx_t ctx)
3934 iflib_init_locked(ctx);
3939 iflib_if_init(void *arg)
3944 iflib_if_init_locked(ctx);
3949 iflib_if_transmit(if_t ifp, struct mbuf *m)
3951 if_ctx_t ctx = if_getsoftc(ifp);
3955 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3957 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3958 DBG_COUNTER_INC(tx_frees);
3963 MPASS(m->m_nextpkt == NULL);
3965 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3966 qidx = QIDX(ctx, m);
3968 * XXX calculate buf_ring based on flowid (divvy up bits?)
3970 txq = &ctx->ifc_txqs[qidx];
3972 #ifdef DRIVER_BACKPRESSURE
3973 if (txq->ift_closed) {
3975 next = m->m_nextpkt;
3976 m->m_nextpkt = NULL;
3989 next = next->m_nextpkt;
3990 } while (next != NULL);
3992 if (count > nitems(marr))
3993 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3994 /* XXX check nextpkt */
3996 /* XXX simplify for now */
3997 DBG_COUNTER_INC(tx_frees);
4000 for (next = m, i = 0; next != NULL; i++) {
4002 next = next->m_nextpkt;
4003 mp[i]->m_nextpkt = NULL;
4006 DBG_COUNTER_INC(tx_seen);
4007 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4010 GROUPTASK_ENQUEUE(&txq->ift_task);
4013 GROUPTASK_ENQUEUE(&txq->ift_task);
4014 /* support forthcoming later */
4015 #ifdef DRIVER_BACKPRESSURE
4016 txq->ift_closed = TRUE;
4018 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4026 iflib_if_qflush(if_t ifp)
4028 if_ctx_t ctx = if_getsoftc(ifp);
4029 iflib_txq_t txq = ctx->ifc_txqs;
4033 ctx->ifc_flags |= IFC_QFLUSH;
4035 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4036 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4037 iflib_txq_check_drain(txq, 0);
4039 ctx->ifc_flags &= ~IFC_QFLUSH;
4046 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4047 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4048 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
4051 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4053 if_ctx_t ctx = if_getsoftc(ifp);
4054 struct ifreq *ifr = (struct ifreq *)data;
4055 #if defined(INET) || defined(INET6)
4056 struct ifaddr *ifa = (struct ifaddr *)data;
4058 bool avoid_reset = FALSE;
4059 int err = 0, reinit = 0, bits;
4064 if (ifa->ifa_addr->sa_family == AF_INET)
4068 if (ifa->ifa_addr->sa_family == AF_INET6)
4072 ** Calling init results in link renegotiation,
4073 ** so we avoid doing it when possible.
4076 if_setflagbits(ifp, IFF_UP,0);
4077 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4080 if (!(if_getflags(ifp) & IFF_NOARP))
4081 arp_ifinit(ifp, ifa);
4084 err = ether_ioctl(ifp, command, data);
4088 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4092 bits = if_getdrvflags(ifp);
4093 /* stop the driver and free any clusters before proceeding */
4096 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4098 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4099 ctx->ifc_flags |= IFC_MULTISEG;
4101 ctx->ifc_flags &= ~IFC_MULTISEG;
4103 err = if_setmtu(ifp, ifr->ifr_mtu);
4105 iflib_init_locked(ctx);
4107 if_setdrvflags(ifp, bits);
4113 if (if_getflags(ifp) & IFF_UP) {
4114 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4115 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4116 (IFF_PROMISC | IFF_ALLMULTI)) {
4117 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4121 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4124 ctx->ifc_if_flags = if_getflags(ifp);
4129 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4131 IFDI_INTR_DISABLE(ctx);
4132 IFDI_MULTI_SET(ctx);
4133 IFDI_INTR_ENABLE(ctx);
4139 IFDI_MEDIA_SET(ctx);
4144 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4148 struct ifi2creq i2c;
4150 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4153 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4157 if (i2c.len > sizeof(i2c.data)) {
4162 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4163 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4171 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4174 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4176 setmask |= (mask & IFCAP_FLAGS);
4178 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4179 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4180 if ((mask & IFCAP_WOL) &&
4181 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4182 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4185 * want to ensure that traffic has stopped before we change any of the flags
4189 bits = if_getdrvflags(ifp);
4190 if (bits & IFF_DRV_RUNNING)
4193 if_togglecapenable(ifp, setmask);
4195 if (bits & IFF_DRV_RUNNING)
4196 iflib_init_locked(ctx);
4198 if_setdrvflags(ifp, bits);
4204 case SIOCGPRIVATE_0:
4208 err = IFDI_PRIV_IOCTL(ctx, command, data);
4212 err = ether_ioctl(ifp, command, data);
4221 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4223 if_ctx_t ctx = if_getsoftc(ifp);
4225 return (IFDI_GET_COUNTER(ctx, cnt));
4228 /*********************************************************************
4230 * OTHER FUNCTIONS EXPORTED TO THE STACK
4232 **********************************************************************/
4235 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4237 if_ctx_t ctx = if_getsoftc(ifp);
4239 if ((void *)ctx != arg)
4242 if ((vtag == 0) || (vtag > 4095))
4246 IFDI_VLAN_REGISTER(ctx, vtag);
4247 /* Re-init to load the changes */
4248 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4249 iflib_if_init_locked(ctx);
4254 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4256 if_ctx_t ctx = if_getsoftc(ifp);
4258 if ((void *)ctx != arg)
4261 if ((vtag == 0) || (vtag > 4095))
4265 IFDI_VLAN_UNREGISTER(ctx, vtag);
4266 /* Re-init to load the changes */
4267 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4268 iflib_if_init_locked(ctx);
4273 iflib_led_func(void *arg, int onoff)
4278 IFDI_LED_FUNC(ctx, onoff);
4282 /*********************************************************************
4284 * BUS FUNCTION DEFINITIONS
4286 **********************************************************************/
4289 iflib_device_probe(device_t dev)
4291 pci_vendor_info_t *ent;
4293 uint16_t pci_vendor_id, pci_device_id;
4294 uint16_t pci_subvendor_id, pci_subdevice_id;
4295 uint16_t pci_rev_id;
4296 if_shared_ctx_t sctx;
4298 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4301 pci_vendor_id = pci_get_vendor(dev);
4302 pci_device_id = pci_get_device(dev);
4303 pci_subvendor_id = pci_get_subvendor(dev);
4304 pci_subdevice_id = pci_get_subdevice(dev);
4305 pci_rev_id = pci_get_revid(dev);
4306 if (sctx->isc_parse_devinfo != NULL)
4307 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4309 ent = sctx->isc_vendor_info;
4310 while (ent->pvi_vendor_id != 0) {
4311 if (pci_vendor_id != ent->pvi_vendor_id) {
4315 if ((pci_device_id == ent->pvi_device_id) &&
4316 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4317 (ent->pvi_subvendor_id == 0)) &&
4318 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4319 (ent->pvi_subdevice_id == 0)) &&
4320 ((pci_rev_id == ent->pvi_rev_id) ||
4321 (ent->pvi_rev_id == 0))) {
4323 device_set_desc_copy(dev, ent->pvi_name);
4324 /* this needs to be changed to zero if the bus probing code
4325 * ever stops re-probing on best match because the sctx
4326 * may have its values over written by register calls
4327 * in subsequent probes
4329 return (BUS_PROBE_DEFAULT);
4337 iflib_reset_qvalues(if_ctx_t ctx)
4339 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4340 if_shared_ctx_t sctx = ctx->ifc_sctx;
4341 device_t dev = ctx->ifc_dev;
4344 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4345 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4347 * XXX sanity check that ntxd & nrxd are a power of 2
4349 if (ctx->ifc_sysctl_ntxqs != 0)
4350 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4351 if (ctx->ifc_sysctl_nrxqs != 0)
4352 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4354 for (i = 0; i < sctx->isc_ntxqs; i++) {
4355 if (ctx->ifc_sysctl_ntxds[i] != 0)
4356 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4358 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4361 for (i = 0; i < sctx->isc_nrxqs; i++) {
4362 if (ctx->ifc_sysctl_nrxds[i] != 0)
4363 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4365 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4368 for (i = 0; i < sctx->isc_nrxqs; i++) {
4369 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4370 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4371 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4372 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4374 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4375 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4376 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4377 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4381 for (i = 0; i < sctx->isc_ntxqs; i++) {
4382 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4383 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4384 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4385 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4387 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4388 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4389 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4390 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4396 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4401 if_softc_ctx_t scctx;
4407 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4410 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4411 device_set_softc(dev, ctx);
4412 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4415 ctx->ifc_sctx = sctx;
4417 ctx->ifc_softc = sc;
4419 if ((err = iflib_register(ctx)) != 0) {
4420 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4423 device_printf(dev, "iflib_register failed %d\n", err);
4426 iflib_add_device_sysctl_pre(ctx);
4428 scctx = &ctx->ifc_softc_ctx;
4431 iflib_reset_qvalues(ctx);
4433 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4435 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4438 _iflib_pre_assert(scctx);
4439 ctx->ifc_txrx = *scctx->isc_txrx;
4442 MPASS(scctx->isc_capabilities);
4443 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4444 MPASS(scctx->isc_tx_csum_flags);
4447 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4448 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4450 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4451 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4452 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4453 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4456 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4457 ctx->ifc_flags |= IFC_DMAR;
4458 #elif !(defined(__i386__) || defined(__amd64__))
4459 /* set unconditionally for !x86 */
4460 ctx->ifc_flags |= IFC_DMAR;
4463 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4464 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4466 /* XXX change for per-queue sizes */
4467 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4468 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4469 for (i = 0; i < sctx->isc_nrxqs; i++) {
4470 if (!powerof2(scctx->isc_nrxd[i])) {
4471 /* round down instead? */
4472 device_printf(dev, "# rx descriptors must be a power of 2\n");
4477 for (i = 0; i < sctx->isc_ntxqs; i++) {
4478 if (!powerof2(scctx->isc_ntxd[i])) {
4480 "# tx descriptors must be a power of 2");
4486 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4487 MAX_SINGLE_PACKET_FRACTION)
4488 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4489 MAX_SINGLE_PACKET_FRACTION);
4490 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4491 MAX_SINGLE_PACKET_FRACTION)
4492 scctx->isc_tx_tso_segments_max = max(1,
4493 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4495 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4496 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4498 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4501 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4504 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4505 * into account. In the worst case, each of these calls will
4506 * add another mbuf and, thus, the requirement for another DMA
4507 * segment. So for best performance, it doesn't make sense to
4508 * advertize a maximum of TSO segments that typically will
4509 * require defragmentation in iflib_encap().
4511 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4512 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4514 if (scctx->isc_rss_table_size == 0)
4515 scctx->isc_rss_table_size = 64;
4516 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4518 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4519 /* XXX format name */
4520 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4522 /* Set up cpu set. If it fails, use the set of all CPUs. */
4523 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4524 device_printf(dev, "Unable to fetch CPU list\n");
4525 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4527 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4530 ** Now setup MSI or MSI/X, should
4531 ** return us the number of supported
4532 ** vectors. (Will be 1 for MSI)
4534 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4535 msix = scctx->isc_vectors;
4536 } else if (scctx->isc_msix_bar != 0)
4538 * The simple fact that isc_msix_bar is not 0 does not mean we
4539 * we have a good value there that is known to work.
4541 msix = iflib_msix_init(ctx);
4543 scctx->isc_vectors = 1;
4544 scctx->isc_ntxqsets = 1;
4545 scctx->isc_nrxqsets = 1;
4546 scctx->isc_intr = IFLIB_INTR_LEGACY;
4549 /* Get memory for the station queues */
4550 if ((err = iflib_queues_alloc(ctx))) {
4551 device_printf(dev, "Unable to allocate queue memory\n");
4555 if ((err = iflib_qset_structures_setup(ctx)))
4559 * Group taskqueues aren't properly set up until SMP is started,
4560 * so we disable interrupts until we can handle them post
4563 * XXX: disabling interrupts doesn't actually work, at least for
4564 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4565 * we do null handling and depend on this not causing too large an
4568 IFDI_INTR_DISABLE(ctx);
4569 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4570 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4571 goto fail_intr_free;
4575 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4579 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4580 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4581 goto fail_intr_free;
4585 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4587 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4588 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4593 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4594 * This must appear after the call to ether_ifattach() because
4595 * ether_ifattach() sets if_hdrlen to the default value.
4597 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4598 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4600 if ((err = iflib_netmap_attach(ctx))) {
4601 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4606 NETDUMP_SET(ctx->ifc_ifp, iflib);
4608 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4609 iflib_add_device_sysctl_post(ctx);
4610 ctx->ifc_flags |= IFC_INIT_DONE;
4614 ether_ifdetach(ctx->ifc_ifp);
4616 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4617 pci_release_msi(ctx->ifc_dev);
4619 iflib_tx_structures_free(ctx);
4620 iflib_rx_structures_free(ctx);
4628 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4629 struct iflib_cloneattach_ctx *clctx)
4634 if_softc_ctx_t scctx;
4640 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4641 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4642 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4643 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4644 ctx->ifc_flags |= IFC_PSEUDO;
4646 ctx->ifc_sctx = sctx;
4647 ctx->ifc_softc = sc;
4650 if ((err = iflib_register(ctx)) != 0) {
4651 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4656 iflib_add_device_sysctl_pre(ctx);
4658 scctx = &ctx->ifc_softc_ctx;
4662 * XXX sanity check that ntxd & nrxd are a power of 2
4664 iflib_reset_qvalues(ctx);
4666 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4667 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4670 if (sctx->isc_flags & IFLIB_GEN_MAC)
4672 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4673 clctx->cc_params)) != 0) {
4674 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4677 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4678 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4679 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4682 MPASS(scctx->isc_capabilities);
4683 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4684 MPASS(scctx->isc_tx_csum_flags);
4687 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4688 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4690 ifp->if_flags |= IFF_NOGROUP;
4691 if (sctx->isc_flags & IFLIB_PSEUDO) {
4692 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4694 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4695 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4701 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4702 * This must appear after the call to ether_ifattach() because
4703 * ether_ifattach() sets if_hdrlen to the default value.
4705 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4706 if_setifheaderlen(ifp,
4707 sizeof(struct ether_vlan_header));
4709 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4710 iflib_add_device_sysctl_post(ctx);
4711 ctx->ifc_flags |= IFC_INIT_DONE;
4714 _iflib_pre_assert(scctx);
4715 ctx->ifc_txrx = *scctx->isc_txrx;
4717 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4718 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4719 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4720 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4722 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4723 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4725 /* XXX change for per-queue sizes */
4726 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4727 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4728 for (i = 0; i < sctx->isc_nrxqs; i++) {
4729 if (!powerof2(scctx->isc_nrxd[i])) {
4730 /* round down instead? */
4731 device_printf(dev, "# rx descriptors must be a power of 2\n");
4736 for (i = 0; i < sctx->isc_ntxqs; i++) {
4737 if (!powerof2(scctx->isc_ntxd[i])) {
4739 "# tx descriptors must be a power of 2");
4745 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4746 MAX_SINGLE_PACKET_FRACTION)
4747 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4748 MAX_SINGLE_PACKET_FRACTION);
4749 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4750 MAX_SINGLE_PACKET_FRACTION)
4751 scctx->isc_tx_tso_segments_max = max(1,
4752 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4754 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4755 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4757 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4760 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4763 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4764 * into account. In the worst case, each of these calls will
4765 * add another mbuf and, thus, the requirement for another DMA
4766 * segment. So for best performance, it doesn't make sense to
4767 * advertize a maximum of TSO segments that typically will
4768 * require defragmentation in iflib_encap().
4770 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4771 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4773 if (scctx->isc_rss_table_size == 0)
4774 scctx->isc_rss_table_size = 64;
4775 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4777 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4778 /* XXX format name */
4779 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4781 /* XXX --- can support > 1 -- but keep it simple for now */
4782 scctx->isc_intr = IFLIB_INTR_LEGACY;
4784 /* Get memory for the station queues */
4785 if ((err = iflib_queues_alloc(ctx))) {
4786 device_printf(dev, "Unable to allocate queue memory\n");
4790 if ((err = iflib_qset_structures_setup(ctx))) {
4791 device_printf(dev, "qset structure setup failed %d\n", err);
4796 * XXX What if anything do we want to do about interrupts?
4798 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4799 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4800 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4805 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4806 * This must appear after the call to ether_ifattach() because
4807 * ether_ifattach() sets if_hdrlen to the default value.
4809 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4810 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4812 /* XXX handle more than one queue */
4813 for (i = 0; i < scctx->isc_nrxqsets; i++)
4814 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4818 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4819 iflib_add_device_sysctl_post(ctx);
4820 ctx->ifc_flags |= IFC_INIT_DONE;
4823 ether_ifdetach(ctx->ifc_ifp);
4825 iflib_tx_structures_free(ctx);
4826 iflib_rx_structures_free(ctx);
4833 iflib_pseudo_deregister(if_ctx_t ctx)
4835 if_t ifp = ctx->ifc_ifp;
4839 struct taskqgroup *tqg;
4842 /* Unregister VLAN events */
4843 if (ctx->ifc_vlan_attach_event != NULL)
4844 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4845 if (ctx->ifc_vlan_detach_event != NULL)
4846 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4848 ether_ifdetach(ifp);
4849 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4850 CTX_LOCK_DESTROY(ctx);
4851 /* XXX drain any dependent tasks */
4852 tqg = qgroup_if_io_tqg;
4853 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4854 callout_drain(&txq->ift_timer);
4855 if (txq->ift_task.gt_uniq != NULL)
4856 taskqgroup_detach(tqg, &txq->ift_task);
4858 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4859 if (rxq->ifr_task.gt_uniq != NULL)
4860 taskqgroup_detach(tqg, &rxq->ifr_task);
4862 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4863 free(fl->ifl_rx_bitmap, M_IFLIB);
4865 tqg = qgroup_if_config_tqg;
4866 if (ctx->ifc_admin_task.gt_uniq != NULL)
4867 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4868 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4869 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4873 iflib_tx_structures_free(ctx);
4874 iflib_rx_structures_free(ctx);
4875 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4876 free(ctx->ifc_softc, M_IFLIB);
4882 iflib_device_attach(device_t dev)
4885 if_shared_ctx_t sctx;
4887 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4890 pci_enable_busmaster(dev);
4892 return (iflib_device_register(dev, NULL, sctx, &ctx));
4896 iflib_device_deregister(if_ctx_t ctx)
4898 if_t ifp = ctx->ifc_ifp;
4901 device_t dev = ctx->ifc_dev;
4903 struct taskqgroup *tqg;
4906 /* Make sure VLANS are not using driver */
4907 if (if_vlantrunkinuse(ifp)) {
4908 device_printf(dev,"Vlan in use, detach first\n");
4913 ctx->ifc_in_detach = 1;
4917 /* Unregister VLAN events */
4918 if (ctx->ifc_vlan_attach_event != NULL)
4919 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4920 if (ctx->ifc_vlan_detach_event != NULL)
4921 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4923 iflib_netmap_detach(ifp);
4924 ether_ifdetach(ifp);
4925 if (ctx->ifc_led_dev != NULL)
4926 led_destroy(ctx->ifc_led_dev);
4927 /* XXX drain any dependent tasks */
4928 tqg = qgroup_if_io_tqg;
4929 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4930 callout_drain(&txq->ift_timer);
4931 if (txq->ift_task.gt_uniq != NULL)
4932 taskqgroup_detach(tqg, &txq->ift_task);
4934 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4935 if (rxq->ifr_task.gt_uniq != NULL)
4936 taskqgroup_detach(tqg, &rxq->ifr_task);
4938 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4939 free(fl->ifl_rx_bitmap, M_IFLIB);
4942 tqg = qgroup_if_config_tqg;
4943 if (ctx->ifc_admin_task.gt_uniq != NULL)
4944 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4945 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4946 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4951 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4952 CTX_LOCK_DESTROY(ctx);
4953 device_set_softc(ctx->ifc_dev, NULL);
4954 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4955 pci_release_msi(dev);
4957 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4958 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4960 if (ctx->ifc_msix_mem != NULL) {
4961 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4962 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4963 ctx->ifc_msix_mem = NULL;
4966 bus_generic_detach(dev);
4969 iflib_tx_structures_free(ctx);
4970 iflib_rx_structures_free(ctx);
4971 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4972 free(ctx->ifc_softc, M_IFLIB);
4979 iflib_device_detach(device_t dev)
4981 if_ctx_t ctx = device_get_softc(dev);
4983 return (iflib_device_deregister(ctx));
4987 iflib_device_suspend(device_t dev)
4989 if_ctx_t ctx = device_get_softc(dev);
4995 return bus_generic_suspend(dev);
4998 iflib_device_shutdown(device_t dev)
5000 if_ctx_t ctx = device_get_softc(dev);
5006 return bus_generic_suspend(dev);
5011 iflib_device_resume(device_t dev)
5013 if_ctx_t ctx = device_get_softc(dev);
5014 iflib_txq_t txq = ctx->ifc_txqs;
5018 iflib_init_locked(ctx);
5020 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5021 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5023 return (bus_generic_resume(dev));
5027 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5030 if_ctx_t ctx = device_get_softc(dev);
5033 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5040 iflib_device_iov_uninit(device_t dev)
5042 if_ctx_t ctx = device_get_softc(dev);
5045 IFDI_IOV_UNINIT(ctx);
5050 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5053 if_ctx_t ctx = device_get_softc(dev);
5056 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5062 /*********************************************************************
5064 * MODULE FUNCTION DEFINITIONS
5066 **********************************************************************/
5069 * - Start a fast taskqueue thread for each core
5070 * - Start a taskqueue for control operations
5073 iflib_module_init(void)
5079 iflib_module_event_handler(module_t mod, int what, void *arg)
5085 if ((err = iflib_module_init()) != 0)
5091 return (EOPNOTSUPP);
5097 /*********************************************************************
5099 * PUBLIC FUNCTION DEFINITIONS
5100 * ordered as in iflib.h
5102 **********************************************************************/
5106 _iflib_assert(if_shared_ctx_t sctx)
5108 MPASS(sctx->isc_tx_maxsize);
5109 MPASS(sctx->isc_tx_maxsegsize);
5111 MPASS(sctx->isc_rx_maxsize);
5112 MPASS(sctx->isc_rx_nsegments);
5113 MPASS(sctx->isc_rx_maxsegsize);
5115 MPASS(sctx->isc_nrxd_min[0]);
5116 MPASS(sctx->isc_nrxd_max[0]);
5117 MPASS(sctx->isc_nrxd_default[0]);
5118 MPASS(sctx->isc_ntxd_min[0]);
5119 MPASS(sctx->isc_ntxd_max[0]);
5120 MPASS(sctx->isc_ntxd_default[0]);
5124 _iflib_pre_assert(if_softc_ctx_t scctx)
5127 MPASS(scctx->isc_txrx->ift_txd_encap);
5128 MPASS(scctx->isc_txrx->ift_txd_flush);
5129 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5130 MPASS(scctx->isc_txrx->ift_rxd_available);
5131 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5132 MPASS(scctx->isc_txrx->ift_rxd_refill);
5133 MPASS(scctx->isc_txrx->ift_rxd_flush);
5137 iflib_register(if_ctx_t ctx)
5139 if_shared_ctx_t sctx = ctx->ifc_sctx;
5140 driver_t *driver = sctx->isc_driver;
5141 device_t dev = ctx->ifc_dev;
5144 _iflib_assert(sctx);
5147 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5148 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
5150 device_printf(dev, "can not allocate ifnet structure\n");
5155 * Initialize our context's device specific methods
5157 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5158 kobj_class_compile((kobj_class_t) driver);
5161 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5162 if_setsoftc(ifp, ctx);
5163 if_setdev(ifp, dev);
5164 if_setinitfn(ifp, iflib_if_init);
5165 if_setioctlfn(ifp, iflib_if_ioctl);
5166 if_settransmitfn(ifp, iflib_if_transmit);
5167 if_setqflushfn(ifp, iflib_if_qflush);
5168 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5170 ctx->ifc_vlan_attach_event =
5171 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5172 EVENTHANDLER_PRI_FIRST);
5173 ctx->ifc_vlan_detach_event =
5174 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5175 EVENTHANDLER_PRI_FIRST);
5177 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5178 iflib_media_change, iflib_media_status);
5185 iflib_queues_alloc(if_ctx_t ctx)
5187 if_shared_ctx_t sctx = ctx->ifc_sctx;
5188 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5189 device_t dev = ctx->ifc_dev;
5190 int nrxqsets = scctx->isc_nrxqsets;
5191 int ntxqsets = scctx->isc_ntxqsets;
5194 iflib_fl_t fl = NULL;
5195 int i, j, cpu, err, txconf, rxconf;
5196 iflib_dma_info_t ifdip;
5197 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5198 uint32_t *txqsizes = scctx->isc_txqsizes;
5199 uint8_t nrxqs = sctx->isc_nrxqs;
5200 uint8_t ntxqs = sctx->isc_ntxqs;
5201 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5205 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5206 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5208 /* Allocate the TX ring struct memory */
5209 if (!(ctx->ifc_txqs =
5210 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5211 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5212 device_printf(dev, "Unable to allocate TX ring memory\n");
5217 /* Now allocate the RX */
5218 if (!(ctx->ifc_rxqs =
5219 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5220 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5221 device_printf(dev, "Unable to allocate RX ring memory\n");
5226 txq = ctx->ifc_txqs;
5227 rxq = ctx->ifc_rxqs;
5230 * XXX handle allocation failure
5232 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5233 /* Set up some basics */
5235 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5236 device_printf(dev, "failed to allocate iflib_dma_info\n");
5240 txq->ift_ifdi = ifdip;
5241 for (j = 0; j < ntxqs; j++, ifdip++) {
5242 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5243 device_printf(dev, "Unable to allocate Descriptor memory\n");
5247 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5248 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5252 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5253 txq->ift_br_offset = 1;
5255 txq->ift_br_offset = 0;
5258 txq->ift_timer.c_cpu = cpu;
5260 if (iflib_txsd_alloc(txq)) {
5261 device_printf(dev, "Critical Failure setting up TX buffers\n");
5266 /* Initialize the TX lock */
5267 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5268 device_get_nameunit(dev), txq->ift_id);
5269 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5270 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5272 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5273 device_get_nameunit(dev), txq->ift_id);
5275 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5276 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5278 /* XXX free any allocated rings */
5279 device_printf(dev, "Unable to allocate buf_ring\n");
5284 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5285 /* Set up some basics */
5287 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5288 device_printf(dev, "failed to allocate iflib_dma_info\n");
5293 rxq->ifr_ifdi = ifdip;
5294 /* XXX this needs to be changed if #rx queues != #tx queues */
5295 rxq->ifr_ntxqirq = 1;
5296 rxq->ifr_txqid[0] = i;
5297 for (j = 0; j < nrxqs; j++, ifdip++) {
5298 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5299 device_printf(dev, "Unable to allocate Descriptor memory\n");
5303 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5307 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5308 rxq->ifr_fl_offset = 1;
5310 rxq->ifr_fl_offset = 0;
5312 rxq->ifr_nfl = nfree_lists;
5314 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5315 device_printf(dev, "Unable to allocate free list memory\n");
5320 for (j = 0; j < nfree_lists; j++) {
5321 fl[j].ifl_rxq = rxq;
5323 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5324 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5326 /* Allocate receive buffers for the ring*/
5327 if (iflib_rxsd_alloc(rxq)) {
5329 "Critical Failure setting up receive buffers\n");
5334 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5335 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
5339 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5340 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5341 for (i = 0; i < ntxqsets; i++) {
5342 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5344 for (j = 0; j < ntxqs; j++, di++) {
5345 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5346 paddrs[i*ntxqs + j] = di->idi_paddr;
5349 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5350 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5351 iflib_tx_structures_free(ctx);
5352 free(vaddrs, M_IFLIB);
5353 free(paddrs, M_IFLIB);
5356 free(vaddrs, M_IFLIB);
5357 free(paddrs, M_IFLIB);
5360 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5361 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5362 for (i = 0; i < nrxqsets; i++) {
5363 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5365 for (j = 0; j < nrxqs; j++, di++) {
5366 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5367 paddrs[i*nrxqs + j] = di->idi_paddr;
5370 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5371 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5372 iflib_tx_structures_free(ctx);
5373 free(vaddrs, M_IFLIB);
5374 free(paddrs, M_IFLIB);
5377 free(vaddrs, M_IFLIB);
5378 free(paddrs, M_IFLIB);
5382 /* XXX handle allocation failure changes */
5386 if (ctx->ifc_rxqs != NULL)
5387 free(ctx->ifc_rxqs, M_IFLIB);
5388 ctx->ifc_rxqs = NULL;
5389 if (ctx->ifc_txqs != NULL)
5390 free(ctx->ifc_txqs, M_IFLIB);
5391 ctx->ifc_txqs = NULL;
5397 iflib_tx_structures_setup(if_ctx_t ctx)
5399 iflib_txq_t txq = ctx->ifc_txqs;
5402 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5403 iflib_txq_setup(txq);
5409 iflib_tx_structures_free(if_ctx_t ctx)
5411 iflib_txq_t txq = ctx->ifc_txqs;
5414 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5415 iflib_txq_destroy(txq);
5416 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
5417 iflib_dma_free(&txq->ift_ifdi[j]);
5419 free(ctx->ifc_txqs, M_IFLIB);
5420 ctx->ifc_txqs = NULL;
5421 IFDI_QUEUES_FREE(ctx);
5424 /*********************************************************************
5426 * Initialize all receive rings.
5428 **********************************************************************/
5430 iflib_rx_structures_setup(if_ctx_t ctx)
5432 iflib_rxq_t rxq = ctx->ifc_rxqs;
5434 #if defined(INET6) || defined(INET)
5438 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5439 #if defined(INET6) || defined(INET)
5440 tcp_lro_free(&rxq->ifr_lc);
5441 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5442 TCP_LRO_ENTRIES, min(1024,
5443 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5444 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5447 rxq->ifr_lro_enabled = TRUE;
5449 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5452 #if defined(INET6) || defined(INET)
5455 * Free RX software descriptors allocated so far, we will only handle
5456 * the rings that completed, the failing case will have
5457 * cleaned up for itself. 'q' failed, so its the terminus.
5459 rxq = ctx->ifc_rxqs;
5460 for (i = 0; i < q; ++i, rxq++) {
5461 iflib_rx_sds_free(rxq);
5462 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5468 /*********************************************************************
5470 * Free all receive rings.
5472 **********************************************************************/
5474 iflib_rx_structures_free(if_ctx_t ctx)
5476 iflib_rxq_t rxq = ctx->ifc_rxqs;
5478 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5479 iflib_rx_sds_free(rxq);
5484 iflib_qset_structures_setup(if_ctx_t ctx)
5489 * It is expected that the caller takes care of freeing queues if this
5492 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5493 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5497 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5498 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5504 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5505 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5508 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5513 find_nth(if_ctx_t ctx, int qid)
5516 int i, cpuid, eqid, count;
5518 CPU_COPY(&ctx->ifc_cpus, &cpus);
5519 count = CPU_COUNT(&cpus);
5521 /* clear up to the qid'th bit */
5522 for (i = 0; i < eqid; i++) {
5523 cpuid = CPU_FFS(&cpus);
5525 CPU_CLR(cpuid-1, &cpus);
5527 cpuid = CPU_FFS(&cpus);
5533 extern struct cpu_group *cpu_top; /* CPU topology */
5536 find_child_with_core(int cpu, struct cpu_group *grp)
5540 if (grp->cg_children == 0)
5543 MPASS(grp->cg_child);
5544 for (i = 0; i < grp->cg_children; i++) {
5545 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5553 * Find the nth "close" core to the specified core
5554 * "close" is defined as the deepest level that shares
5555 * at least an L2 cache. With threads, this will be
5556 * threads on the same core. If the sahred cache is L3
5557 * or higher, simply returns the same core.
5560 find_close_core(int cpu, int core_offset)
5562 struct cpu_group *grp;
5571 while ((i = find_child_with_core(cpu, grp)) != -1) {
5572 /* If the child only has one cpu, don't descend */
5573 if (grp->cg_child[i].cg_count <= 1)
5575 grp = &grp->cg_child[i];
5578 /* If they don't share at least an L2 cache, use the same CPU */
5579 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5583 CPU_COPY(&grp->cg_mask, &cs);
5585 /* Add the selected CPU offset to core offset. */
5586 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5587 if (fcpu - 1 == cpu)
5589 CPU_CLR(fcpu - 1, &cs);
5595 CPU_COPY(&grp->cg_mask, &cs);
5596 for (i = core_offset % grp->cg_count; i > 0; i--) {
5597 MPASS(CPU_FFS(&cs));
5598 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5600 MPASS(CPU_FFS(&cs));
5601 return CPU_FFS(&cs) - 1;
5605 find_close_core(int cpu, int core_offset __unused)
5612 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5616 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5617 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5618 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5620 case IFLIB_INTR_RXTX:
5621 /* RX queues get the specified core */
5622 return qid / CPU_COUNT(&ctx->ifc_cpus);
5628 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5629 #define find_close_core(cpuid, tid) CPU_FIRST()
5630 #define find_nth(ctx, gid) CPU_FIRST()
5633 /* Just to avoid copy/paste */
5635 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5636 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5641 cpuid = find_nth(ctx, qid);
5642 tid = get_core_offset(ctx, type, qid);
5644 cpuid = find_close_core(cpuid, tid);
5645 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5647 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5651 if (cpuid > ctx->ifc_cpuid_highest)
5652 ctx->ifc_cpuid_highest = cpuid;
5658 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5659 iflib_intr_type_t type, driver_filter_t *filter,
5660 void *filter_arg, int qid, const char *name)
5662 struct grouptask *gtask;
5663 struct taskqgroup *tqg;
5664 iflib_filter_info_t info;
5667 driver_filter_t *intr_fast;
5670 info = &ctx->ifc_filter_info;
5674 /* XXX merge tx/rx for netmap? */
5676 q = &ctx->ifc_txqs[qid];
5677 info = &ctx->ifc_txqs[qid].ift_filter_info;
5678 gtask = &ctx->ifc_txqs[qid].ift_task;
5679 tqg = qgroup_if_io_tqg;
5681 intr_fast = iflib_fast_intr;
5682 GROUPTASK_INIT(gtask, 0, fn, q);
5683 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5686 q = &ctx->ifc_rxqs[qid];
5687 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5688 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5689 tqg = qgroup_if_io_tqg;
5691 intr_fast = iflib_fast_intr;
5692 GROUPTASK_INIT(gtask, 0, fn, q);
5694 case IFLIB_INTR_RXTX:
5695 q = &ctx->ifc_rxqs[qid];
5696 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5697 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5698 tqg = qgroup_if_io_tqg;
5700 intr_fast = iflib_fast_intr_rxtx;
5701 GROUPTASK_INIT(gtask, 0, fn, q);
5703 case IFLIB_INTR_ADMIN:
5706 info = &ctx->ifc_filter_info;
5707 gtask = &ctx->ifc_admin_task;
5708 tqg = qgroup_if_config_tqg;
5709 fn = _task_fn_admin;
5710 intr_fast = iflib_fast_intr_ctx;
5713 panic("unknown net intr type");
5716 info->ifi_filter = filter;
5717 info->ifi_filter_arg = filter_arg;
5718 info->ifi_task = gtask;
5721 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5723 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5726 if (type == IFLIB_INTR_ADMIN)
5730 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5734 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5741 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5743 struct grouptask *gtask;
5744 struct taskqgroup *tqg;
5752 q = &ctx->ifc_txqs[qid];
5753 gtask = &ctx->ifc_txqs[qid].ift_task;
5754 tqg = qgroup_if_io_tqg;
5757 irq_num = rman_get_start(irq->ii_res);
5760 q = &ctx->ifc_rxqs[qid];
5761 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5762 tqg = qgroup_if_io_tqg;
5765 irq_num = rman_get_start(irq->ii_res);
5767 case IFLIB_INTR_IOV:
5769 gtask = &ctx->ifc_vflr_task;
5770 tqg = qgroup_if_config_tqg;
5774 panic("unknown net intr type");
5776 GROUPTASK_INIT(gtask, 0, fn, q);
5777 if (irq_num != -1) {
5778 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5780 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5783 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5788 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5791 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5794 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5798 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5800 iflib_txq_t txq = ctx->ifc_txqs;
5801 iflib_rxq_t rxq = ctx->ifc_rxqs;
5802 if_irq_t irq = &ctx->ifc_legacy_irq;
5803 iflib_filter_info_t info;
5804 struct grouptask *gtask;
5805 struct taskqgroup *tqg;
5811 q = &ctx->ifc_rxqs[0];
5812 info = &rxq[0].ifr_filter_info;
5813 gtask = &rxq[0].ifr_task;
5814 tqg = qgroup_if_io_tqg;
5815 tqrid = irq->ii_rid = *rid;
5818 ctx->ifc_flags |= IFC_LEGACY;
5819 info->ifi_filter = filter;
5820 info->ifi_filter_arg = filter_arg;
5821 info->ifi_task = gtask;
5822 info->ifi_ctx = ctx;
5824 /* We allocate a single interrupt resource */
5825 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5827 GROUPTASK_INIT(gtask, 0, fn, q);
5828 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5830 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5831 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5836 iflib_led_create(if_ctx_t ctx)
5839 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5840 device_get_nameunit(ctx->ifc_dev));
5844 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5847 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5851 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5854 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5858 iflib_admin_intr_deferred(if_ctx_t ctx)
5861 struct grouptask *gtask;
5863 gtask = &ctx->ifc_admin_task;
5864 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5867 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5871 iflib_iov_intr_deferred(if_ctx_t ctx)
5874 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5878 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5881 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5885 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5889 GROUPTASK_INIT(gtask, 0, fn, ctx);
5890 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5894 iflib_config_gtask_deinit(struct grouptask *gtask)
5897 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5901 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5903 if_t ifp = ctx->ifc_ifp;
5904 iflib_txq_t txq = ctx->ifc_txqs;
5906 if_setbaudrate(ifp, baudrate);
5907 if (baudrate >= IF_Gbps(10)) {
5909 ctx->ifc_flags |= IFC_PREFETCH;
5912 /* If link down, disable watchdog */
5913 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5914 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5915 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5917 ctx->ifc_link_state = link_state;
5918 if_link_state_change(ifp, link_state);
5922 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5926 int credits_pre = txq->ift_cidx_processed;
5929 if (ctx->isc_txd_credits_update == NULL)
5932 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5935 txq->ift_processed += credits;
5936 txq->ift_cidx_processed += credits;
5938 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5939 if (txq->ift_cidx_processed >= txq->ift_size)
5940 txq->ift_cidx_processed -= txq->ift_size;
5945 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5948 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5953 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5954 const char *description, if_int_delay_info_t info,
5955 int offset, int value)
5957 info->iidi_ctx = ctx;
5958 info->iidi_offset = offset;
5959 info->iidi_value = value;
5960 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5961 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5962 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5963 info, 0, iflib_sysctl_int_delay, "I", description);
5967 iflib_ctx_lock_get(if_ctx_t ctx)
5970 return (&ctx->ifc_ctx_sx);
5974 iflib_msix_init(if_ctx_t ctx)
5976 device_t dev = ctx->ifc_dev;
5977 if_shared_ctx_t sctx = ctx->ifc_sctx;
5978 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5979 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5980 int iflib_num_tx_queues, iflib_num_rx_queues;
5981 int err, admincnt, bar;
5983 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5984 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5986 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5988 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5989 admincnt = sctx->isc_admin_intrcnt;
5990 /* Override by tuneable */
5991 if (scctx->isc_disable_msix)
5995 * bar == -1 => "trust me I know what I'm doing"
5996 * Some drivers are for hardware that is so shoddily
5997 * documented that no one knows which bars are which
5998 * so the developer has to map all bars. This hack
5999 * allows shoddy garbage to use msix in this framework.
6002 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6003 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6004 if (ctx->ifc_msix_mem == NULL) {
6005 /* May not be enabled */
6006 device_printf(dev, "Unable to map MSIX table \n");
6010 /* First try MSI/X */
6011 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
6012 device_printf(dev, "System has MSIX disabled \n");
6013 bus_release_resource(dev, SYS_RES_MEMORY,
6014 bar, ctx->ifc_msix_mem);
6015 ctx->ifc_msix_mem = NULL;
6019 /* use only 1 qset in debug mode */
6020 queuemsgs = min(msgs - admincnt, 1);
6022 queuemsgs = msgs - admincnt;
6025 queues = imin(queuemsgs, rss_getnumbuckets());
6029 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6030 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
6031 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6033 /* If we're doing RSS, clamp at the number of RSS buckets */
6034 if (queues > rss_getnumbuckets())
6035 queues = rss_getnumbuckets();
6037 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6038 rx_queues = iflib_num_rx_queues;
6042 if (rx_queues > scctx->isc_nrxqsets)
6043 rx_queues = scctx->isc_nrxqsets;
6046 * We want this to be all logical CPUs by default
6048 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6049 tx_queues = iflib_num_tx_queues;
6051 tx_queues = mp_ncpus;
6053 if (tx_queues > scctx->isc_ntxqsets)
6054 tx_queues = scctx->isc_ntxqsets;
6056 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6058 if (tx_queues != rx_queues)
6059 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6060 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6062 tx_queues = min(rx_queues, tx_queues);
6063 rx_queues = min(rx_queues, tx_queues);
6066 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
6068 vectors = rx_queues + admincnt;
6069 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6071 "Using MSIX interrupts with %d vectors\n", vectors);
6072 scctx->isc_vectors = vectors;
6073 scctx->isc_nrxqsets = rx_queues;
6074 scctx->isc_ntxqsets = tx_queues;
6075 scctx->isc_intr = IFLIB_INTR_MSIX;
6079 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
6080 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6082 ctx->ifc_msix_mem = NULL;
6085 vectors = pci_msi_count(dev);
6086 scctx->isc_nrxqsets = 1;
6087 scctx->isc_ntxqsets = 1;
6088 scctx->isc_vectors = vectors;
6089 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6090 device_printf(dev,"Using an MSI interrupt\n");
6091 scctx->isc_intr = IFLIB_INTR_MSI;
6093 scctx->isc_vectors = 1;
6094 device_printf(dev,"Using a Legacy interrupt\n");
6095 scctx->isc_intr = IFLIB_INTR_LEGACY;
6101 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6104 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6107 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6109 const char *ring_state = "UNKNOWN";
6112 rc = sysctl_wire_old_buffer(req, 0);
6116 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6121 ring_state = ring_states[state[3]];
6123 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6124 state[0], state[1], state[2], ring_state);
6125 rc = sbuf_finish(sb);
6130 enum iflib_ndesc_handler {
6136 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6138 if_ctx_t ctx = (void *)arg1;
6139 enum iflib_ndesc_handler type = arg2;
6140 char buf[256] = {0};
6145 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6149 case IFLIB_NTXD_HANDLER:
6150 ndesc = ctx->ifc_sysctl_ntxds;
6152 nqs = ctx->ifc_sctx->isc_ntxqs;
6154 case IFLIB_NRXD_HANDLER:
6155 ndesc = ctx->ifc_sysctl_nrxds;
6157 nqs = ctx->ifc_sctx->isc_nrxqs;
6160 panic("unhandled type");
6165 for (i=0; i<8; i++) {
6170 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6173 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6174 if (rc || req->newptr == NULL)
6177 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6178 i++, p = strsep(&next, " ,")) {
6179 ndesc[i] = strtoul(p, NULL, 10);
6185 #define NAME_BUFLEN 32
6187 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6189 device_t dev = iflib_get_dev(ctx);
6190 struct sysctl_oid_list *child, *oid_list;
6191 struct sysctl_ctx_list *ctx_list;
6192 struct sysctl_oid *node;
6194 ctx_list = device_get_sysctl_ctx(dev);
6195 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6196 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6197 CTLFLAG_RD, NULL, "IFLIB fields");
6198 oid_list = SYSCTL_CHILDREN(node);
6200 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6201 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6204 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6205 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6206 "# of txqs to use, 0 => use default #");
6207 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6208 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6209 "# of rxqs to use, 0 => use default #");
6210 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6211 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6212 "permit #txq != #rxq");
6213 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6214 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6215 "disable MSIX (default 0)");
6216 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6217 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6218 "set the rx budget");
6219 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6220 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6221 "cause tx to abdicate instead of running to completion");
6223 /* XXX change for per-queue sizes */
6224 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6225 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6226 mp_ndesc_handler, "A",
6227 "list of # of tx descriptors to use, 0 = use default #");
6228 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6229 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6230 mp_ndesc_handler, "A",
6231 "list of # of rx descriptors to use, 0 = use default #");
6235 iflib_add_device_sysctl_post(if_ctx_t ctx)
6237 if_shared_ctx_t sctx = ctx->ifc_sctx;
6238 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6239 device_t dev = iflib_get_dev(ctx);
6240 struct sysctl_oid_list *child;
6241 struct sysctl_ctx_list *ctx_list;
6246 char namebuf[NAME_BUFLEN];
6248 struct sysctl_oid *queue_node, *fl_node, *node;
6249 struct sysctl_oid_list *queue_list, *fl_list;
6250 ctx_list = device_get_sysctl_ctx(dev);
6252 node = ctx->ifc_sysctl_node;
6253 child = SYSCTL_CHILDREN(node);
6255 if (scctx->isc_ntxqsets > 100)
6257 else if (scctx->isc_ntxqsets > 10)
6261 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6262 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6263 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6264 CTLFLAG_RD, NULL, "Queue Name");
6265 queue_list = SYSCTL_CHILDREN(queue_node);
6267 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6269 &txq->ift_dequeued, "total mbufs freed");
6270 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6272 &txq->ift_enqueued, "total mbufs enqueued");
6274 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6276 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6277 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6279 &txq->ift_pullups, "# of times m_pullup was called");
6280 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6282 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6283 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6285 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6286 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6288 &txq->ift_map_failed, "# of times dma map failed");
6289 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6291 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6292 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6294 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6295 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6297 &txq->ift_pidx, 1, "Producer Index");
6298 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6300 &txq->ift_cidx, 1, "Consumer Index");
6301 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6303 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6304 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6306 &txq->ift_in_use, 1, "descriptors in use");
6307 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6309 &txq->ift_processed, "descriptors procesed for clean");
6310 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6312 &txq->ift_cleaned, "total cleaned");
6313 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6314 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6315 0, mp_ring_state_handler, "A", "soft ring state");
6316 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6317 CTLFLAG_RD, &txq->ift_br->enqueues,
6318 "# of enqueues to the mp_ring for this queue");
6319 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6320 CTLFLAG_RD, &txq->ift_br->drops,
6321 "# of drops in the mp_ring for this queue");
6322 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6323 CTLFLAG_RD, &txq->ift_br->starts,
6324 "# of normal consumer starts in the mp_ring for this queue");
6325 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6326 CTLFLAG_RD, &txq->ift_br->stalls,
6327 "# of consumer stalls in the mp_ring for this queue");
6328 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6329 CTLFLAG_RD, &txq->ift_br->restarts,
6330 "# of consumer restarts in the mp_ring for this queue");
6331 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6332 CTLFLAG_RD, &txq->ift_br->abdications,
6333 "# of consumer abdications in the mp_ring for this queue");
6336 if (scctx->isc_nrxqsets > 100)
6338 else if (scctx->isc_nrxqsets > 10)
6342 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6343 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6344 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6345 CTLFLAG_RD, NULL, "Queue Name");
6346 queue_list = SYSCTL_CHILDREN(queue_node);
6347 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6348 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6350 &rxq->ifr_cq_pidx, 1, "Producer Index");
6351 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6353 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6356 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6357 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6358 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6359 CTLFLAG_RD, NULL, "freelist Name");
6360 fl_list = SYSCTL_CHILDREN(fl_node);
6361 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6363 &fl->ifl_pidx, 1, "Producer Index");
6364 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6366 &fl->ifl_cidx, 1, "Consumer Index");
6367 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6369 &fl->ifl_credits, 1, "credits available");
6371 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6373 &fl->ifl_m_enqueued, "mbufs allocated");
6374 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6376 &fl->ifl_m_dequeued, "mbufs freed");
6377 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6379 &fl->ifl_cl_enqueued, "clusters allocated");
6380 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6382 &fl->ifl_cl_dequeued, "clusters freed");
6390 #ifndef __NO_STRICT_ALIGNMENT
6391 static struct mbuf *
6392 iflib_fixup_rx(struct mbuf *m)
6396 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6397 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6398 m->m_data += ETHER_HDR_LEN;
6401 MGETHDR(n, M_NOWAIT, MT_DATA);
6406 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6407 m->m_data += ETHER_HDR_LEN;
6408 m->m_len -= ETHER_HDR_LEN;
6409 n->m_len = ETHER_HDR_LEN;
6410 M_MOVE_PKTHDR(n, m);
6419 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6423 ctx = if_getsoftc(ifp);
6425 *nrxr = NRXQSETS(ctx);
6426 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6427 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6432 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6435 if_softc_ctx_t scctx;
6440 ctx = if_getsoftc(ifp);
6441 scctx = &ctx->ifc_softc_ctx;
6445 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6446 rxq = &ctx->ifc_rxqs[i];
6447 for (j = 0; j < rxq->ifr_nfl; j++) {
6449 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6452 iflib_no_tx_batch = 1;
6460 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6466 ctx = if_getsoftc(ifp);
6467 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6471 txq = &ctx->ifc_txqs[0];
6472 error = iflib_encap(txq, &m);
6474 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6479 iflib_netdump_poll(struct ifnet *ifp, int count)
6482 if_softc_ctx_t scctx;
6486 ctx = if_getsoftc(ifp);
6487 scctx = &ctx->ifc_softc_ctx;
6489 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6493 txq = &ctx->ifc_txqs[0];
6494 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6496 for (i = 0; i < scctx->isc_nrxqsets; i++)
6497 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6500 #endif /* NETDUMP */