2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/types.h>
38 #include <sys/eventhandler.h>
39 #include <sys/sockio.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
63 #include <netinet/in.h>
64 #include <netinet/in_pcb.h>
65 #include <netinet/tcp_lro.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/if_ether.h>
68 #include <netinet/ip.h>
69 #include <netinet/ip6.h>
70 #include <netinet/tcp.h>
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
78 #include <dev/led/led.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pci_private.h>
83 #include <net/iflib.h>
87 #if defined(__i386__) || defined(__amd64__)
88 #include <sys/memdesc.h>
89 #include <machine/bus.h>
90 #include <machine/md_var.h>
91 #include <machine/specialreg.h>
92 #include <x86/include/busdma_impl.h>
93 #include <x86/iommu/busdma_dmar.h>
96 #include <sys/bitstring.h>
98 * enable accounting of every mbuf as it comes in to and goes out of
99 * iflib's software descriptor references
101 #define MEMORY_LOGGING 0
103 * Enable mbuf vectors for compressing long mbuf chains
108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
109 * we prefetch needs to be determined by the time spent in m_free vis a vis
110 * the cost of a prefetch. This will of course vary based on the workload:
111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
112 * is quite expensive, thus suggesting very little prefetch.
113 * - small packet forwarding which is just returning a single mbuf to
114 * UMA will typically be very fast vis a vis the cost of a memory
121 * - private structures
122 * - iflib private utility functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 typedef struct iflib_txq *iflib_txq_t;
134 typedef struct iflib_rxq *iflib_rxq_t;
136 typedef struct iflib_fl *iflib_fl_t;
140 typedef struct iflib_filter_info {
141 driver_filter_t *ifi_filter;
142 void *ifi_filter_arg;
143 struct grouptask *ifi_task;
145 } *iflib_filter_info_t;
150 * Pointer to hardware driver's softc
157 if_shared_ctx_t ifc_sctx;
158 struct if_softc_ctx ifc_softc_ctx;
162 uint16_t ifc_nhwtxqs;
163 uint16_t ifc_nhwrxqs;
165 iflib_txq_t ifc_txqs;
166 iflib_rxq_t ifc_rxqs;
167 uint32_t ifc_if_flags;
169 uint32_t ifc_max_fl_buf_size;
174 int ifc_watchdog_events;
175 struct cdev *ifc_led_dev;
176 struct resource *ifc_msix_mem;
178 struct if_irq ifc_legacy_irq;
179 struct grouptask ifc_admin_task;
180 struct grouptask ifc_vflr_task;
181 struct iflib_filter_info ifc_filter_info;
182 struct ifmedia ifc_media;
184 struct sysctl_oid *ifc_sysctl_node;
185 uint16_t ifc_sysctl_ntxqs;
186 uint16_t ifc_sysctl_nrxqs;
187 uint16_t ifc_sysctl_qs_eq_override;
189 qidx_t ifc_sysctl_ntxds[8];
190 qidx_t ifc_sysctl_nrxds[8];
191 struct if_txrx ifc_txrx;
192 #define isc_txd_encap ifc_txrx.ift_txd_encap
193 #define isc_txd_flush ifc_txrx.ift_txd_flush
194 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
195 #define isc_rxd_available ifc_txrx.ift_rxd_available
196 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
198 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
201 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
202 eventhandler_tag ifc_vlan_attach_event;
203 eventhandler_tag ifc_vlan_detach_event;
204 uint8_t ifc_mac[ETHER_ADDR_LEN];
205 char ifc_mtx_name[16];
210 iflib_get_softc(if_ctx_t ctx)
213 return (ctx->ifc_softc);
217 iflib_get_dev(if_ctx_t ctx)
220 return (ctx->ifc_dev);
224 iflib_get_ifp(if_ctx_t ctx)
227 return (ctx->ifc_ifp);
231 iflib_get_media(if_ctx_t ctx)
234 return (&ctx->ifc_media);
238 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
241 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
245 iflib_get_softc_ctx(if_ctx_t ctx)
248 return (&ctx->ifc_softc_ctx);
252 iflib_get_sctx(if_ctx_t ctx)
255 return (ctx->ifc_sctx);
258 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
259 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
260 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
262 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
263 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
265 #define RX_SW_DESC_MAP_CREATED (1 << 0)
266 #define TX_SW_DESC_MAP_CREATED (1 << 1)
267 #define RX_SW_DESC_INUSE (1 << 3)
268 #define TX_SW_DESC_MAPPED (1 << 4)
270 typedef struct iflib_sw_rx_desc_array {
271 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
272 struct mbuf **ifsd_m; /* pkthdr mbufs */
273 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
275 } iflib_rxsd_array_t;
277 typedef struct iflib_sw_tx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
284 /* magic number that should be high enough for any hardware */
285 #define IFLIB_MAX_TX_SEGS 128
286 #define IFLIB_MAX_RX_SEGS 32
287 #define IFLIB_RX_COPY_THRESH 128
288 #define IFLIB_MAX_RX_REFRESH 32
289 /* The minimum descriptors per second before we start coalescing */
290 #define IFLIB_MIN_DESC_SEC 16384
291 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
292 #define IFLIB_QUEUE_IDLE 0
293 #define IFLIB_QUEUE_HUNG 1
294 #define IFLIB_QUEUE_WORKING 2
295 /* maximum number of txqs that can share an rx interrupt */
296 #define IFLIB_MAX_TX_SHARED_INTR 4
298 /* this should really scale with ring size - this is a fairly arbitrary value */
299 #define TX_BATCH_SIZE 32
301 #define IFLIB_RESTART_BUDGET 8
303 #define IFC_LEGACY 0x001
304 #define IFC_QFLUSH 0x002
305 #define IFC_MULTISEG 0x004
306 #define IFC_DMAR 0x008
307 #define IFC_SC_ALLOCATED 0x010
308 #define IFC_INIT_DONE 0x020
309 #define IFC_PREFETCH 0x040
310 #define IFC_DO_RESET 0x080
311 #define IFC_CHECK_HUNG 0x100
313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
319 qidx_t ift_cidx_processed;
322 uint8_t ift_br_offset;
323 uint16_t ift_npending;
324 uint16_t ift_db_pending;
325 uint16_t ift_rs_pending;
327 uint8_t ift_txd_size[8];
328 uint64_t ift_processed;
329 uint64_t ift_cleaned;
330 uint64_t ift_cleaned_prev;
332 uint64_t ift_enqueued;
333 uint64_t ift_dequeued;
335 uint64_t ift_no_tx_dma_setup;
336 uint64_t ift_no_desc_avail;
337 uint64_t ift_mbuf_defrag_failed;
338 uint64_t ift_mbuf_defrag;
339 uint64_t ift_map_failed;
340 uint64_t ift_txd_encap_efbig;
341 uint64_t ift_pullups;
344 struct mtx ift_db_mtx;
346 /* constant values */
348 struct ifmp_ring *ift_br;
349 struct grouptask ift_task;
352 struct callout ift_timer;
354 if_txsd_vec_t ift_sds;
357 uint8_t ift_update_freq;
358 struct iflib_filter_info ift_filter_info;
359 bus_dma_tag_t ift_desc_tag;
360 bus_dma_tag_t ift_tso_desc_tag;
361 iflib_dma_info_t ift_ifdi;
362 #define MTX_NAME_LEN 16
363 char ift_mtx_name[MTX_NAME_LEN];
364 char ift_db_mtx_name[MTX_NAME_LEN];
365 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
366 #ifdef IFLIB_DIAGNOSTICS
367 uint64_t ift_cpu_exec_count[256];
369 } __aligned(CACHE_LINE_SIZE);
376 uint8_t ifl_rxd_size;
378 uint64_t ifl_m_enqueued;
379 uint64_t ifl_m_dequeued;
380 uint64_t ifl_cl_enqueued;
381 uint64_t ifl_cl_dequeued;
385 bitstr_t *ifl_rx_bitmap;
389 uint16_t ifl_buf_size;
392 iflib_rxsd_array_t ifl_sds;
395 bus_dma_tag_t ifl_desc_tag;
396 iflib_dma_info_t ifl_ifdi;
397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
398 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
399 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
400 } __aligned(CACHE_LINE_SIZE);
403 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
409 else if (pidx < cidx)
410 used = size - cidx + pidx;
411 else if (gen == 0 && pidx == cidx)
413 else if (gen == 1 && pidx == cidx)
421 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
423 #define IDXDIFF(head, tail, wrap) \
424 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
427 /* If there is a separate completion queue -
428 * these are the cq cidx and pidx. Otherwise
435 uint8_t ifr_fl_offset;
441 uint8_t ifr_lro_enabled;
444 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
445 struct lro_ctrl ifr_lc;
446 struct grouptask ifr_task;
447 struct iflib_filter_info ifr_filter_info;
448 iflib_dma_info_t ifr_ifdi;
450 /* dynamically allocate if any drivers need a value substantially larger than this */
451 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
452 #ifdef IFLIB_DIAGNOSTICS
453 uint64_t ifr_cpu_exec_count[256];
455 } __aligned(CACHE_LINE_SIZE);
457 typedef struct if_rxsd {
459 struct mbuf **ifsd_m;
464 /* multiple of word size */
466 #define PKT_INFO_SIZE 6
467 #define RXD_INFO_SIZE 5
468 #define PKT_TYPE uint64_t
470 #define PKT_INFO_SIZE 11
471 #define RXD_INFO_SIZE 8
472 #define PKT_TYPE uint32_t
474 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
475 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
477 typedef struct if_pkt_info_pad {
478 PKT_TYPE pkt_val[PKT_INFO_SIZE];
479 } *if_pkt_info_pad_t;
480 typedef struct if_rxd_info_pad {
481 PKT_TYPE rxd_val[RXD_INFO_SIZE];
482 } *if_rxd_info_pad_t;
484 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
485 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
489 pkt_info_zero(if_pkt_info_t pi)
491 if_pkt_info_pad_t pi_pad;
493 pi_pad = (if_pkt_info_pad_t)pi;
494 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
495 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
497 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
498 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
503 rxd_info_zero(if_rxd_info_t ri)
505 if_rxd_info_pad_t ri_pad;
508 ri_pad = (if_rxd_info_pad_t)ri;
509 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
510 ri_pad->rxd_val[i] = 0;
511 ri_pad->rxd_val[i+1] = 0;
512 ri_pad->rxd_val[i+2] = 0;
513 ri_pad->rxd_val[i+3] = 0;
516 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
521 * Only allow a single packet to take up most 1/nth of the tx ring
523 #define MAX_SINGLE_PACKET_FRACTION 12
524 #define IF_BAD_DMA (bus_addr_t)-1
526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
528 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
530 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
531 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
532 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
539 /* Our boot-time initialization hook */
540 static int iflib_module_event_handler(module_t, int, void *);
542 static moduledata_t iflib_moduledata = {
544 iflib_module_event_handler,
548 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
549 MODULE_VERSION(iflib, 1);
551 MODULE_DEPEND(iflib, pci, 1, 1, 1);
552 MODULE_DEPEND(iflib, ether, 1, 1, 1);
554 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
555 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
557 #ifndef IFLIB_DEBUG_COUNTERS
559 #define IFLIB_DEBUG_COUNTERS 1
561 #define IFLIB_DEBUG_COUNTERS 0
562 #endif /* !INVARIANTS */
565 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
566 "iflib driver parameters");
569 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
571 static int iflib_min_tx_latency = 0;
572 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
573 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
574 static int iflib_no_tx_batch = 0;
575 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
576 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
579 #if IFLIB_DEBUG_COUNTERS
581 static int iflib_tx_seen;
582 static int iflib_tx_sent;
583 static int iflib_tx_encap;
584 static int iflib_rx_allocs;
585 static int iflib_fl_refills;
586 static int iflib_fl_refills_large;
587 static int iflib_tx_frees;
589 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
590 &iflib_tx_seen, 0, "# tx mbufs seen");
591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
592 &iflib_tx_sent, 0, "# tx mbufs sent");
593 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
594 &iflib_tx_encap, 0, "# tx mbufs encapped");
595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
596 &iflib_tx_frees, 0, "# tx frees");
597 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
598 &iflib_rx_allocs, 0, "# rx allocations");
599 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
600 &iflib_fl_refills, 0, "# refills");
601 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
602 &iflib_fl_refills_large, 0, "# large refills");
605 static int iflib_txq_drain_flushing;
606 static int iflib_txq_drain_oactive;
607 static int iflib_txq_drain_notready;
608 static int iflib_txq_drain_encapfail;
610 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
611 &iflib_txq_drain_flushing, 0, "# drain flushes");
612 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
613 &iflib_txq_drain_oactive, 0, "# drain oactives");
614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
615 &iflib_txq_drain_notready, 0, "# drain notready");
616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
617 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
620 static int iflib_encap_load_mbuf_fail;
621 static int iflib_encap_txq_avail_fail;
622 static int iflib_encap_txd_encap_fail;
624 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
625 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
627 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
629 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
631 static int iflib_task_fn_rxs;
632 static int iflib_rx_intr_enables;
633 static int iflib_fast_intrs;
634 static int iflib_intr_link;
635 static int iflib_intr_msix;
636 static int iflib_rx_unavail;
637 static int iflib_rx_ctx_inactive;
638 static int iflib_rx_zero_len;
639 static int iflib_rx_if_input;
640 static int iflib_rx_mbuf_null;
641 static int iflib_rxd_flush;
643 static int iflib_verbose_debug;
645 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
646 &iflib_intr_link, 0, "# intr link calls");
647 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
648 &iflib_intr_msix, 0, "# intr msix calls");
649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
650 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
652 &iflib_rx_intr_enables, 0, "# rx intr enables");
653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
654 &iflib_fast_intrs, 0, "# fast_intr calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
656 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
660 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
662 &iflib_rx_if_input, 0, "# times rxeof called if_input");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
664 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
666 &iflib_rxd_flush, 0, "# times rxd_flush called");
667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
668 &iflib_verbose_debug, 0, "enable verbose debugging");
670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
672 iflib_debug_reset(void)
674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
676 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
677 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
678 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail =
679 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables =
680 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
681 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
682 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
686 #define DBG_COUNTER_INC(name)
687 static void iflib_debug_reset(void) {}
692 #define IFLIB_DEBUG 0
694 static void iflib_tx_structures_free(if_ctx_t ctx);
695 static void iflib_rx_structures_free(if_ctx_t ctx);
696 static int iflib_queues_alloc(if_ctx_t ctx);
697 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
698 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
699 static int iflib_qset_structures_setup(if_ctx_t ctx);
700 static int iflib_msix_init(if_ctx_t ctx);
701 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
702 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
703 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
704 static int iflib_register(if_ctx_t);
705 static void iflib_init_locked(if_ctx_t ctx);
706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
707 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
708 static void iflib_ifmp_purge(iflib_txq_t txq);
709 static void _iflib_pre_assert(if_softc_ctx_t scctx);
710 static void iflib_stop(if_ctx_t ctx);
711 static void iflib_if_init_locked(if_ctx_t ctx);
712 #ifndef __NO_STRICT_ALIGNMENT
713 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
717 #include <sys/selinfo.h>
718 #include <net/netmap.h>
719 #include <dev/netmap/netmap_kern.h>
721 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
724 * device-specific sysctl variables:
726 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
727 * During regular operations the CRC is stripped, but on some
728 * hardware reception of frames not multiple of 64 is slower,
729 * so using crcstrip=0 helps in benchmarks.
731 * iflib_rx_miss, iflib_rx_miss_bufs:
732 * count packets that might be missed due to lost interrupts.
734 SYSCTL_DECL(_dev_netmap);
736 * The xl driver by default strips CRCs and we do not override it.
739 int iflib_crcstrip = 1;
740 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
741 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
743 int iflib_rx_miss, iflib_rx_miss_bufs;
744 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
745 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
746 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
747 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
750 * Register/unregister. We are already under netmap lock.
751 * Only called on the first register or the last unregister.
754 iflib_netmap_register(struct netmap_adapter *na, int onoff)
756 struct ifnet *ifp = na->ifp;
757 if_ctx_t ctx = ifp->if_softc;
761 IFDI_INTR_DISABLE(ctx);
763 /* Tell the stack that the interface is no longer active */
764 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
767 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
769 /* enable or disable flags and callbacks in na and ifp */
771 nm_set_native_flags(na);
773 nm_clear_native_flags(na);
776 iflib_init_locked(ctx);
777 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
778 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
780 nm_clear_native_flags(na);
786 * Reconcile kernel and user view of the transmit ring.
788 * All information is in the kring.
789 * Userspace wants to send packets up to the one before kring->rhead,
790 * kernel knows kring->nr_hwcur is the first unsent packet.
792 * Here we push packets out (as many as possible), and possibly
793 * reclaim buffers from previously completed transmission.
795 * The caller (netmap) guarantees that there is only one instance
796 * running at any time. Any interference with other driver
797 * methods should be handled by the individual drivers.
800 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
802 struct netmap_adapter *na = kring->na;
803 struct ifnet *ifp = na->ifp;
804 struct netmap_ring *ring = kring->ring;
805 u_int nm_i; /* index into the netmap ring */
806 u_int nic_i; /* index into the NIC ring */
808 u_int const lim = kring->nkr_num_slots - 1;
809 u_int const head = kring->rhead;
810 struct if_pkt_info pi;
813 * interrupts on every tx packet are expensive so request
814 * them every half ring, or where NS_REPORT is set
816 u_int report_frequency = kring->nkr_num_slots >> 1;
817 /* device-specific */
818 if_ctx_t ctx = ifp->if_softc;
819 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
821 if (txq->ift_sds.ifsd_map)
822 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
823 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
827 * First part: process new packets to send.
828 * nm_i is the current index in the netmap ring,
829 * nic_i is the corresponding index in the NIC ring.
831 * If we have packets to send (nm_i != head)
832 * iterate over the netmap ring, fetch length and update
833 * the corresponding slot in the NIC ring. Some drivers also
834 * need to update the buffer's physical address in the NIC slot
835 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
837 * The netmap_reload_map() calls is especially expensive,
838 * even when (as in this case) the tag is 0, so do only
839 * when the buffer has actually changed.
841 * If possible do not set the report/intr bit on all slots,
842 * but only a few times per ring or when NS_REPORT is set.
844 * Finally, on 10G and faster drivers, it might be useful
845 * to prefetch the next slot and txr entry.
848 nm_i = kring->nr_hwcur;
850 pi.ipi_segs = txq->ift_segs;
851 pi.ipi_qsidx = kring->ring_id;
852 if (nm_i != head) { /* we have new packets to send */
853 nic_i = netmap_idx_k2n(kring, nm_i);
855 __builtin_prefetch(&ring->slot[nm_i]);
856 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
857 if (txq->ift_sds.ifsd_map)
858 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
860 for (n = 0; nm_i != head; n++) {
861 struct netmap_slot *slot = &ring->slot[nm_i];
862 u_int len = slot->len;
864 void *addr = PNMB(na, slot, &paddr);
865 int flags = (slot->flags & NS_REPORT ||
866 nic_i == 0 || nic_i == report_frequency) ?
869 /* device-specific */
871 pi.ipi_segs[0].ds_addr = paddr;
872 pi.ipi_segs[0].ds_len = len;
876 pi.ipi_flags = flags;
878 /* Fill the slot in the NIC ring. */
879 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
881 /* prefetch for next round */
882 __builtin_prefetch(&ring->slot[nm_i + 1]);
883 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
884 if (txq->ift_sds.ifsd_map) {
885 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
887 NM_CHECK_ADDR_LEN(na, addr, len);
889 if (slot->flags & NS_BUF_CHANGED) {
890 /* buffer has changed, reload map */
891 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
893 /* make sure changes to the buffer are synced */
894 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
895 BUS_DMASYNC_PREWRITE);
897 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
898 nm_i = nm_next(nm_i, lim);
899 nic_i = nm_next(nic_i, lim);
901 kring->nr_hwcur = head;
903 /* synchronize the NIC ring */
904 if (txq->ift_sds.ifsd_map)
905 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
908 /* (re)start the tx unit up to slot nic_i (excluded) */
909 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
913 * Second part: reclaim buffers for completed transmissions.
915 if (iflib_tx_credits_update(ctx, txq)) {
916 /* some tx completed, increment avail */
917 nic_i = txq->ift_cidx_processed;
918 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
924 * Reconcile kernel and user view of the receive ring.
925 * Same as for the txsync, this routine must be efficient.
926 * The caller guarantees a single invocations, but races against
927 * the rest of the driver should be handled here.
929 * On call, kring->rhead is the first packet that userspace wants
930 * to keep, and kring->rcur is the wakeup point.
931 * The kernel has previously reported packets up to kring->rtail.
933 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
934 * of whether or not we received an interrupt.
937 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
939 struct netmap_adapter *na = kring->na;
940 struct netmap_ring *ring = kring->ring;
941 uint32_t nm_i; /* index into the netmap ring */
942 uint32_t nic_i, nic_i_start; /* index into the NIC ring */
944 u_int const lim = kring->nkr_num_slots - 1;
945 u_int const head = kring->rhead;
946 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
947 struct if_rxd_info ri;
948 struct if_rxd_update iru;
950 struct ifnet *ifp = na->ifp;
951 if_ctx_t ctx = ifp->if_softc;
952 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
953 iflib_fl_t fl = rxq->ifr_fl;
955 return netmap_ring_reinit(kring);
957 /* XXX check sync modes */
958 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
959 if (fl->ifl_sds.ifsd_map == NULL)
961 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
962 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
965 * First part: import newly received packets.
967 * nm_i is the index of the next free slot in the netmap ring,
968 * nic_i is the index of the next received packet in the NIC ring,
969 * and they may differ in case if_init() has been called while
970 * in netmap mode. For the receive ring we have
972 * nic_i = rxr->next_check;
973 * nm_i = kring->nr_hwtail (previous)
975 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
977 * rxr->next_check is set to 0 on a ring reinit
979 if (netmap_no_pendintr || force_update) {
980 int crclen = iflib_crcstrip ? 0 : 4;
982 uint16_t slot_flags = kring->nkr_slot_flags;
984 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) {
985 nic_i = fl->ifl_cidx;
986 nm_i = netmap_idx_n2k(kring, nic_i);
987 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
988 for (n = 0; avail > 0; n++, avail--) {
990 ri.iri_frags = rxq->ifr_frags;
991 ri.iri_qsidx = kring->ring_id;
992 ri.iri_ifp = ctx->ifc_ifp;
995 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
996 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
997 ring->slot[nm_i].flags = slot_flags;
998 if (fl->ifl_sds.ifsd_map)
999 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1000 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1001 nm_i = nm_next(nm_i, lim);
1002 nic_i = nm_next(nic_i, lim);
1004 if (n) { /* update the state variables */
1005 if (netmap_no_pendintr && !force_update) {
1008 iflib_rx_miss_bufs += n;
1010 fl->ifl_cidx = nic_i;
1011 kring->nr_hwtail = nm_i;
1013 kring->nr_kflags &= ~NKR_PENDINTR;
1017 * Second part: skip past packets that userspace has released.
1018 * (kring->nr_hwcur to head excluded),
1019 * and make the buffers available for reception.
1020 * As usual nm_i is the index in the netmap ring,
1021 * nic_i is the index in the NIC ring, and
1022 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1024 /* XXX not sure how this will work with multiple free lists */
1025 nm_i = kring->nr_hwcur;
1029 iru.iru_paddrs = fl->ifl_bus_addrs;
1030 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1031 iru.iru_idxs = fl->ifl_rxd_idxs;
1032 iru.iru_qsidx = rxq->ifr_id;
1033 iru.iru_buf_size = fl->ifl_buf_size;
1034 iru.iru_flidx = fl->ifl_id;
1035 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i);
1036 for (i = 0; nm_i != head; i++) {
1037 struct netmap_slot *slot = &ring->slot[nm_i];
1038 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
1040 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
1043 fl->ifl_vm_addrs[i] = addr;
1044 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) {
1045 /* buffer has changed, reload map */
1046 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr);
1048 slot->flags &= ~NS_BUF_CHANGED;
1050 nm_i = nm_next(nm_i, lim);
1051 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim);
1052 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH)
1055 iru.iru_pidx = nic_i_start;
1058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1059 if (fl->ifl_sds.ifsd_map == NULL) {
1060 nic_i_start = nic_i;
1063 nic_i = nic_i_start;
1064 for (n = 0; n < iru.iru_count; n++) {
1065 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i],
1066 BUS_DMASYNC_PREREAD);
1067 nic_i = nm_next(nic_i, lim);
1069 nic_i_start = nic_i;
1071 kring->nr_hwcur = head;
1073 if (fl->ifl_sds.ifsd_map)
1074 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1075 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1077 * IMPORTANT: we must leave one free slot in the ring,
1078 * so move nic_i back by one unit
1080 nic_i = nm_prev(nic_i, lim);
1081 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
1085 return netmap_ring_reinit(kring);
1089 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1091 struct ifnet *ifp = na->ifp;
1092 if_ctx_t ctx = ifp->if_softc;
1096 IFDI_INTR_ENABLE(ctx);
1098 IFDI_INTR_DISABLE(ctx);
1105 iflib_netmap_attach(if_ctx_t ctx)
1107 struct netmap_adapter na;
1108 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1110 bzero(&na, sizeof(na));
1112 na.ifp = ctx->ifc_ifp;
1113 na.na_flags = NAF_BDG_MAYSLEEP;
1114 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1115 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1117 na.num_tx_desc = scctx->isc_ntxd[0];
1118 na.num_rx_desc = scctx->isc_nrxd[0];
1119 na.nm_txsync = iflib_netmap_txsync;
1120 na.nm_rxsync = iflib_netmap_rxsync;
1121 na.nm_register = iflib_netmap_register;
1122 na.nm_intr = iflib_netmap_intr;
1123 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1124 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1125 return (netmap_attach(&na));
1129 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1131 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1132 struct netmap_slot *slot;
1134 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1137 if (txq->ift_sds.ifsd_map == NULL)
1140 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1143 * In netmap mode, set the map for the packet buffer.
1144 * NOTE: Some drivers (not this one) also need to set
1145 * the physical buffer address in the NIC ring.
1146 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1147 * netmap slot index, si
1149 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1150 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1154 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1156 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1157 struct netmap_slot *slot;
1158 struct if_rxd_update iru;
1162 uint32_t i, j, pidx_start;
1164 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1167 fl = &rxq->ifr_fl[0];
1168 map = fl->ifl_sds.ifsd_map;
1169 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0];
1170 iru.iru_paddrs = fl->ifl_bus_addrs;
1171 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1172 iru.iru_idxs = fl->ifl_rxd_idxs;
1173 iru.iru_qsidx = rxq->ifr_id;
1174 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size;
1177 for (pidx_start = i = j = 0; i < nrxd; i++, j++) {
1178 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i);
1181 fl->ifl_rxd_idxs[j] = i;
1182 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]);
1184 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr);
1188 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1)
1191 iru.iru_pidx = pidx_start;
1195 MPASS(pidx_start + j <= nrxd);
1196 /* Update descriptors and the cached value */
1197 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1199 /* preserve queue */
1200 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) {
1201 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1202 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1203 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t);
1205 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1);
1208 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1211 #define iflib_netmap_txq_init(ctx, txq)
1212 #define iflib_netmap_rxq_init(ctx, rxq)
1213 #define iflib_netmap_detach(ifp)
1215 #define iflib_netmap_attach(ctx) (0)
1216 #define netmap_rx_irq(ifp, qid, budget) (0)
1217 #define netmap_tx_irq(ifp, qid) do {} while (0)
1221 #if defined(__i386__) || defined(__amd64__)
1222 static __inline void
1225 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1232 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1236 *(bus_addr_t *) arg = segs[0].ds_addr;
1240 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1243 if_shared_ctx_t sctx = ctx->ifc_sctx;
1244 device_t dev = ctx->ifc_dev;
1246 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1248 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1249 sctx->isc_q_align, 0, /* alignment, bounds */
1250 BUS_SPACE_MAXADDR, /* lowaddr */
1251 BUS_SPACE_MAXADDR, /* highaddr */
1252 NULL, NULL, /* filter, filterarg */
1255 size, /* maxsegsize */
1256 BUS_DMA_ALLOCNOW, /* flags */
1257 NULL, /* lockfunc */
1262 "%s: bus_dma_tag_create failed: %d\n",
1267 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1268 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1271 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1272 __func__, (uintmax_t)size, err);
1276 dma->idi_paddr = IF_BAD_DMA;
1277 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1278 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1279 if (err || dma->idi_paddr == IF_BAD_DMA) {
1281 "%s: bus_dmamap_load failed: %d\n",
1286 dma->idi_size = size;
1290 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1292 bus_dma_tag_destroy(dma->idi_tag);
1294 dma->idi_tag = NULL;
1300 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1303 iflib_dma_info_t *dmaiter;
1306 for (i = 0; i < count; i++, dmaiter++) {
1307 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1311 iflib_dma_free_multi(dmalist, i);
1316 iflib_dma_free(iflib_dma_info_t dma)
1318 if (dma->idi_tag == NULL)
1320 if (dma->idi_paddr != IF_BAD_DMA) {
1321 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1322 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1323 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1324 dma->idi_paddr = IF_BAD_DMA;
1326 if (dma->idi_vaddr != NULL) {
1327 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1328 dma->idi_vaddr = NULL;
1330 bus_dma_tag_destroy(dma->idi_tag);
1331 dma->idi_tag = NULL;
1335 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1338 iflib_dma_info_t *dmaiter = dmalist;
1340 for (i = 0; i < count; i++, dmaiter++)
1341 iflib_dma_free(*dmaiter);
1344 #ifdef EARLY_AP_STARTUP
1345 static const int iflib_started = 1;
1348 * We used to abuse the smp_started flag to decide if the queues have been
1349 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1350 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1351 * is set. Run a SYSINIT() strictly after that to just set a usable
1355 static int iflib_started;
1358 iflib_record_started(void *arg)
1363 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1364 iflib_record_started, NULL);
1368 iflib_fast_intr(void *arg)
1370 iflib_filter_info_t info = arg;
1371 struct grouptask *gtask = info->ifi_task;
1373 return (FILTER_HANDLED);
1375 DBG_COUNTER_INC(fast_intrs);
1376 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1377 return (FILTER_HANDLED);
1379 GROUPTASK_ENQUEUE(gtask);
1380 return (FILTER_HANDLED);
1384 iflib_fast_intr_rxtx(void *arg)
1386 iflib_filter_info_t info = arg;
1387 struct grouptask *gtask = info->ifi_task;
1388 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1393 return (FILTER_HANDLED);
1395 DBG_COUNTER_INC(fast_intrs);
1396 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1397 return (FILTER_HANDLED);
1399 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1400 qidx_t txqid = rxq->ifr_txqid[i];
1404 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1405 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1408 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1410 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1411 cidx = rxq->ifr_cq_cidx;
1413 cidx = rxq->ifr_fl[0].ifl_cidx;
1414 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1415 GROUPTASK_ENQUEUE(gtask);
1417 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1418 return (FILTER_HANDLED);
1423 iflib_fast_intr_ctx(void *arg)
1425 iflib_filter_info_t info = arg;
1426 struct grouptask *gtask = info->ifi_task;
1429 return (FILTER_HANDLED);
1431 DBG_COUNTER_INC(fast_intrs);
1432 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1433 return (FILTER_HANDLED);
1435 GROUPTASK_ENQUEUE(gtask);
1436 return (FILTER_HANDLED);
1440 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1441 driver_filter_t filter, driver_intr_t handler, void *arg,
1445 struct resource *res;
1447 device_t dev = ctx->ifc_dev;
1450 if (ctx->ifc_flags & IFC_LEGACY)
1451 flags |= RF_SHAREABLE;
1454 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1457 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1461 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1462 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1463 filter, handler, arg, &tag);
1466 "failed to setup interrupt for rid %d, name %s: %d\n",
1467 rid, name ? name : "unknown", rc);
1470 bus_describe_intr(dev, res, tag, "%s", name);
1477 /*********************************************************************
1479 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1480 * the information needed to transmit a packet on the wire. This is
1481 * called only once at attach, setup is done every reset.
1483 **********************************************************************/
1486 iflib_txsd_alloc(iflib_txq_t txq)
1488 if_ctx_t ctx = txq->ift_ctx;
1489 if_shared_ctx_t sctx = ctx->ifc_sctx;
1490 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1491 device_t dev = ctx->ifc_dev;
1492 int err, nsegments, ntsosegments;
1494 nsegments = scctx->isc_tx_nsegments;
1495 ntsosegments = scctx->isc_tx_tso_segments_max;
1496 MPASS(scctx->isc_ntxd[0] > 0);
1497 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1498 MPASS(nsegments > 0);
1499 MPASS(ntsosegments > 0);
1501 * Setup DMA descriptor areas.
1503 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1504 1, 0, /* alignment, bounds */
1505 BUS_SPACE_MAXADDR, /* lowaddr */
1506 BUS_SPACE_MAXADDR, /* highaddr */
1507 NULL, NULL, /* filter, filterarg */
1508 sctx->isc_tx_maxsize, /* maxsize */
1509 nsegments, /* nsegments */
1510 sctx->isc_tx_maxsegsize, /* maxsegsize */
1512 NULL, /* lockfunc */
1513 NULL, /* lockfuncarg */
1514 &txq->ift_desc_tag))) {
1515 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1516 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n",
1517 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize);
1520 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1521 1, 0, /* alignment, bounds */
1522 BUS_SPACE_MAXADDR, /* lowaddr */
1523 BUS_SPACE_MAXADDR, /* highaddr */
1524 NULL, NULL, /* filter, filterarg */
1525 scctx->isc_tx_tso_size_max, /* maxsize */
1526 ntsosegments, /* nsegments */
1527 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1529 NULL, /* lockfunc */
1530 NULL, /* lockfuncarg */
1531 &txq->ift_tso_desc_tag))) {
1532 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1536 if (!(txq->ift_sds.ifsd_flags =
1537 (uint8_t *) malloc(sizeof(uint8_t) *
1538 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1539 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1543 if (!(txq->ift_sds.ifsd_m =
1544 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1545 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1546 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1551 /* Create the descriptor buffer dma maps */
1552 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1553 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1556 if (!(txq->ift_sds.ifsd_map =
1557 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1558 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1563 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1564 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1566 device_printf(dev, "Unable to create TX DMA map\n");
1573 /* We free all, it handles case where we are in the middle */
1574 iflib_tx_structures_free(ctx);
1579 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1584 if (txq->ift_sds.ifsd_map != NULL)
1585 map = txq->ift_sds.ifsd_map[i];
1587 bus_dmamap_unload(txq->ift_desc_tag, map);
1588 bus_dmamap_destroy(txq->ift_desc_tag, map);
1589 txq->ift_sds.ifsd_map[i] = NULL;
1594 iflib_txq_destroy(iflib_txq_t txq)
1596 if_ctx_t ctx = txq->ift_ctx;
1598 for (int i = 0; i < txq->ift_size; i++)
1599 iflib_txsd_destroy(ctx, txq, i);
1600 if (txq->ift_sds.ifsd_map != NULL) {
1601 free(txq->ift_sds.ifsd_map, M_IFLIB);
1602 txq->ift_sds.ifsd_map = NULL;
1604 if (txq->ift_sds.ifsd_m != NULL) {
1605 free(txq->ift_sds.ifsd_m, M_IFLIB);
1606 txq->ift_sds.ifsd_m = NULL;
1608 if (txq->ift_sds.ifsd_flags != NULL) {
1609 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1610 txq->ift_sds.ifsd_flags = NULL;
1612 if (txq->ift_desc_tag != NULL) {
1613 bus_dma_tag_destroy(txq->ift_desc_tag);
1614 txq->ift_desc_tag = NULL;
1616 if (txq->ift_tso_desc_tag != NULL) {
1617 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1618 txq->ift_tso_desc_tag = NULL;
1623 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1627 mp = &txq->ift_sds.ifsd_m[i];
1631 if (txq->ift_sds.ifsd_map != NULL) {
1632 bus_dmamap_sync(txq->ift_desc_tag,
1633 txq->ift_sds.ifsd_map[i],
1634 BUS_DMASYNC_POSTWRITE);
1635 bus_dmamap_unload(txq->ift_desc_tag,
1636 txq->ift_sds.ifsd_map[i]);
1639 DBG_COUNTER_INC(tx_frees);
1644 iflib_txq_setup(iflib_txq_t txq)
1646 if_ctx_t ctx = txq->ift_ctx;
1647 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1648 iflib_dma_info_t di;
1651 /* Set number of descriptors available */
1652 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1653 /* XXX make configurable */
1654 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1657 txq->ift_cidx_processed = 0;
1658 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1659 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1661 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1662 bzero((void *)di->idi_vaddr, di->idi_size);
1664 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1665 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1666 bus_dmamap_sync(di->idi_tag, di->idi_map,
1667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1671 /*********************************************************************
1673 * Allocate memory for rx_buffer structures. Since we use one
1674 * rx_buffer per received packet, the maximum number of rx_buffer's
1675 * that we'll need is equal to the number of receive descriptors
1676 * that we've allocated.
1678 **********************************************************************/
1680 iflib_rxsd_alloc(iflib_rxq_t rxq)
1682 if_ctx_t ctx = rxq->ifr_ctx;
1683 if_shared_ctx_t sctx = ctx->ifc_sctx;
1684 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1685 device_t dev = ctx->ifc_dev;
1689 MPASS(scctx->isc_nrxd[0] > 0);
1690 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1693 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1694 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1695 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1696 1, 0, /* alignment, bounds */
1697 BUS_SPACE_MAXADDR, /* lowaddr */
1698 BUS_SPACE_MAXADDR, /* highaddr */
1699 NULL, NULL, /* filter, filterarg */
1700 sctx->isc_rx_maxsize, /* maxsize */
1701 sctx->isc_rx_nsegments, /* nsegments */
1702 sctx->isc_rx_maxsegsize, /* maxsegsize */
1704 NULL, /* lockfunc */
1708 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1712 if (!(fl->ifl_sds.ifsd_flags =
1713 (uint8_t *) malloc(sizeof(uint8_t) *
1714 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1715 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1719 if (!(fl->ifl_sds.ifsd_m =
1720 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1721 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1722 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1726 if (!(fl->ifl_sds.ifsd_cl =
1727 (caddr_t *) malloc(sizeof(caddr_t) *
1728 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1729 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1734 /* Create the descriptor buffer dma maps */
1735 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1736 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1739 if (!(fl->ifl_sds.ifsd_map =
1740 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1741 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1746 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1747 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1749 device_printf(dev, "Unable to create RX buffer DMA map\n");
1758 iflib_rx_structures_free(ctx);
1764 * Internal service routines
1767 struct rxq_refill_cb_arg {
1769 bus_dma_segment_t seg;
1774 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1776 struct rxq_refill_cb_arg *cb_arg = arg;
1778 cb_arg->error = error;
1779 cb_arg->seg = segs[0];
1780 cb_arg->nseg = nseg;
1785 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1787 #define IS_DMAR(ctx) (0)
1791 * rxq_refill - refill an rxq free-buffer list
1792 * @ctx: the iflib context
1793 * @rxq: the free-list to refill
1794 * @n: the number of new buffers to allocate
1796 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1797 * The caller must assure that @n does not exceed the queue's capacity.
1800 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1803 int idx, frag_idx = fl->ifl_fragidx;
1804 int pidx = fl->ifl_pidx;
1808 struct if_rxd_update iru;
1809 bus_dmamap_t *sd_map;
1814 sd_m = fl->ifl_sds.ifsd_m;
1815 sd_map = fl->ifl_sds.ifsd_map;
1816 sd_cl = fl->ifl_sds.ifsd_cl;
1817 sd_flags = fl->ifl_sds.ifsd_flags;
1822 MPASS(fl->ifl_credits + n <= fl->ifl_size);
1824 if (pidx < fl->ifl_cidx)
1825 MPASS(pidx + n <= fl->ifl_cidx);
1826 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size))
1827 MPASS(fl->ifl_gen == 0);
1828 if (pidx > fl->ifl_cidx)
1829 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1831 DBG_COUNTER_INC(fl_refills);
1833 DBG_COUNTER_INC(fl_refills_large);
1834 iru.iru_paddrs = fl->ifl_bus_addrs;
1835 iru.iru_vaddrs = &fl->ifl_vm_addrs[0];
1836 iru.iru_idxs = fl->ifl_rxd_idxs;
1837 iru.iru_qsidx = fl->ifl_rxq->ifr_id;
1838 iru.iru_buf_size = fl->ifl_buf_size;
1839 iru.iru_flidx = fl->ifl_id;
1842 * We allocate an uninitialized mbuf + cluster, mbuf is
1843 * initialized after rx.
1845 * If the cluster is still set then we know a minimum sized packet was received
1847 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1848 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1849 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1850 if ((cl = sd_cl[frag_idx]) == NULL) {
1851 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1854 fl->ifl_cl_enqueued++;
1857 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1861 fl->ifl_m_enqueued++;
1864 DBG_COUNTER_INC(rx_allocs);
1865 #if defined(__i386__) || defined(__amd64__)
1866 if (!IS_DMAR(ctx)) {
1867 bus_addr = pmap_kextract((vm_offset_t)cl);
1871 struct rxq_refill_cb_arg cb_arg;
1876 MPASS(sd_map != NULL);
1877 MPASS(sd_map[frag_idx] != NULL);
1878 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1879 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1880 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1881 BUS_DMASYNC_PREREAD);
1883 if (err != 0 || cb_arg.error) {
1887 if (fl->ifl_zone == zone_pack)
1888 uma_zfree(fl->ifl_zone, cl);
1893 bus_addr = cb_arg.seg.ds_addr;
1895 bit_set(fl->ifl_rx_bitmap, frag_idx);
1896 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1898 MPASS(sd_m[frag_idx] == NULL);
1899 sd_cl[frag_idx] = cl;
1901 fl->ifl_rxd_idxs[i] = frag_idx;
1902 fl->ifl_bus_addrs[i] = bus_addr;
1903 fl->ifl_vm_addrs[i] = cl;
1906 MPASS(fl->ifl_credits <= fl->ifl_size);
1907 if (++idx == fl->ifl_size) {
1911 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1912 iru.iru_pidx = pidx;
1914 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1922 DBG_COUNTER_INC(rxd_flush);
1923 if (fl->ifl_pidx == 0)
1924 pidx = fl->ifl_size - 1;
1926 pidx = fl->ifl_pidx - 1;
1929 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1931 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1932 fl->ifl_fragidx = frag_idx;
1935 static __inline void
1936 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1938 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1939 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1941 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1944 MPASS(fl->ifl_credits <= fl->ifl_size);
1945 MPASS(reclaimable == delta);
1947 if (reclaimable > 0)
1948 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1952 iflib_fl_bufs_free(iflib_fl_t fl)
1954 iflib_dma_info_t idi = fl->ifl_ifdi;
1957 for (i = 0; i < fl->ifl_size; i++) {
1958 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1959 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1960 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1962 if (*sd_flags & RX_SW_DESC_INUSE) {
1963 if (fl->ifl_sds.ifsd_map != NULL) {
1964 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1965 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1966 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1968 if (*sd_m != NULL) {
1969 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1970 uma_zfree(zone_mbuf, *sd_m);
1973 uma_zfree(fl->ifl_zone, *sd_cl);
1976 MPASS(*sd_cl == NULL);
1977 MPASS(*sd_m == NULL);
1980 fl->ifl_m_dequeued++;
1981 fl->ifl_cl_dequeued++;
1987 for (i = 0; i < fl->ifl_size; i++) {
1988 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
1989 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
1990 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
1994 * Reset free list values
1996 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
1997 bzero(idi->idi_vaddr, idi->idi_size);
2000 /*********************************************************************
2002 * Initialize a receive ring and its buffers.
2004 **********************************************************************/
2006 iflib_fl_setup(iflib_fl_t fl)
2008 iflib_rxq_t rxq = fl->ifl_rxq;
2009 if_ctx_t ctx = rxq->ifr_ctx;
2010 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2012 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size);
2014 ** Free current RX buffer structs and their mbufs
2016 iflib_fl_bufs_free(fl);
2017 /* Now replenish the mbufs */
2018 MPASS(fl->ifl_credits == 0);
2020 * XXX don't set the max_frame_size to larger
2021 * than the hardware can handle
2023 if (sctx->isc_max_frame_size <= 2048)
2024 fl->ifl_buf_size = MCLBYTES;
2025 #ifndef CONTIGMALLOC_WORKS
2027 fl->ifl_buf_size = MJUMPAGESIZE;
2029 else if (sctx->isc_max_frame_size <= 4096)
2030 fl->ifl_buf_size = MJUMPAGESIZE;
2031 else if (sctx->isc_max_frame_size <= 9216)
2032 fl->ifl_buf_size = MJUM9BYTES;
2034 fl->ifl_buf_size = MJUM16BYTES;
2036 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2037 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2038 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2039 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2042 /* avoid pre-allocating zillions of clusters to an idle card
2043 * potentially speeding up attach
2045 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2046 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2047 if (min(128, fl->ifl_size) != fl->ifl_credits)
2053 MPASS(fl->ifl_ifdi != NULL);
2054 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2055 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2059 /*********************************************************************
2061 * Free receive ring data structures
2063 **********************************************************************/
2065 iflib_rx_sds_free(iflib_rxq_t rxq)
2070 if (rxq->ifr_fl != NULL) {
2071 for (i = 0; i < rxq->ifr_nfl; i++) {
2072 fl = &rxq->ifr_fl[i];
2073 if (fl->ifl_desc_tag != NULL) {
2074 bus_dma_tag_destroy(fl->ifl_desc_tag);
2075 fl->ifl_desc_tag = NULL;
2077 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2078 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2079 /* XXX destroy maps first */
2080 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2081 fl->ifl_sds.ifsd_m = NULL;
2082 fl->ifl_sds.ifsd_cl = NULL;
2083 fl->ifl_sds.ifsd_map = NULL;
2085 free(rxq->ifr_fl, M_IFLIB);
2087 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2092 * MI independent logic
2096 iflib_timer(void *arg)
2098 iflib_txq_t txq = arg;
2099 if_ctx_t ctx = txq->ift_ctx;
2100 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2102 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2105 ** Check on the state of the TX queue(s), this
2106 ** can be done without the lock because its RO
2107 ** and the HUNG state will be static if set.
2109 IFDI_TIMER(ctx, txq->ift_id);
2110 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2111 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2112 (sctx->isc_pause_frames == 0)))
2115 if (ifmp_ring_is_stalled(txq->ift_br))
2116 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2117 txq->ift_cleaned_prev = txq->ift_cleaned;
2118 /* handle any laggards */
2119 if (txq->ift_db_pending)
2120 GROUPTASK_ENQUEUE(&txq->ift_task);
2122 sctx->isc_pause_frames = 0;
2123 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2124 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2128 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2129 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2130 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2132 IFDI_WATCHDOG_RESET(ctx);
2133 ctx->ifc_watchdog_events++;
2135 ctx->ifc_flags |= IFC_DO_RESET;
2136 iflib_admin_intr_deferred(ctx);
2141 iflib_init_locked(if_ctx_t ctx)
2143 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2144 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2145 if_t ifp = ctx->ifc_ifp;
2149 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2152 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2153 IFDI_INTR_DISABLE(ctx);
2155 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2156 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2157 /* Set hardware offload abilities */
2158 if_clearhwassist(ifp);
2159 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2160 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2161 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2162 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2163 if (if_getcapenable(ifp) & IFCAP_TSO4)
2164 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2165 if (if_getcapenable(ifp) & IFCAP_TSO6)
2166 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2168 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2170 callout_stop(&txq->ift_timer);
2171 CALLOUT_UNLOCK(txq);
2172 iflib_netmap_txq_init(ctx, txq);
2174 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2175 MPASS(rxq->ifr_id == i);
2176 iflib_netmap_rxq_init(ctx, rxq);
2179 i = if_getdrvflags(ifp);
2182 MPASS(if_getdrvflags(ifp) == i);
2183 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2184 /* XXX this should really be done on a per-queue basis */
2185 if (if_getcapenable(ifp) & IFCAP_NETMAP)
2187 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2188 if (iflib_fl_setup(fl)) {
2189 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2195 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2196 IFDI_INTR_ENABLE(ctx);
2197 txq = ctx->ifc_txqs;
2198 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2199 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2200 txq->ift_timer.c_cpu);
2204 iflib_media_change(if_t ifp)
2206 if_ctx_t ctx = if_getsoftc(ifp);
2210 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2211 iflib_init_locked(ctx);
2217 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2219 if_ctx_t ctx = if_getsoftc(ifp);
2222 IFDI_UPDATE_ADMIN_STATUS(ctx);
2223 IFDI_MEDIA_STATUS(ctx, ifmr);
2228 iflib_stop(if_ctx_t ctx)
2230 iflib_txq_t txq = ctx->ifc_txqs;
2231 iflib_rxq_t rxq = ctx->ifc_rxqs;
2232 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2233 iflib_dma_info_t di;
2237 /* Tell the stack that the interface is no longer active */
2238 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2240 IFDI_INTR_DISABLE(ctx);
2245 iflib_debug_reset();
2246 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2247 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2248 /* make sure all transmitters have completed before proceeding XXX */
2250 /* clean any enqueued buffers */
2251 iflib_ifmp_purge(txq);
2252 /* Free any existing tx buffers. */
2253 for (j = 0; j < txq->ift_size; j++) {
2254 iflib_txsd_free(ctx, txq, j);
2256 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2257 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2258 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2259 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2260 txq->ift_pullups = 0;
2261 ifmp_ring_reset_stats(txq->ift_br);
2262 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2263 bzero((void *)di->idi_vaddr, di->idi_size);
2265 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2266 /* make sure all transmitters have completed before proceeding XXX */
2268 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2269 bzero((void *)di->idi_vaddr, di->idi_size);
2270 /* also resets the free lists pidx/cidx */
2271 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2272 iflib_fl_bufs_free(fl);
2276 static inline caddr_t
2277 calc_next_rxd(iflib_fl_t fl, int cidx)
2281 caddr_t start, end, cur, next;
2283 nrxd = fl->ifl_size;
2284 size = fl->ifl_rxd_size;
2285 start = fl->ifl_ifdi->idi_vaddr;
2287 if (__predict_false(size == 0))
2289 cur = start + size*cidx;
2290 end = start + size*nrxd;
2291 next = CACHE_PTR_NEXT(cur);
2292 return (next < end ? next : start);
2296 prefetch_pkts(iflib_fl_t fl, int cidx)
2299 int nrxd = fl->ifl_size;
2303 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2304 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2305 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2306 next_rxd = calc_next_rxd(fl, cidx);
2308 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2309 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2310 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2311 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2312 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2313 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2314 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2315 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2319 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2324 iflib_dma_info_t di;
2328 flid = irf->irf_flid;
2329 cidx = irf->irf_idx;
2330 fl = &rxq->ifr_fl[flid];
2332 sd->ifsd_cidx = cidx;
2333 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2334 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2337 fl->ifl_m_dequeued++;
2339 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2340 prefetch_pkts(fl, cidx);
2341 if (fl->ifl_sds.ifsd_map != NULL) {
2342 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2343 prefetch(&fl->ifl_sds.ifsd_map[next]);
2344 map = fl->ifl_sds.ifsd_map[cidx];
2346 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2347 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2348 bus_dmamap_sync(di->idi_tag, di->idi_map,
2349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2351 /* not valid assert if bxe really does SGE from non-contiguous elements */
2352 MPASS(fl->ifl_cidx == cidx);
2354 bus_dmamap_unload(fl->ifl_desc_tag, map);
2356 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2357 if (__predict_false(fl->ifl_cidx == 0))
2360 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2361 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2362 bit_clear(fl->ifl_rx_bitmap, cidx);
2365 static struct mbuf *
2366 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2368 int i, padlen , flags;
2369 struct mbuf *m, *mh, *mt;
2375 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2377 MPASS(*sd->ifsd_cl != NULL);
2378 MPASS(*sd->ifsd_m != NULL);
2380 /* Don't include zero-length frags */
2381 if (ri->iri_frags[i].irf_len == 0) {
2382 /* XXX we can save the cluster here, but not the mbuf */
2383 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2384 m_free(*sd->ifsd_m);
2391 flags = M_PKTHDR|M_EXT;
2393 padlen = ri->iri_pad;
2398 /* assuming padding is only on the first fragment */
2402 *sd->ifsd_cl = NULL;
2404 /* Can these two be made one ? */
2405 m_init(m, M_NOWAIT, MT_DATA, flags);
2406 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2408 * These must follow m_init and m_cljset
2410 m->m_data += padlen;
2411 ri->iri_len -= padlen;
2412 m->m_len = ri->iri_frags[i].irf_len;
2413 } while (++i < ri->iri_nfrags);
2419 * Process one software descriptor
2421 static struct mbuf *
2422 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2427 /* should I merge this back in now that the two paths are basically duplicated? */
2428 if (ri->iri_nfrags == 1 &&
2429 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2430 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2433 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2434 #ifndef __NO_STRICT_ALIGNMENT
2438 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2439 m->m_len = ri->iri_frags[0].irf_len;
2441 m = assemble_segments(rxq, ri, &sd);
2443 m->m_pkthdr.len = ri->iri_len;
2444 m->m_pkthdr.rcvif = ri->iri_ifp;
2445 m->m_flags |= ri->iri_flags;
2446 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2447 m->m_pkthdr.flowid = ri->iri_flowid;
2448 M_HASHTYPE_SET(m, ri->iri_rsstype);
2449 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2450 m->m_pkthdr.csum_data = ri->iri_csum_data;
2455 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2457 if_ctx_t ctx = rxq->ifr_ctx;
2458 if_shared_ctx_t sctx = ctx->ifc_sctx;
2459 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2462 struct if_rxd_info ri;
2463 int err, budget_left, rx_bytes, rx_pkts;
2469 * XXX early demux data packets so that if_input processing only handles
2470 * acks in interrupt context
2472 struct mbuf *m, *mh, *mt;
2476 if (ifp->if_capenable & IFCAP_NETMAP) {
2478 if (netmap_rx_irq(ifp, rxq->ifr_id, &work))
2485 rx_pkts = rx_bytes = 0;
2486 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2487 cidxp = &rxq->ifr_cq_cidx;
2489 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2490 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2491 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2492 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2493 DBG_COUNTER_INC(rx_unavail);
2497 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2498 if (__predict_false(!CTX_ACTIVE(ctx))) {
2499 DBG_COUNTER_INC(rx_ctx_inactive);
2503 * Reset client set fields to their default values
2506 ri.iri_qsidx = rxq->ifr_id;
2507 ri.iri_cidx = *cidxp;
2509 ri.iri_frags = rxq->ifr_frags;
2510 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2514 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2515 *cidxp = ri.iri_cidx;
2516 /* Update our consumer index */
2517 /* XXX NB: shurd - check if this is still safe */
2518 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2519 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2520 rxq->ifr_cq_gen = 0;
2522 /* was this only a completion queue message? */
2523 if (__predict_false(ri.iri_nfrags == 0))
2526 MPASS(ri.iri_nfrags != 0);
2527 MPASS(ri.iri_len != 0);
2529 /* will advance the cidx on the corresponding free lists */
2530 m = iflib_rxd_pkt_get(rxq, &ri);
2531 if (avail == 0 && budget_left)
2532 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2534 if (__predict_false(m == NULL)) {
2535 DBG_COUNTER_INC(rx_mbuf_null);
2538 /* imm_pkt: -- cxgb */
2546 /* make sure that we can refill faster than drain */
2547 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2548 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2550 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2551 while (mh != NULL) {
2554 m->m_nextpkt = NULL;
2555 #ifndef __NO_STRICT_ALIGNMENT
2556 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2559 rx_bytes += m->m_pkthdr.len;
2561 #if defined(INET6) || defined(INET)
2562 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2565 DBG_COUNTER_INC(rx_if_input);
2566 ifp->if_input(ifp, m);
2569 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2570 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2573 * Flush any outstanding LRO work
2575 #if defined(INET6) || defined(INET)
2576 tcp_lro_flush_all(&rxq->ifr_lc);
2580 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2583 ctx->ifc_flags |= IFC_DO_RESET;
2584 iflib_admin_intr_deferred(ctx);
2589 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2590 static inline qidx_t
2591 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2593 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2594 qidx_t minthresh = txq->ift_size / 8;
2595 if (in_use > 4*minthresh)
2596 return (notify_count);
2597 if (in_use > 2*minthresh)
2598 return (notify_count >> 1);
2599 if (in_use > minthresh)
2600 return (notify_count >> 3);
2604 static inline qidx_t
2605 txq_max_rs_deferred(iflib_txq_t txq)
2607 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2608 qidx_t minthresh = txq->ift_size / 8;
2609 if (txq->ift_in_use > 4*minthresh)
2610 return (notify_count);
2611 if (txq->ift_in_use > 2*minthresh)
2612 return (notify_count >> 1);
2613 if (txq->ift_in_use > minthresh)
2614 return (notify_count >> 2);
2618 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2619 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2621 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2622 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2623 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2625 /* forward compatibility for cxgb */
2626 #define FIRST_QSET(ctx) 0
2627 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2628 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2629 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2630 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2632 /* XXX we should be setting this to something other than zero */
2633 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2634 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2637 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2643 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2644 if (ring || txq->ift_db_pending >= max) {
2645 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2646 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2647 txq->ift_db_pending = txq->ift_npending = 0;
2655 print_pkt(if_pkt_info_t pi)
2657 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2658 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2659 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2660 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2661 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2662 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2666 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2667 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2670 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2672 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2673 struct ether_vlan_header *eh;
2677 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2678 M_WRITABLE(m) == 0) {
2679 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2688 * Determine where frame payload starts.
2689 * Jump over vlan headers if already present,
2690 * helpful for QinQ too.
2692 if (__predict_false(m->m_len < sizeof(*eh))) {
2694 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2697 eh = mtod(m, struct ether_vlan_header *);
2698 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2699 pi->ipi_etype = ntohs(eh->evl_proto);
2700 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2702 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2703 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2706 switch (pi->ipi_etype) {
2710 struct ip *ip = NULL;
2711 struct tcphdr *th = NULL;
2714 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2715 if (__predict_false(m->m_len < minthlen)) {
2717 * if this code bloat is causing too much of a hit
2718 * move it to a separate function and mark it noinline
2720 if (m->m_len == pi->ipi_ehdrlen) {
2723 if (n->m_len >= sizeof(*ip)) {
2724 ip = (struct ip *)n->m_data;
2725 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2726 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2729 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2731 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2735 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2737 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2738 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2739 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2742 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2743 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2744 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2746 pi->ipi_ip_hlen = ip->ip_hl << 2;
2747 pi->ipi_ipproto = ip->ip_p;
2748 pi->ipi_flags |= IPI_TX_IPV4;
2750 if (pi->ipi_csum_flags & CSUM_IP)
2753 if (pi->ipi_ipproto == IPPROTO_TCP) {
2754 if (__predict_false(th == NULL)) {
2756 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2758 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2760 pi->ipi_tcp_hflags = th->th_flags;
2761 pi->ipi_tcp_hlen = th->th_off << 2;
2762 pi->ipi_tcp_seq = th->th_seq;
2765 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2767 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2768 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2769 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2770 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2772 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2779 case ETHERTYPE_IPV6:
2781 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2783 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2785 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2786 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2789 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2791 /* XXX-BZ this will go badly in case of ext hdrs. */
2792 pi->ipi_ipproto = ip6->ip6_nxt;
2793 pi->ipi_flags |= IPI_TX_IPV6;
2795 if (pi->ipi_ipproto == IPPROTO_TCP) {
2796 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2797 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2800 pi->ipi_tcp_hflags = th->th_flags;
2801 pi->ipi_tcp_hlen = th->th_off << 2;
2805 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2808 * The corresponding flag is set by the stack in the IPv4
2809 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2810 * So, set it here because the rest of the flow requires it.
2812 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2813 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2814 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2820 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2821 pi->ipi_ip_hlen = 0;
2829 static __noinline struct mbuf *
2830 collapse_pkthdr(struct mbuf *m0)
2832 struct mbuf *m, *m_next, *tmp;
2836 while (m_next != NULL && m_next->m_len == 0) {
2840 m_next = m_next->m_next;
2844 if ((m_next->m_flags & M_EXT) == 0) {
2845 m = m_defrag(m, M_NOWAIT);
2847 tmp = m_next->m_next;
2848 memcpy(m_next, m, MPKTHSIZE);
2856 * If dodgy hardware rejects the scatter gather chain we've handed it
2857 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2860 static __noinline struct mbuf *
2861 iflib_remove_mbuf(iflib_txq_t txq)
2864 struct mbuf *m, *mh, **ifsd_m;
2866 pidx = txq->ift_pidx;
2867 ifsd_m = txq->ift_sds.ifsd_m;
2868 ntxd = txq->ift_size;
2869 mh = m = ifsd_m[pidx];
2870 ifsd_m[pidx] = NULL;
2872 txq->ift_dequeued++;
2877 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2879 txq->ift_dequeued++;
2888 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2889 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2890 int max_segs, int flags)
2893 if_shared_ctx_t sctx;
2894 if_softc_ctx_t scctx;
2895 int i, next, pidx, err, ntxd, count;
2896 struct mbuf *m, *tmp, **ifsd_m;
2901 * Please don't ever do this
2903 if (__predict_false(m->m_len == 0))
2904 *m0 = m = collapse_pkthdr(m);
2907 sctx = ctx->ifc_sctx;
2908 scctx = &ctx->ifc_softc_ctx;
2909 ifsd_m = txq->ift_sds.ifsd_m;
2910 ntxd = txq->ift_size;
2911 pidx = txq->ift_pidx;
2913 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
2915 err = bus_dmamap_load_mbuf_sg(tag, map,
2916 *m0, segs, nsegs, BUS_DMA_NOWAIT);
2919 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
2923 if (__predict_false(m->m_len <= 0)) {
2930 next = (pidx + count) & (ntxd-1);
2931 MPASS(ifsd_m[next] == NULL);
2936 } while (m != NULL);
2938 int buflen, sgsize, maxsegsz, max_sgsize;
2944 if (m->m_pkthdr.csum_flags & CSUM_TSO)
2945 maxsegsz = scctx->isc_tx_tso_segsize_max;
2947 maxsegsz = sctx->isc_tx_maxsegsize;
2950 if (__predict_false(m->m_len <= 0)) {
2958 vaddr = (vm_offset_t)m->m_data;
2960 * see if we can't be smarter about physically
2961 * contiguous mappings
2963 next = (pidx + count) & (ntxd-1);
2964 MPASS(ifsd_m[next] == NULL);
2966 txq->ift_enqueued++;
2969 while (buflen > 0) {
2970 max_sgsize = MIN(buflen, maxsegsz);
2971 curaddr = pmap_kextract(vaddr);
2972 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
2973 sgsize = MIN(sgsize, max_sgsize);
2974 segs[i].ds_addr = curaddr;
2975 segs[i].ds_len = sgsize;
2985 } while (m != NULL);
2990 *m0 = iflib_remove_mbuf(txq);
2994 static inline caddr_t
2995 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
2999 caddr_t start, end, cur, next;
3001 ntxd = txq->ift_size;
3002 size = txq->ift_txd_size[qid];
3003 start = txq->ift_ifdi[qid].idi_vaddr;
3005 if (__predict_false(size == 0))
3007 cur = start + size*cidx;
3008 end = start + size*ntxd;
3009 next = CACHE_PTR_NEXT(cur);
3010 return (next < end ? next : start);
3014 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3017 if_shared_ctx_t sctx;
3018 if_softc_ctx_t scctx;
3019 bus_dma_segment_t *segs;
3020 struct mbuf *m_head;
3023 struct if_pkt_info pi;
3025 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3026 bus_dma_tag_t desc_tag;
3028 segs = txq->ift_segs;
3030 sctx = ctx->ifc_sctx;
3031 scctx = &ctx->ifc_softc_ctx;
3032 segs = txq->ift_segs;
3033 ntxd = txq->ift_size;
3038 * If we're doing TSO the next descriptor to clean may be quite far ahead
3040 cidx = txq->ift_cidx;
3041 pidx = txq->ift_pidx;
3042 if (ctx->ifc_flags & IFC_PREFETCH) {
3043 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3044 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3045 next_txd = calc_next_txd(txq, cidx, 0);
3049 /* prefetch the next cache line of mbuf pointers and flags */
3050 prefetch(&txq->ift_sds.ifsd_m[next]);
3051 if (txq->ift_sds.ifsd_map != NULL) {
3052 prefetch(&txq->ift_sds.ifsd_map[next]);
3053 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3054 prefetch(&txq->ift_sds.ifsd_flags[next]);
3056 } else if (txq->ift_sds.ifsd_map != NULL)
3057 map = txq->ift_sds.ifsd_map[pidx];
3059 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3060 desc_tag = txq->ift_tso_desc_tag;
3061 max_segs = scctx->isc_tx_tso_segments_max;
3063 desc_tag = txq->ift_desc_tag;
3064 max_segs = scctx->isc_tx_nsegments;
3069 pi.ipi_len = m_head->m_pkthdr.len;
3070 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3071 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3072 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3074 pi.ipi_qsidx = txq->ift_id;
3076 /* deliberate bitwise OR to make one condition */
3077 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3078 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3084 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3086 if (__predict_false(err)) {
3089 /* try collapse once and defrag once */
3091 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3093 m_head = m_defrag(*m_headp, M_NOWAIT);
3095 if (__predict_false(m_head == NULL))
3097 txq->ift_mbuf_defrag++;
3102 txq->ift_no_tx_dma_setup++;
3105 txq->ift_no_tx_dma_setup++;
3107 DBG_COUNTER_INC(tx_frees);
3111 txq->ift_map_failed++;
3112 DBG_COUNTER_INC(encap_load_mbuf_fail);
3117 * XXX assumes a 1 to 1 relationship between segments and
3118 * descriptors - this does not hold true on all drivers, e.g.
3121 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3122 txq->ift_no_desc_avail++;
3124 bus_dmamap_unload(desc_tag, map);
3125 DBG_COUNTER_INC(encap_txq_avail_fail);
3126 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3127 GROUPTASK_ENQUEUE(&txq->ift_task);
3131 * On Intel cards we can greatly reduce the number of TX interrupts
3132 * we see by only setting report status on every Nth descriptor.
3133 * However, this also means that the driver will need to keep track
3134 * of the descriptors that RS was set on to check them for the DD bit.
3136 txq->ift_rs_pending += nsegs + 1;
3137 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3138 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3139 pi.ipi_flags |= IPI_TX_INTR;
3140 txq->ift_rs_pending = 0;
3144 pi.ipi_nsegs = nsegs;
3146 MPASS(pidx >= 0 && pidx < txq->ift_size);
3151 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3152 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3154 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3155 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3156 DBG_COUNTER_INC(tx_encap);
3157 MPASS(pi.ipi_new_pidx < txq->ift_size);
3159 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3160 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3161 ndesc += txq->ift_size;
3165 * drivers can need as many as
3168 MPASS(ndesc <= pi.ipi_nsegs + 2);
3169 MPASS(pi.ipi_new_pidx != pidx);
3171 txq->ift_in_use += ndesc;
3174 * We update the last software descriptor again here because there may
3175 * be a sentinel and/or there may be more mbufs than segments
3177 txq->ift_pidx = pi.ipi_new_pidx;
3178 txq->ift_npending += pi.ipi_ndescs;
3179 } else if (__predict_false(err == EFBIG && remap < 2)) {
3180 *m_headp = m_head = iflib_remove_mbuf(txq);
3182 txq->ift_txd_encap_efbig++;
3185 DBG_COUNTER_INC(encap_txd_encap_fail);
3189 txq->ift_mbuf_defrag_failed++;
3190 txq->ift_map_failed++;
3192 DBG_COUNTER_INC(tx_frees);
3198 iflib_tx_desc_free(iflib_txq_t txq, int n)
3201 uint32_t qsize, cidx, mask, gen;
3202 struct mbuf *m, **ifsd_m;
3203 uint8_t *ifsd_flags;
3204 bus_dmamap_t *ifsd_map;
3207 cidx = txq->ift_cidx;
3209 qsize = txq->ift_size;
3211 hasmap = txq->ift_sds.ifsd_map != NULL;
3212 ifsd_flags = txq->ift_sds.ifsd_flags;
3213 ifsd_m = txq->ift_sds.ifsd_m;
3214 ifsd_map = txq->ift_sds.ifsd_map;
3215 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3219 prefetch(ifsd_m[(cidx + 3) & mask]);
3220 prefetch(ifsd_m[(cidx + 4) & mask]);
3222 if (ifsd_m[cidx] != NULL) {
3223 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3224 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3225 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3227 * does it matter if it's not the TSO tag? If so we'll
3228 * have to add the type to flags
3230 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3231 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3233 if ((m = ifsd_m[cidx]) != NULL) {
3234 /* XXX we don't support any drivers that batch packets yet */
3235 MPASS(m->m_nextpkt == NULL);
3238 ifsd_m[cidx] = NULL;
3240 txq->ift_dequeued++;
3242 DBG_COUNTER_INC(tx_frees);
3245 if (__predict_false(++cidx == qsize)) {
3250 txq->ift_cidx = cidx;
3255 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3258 if_ctx_t ctx = txq->ift_ctx;
3260 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3261 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3264 * Need a rate-limiting check so that this isn't called every time
3266 iflib_tx_credits_update(ctx, txq);
3267 reclaim = DESC_RECLAIMABLE(txq);
3269 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3271 if (iflib_verbose_debug) {
3272 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3273 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3280 iflib_tx_desc_free(txq, reclaim);
3281 txq->ift_cleaned += reclaim;
3282 txq->ift_in_use -= reclaim;
3287 static struct mbuf **
3288 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3291 struct mbuf **items;
3294 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3295 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3297 prefetch(items[(cidx + offset) & (size-1)]);
3298 if (remaining > 1) {
3299 prefetch(&items[next]);
3300 prefetch(items[(cidx + offset + 1) & (size-1)]);
3301 prefetch(items[(cidx + offset + 2) & (size-1)]);
3302 prefetch(items[(cidx + offset + 3) & (size-1)]);
3304 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3308 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3311 ifmp_ring_check_drainage(txq->ift_br, budget);
3315 iflib_txq_can_drain(struct ifmp_ring *r)
3317 iflib_txq_t txq = r->cookie;
3318 if_ctx_t ctx = txq->ift_ctx;
3320 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3321 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3325 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3327 iflib_txq_t txq = r->cookie;
3328 if_ctx_t ctx = txq->ift_ctx;
3329 struct ifnet *ifp = ctx->ifc_ifp;
3330 struct mbuf **mp, *m;
3331 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3332 int reclaimed, err, in_use_prev, desc_used;
3333 bool do_prefetch, ring, rang;
3335 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3336 !LINK_ACTIVE(ctx))) {
3337 DBG_COUNTER_INC(txq_drain_notready);
3340 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3341 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3342 avail = IDXDIFF(pidx, cidx, r->size);
3343 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3344 DBG_COUNTER_INC(txq_drain_flushing);
3345 for (i = 0; i < avail; i++) {
3346 m_free(r->items[(cidx + i) & (r->size-1)]);
3347 r->items[(cidx + i) & (r->size-1)] = NULL;
3352 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3353 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3355 callout_stop(&txq->ift_timer);
3356 CALLOUT_UNLOCK(txq);
3357 DBG_COUNTER_INC(txq_drain_oactive);
3361 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3362 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3363 count = MIN(avail, TX_BATCH_SIZE);
3365 if (iflib_verbose_debug)
3366 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3367 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3369 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3370 avail = TXQ_AVAIL(txq);
3371 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3372 int pidx_prev, rem = do_prefetch ? count - i : 0;
3374 mp = _ring_peek_one(r, cidx, i, rem);
3375 MPASS(mp != NULL && *mp != NULL);
3376 if (__predict_false(*mp == (struct mbuf *)txq)) {
3381 in_use_prev = txq->ift_in_use;
3382 pidx_prev = txq->ift_pidx;
3383 err = iflib_encap(txq, mp);
3384 if (__predict_false(err)) {
3385 DBG_COUNTER_INC(txq_drain_encapfail);
3386 /* no room - bail out */
3390 DBG_COUNTER_INC(txq_drain_encapfail);
3391 /* we can't send this packet - skip it */
3397 DBG_COUNTER_INC(tx_sent);
3398 bytes_sent += m->m_pkthdr.len;
3399 mcast_sent += !!(m->m_flags & M_MCAST);
3400 avail = TXQ_AVAIL(txq);
3402 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3403 desc_used += (txq->ift_in_use - in_use_prev);
3404 ETHER_BPF_MTAP(ifp, m);
3405 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3407 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3410 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3411 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3412 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3413 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3414 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3416 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3418 if (iflib_verbose_debug)
3419 printf("consumed=%d\n", consumed);
3425 iflib_txq_drain_always(struct ifmp_ring *r)
3431 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3439 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3441 callout_stop(&txq->ift_timer);
3442 CALLOUT_UNLOCK(txq);
3444 avail = IDXDIFF(pidx, cidx, r->size);
3445 for (i = 0; i < avail; i++) {
3446 mp = _ring_peek_one(r, cidx, i, avail - i);
3447 if (__predict_false(*mp == (struct mbuf *)txq))
3451 MPASS(ifmp_ring_is_stalled(r) == 0);
3456 iflib_ifmp_purge(iflib_txq_t txq)
3458 struct ifmp_ring *r;
3461 r->drain = iflib_txq_drain_free;
3462 r->can_drain = iflib_txq_drain_always;
3464 ifmp_ring_check_drainage(r, r->size);
3466 r->drain = iflib_txq_drain;
3467 r->can_drain = iflib_txq_can_drain;
3471 _task_fn_tx(void *context)
3473 iflib_txq_t txq = context;
3474 if_ctx_t ctx = txq->ift_ctx;
3475 struct ifnet *ifp = ctx->ifc_ifp;
3478 #ifdef IFLIB_DIAGNOSTICS
3479 txq->ift_cpu_exec_count[curcpu]++;
3481 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3483 if ((ifp->if_capenable & IFCAP_NETMAP)) {
3484 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3485 netmap_tx_irq(ifp, txq->ift_id);
3486 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3489 if (txq->ift_db_pending)
3490 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3492 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3493 if (ctx->ifc_flags & IFC_LEGACY)
3494 IFDI_INTR_ENABLE(ctx);
3496 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3497 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3502 _task_fn_rx(void *context)
3504 iflib_rxq_t rxq = context;
3505 if_ctx_t ctx = rxq->ifr_ctx;
3509 #ifdef IFLIB_DIAGNOSTICS
3510 rxq->ifr_cpu_exec_count[curcpu]++;
3512 DBG_COUNTER_INC(task_fn_rxs);
3513 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3515 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) {
3516 if (ctx->ifc_flags & IFC_LEGACY)
3517 IFDI_INTR_ENABLE(ctx);
3519 DBG_COUNTER_INC(rx_intr_enables);
3520 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3521 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3524 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3527 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3531 _task_fn_admin(void *context)
3533 if_ctx_t ctx = context;
3534 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3538 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) {
3539 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3545 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3547 callout_stop(&txq->ift_timer);
3548 CALLOUT_UNLOCK(txq);
3550 IFDI_UPDATE_ADMIN_STATUS(ctx);
3551 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3552 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3553 IFDI_LINK_INTR_ENABLE(ctx);
3554 if (ctx->ifc_flags & IFC_DO_RESET) {
3555 ctx->ifc_flags &= ~IFC_DO_RESET;
3556 iflib_if_init_locked(ctx);
3560 if (LINK_ACTIVE(ctx) == 0)
3562 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3563 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3568 _task_fn_iov(void *context)
3570 if_ctx_t ctx = context;
3572 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3576 IFDI_VFLR_HANDLE(ctx);
3581 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3584 if_int_delay_info_t info;
3587 info = (if_int_delay_info_t)arg1;
3588 ctx = info->iidi_ctx;
3589 info->iidi_req = req;
3590 info->iidi_oidp = oidp;
3592 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3597 /*********************************************************************
3601 **********************************************************************/
3604 iflib_if_init_locked(if_ctx_t ctx)
3607 iflib_init_locked(ctx);
3612 iflib_if_init(void *arg)
3617 iflib_if_init_locked(ctx);
3622 iflib_if_transmit(if_t ifp, struct mbuf *m)
3624 if_ctx_t ctx = if_getsoftc(ifp);
3629 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3630 DBG_COUNTER_INC(tx_frees);
3635 MPASS(m->m_nextpkt == NULL);
3637 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3638 qidx = QIDX(ctx, m);
3640 * XXX calculate buf_ring based on flowid (divvy up bits?)
3642 txq = &ctx->ifc_txqs[qidx];
3644 #ifdef DRIVER_BACKPRESSURE
3645 if (txq->ift_closed) {
3647 next = m->m_nextpkt;
3648 m->m_nextpkt = NULL;
3661 next = next->m_nextpkt;
3662 } while (next != NULL);
3664 if (count > nitems(marr))
3665 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3666 /* XXX check nextpkt */
3668 /* XXX simplify for now */
3669 DBG_COUNTER_INC(tx_frees);
3672 for (next = m, i = 0; next != NULL; i++) {
3674 next = next->m_nextpkt;
3675 mp[i]->m_nextpkt = NULL;
3678 DBG_COUNTER_INC(tx_seen);
3679 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3682 GROUPTASK_ENQUEUE(&txq->ift_task);
3683 /* support forthcoming later */
3684 #ifdef DRIVER_BACKPRESSURE
3685 txq->ift_closed = TRUE;
3687 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3689 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) {
3690 GROUPTASK_ENQUEUE(&txq->ift_task);
3697 iflib_if_qflush(if_t ifp)
3699 if_ctx_t ctx = if_getsoftc(ifp);
3700 iflib_txq_t txq = ctx->ifc_txqs;
3704 ctx->ifc_flags |= IFC_QFLUSH;
3706 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3707 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3708 iflib_txq_check_drain(txq, 0);
3710 ctx->ifc_flags &= ~IFC_QFLUSH;
3717 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3718 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \
3719 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3722 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3724 if_ctx_t ctx = if_getsoftc(ifp);
3725 struct ifreq *ifr = (struct ifreq *)data;
3726 #if defined(INET) || defined(INET6)
3727 struct ifaddr *ifa = (struct ifaddr *)data;
3729 bool avoid_reset = FALSE;
3730 int err = 0, reinit = 0, bits;
3735 if (ifa->ifa_addr->sa_family == AF_INET)
3739 if (ifa->ifa_addr->sa_family == AF_INET6)
3743 ** Calling init results in link renegotiation,
3744 ** so we avoid doing it when possible.
3747 if_setflagbits(ifp, IFF_UP,0);
3748 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3751 if (!(if_getflags(ifp) & IFF_NOARP))
3752 arp_ifinit(ifp, ifa);
3755 err = ether_ioctl(ifp, command, data);
3759 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3763 bits = if_getdrvflags(ifp);
3764 /* stop the driver and free any clusters before proceeding */
3767 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3768 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3769 ctx->ifc_flags |= IFC_MULTISEG;
3771 ctx->ifc_flags &= ~IFC_MULTISEG;
3772 err = if_setmtu(ifp, ifr->ifr_mtu);
3774 iflib_init_locked(ctx);
3775 if_setdrvflags(ifp, bits);
3780 if (if_getflags(ifp) & IFF_UP) {
3781 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3782 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3783 (IFF_PROMISC | IFF_ALLMULTI)) {
3784 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3788 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3791 ctx->ifc_if_flags = if_getflags(ifp);
3796 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3798 IFDI_INTR_DISABLE(ctx);
3799 IFDI_MULTI_SET(ctx);
3800 IFDI_INTR_ENABLE(ctx);
3806 IFDI_MEDIA_SET(ctx);
3810 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3814 struct ifi2creq i2c;
3816 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3819 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3823 if (i2c.len > sizeof(i2c.data)) {
3828 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3829 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
3836 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3839 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
3841 setmask |= (mask & IFCAP_FLAGS);
3843 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
3844 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
3845 if ((mask & IFCAP_WOL) &&
3846 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
3847 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
3850 * want to ensure that traffic has stopped before we change any of the flags
3854 bits = if_getdrvflags(ifp);
3855 if (bits & IFF_DRV_RUNNING)
3857 if_togglecapenable(ifp, setmask);
3858 if (bits & IFF_DRV_RUNNING)
3859 iflib_init_locked(ctx);
3860 if_setdrvflags(ifp, bits);
3865 case SIOCGPRIVATE_0:
3869 err = IFDI_PRIV_IOCTL(ctx, command, data);
3873 err = ether_ioctl(ifp, command, data);
3882 iflib_if_get_counter(if_t ifp, ift_counter cnt)
3884 if_ctx_t ctx = if_getsoftc(ifp);
3886 return (IFDI_GET_COUNTER(ctx, cnt));
3889 /*********************************************************************
3891 * OTHER FUNCTIONS EXPORTED TO THE STACK
3893 **********************************************************************/
3896 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
3898 if_ctx_t ctx = if_getsoftc(ifp);
3900 if ((void *)ctx != arg)
3903 if ((vtag == 0) || (vtag > 4095))
3907 IFDI_VLAN_REGISTER(ctx, vtag);
3908 /* Re-init to load the changes */
3909 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3910 iflib_init_locked(ctx);
3915 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
3917 if_ctx_t ctx = if_getsoftc(ifp);
3919 if ((void *)ctx != arg)
3922 if ((vtag == 0) || (vtag > 4095))
3926 IFDI_VLAN_UNREGISTER(ctx, vtag);
3927 /* Re-init to load the changes */
3928 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3929 iflib_init_locked(ctx);
3934 iflib_led_func(void *arg, int onoff)
3939 IFDI_LED_FUNC(ctx, onoff);
3943 /*********************************************************************
3945 * BUS FUNCTION DEFINITIONS
3947 **********************************************************************/
3950 iflib_device_probe(device_t dev)
3952 pci_vendor_info_t *ent;
3954 uint16_t pci_vendor_id, pci_device_id;
3955 uint16_t pci_subvendor_id, pci_subdevice_id;
3956 uint16_t pci_rev_id;
3957 if_shared_ctx_t sctx;
3959 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
3962 pci_vendor_id = pci_get_vendor(dev);
3963 pci_device_id = pci_get_device(dev);
3964 pci_subvendor_id = pci_get_subvendor(dev);
3965 pci_subdevice_id = pci_get_subdevice(dev);
3966 pci_rev_id = pci_get_revid(dev);
3967 if (sctx->isc_parse_devinfo != NULL)
3968 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
3970 ent = sctx->isc_vendor_info;
3971 while (ent->pvi_vendor_id != 0) {
3972 if (pci_vendor_id != ent->pvi_vendor_id) {
3976 if ((pci_device_id == ent->pvi_device_id) &&
3977 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
3978 (ent->pvi_subvendor_id == 0)) &&
3979 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
3980 (ent->pvi_subdevice_id == 0)) &&
3981 ((pci_rev_id == ent->pvi_rev_id) ||
3982 (ent->pvi_rev_id == 0))) {
3984 device_set_desc_copy(dev, ent->pvi_name);
3985 /* this needs to be changed to zero if the bus probing code
3986 * ever stops re-probing on best match because the sctx
3987 * may have its values over written by register calls
3988 * in subsequent probes
3990 return (BUS_PROBE_DEFAULT);
3998 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4000 int err, rid, msix, msix_bar;
4003 if_softc_ctx_t scctx;
4009 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4012 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4013 device_set_softc(dev, ctx);
4014 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4017 ctx->ifc_sctx = sctx;
4019 ctx->ifc_softc = sc;
4021 if ((err = iflib_register(ctx)) != 0) {
4022 device_printf(dev, "iflib_register failed %d\n", err);
4025 iflib_add_device_sysctl_pre(ctx);
4027 scctx = &ctx->ifc_softc_ctx;
4031 * XXX sanity check that ntxd & nrxd are a power of 2
4033 if (ctx->ifc_sysctl_ntxqs != 0)
4034 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4035 if (ctx->ifc_sysctl_nrxqs != 0)
4036 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4038 for (i = 0; i < sctx->isc_ntxqs; i++) {
4039 if (ctx->ifc_sysctl_ntxds[i] != 0)
4040 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4042 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4045 for (i = 0; i < sctx->isc_nrxqs; i++) {
4046 if (ctx->ifc_sysctl_nrxds[i] != 0)
4047 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4049 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4052 for (i = 0; i < sctx->isc_nrxqs; i++) {
4053 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4054 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4055 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4056 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4058 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4059 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4060 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4061 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4065 for (i = 0; i < sctx->isc_ntxqs; i++) {
4066 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4067 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4068 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4069 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4071 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4072 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4073 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4074 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4078 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4079 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4082 _iflib_pre_assert(scctx);
4083 ctx->ifc_txrx = *scctx->isc_txrx;
4086 MPASS(scctx->isc_capenable);
4087 if (scctx->isc_capenable & IFCAP_TXCSUM)
4088 MPASS(scctx->isc_tx_csum_flags);
4091 if_setcapabilities(ifp, scctx->isc_capenable);
4092 if_setcapenable(ifp, scctx->isc_capenable);
4094 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4095 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4096 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4097 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4100 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4101 ctx->ifc_flags |= IFC_DMAR;
4102 #elif !(defined(__i386__) || defined(__amd64__))
4103 /* set unconditionally for !x86 */
4104 ctx->ifc_flags |= IFC_DMAR;
4107 msix_bar = scctx->isc_msix_bar;
4108 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4109 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4111 /* XXX change for per-queue sizes */
4112 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4113 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4114 for (i = 0; i < sctx->isc_nrxqs; i++) {
4115 if (!powerof2(scctx->isc_nrxd[i])) {
4116 /* round down instead? */
4117 device_printf(dev, "# rx descriptors must be a power of 2\n");
4122 for (i = 0; i < sctx->isc_ntxqs; i++) {
4123 if (!powerof2(scctx->isc_ntxd[i])) {
4125 "# tx descriptors must be a power of 2");
4131 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4132 MAX_SINGLE_PACKET_FRACTION)
4133 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4134 MAX_SINGLE_PACKET_FRACTION);
4135 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4136 MAX_SINGLE_PACKET_FRACTION)
4137 scctx->isc_tx_tso_segments_max = max(1,
4138 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4141 * Protect the stack against modern hardware
4143 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4144 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4146 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4147 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4148 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4149 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4150 if (scctx->isc_rss_table_size == 0)
4151 scctx->isc_rss_table_size = 64;
4152 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4154 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4155 /* XXX format name */
4156 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4158 ** Now setup MSI or MSI/X, should
4159 ** return us the number of supported
4160 ** vectors. (Will be 1 for MSI)
4162 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4163 msix = scctx->isc_vectors;
4164 } else if (scctx->isc_msix_bar != 0)
4166 * The simple fact that isc_msix_bar is not 0 does not mean we
4167 * we have a good value there that is known to work.
4169 msix = iflib_msix_init(ctx);
4171 scctx->isc_vectors = 1;
4172 scctx->isc_ntxqsets = 1;
4173 scctx->isc_nrxqsets = 1;
4174 scctx->isc_intr = IFLIB_INTR_LEGACY;
4177 /* Get memory for the station queues */
4178 if ((err = iflib_queues_alloc(ctx))) {
4179 device_printf(dev, "Unable to allocate queue memory\n");
4183 if ((err = iflib_qset_structures_setup(ctx))) {
4184 device_printf(dev, "qset structure setup failed %d\n", err);
4189 * Group taskqueues aren't properly set up until SMP is started,
4190 * so we disable interrupts until we can handle them post
4193 * XXX: disabling interrupts doesn't actually work, at least for
4194 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4195 * we do null handling and depend on this not causing too large an
4198 IFDI_INTR_DISABLE(ctx);
4199 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4200 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4201 goto fail_intr_free;
4205 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4209 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4210 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4211 goto fail_intr_free;
4214 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4215 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4216 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4219 if ((err = iflib_netmap_attach(ctx))) {
4220 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4225 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4226 iflib_add_device_sysctl_post(ctx);
4227 ctx->ifc_flags |= IFC_INIT_DONE;
4230 ether_ifdetach(ctx->ifc_ifp);
4232 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4233 pci_release_msi(ctx->ifc_dev);
4235 /* XXX free queues */
4242 iflib_device_attach(device_t dev)
4245 if_shared_ctx_t sctx;
4247 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4250 pci_enable_busmaster(dev);
4252 return (iflib_device_register(dev, NULL, sctx, &ctx));
4256 iflib_device_deregister(if_ctx_t ctx)
4258 if_t ifp = ctx->ifc_ifp;
4261 device_t dev = ctx->ifc_dev;
4263 struct taskqgroup *tqg;
4266 /* Make sure VLANS are not using driver */
4267 if (if_vlantrunkinuse(ifp)) {
4268 device_printf(dev,"Vlan in use, detach first\n");
4273 ctx->ifc_in_detach = 1;
4277 /* Unregister VLAN events */
4278 if (ctx->ifc_vlan_attach_event != NULL)
4279 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4280 if (ctx->ifc_vlan_detach_event != NULL)
4281 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4283 iflib_netmap_detach(ifp);
4284 ether_ifdetach(ifp);
4285 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4286 CTX_LOCK_DESTROY(ctx);
4287 if (ctx->ifc_led_dev != NULL)
4288 led_destroy(ctx->ifc_led_dev);
4289 /* XXX drain any dependent tasks */
4290 tqg = qgroup_if_io_tqg;
4291 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4292 callout_drain(&txq->ift_timer);
4293 if (txq->ift_task.gt_uniq != NULL)
4294 taskqgroup_detach(tqg, &txq->ift_task);
4296 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4297 if (rxq->ifr_task.gt_uniq != NULL)
4298 taskqgroup_detach(tqg, &rxq->ifr_task);
4300 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4301 free(fl->ifl_rx_bitmap, M_IFLIB);
4304 tqg = qgroup_if_config_tqg;
4305 if (ctx->ifc_admin_task.gt_uniq != NULL)
4306 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4307 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4308 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4311 device_set_softc(ctx->ifc_dev, NULL);
4312 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4313 pci_release_msi(dev);
4315 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4316 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4318 if (ctx->ifc_msix_mem != NULL) {
4319 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4320 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4321 ctx->ifc_msix_mem = NULL;
4324 bus_generic_detach(dev);
4327 iflib_tx_structures_free(ctx);
4328 iflib_rx_structures_free(ctx);
4329 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4330 free(ctx->ifc_softc, M_IFLIB);
4337 iflib_device_detach(device_t dev)
4339 if_ctx_t ctx = device_get_softc(dev);
4341 return (iflib_device_deregister(ctx));
4345 iflib_device_suspend(device_t dev)
4347 if_ctx_t ctx = device_get_softc(dev);
4353 return bus_generic_suspend(dev);
4356 iflib_device_shutdown(device_t dev)
4358 if_ctx_t ctx = device_get_softc(dev);
4364 return bus_generic_suspend(dev);
4369 iflib_device_resume(device_t dev)
4371 if_ctx_t ctx = device_get_softc(dev);
4372 iflib_txq_t txq = ctx->ifc_txqs;
4376 iflib_init_locked(ctx);
4378 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4379 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4381 return (bus_generic_resume(dev));
4385 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4388 if_ctx_t ctx = device_get_softc(dev);
4391 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4398 iflib_device_iov_uninit(device_t dev)
4400 if_ctx_t ctx = device_get_softc(dev);
4403 IFDI_IOV_UNINIT(ctx);
4408 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4411 if_ctx_t ctx = device_get_softc(dev);
4414 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4420 /*********************************************************************
4422 * MODULE FUNCTION DEFINITIONS
4424 **********************************************************************/
4427 * - Start a fast taskqueue thread for each core
4428 * - Start a taskqueue for control operations
4431 iflib_module_init(void)
4437 iflib_module_event_handler(module_t mod, int what, void *arg)
4443 if ((err = iflib_module_init()) != 0)
4449 return (EOPNOTSUPP);
4455 /*********************************************************************
4457 * PUBLIC FUNCTION DEFINITIONS
4458 * ordered as in iflib.h
4460 **********************************************************************/
4464 _iflib_assert(if_shared_ctx_t sctx)
4466 MPASS(sctx->isc_tx_maxsize);
4467 MPASS(sctx->isc_tx_maxsegsize);
4469 MPASS(sctx->isc_rx_maxsize);
4470 MPASS(sctx->isc_rx_nsegments);
4471 MPASS(sctx->isc_rx_maxsegsize);
4473 MPASS(sctx->isc_nrxd_min[0]);
4474 MPASS(sctx->isc_nrxd_max[0]);
4475 MPASS(sctx->isc_nrxd_default[0]);
4476 MPASS(sctx->isc_ntxd_min[0]);
4477 MPASS(sctx->isc_ntxd_max[0]);
4478 MPASS(sctx->isc_ntxd_default[0]);
4482 _iflib_pre_assert(if_softc_ctx_t scctx)
4485 MPASS(scctx->isc_txrx->ift_txd_encap);
4486 MPASS(scctx->isc_txrx->ift_txd_flush);
4487 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4488 MPASS(scctx->isc_txrx->ift_rxd_available);
4489 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4490 MPASS(scctx->isc_txrx->ift_rxd_refill);
4491 MPASS(scctx->isc_txrx->ift_rxd_flush);
4495 iflib_register(if_ctx_t ctx)
4497 if_shared_ctx_t sctx = ctx->ifc_sctx;
4498 driver_t *driver = sctx->isc_driver;
4499 device_t dev = ctx->ifc_dev;
4502 _iflib_assert(sctx);
4504 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4506 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4508 device_printf(dev, "can not allocate ifnet structure\n");
4513 * Initialize our context's device specific methods
4515 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4516 kobj_class_compile((kobj_class_t) driver);
4519 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4520 if_setsoftc(ifp, ctx);
4521 if_setdev(ifp, dev);
4522 if_setinitfn(ifp, iflib_if_init);
4523 if_setioctlfn(ifp, iflib_if_ioctl);
4524 if_settransmitfn(ifp, iflib_if_transmit);
4525 if_setqflushfn(ifp, iflib_if_qflush);
4526 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4528 ctx->ifc_vlan_attach_event =
4529 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4530 EVENTHANDLER_PRI_FIRST);
4531 ctx->ifc_vlan_detach_event =
4532 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4533 EVENTHANDLER_PRI_FIRST);
4535 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4536 iflib_media_change, iflib_media_status);
4543 iflib_queues_alloc(if_ctx_t ctx)
4545 if_shared_ctx_t sctx = ctx->ifc_sctx;
4546 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4547 device_t dev = ctx->ifc_dev;
4548 int nrxqsets = scctx->isc_nrxqsets;
4549 int ntxqsets = scctx->isc_ntxqsets;
4552 iflib_fl_t fl = NULL;
4553 int i, j, cpu, err, txconf, rxconf;
4554 iflib_dma_info_t ifdip;
4555 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4556 uint32_t *txqsizes = scctx->isc_txqsizes;
4557 uint8_t nrxqs = sctx->isc_nrxqs;
4558 uint8_t ntxqs = sctx->isc_ntxqs;
4559 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4562 struct ifmp_ring **brscp;
4564 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4565 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4571 /* Allocate the TX ring struct memory */
4573 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4574 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4575 device_printf(dev, "Unable to allocate TX ring memory\n");
4580 /* Now allocate the RX */
4582 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4583 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4584 device_printf(dev, "Unable to allocate RX ring memory\n");
4589 ctx->ifc_txqs = txq;
4590 ctx->ifc_rxqs = rxq;
4593 * XXX handle allocation failure
4595 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4596 /* Set up some basics */
4598 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4599 device_printf(dev, "failed to allocate iflib_dma_info\n");
4603 txq->ift_ifdi = ifdip;
4604 for (j = 0; j < ntxqs; j++, ifdip++) {
4605 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4606 device_printf(dev, "Unable to allocate Descriptor memory\n");
4610 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4611 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4615 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4616 txq->ift_br_offset = 1;
4618 txq->ift_br_offset = 0;
4621 txq->ift_timer.c_cpu = cpu;
4623 if (iflib_txsd_alloc(txq)) {
4624 device_printf(dev, "Critical Failure setting up TX buffers\n");
4629 /* Initialize the TX lock */
4630 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4631 device_get_nameunit(dev), txq->ift_id);
4632 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4633 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4635 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4636 device_get_nameunit(dev), txq->ift_id);
4638 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4639 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4641 /* XXX free any allocated rings */
4642 device_printf(dev, "Unable to allocate buf_ring\n");
4647 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4648 /* Set up some basics */
4650 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4651 device_printf(dev, "failed to allocate iflib_dma_info\n");
4656 rxq->ifr_ifdi = ifdip;
4657 /* XXX this needs to be changed if #rx queues != #tx queues */
4658 rxq->ifr_ntxqirq = 1;
4659 rxq->ifr_txqid[0] = i;
4660 for (j = 0; j < nrxqs; j++, ifdip++) {
4661 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4662 device_printf(dev, "Unable to allocate Descriptor memory\n");
4666 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4670 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4671 rxq->ifr_fl_offset = 1;
4673 rxq->ifr_fl_offset = 0;
4675 rxq->ifr_nfl = nfree_lists;
4677 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4678 device_printf(dev, "Unable to allocate free list memory\n");
4683 for (j = 0; j < nfree_lists; j++) {
4684 fl[j].ifl_rxq = rxq;
4686 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4687 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4689 /* Allocate receive buffers for the ring*/
4690 if (iflib_rxsd_alloc(rxq)) {
4692 "Critical Failure setting up receive buffers\n");
4697 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4698 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4702 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4703 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4704 for (i = 0; i < ntxqsets; i++) {
4705 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4707 for (j = 0; j < ntxqs; j++, di++) {
4708 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4709 paddrs[i*ntxqs + j] = di->idi_paddr;
4712 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4713 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4714 iflib_tx_structures_free(ctx);
4715 free(vaddrs, M_IFLIB);
4716 free(paddrs, M_IFLIB);
4719 free(vaddrs, M_IFLIB);
4720 free(paddrs, M_IFLIB);
4723 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4724 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4725 for (i = 0; i < nrxqsets; i++) {
4726 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4728 for (j = 0; j < nrxqs; j++, di++) {
4729 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4730 paddrs[i*nrxqs + j] = di->idi_paddr;
4733 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4734 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4735 iflib_tx_structures_free(ctx);
4736 free(vaddrs, M_IFLIB);
4737 free(paddrs, M_IFLIB);
4740 free(vaddrs, M_IFLIB);
4741 free(paddrs, M_IFLIB);
4745 /* XXX handle allocation failure changes */
4748 if (ctx->ifc_rxqs != NULL)
4749 free(ctx->ifc_rxqs, M_IFLIB);
4750 ctx->ifc_rxqs = NULL;
4751 if (ctx->ifc_txqs != NULL)
4752 free(ctx->ifc_txqs, M_IFLIB);
4753 ctx->ifc_txqs = NULL;
4756 free(brscp, M_IFLIB);
4766 iflib_tx_structures_setup(if_ctx_t ctx)
4768 iflib_txq_t txq = ctx->ifc_txqs;
4771 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4772 iflib_txq_setup(txq);
4778 iflib_tx_structures_free(if_ctx_t ctx)
4780 iflib_txq_t txq = ctx->ifc_txqs;
4783 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4784 iflib_txq_destroy(txq);
4785 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4786 iflib_dma_free(&txq->ift_ifdi[j]);
4788 free(ctx->ifc_txqs, M_IFLIB);
4789 ctx->ifc_txqs = NULL;
4790 IFDI_QUEUES_FREE(ctx);
4793 /*********************************************************************
4795 * Initialize all receive rings.
4797 **********************************************************************/
4799 iflib_rx_structures_setup(if_ctx_t ctx)
4801 iflib_rxq_t rxq = ctx->ifc_rxqs;
4803 #if defined(INET6) || defined(INET)
4807 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4808 #if defined(INET6) || defined(INET)
4809 tcp_lro_free(&rxq->ifr_lc);
4810 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4811 TCP_LRO_ENTRIES, min(1024,
4812 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4813 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4816 rxq->ifr_lro_enabled = TRUE;
4818 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4821 #if defined(INET6) || defined(INET)
4824 * Free RX software descriptors allocated so far, we will only handle
4825 * the rings that completed, the failing case will have
4826 * cleaned up for itself. 'q' failed, so its the terminus.
4828 rxq = ctx->ifc_rxqs;
4829 for (i = 0; i < q; ++i, rxq++) {
4830 iflib_rx_sds_free(rxq);
4831 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
4837 /*********************************************************************
4839 * Free all receive rings.
4841 **********************************************************************/
4843 iflib_rx_structures_free(if_ctx_t ctx)
4845 iflib_rxq_t rxq = ctx->ifc_rxqs;
4847 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
4848 iflib_rx_sds_free(rxq);
4853 iflib_qset_structures_setup(if_ctx_t ctx)
4857 if ((err = iflib_tx_structures_setup(ctx)) != 0)
4860 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
4861 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
4862 iflib_tx_structures_free(ctx);
4863 iflib_rx_structures_free(ctx);
4869 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
4870 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
4873 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
4877 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid)
4879 int i, cpuid, eqid, count;
4881 CPU_COPY(&ctx->ifc_cpus, cpus);
4882 count = CPU_COUNT(&ctx->ifc_cpus);
4884 /* clear up to the qid'th bit */
4885 for (i = 0; i < eqid; i++) {
4886 cpuid = CPU_FFS(cpus);
4888 CPU_CLR(cpuid-1, cpus);
4890 cpuid = CPU_FFS(cpus);
4896 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
4897 iflib_intr_type_t type, driver_filter_t *filter,
4898 void *filter_arg, int qid, char *name)
4900 struct grouptask *gtask;
4901 struct taskqgroup *tqg;
4902 iflib_filter_info_t info;
4905 int tqrid, err, cpuid;
4906 driver_filter_t *intr_fast;
4909 info = &ctx->ifc_filter_info;
4913 /* XXX merge tx/rx for netmap? */
4915 q = &ctx->ifc_txqs[qid];
4916 info = &ctx->ifc_txqs[qid].ift_filter_info;
4917 gtask = &ctx->ifc_txqs[qid].ift_task;
4918 tqg = qgroup_if_io_tqg;
4920 intr_fast = iflib_fast_intr;
4921 GROUPTASK_INIT(gtask, 0, fn, q);
4924 q = &ctx->ifc_rxqs[qid];
4925 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4926 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4927 tqg = qgroup_if_io_tqg;
4929 intr_fast = iflib_fast_intr;
4930 GROUPTASK_INIT(gtask, 0, fn, q);
4932 case IFLIB_INTR_RXTX:
4933 q = &ctx->ifc_rxqs[qid];
4934 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
4935 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4936 tqg = qgroup_if_io_tqg;
4938 intr_fast = iflib_fast_intr_rxtx;
4939 GROUPTASK_INIT(gtask, 0, fn, q);
4941 case IFLIB_INTR_ADMIN:
4944 info = &ctx->ifc_filter_info;
4945 gtask = &ctx->ifc_admin_task;
4946 tqg = qgroup_if_config_tqg;
4947 fn = _task_fn_admin;
4948 intr_fast = iflib_fast_intr_ctx;
4951 panic("unknown net intr type");
4954 info->ifi_filter = filter;
4955 info->ifi_filter_arg = filter_arg;
4956 info->ifi_task = gtask;
4959 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
4961 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
4964 if (type == IFLIB_INTR_ADMIN)
4968 cpuid = find_nth(ctx, &cpus, qid);
4969 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name);
4971 taskqgroup_attach(tqg, gtask, q, tqrid, name);
4978 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name)
4980 struct grouptask *gtask;
4981 struct taskqgroup *tqg;
4987 q = &ctx->ifc_txqs[qid];
4988 gtask = &ctx->ifc_txqs[qid].ift_task;
4989 tqg = qgroup_if_io_tqg;
4993 q = &ctx->ifc_rxqs[qid];
4994 gtask = &ctx->ifc_rxqs[qid].ifr_task;
4995 tqg = qgroup_if_io_tqg;
4998 case IFLIB_INTR_IOV:
5000 gtask = &ctx->ifc_vflr_task;
5001 tqg = qgroup_if_config_tqg;
5006 panic("unknown net intr type");
5008 GROUPTASK_INIT(gtask, 0, fn, q);
5009 taskqgroup_attach(tqg, gtask, q, rid, name);
5013 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5016 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5019 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5023 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5025 iflib_txq_t txq = ctx->ifc_txqs;
5026 iflib_rxq_t rxq = ctx->ifc_rxqs;
5027 if_irq_t irq = &ctx->ifc_legacy_irq;
5028 iflib_filter_info_t info;
5029 struct grouptask *gtask;
5030 struct taskqgroup *tqg;
5036 q = &ctx->ifc_rxqs[0];
5037 info = &rxq[0].ifr_filter_info;
5038 gtask = &rxq[0].ifr_task;
5039 tqg = qgroup_if_io_tqg;
5040 tqrid = irq->ii_rid = *rid;
5043 ctx->ifc_flags |= IFC_LEGACY;
5044 info->ifi_filter = filter;
5045 info->ifi_filter_arg = filter_arg;
5046 info->ifi_task = gtask;
5047 info->ifi_ctx = ctx;
5049 /* We allocate a single interrupt resource */
5050 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5052 GROUPTASK_INIT(gtask, 0, fn, q);
5053 taskqgroup_attach(tqg, gtask, q, tqrid, name);
5055 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5056 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx");
5061 iflib_led_create(if_ctx_t ctx)
5064 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5065 device_get_nameunit(ctx->ifc_dev));
5069 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5072 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5076 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5079 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5083 iflib_admin_intr_deferred(if_ctx_t ctx)
5086 struct grouptask *gtask;
5088 gtask = &ctx->ifc_admin_task;
5089 MPASS(gtask->gt_taskqueue != NULL);
5092 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5096 iflib_iov_intr_deferred(if_ctx_t ctx)
5099 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5103 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5106 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5110 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
5114 GROUPTASK_INIT(gtask, 0, fn, ctx);
5115 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5119 iflib_config_gtask_deinit(struct grouptask *gtask)
5122 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5126 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5128 if_t ifp = ctx->ifc_ifp;
5129 iflib_txq_t txq = ctx->ifc_txqs;
5131 if_setbaudrate(ifp, baudrate);
5132 if (baudrate >= IF_Gbps(10))
5133 ctx->ifc_flags |= IFC_PREFETCH;
5135 /* If link down, disable watchdog */
5136 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5137 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5138 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5140 ctx->ifc_link_state = link_state;
5141 if_link_state_change(ifp, link_state);
5145 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5149 int credits_pre = txq->ift_cidx_processed;
5152 if (ctx->isc_txd_credits_update == NULL)
5155 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5158 txq->ift_processed += credits;
5159 txq->ift_cidx_processed += credits;
5161 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5162 if (txq->ift_cidx_processed >= txq->ift_size)
5163 txq->ift_cidx_processed -= txq->ift_size;
5168 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5171 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5176 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5177 const char *description, if_int_delay_info_t info,
5178 int offset, int value)
5180 info->iidi_ctx = ctx;
5181 info->iidi_offset = offset;
5182 info->iidi_value = value;
5183 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5184 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5185 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5186 info, 0, iflib_sysctl_int_delay, "I", description);
5190 iflib_ctx_lock_get(if_ctx_t ctx)
5193 return (&ctx->ifc_mtx);
5197 iflib_msix_init(if_ctx_t ctx)
5199 device_t dev = ctx->ifc_dev;
5200 if_shared_ctx_t sctx = ctx->ifc_sctx;
5201 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5202 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5203 int iflib_num_tx_queues, iflib_num_rx_queues;
5204 int err, admincnt, bar;
5206 iflib_num_tx_queues = scctx->isc_ntxqsets;
5207 iflib_num_rx_queues = scctx->isc_nrxqsets;
5209 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues);
5211 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5212 admincnt = sctx->isc_admin_intrcnt;
5213 /* Override by tuneable */
5214 if (scctx->isc_disable_msix)
5218 ** When used in a virtualized environment
5219 ** PCI BUSMASTER capability may not be set
5220 ** so explicity set it here and rewrite
5221 ** the ENABLE in the MSIX control register
5222 ** at this point to cause the host to
5223 ** successfully initialize us.
5228 pci_enable_busmaster(dev);
5230 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5231 rid += PCIR_MSIX_CTRL;
5232 msix_ctrl = pci_read_config(dev, rid, 2);
5233 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5234 pci_write_config(dev, rid, msix_ctrl, 2);
5236 device_printf(dev, "PCIY_MSIX capability not found; "
5237 "or rid %d == 0.\n", rid);
5243 * bar == -1 => "trust me I know what I'm doing"
5244 * Some drivers are for hardware that is so shoddily
5245 * documented that no one knows which bars are which
5246 * so the developer has to map all bars. This hack
5247 * allows shoddy garbage to use msix in this framework.
5250 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5251 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5252 if (ctx->ifc_msix_mem == NULL) {
5253 /* May not be enabled */
5254 device_printf(dev, "Unable to map MSIX table \n");
5258 /* First try MSI/X */
5259 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5260 device_printf(dev, "System has MSIX disabled \n");
5261 bus_release_resource(dev, SYS_RES_MEMORY,
5262 bar, ctx->ifc_msix_mem);
5263 ctx->ifc_msix_mem = NULL;
5267 /* use only 1 qset in debug mode */
5268 queuemsgs = min(msgs - admincnt, 1);
5270 queuemsgs = msgs - admincnt;
5272 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) {
5274 queues = imin(queuemsgs, rss_getnumbuckets());
5278 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5279 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5280 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5282 device_printf(dev, "Unable to fetch CPU list\n");
5283 /* Figure out a reasonable auto config value */
5284 queues = min(queuemsgs, mp_ncpus);
5287 /* If we're doing RSS, clamp at the number of RSS buckets */
5288 if (queues > rss_getnumbuckets())
5289 queues = rss_getnumbuckets();
5291 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5292 rx_queues = iflib_num_rx_queues;
5296 * We want this to be all logical CPUs by default
5298 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5299 tx_queues = iflib_num_tx_queues;
5301 tx_queues = mp_ncpus;
5303 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5305 if (tx_queues != rx_queues)
5306 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5307 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5309 tx_queues = min(rx_queues, tx_queues);
5310 rx_queues = min(rx_queues, tx_queues);
5313 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5315 vectors = rx_queues + admincnt;
5316 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5318 "Using MSIX interrupts with %d vectors\n", vectors);
5319 scctx->isc_vectors = vectors;
5320 scctx->isc_nrxqsets = rx_queues;
5321 scctx->isc_ntxqsets = tx_queues;
5322 scctx->isc_intr = IFLIB_INTR_MSIX;
5326 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5329 vectors = pci_msi_count(dev);
5330 scctx->isc_nrxqsets = 1;
5331 scctx->isc_ntxqsets = 1;
5332 scctx->isc_vectors = vectors;
5333 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5334 device_printf(dev,"Using an MSI interrupt\n");
5335 scctx->isc_intr = IFLIB_INTR_MSI;
5337 device_printf(dev,"Using a Legacy interrupt\n");
5338 scctx->isc_intr = IFLIB_INTR_LEGACY;
5344 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5347 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5350 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5352 char *ring_state = "UNKNOWN";
5355 rc = sysctl_wire_old_buffer(req, 0);
5359 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5364 ring_state = ring_states[state[3]];
5366 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5367 state[0], state[1], state[2], ring_state);
5368 rc = sbuf_finish(sb);
5373 enum iflib_ndesc_handler {
5379 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5381 if_ctx_t ctx = (void *)arg1;
5382 enum iflib_ndesc_handler type = arg2;
5383 char buf[256] = {0};
5388 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5392 case IFLIB_NTXD_HANDLER:
5393 ndesc = ctx->ifc_sysctl_ntxds;
5395 nqs = ctx->ifc_sctx->isc_ntxqs;
5397 case IFLIB_NRXD_HANDLER:
5398 ndesc = ctx->ifc_sysctl_nrxds;
5400 nqs = ctx->ifc_sctx->isc_nrxqs;
5406 for (i=0; i<8; i++) {
5411 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5414 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5415 if (rc || req->newptr == NULL)
5418 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5419 i++, p = strsep(&next, " ,")) {
5420 ndesc[i] = strtoul(p, NULL, 10);
5426 #define NAME_BUFLEN 32
5428 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5430 device_t dev = iflib_get_dev(ctx);
5431 struct sysctl_oid_list *child, *oid_list;
5432 struct sysctl_ctx_list *ctx_list;
5433 struct sysctl_oid *node;
5435 ctx_list = device_get_sysctl_ctx(dev);
5436 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5437 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5438 CTLFLAG_RD, NULL, "IFLIB fields");
5439 oid_list = SYSCTL_CHILDREN(node);
5441 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5442 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5445 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5446 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5447 "# of txqs to use, 0 => use default #");
5448 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5449 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5450 "# of rxqs to use, 0 => use default #");
5451 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5452 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5453 "permit #txq != #rxq");
5454 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5455 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5456 "disable MSIX (default 0)");
5458 /* XXX change for per-queue sizes */
5459 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5460 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5461 mp_ndesc_handler, "A",
5462 "list of # of tx descriptors to use, 0 = use default #");
5463 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5464 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5465 mp_ndesc_handler, "A",
5466 "list of # of rx descriptors to use, 0 = use default #");
5470 iflib_add_device_sysctl_post(if_ctx_t ctx)
5472 if_shared_ctx_t sctx = ctx->ifc_sctx;
5473 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5474 device_t dev = iflib_get_dev(ctx);
5475 struct sysctl_oid_list *child;
5476 struct sysctl_ctx_list *ctx_list;
5481 char namebuf[NAME_BUFLEN];
5483 struct sysctl_oid *queue_node, *fl_node, *node;
5484 struct sysctl_oid_list *queue_list, *fl_list;
5485 ctx_list = device_get_sysctl_ctx(dev);
5487 node = ctx->ifc_sysctl_node;
5488 child = SYSCTL_CHILDREN(node);
5490 if (scctx->isc_ntxqsets > 100)
5492 else if (scctx->isc_ntxqsets > 10)
5496 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5497 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5498 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5499 CTLFLAG_RD, NULL, "Queue Name");
5500 queue_list = SYSCTL_CHILDREN(queue_node);
5502 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5504 &txq->ift_dequeued, "total mbufs freed");
5505 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5507 &txq->ift_enqueued, "total mbufs enqueued");
5509 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5511 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5512 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5514 &txq->ift_pullups, "# of times m_pullup was called");
5515 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5517 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5518 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5520 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5521 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5523 &txq->ift_map_failed, "# of times dma map failed");
5524 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5526 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5527 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5529 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5530 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5532 &txq->ift_pidx, 1, "Producer Index");
5533 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5535 &txq->ift_cidx, 1, "Consumer Index");
5536 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5538 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5539 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5541 &txq->ift_in_use, 1, "descriptors in use");
5542 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5544 &txq->ift_processed, "descriptors procesed for clean");
5545 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5547 &txq->ift_cleaned, "total cleaned");
5548 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5549 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5550 0, mp_ring_state_handler, "A", "soft ring state");
5551 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5552 CTLFLAG_RD, &txq->ift_br->enqueues,
5553 "# of enqueues to the mp_ring for this queue");
5554 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5555 CTLFLAG_RD, &txq->ift_br->drops,
5556 "# of drops in the mp_ring for this queue");
5557 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5558 CTLFLAG_RD, &txq->ift_br->starts,
5559 "# of normal consumer starts in the mp_ring for this queue");
5560 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5561 CTLFLAG_RD, &txq->ift_br->stalls,
5562 "# of consumer stalls in the mp_ring for this queue");
5563 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5564 CTLFLAG_RD, &txq->ift_br->restarts,
5565 "# of consumer restarts in the mp_ring for this queue");
5566 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5567 CTLFLAG_RD, &txq->ift_br->abdications,
5568 "# of consumer abdications in the mp_ring for this queue");
5571 if (scctx->isc_nrxqsets > 100)
5573 else if (scctx->isc_nrxqsets > 10)
5577 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5578 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5579 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5580 CTLFLAG_RD, NULL, "Queue Name");
5581 queue_list = SYSCTL_CHILDREN(queue_node);
5582 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5583 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5585 &rxq->ifr_cq_pidx, 1, "Producer Index");
5586 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5588 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5591 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5592 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5593 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5594 CTLFLAG_RD, NULL, "freelist Name");
5595 fl_list = SYSCTL_CHILDREN(fl_node);
5596 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5598 &fl->ifl_pidx, 1, "Producer Index");
5599 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5601 &fl->ifl_cidx, 1, "Consumer Index");
5602 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5604 &fl->ifl_credits, 1, "credits available");
5606 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5608 &fl->ifl_m_enqueued, "mbufs allocated");
5609 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5611 &fl->ifl_m_dequeued, "mbufs freed");
5612 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5614 &fl->ifl_cl_enqueued, "clusters allocated");
5615 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5617 &fl->ifl_cl_dequeued, "clusters freed");
5625 #ifndef __NO_STRICT_ALIGNMENT
5626 static struct mbuf *
5627 iflib_fixup_rx(struct mbuf *m)
5631 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5632 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5633 m->m_data += ETHER_HDR_LEN;
5636 MGETHDR(n, M_NOWAIT, MT_DATA);
5641 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
5642 m->m_data += ETHER_HDR_LEN;
5643 m->m_len -= ETHER_HDR_LEN;
5644 n->m_len = ETHER_HDR_LEN;
5645 M_MOVE_PKTHDR(n, m);