2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
95 #if defined(__i386__) || defined(__amd64__)
96 #include <sys/memdesc.h>
97 #include <machine/bus.h>
98 #include <machine/md_var.h>
99 #include <machine/specialreg.h>
100 #include <x86/include/busdma_impl.h>
101 #include <x86/iommu/busdma_dmar.h>
104 #include <sys/bitstring.h>
106 * enable accounting of every mbuf as it comes in to and goes out of
107 * iflib's software descriptor references
109 #define MEMORY_LOGGING 0
111 * Enable mbuf vectors for compressing long mbuf chains
116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
117 * we prefetch needs to be determined by the time spent in m_free vis a vis
118 * the cost of a prefetch. This will of course vary based on the workload:
119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
120 * is quite expensive, thus suggesting very little prefetch.
121 * - small packet forwarding which is just returning a single mbuf to
122 * UMA will typically be very fast vis a vis the cost of a memory
129 * - private structures
130 * - iflib private utility functions
132 * - vlan registry and other exported functions
133 * - iflib public core functions
137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
140 typedef struct iflib_txq *iflib_txq_t;
142 typedef struct iflib_rxq *iflib_rxq_t;
144 typedef struct iflib_fl *iflib_fl_t;
148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
149 static void iflib_timer(void *arg);
151 typedef struct iflib_filter_info {
152 driver_filter_t *ifi_filter;
153 void *ifi_filter_arg;
154 struct grouptask *ifi_task;
156 } *iflib_filter_info_t;
161 * Pointer to hardware driver's softc
168 if_shared_ctx_t ifc_sctx;
169 struct if_softc_ctx ifc_softc_ctx;
171 struct sx ifc_ctx_sx;
172 struct mtx ifc_state_mtx;
174 uint16_t ifc_nhwtxqs;
176 iflib_txq_t ifc_txqs;
177 iflib_rxq_t ifc_rxqs;
178 uint32_t ifc_if_flags;
180 uint32_t ifc_max_fl_buf_size;
185 int ifc_watchdog_events;
186 struct cdev *ifc_led_dev;
187 struct resource *ifc_msix_mem;
189 struct if_irq ifc_legacy_irq;
190 struct grouptask ifc_admin_task;
191 struct grouptask ifc_vflr_task;
192 struct iflib_filter_info ifc_filter_info;
193 struct ifmedia ifc_media;
195 struct sysctl_oid *ifc_sysctl_node;
196 uint16_t ifc_sysctl_ntxqs;
197 uint16_t ifc_sysctl_nrxqs;
198 uint16_t ifc_sysctl_qs_eq_override;
199 uint16_t ifc_sysctl_rx_budget;
200 uint16_t ifc_sysctl_tx_abdicate;
202 qidx_t ifc_sysctl_ntxds[8];
203 qidx_t ifc_sysctl_nrxds[8];
204 struct if_txrx ifc_txrx;
205 #define isc_txd_encap ifc_txrx.ift_txd_encap
206 #define isc_txd_flush ifc_txrx.ift_txd_flush
207 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
208 #define isc_rxd_available ifc_txrx.ift_rxd_available
209 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
212 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
213 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
214 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
215 eventhandler_tag ifc_vlan_attach_event;
216 eventhandler_tag ifc_vlan_detach_event;
217 uint8_t ifc_mac[ETHER_ADDR_LEN];
218 char ifc_mtx_name[16];
223 iflib_get_softc(if_ctx_t ctx)
226 return (ctx->ifc_softc);
230 iflib_get_dev(if_ctx_t ctx)
233 return (ctx->ifc_dev);
237 iflib_get_ifp(if_ctx_t ctx)
240 return (ctx->ifc_ifp);
244 iflib_get_media(if_ctx_t ctx)
247 return (&ctx->ifc_media);
251 iflib_get_flags(if_ctx_t ctx)
253 return (ctx->ifc_flags);
257 iflib_set_detach(if_ctx_t ctx)
259 ctx->ifc_in_detach = 1;
263 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
266 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
270 iflib_get_softc_ctx(if_ctx_t ctx)
273 return (&ctx->ifc_softc_ctx);
277 iflib_get_sctx(if_ctx_t ctx)
280 return (ctx->ifc_sctx);
283 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
284 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
285 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
287 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
288 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
290 #define RX_SW_DESC_MAP_CREATED (1 << 0)
291 #define TX_SW_DESC_MAP_CREATED (1 << 1)
292 #define RX_SW_DESC_INUSE (1 << 3)
293 #define TX_SW_DESC_MAPPED (1 << 4)
295 #define M_TOOBIG M_PROTO1
297 typedef struct iflib_sw_rx_desc_array {
298 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
299 struct mbuf **ifsd_m; /* pkthdr mbufs */
300 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
302 } iflib_rxsd_array_t;
304 typedef struct iflib_sw_tx_desc_array {
305 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
306 struct mbuf **ifsd_m; /* pkthdr mbufs */
311 /* magic number that should be high enough for any hardware */
312 #define IFLIB_MAX_TX_SEGS 128
313 /* bnxt supports 64 with hardware LRO enabled */
314 #define IFLIB_MAX_RX_SEGS 64
315 #define IFLIB_RX_COPY_THRESH 128
316 #define IFLIB_MAX_RX_REFRESH 32
317 /* The minimum descriptors per second before we start coalescing */
318 #define IFLIB_MIN_DESC_SEC 16384
319 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
320 #define IFLIB_QUEUE_IDLE 0
321 #define IFLIB_QUEUE_HUNG 1
322 #define IFLIB_QUEUE_WORKING 2
323 /* maximum number of txqs that can share an rx interrupt */
324 #define IFLIB_MAX_TX_SHARED_INTR 4
326 /* this should really scale with ring size - this is a fairly arbitrary value */
327 #define TX_BATCH_SIZE 32
329 #define IFLIB_RESTART_BUDGET 8
332 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
333 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
334 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
338 qidx_t ift_cidx_processed;
341 uint8_t ift_br_offset;
342 uint16_t ift_npending;
343 uint16_t ift_db_pending;
344 uint16_t ift_rs_pending;
346 uint8_t ift_txd_size[8];
347 uint64_t ift_processed;
348 uint64_t ift_cleaned;
349 uint64_t ift_cleaned_prev;
351 uint64_t ift_enqueued;
352 uint64_t ift_dequeued;
354 uint64_t ift_no_tx_dma_setup;
355 uint64_t ift_no_desc_avail;
356 uint64_t ift_mbuf_defrag_failed;
357 uint64_t ift_mbuf_defrag;
358 uint64_t ift_map_failed;
359 uint64_t ift_txd_encap_efbig;
360 uint64_t ift_pullups;
361 uint64_t ift_last_timer_tick;
364 struct mtx ift_db_mtx;
366 /* constant values */
368 struct ifmp_ring *ift_br;
369 struct grouptask ift_task;
372 struct callout ift_timer;
374 if_txsd_vec_t ift_sds;
377 uint8_t ift_update_freq;
378 struct iflib_filter_info ift_filter_info;
379 bus_dma_tag_t ift_desc_tag;
380 bus_dma_tag_t ift_tso_desc_tag;
381 iflib_dma_info_t ift_ifdi;
382 #define MTX_NAME_LEN 16
383 char ift_mtx_name[MTX_NAME_LEN];
384 char ift_db_mtx_name[MTX_NAME_LEN];
385 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
386 #ifdef IFLIB_DIAGNOSTICS
387 uint64_t ift_cpu_exec_count[256];
389 } __aligned(CACHE_LINE_SIZE);
396 uint8_t ifl_rxd_size;
398 uint64_t ifl_m_enqueued;
399 uint64_t ifl_m_dequeued;
400 uint64_t ifl_cl_enqueued;
401 uint64_t ifl_cl_dequeued;
405 bitstr_t *ifl_rx_bitmap;
409 uint16_t ifl_buf_size;
412 iflib_rxsd_array_t ifl_sds;
415 bus_dma_tag_t ifl_desc_tag;
416 iflib_dma_info_t ifl_ifdi;
417 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
418 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
419 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
420 } __aligned(CACHE_LINE_SIZE);
423 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
429 else if (pidx < cidx)
430 used = size - cidx + pidx;
431 else if (gen == 0 && pidx == cidx)
433 else if (gen == 1 && pidx == cidx)
441 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
443 #define IDXDIFF(head, tail, wrap) \
444 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
447 /* If there is a separate completion queue -
448 * these are the cq cidx and pidx. Otherwise
455 uint8_t ifr_fl_offset;
461 uint8_t ifr_lro_enabled;
464 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
465 struct lro_ctrl ifr_lc;
466 struct grouptask ifr_task;
467 struct iflib_filter_info ifr_filter_info;
468 iflib_dma_info_t ifr_ifdi;
470 /* dynamically allocate if any drivers need a value substantially larger than this */
471 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
472 #ifdef IFLIB_DIAGNOSTICS
473 uint64_t ifr_cpu_exec_count[256];
475 } __aligned(CACHE_LINE_SIZE);
477 typedef struct if_rxsd {
479 struct mbuf **ifsd_m;
484 /* multiple of word size */
486 #define PKT_INFO_SIZE 6
487 #define RXD_INFO_SIZE 5
488 #define PKT_TYPE uint64_t
490 #define PKT_INFO_SIZE 11
491 #define RXD_INFO_SIZE 8
492 #define PKT_TYPE uint32_t
494 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
495 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
497 typedef struct if_pkt_info_pad {
498 PKT_TYPE pkt_val[PKT_INFO_SIZE];
499 } *if_pkt_info_pad_t;
500 typedef struct if_rxd_info_pad {
501 PKT_TYPE rxd_val[RXD_INFO_SIZE];
502 } *if_rxd_info_pad_t;
504 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
505 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
509 pkt_info_zero(if_pkt_info_t pi)
511 if_pkt_info_pad_t pi_pad;
513 pi_pad = (if_pkt_info_pad_t)pi;
514 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
515 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
517 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
518 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
522 static device_method_t iflib_pseudo_methods[] = {
523 DEVMETHOD(device_attach, noop_attach),
524 DEVMETHOD(device_detach, iflib_pseudo_detach),
528 driver_t iflib_pseudodriver = {
529 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
533 rxd_info_zero(if_rxd_info_t ri)
535 if_rxd_info_pad_t ri_pad;
538 ri_pad = (if_rxd_info_pad_t)ri;
539 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
540 ri_pad->rxd_val[i] = 0;
541 ri_pad->rxd_val[i+1] = 0;
542 ri_pad->rxd_val[i+2] = 0;
543 ri_pad->rxd_val[i+3] = 0;
546 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
551 * Only allow a single packet to take up most 1/nth of the tx ring
553 #define MAX_SINGLE_PACKET_FRACTION 12
554 #define IF_BAD_DMA (bus_addr_t)-1
556 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
558 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
559 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
560 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
561 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
564 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
565 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
566 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
567 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
571 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
572 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
575 /* Our boot-time initialization hook */
576 static int iflib_module_event_handler(module_t, int, void *);
578 static moduledata_t iflib_moduledata = {
580 iflib_module_event_handler,
584 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
585 MODULE_VERSION(iflib, 1);
587 MODULE_DEPEND(iflib, pci, 1, 1, 1);
588 MODULE_DEPEND(iflib, ether, 1, 1, 1);
590 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
591 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
593 #ifndef IFLIB_DEBUG_COUNTERS
595 #define IFLIB_DEBUG_COUNTERS 1
597 #define IFLIB_DEBUG_COUNTERS 0
598 #endif /* !INVARIANTS */
601 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
602 "iflib driver parameters");
605 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
607 static int iflib_min_tx_latency = 0;
608 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
609 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
610 static int iflib_no_tx_batch = 0;
611 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
612 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
615 #if IFLIB_DEBUG_COUNTERS
617 static int iflib_tx_seen;
618 static int iflib_tx_sent;
619 static int iflib_tx_encap;
620 static int iflib_rx_allocs;
621 static int iflib_fl_refills;
622 static int iflib_fl_refills_large;
623 static int iflib_tx_frees;
625 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
626 &iflib_tx_seen, 0, "# tx mbufs seen");
627 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
628 &iflib_tx_sent, 0, "# tx mbufs sent");
629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
630 &iflib_tx_encap, 0, "# tx mbufs encapped");
631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
632 &iflib_tx_frees, 0, "# tx frees");
633 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
634 &iflib_rx_allocs, 0, "# rx allocations");
635 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
636 &iflib_fl_refills, 0, "# refills");
637 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
638 &iflib_fl_refills_large, 0, "# large refills");
641 static int iflib_txq_drain_flushing;
642 static int iflib_txq_drain_oactive;
643 static int iflib_txq_drain_notready;
644 static int iflib_txq_drain_encapfail;
646 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
647 &iflib_txq_drain_flushing, 0, "# drain flushes");
648 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
649 &iflib_txq_drain_oactive, 0, "# drain oactives");
650 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
651 &iflib_txq_drain_notready, 0, "# drain notready");
652 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
653 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
656 static int iflib_encap_load_mbuf_fail;
657 static int iflib_encap_pad_mbuf_fail;
658 static int iflib_encap_txq_avail_fail;
659 static int iflib_encap_txd_encap_fail;
661 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
662 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
663 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
664 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
665 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
666 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
667 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
668 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
670 static int iflib_task_fn_rxs;
671 static int iflib_rx_intr_enables;
672 static int iflib_fast_intrs;
673 static int iflib_intr_link;
674 static int iflib_intr_msix;
675 static int iflib_rx_unavail;
676 static int iflib_rx_ctx_inactive;
677 static int iflib_rx_zero_len;
678 static int iflib_rx_if_input;
679 static int iflib_rx_mbuf_null;
680 static int iflib_rxd_flush;
682 static int iflib_verbose_debug;
684 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
685 &iflib_intr_link, 0, "# intr link calls");
686 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
687 &iflib_intr_msix, 0, "# intr msix calls");
688 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
689 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
691 &iflib_rx_intr_enables, 0, "# rx intr enables");
692 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
693 &iflib_fast_intrs, 0, "# fast_intr calls");
694 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
695 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
696 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
697 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
698 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
699 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
700 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
701 &iflib_rx_if_input, 0, "# times rxeof called if_input");
702 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
703 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
704 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
705 &iflib_rxd_flush, 0, "# times rxd_flush called");
706 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
707 &iflib_verbose_debug, 0, "enable verbose debugging");
709 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
711 iflib_debug_reset(void)
713 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
714 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
715 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
716 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
717 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
718 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
719 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
720 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
721 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
722 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
726 #define DBG_COUNTER_INC(name)
727 static void iflib_debug_reset(void) {}
730 #define IFLIB_DEBUG 0
732 static void iflib_tx_structures_free(if_ctx_t ctx);
733 static void iflib_rx_structures_free(if_ctx_t ctx);
734 static int iflib_queues_alloc(if_ctx_t ctx);
735 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
736 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
737 static int iflib_qset_structures_setup(if_ctx_t ctx);
738 static int iflib_msix_init(if_ctx_t ctx);
739 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
740 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
741 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
743 static void iflib_altq_if_start(if_t ifp);
744 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
746 static int iflib_register(if_ctx_t);
747 static void iflib_init_locked(if_ctx_t ctx);
748 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
749 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
750 static void iflib_ifmp_purge(iflib_txq_t txq);
751 static void _iflib_pre_assert(if_softc_ctx_t scctx);
752 static void iflib_if_init_locked(if_ctx_t ctx);
753 #ifndef __NO_STRICT_ALIGNMENT
754 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
757 NETDUMP_DEFINE(iflib);
760 #include <sys/selinfo.h>
761 #include <net/netmap.h>
762 #include <dev/netmap/netmap_kern.h>
764 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
766 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
769 * device-specific sysctl variables:
771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
772 * During regular operations the CRC is stripped, but on some
773 * hardware reception of frames not multiple of 64 is slower,
774 * so using crcstrip=0 helps in benchmarks.
776 * iflib_rx_miss, iflib_rx_miss_bufs:
777 * count packets that might be missed due to lost interrupts.
779 SYSCTL_DECL(_dev_netmap);
781 * The xl driver by default strips CRCs and we do not override it.
784 int iflib_crcstrip = 1;
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
788 int iflib_rx_miss, iflib_rx_miss_bufs;
789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
795 * Register/unregister. We are already under netmap lock.
796 * Only called on the first register or the last unregister.
799 iflib_netmap_register(struct netmap_adapter *na, int onoff)
801 struct ifnet *ifp = na->ifp;
802 if_ctx_t ctx = ifp->if_softc;
806 IFDI_INTR_DISABLE(ctx);
808 /* Tell the stack that the interface is no longer active */
809 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
812 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
814 /* enable or disable flags and callbacks in na and ifp */
816 nm_set_native_flags(na);
818 nm_clear_native_flags(na);
821 iflib_init_locked(ctx);
822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
825 nm_clear_native_flags(na);
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
833 struct netmap_adapter *na = kring->na;
834 u_int const lim = kring->nkr_num_slots - 1;
835 u_int head = kring->rhead;
836 struct netmap_ring *ring = kring->ring;
838 struct if_rxd_update iru;
839 if_ctx_t ctx = rxq->ifr_ctx;
840 iflib_fl_t fl = &rxq->ifr_fl[0];
841 uint32_t refill_pidx, nic_i;
843 if (nm_i == head && __predict_true(!init))
845 iru_init(&iru, rxq, 0 /* flid */);
846 map = fl->ifl_sds.ifsd_map;
847 refill_pidx = netmap_idx_k2n(kring, nm_i);
849 * IMPORTANT: we must leave one free slot in the ring,
850 * so move head back by one unit
852 head = nm_prev(head, lim);
854 while (nm_i != head) {
855 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
856 struct netmap_slot *slot = &ring->slot[nm_i];
857 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
858 uint32_t nic_i_dma = refill_pidx;
859 nic_i = netmap_idx_k2n(kring, nm_i);
861 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
863 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
864 return netmap_ring_reinit(kring);
866 fl->ifl_vm_addrs[tmp_pidx] = addr;
867 if (__predict_false(init) && map) {
868 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
869 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
870 /* buffer has changed, reload map */
871 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
873 slot->flags &= ~NS_BUF_CHANGED;
875 nm_i = nm_next(nm_i, lim);
876 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
877 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
880 iru.iru_pidx = refill_pidx;
881 iru.iru_count = tmp_pidx+1;
882 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
888 for (int n = 0; n < iru.iru_count; n++) {
889 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
890 BUS_DMASYNC_PREREAD);
891 /* XXX - change this to not use the netmap func*/
892 nic_i_dma = nm_next(nic_i_dma, lim);
896 kring->nr_hwcur = head;
899 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
900 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
901 if (__predict_true(nic_i != UINT_MAX))
902 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
907 * Reconcile kernel and user view of the transmit ring.
909 * All information is in the kring.
910 * Userspace wants to send packets up to the one before kring->rhead,
911 * kernel knows kring->nr_hwcur is the first unsent packet.
913 * Here we push packets out (as many as possible), and possibly
914 * reclaim buffers from previously completed transmission.
916 * The caller (netmap) guarantees that there is only one instance
917 * running at any time. Any interference with other driver
918 * methods should be handled by the individual drivers.
921 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
923 struct netmap_adapter *na = kring->na;
924 struct ifnet *ifp = na->ifp;
925 struct netmap_ring *ring = kring->ring;
926 u_int nm_i; /* index into the netmap kring */
927 u_int nic_i; /* index into the NIC ring */
929 u_int const lim = kring->nkr_num_slots - 1;
930 u_int const head = kring->rhead;
931 struct if_pkt_info pi;
934 * interrupts on every tx packet are expensive so request
935 * them every half ring, or where NS_REPORT is set
937 u_int report_frequency = kring->nkr_num_slots >> 1;
938 /* device-specific */
939 if_ctx_t ctx = ifp->if_softc;
940 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
942 if (txq->ift_sds.ifsd_map)
943 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
944 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
948 * First part: process new packets to send.
949 * nm_i is the current index in the netmap kring,
950 * nic_i is the corresponding index in the NIC ring.
952 * If we have packets to send (nm_i != head)
953 * iterate over the netmap ring, fetch length and update
954 * the corresponding slot in the NIC ring. Some drivers also
955 * need to update the buffer's physical address in the NIC slot
956 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
958 * The netmap_reload_map() calls is especially expensive,
959 * even when (as in this case) the tag is 0, so do only
960 * when the buffer has actually changed.
962 * If possible do not set the report/intr bit on all slots,
963 * but only a few times per ring or when NS_REPORT is set.
965 * Finally, on 10G and faster drivers, it might be useful
966 * to prefetch the next slot and txr entry.
969 nm_i = kring->nr_hwcur;
970 if (nm_i != head) { /* we have new packets to send */
972 pi.ipi_segs = txq->ift_segs;
973 pi.ipi_qsidx = kring->ring_id;
974 nic_i = netmap_idx_k2n(kring, nm_i);
976 __builtin_prefetch(&ring->slot[nm_i]);
977 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
978 if (txq->ift_sds.ifsd_map)
979 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
981 for (n = 0; nm_i != head; n++) {
982 struct netmap_slot *slot = &ring->slot[nm_i];
983 u_int len = slot->len;
985 void *addr = PNMB(na, slot, &paddr);
986 int flags = (slot->flags & NS_REPORT ||
987 nic_i == 0 || nic_i == report_frequency) ?
990 /* device-specific */
992 pi.ipi_segs[0].ds_addr = paddr;
993 pi.ipi_segs[0].ds_len = len;
997 pi.ipi_flags = flags;
999 /* Fill the slot in the NIC ring. */
1000 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1002 /* prefetch for next round */
1003 __builtin_prefetch(&ring->slot[nm_i + 1]);
1004 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1005 if (txq->ift_sds.ifsd_map) {
1006 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1008 NM_CHECK_ADDR_LEN(na, addr, len);
1010 if (slot->flags & NS_BUF_CHANGED) {
1011 /* buffer has changed, reload map */
1012 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
1014 /* make sure changes to the buffer are synced */
1015 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1016 BUS_DMASYNC_PREWRITE);
1018 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1019 nm_i = nm_next(nm_i, lim);
1020 nic_i = nm_next(nic_i, lim);
1022 kring->nr_hwcur = nm_i;
1024 /* synchronize the NIC ring */
1025 if (txq->ift_sds.ifsd_map)
1026 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1027 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1029 /* (re)start the tx unit up to slot nic_i (excluded) */
1030 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1034 * Second part: reclaim buffers for completed transmissions.
1036 * If there are unclaimed buffers, attempt to reclaim them.
1037 * If none are reclaimed, and TX IRQs are not in use, do an initial
1038 * minimal delay, then trigger the tx handler which will spin in the
1041 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1042 if (iflib_tx_credits_update(ctx, txq)) {
1043 /* some tx completed, increment avail */
1044 nic_i = txq->ift_cidx_processed;
1045 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1048 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1049 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1050 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1051 iflib_timer, txq, txq->ift_timer.c_cpu);
1057 * Reconcile kernel and user view of the receive ring.
1058 * Same as for the txsync, this routine must be efficient.
1059 * The caller guarantees a single invocations, but races against
1060 * the rest of the driver should be handled here.
1062 * On call, kring->rhead is the first packet that userspace wants
1063 * to keep, and kring->rcur is the wakeup point.
1064 * The kernel has previously reported packets up to kring->rtail.
1066 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1067 * of whether or not we received an interrupt.
1070 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1072 struct netmap_adapter *na = kring->na;
1073 struct netmap_ring *ring = kring->ring;
1074 uint32_t nm_i; /* index into the netmap ring */
1075 uint32_t nic_i; /* index into the NIC ring */
1077 u_int const lim = kring->nkr_num_slots - 1;
1078 u_int const head = kring->rhead;
1079 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1080 struct if_rxd_info ri;
1082 struct ifnet *ifp = na->ifp;
1083 if_ctx_t ctx = ifp->if_softc;
1084 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1085 iflib_fl_t fl = rxq->ifr_fl;
1087 return netmap_ring_reinit(kring);
1089 /* XXX check sync modes */
1090 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1091 if (fl->ifl_sds.ifsd_map == NULL)
1093 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1094 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1097 * First part: import newly received packets.
1099 * nm_i is the index of the next free slot in the netmap ring,
1100 * nic_i is the index of the next received packet in the NIC ring,
1101 * and they may differ in case if_init() has been called while
1102 * in netmap mode. For the receive ring we have
1104 * nic_i = rxr->next_check;
1105 * nm_i = kring->nr_hwtail (previous)
1107 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1109 * rxr->next_check is set to 0 on a ring reinit
1111 if (netmap_no_pendintr || force_update) {
1112 int crclen = iflib_crcstrip ? 0 : 4;
1115 for (i = 0; i < rxq->ifr_nfl; i++) {
1116 fl = &rxq->ifr_fl[i];
1117 nic_i = fl->ifl_cidx;
1118 nm_i = netmap_idx_n2k(kring, nic_i);
1119 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1120 for (n = 0; avail > 0; n++, avail--) {
1122 ri.iri_frags = rxq->ifr_frags;
1123 ri.iri_qsidx = kring->ring_id;
1124 ri.iri_ifp = ctx->ifc_ifp;
1125 ri.iri_cidx = nic_i;
1127 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1128 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1129 ring->slot[nm_i].flags = 0;
1130 if (fl->ifl_sds.ifsd_map)
1131 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1132 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1133 nm_i = nm_next(nm_i, lim);
1134 nic_i = nm_next(nic_i, lim);
1136 if (n) { /* update the state variables */
1137 if (netmap_no_pendintr && !force_update) {
1140 iflib_rx_miss_bufs += n;
1142 fl->ifl_cidx = nic_i;
1143 kring->nr_hwtail = nm_i;
1145 kring->nr_kflags &= ~NKR_PENDINTR;
1149 * Second part: skip past packets that userspace has released.
1150 * (kring->nr_hwcur to head excluded),
1151 * and make the buffers available for reception.
1152 * As usual nm_i is the index in the netmap ring,
1153 * nic_i is the index in the NIC ring, and
1154 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1156 /* XXX not sure how this will work with multiple free lists */
1157 nm_i = kring->nr_hwcur;
1159 return (netmap_fl_refill(rxq, kring, nm_i, false));
1163 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1165 struct ifnet *ifp = na->ifp;
1166 if_ctx_t ctx = ifp->if_softc;
1170 IFDI_INTR_ENABLE(ctx);
1172 IFDI_INTR_DISABLE(ctx);
1179 iflib_netmap_attach(if_ctx_t ctx)
1181 struct netmap_adapter na;
1182 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1184 bzero(&na, sizeof(na));
1186 na.ifp = ctx->ifc_ifp;
1187 na.na_flags = NAF_BDG_MAYSLEEP;
1188 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1189 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1191 na.num_tx_desc = scctx->isc_ntxd[0];
1192 na.num_rx_desc = scctx->isc_nrxd[0];
1193 na.nm_txsync = iflib_netmap_txsync;
1194 na.nm_rxsync = iflib_netmap_rxsync;
1195 na.nm_register = iflib_netmap_register;
1196 na.nm_intr = iflib_netmap_intr;
1197 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1198 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1199 return (netmap_attach(&na));
1203 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1205 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1206 struct netmap_slot *slot;
1208 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1211 if (txq->ift_sds.ifsd_map == NULL)
1214 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1217 * In netmap mode, set the map for the packet buffer.
1218 * NOTE: Some drivers (not this one) also need to set
1219 * the physical buffer address in the NIC ring.
1220 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1221 * netmap slot index, si
1223 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1224 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1229 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1231 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1232 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1233 struct netmap_slot *slot;
1236 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1239 nm_i = netmap_idx_n2k(kring, 0);
1240 netmap_fl_refill(rxq, kring, nm_i, true);
1244 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1246 struct netmap_kring *kring;
1248 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1250 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1251 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1252 netmap_tx_irq(ctx->ifc_ifp, txqid);
1253 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1257 *reset_on = hz / 1000;
1262 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1265 #define iflib_netmap_txq_init(ctx, txq)
1266 #define iflib_netmap_rxq_init(ctx, rxq)
1267 #define iflib_netmap_detach(ifp)
1269 #define iflib_netmap_attach(ctx) (0)
1270 #define netmap_rx_irq(ifp, qid, budget) (0)
1271 #define netmap_tx_irq(ifp, qid) do {} while (0)
1272 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1276 #if defined(__i386__) || defined(__amd64__)
1277 static __inline void
1280 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1282 static __inline void
1283 prefetch2cachelines(void *x)
1285 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1286 #if (CACHE_LINE_SIZE < 128)
1287 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1292 #define prefetch2cachelines(x)
1296 iflib_gen_mac(if_ctx_t ctx)
1300 char uuid[HOSTUUIDLEN+1];
1301 char buf[HOSTUUIDLEN+16];
1303 unsigned char digest[16];
1307 uuid[HOSTUUIDLEN] = 0;
1308 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1309 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1311 * Generate a pseudo-random, deterministic MAC
1312 * address based on the UUID and unit number.
1313 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1316 MD5Update(&mdctx, buf, strlen(buf));
1317 MD5Final(digest, &mdctx);
1328 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1332 fl = &rxq->ifr_fl[flid];
1333 iru->iru_paddrs = fl->ifl_bus_addrs;
1334 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1335 iru->iru_idxs = fl->ifl_rxd_idxs;
1336 iru->iru_qsidx = rxq->ifr_id;
1337 iru->iru_buf_size = fl->ifl_buf_size;
1338 iru->iru_flidx = fl->ifl_id;
1342 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1346 *(bus_addr_t *) arg = segs[0].ds_addr;
1350 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1353 if_shared_ctx_t sctx = ctx->ifc_sctx;
1354 device_t dev = ctx->ifc_dev;
1356 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1358 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1359 sctx->isc_q_align, 0, /* alignment, bounds */
1360 BUS_SPACE_MAXADDR, /* lowaddr */
1361 BUS_SPACE_MAXADDR, /* highaddr */
1362 NULL, NULL, /* filter, filterarg */
1365 size, /* maxsegsize */
1366 BUS_DMA_ALLOCNOW, /* flags */
1367 NULL, /* lockfunc */
1372 "%s: bus_dma_tag_create failed: %d\n",
1377 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1378 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1381 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1382 __func__, (uintmax_t)size, err);
1386 dma->idi_paddr = IF_BAD_DMA;
1387 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1388 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1389 if (err || dma->idi_paddr == IF_BAD_DMA) {
1391 "%s: bus_dmamap_load failed: %d\n",
1396 dma->idi_size = size;
1400 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1402 bus_dma_tag_destroy(dma->idi_tag);
1404 dma->idi_tag = NULL;
1410 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1413 iflib_dma_info_t *dmaiter;
1416 for (i = 0; i < count; i++, dmaiter++) {
1417 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1421 iflib_dma_free_multi(dmalist, i);
1426 iflib_dma_free(iflib_dma_info_t dma)
1428 if (dma->idi_tag == NULL)
1430 if (dma->idi_paddr != IF_BAD_DMA) {
1431 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1432 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1433 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1434 dma->idi_paddr = IF_BAD_DMA;
1436 if (dma->idi_vaddr != NULL) {
1437 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1438 dma->idi_vaddr = NULL;
1440 bus_dma_tag_destroy(dma->idi_tag);
1441 dma->idi_tag = NULL;
1445 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1448 iflib_dma_info_t *dmaiter = dmalist;
1450 for (i = 0; i < count; i++, dmaiter++)
1451 iflib_dma_free(*dmaiter);
1454 #ifdef EARLY_AP_STARTUP
1455 static const int iflib_started = 1;
1458 * We used to abuse the smp_started flag to decide if the queues have been
1459 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1460 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1461 * is set. Run a SYSINIT() strictly after that to just set a usable
1465 static int iflib_started;
1468 iflib_record_started(void *arg)
1473 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1474 iflib_record_started, NULL);
1478 iflib_fast_intr(void *arg)
1480 iflib_filter_info_t info = arg;
1481 struct grouptask *gtask = info->ifi_task;
1483 return (FILTER_HANDLED);
1485 DBG_COUNTER_INC(fast_intrs);
1486 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1487 return (FILTER_HANDLED);
1489 GROUPTASK_ENQUEUE(gtask);
1490 return (FILTER_HANDLED);
1494 iflib_fast_intr_rxtx(void *arg)
1496 iflib_filter_info_t info = arg;
1497 struct grouptask *gtask = info->ifi_task;
1498 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1499 if_ctx_t ctx = NULL;;
1503 return (FILTER_HANDLED);
1505 DBG_COUNTER_INC(fast_intrs);
1506 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1507 return (FILTER_HANDLED);
1509 MPASS(rxq->ifr_ntxqirq);
1510 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1511 qidx_t txqid = rxq->ifr_txqid[i];
1515 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1516 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1519 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1521 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1522 cidx = rxq->ifr_cq_cidx;
1524 cidx = rxq->ifr_fl[0].ifl_cidx;
1525 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1526 GROUPTASK_ENQUEUE(gtask);
1528 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1529 return (FILTER_HANDLED);
1534 iflib_fast_intr_ctx(void *arg)
1536 iflib_filter_info_t info = arg;
1537 struct grouptask *gtask = info->ifi_task;
1540 return (FILTER_HANDLED);
1542 DBG_COUNTER_INC(fast_intrs);
1543 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1544 return (FILTER_HANDLED);
1546 GROUPTASK_ENQUEUE(gtask);
1547 return (FILTER_HANDLED);
1551 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1552 driver_filter_t filter, driver_intr_t handler, void *arg,
1556 struct resource *res;
1558 device_t dev = ctx->ifc_dev;
1561 if (ctx->ifc_flags & IFC_LEGACY)
1562 flags |= RF_SHAREABLE;
1565 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1568 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1572 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1573 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1574 filter, handler, arg, &tag);
1577 "failed to setup interrupt for rid %d, name %s: %d\n",
1578 rid, name ? name : "unknown", rc);
1581 bus_describe_intr(dev, res, tag, "%s", name);
1588 /*********************************************************************
1590 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1591 * the information needed to transmit a packet on the wire. This is
1592 * called only once at attach, setup is done every reset.
1594 **********************************************************************/
1597 iflib_txsd_alloc(iflib_txq_t txq)
1599 if_ctx_t ctx = txq->ift_ctx;
1600 if_shared_ctx_t sctx = ctx->ifc_sctx;
1601 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1602 device_t dev = ctx->ifc_dev;
1603 bus_size_t tsomaxsize;
1604 int err, nsegments, ntsosegments;
1606 nsegments = scctx->isc_tx_nsegments;
1607 ntsosegments = scctx->isc_tx_tso_segments_max;
1608 tsomaxsize = scctx->isc_tx_tso_size_max;
1609 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1610 tsomaxsize += sizeof(struct ether_vlan_header);
1611 MPASS(scctx->isc_ntxd[0] > 0);
1612 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1613 MPASS(nsegments > 0);
1614 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1615 MPASS(ntsosegments > 0);
1616 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1620 * Setup DMA descriptor areas.
1622 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1623 1, 0, /* alignment, bounds */
1624 BUS_SPACE_MAXADDR, /* lowaddr */
1625 BUS_SPACE_MAXADDR, /* highaddr */
1626 NULL, NULL, /* filter, filterarg */
1627 sctx->isc_tx_maxsize, /* maxsize */
1628 nsegments, /* nsegments */
1629 sctx->isc_tx_maxsegsize, /* maxsegsize */
1631 NULL, /* lockfunc */
1632 NULL, /* lockfuncarg */
1633 &txq->ift_desc_tag))) {
1634 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1635 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1636 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1639 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) &
1640 (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1641 1, 0, /* alignment, bounds */
1642 BUS_SPACE_MAXADDR, /* lowaddr */
1643 BUS_SPACE_MAXADDR, /* highaddr */
1644 NULL, NULL, /* filter, filterarg */
1645 tsomaxsize, /* maxsize */
1646 ntsosegments, /* nsegments */
1647 sctx->isc_tso_maxsegsize,/* maxsegsize */
1649 NULL, /* lockfunc */
1650 NULL, /* lockfuncarg */
1651 &txq->ift_tso_desc_tag))) {
1652 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1656 if (!(txq->ift_sds.ifsd_flags =
1657 (uint8_t *) malloc(sizeof(uint8_t) *
1658 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1659 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1663 if (!(txq->ift_sds.ifsd_m =
1664 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1665 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1666 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1671 /* Create the descriptor buffer dma maps */
1672 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1673 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1676 if (!(txq->ift_sds.ifsd_map =
1677 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1678 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1683 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1684 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1686 device_printf(dev, "Unable to create TX DMA map\n");
1693 /* We free all, it handles case where we are in the middle */
1694 iflib_tx_structures_free(ctx);
1699 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1704 if (txq->ift_sds.ifsd_map != NULL)
1705 map = txq->ift_sds.ifsd_map[i];
1707 bus_dmamap_unload(txq->ift_desc_tag, map);
1708 bus_dmamap_destroy(txq->ift_desc_tag, map);
1709 txq->ift_sds.ifsd_map[i] = NULL;
1714 iflib_txq_destroy(iflib_txq_t txq)
1716 if_ctx_t ctx = txq->ift_ctx;
1718 for (int i = 0; i < txq->ift_size; i++)
1719 iflib_txsd_destroy(ctx, txq, i);
1720 if (txq->ift_sds.ifsd_map != NULL) {
1721 free(txq->ift_sds.ifsd_map, M_IFLIB);
1722 txq->ift_sds.ifsd_map = NULL;
1724 if (txq->ift_sds.ifsd_m != NULL) {
1725 free(txq->ift_sds.ifsd_m, M_IFLIB);
1726 txq->ift_sds.ifsd_m = NULL;
1728 if (txq->ift_sds.ifsd_flags != NULL) {
1729 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1730 txq->ift_sds.ifsd_flags = NULL;
1732 if (txq->ift_desc_tag != NULL) {
1733 bus_dma_tag_destroy(txq->ift_desc_tag);
1734 txq->ift_desc_tag = NULL;
1736 if (txq->ift_tso_desc_tag != NULL) {
1737 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1738 txq->ift_tso_desc_tag = NULL;
1743 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1747 mp = &txq->ift_sds.ifsd_m[i];
1751 if (txq->ift_sds.ifsd_map != NULL) {
1752 bus_dmamap_sync(txq->ift_desc_tag,
1753 txq->ift_sds.ifsd_map[i],
1754 BUS_DMASYNC_POSTWRITE);
1755 bus_dmamap_unload(txq->ift_desc_tag,
1756 txq->ift_sds.ifsd_map[i]);
1759 DBG_COUNTER_INC(tx_frees);
1764 iflib_txq_setup(iflib_txq_t txq)
1766 if_ctx_t ctx = txq->ift_ctx;
1767 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1768 iflib_dma_info_t di;
1771 /* Set number of descriptors available */
1772 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1773 /* XXX make configurable */
1774 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1777 txq->ift_cidx_processed = 0;
1778 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1779 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1781 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1782 bzero((void *)di->idi_vaddr, di->idi_size);
1784 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1785 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1786 bus_dmamap_sync(di->idi_tag, di->idi_map,
1787 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1791 /*********************************************************************
1793 * Allocate memory for rx_buffer structures. Since we use one
1794 * rx_buffer per received packet, the maximum number of rx_buffer's
1795 * that we'll need is equal to the number of receive descriptors
1796 * that we've allocated.
1798 **********************************************************************/
1800 iflib_rxsd_alloc(iflib_rxq_t rxq)
1802 if_ctx_t ctx = rxq->ifr_ctx;
1803 if_shared_ctx_t sctx = ctx->ifc_sctx;
1804 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1805 device_t dev = ctx->ifc_dev;
1809 MPASS(scctx->isc_nrxd[0] > 0);
1810 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1813 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1814 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1815 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1816 1, 0, /* alignment, bounds */
1817 BUS_SPACE_MAXADDR, /* lowaddr */
1818 BUS_SPACE_MAXADDR, /* highaddr */
1819 NULL, NULL, /* filter, filterarg */
1820 sctx->isc_rx_maxsize, /* maxsize */
1821 sctx->isc_rx_nsegments, /* nsegments */
1822 sctx->isc_rx_maxsegsize, /* maxsegsize */
1824 NULL, /* lockfunc */
1828 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1832 if (!(fl->ifl_sds.ifsd_flags =
1833 (uint8_t *) malloc(sizeof(uint8_t) *
1834 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1835 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1839 if (!(fl->ifl_sds.ifsd_m =
1840 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1841 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1842 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1846 if (!(fl->ifl_sds.ifsd_cl =
1847 (caddr_t *) malloc(sizeof(caddr_t) *
1848 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1849 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1854 /* Create the descriptor buffer dma maps */
1855 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1856 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1859 if (!(fl->ifl_sds.ifsd_map =
1860 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1861 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1866 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1867 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1869 device_printf(dev, "Unable to create RX buffer DMA map\n");
1878 iflib_rx_structures_free(ctx);
1884 * Internal service routines
1887 struct rxq_refill_cb_arg {
1889 bus_dma_segment_t seg;
1894 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1896 struct rxq_refill_cb_arg *cb_arg = arg;
1898 cb_arg->error = error;
1899 cb_arg->seg = segs[0];
1900 cb_arg->nseg = nseg;
1905 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1907 #define IS_DMAR(ctx) (0)
1911 * rxq_refill - refill an rxq free-buffer list
1912 * @ctx: the iflib context
1913 * @rxq: the free-list to refill
1914 * @n: the number of new buffers to allocate
1916 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1917 * The caller must assure that @n does not exceed the queue's capacity.
1920 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1923 int idx, frag_idx = fl->ifl_fragidx;
1924 int pidx = fl->ifl_pidx;
1928 struct if_rxd_update iru;
1929 bus_dmamap_t *sd_map;
1935 sd_m = fl->ifl_sds.ifsd_m;
1936 sd_map = fl->ifl_sds.ifsd_map;
1937 sd_cl = fl->ifl_sds.ifsd_cl;
1938 sd_flags = fl->ifl_sds.ifsd_flags;
1940 credits = fl->ifl_credits;
1944 MPASS(credits + n <= fl->ifl_size);
1946 if (pidx < fl->ifl_cidx)
1947 MPASS(pidx + n <= fl->ifl_cidx);
1948 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1949 MPASS(fl->ifl_gen == 0);
1950 if (pidx > fl->ifl_cidx)
1951 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1953 DBG_COUNTER_INC(fl_refills);
1955 DBG_COUNTER_INC(fl_refills_large);
1956 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1959 * We allocate an uninitialized mbuf + cluster, mbuf is
1960 * initialized after rx.
1962 * If the cluster is still set then we know a minimum sized packet was received
1964 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1965 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1966 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1967 if ((cl = sd_cl[frag_idx]) == NULL) {
1968 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1971 fl->ifl_cl_enqueued++;
1974 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1978 fl->ifl_m_enqueued++;
1981 DBG_COUNTER_INC(rx_allocs);
1982 #if defined(__i386__) || defined(__amd64__)
1983 if (!IS_DMAR(ctx)) {
1984 bus_addr = pmap_kextract((vm_offset_t)cl);
1988 struct rxq_refill_cb_arg cb_arg;
1991 MPASS(sd_map != NULL);
1992 MPASS(sd_map[frag_idx] != NULL);
1993 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1994 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1995 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1996 BUS_DMASYNC_PREREAD);
1998 if (err != 0 || cb_arg.error) {
2002 if (fl->ifl_zone == zone_pack)
2003 uma_zfree(fl->ifl_zone, cl);
2008 bus_addr = cb_arg.seg.ds_addr;
2010 bit_set(fl->ifl_rx_bitmap, frag_idx);
2011 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
2013 MPASS(sd_m[frag_idx] == NULL);
2014 sd_cl[frag_idx] = cl;
2016 fl->ifl_rxd_idxs[i] = frag_idx;
2017 fl->ifl_bus_addrs[i] = bus_addr;
2018 fl->ifl_vm_addrs[i] = cl;
2021 MPASS(credits <= fl->ifl_size);
2022 if (++idx == fl->ifl_size) {
2026 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2027 iru.iru_pidx = pidx;
2029 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2033 fl->ifl_credits = credits;
2039 iru.iru_pidx = pidx;
2041 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2043 fl->ifl_credits = credits;
2045 DBG_COUNTER_INC(rxd_flush);
2046 if (fl->ifl_pidx == 0)
2047 pidx = fl->ifl_size - 1;
2049 pidx = fl->ifl_pidx - 1;
2052 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2054 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2055 fl->ifl_fragidx = frag_idx;
2058 static __inline void
2059 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2061 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2062 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2064 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2067 MPASS(fl->ifl_credits <= fl->ifl_size);
2068 MPASS(reclaimable == delta);
2070 if (reclaimable > 0)
2071 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2075 iflib_fl_bufs_free(iflib_fl_t fl)
2077 iflib_dma_info_t idi = fl->ifl_ifdi;
2080 for (i = 0; i < fl->ifl_size; i++) {
2081 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2082 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
2083 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2085 if (*sd_flags & RX_SW_DESC_INUSE) {
2086 if (fl->ifl_sds.ifsd_map != NULL) {
2087 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
2088 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2089 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
2090 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2092 if (*sd_m != NULL) {
2093 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2094 uma_zfree(zone_mbuf, *sd_m);
2097 uma_zfree(fl->ifl_zone, *sd_cl);
2100 MPASS(*sd_cl == NULL);
2101 MPASS(*sd_m == NULL);
2104 fl->ifl_m_dequeued++;
2105 fl->ifl_cl_dequeued++;
2111 for (i = 0; i < fl->ifl_size; i++) {
2112 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2113 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2114 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2118 * Reset free list values
2120 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2121 bzero(idi->idi_vaddr, idi->idi_size);
2124 /*********************************************************************
2126 * Initialize a receive ring and its buffers.
2128 **********************************************************************/
2130 iflib_fl_setup(iflib_fl_t fl)
2132 iflib_rxq_t rxq = fl->ifl_rxq;
2133 if_ctx_t ctx = rxq->ifr_ctx;
2134 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2136 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2138 ** Free current RX buffer structs and their mbufs
2140 iflib_fl_bufs_free(fl);
2141 /* Now replenish the mbufs */
2142 MPASS(fl->ifl_credits == 0);
2144 * XXX don't set the max_frame_size to larger
2145 * than the hardware can handle
2147 if (sctx->isc_max_frame_size <= 2048)
2148 fl->ifl_buf_size = MCLBYTES;
2149 #ifndef CONTIGMALLOC_WORKS
2151 fl->ifl_buf_size = MJUMPAGESIZE;
2153 else if (sctx->isc_max_frame_size <= 4096)
2154 fl->ifl_buf_size = MJUMPAGESIZE;
2155 else if (sctx->isc_max_frame_size <= 9216)
2156 fl->ifl_buf_size = MJUM9BYTES;
2158 fl->ifl_buf_size = MJUM16BYTES;
2160 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2161 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2162 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2163 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2166 /* avoid pre-allocating zillions of clusters to an idle card
2167 * potentially speeding up attach
2169 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2170 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2171 if (min(128, fl->ifl_size) != fl->ifl_credits)
2177 MPASS(fl->ifl_ifdi != NULL);
2178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2183 /*********************************************************************
2185 * Free receive ring data structures
2187 **********************************************************************/
2189 iflib_rx_sds_free(iflib_rxq_t rxq)
2194 if (rxq->ifr_fl != NULL) {
2195 for (i = 0; i < rxq->ifr_nfl; i++) {
2196 fl = &rxq->ifr_fl[i];
2197 if (fl->ifl_desc_tag != NULL) {
2198 bus_dma_tag_destroy(fl->ifl_desc_tag);
2199 fl->ifl_desc_tag = NULL;
2201 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2202 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2203 /* XXX destroy maps first */
2204 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2205 fl->ifl_sds.ifsd_m = NULL;
2206 fl->ifl_sds.ifsd_cl = NULL;
2207 fl->ifl_sds.ifsd_map = NULL;
2209 free(rxq->ifr_fl, M_IFLIB);
2211 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2216 * MI independent logic
2220 iflib_timer(void *arg)
2222 iflib_txq_t txq = arg;
2223 if_ctx_t ctx = txq->ift_ctx;
2224 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2225 uint64_t this_tick = ticks;
2226 uint32_t reset_on = hz / 2;
2228 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2231 ** Check on the state of the TX queue(s), this
2232 ** can be done without the lock because its RO
2233 ** and the HUNG state will be static if set.
2235 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2236 txq->ift_last_timer_tick = this_tick;
2237 IFDI_TIMER(ctx, txq->ift_id);
2238 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2239 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2240 (sctx->isc_pause_frames == 0)))
2243 if (ifmp_ring_is_stalled(txq->ift_br))
2244 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2245 txq->ift_cleaned_prev = txq->ift_cleaned;
2248 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2249 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2251 /* handle any laggards */
2252 if (txq->ift_db_pending)
2253 GROUPTASK_ENQUEUE(&txq->ift_task);
2255 sctx->isc_pause_frames = 0;
2256 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2257 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2260 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2261 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2263 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2264 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2265 iflib_admin_intr_deferred(ctx);
2270 iflib_init_locked(if_ctx_t ctx)
2272 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2273 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2274 if_t ifp = ctx->ifc_ifp;
2278 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2281 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2282 IFDI_INTR_DISABLE(ctx);
2284 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2285 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2286 /* Set hardware offload abilities */
2287 if_clearhwassist(ifp);
2288 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2289 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2290 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2291 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2292 if (if_getcapenable(ifp) & IFCAP_TSO4)
2293 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2294 if (if_getcapenable(ifp) & IFCAP_TSO6)
2295 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2297 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2299 callout_stop(&txq->ift_timer);
2300 CALLOUT_UNLOCK(txq);
2301 iflib_netmap_txq_init(ctx, txq);
2304 i = if_getdrvflags(ifp);
2307 MPASS(if_getdrvflags(ifp) == i);
2308 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2309 /* XXX this should really be done on a per-queue basis */
2310 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2311 MPASS(rxq->ifr_id == i);
2312 iflib_netmap_rxq_init(ctx, rxq);
2315 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2316 if (iflib_fl_setup(fl)) {
2317 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2323 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2324 IFDI_INTR_ENABLE(ctx);
2325 txq = ctx->ifc_txqs;
2326 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2327 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2328 txq->ift_timer.c_cpu);
2332 iflib_media_change(if_t ifp)
2334 if_ctx_t ctx = if_getsoftc(ifp);
2338 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2339 iflib_init_locked(ctx);
2345 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2347 if_ctx_t ctx = if_getsoftc(ifp);
2350 IFDI_UPDATE_ADMIN_STATUS(ctx);
2351 IFDI_MEDIA_STATUS(ctx, ifmr);
2356 iflib_stop(if_ctx_t ctx)
2358 iflib_txq_t txq = ctx->ifc_txqs;
2359 iflib_rxq_t rxq = ctx->ifc_rxqs;
2360 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2361 iflib_dma_info_t di;
2365 /* Tell the stack that the interface is no longer active */
2366 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2368 IFDI_INTR_DISABLE(ctx);
2373 iflib_debug_reset();
2374 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2375 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2376 /* make sure all transmitters have completed before proceeding XXX */
2379 callout_stop(&txq->ift_timer);
2380 CALLOUT_UNLOCK(txq);
2382 /* clean any enqueued buffers */
2383 iflib_ifmp_purge(txq);
2384 /* Free any existing tx buffers. */
2385 for (j = 0; j < txq->ift_size; j++) {
2386 iflib_txsd_free(ctx, txq, j);
2388 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2389 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2390 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2391 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2392 txq->ift_pullups = 0;
2393 ifmp_ring_reset_stats(txq->ift_br);
2394 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2395 bzero((void *)di->idi_vaddr, di->idi_size);
2397 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2398 /* make sure all transmitters have completed before proceeding XXX */
2400 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++)
2401 bzero((void *)di->idi_vaddr, di->idi_size);
2402 /* also resets the free lists pidx/cidx */
2403 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2404 iflib_fl_bufs_free(fl);
2408 static inline caddr_t
2409 calc_next_rxd(iflib_fl_t fl, int cidx)
2413 caddr_t start, end, cur, next;
2415 nrxd = fl->ifl_size;
2416 size = fl->ifl_rxd_size;
2417 start = fl->ifl_ifdi->idi_vaddr;
2419 if (__predict_false(size == 0))
2421 cur = start + size*cidx;
2422 end = start + size*nrxd;
2423 next = CACHE_PTR_NEXT(cur);
2424 return (next < end ? next : start);
2428 prefetch_pkts(iflib_fl_t fl, int cidx)
2431 int nrxd = fl->ifl_size;
2435 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2436 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2437 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2438 next_rxd = calc_next_rxd(fl, cidx);
2440 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2441 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2442 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2443 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2444 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2445 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2446 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2447 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2451 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2456 iflib_dma_info_t di;
2460 flid = irf->irf_flid;
2461 cidx = irf->irf_idx;
2462 fl = &rxq->ifr_fl[flid];
2464 sd->ifsd_cidx = cidx;
2465 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2466 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2469 fl->ifl_m_dequeued++;
2471 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2472 prefetch_pkts(fl, cidx);
2473 if (fl->ifl_sds.ifsd_map != NULL) {
2474 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2475 prefetch(&fl->ifl_sds.ifsd_map[next]);
2476 map = fl->ifl_sds.ifsd_map[cidx];
2478 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2479 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2480 bus_dmamap_sync(di->idi_tag, di->idi_map,
2481 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2483 /* not valid assert if bxe really does SGE from non-contiguous elements */
2484 MPASS(fl->ifl_cidx == cidx);
2486 bus_dmamap_unload(fl->ifl_desc_tag, map);
2488 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2489 if (__predict_false(fl->ifl_cidx == 0))
2492 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2494 bit_clear(fl->ifl_rx_bitmap, cidx);
2497 static struct mbuf *
2498 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2500 int i, padlen , flags;
2501 struct mbuf *m, *mh, *mt;
2507 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2509 MPASS(*sd->ifsd_cl != NULL);
2510 MPASS(*sd->ifsd_m != NULL);
2512 /* Don't include zero-length frags */
2513 if (ri->iri_frags[i].irf_len == 0) {
2514 /* XXX we can save the cluster here, but not the mbuf */
2515 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2516 m_free(*sd->ifsd_m);
2523 flags = M_PKTHDR|M_EXT;
2525 padlen = ri->iri_pad;
2530 /* assuming padding is only on the first fragment */
2534 *sd->ifsd_cl = NULL;
2536 /* Can these two be made one ? */
2537 m_init(m, M_NOWAIT, MT_DATA, flags);
2538 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2540 * These must follow m_init and m_cljset
2542 m->m_data += padlen;
2543 ri->iri_len -= padlen;
2544 m->m_len = ri->iri_frags[i].irf_len;
2545 } while (++i < ri->iri_nfrags);
2551 * Process one software descriptor
2553 static struct mbuf *
2554 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2559 /* should I merge this back in now that the two paths are basically duplicated? */
2560 if (ri->iri_nfrags == 1 &&
2561 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2562 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2565 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2566 #ifndef __NO_STRICT_ALIGNMENT
2570 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2571 m->m_len = ri->iri_frags[0].irf_len;
2573 m = assemble_segments(rxq, ri, &sd);
2575 m->m_pkthdr.len = ri->iri_len;
2576 m->m_pkthdr.rcvif = ri->iri_ifp;
2577 m->m_flags |= ri->iri_flags;
2578 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2579 m->m_pkthdr.flowid = ri->iri_flowid;
2580 M_HASHTYPE_SET(m, ri->iri_rsstype);
2581 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2582 m->m_pkthdr.csum_data = ri->iri_csum_data;
2586 #if defined(INET6) || defined(INET)
2588 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2590 CURVNET_SET(lc->ifp->if_vnet);
2592 *v6 = VNET(ip6_forwarding);
2595 *v4 = VNET(ipforwarding);
2601 * Returns true if it's possible this packet could be LROed.
2602 * if it returns false, it is guaranteed that tcp_lro_rx()
2603 * would not return zero.
2606 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2608 struct ether_header *eh;
2611 eh = mtod(m, struct ether_header *);
2612 eh_type = ntohs(eh->ether_type);
2615 case ETHERTYPE_IPV6:
2616 return !v6_forwarding;
2620 return !v4_forwarding;
2628 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2634 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2636 if_ctx_t ctx = rxq->ifr_ctx;
2637 if_shared_ctx_t sctx = ctx->ifc_sctx;
2638 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2641 struct if_rxd_info ri;
2642 int err, budget_left, rx_bytes, rx_pkts;
2646 bool v4_forwarding, v6_forwarding, lro_possible;
2649 * XXX early demux data packets so that if_input processing only handles
2650 * acks in interrupt context
2652 struct mbuf *m, *mh, *mt, *mf;
2654 lro_possible = v4_forwarding = v6_forwarding = false;
2658 rx_pkts = rx_bytes = 0;
2659 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2660 cidxp = &rxq->ifr_cq_cidx;
2662 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2663 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2664 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2665 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2666 DBG_COUNTER_INC(rx_unavail);
2670 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2671 if (__predict_false(!CTX_ACTIVE(ctx))) {
2672 DBG_COUNTER_INC(rx_ctx_inactive);
2676 * Reset client set fields to their default values
2679 ri.iri_qsidx = rxq->ifr_id;
2680 ri.iri_cidx = *cidxp;
2682 ri.iri_frags = rxq->ifr_frags;
2683 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2687 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2688 *cidxp = ri.iri_cidx;
2689 /* Update our consumer index */
2690 /* XXX NB: shurd - check if this is still safe */
2691 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2692 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2693 rxq->ifr_cq_gen = 0;
2695 /* was this only a completion queue message? */
2696 if (__predict_false(ri.iri_nfrags == 0))
2699 MPASS(ri.iri_nfrags != 0);
2700 MPASS(ri.iri_len != 0);
2702 /* will advance the cidx on the corresponding free lists */
2703 m = iflib_rxd_pkt_get(rxq, &ri);
2706 if (avail == 0 && budget_left)
2707 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2709 if (__predict_false(m == NULL)) {
2710 DBG_COUNTER_INC(rx_mbuf_null);
2713 /* imm_pkt: -- cxgb */
2721 /* make sure that we can refill faster than drain */
2722 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2723 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2725 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2727 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2729 while (mh != NULL) {
2732 m->m_nextpkt = NULL;
2733 #ifndef __NO_STRICT_ALIGNMENT
2734 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2737 rx_bytes += m->m_pkthdr.len;
2739 #if defined(INET6) || defined(INET)
2741 if (!lro_possible) {
2742 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2743 if (lro_possible && mf != NULL) {
2744 ifp->if_input(ifp, mf);
2745 DBG_COUNTER_INC(rx_if_input);
2749 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2750 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2751 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2757 ifp->if_input(ifp, m);
2758 DBG_COUNTER_INC(rx_if_input);
2769 ifp->if_input(ifp, mf);
2770 DBG_COUNTER_INC(rx_if_input);
2773 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2774 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2777 * Flush any outstanding LRO work
2779 #if defined(INET6) || defined(INET)
2780 tcp_lro_flush_all(&rxq->ifr_lc);
2784 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2787 ctx->ifc_flags |= IFC_DO_RESET;
2788 iflib_admin_intr_deferred(ctx);
2793 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2794 static inline qidx_t
2795 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2797 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2798 qidx_t minthresh = txq->ift_size / 8;
2799 if (in_use > 4*minthresh)
2800 return (notify_count);
2801 if (in_use > 2*minthresh)
2802 return (notify_count >> 1);
2803 if (in_use > minthresh)
2804 return (notify_count >> 3);
2808 static inline qidx_t
2809 txq_max_rs_deferred(iflib_txq_t txq)
2811 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2812 qidx_t minthresh = txq->ift_size / 8;
2813 if (txq->ift_in_use > 4*minthresh)
2814 return (notify_count);
2815 if (txq->ift_in_use > 2*minthresh)
2816 return (notify_count >> 1);
2817 if (txq->ift_in_use > minthresh)
2818 return (notify_count >> 2);
2822 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2823 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2825 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2826 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2827 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2829 /* forward compatibility for cxgb */
2830 #define FIRST_QSET(ctx) 0
2831 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2832 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2833 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2834 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2836 /* XXX we should be setting this to something other than zero */
2837 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2838 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2839 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2842 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2848 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2849 if (ring || txq->ift_db_pending >= max) {
2850 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2851 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2852 txq->ift_db_pending = txq->ift_npending = 0;
2860 print_pkt(if_pkt_info_t pi)
2862 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2863 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2864 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2865 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2866 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2867 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2871 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2872 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2873 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2874 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2877 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2879 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2880 struct ether_vlan_header *eh;
2884 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2885 M_WRITABLE(m) == 0) {
2886 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2895 * Determine where frame payload starts.
2896 * Jump over vlan headers if already present,
2897 * helpful for QinQ too.
2899 if (__predict_false(m->m_len < sizeof(*eh))) {
2901 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2904 eh = mtod(m, struct ether_vlan_header *);
2905 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2906 pi->ipi_etype = ntohs(eh->evl_proto);
2907 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2909 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2910 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2913 switch (pi->ipi_etype) {
2918 struct ip *ip = NULL;
2919 struct tcphdr *th = NULL;
2922 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2923 if (__predict_false(m->m_len < minthlen)) {
2925 * if this code bloat is causing too much of a hit
2926 * move it to a separate function and mark it noinline
2928 if (m->m_len == pi->ipi_ehdrlen) {
2931 if (n->m_len >= sizeof(*ip)) {
2932 ip = (struct ip *)n->m_data;
2933 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2934 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2937 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2939 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2943 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2945 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2946 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2947 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2950 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2951 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2952 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2954 pi->ipi_ip_hlen = ip->ip_hl << 2;
2955 pi->ipi_ipproto = ip->ip_p;
2956 pi->ipi_flags |= IPI_TX_IPV4;
2958 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2961 /* TCP checksum offload may require TCP header length */
2962 if (IS_TX_OFFLOAD4(pi)) {
2963 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2964 if (__predict_false(th == NULL)) {
2966 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2968 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2970 pi->ipi_tcp_hflags = th->th_flags;
2971 pi->ipi_tcp_hlen = th->th_off << 2;
2972 pi->ipi_tcp_seq = th->th_seq;
2975 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2977 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2978 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2979 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2980 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2982 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2990 case ETHERTYPE_IPV6:
2992 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2994 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2996 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2997 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3000 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3002 /* XXX-BZ this will go badly in case of ext hdrs. */
3003 pi->ipi_ipproto = ip6->ip6_nxt;
3004 pi->ipi_flags |= IPI_TX_IPV6;
3006 /* TCP checksum offload may require TCP header length */
3007 if (IS_TX_OFFLOAD6(pi)) {
3008 if (pi->ipi_ipproto == IPPROTO_TCP) {
3009 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3011 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3014 pi->ipi_tcp_hflags = th->th_flags;
3015 pi->ipi_tcp_hlen = th->th_off << 2;
3016 pi->ipi_tcp_seq = th->th_seq;
3019 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3022 * The corresponding flag is set by the stack in the IPv4
3023 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
3024 * So, set it here because the rest of the flow requires it.
3026 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3027 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3028 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3035 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3036 pi->ipi_ip_hlen = 0;
3044 static __noinline struct mbuf *
3045 collapse_pkthdr(struct mbuf *m0)
3047 struct mbuf *m, *m_next, *tmp;
3051 while (m_next != NULL && m_next->m_len == 0) {
3055 m_next = m_next->m_next;
3061 if ((m_next->m_flags & M_EXT) == 0) {
3062 m = m_defrag(m, M_NOWAIT);
3064 tmp = m_next->m_next;
3065 memcpy(m_next, m, MPKTHSIZE);
3073 * If dodgy hardware rejects the scatter gather chain we've handed it
3074 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3077 static __noinline struct mbuf *
3078 iflib_remove_mbuf(iflib_txq_t txq)
3081 struct mbuf *m, *mh, **ifsd_m;
3083 pidx = txq->ift_pidx;
3084 ifsd_m = txq->ift_sds.ifsd_m;
3085 ntxd = txq->ift_size;
3086 mh = m = ifsd_m[pidx];
3087 ifsd_m[pidx] = NULL;
3089 txq->ift_dequeued++;
3094 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
3096 txq->ift_dequeued++;
3105 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
3106 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
3107 int max_segs, int flags)
3110 if_shared_ctx_t sctx;
3111 if_softc_ctx_t scctx;
3112 int i, next, pidx, err, ntxd, count;
3113 struct mbuf *m, *tmp, **ifsd_m;
3118 * Please don't ever do this
3120 if (__predict_false(m->m_len == 0))
3121 *m0 = collapse_pkthdr(m);
3124 sctx = ctx->ifc_sctx;
3125 scctx = &ctx->ifc_softc_ctx;
3126 ifsd_m = txq->ift_sds.ifsd_m;
3127 ntxd = txq->ift_size;
3128 pidx = txq->ift_pidx;
3130 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3132 err = bus_dmamap_load_mbuf_sg(tag, map,
3133 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3136 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3140 if (__predict_false(m->m_len <= 0)) {
3149 } while (m != NULL);
3150 if (count > *nsegs) {
3152 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3158 next = (pidx + count) & (ntxd-1);
3159 MPASS(ifsd_m[next] == NULL);
3164 } while (m != NULL);
3166 int buflen, sgsize, maxsegsz, max_sgsize;
3172 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3173 maxsegsz = scctx->isc_tx_tso_segsize_max;
3175 maxsegsz = sctx->isc_tx_maxsegsize;
3178 if (__predict_false(m->m_len <= 0)) {
3186 vaddr = (vm_offset_t)m->m_data;
3188 * see if we can't be smarter about physically
3189 * contiguous mappings
3191 next = (pidx + count) & (ntxd-1);
3192 MPASS(ifsd_m[next] == NULL);
3194 txq->ift_enqueued++;
3197 while (buflen > 0) {
3200 max_sgsize = MIN(buflen, maxsegsz);
3201 curaddr = pmap_kextract(vaddr);
3202 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3203 sgsize = MIN(sgsize, max_sgsize);
3204 segs[i].ds_addr = curaddr;
3205 segs[i].ds_len = sgsize;
3213 } while (m != NULL);
3218 *m0 = iflib_remove_mbuf(txq);
3222 static inline caddr_t
3223 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3227 caddr_t start, end, cur, next;
3229 ntxd = txq->ift_size;
3230 size = txq->ift_txd_size[qid];
3231 start = txq->ift_ifdi[qid].idi_vaddr;
3233 if (__predict_false(size == 0))
3235 cur = start + size*cidx;
3236 end = start + size*ntxd;
3237 next = CACHE_PTR_NEXT(cur);
3238 return (next < end ? next : start);
3242 * Pad an mbuf to ensure a minimum ethernet frame size.
3243 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3245 static __noinline int
3246 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3249 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3250 * and ARP message is the smallest common payload I can think of
3252 static char pad[18]; /* just zeros */
3254 struct mbuf *new_head;
3256 if (!M_WRITABLE(*m_head)) {
3257 new_head = m_dup(*m_head, M_NOWAIT);
3258 if (new_head == NULL) {
3260 device_printf(dev, "cannot pad short frame, m_dup() failed");
3261 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3268 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3269 n > 0; n -= sizeof(pad))
3270 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3275 device_printf(dev, "cannot pad short frame\n");
3276 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3284 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3287 if_shared_ctx_t sctx;
3288 if_softc_ctx_t scctx;
3289 bus_dma_segment_t *segs;
3290 struct mbuf *m_head;
3293 struct if_pkt_info pi;
3295 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3296 bus_dma_tag_t desc_tag;
3299 sctx = ctx->ifc_sctx;
3300 scctx = &ctx->ifc_softc_ctx;
3301 segs = txq->ift_segs;
3302 ntxd = txq->ift_size;
3307 * If we're doing TSO the next descriptor to clean may be quite far ahead
3309 cidx = txq->ift_cidx;
3310 pidx = txq->ift_pidx;
3311 if (ctx->ifc_flags & IFC_PREFETCH) {
3312 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3313 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3314 next_txd = calc_next_txd(txq, cidx, 0);
3318 /* prefetch the next cache line of mbuf pointers and flags */
3319 prefetch(&txq->ift_sds.ifsd_m[next]);
3320 if (txq->ift_sds.ifsd_map != NULL) {
3321 prefetch(&txq->ift_sds.ifsd_map[next]);
3322 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3323 prefetch(&txq->ift_sds.ifsd_flags[next]);
3325 } else if (txq->ift_sds.ifsd_map != NULL)
3326 map = txq->ift_sds.ifsd_map[pidx];
3328 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3329 desc_tag = txq->ift_tso_desc_tag;
3330 max_segs = scctx->isc_tx_tso_segments_max;
3331 MPASS(desc_tag != NULL);
3332 MPASS(max_segs > 0);
3334 desc_tag = txq->ift_desc_tag;
3335 max_segs = scctx->isc_tx_nsegments;
3337 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3338 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3339 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3346 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3348 pi.ipi_qsidx = txq->ift_id;
3349 pi.ipi_len = m_head->m_pkthdr.len;
3350 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3351 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3353 /* deliberate bitwise OR to make one condition */
3354 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3355 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3361 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3363 if (__predict_false(err)) {
3366 /* try collapse once and defrag once */
3368 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3369 /* try defrag if collapsing fails */
3374 m_head = m_defrag(*m_headp, M_NOWAIT);
3376 if (__predict_false(m_head == NULL))
3378 txq->ift_mbuf_defrag++;
3383 txq->ift_no_tx_dma_setup++;
3386 txq->ift_no_tx_dma_setup++;
3388 DBG_COUNTER_INC(tx_frees);
3392 txq->ift_map_failed++;
3393 DBG_COUNTER_INC(encap_load_mbuf_fail);
3398 * XXX assumes a 1 to 1 relationship between segments and
3399 * descriptors - this does not hold true on all drivers, e.g.
3402 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3403 txq->ift_no_desc_avail++;
3405 bus_dmamap_unload(desc_tag, map);
3406 DBG_COUNTER_INC(encap_txq_avail_fail);
3407 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3408 GROUPTASK_ENQUEUE(&txq->ift_task);
3412 * On Intel cards we can greatly reduce the number of TX interrupts
3413 * we see by only setting report status on every Nth descriptor.
3414 * However, this also means that the driver will need to keep track
3415 * of the descriptors that RS was set on to check them for the DD bit.
3417 txq->ift_rs_pending += nsegs + 1;
3418 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3419 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3420 pi.ipi_flags |= IPI_TX_INTR;
3421 txq->ift_rs_pending = 0;
3425 pi.ipi_nsegs = nsegs;
3427 MPASS(pidx >= 0 && pidx < txq->ift_size);
3432 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3433 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3435 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3436 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3437 DBG_COUNTER_INC(tx_encap);
3438 MPASS(pi.ipi_new_pidx < txq->ift_size);
3440 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3441 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3442 ndesc += txq->ift_size;
3446 * drivers can need as many as
3449 MPASS(ndesc <= pi.ipi_nsegs + 2);
3450 MPASS(pi.ipi_new_pidx != pidx);
3452 txq->ift_in_use += ndesc;
3455 * We update the last software descriptor again here because there may
3456 * be a sentinel and/or there may be more mbufs than segments
3458 txq->ift_pidx = pi.ipi_new_pidx;
3459 txq->ift_npending += pi.ipi_ndescs;
3461 *m_headp = m_head = iflib_remove_mbuf(txq);
3463 txq->ift_txd_encap_efbig++;
3469 DBG_COUNTER_INC(encap_txd_encap_fail);
3475 txq->ift_mbuf_defrag_failed++;
3476 txq->ift_map_failed++;
3478 DBG_COUNTER_INC(tx_frees);
3484 iflib_tx_desc_free(iflib_txq_t txq, int n)
3487 uint32_t qsize, cidx, mask, gen;
3488 struct mbuf *m, **ifsd_m;
3489 uint8_t *ifsd_flags;
3490 bus_dmamap_t *ifsd_map;
3493 cidx = txq->ift_cidx;
3495 qsize = txq->ift_size;
3497 hasmap = txq->ift_sds.ifsd_map != NULL;
3498 ifsd_flags = txq->ift_sds.ifsd_flags;
3499 ifsd_m = txq->ift_sds.ifsd_m;
3500 ifsd_map = txq->ift_sds.ifsd_map;
3501 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3505 prefetch(ifsd_m[(cidx + 3) & mask]);
3506 prefetch(ifsd_m[(cidx + 4) & mask]);
3508 if (ifsd_m[cidx] != NULL) {
3509 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3510 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3511 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3513 * does it matter if it's not the TSO tag? If so we'll
3514 * have to add the type to flags
3516 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3517 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3519 if ((m = ifsd_m[cidx]) != NULL) {
3520 /* XXX we don't support any drivers that batch packets yet */
3521 MPASS(m->m_nextpkt == NULL);
3522 /* if the number of clusters exceeds the number of segments
3523 * there won't be space on the ring to save a pointer to each
3524 * cluster so we simply free the list here
3526 if (m->m_flags & M_TOOBIG) {
3531 ifsd_m[cidx] = NULL;
3533 txq->ift_dequeued++;
3535 DBG_COUNTER_INC(tx_frees);
3538 if (__predict_false(++cidx == qsize)) {
3543 txq->ift_cidx = cidx;
3548 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3551 if_ctx_t ctx = txq->ift_ctx;
3553 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3554 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3557 * Need a rate-limiting check so that this isn't called every time
3559 iflib_tx_credits_update(ctx, txq);
3560 reclaim = DESC_RECLAIMABLE(txq);
3562 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3564 if (iflib_verbose_debug) {
3565 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3566 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3573 iflib_tx_desc_free(txq, reclaim);
3574 txq->ift_cleaned += reclaim;
3575 txq->ift_in_use -= reclaim;
3580 static struct mbuf **
3581 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3584 struct mbuf **items;
3587 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3588 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3590 prefetch(items[(cidx + offset) & (size-1)]);
3591 if (remaining > 1) {
3592 prefetch2cachelines(&items[next]);
3593 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3594 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3595 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3597 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3601 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3604 ifmp_ring_check_drainage(txq->ift_br, budget);
3608 iflib_txq_can_drain(struct ifmp_ring *r)
3610 iflib_txq_t txq = r->cookie;
3611 if_ctx_t ctx = txq->ift_ctx;
3613 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3614 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3618 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3620 iflib_txq_t txq = r->cookie;
3621 if_ctx_t ctx = txq->ift_ctx;
3622 struct ifnet *ifp = ctx->ifc_ifp;
3623 struct mbuf **mp, *m;
3624 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3625 int reclaimed, err, in_use_prev, desc_used;
3626 bool do_prefetch, ring, rang;
3628 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3629 !LINK_ACTIVE(ctx))) {
3630 DBG_COUNTER_INC(txq_drain_notready);
3633 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3634 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3635 avail = IDXDIFF(pidx, cidx, r->size);
3636 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3637 DBG_COUNTER_INC(txq_drain_flushing);
3638 for (i = 0; i < avail; i++) {
3639 m_free(r->items[(cidx + i) & (r->size-1)]);
3640 r->items[(cidx + i) & (r->size-1)] = NULL;
3645 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3646 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3648 callout_stop(&txq->ift_timer);
3649 CALLOUT_UNLOCK(txq);
3650 DBG_COUNTER_INC(txq_drain_oactive);
3654 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3655 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3656 count = MIN(avail, TX_BATCH_SIZE);
3658 if (iflib_verbose_debug)
3659 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3660 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3662 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3663 avail = TXQ_AVAIL(txq);
3665 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3666 int rem = do_prefetch ? count - i : 0;
3668 mp = _ring_peek_one(r, cidx, i, rem);
3669 MPASS(mp != NULL && *mp != NULL);
3670 if (__predict_false(*mp == (struct mbuf *)txq)) {
3675 in_use_prev = txq->ift_in_use;
3676 err = iflib_encap(txq, mp);
3677 if (__predict_false(err)) {
3678 DBG_COUNTER_INC(txq_drain_encapfail);
3679 /* no room - bail out */
3683 DBG_COUNTER_INC(txq_drain_encapfail);
3684 /* we can't send this packet - skip it */
3690 DBG_COUNTER_INC(tx_sent);
3691 bytes_sent += m->m_pkthdr.len;
3692 mcast_sent += !!(m->m_flags & M_MCAST);
3693 avail = TXQ_AVAIL(txq);
3695 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3696 desc_used += (txq->ift_in_use - in_use_prev);
3697 ETHER_BPF_MTAP(ifp, m);
3698 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3700 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3703 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3704 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3705 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3706 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3707 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3709 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3711 if (iflib_verbose_debug)
3712 printf("consumed=%d\n", consumed);
3718 iflib_txq_drain_always(struct ifmp_ring *r)
3724 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3732 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3734 callout_stop(&txq->ift_timer);
3735 CALLOUT_UNLOCK(txq);
3737 avail = IDXDIFF(pidx, cidx, r->size);
3738 for (i = 0; i < avail; i++) {
3739 mp = _ring_peek_one(r, cidx, i, avail - i);
3740 if (__predict_false(*mp == (struct mbuf *)txq))
3744 MPASS(ifmp_ring_is_stalled(r) == 0);
3749 iflib_ifmp_purge(iflib_txq_t txq)
3751 struct ifmp_ring *r;
3754 r->drain = iflib_txq_drain_free;
3755 r->can_drain = iflib_txq_drain_always;
3757 ifmp_ring_check_drainage(r, r->size);
3759 r->drain = iflib_txq_drain;
3760 r->can_drain = iflib_txq_can_drain;
3764 _task_fn_tx(void *context)
3766 iflib_txq_t txq = context;
3767 if_ctx_t ctx = txq->ift_ctx;
3768 struct ifnet *ifp = ctx->ifc_ifp;
3769 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3771 #ifdef IFLIB_DIAGNOSTICS
3772 txq->ift_cpu_exec_count[curcpu]++;
3774 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3776 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3777 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3778 netmap_tx_irq(ifp, txq->ift_id);
3779 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3783 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3784 iflib_altq_if_start(ifp);
3786 if (txq->ift_db_pending)
3787 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3789 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3791 * When abdicating, we always need to check drainage, not just when we don't enqueue
3794 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3795 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3796 if (ctx->ifc_flags & IFC_LEGACY)
3797 IFDI_INTR_ENABLE(ctx);
3802 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3803 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3808 _task_fn_rx(void *context)
3810 iflib_rxq_t rxq = context;
3811 if_ctx_t ctx = rxq->ifr_ctx;
3815 #ifdef IFLIB_DIAGNOSTICS
3816 rxq->ifr_cpu_exec_count[curcpu]++;
3818 DBG_COUNTER_INC(task_fn_rxs);
3819 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3823 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3825 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3830 budget = ctx->ifc_sysctl_rx_budget;
3832 budget = 16; /* XXX */
3833 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3834 if (ctx->ifc_flags & IFC_LEGACY)
3835 IFDI_INTR_ENABLE(ctx);
3840 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3841 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3842 DBG_COUNTER_INC(rx_intr_enables);
3845 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3848 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3852 _task_fn_admin(void *context)
3854 if_ctx_t ctx = context;
3855 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3858 bool oactive, running, do_reset, do_watchdog;
3859 uint32_t reset_on = hz / 2;
3862 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3863 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3864 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3865 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3866 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3869 if ((!running & !oactive) &&
3870 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3874 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3876 callout_stop(&txq->ift_timer);
3877 CALLOUT_UNLOCK(txq);
3880 ctx->ifc_watchdog_events++;
3881 IFDI_WATCHDOG_RESET(ctx);
3883 IFDI_UPDATE_ADMIN_STATUS(ctx);
3884 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3887 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3888 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3890 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3892 IFDI_LINK_INTR_ENABLE(ctx);
3894 iflib_if_init_locked(ctx);
3897 if (LINK_ACTIVE(ctx) == 0)
3899 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3900 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3905 _task_fn_iov(void *context)
3907 if_ctx_t ctx = context;
3909 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3913 IFDI_VFLR_HANDLE(ctx);
3918 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3921 if_int_delay_info_t info;
3924 info = (if_int_delay_info_t)arg1;
3925 ctx = info->iidi_ctx;
3926 info->iidi_req = req;
3927 info->iidi_oidp = oidp;
3929 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3934 /*********************************************************************
3938 **********************************************************************/
3941 iflib_if_init_locked(if_ctx_t ctx)
3944 iflib_init_locked(ctx);
3949 iflib_if_init(void *arg)
3954 iflib_if_init_locked(ctx);
3959 iflib_if_transmit(if_t ifp, struct mbuf *m)
3961 if_ctx_t ctx = if_getsoftc(ifp);
3965 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3967 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3968 DBG_COUNTER_INC(tx_frees);
3973 MPASS(m->m_nextpkt == NULL);
3974 /* ALTQ-enabled interfaces always use queue 0. */
3976 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3977 qidx = QIDX(ctx, m);
3979 * XXX calculate buf_ring based on flowid (divvy up bits?)
3981 txq = &ctx->ifc_txqs[qidx];
3983 #ifdef DRIVER_BACKPRESSURE
3984 if (txq->ift_closed) {
3986 next = m->m_nextpkt;
3987 m->m_nextpkt = NULL;
4000 next = next->m_nextpkt;
4001 } while (next != NULL);
4003 if (count > nitems(marr))
4004 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4005 /* XXX check nextpkt */
4007 /* XXX simplify for now */
4008 DBG_COUNTER_INC(tx_frees);
4011 for (next = m, i = 0; next != NULL; i++) {
4013 next = next->m_nextpkt;
4014 mp[i]->m_nextpkt = NULL;
4017 DBG_COUNTER_INC(tx_seen);
4018 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4021 GROUPTASK_ENQUEUE(&txq->ift_task);
4024 GROUPTASK_ENQUEUE(&txq->ift_task);
4025 /* support forthcoming later */
4026 #ifdef DRIVER_BACKPRESSURE
4027 txq->ift_closed = TRUE;
4029 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4038 * The overall approach to integrating iflib with ALTQ is to continue to use
4039 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4040 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4041 * is redundant/unnecessary, but doing so minimizes the amount of
4042 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4043 * redundantly queueing to an intermediate mp_ring is swamped by the
4044 * performance limitations inherent in using ALTQ.
4046 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4047 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4048 * given interface. If ALTQ is enabled for an interface, then all
4049 * transmitted packets for that interface will be submitted to the ALTQ
4050 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4051 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4052 * update stats that the iflib machinery handles, and which is sensitve to
4053 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4054 * will be installed as the start routine for use by ALTQ facilities that
4055 * need to trigger queue drains on a scheduled basis.
4059 iflib_altq_if_start(if_t ifp)
4061 struct ifaltq *ifq = &ifp->if_snd;
4065 IFQ_DEQUEUE_NOLOCK(ifq, m);
4067 iflib_if_transmit(ifp, m);
4068 IFQ_DEQUEUE_NOLOCK(ifq, m);
4074 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4078 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4079 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4081 iflib_altq_if_start(ifp);
4083 err = iflib_if_transmit(ifp, m);
4090 iflib_if_qflush(if_t ifp)
4092 if_ctx_t ctx = if_getsoftc(ifp);
4093 iflib_txq_t txq = ctx->ifc_txqs;
4097 ctx->ifc_flags |= IFC_QFLUSH;
4099 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4100 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4101 iflib_txq_check_drain(txq, 0);
4103 ctx->ifc_flags &= ~IFC_QFLUSH;
4107 * When ALTQ is enabled, this will also take care of purging the
4114 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4115 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4116 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
4119 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4121 if_ctx_t ctx = if_getsoftc(ifp);
4122 struct ifreq *ifr = (struct ifreq *)data;
4123 #if defined(INET) || defined(INET6)
4124 struct ifaddr *ifa = (struct ifaddr *)data;
4126 bool avoid_reset = FALSE;
4127 int err = 0, reinit = 0, bits;
4132 if (ifa->ifa_addr->sa_family == AF_INET)
4136 if (ifa->ifa_addr->sa_family == AF_INET6)
4140 ** Calling init results in link renegotiation,
4141 ** so we avoid doing it when possible.
4144 if_setflagbits(ifp, IFF_UP,0);
4145 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4148 if (!(if_getflags(ifp) & IFF_NOARP))
4149 arp_ifinit(ifp, ifa);
4152 err = ether_ioctl(ifp, command, data);
4156 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4160 bits = if_getdrvflags(ifp);
4161 /* stop the driver and free any clusters before proceeding */
4164 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4166 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4167 ctx->ifc_flags |= IFC_MULTISEG;
4169 ctx->ifc_flags &= ~IFC_MULTISEG;
4171 err = if_setmtu(ifp, ifr->ifr_mtu);
4173 iflib_init_locked(ctx);
4175 if_setdrvflags(ifp, bits);
4181 if (if_getflags(ifp) & IFF_UP) {
4182 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4183 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4184 (IFF_PROMISC | IFF_ALLMULTI)) {
4185 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4189 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4192 ctx->ifc_if_flags = if_getflags(ifp);
4197 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4199 IFDI_INTR_DISABLE(ctx);
4200 IFDI_MULTI_SET(ctx);
4201 IFDI_INTR_ENABLE(ctx);
4207 IFDI_MEDIA_SET(ctx);
4212 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4216 struct ifi2creq i2c;
4218 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4221 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4225 if (i2c.len > sizeof(i2c.data)) {
4230 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4231 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4239 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4242 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4244 setmask |= (mask & IFCAP_FLAGS);
4246 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4247 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4248 if ((mask & IFCAP_WOL) &&
4249 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4250 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4253 * want to ensure that traffic has stopped before we change any of the flags
4257 bits = if_getdrvflags(ifp);
4258 if (bits & IFF_DRV_RUNNING)
4261 if_togglecapenable(ifp, setmask);
4263 if (bits & IFF_DRV_RUNNING)
4264 iflib_init_locked(ctx);
4266 if_setdrvflags(ifp, bits);
4272 case SIOCGPRIVATE_0:
4276 err = IFDI_PRIV_IOCTL(ctx, command, data);
4280 err = ether_ioctl(ifp, command, data);
4289 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4291 if_ctx_t ctx = if_getsoftc(ifp);
4293 return (IFDI_GET_COUNTER(ctx, cnt));
4296 /*********************************************************************
4298 * OTHER FUNCTIONS EXPORTED TO THE STACK
4300 **********************************************************************/
4303 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4305 if_ctx_t ctx = if_getsoftc(ifp);
4307 if ((void *)ctx != arg)
4310 if ((vtag == 0) || (vtag > 4095))
4314 IFDI_VLAN_REGISTER(ctx, vtag);
4315 /* Re-init to load the changes */
4316 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4317 iflib_if_init_locked(ctx);
4322 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4324 if_ctx_t ctx = if_getsoftc(ifp);
4326 if ((void *)ctx != arg)
4329 if ((vtag == 0) || (vtag > 4095))
4333 IFDI_VLAN_UNREGISTER(ctx, vtag);
4334 /* Re-init to load the changes */
4335 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4336 iflib_if_init_locked(ctx);
4341 iflib_led_func(void *arg, int onoff)
4346 IFDI_LED_FUNC(ctx, onoff);
4350 /*********************************************************************
4352 * BUS FUNCTION DEFINITIONS
4354 **********************************************************************/
4357 iflib_device_probe(device_t dev)
4359 pci_vendor_info_t *ent;
4361 uint16_t pci_vendor_id, pci_device_id;
4362 uint16_t pci_subvendor_id, pci_subdevice_id;
4363 uint16_t pci_rev_id;
4364 if_shared_ctx_t sctx;
4366 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4369 pci_vendor_id = pci_get_vendor(dev);
4370 pci_device_id = pci_get_device(dev);
4371 pci_subvendor_id = pci_get_subvendor(dev);
4372 pci_subdevice_id = pci_get_subdevice(dev);
4373 pci_rev_id = pci_get_revid(dev);
4374 if (sctx->isc_parse_devinfo != NULL)
4375 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4377 ent = sctx->isc_vendor_info;
4378 while (ent->pvi_vendor_id != 0) {
4379 if (pci_vendor_id != ent->pvi_vendor_id) {
4383 if ((pci_device_id == ent->pvi_device_id) &&
4384 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4385 (ent->pvi_subvendor_id == 0)) &&
4386 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4387 (ent->pvi_subdevice_id == 0)) &&
4388 ((pci_rev_id == ent->pvi_rev_id) ||
4389 (ent->pvi_rev_id == 0))) {
4391 device_set_desc_copy(dev, ent->pvi_name);
4392 /* this needs to be changed to zero if the bus probing code
4393 * ever stops re-probing on best match because the sctx
4394 * may have its values over written by register calls
4395 * in subsequent probes
4397 return (BUS_PROBE_DEFAULT);
4405 iflib_reset_qvalues(if_ctx_t ctx)
4407 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4408 if_shared_ctx_t sctx = ctx->ifc_sctx;
4409 device_t dev = ctx->ifc_dev;
4412 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4413 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4415 * XXX sanity check that ntxd & nrxd are a power of 2
4417 if (ctx->ifc_sysctl_ntxqs != 0)
4418 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4419 if (ctx->ifc_sysctl_nrxqs != 0)
4420 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4422 for (i = 0; i < sctx->isc_ntxqs; i++) {
4423 if (ctx->ifc_sysctl_ntxds[i] != 0)
4424 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4426 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4429 for (i = 0; i < sctx->isc_nrxqs; i++) {
4430 if (ctx->ifc_sysctl_nrxds[i] != 0)
4431 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4433 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4436 for (i = 0; i < sctx->isc_nrxqs; i++) {
4437 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4438 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4439 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4440 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4442 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4443 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4444 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4445 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4449 for (i = 0; i < sctx->isc_ntxqs; i++) {
4450 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4451 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4452 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4453 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4455 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4456 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4457 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4458 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4464 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4469 if_softc_ctx_t scctx;
4475 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4478 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4479 device_set_softc(dev, ctx);
4480 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4483 ctx->ifc_sctx = sctx;
4485 ctx->ifc_softc = sc;
4487 if ((err = iflib_register(ctx)) != 0) {
4488 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4491 device_printf(dev, "iflib_register failed %d\n", err);
4494 iflib_add_device_sysctl_pre(ctx);
4496 scctx = &ctx->ifc_softc_ctx;
4499 iflib_reset_qvalues(ctx);
4501 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4503 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4506 _iflib_pre_assert(scctx);
4507 ctx->ifc_txrx = *scctx->isc_txrx;
4510 MPASS(scctx->isc_capabilities);
4511 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4512 MPASS(scctx->isc_tx_csum_flags);
4515 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4516 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4518 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4519 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4520 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4521 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4524 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4525 ctx->ifc_flags |= IFC_DMAR;
4526 #elif !(defined(__i386__) || defined(__amd64__))
4527 /* set unconditionally for !x86 */
4528 ctx->ifc_flags |= IFC_DMAR;
4531 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4532 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4534 /* XXX change for per-queue sizes */
4535 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4536 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4537 for (i = 0; i < sctx->isc_nrxqs; i++) {
4538 if (!powerof2(scctx->isc_nrxd[i])) {
4539 /* round down instead? */
4540 device_printf(dev, "# rx descriptors must be a power of 2\n");
4545 for (i = 0; i < sctx->isc_ntxqs; i++) {
4546 if (!powerof2(scctx->isc_ntxd[i])) {
4548 "# tx descriptors must be a power of 2");
4554 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4555 MAX_SINGLE_PACKET_FRACTION)
4556 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4557 MAX_SINGLE_PACKET_FRACTION);
4558 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4559 MAX_SINGLE_PACKET_FRACTION)
4560 scctx->isc_tx_tso_segments_max = max(1,
4561 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4563 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4564 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4566 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4569 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4572 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4573 * into account. In the worst case, each of these calls will
4574 * add another mbuf and, thus, the requirement for another DMA
4575 * segment. So for best performance, it doesn't make sense to
4576 * advertize a maximum of TSO segments that typically will
4577 * require defragmentation in iflib_encap().
4579 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4580 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4582 if (scctx->isc_rss_table_size == 0)
4583 scctx->isc_rss_table_size = 64;
4584 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4586 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4587 /* XXX format name */
4588 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4590 /* Set up cpu set. If it fails, use the set of all CPUs. */
4591 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4592 device_printf(dev, "Unable to fetch CPU list\n");
4593 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4595 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4598 ** Now setup MSI or MSI/X, should
4599 ** return us the number of supported
4600 ** vectors. (Will be 1 for MSI)
4602 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4603 msix = scctx->isc_vectors;
4604 } else if (scctx->isc_msix_bar != 0)
4606 * The simple fact that isc_msix_bar is not 0 does not mean we
4607 * we have a good value there that is known to work.
4609 msix = iflib_msix_init(ctx);
4611 scctx->isc_vectors = 1;
4612 scctx->isc_ntxqsets = 1;
4613 scctx->isc_nrxqsets = 1;
4614 scctx->isc_intr = IFLIB_INTR_LEGACY;
4617 /* Get memory for the station queues */
4618 if ((err = iflib_queues_alloc(ctx))) {
4619 device_printf(dev, "Unable to allocate queue memory\n");
4623 if ((err = iflib_qset_structures_setup(ctx)))
4627 * Group taskqueues aren't properly set up until SMP is started,
4628 * so we disable interrupts until we can handle them post
4631 * XXX: disabling interrupts doesn't actually work, at least for
4632 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4633 * we do null handling and depend on this not causing too large an
4636 IFDI_INTR_DISABLE(ctx);
4637 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4638 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4639 goto fail_intr_free;
4643 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4647 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4648 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4649 goto fail_intr_free;
4653 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4655 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4656 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4661 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4662 * This must appear after the call to ether_ifattach() because
4663 * ether_ifattach() sets if_hdrlen to the default value.
4665 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4666 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4668 if ((err = iflib_netmap_attach(ctx))) {
4669 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4674 NETDUMP_SET(ctx->ifc_ifp, iflib);
4676 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4677 iflib_add_device_sysctl_post(ctx);
4678 ctx->ifc_flags |= IFC_INIT_DONE;
4682 ether_ifdetach(ctx->ifc_ifp);
4684 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4685 pci_release_msi(ctx->ifc_dev);
4687 iflib_tx_structures_free(ctx);
4688 iflib_rx_structures_free(ctx);
4696 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4697 struct iflib_cloneattach_ctx *clctx)
4702 if_softc_ctx_t scctx;
4708 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4709 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4710 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4711 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4712 ctx->ifc_flags |= IFC_PSEUDO;
4714 ctx->ifc_sctx = sctx;
4715 ctx->ifc_softc = sc;
4718 if ((err = iflib_register(ctx)) != 0) {
4719 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4724 iflib_add_device_sysctl_pre(ctx);
4726 scctx = &ctx->ifc_softc_ctx;
4730 * XXX sanity check that ntxd & nrxd are a power of 2
4732 iflib_reset_qvalues(ctx);
4734 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4735 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4738 if (sctx->isc_flags & IFLIB_GEN_MAC)
4740 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4741 clctx->cc_params)) != 0) {
4742 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4745 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4746 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4747 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4750 MPASS(scctx->isc_capabilities);
4751 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4752 MPASS(scctx->isc_tx_csum_flags);
4755 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4756 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4758 ifp->if_flags |= IFF_NOGROUP;
4759 if (sctx->isc_flags & IFLIB_PSEUDO) {
4760 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4762 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4763 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4769 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4770 * This must appear after the call to ether_ifattach() because
4771 * ether_ifattach() sets if_hdrlen to the default value.
4773 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4774 if_setifheaderlen(ifp,
4775 sizeof(struct ether_vlan_header));
4777 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4778 iflib_add_device_sysctl_post(ctx);
4779 ctx->ifc_flags |= IFC_INIT_DONE;
4782 _iflib_pre_assert(scctx);
4783 ctx->ifc_txrx = *scctx->isc_txrx;
4785 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4786 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4787 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4788 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4790 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4791 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4793 /* XXX change for per-queue sizes */
4794 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4795 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4796 for (i = 0; i < sctx->isc_nrxqs; i++) {
4797 if (!powerof2(scctx->isc_nrxd[i])) {
4798 /* round down instead? */
4799 device_printf(dev, "# rx descriptors must be a power of 2\n");
4804 for (i = 0; i < sctx->isc_ntxqs; i++) {
4805 if (!powerof2(scctx->isc_ntxd[i])) {
4807 "# tx descriptors must be a power of 2");
4813 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4814 MAX_SINGLE_PACKET_FRACTION)
4815 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4816 MAX_SINGLE_PACKET_FRACTION);
4817 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4818 MAX_SINGLE_PACKET_FRACTION)
4819 scctx->isc_tx_tso_segments_max = max(1,
4820 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4822 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4823 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4825 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4828 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4831 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4832 * into account. In the worst case, each of these calls will
4833 * add another mbuf and, thus, the requirement for another DMA
4834 * segment. So for best performance, it doesn't make sense to
4835 * advertize a maximum of TSO segments that typically will
4836 * require defragmentation in iflib_encap().
4838 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4839 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4841 if (scctx->isc_rss_table_size == 0)
4842 scctx->isc_rss_table_size = 64;
4843 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4845 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4846 /* XXX format name */
4847 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4849 /* XXX --- can support > 1 -- but keep it simple for now */
4850 scctx->isc_intr = IFLIB_INTR_LEGACY;
4852 /* Get memory for the station queues */
4853 if ((err = iflib_queues_alloc(ctx))) {
4854 device_printf(dev, "Unable to allocate queue memory\n");
4858 if ((err = iflib_qset_structures_setup(ctx))) {
4859 device_printf(dev, "qset structure setup failed %d\n", err);
4864 * XXX What if anything do we want to do about interrupts?
4866 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4867 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4868 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4873 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4874 * This must appear after the call to ether_ifattach() because
4875 * ether_ifattach() sets if_hdrlen to the default value.
4877 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4878 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4880 /* XXX handle more than one queue */
4881 for (i = 0; i < scctx->isc_nrxqsets; i++)
4882 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4886 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4887 iflib_add_device_sysctl_post(ctx);
4888 ctx->ifc_flags |= IFC_INIT_DONE;
4891 ether_ifdetach(ctx->ifc_ifp);
4893 iflib_tx_structures_free(ctx);
4894 iflib_rx_structures_free(ctx);
4901 iflib_pseudo_deregister(if_ctx_t ctx)
4903 if_t ifp = ctx->ifc_ifp;
4907 struct taskqgroup *tqg;
4910 /* Unregister VLAN events */
4911 if (ctx->ifc_vlan_attach_event != NULL)
4912 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4913 if (ctx->ifc_vlan_detach_event != NULL)
4914 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4916 ether_ifdetach(ifp);
4917 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4918 CTX_LOCK_DESTROY(ctx);
4919 /* XXX drain any dependent tasks */
4920 tqg = qgroup_if_io_tqg;
4921 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4922 callout_drain(&txq->ift_timer);
4923 if (txq->ift_task.gt_uniq != NULL)
4924 taskqgroup_detach(tqg, &txq->ift_task);
4926 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4927 if (rxq->ifr_task.gt_uniq != NULL)
4928 taskqgroup_detach(tqg, &rxq->ifr_task);
4930 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4931 free(fl->ifl_rx_bitmap, M_IFLIB);
4933 tqg = qgroup_if_config_tqg;
4934 if (ctx->ifc_admin_task.gt_uniq != NULL)
4935 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4936 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4937 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4941 iflib_tx_structures_free(ctx);
4942 iflib_rx_structures_free(ctx);
4943 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4944 free(ctx->ifc_softc, M_IFLIB);
4950 iflib_device_attach(device_t dev)
4953 if_shared_ctx_t sctx;
4955 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4958 pci_enable_busmaster(dev);
4960 return (iflib_device_register(dev, NULL, sctx, &ctx));
4964 iflib_device_deregister(if_ctx_t ctx)
4966 if_t ifp = ctx->ifc_ifp;
4969 device_t dev = ctx->ifc_dev;
4971 struct taskqgroup *tqg;
4974 /* Make sure VLANS are not using driver */
4975 if (if_vlantrunkinuse(ifp)) {
4976 device_printf(dev,"Vlan in use, detach first\n");
4981 ctx->ifc_in_detach = 1;
4985 /* Unregister VLAN events */
4986 if (ctx->ifc_vlan_attach_event != NULL)
4987 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4988 if (ctx->ifc_vlan_detach_event != NULL)
4989 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4991 iflib_netmap_detach(ifp);
4992 ether_ifdetach(ifp);
4993 if (ctx->ifc_led_dev != NULL)
4994 led_destroy(ctx->ifc_led_dev);
4995 /* XXX drain any dependent tasks */
4996 tqg = qgroup_if_io_tqg;
4997 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4998 callout_drain(&txq->ift_timer);
4999 if (txq->ift_task.gt_uniq != NULL)
5000 taskqgroup_detach(tqg, &txq->ift_task);
5002 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5003 if (rxq->ifr_task.gt_uniq != NULL)
5004 taskqgroup_detach(tqg, &rxq->ifr_task);
5006 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5007 free(fl->ifl_rx_bitmap, M_IFLIB);
5010 tqg = qgroup_if_config_tqg;
5011 if (ctx->ifc_admin_task.gt_uniq != NULL)
5012 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5013 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5014 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5019 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5020 CTX_LOCK_DESTROY(ctx);
5021 device_set_softc(ctx->ifc_dev, NULL);
5022 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5023 pci_release_msi(dev);
5025 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5026 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5028 if (ctx->ifc_msix_mem != NULL) {
5029 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5030 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
5031 ctx->ifc_msix_mem = NULL;
5034 bus_generic_detach(dev);
5037 iflib_tx_structures_free(ctx);
5038 iflib_rx_structures_free(ctx);
5039 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5040 free(ctx->ifc_softc, M_IFLIB);
5047 iflib_device_detach(device_t dev)
5049 if_ctx_t ctx = device_get_softc(dev);
5051 return (iflib_device_deregister(ctx));
5055 iflib_device_suspend(device_t dev)
5057 if_ctx_t ctx = device_get_softc(dev);
5063 return bus_generic_suspend(dev);
5066 iflib_device_shutdown(device_t dev)
5068 if_ctx_t ctx = device_get_softc(dev);
5074 return bus_generic_suspend(dev);
5079 iflib_device_resume(device_t dev)
5081 if_ctx_t ctx = device_get_softc(dev);
5082 iflib_txq_t txq = ctx->ifc_txqs;
5086 iflib_init_locked(ctx);
5088 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5089 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5091 return (bus_generic_resume(dev));
5095 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5098 if_ctx_t ctx = device_get_softc(dev);
5101 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5108 iflib_device_iov_uninit(device_t dev)
5110 if_ctx_t ctx = device_get_softc(dev);
5113 IFDI_IOV_UNINIT(ctx);
5118 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5121 if_ctx_t ctx = device_get_softc(dev);
5124 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5130 /*********************************************************************
5132 * MODULE FUNCTION DEFINITIONS
5134 **********************************************************************/
5137 * - Start a fast taskqueue thread for each core
5138 * - Start a taskqueue for control operations
5141 iflib_module_init(void)
5147 iflib_module_event_handler(module_t mod, int what, void *arg)
5153 if ((err = iflib_module_init()) != 0)
5159 return (EOPNOTSUPP);
5165 /*********************************************************************
5167 * PUBLIC FUNCTION DEFINITIONS
5168 * ordered as in iflib.h
5170 **********************************************************************/
5174 _iflib_assert(if_shared_ctx_t sctx)
5176 MPASS(sctx->isc_tx_maxsize);
5177 MPASS(sctx->isc_tx_maxsegsize);
5179 MPASS(sctx->isc_rx_maxsize);
5180 MPASS(sctx->isc_rx_nsegments);
5181 MPASS(sctx->isc_rx_maxsegsize);
5183 MPASS(sctx->isc_nrxd_min[0]);
5184 MPASS(sctx->isc_nrxd_max[0]);
5185 MPASS(sctx->isc_nrxd_default[0]);
5186 MPASS(sctx->isc_ntxd_min[0]);
5187 MPASS(sctx->isc_ntxd_max[0]);
5188 MPASS(sctx->isc_ntxd_default[0]);
5192 _iflib_pre_assert(if_softc_ctx_t scctx)
5195 MPASS(scctx->isc_txrx->ift_txd_encap);
5196 MPASS(scctx->isc_txrx->ift_txd_flush);
5197 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5198 MPASS(scctx->isc_txrx->ift_rxd_available);
5199 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5200 MPASS(scctx->isc_txrx->ift_rxd_refill);
5201 MPASS(scctx->isc_txrx->ift_rxd_flush);
5205 iflib_register(if_ctx_t ctx)
5207 if_shared_ctx_t sctx = ctx->ifc_sctx;
5208 driver_t *driver = sctx->isc_driver;
5209 device_t dev = ctx->ifc_dev;
5212 _iflib_assert(sctx);
5215 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5216 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
5218 device_printf(dev, "can not allocate ifnet structure\n");
5223 * Initialize our context's device specific methods
5225 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5226 kobj_class_compile((kobj_class_t) driver);
5229 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5230 if_setsoftc(ifp, ctx);
5231 if_setdev(ifp, dev);
5232 if_setinitfn(ifp, iflib_if_init);
5233 if_setioctlfn(ifp, iflib_if_ioctl);
5235 if_setstartfn(ifp, iflib_altq_if_start);
5236 if_settransmitfn(ifp, iflib_altq_if_transmit);
5238 if_settransmitfn(ifp, iflib_if_transmit);
5240 if_setqflushfn(ifp, iflib_if_qflush);
5241 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5243 ctx->ifc_vlan_attach_event =
5244 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5245 EVENTHANDLER_PRI_FIRST);
5246 ctx->ifc_vlan_detach_event =
5247 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5248 EVENTHANDLER_PRI_FIRST);
5250 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5251 iflib_media_change, iflib_media_status);
5258 iflib_queues_alloc(if_ctx_t ctx)
5260 if_shared_ctx_t sctx = ctx->ifc_sctx;
5261 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5262 device_t dev = ctx->ifc_dev;
5263 int nrxqsets = scctx->isc_nrxqsets;
5264 int ntxqsets = scctx->isc_ntxqsets;
5267 iflib_fl_t fl = NULL;
5268 int i, j, cpu, err, txconf, rxconf;
5269 iflib_dma_info_t ifdip;
5270 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5271 uint32_t *txqsizes = scctx->isc_txqsizes;
5272 uint8_t nrxqs = sctx->isc_nrxqs;
5273 uint8_t ntxqs = sctx->isc_ntxqs;
5274 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5278 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5279 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5281 /* Allocate the TX ring struct memory */
5282 if (!(ctx->ifc_txqs =
5283 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5284 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5285 device_printf(dev, "Unable to allocate TX ring memory\n");
5290 /* Now allocate the RX */
5291 if (!(ctx->ifc_rxqs =
5292 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5293 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5294 device_printf(dev, "Unable to allocate RX ring memory\n");
5299 txq = ctx->ifc_txqs;
5300 rxq = ctx->ifc_rxqs;
5303 * XXX handle allocation failure
5305 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5306 /* Set up some basics */
5308 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5309 device_printf(dev, "failed to allocate iflib_dma_info\n");
5313 txq->ift_ifdi = ifdip;
5314 for (j = 0; j < ntxqs; j++, ifdip++) {
5315 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5316 device_printf(dev, "Unable to allocate Descriptor memory\n");
5320 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5321 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5325 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5326 txq->ift_br_offset = 1;
5328 txq->ift_br_offset = 0;
5331 txq->ift_timer.c_cpu = cpu;
5333 if (iflib_txsd_alloc(txq)) {
5334 device_printf(dev, "Critical Failure setting up TX buffers\n");
5339 /* Initialize the TX lock */
5340 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5341 device_get_nameunit(dev), txq->ift_id);
5342 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5343 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5345 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5346 device_get_nameunit(dev), txq->ift_id);
5348 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5349 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5351 /* XXX free any allocated rings */
5352 device_printf(dev, "Unable to allocate buf_ring\n");
5357 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5358 /* Set up some basics */
5360 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5361 device_printf(dev, "failed to allocate iflib_dma_info\n");
5366 rxq->ifr_ifdi = ifdip;
5367 /* XXX this needs to be changed if #rx queues != #tx queues */
5368 rxq->ifr_ntxqirq = 1;
5369 rxq->ifr_txqid[0] = i;
5370 for (j = 0; j < nrxqs; j++, ifdip++) {
5371 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5372 device_printf(dev, "Unable to allocate Descriptor memory\n");
5376 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5380 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5381 rxq->ifr_fl_offset = 1;
5383 rxq->ifr_fl_offset = 0;
5385 rxq->ifr_nfl = nfree_lists;
5387 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5388 device_printf(dev, "Unable to allocate free list memory\n");
5393 for (j = 0; j < nfree_lists; j++) {
5394 fl[j].ifl_rxq = rxq;
5396 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5397 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5399 /* Allocate receive buffers for the ring*/
5400 if (iflib_rxsd_alloc(rxq)) {
5402 "Critical Failure setting up receive buffers\n");
5407 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5408 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
5412 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5413 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5414 for (i = 0; i < ntxqsets; i++) {
5415 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5417 for (j = 0; j < ntxqs; j++, di++) {
5418 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5419 paddrs[i*ntxqs + j] = di->idi_paddr;
5422 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5423 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5424 iflib_tx_structures_free(ctx);
5425 free(vaddrs, M_IFLIB);
5426 free(paddrs, M_IFLIB);
5429 free(vaddrs, M_IFLIB);
5430 free(paddrs, M_IFLIB);
5433 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5434 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5435 for (i = 0; i < nrxqsets; i++) {
5436 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5438 for (j = 0; j < nrxqs; j++, di++) {
5439 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5440 paddrs[i*nrxqs + j] = di->idi_paddr;
5443 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5444 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5445 iflib_tx_structures_free(ctx);
5446 free(vaddrs, M_IFLIB);
5447 free(paddrs, M_IFLIB);
5450 free(vaddrs, M_IFLIB);
5451 free(paddrs, M_IFLIB);
5455 /* XXX handle allocation failure changes */
5459 if (ctx->ifc_rxqs != NULL)
5460 free(ctx->ifc_rxqs, M_IFLIB);
5461 ctx->ifc_rxqs = NULL;
5462 if (ctx->ifc_txqs != NULL)
5463 free(ctx->ifc_txqs, M_IFLIB);
5464 ctx->ifc_txqs = NULL;
5470 iflib_tx_structures_setup(if_ctx_t ctx)
5472 iflib_txq_t txq = ctx->ifc_txqs;
5475 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5476 iflib_txq_setup(txq);
5482 iflib_tx_structures_free(if_ctx_t ctx)
5484 iflib_txq_t txq = ctx->ifc_txqs;
5487 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5488 iflib_txq_destroy(txq);
5489 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
5490 iflib_dma_free(&txq->ift_ifdi[j]);
5492 free(ctx->ifc_txqs, M_IFLIB);
5493 ctx->ifc_txqs = NULL;
5494 IFDI_QUEUES_FREE(ctx);
5497 /*********************************************************************
5499 * Initialize all receive rings.
5501 **********************************************************************/
5503 iflib_rx_structures_setup(if_ctx_t ctx)
5505 iflib_rxq_t rxq = ctx->ifc_rxqs;
5507 #if defined(INET6) || defined(INET)
5511 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5512 #if defined(INET6) || defined(INET)
5513 tcp_lro_free(&rxq->ifr_lc);
5514 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5515 TCP_LRO_ENTRIES, min(1024,
5516 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5517 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5520 rxq->ifr_lro_enabled = TRUE;
5522 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5525 #if defined(INET6) || defined(INET)
5528 * Free RX software descriptors allocated so far, we will only handle
5529 * the rings that completed, the failing case will have
5530 * cleaned up for itself. 'q' failed, so its the terminus.
5532 rxq = ctx->ifc_rxqs;
5533 for (i = 0; i < q; ++i, rxq++) {
5534 iflib_rx_sds_free(rxq);
5535 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5541 /*********************************************************************
5543 * Free all receive rings.
5545 **********************************************************************/
5547 iflib_rx_structures_free(if_ctx_t ctx)
5549 iflib_rxq_t rxq = ctx->ifc_rxqs;
5551 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5552 iflib_rx_sds_free(rxq);
5557 iflib_qset_structures_setup(if_ctx_t ctx)
5562 * It is expected that the caller takes care of freeing queues if this
5565 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5566 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5570 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5571 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5577 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5578 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5581 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5586 find_nth(if_ctx_t ctx, int qid)
5589 int i, cpuid, eqid, count;
5591 CPU_COPY(&ctx->ifc_cpus, &cpus);
5592 count = CPU_COUNT(&cpus);
5594 /* clear up to the qid'th bit */
5595 for (i = 0; i < eqid; i++) {
5596 cpuid = CPU_FFS(&cpus);
5598 CPU_CLR(cpuid-1, &cpus);
5600 cpuid = CPU_FFS(&cpus);
5606 extern struct cpu_group *cpu_top; /* CPU topology */
5609 find_child_with_core(int cpu, struct cpu_group *grp)
5613 if (grp->cg_children == 0)
5616 MPASS(grp->cg_child);
5617 for (i = 0; i < grp->cg_children; i++) {
5618 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5626 * Find the nth "close" core to the specified core
5627 * "close" is defined as the deepest level that shares
5628 * at least an L2 cache. With threads, this will be
5629 * threads on the same core. If the sahred cache is L3
5630 * or higher, simply returns the same core.
5633 find_close_core(int cpu, int core_offset)
5635 struct cpu_group *grp;
5644 while ((i = find_child_with_core(cpu, grp)) != -1) {
5645 /* If the child only has one cpu, don't descend */
5646 if (grp->cg_child[i].cg_count <= 1)
5648 grp = &grp->cg_child[i];
5651 /* If they don't share at least an L2 cache, use the same CPU */
5652 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5656 CPU_COPY(&grp->cg_mask, &cs);
5658 /* Add the selected CPU offset to core offset. */
5659 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5660 if (fcpu - 1 == cpu)
5662 CPU_CLR(fcpu - 1, &cs);
5668 CPU_COPY(&grp->cg_mask, &cs);
5669 for (i = core_offset % grp->cg_count; i > 0; i--) {
5670 MPASS(CPU_FFS(&cs));
5671 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5673 MPASS(CPU_FFS(&cs));
5674 return CPU_FFS(&cs) - 1;
5678 find_close_core(int cpu, int core_offset __unused)
5685 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5689 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5690 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5691 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5693 case IFLIB_INTR_RXTX:
5694 /* RX queues get the specified core */
5695 return qid / CPU_COUNT(&ctx->ifc_cpus);
5701 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5702 #define find_close_core(cpuid, tid) CPU_FIRST()
5703 #define find_nth(ctx, gid) CPU_FIRST()
5706 /* Just to avoid copy/paste */
5708 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5709 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5714 cpuid = find_nth(ctx, qid);
5715 tid = get_core_offset(ctx, type, qid);
5717 cpuid = find_close_core(cpuid, tid);
5718 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5720 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5724 if (cpuid > ctx->ifc_cpuid_highest)
5725 ctx->ifc_cpuid_highest = cpuid;
5731 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5732 iflib_intr_type_t type, driver_filter_t *filter,
5733 void *filter_arg, int qid, const char *name)
5735 struct grouptask *gtask;
5736 struct taskqgroup *tqg;
5737 iflib_filter_info_t info;
5740 driver_filter_t *intr_fast;
5743 info = &ctx->ifc_filter_info;
5747 /* XXX merge tx/rx for netmap? */
5749 q = &ctx->ifc_txqs[qid];
5750 info = &ctx->ifc_txqs[qid].ift_filter_info;
5751 gtask = &ctx->ifc_txqs[qid].ift_task;
5752 tqg = qgroup_if_io_tqg;
5754 intr_fast = iflib_fast_intr;
5755 GROUPTASK_INIT(gtask, 0, fn, q);
5756 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5759 q = &ctx->ifc_rxqs[qid];
5760 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5761 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5762 tqg = qgroup_if_io_tqg;
5764 intr_fast = iflib_fast_intr;
5765 GROUPTASK_INIT(gtask, 0, fn, q);
5767 case IFLIB_INTR_RXTX:
5768 q = &ctx->ifc_rxqs[qid];
5769 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5770 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5771 tqg = qgroup_if_io_tqg;
5773 intr_fast = iflib_fast_intr_rxtx;
5774 GROUPTASK_INIT(gtask, 0, fn, q);
5776 case IFLIB_INTR_ADMIN:
5779 info = &ctx->ifc_filter_info;
5780 gtask = &ctx->ifc_admin_task;
5781 tqg = qgroup_if_config_tqg;
5782 fn = _task_fn_admin;
5783 intr_fast = iflib_fast_intr_ctx;
5786 panic("unknown net intr type");
5789 info->ifi_filter = filter;
5790 info->ifi_filter_arg = filter_arg;
5791 info->ifi_task = gtask;
5794 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5796 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5799 if (type == IFLIB_INTR_ADMIN)
5803 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5807 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5814 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5816 struct grouptask *gtask;
5817 struct taskqgroup *tqg;
5825 q = &ctx->ifc_txqs[qid];
5826 gtask = &ctx->ifc_txqs[qid].ift_task;
5827 tqg = qgroup_if_io_tqg;
5830 irq_num = rman_get_start(irq->ii_res);
5833 q = &ctx->ifc_rxqs[qid];
5834 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5835 tqg = qgroup_if_io_tqg;
5838 irq_num = rman_get_start(irq->ii_res);
5840 case IFLIB_INTR_IOV:
5842 gtask = &ctx->ifc_vflr_task;
5843 tqg = qgroup_if_config_tqg;
5847 panic("unknown net intr type");
5849 GROUPTASK_INIT(gtask, 0, fn, q);
5850 if (irq_num != -1) {
5851 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5853 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5856 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5861 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5864 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5867 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5871 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5873 iflib_txq_t txq = ctx->ifc_txqs;
5874 iflib_rxq_t rxq = ctx->ifc_rxqs;
5875 if_irq_t irq = &ctx->ifc_legacy_irq;
5876 iflib_filter_info_t info;
5877 struct grouptask *gtask;
5878 struct taskqgroup *tqg;
5884 q = &ctx->ifc_rxqs[0];
5885 info = &rxq[0].ifr_filter_info;
5886 gtask = &rxq[0].ifr_task;
5887 tqg = qgroup_if_io_tqg;
5888 tqrid = irq->ii_rid = *rid;
5891 ctx->ifc_flags |= IFC_LEGACY;
5892 info->ifi_filter = filter;
5893 info->ifi_filter_arg = filter_arg;
5894 info->ifi_task = gtask;
5895 info->ifi_ctx = ctx;
5897 /* We allocate a single interrupt resource */
5898 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5900 GROUPTASK_INIT(gtask, 0, fn, q);
5901 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5903 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5904 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5909 iflib_led_create(if_ctx_t ctx)
5912 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5913 device_get_nameunit(ctx->ifc_dev));
5917 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5920 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5924 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5927 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5931 iflib_admin_intr_deferred(if_ctx_t ctx)
5934 struct grouptask *gtask;
5936 gtask = &ctx->ifc_admin_task;
5937 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5940 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5944 iflib_iov_intr_deferred(if_ctx_t ctx)
5947 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5951 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5954 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5958 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5962 GROUPTASK_INIT(gtask, 0, fn, ctx);
5963 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5967 iflib_config_gtask_deinit(struct grouptask *gtask)
5970 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5974 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5976 if_t ifp = ctx->ifc_ifp;
5977 iflib_txq_t txq = ctx->ifc_txqs;
5979 if_setbaudrate(ifp, baudrate);
5980 if (baudrate >= IF_Gbps(10)) {
5982 ctx->ifc_flags |= IFC_PREFETCH;
5985 /* If link down, disable watchdog */
5986 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5987 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5988 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5990 ctx->ifc_link_state = link_state;
5991 if_link_state_change(ifp, link_state);
5995 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5999 int credits_pre = txq->ift_cidx_processed;
6002 if (ctx->isc_txd_credits_update == NULL)
6005 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6008 txq->ift_processed += credits;
6009 txq->ift_cidx_processed += credits;
6011 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6012 if (txq->ift_cidx_processed >= txq->ift_size)
6013 txq->ift_cidx_processed -= txq->ift_size;
6018 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6021 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6026 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6027 const char *description, if_int_delay_info_t info,
6028 int offset, int value)
6030 info->iidi_ctx = ctx;
6031 info->iidi_offset = offset;
6032 info->iidi_value = value;
6033 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6034 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6035 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6036 info, 0, iflib_sysctl_int_delay, "I", description);
6040 iflib_ctx_lock_get(if_ctx_t ctx)
6043 return (&ctx->ifc_ctx_sx);
6047 iflib_msix_init(if_ctx_t ctx)
6049 device_t dev = ctx->ifc_dev;
6050 if_shared_ctx_t sctx = ctx->ifc_sctx;
6051 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6052 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
6053 int iflib_num_tx_queues, iflib_num_rx_queues;
6054 int err, admincnt, bar;
6056 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6057 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6059 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6061 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6062 admincnt = sctx->isc_admin_intrcnt;
6063 /* Override by tuneable */
6064 if (scctx->isc_disable_msix)
6068 * bar == -1 => "trust me I know what I'm doing"
6069 * Some drivers are for hardware that is so shoddily
6070 * documented that no one knows which bars are which
6071 * so the developer has to map all bars. This hack
6072 * allows shoddy garbage to use msix in this framework.
6075 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6076 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6077 if (ctx->ifc_msix_mem == NULL) {
6078 /* May not be enabled */
6079 device_printf(dev, "Unable to map MSIX table \n");
6083 /* First try MSI/X */
6084 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
6085 device_printf(dev, "System has MSIX disabled \n");
6086 bus_release_resource(dev, SYS_RES_MEMORY,
6087 bar, ctx->ifc_msix_mem);
6088 ctx->ifc_msix_mem = NULL;
6092 /* use only 1 qset in debug mode */
6093 queuemsgs = min(msgs - admincnt, 1);
6095 queuemsgs = msgs - admincnt;
6098 queues = imin(queuemsgs, rss_getnumbuckets());
6102 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6103 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
6104 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6106 /* If we're doing RSS, clamp at the number of RSS buckets */
6107 if (queues > rss_getnumbuckets())
6108 queues = rss_getnumbuckets();
6110 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6111 rx_queues = iflib_num_rx_queues;
6115 if (rx_queues > scctx->isc_nrxqsets)
6116 rx_queues = scctx->isc_nrxqsets;
6119 * We want this to be all logical CPUs by default
6121 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6122 tx_queues = iflib_num_tx_queues;
6124 tx_queues = mp_ncpus;
6126 if (tx_queues > scctx->isc_ntxqsets)
6127 tx_queues = scctx->isc_ntxqsets;
6129 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6131 if (tx_queues != rx_queues)
6132 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6133 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6135 tx_queues = min(rx_queues, tx_queues);
6136 rx_queues = min(rx_queues, tx_queues);
6139 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
6141 vectors = rx_queues + admincnt;
6142 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6144 "Using MSIX interrupts with %d vectors\n", vectors);
6145 scctx->isc_vectors = vectors;
6146 scctx->isc_nrxqsets = rx_queues;
6147 scctx->isc_ntxqsets = tx_queues;
6148 scctx->isc_intr = IFLIB_INTR_MSIX;
6152 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
6153 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6155 ctx->ifc_msix_mem = NULL;
6158 vectors = pci_msi_count(dev);
6159 scctx->isc_nrxqsets = 1;
6160 scctx->isc_ntxqsets = 1;
6161 scctx->isc_vectors = vectors;
6162 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6163 device_printf(dev,"Using an MSI interrupt\n");
6164 scctx->isc_intr = IFLIB_INTR_MSI;
6166 scctx->isc_vectors = 1;
6167 device_printf(dev,"Using a Legacy interrupt\n");
6168 scctx->isc_intr = IFLIB_INTR_LEGACY;
6174 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6177 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6180 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6182 const char *ring_state = "UNKNOWN";
6185 rc = sysctl_wire_old_buffer(req, 0);
6189 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6194 ring_state = ring_states[state[3]];
6196 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6197 state[0], state[1], state[2], ring_state);
6198 rc = sbuf_finish(sb);
6203 enum iflib_ndesc_handler {
6209 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6211 if_ctx_t ctx = (void *)arg1;
6212 enum iflib_ndesc_handler type = arg2;
6213 char buf[256] = {0};
6218 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6222 case IFLIB_NTXD_HANDLER:
6223 ndesc = ctx->ifc_sysctl_ntxds;
6225 nqs = ctx->ifc_sctx->isc_ntxqs;
6227 case IFLIB_NRXD_HANDLER:
6228 ndesc = ctx->ifc_sysctl_nrxds;
6230 nqs = ctx->ifc_sctx->isc_nrxqs;
6233 panic("unhandled type");
6238 for (i=0; i<8; i++) {
6243 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6246 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6247 if (rc || req->newptr == NULL)
6250 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6251 i++, p = strsep(&next, " ,")) {
6252 ndesc[i] = strtoul(p, NULL, 10);
6258 #define NAME_BUFLEN 32
6260 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6262 device_t dev = iflib_get_dev(ctx);
6263 struct sysctl_oid_list *child, *oid_list;
6264 struct sysctl_ctx_list *ctx_list;
6265 struct sysctl_oid *node;
6267 ctx_list = device_get_sysctl_ctx(dev);
6268 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6269 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6270 CTLFLAG_RD, NULL, "IFLIB fields");
6271 oid_list = SYSCTL_CHILDREN(node);
6273 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6274 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6277 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6278 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6279 "# of txqs to use, 0 => use default #");
6280 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6281 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6282 "# of rxqs to use, 0 => use default #");
6283 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6284 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6285 "permit #txq != #rxq");
6286 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6287 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6288 "disable MSIX (default 0)");
6289 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6290 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6291 "set the rx budget");
6292 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6293 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6294 "cause tx to abdicate instead of running to completion");
6296 /* XXX change for per-queue sizes */
6297 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6298 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6299 mp_ndesc_handler, "A",
6300 "list of # of tx descriptors to use, 0 = use default #");
6301 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6302 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6303 mp_ndesc_handler, "A",
6304 "list of # of rx descriptors to use, 0 = use default #");
6308 iflib_add_device_sysctl_post(if_ctx_t ctx)
6310 if_shared_ctx_t sctx = ctx->ifc_sctx;
6311 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6312 device_t dev = iflib_get_dev(ctx);
6313 struct sysctl_oid_list *child;
6314 struct sysctl_ctx_list *ctx_list;
6319 char namebuf[NAME_BUFLEN];
6321 struct sysctl_oid *queue_node, *fl_node, *node;
6322 struct sysctl_oid_list *queue_list, *fl_list;
6323 ctx_list = device_get_sysctl_ctx(dev);
6325 node = ctx->ifc_sysctl_node;
6326 child = SYSCTL_CHILDREN(node);
6328 if (scctx->isc_ntxqsets > 100)
6330 else if (scctx->isc_ntxqsets > 10)
6334 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6335 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6336 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6337 CTLFLAG_RD, NULL, "Queue Name");
6338 queue_list = SYSCTL_CHILDREN(queue_node);
6340 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6342 &txq->ift_dequeued, "total mbufs freed");
6343 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6345 &txq->ift_enqueued, "total mbufs enqueued");
6347 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6349 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6350 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6352 &txq->ift_pullups, "# of times m_pullup was called");
6353 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6355 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6356 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6358 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6359 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6361 &txq->ift_map_failed, "# of times dma map failed");
6362 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6364 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6365 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6367 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6368 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6370 &txq->ift_pidx, 1, "Producer Index");
6371 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6373 &txq->ift_cidx, 1, "Consumer Index");
6374 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6376 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6377 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6379 &txq->ift_in_use, 1, "descriptors in use");
6380 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6382 &txq->ift_processed, "descriptors procesed for clean");
6383 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6385 &txq->ift_cleaned, "total cleaned");
6386 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6387 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6388 0, mp_ring_state_handler, "A", "soft ring state");
6389 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6390 CTLFLAG_RD, &txq->ift_br->enqueues,
6391 "# of enqueues to the mp_ring for this queue");
6392 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6393 CTLFLAG_RD, &txq->ift_br->drops,
6394 "# of drops in the mp_ring for this queue");
6395 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6396 CTLFLAG_RD, &txq->ift_br->starts,
6397 "# of normal consumer starts in the mp_ring for this queue");
6398 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6399 CTLFLAG_RD, &txq->ift_br->stalls,
6400 "# of consumer stalls in the mp_ring for this queue");
6401 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6402 CTLFLAG_RD, &txq->ift_br->restarts,
6403 "# of consumer restarts in the mp_ring for this queue");
6404 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6405 CTLFLAG_RD, &txq->ift_br->abdications,
6406 "# of consumer abdications in the mp_ring for this queue");
6409 if (scctx->isc_nrxqsets > 100)
6411 else if (scctx->isc_nrxqsets > 10)
6415 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6416 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6417 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6418 CTLFLAG_RD, NULL, "Queue Name");
6419 queue_list = SYSCTL_CHILDREN(queue_node);
6420 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6421 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6423 &rxq->ifr_cq_pidx, 1, "Producer Index");
6424 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6426 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6429 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6430 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6431 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6432 CTLFLAG_RD, NULL, "freelist Name");
6433 fl_list = SYSCTL_CHILDREN(fl_node);
6434 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6436 &fl->ifl_pidx, 1, "Producer Index");
6437 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6439 &fl->ifl_cidx, 1, "Consumer Index");
6440 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6442 &fl->ifl_credits, 1, "credits available");
6444 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6446 &fl->ifl_m_enqueued, "mbufs allocated");
6447 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6449 &fl->ifl_m_dequeued, "mbufs freed");
6450 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6452 &fl->ifl_cl_enqueued, "clusters allocated");
6453 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6455 &fl->ifl_cl_dequeued, "clusters freed");
6463 #ifndef __NO_STRICT_ALIGNMENT
6464 static struct mbuf *
6465 iflib_fixup_rx(struct mbuf *m)
6469 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6470 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6471 m->m_data += ETHER_HDR_LEN;
6474 MGETHDR(n, M_NOWAIT, MT_DATA);
6479 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6480 m->m_data += ETHER_HDR_LEN;
6481 m->m_len -= ETHER_HDR_LEN;
6482 n->m_len = ETHER_HDR_LEN;
6483 M_MOVE_PKTHDR(n, m);
6492 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6496 ctx = if_getsoftc(ifp);
6498 *nrxr = NRXQSETS(ctx);
6499 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6500 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6505 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6508 if_softc_ctx_t scctx;
6513 ctx = if_getsoftc(ifp);
6514 scctx = &ctx->ifc_softc_ctx;
6518 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6519 rxq = &ctx->ifc_rxqs[i];
6520 for (j = 0; j < rxq->ifr_nfl; j++) {
6522 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6525 iflib_no_tx_batch = 1;
6533 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6539 ctx = if_getsoftc(ifp);
6540 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6544 txq = &ctx->ifc_txqs[0];
6545 error = iflib_encap(txq, &m);
6547 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6552 iflib_netdump_poll(struct ifnet *ifp, int count)
6555 if_softc_ctx_t scctx;
6559 ctx = if_getsoftc(ifp);
6560 scctx = &ctx->ifc_softc_ctx;
6562 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6566 txq = &ctx->ifc_txqs[0];
6567 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6569 for (i = 0; i < scctx->isc_nrxqsets; i++)
6570 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6573 #endif /* NETDUMP */