2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
212 eventhandler_tag ifc_vlan_attach_event;
213 eventhandler_tag ifc_vlan_detach_event;
214 struct ether_addr ifc_mac;
218 iflib_get_softc(if_ctx_t ctx)
221 return (ctx->ifc_softc);
225 iflib_get_dev(if_ctx_t ctx)
228 return (ctx->ifc_dev);
232 iflib_get_ifp(if_ctx_t ctx)
235 return (ctx->ifc_ifp);
239 iflib_get_media(if_ctx_t ctx)
242 return (ctx->ifc_mediap);
246 iflib_get_flags(if_ctx_t ctx)
248 return (ctx->ifc_flags);
252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
259 iflib_get_softc_ctx(if_ctx_t ctx)
262 return (&ctx->ifc_softc_ctx);
266 iflib_get_sctx(if_ctx_t ctx)
269 return (ctx->ifc_sctx);
272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
289 struct mbuf **ifsd_m; /* pkthdr mbufs */
292 /* magic number that should be high enough for any hardware */
293 #define IFLIB_MAX_TX_SEGS 128
294 #define IFLIB_RX_COPY_THRESH 128
295 #define IFLIB_MAX_RX_REFRESH 32
296 /* The minimum descriptors per second before we start coalescing */
297 #define IFLIB_MIN_DESC_SEC 16384
298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
299 #define IFLIB_QUEUE_IDLE 0
300 #define IFLIB_QUEUE_HUNG 1
301 #define IFLIB_QUEUE_WORKING 2
302 /* maximum number of txqs that can share an rx interrupt */
303 #define IFLIB_MAX_TX_SHARED_INTR 4
305 /* this should really scale with ring size - this is a fairly arbitrary value */
306 #define TX_BATCH_SIZE 32
308 #define IFLIB_RESTART_BUDGET 8
310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
317 qidx_t ift_cidx_processed;
320 uint8_t ift_br_offset;
321 uint16_t ift_npending;
322 uint16_t ift_db_pending;
323 uint16_t ift_rs_pending;
325 uint8_t ift_txd_size[8];
326 uint64_t ift_processed;
327 uint64_t ift_cleaned;
328 uint64_t ift_cleaned_prev;
330 uint64_t ift_enqueued;
331 uint64_t ift_dequeued;
333 uint64_t ift_no_tx_dma_setup;
334 uint64_t ift_no_desc_avail;
335 uint64_t ift_mbuf_defrag_failed;
336 uint64_t ift_mbuf_defrag;
337 uint64_t ift_map_failed;
338 uint64_t ift_txd_encap_efbig;
339 uint64_t ift_pullups;
340 uint64_t ift_last_timer_tick;
343 struct mtx ift_db_mtx;
345 /* constant values */
347 struct ifmp_ring *ift_br;
348 struct grouptask ift_task;
351 struct callout ift_timer;
353 if_txsd_vec_t ift_sds;
356 uint8_t ift_update_freq;
357 struct iflib_filter_info ift_filter_info;
358 bus_dma_tag_t ift_buf_tag;
359 bus_dma_tag_t ift_tso_buf_tag;
360 iflib_dma_info_t ift_ifdi;
361 #define MTX_NAME_LEN 32
362 char ift_mtx_name[MTX_NAME_LEN];
363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
364 #ifdef IFLIB_DIAGNOSTICS
365 uint64_t ift_cpu_exec_count[256];
367 } __aligned(CACHE_LINE_SIZE);
374 uint8_t ifl_rxd_size;
376 uint64_t ifl_m_enqueued;
377 uint64_t ifl_m_dequeued;
378 uint64_t ifl_cl_enqueued;
379 uint64_t ifl_cl_dequeued;
382 bitstr_t *ifl_rx_bitmap;
386 uint16_t ifl_buf_size;
389 iflib_rxsd_array_t ifl_sds;
392 bus_dma_tag_t ifl_buf_tag;
393 iflib_dma_info_t ifl_ifdi;
394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 } __aligned(CACHE_LINE_SIZE);
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
406 else if (pidx < cidx)
407 used = size - cidx + pidx;
408 else if (gen == 0 && pidx == cidx)
410 else if (gen == 1 && pidx == cidx)
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
420 #define IDXDIFF(head, tail, wrap) \
421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
427 struct pfil_head *pfil;
429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
430 * the command queue consumer index. Otherwise it's unused.
436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
437 uint8_t ifr_fl_offset;
438 struct lro_ctrl ifr_lc;
439 struct grouptask ifr_task;
440 struct callout ifr_watchdog;
441 struct iflib_filter_info ifr_filter_info;
442 iflib_dma_info_t ifr_ifdi;
444 /* dynamically allocate if any drivers need a value substantially larger than this */
445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
446 #ifdef IFLIB_DIAGNOSTICS
447 uint64_t ifr_cpu_exec_count[256];
449 } __aligned(CACHE_LINE_SIZE);
451 typedef struct if_rxsd {
456 /* multiple of word size */
458 #define PKT_INFO_SIZE 6
459 #define RXD_INFO_SIZE 5
460 #define PKT_TYPE uint64_t
462 #define PKT_INFO_SIZE 11
463 #define RXD_INFO_SIZE 8
464 #define PKT_TYPE uint32_t
466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
469 typedef struct if_pkt_info_pad {
470 PKT_TYPE pkt_val[PKT_INFO_SIZE];
471 } *if_pkt_info_pad_t;
472 typedef struct if_rxd_info_pad {
473 PKT_TYPE rxd_val[RXD_INFO_SIZE];
474 } *if_rxd_info_pad_t;
476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
481 pkt_info_zero(if_pkt_info_t pi)
483 if_pkt_info_pad_t pi_pad;
485 pi_pad = (if_pkt_info_pad_t)pi;
486 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
487 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
489 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
490 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
494 static device_method_t iflib_pseudo_methods[] = {
495 DEVMETHOD(device_attach, noop_attach),
496 DEVMETHOD(device_detach, iflib_pseudo_detach),
500 driver_t iflib_pseudodriver = {
501 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
505 rxd_info_zero(if_rxd_info_t ri)
507 if_rxd_info_pad_t ri_pad;
510 ri_pad = (if_rxd_info_pad_t)ri;
511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
512 ri_pad->rxd_val[i] = 0;
513 ri_pad->rxd_val[i+1] = 0;
514 ri_pad->rxd_val[i+2] = 0;
515 ri_pad->rxd_val[i+3] = 0;
518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
523 * Only allow a single packet to take up most 1/nth of the tx ring
525 #define MAX_SINGLE_PACKET_FRACTION 12
526 #define IF_BAD_DMA (bus_addr_t)-1
528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
530 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
535 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
540 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
541 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
544 iflib_set_detach(if_ctx_t ctx)
547 ctx->ifc_flags |= IFC_IN_DETACH;
551 /* Our boot-time initialization hook */
552 static int iflib_module_event_handler(module_t, int, void *);
554 static moduledata_t iflib_moduledata = {
556 iflib_module_event_handler,
560 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
561 MODULE_VERSION(iflib, 1);
563 MODULE_DEPEND(iflib, pci, 1, 1, 1);
564 MODULE_DEPEND(iflib, ether, 1, 1, 1);
566 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
567 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
569 #ifndef IFLIB_DEBUG_COUNTERS
571 #define IFLIB_DEBUG_COUNTERS 1
573 #define IFLIB_DEBUG_COUNTERS 0
574 #endif /* !INVARIANTS */
577 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
578 "iflib driver parameters");
581 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
583 static int iflib_min_tx_latency = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
585 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
586 static int iflib_no_tx_batch = 0;
587 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
588 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
591 #if IFLIB_DEBUG_COUNTERS
593 static int iflib_tx_seen;
594 static int iflib_tx_sent;
595 static int iflib_tx_encap;
596 static int iflib_rx_allocs;
597 static int iflib_fl_refills;
598 static int iflib_fl_refills_large;
599 static int iflib_tx_frees;
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
602 &iflib_tx_seen, 0, "# TX mbufs seen");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
604 &iflib_tx_sent, 0, "# TX mbufs sent");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
606 &iflib_tx_encap, 0, "# TX mbufs encapped");
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
608 &iflib_tx_frees, 0, "# TX frees");
609 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
610 &iflib_rx_allocs, 0, "# RX allocations");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
612 &iflib_fl_refills, 0, "# refills");
613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
614 &iflib_fl_refills_large, 0, "# large refills");
617 static int iflib_txq_drain_flushing;
618 static int iflib_txq_drain_oactive;
619 static int iflib_txq_drain_notready;
621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
622 &iflib_txq_drain_flushing, 0, "# drain flushes");
623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
624 &iflib_txq_drain_oactive, 0, "# drain oactives");
625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
626 &iflib_txq_drain_notready, 0, "# drain notready");
629 static int iflib_encap_load_mbuf_fail;
630 static int iflib_encap_pad_mbuf_fail;
631 static int iflib_encap_txq_avail_fail;
632 static int iflib_encap_txd_encap_fail;
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
643 static int iflib_task_fn_rxs;
644 static int iflib_rx_intr_enables;
645 static int iflib_fast_intrs;
646 static int iflib_rx_unavail;
647 static int iflib_rx_ctx_inactive;
648 static int iflib_rx_if_input;
649 static int iflib_rxd_flush;
651 static int iflib_verbose_debug;
653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
656 &iflib_rx_intr_enables, 0, "# RX intr enables");
657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
658 &iflib_fast_intrs, 0, "# fast_intr calls");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
660 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
664 &iflib_rx_if_input, 0, "# times rxeof called if_input");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
666 &iflib_rxd_flush, 0, "# times rxd_flush called");
667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
668 &iflib_verbose_debug, 0, "enable verbose debugging");
670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
672 iflib_debug_reset(void)
674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
676 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
677 iflib_txq_drain_notready =
678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
682 iflib_rx_ctx_inactive = iflib_rx_if_input =
687 #define DBG_COUNTER_INC(name)
688 static void iflib_debug_reset(void) {}
691 #define IFLIB_DEBUG 0
693 static void iflib_tx_structures_free(if_ctx_t ctx);
694 static void iflib_rx_structures_free(if_ctx_t ctx);
695 static int iflib_queues_alloc(if_ctx_t ctx);
696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
698 static int iflib_qset_structures_setup(if_ctx_t ctx);
699 static int iflib_msix_init(if_ctx_t ctx);
700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
704 static void iflib_altq_if_start(if_t ifp);
705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
707 static int iflib_register(if_ctx_t);
708 static void iflib_deregister(if_ctx_t);
709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
710 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
711 static void iflib_init_locked(if_ctx_t ctx);
712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
713 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
714 static void iflib_ifmp_purge(iflib_txq_t txq);
715 static void _iflib_pre_assert(if_softc_ctx_t scctx);
716 static void iflib_if_init_locked(if_ctx_t ctx);
717 static void iflib_free_intr_mem(if_ctx_t ctx);
718 #ifndef __NO_STRICT_ALIGNMENT
719 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
723 SLIST_HEAD_INITIALIZER(cpu_offsets);
725 SLIST_ENTRY(cpu_offset) entries;
727 unsigned int refcount;
730 static struct mtx cpu_offset_mtx;
731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
734 DEBUGNET_DEFINE(iflib);
737 #include <sys/selinfo.h>
738 #include <net/netmap.h>
739 #include <dev/netmap/netmap_kern.h>
741 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
746 * device-specific sysctl variables:
748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
749 * During regular operations the CRC is stripped, but on some
750 * hardware reception of frames not multiple of 64 is slower,
751 * so using crcstrip=0 helps in benchmarks.
753 * iflib_rx_miss, iflib_rx_miss_bufs:
754 * count packets that might be missed due to lost interrupts.
756 SYSCTL_DECL(_dev_netmap);
758 * The xl driver by default strips CRCs and we do not override it.
761 int iflib_crcstrip = 1;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
765 int iflib_rx_miss, iflib_rx_miss_bufs;
766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
772 * Register/unregister. We are already under netmap lock.
773 * Only called on the first register or the last unregister.
776 iflib_netmap_register(struct netmap_adapter *na, int onoff)
779 if_ctx_t ctx = ifp->if_softc;
783 IFDI_INTR_DISABLE(ctx);
785 /* Tell the stack that the interface is no longer active */
786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
794 * Enable (or disable) netmap flags, and intercept (or restore)
795 * ifp->if_transmit. This is done once the device has been stopped
796 * to prevent race conditions.
799 nm_set_native_flags(na);
801 nm_clear_native_flags(na);
804 iflib_init_locked(ctx);
805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
806 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
808 nm_clear_native_flags(na);
814 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
816 struct netmap_adapter *na = kring->na;
817 u_int const lim = kring->nkr_num_slots - 1;
818 u_int head = kring->rhead;
819 struct netmap_ring *ring = kring->ring;
821 struct if_rxd_update iru;
822 if_ctx_t ctx = rxq->ifr_ctx;
823 iflib_fl_t fl = &rxq->ifr_fl[0];
824 uint32_t refill_pidx, nic_i;
825 #if IFLIB_DEBUG_COUNTERS
829 if (nm_i == head && __predict_true(!init))
831 iru_init(&iru, rxq, 0 /* flid */);
832 map = fl->ifl_sds.ifsd_map;
833 refill_pidx = netmap_idx_k2n(kring, nm_i);
835 * IMPORTANT: we must leave one free slot in the ring,
836 * so move head back by one unit
838 head = nm_prev(head, lim);
840 DBG_COUNTER_INC(fl_refills);
841 while (nm_i != head) {
842 #if IFLIB_DEBUG_COUNTERS
844 DBG_COUNTER_INC(fl_refills_large);
846 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
847 struct netmap_slot *slot = &ring->slot[nm_i];
848 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
849 uint32_t nic_i_dma = refill_pidx;
850 nic_i = netmap_idx_k2n(kring, nm_i);
852 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
854 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
855 return netmap_ring_reinit(kring);
857 fl->ifl_vm_addrs[tmp_pidx] = addr;
858 if (__predict_false(init)) {
859 netmap_load_map(na, fl->ifl_buf_tag,
861 } else if (slot->flags & NS_BUF_CHANGED) {
862 /* buffer has changed, reload map */
863 netmap_reload_map(na, fl->ifl_buf_tag,
866 slot->flags &= ~NS_BUF_CHANGED;
868 nm_i = nm_next(nm_i, lim);
869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
873 iru.iru_pidx = refill_pidx;
874 iru.iru_count = tmp_pidx+1;
875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
877 for (int n = 0; n < iru.iru_count; n++) {
878 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
879 BUS_DMASYNC_PREREAD);
880 /* XXX - change this to not use the netmap func*/
881 nic_i_dma = nm_next(nic_i_dma, lim);
885 kring->nr_hwcur = head;
887 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
889 if (__predict_true(nic_i != UINT_MAX)) {
890 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
891 DBG_COUNTER_INC(rxd_flush);
897 * Reconcile kernel and user view of the transmit ring.
899 * All information is in the kring.
900 * Userspace wants to send packets up to the one before kring->rhead,
901 * kernel knows kring->nr_hwcur is the first unsent packet.
903 * Here we push packets out (as many as possible), and possibly
904 * reclaim buffers from previously completed transmission.
906 * The caller (netmap) guarantees that there is only one instance
907 * running at any time. Any interference with other driver
908 * methods should be handled by the individual drivers.
911 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
913 struct netmap_adapter *na = kring->na;
915 struct netmap_ring *ring = kring->ring;
916 u_int nm_i; /* index into the netmap kring */
917 u_int nic_i; /* index into the NIC ring */
919 u_int const lim = kring->nkr_num_slots - 1;
920 u_int const head = kring->rhead;
921 struct if_pkt_info pi;
924 * interrupts on every tx packet are expensive so request
925 * them every half ring, or where NS_REPORT is set
927 u_int report_frequency = kring->nkr_num_slots >> 1;
928 /* device-specific */
929 if_ctx_t ctx = ifp->if_softc;
930 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
932 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
936 * First part: process new packets to send.
937 * nm_i is the current index in the netmap kring,
938 * nic_i is the corresponding index in the NIC ring.
940 * If we have packets to send (nm_i != head)
941 * iterate over the netmap ring, fetch length and update
942 * the corresponding slot in the NIC ring. Some drivers also
943 * need to update the buffer's physical address in the NIC slot
944 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
946 * The netmap_reload_map() calls is especially expensive,
947 * even when (as in this case) the tag is 0, so do only
948 * when the buffer has actually changed.
950 * If possible do not set the report/intr bit on all slots,
951 * but only a few times per ring or when NS_REPORT is set.
953 * Finally, on 10G and faster drivers, it might be useful
954 * to prefetch the next slot and txr entry.
957 nm_i = kring->nr_hwcur;
958 if (nm_i != head) { /* we have new packets to send */
960 pi.ipi_segs = txq->ift_segs;
961 pi.ipi_qsidx = kring->ring_id;
962 nic_i = netmap_idx_k2n(kring, nm_i);
964 __builtin_prefetch(&ring->slot[nm_i]);
965 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
966 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
968 for (n = 0; nm_i != head; n++) {
969 struct netmap_slot *slot = &ring->slot[nm_i];
970 u_int len = slot->len;
972 void *addr = PNMB(na, slot, &paddr);
973 int flags = (slot->flags & NS_REPORT ||
974 nic_i == 0 || nic_i == report_frequency) ?
977 /* device-specific */
979 pi.ipi_segs[0].ds_addr = paddr;
980 pi.ipi_segs[0].ds_len = len;
984 pi.ipi_flags = flags;
986 /* Fill the slot in the NIC ring. */
987 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
988 DBG_COUNTER_INC(tx_encap);
990 /* prefetch for next round */
991 __builtin_prefetch(&ring->slot[nm_i + 1]);
992 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
993 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
995 NM_CHECK_ADDR_LEN(na, addr, len);
997 if (slot->flags & NS_BUF_CHANGED) {
998 /* buffer has changed, reload map */
999 netmap_reload_map(na, txq->ift_buf_tag,
1000 txq->ift_sds.ifsd_map[nic_i], addr);
1002 /* make sure changes to the buffer are synced */
1003 bus_dmamap_sync(txq->ift_buf_tag,
1004 txq->ift_sds.ifsd_map[nic_i],
1005 BUS_DMASYNC_PREWRITE);
1007 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1008 nm_i = nm_next(nm_i, lim);
1009 nic_i = nm_next(nic_i, lim);
1011 kring->nr_hwcur = nm_i;
1013 /* synchronize the NIC ring */
1014 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1017 /* (re)start the tx unit up to slot nic_i (excluded) */
1018 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1022 * Second part: reclaim buffers for completed transmissions.
1024 * If there are unclaimed buffers, attempt to reclaim them.
1025 * If none are reclaimed, and TX IRQs are not in use, do an initial
1026 * minimal delay, then trigger the tx handler which will spin in the
1029 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1030 if (iflib_tx_credits_update(ctx, txq)) {
1031 /* some tx completed, increment avail */
1032 nic_i = txq->ift_cidx_processed;
1033 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1036 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1037 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1038 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1039 iflib_timer, txq, txq->ift_timer.c_cpu);
1045 * Reconcile kernel and user view of the receive ring.
1046 * Same as for the txsync, this routine must be efficient.
1047 * The caller guarantees a single invocations, but races against
1048 * the rest of the driver should be handled here.
1050 * On call, kring->rhead is the first packet that userspace wants
1051 * to keep, and kring->rcur is the wakeup point.
1052 * The kernel has previously reported packets up to kring->rtail.
1054 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1055 * of whether or not we received an interrupt.
1058 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1060 struct netmap_adapter *na = kring->na;
1061 struct netmap_ring *ring = kring->ring;
1064 uint32_t nm_i; /* index into the netmap ring */
1065 uint32_t nic_i; /* index into the NIC ring */
1067 u_int const lim = kring->nkr_num_slots - 1;
1068 u_int const head = kring->rhead;
1069 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1070 struct if_rxd_info ri;
1072 if_ctx_t ctx = ifp->if_softc;
1073 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1075 return netmap_ring_reinit(kring);
1078 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1081 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1082 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1087 * First part: import newly received packets.
1089 * nm_i is the index of the next free slot in the netmap ring,
1090 * nic_i is the index of the next received packet in the NIC ring,
1091 * and they may differ in case if_init() has been called while
1092 * in netmap mode. For the receive ring we have
1094 * nic_i = rxr->next_check;
1095 * nm_i = kring->nr_hwtail (previous)
1097 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1099 * rxr->next_check is set to 0 on a ring reinit
1101 if (netmap_no_pendintr || force_update) {
1102 int crclen = iflib_crcstrip ? 0 : 4;
1105 for (i = 0; i < rxq->ifr_nfl; i++) {
1106 fl = &rxq->ifr_fl[i];
1107 nic_i = fl->ifl_cidx;
1108 nm_i = netmap_idx_n2k(kring, nic_i);
1109 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1110 rxq->ifr_id, nic_i, USHRT_MAX);
1111 for (n = 0; avail > 0; n++, avail--) {
1113 ri.iri_frags = rxq->ifr_frags;
1114 ri.iri_qsidx = kring->ring_id;
1115 ri.iri_ifp = ctx->ifc_ifp;
1116 ri.iri_cidx = nic_i;
1118 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1119 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1120 ring->slot[nm_i].flags = 0;
1121 bus_dmamap_sync(fl->ifl_buf_tag,
1122 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1123 nm_i = nm_next(nm_i, lim);
1124 nic_i = nm_next(nic_i, lim);
1126 if (n) { /* update the state variables */
1127 if (netmap_no_pendintr && !force_update) {
1130 iflib_rx_miss_bufs += n;
1132 fl->ifl_cidx = nic_i;
1133 kring->nr_hwtail = nm_i;
1135 kring->nr_kflags &= ~NKR_PENDINTR;
1139 * Second part: skip past packets that userspace has released.
1140 * (kring->nr_hwcur to head excluded),
1141 * and make the buffers available for reception.
1142 * As usual nm_i is the index in the netmap ring,
1143 * nic_i is the index in the NIC ring, and
1144 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1146 /* XXX not sure how this will work with multiple free lists */
1147 nm_i = kring->nr_hwcur;
1149 return (netmap_fl_refill(rxq, kring, nm_i, false));
1153 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1155 if_ctx_t ctx = na->ifp->if_softc;
1159 IFDI_INTR_ENABLE(ctx);
1161 IFDI_INTR_DISABLE(ctx);
1168 iflib_netmap_attach(if_ctx_t ctx)
1170 struct netmap_adapter na;
1171 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1173 bzero(&na, sizeof(na));
1175 na.ifp = ctx->ifc_ifp;
1176 na.na_flags = NAF_BDG_MAYSLEEP;
1177 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1178 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1180 na.num_tx_desc = scctx->isc_ntxd[0];
1181 na.num_rx_desc = scctx->isc_nrxd[0];
1182 na.nm_txsync = iflib_netmap_txsync;
1183 na.nm_rxsync = iflib_netmap_rxsync;
1184 na.nm_register = iflib_netmap_register;
1185 na.nm_intr = iflib_netmap_intr;
1186 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1187 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1188 return (netmap_attach(&na));
1192 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1194 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1195 struct netmap_slot *slot;
1197 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1200 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1203 * In netmap mode, set the map for the packet buffer.
1204 * NOTE: Some drivers (not this one) also need to set
1205 * the physical buffer address in the NIC ring.
1206 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1207 * netmap slot index, si
1209 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1210 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1211 NMB(na, slot + si));
1216 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1218 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1219 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1220 struct netmap_slot *slot;
1223 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1226 nm_i = netmap_idx_n2k(kring, 0);
1227 netmap_fl_refill(rxq, kring, nm_i, true);
1231 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1233 struct netmap_kring *kring;
1236 txqid = txq->ift_id;
1237 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1239 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1240 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1241 BUS_DMASYNC_POSTREAD);
1242 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1243 netmap_tx_irq(ctx->ifc_ifp, txqid);
1244 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1248 *reset_on = hz / 1000;
1253 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1256 #define iflib_netmap_txq_init(ctx, txq)
1257 #define iflib_netmap_rxq_init(ctx, rxq)
1258 #define iflib_netmap_detach(ifp)
1260 #define iflib_netmap_attach(ctx) (0)
1261 #define netmap_rx_irq(ifp, qid, budget) (0)
1262 #define netmap_tx_irq(ifp, qid) do {} while (0)
1263 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1266 #if defined(__i386__) || defined(__amd64__)
1267 static __inline void
1270 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1272 static __inline void
1273 prefetch2cachelines(void *x)
1275 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1276 #if (CACHE_LINE_SIZE < 128)
1277 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1282 #define prefetch2cachelines(x)
1286 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1290 fl = &rxq->ifr_fl[flid];
1291 iru->iru_paddrs = fl->ifl_bus_addrs;
1292 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1293 iru->iru_idxs = fl->ifl_rxd_idxs;
1294 iru->iru_qsidx = rxq->ifr_id;
1295 iru->iru_buf_size = fl->ifl_buf_size;
1296 iru->iru_flidx = fl->ifl_id;
1300 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1304 *(bus_addr_t *) arg = segs[0].ds_addr;
1308 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1311 device_t dev = ctx->ifc_dev;
1313 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1314 align, 0, /* alignment, bounds */
1315 BUS_SPACE_MAXADDR, /* lowaddr */
1316 BUS_SPACE_MAXADDR, /* highaddr */
1317 NULL, NULL, /* filter, filterarg */
1320 size, /* maxsegsize */
1321 BUS_DMA_ALLOCNOW, /* flags */
1322 NULL, /* lockfunc */
1327 "%s: bus_dma_tag_create failed: %d\n",
1332 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1333 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1336 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1337 __func__, (uintmax_t)size, err);
1341 dma->idi_paddr = IF_BAD_DMA;
1342 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1343 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1344 if (err || dma->idi_paddr == IF_BAD_DMA) {
1346 "%s: bus_dmamap_load failed: %d\n",
1351 dma->idi_size = size;
1355 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1357 bus_dma_tag_destroy(dma->idi_tag);
1359 dma->idi_tag = NULL;
1365 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1367 if_shared_ctx_t sctx = ctx->ifc_sctx;
1369 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1371 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1375 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1378 iflib_dma_info_t *dmaiter;
1381 for (i = 0; i < count; i++, dmaiter++) {
1382 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1386 iflib_dma_free_multi(dmalist, i);
1391 iflib_dma_free(iflib_dma_info_t dma)
1393 if (dma->idi_tag == NULL)
1395 if (dma->idi_paddr != IF_BAD_DMA) {
1396 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1397 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1398 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1399 dma->idi_paddr = IF_BAD_DMA;
1401 if (dma->idi_vaddr != NULL) {
1402 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1403 dma->idi_vaddr = NULL;
1405 bus_dma_tag_destroy(dma->idi_tag);
1406 dma->idi_tag = NULL;
1410 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1413 iflib_dma_info_t *dmaiter = dmalist;
1415 for (i = 0; i < count; i++, dmaiter++)
1416 iflib_dma_free(*dmaiter);
1420 iflib_fast_intr(void *arg)
1422 iflib_filter_info_t info = arg;
1423 struct grouptask *gtask = info->ifi_task;
1426 DBG_COUNTER_INC(fast_intrs);
1427 if (info->ifi_filter != NULL) {
1428 result = info->ifi_filter(info->ifi_filter_arg);
1429 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1433 GROUPTASK_ENQUEUE(gtask);
1434 return (FILTER_HANDLED);
1438 iflib_fast_intr_rxtx(void *arg)
1440 iflib_filter_info_t info = arg;
1441 struct grouptask *gtask = info->ifi_task;
1443 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1446 int i, cidx, result;
1448 bool intr_enable, intr_legacy;
1450 DBG_COUNTER_INC(fast_intrs);
1451 if (info->ifi_filter != NULL) {
1452 result = info->ifi_filter(info->ifi_filter_arg);
1453 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1458 sc = ctx->ifc_softc;
1459 intr_enable = false;
1460 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1461 MPASS(rxq->ifr_ntxqirq);
1462 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1463 txqid = rxq->ifr_txqid[i];
1464 txq = &ctx->ifc_txqs[txqid];
1465 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1466 BUS_DMASYNC_POSTREAD);
1467 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1471 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1474 GROUPTASK_ENQUEUE(&txq->ift_task);
1476 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1477 cidx = rxq->ifr_cq_cidx;
1479 cidx = rxq->ifr_fl[0].ifl_cidx;
1480 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1481 GROUPTASK_ENQUEUE(gtask);
1486 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1487 DBG_COUNTER_INC(rx_intr_enables);
1490 IFDI_INTR_ENABLE(ctx);
1491 return (FILTER_HANDLED);
1496 iflib_fast_intr_ctx(void *arg)
1498 iflib_filter_info_t info = arg;
1499 struct grouptask *gtask = info->ifi_task;
1502 DBG_COUNTER_INC(fast_intrs);
1503 if (info->ifi_filter != NULL) {
1504 result = info->ifi_filter(info->ifi_filter_arg);
1505 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1509 GROUPTASK_ENQUEUE(gtask);
1510 return (FILTER_HANDLED);
1514 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1515 driver_filter_t filter, driver_intr_t handler, void *arg,
1518 struct resource *res;
1520 device_t dev = ctx->ifc_dev;
1524 if (ctx->ifc_flags & IFC_LEGACY)
1525 flags |= RF_SHAREABLE;
1528 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1531 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1535 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1536 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1537 filter, handler, arg, &tag);
1540 "failed to setup interrupt for rid %d, name %s: %d\n",
1541 rid, name ? name : "unknown", rc);
1544 bus_describe_intr(dev, res, tag, "%s", name);
1550 /*********************************************************************
1552 * Allocate DMA resources for TX buffers as well as memory for the TX
1553 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1554 * iflib_sw_tx_desc_array structure, storing all the information that
1555 * is needed to transmit a packet on the wire. This is called only
1556 * once at attach, setup is done every reset.
1558 **********************************************************************/
1560 iflib_txsd_alloc(iflib_txq_t txq)
1562 if_ctx_t ctx = txq->ift_ctx;
1563 if_shared_ctx_t sctx = ctx->ifc_sctx;
1564 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1565 device_t dev = ctx->ifc_dev;
1566 bus_size_t tsomaxsize;
1567 int err, nsegments, ntsosegments;
1570 nsegments = scctx->isc_tx_nsegments;
1571 ntsosegments = scctx->isc_tx_tso_segments_max;
1572 tsomaxsize = scctx->isc_tx_tso_size_max;
1573 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1574 tsomaxsize += sizeof(struct ether_vlan_header);
1575 MPASS(scctx->isc_ntxd[0] > 0);
1576 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1577 MPASS(nsegments > 0);
1578 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1579 MPASS(ntsosegments > 0);
1580 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1584 * Set up DMA tags for TX buffers.
1586 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1587 1, 0, /* alignment, bounds */
1588 BUS_SPACE_MAXADDR, /* lowaddr */
1589 BUS_SPACE_MAXADDR, /* highaddr */
1590 NULL, NULL, /* filter, filterarg */
1591 sctx->isc_tx_maxsize, /* maxsize */
1592 nsegments, /* nsegments */
1593 sctx->isc_tx_maxsegsize, /* maxsegsize */
1595 NULL, /* lockfunc */
1596 NULL, /* lockfuncarg */
1597 &txq->ift_buf_tag))) {
1598 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1599 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1600 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1603 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1604 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1605 1, 0, /* alignment, bounds */
1606 BUS_SPACE_MAXADDR, /* lowaddr */
1607 BUS_SPACE_MAXADDR, /* highaddr */
1608 NULL, NULL, /* filter, filterarg */
1609 tsomaxsize, /* maxsize */
1610 ntsosegments, /* nsegments */
1611 sctx->isc_tso_maxsegsize,/* maxsegsize */
1613 NULL, /* lockfunc */
1614 NULL, /* lockfuncarg */
1615 &txq->ift_tso_buf_tag))) {
1616 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1621 /* Allocate memory for the TX mbuf map. */
1622 if (!(txq->ift_sds.ifsd_m =
1623 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1624 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1625 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1631 * Create the DMA maps for TX buffers.
1633 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1634 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1635 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1637 "Unable to allocate TX buffer DMA map memory\n");
1641 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1642 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1643 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1645 "Unable to allocate TSO TX buffer map memory\n");
1649 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1650 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1651 &txq->ift_sds.ifsd_map[i]);
1653 device_printf(dev, "Unable to create TX DMA map\n");
1658 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1659 &txq->ift_sds.ifsd_tso_map[i]);
1661 device_printf(dev, "Unable to create TSO TX DMA map\n");
1667 /* We free all, it handles case where we are in the middle */
1668 iflib_tx_structures_free(ctx);
1673 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1677 if (txq->ift_sds.ifsd_map != NULL) {
1678 map = txq->ift_sds.ifsd_map[i];
1679 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1680 bus_dmamap_unload(txq->ift_buf_tag, map);
1681 bus_dmamap_destroy(txq->ift_buf_tag, map);
1682 txq->ift_sds.ifsd_map[i] = NULL;
1685 if (txq->ift_sds.ifsd_tso_map != NULL) {
1686 map = txq->ift_sds.ifsd_tso_map[i];
1687 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1688 BUS_DMASYNC_POSTWRITE);
1689 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1690 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1691 txq->ift_sds.ifsd_tso_map[i] = NULL;
1696 iflib_txq_destroy(iflib_txq_t txq)
1698 if_ctx_t ctx = txq->ift_ctx;
1700 for (int i = 0; i < txq->ift_size; i++)
1701 iflib_txsd_destroy(ctx, txq, i);
1703 if (txq->ift_br != NULL) {
1704 ifmp_ring_free(txq->ift_br);
1708 mtx_destroy(&txq->ift_mtx);
1710 if (txq->ift_sds.ifsd_map != NULL) {
1711 free(txq->ift_sds.ifsd_map, M_IFLIB);
1712 txq->ift_sds.ifsd_map = NULL;
1714 if (txq->ift_sds.ifsd_tso_map != NULL) {
1715 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1716 txq->ift_sds.ifsd_tso_map = NULL;
1718 if (txq->ift_sds.ifsd_m != NULL) {
1719 free(txq->ift_sds.ifsd_m, M_IFLIB);
1720 txq->ift_sds.ifsd_m = NULL;
1722 if (txq->ift_buf_tag != NULL) {
1723 bus_dma_tag_destroy(txq->ift_buf_tag);
1724 txq->ift_buf_tag = NULL;
1726 if (txq->ift_tso_buf_tag != NULL) {
1727 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1728 txq->ift_tso_buf_tag = NULL;
1730 if (txq->ift_ifdi != NULL) {
1731 free(txq->ift_ifdi, M_IFLIB);
1736 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1740 mp = &txq->ift_sds.ifsd_m[i];
1744 if (txq->ift_sds.ifsd_map != NULL) {
1745 bus_dmamap_sync(txq->ift_buf_tag,
1746 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1747 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1749 if (txq->ift_sds.ifsd_tso_map != NULL) {
1750 bus_dmamap_sync(txq->ift_tso_buf_tag,
1751 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1752 bus_dmamap_unload(txq->ift_tso_buf_tag,
1753 txq->ift_sds.ifsd_tso_map[i]);
1756 DBG_COUNTER_INC(tx_frees);
1761 iflib_txq_setup(iflib_txq_t txq)
1763 if_ctx_t ctx = txq->ift_ctx;
1764 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1765 if_shared_ctx_t sctx = ctx->ifc_sctx;
1766 iflib_dma_info_t di;
1769 /* Set number of descriptors available */
1770 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1771 /* XXX make configurable */
1772 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1775 txq->ift_cidx_processed = 0;
1776 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1777 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1779 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1780 bzero((void *)di->idi_vaddr, di->idi_size);
1782 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1783 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1784 bus_dmamap_sync(di->idi_tag, di->idi_map,
1785 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1789 /*********************************************************************
1791 * Allocate DMA resources for RX buffers as well as memory for the RX
1792 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1793 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1794 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1795 * Since we use use one entry in iflib_sw_rx_desc_array per received
1796 * packet, the maximum number of entries we'll need is equal to the
1797 * number of hardware receive descriptors that we've allocated.
1799 **********************************************************************/
1801 iflib_rxsd_alloc(iflib_rxq_t rxq)
1803 if_ctx_t ctx = rxq->ifr_ctx;
1804 if_shared_ctx_t sctx = ctx->ifc_sctx;
1805 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1806 device_t dev = ctx->ifc_dev;
1810 MPASS(scctx->isc_nrxd[0] > 0);
1811 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1814 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1815 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1816 /* Set up DMA tag for RX buffers. */
1817 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1818 1, 0, /* alignment, bounds */
1819 BUS_SPACE_MAXADDR, /* lowaddr */
1820 BUS_SPACE_MAXADDR, /* highaddr */
1821 NULL, NULL, /* filter, filterarg */
1822 sctx->isc_rx_maxsize, /* maxsize */
1823 sctx->isc_rx_nsegments, /* nsegments */
1824 sctx->isc_rx_maxsegsize, /* maxsegsize */
1826 NULL, /* lockfunc */
1831 "Unable to allocate RX DMA tag: %d\n", err);
1835 /* Allocate memory for the RX mbuf map. */
1836 if (!(fl->ifl_sds.ifsd_m =
1837 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1838 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1840 "Unable to allocate RX mbuf map memory\n");
1845 /* Allocate memory for the direct RX cluster pointer map. */
1846 if (!(fl->ifl_sds.ifsd_cl =
1847 (caddr_t *) malloc(sizeof(caddr_t) *
1848 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1850 "Unable to allocate RX cluster map memory\n");
1855 /* Allocate memory for the RX cluster bus address map. */
1856 if (!(fl->ifl_sds.ifsd_ba =
1857 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1858 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1860 "Unable to allocate RX bus address map memory\n");
1866 * Create the DMA maps for RX buffers.
1868 if (!(fl->ifl_sds.ifsd_map =
1869 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1871 "Unable to allocate RX buffer DMA map memory\n");
1875 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1876 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1877 &fl->ifl_sds.ifsd_map[i]);
1879 device_printf(dev, "Unable to create RX buffer DMA map\n");
1887 iflib_rx_structures_free(ctx);
1893 * Internal service routines
1896 struct rxq_refill_cb_arg {
1898 bus_dma_segment_t seg;
1903 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1905 struct rxq_refill_cb_arg *cb_arg = arg;
1907 cb_arg->error = error;
1908 cb_arg->seg = segs[0];
1909 cb_arg->nseg = nseg;
1913 * _iflib_fl_refill - refill an rxq free-buffer list
1914 * @ctx: the iflib context
1915 * @fl: the free list to refill
1916 * @count: the number of new buffers to allocate
1918 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1919 * The caller must assure that @count does not exceed the queue's capacity.
1922 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1924 struct if_rxd_update iru;
1925 struct rxq_refill_cb_arg cb_arg;
1929 bus_dmamap_t *sd_map;
1930 bus_addr_t bus_addr, *sd_ba;
1931 int err, frag_idx, i, idx, n, pidx;
1934 sd_m = fl->ifl_sds.ifsd_m;
1935 sd_map = fl->ifl_sds.ifsd_map;
1936 sd_cl = fl->ifl_sds.ifsd_cl;
1937 sd_ba = fl->ifl_sds.ifsd_ba;
1938 pidx = fl->ifl_pidx;
1940 frag_idx = fl->ifl_fragidx;
1941 credits = fl->ifl_credits;
1946 MPASS(credits + n <= fl->ifl_size);
1948 if (pidx < fl->ifl_cidx)
1949 MPASS(pidx + n <= fl->ifl_cidx);
1950 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1951 MPASS(fl->ifl_gen == 0);
1952 if (pidx > fl->ifl_cidx)
1953 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1955 DBG_COUNTER_INC(fl_refills);
1957 DBG_COUNTER_INC(fl_refills_large);
1958 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1961 * We allocate an uninitialized mbuf + cluster, mbuf is
1962 * initialized after rx.
1964 * If the cluster is still set then we know a minimum sized packet was received
1966 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1969 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1970 MPASS(frag_idx >= 0);
1971 if ((cl = sd_cl[frag_idx]) == NULL) {
1972 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1976 MPASS(sd_map != NULL);
1977 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1978 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1980 if (err != 0 || cb_arg.error) {
1984 if (fl->ifl_zone == zone_pack)
1985 uma_zfree(fl->ifl_zone, cl);
1989 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
1990 sd_cl[frag_idx] = cl;
1992 fl->ifl_cl_enqueued++;
1995 bus_addr = sd_ba[frag_idx];
1997 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
1998 BUS_DMASYNC_PREREAD);
2000 if (sd_m[frag_idx] == NULL) {
2001 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2006 bit_set(fl->ifl_rx_bitmap, frag_idx);
2008 fl->ifl_m_enqueued++;
2011 DBG_COUNTER_INC(rx_allocs);
2012 fl->ifl_rxd_idxs[i] = frag_idx;
2013 fl->ifl_bus_addrs[i] = bus_addr;
2014 fl->ifl_vm_addrs[i] = cl;
2017 MPASS(credits <= fl->ifl_size);
2018 if (++idx == fl->ifl_size) {
2022 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2023 iru.iru_pidx = pidx;
2025 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2029 fl->ifl_credits = credits;
2034 iru.iru_pidx = pidx;
2036 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2038 fl->ifl_credits = credits;
2040 DBG_COUNTER_INC(rxd_flush);
2041 if (fl->ifl_pidx == 0)
2042 pidx = fl->ifl_size - 1;
2044 pidx = fl->ifl_pidx - 1;
2046 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2048 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2049 fl->ifl_fragidx = frag_idx + 1;
2050 if (fl->ifl_fragidx == fl->ifl_size)
2051 fl->ifl_fragidx = 0;
2053 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2056 static __inline uint8_t
2057 __iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2059 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2060 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2062 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2065 MPASS(fl->ifl_credits <= fl->ifl_size);
2066 MPASS(reclaimable == delta);
2068 if (reclaimable > 0)
2069 return (_iflib_fl_refill(ctx, fl, reclaimable));
2074 iflib_in_detach(if_ctx_t ctx)
2079 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2085 iflib_fl_bufs_free(iflib_fl_t fl)
2087 iflib_dma_info_t idi = fl->ifl_ifdi;
2088 bus_dmamap_t sd_map;
2091 for (i = 0; i < fl->ifl_size; i++) {
2092 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2093 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2095 if (*sd_cl != NULL) {
2096 sd_map = fl->ifl_sds.ifsd_map[i];
2097 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2098 BUS_DMASYNC_POSTREAD);
2099 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2101 uma_zfree(fl->ifl_zone, *sd_cl);
2102 if (*sd_m != NULL) {
2103 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2104 uma_zfree(zone_mbuf, *sd_m);
2107 MPASS(*sd_cl == NULL);
2108 MPASS(*sd_m == NULL);
2111 fl->ifl_m_dequeued++;
2112 fl->ifl_cl_dequeued++;
2118 for (i = 0; i < fl->ifl_size; i++) {
2119 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2120 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2124 * Reset free list values
2126 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2127 bzero(idi->idi_vaddr, idi->idi_size);
2130 /*********************************************************************
2132 * Initialize a free list and its buffers.
2134 **********************************************************************/
2136 iflib_fl_setup(iflib_fl_t fl)
2138 iflib_rxq_t rxq = fl->ifl_rxq;
2139 if_ctx_t ctx = rxq->ifr_ctx;
2140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2143 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2145 ** Free current RX buffer structs and their mbufs
2147 iflib_fl_bufs_free(fl);
2148 /* Now replenish the mbufs */
2149 MPASS(fl->ifl_credits == 0);
2150 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2151 if (scctx->isc_rxd_buf_size[qidx] != 0)
2152 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2154 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2156 * ifl_buf_size may be a driver-supplied value, so pull it up
2157 * to the selected mbuf size.
2159 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2160 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2161 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2162 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2163 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2166 /* avoid pre-allocating zillions of clusters to an idle card
2167 * potentially speeding up attach
2169 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2170 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2171 if (min(128, fl->ifl_size) != fl->ifl_credits)
2177 MPASS(fl->ifl_ifdi != NULL);
2178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2183 /*********************************************************************
2185 * Free receive ring data structures
2187 **********************************************************************/
2189 iflib_rx_sds_free(iflib_rxq_t rxq)
2194 if (rxq->ifr_fl != NULL) {
2195 for (i = 0; i < rxq->ifr_nfl; i++) {
2196 fl = &rxq->ifr_fl[i];
2197 if (fl->ifl_buf_tag != NULL) {
2198 if (fl->ifl_sds.ifsd_map != NULL) {
2199 for (j = 0; j < fl->ifl_size; j++) {
2202 fl->ifl_sds.ifsd_map[j],
2203 BUS_DMASYNC_POSTREAD);
2206 fl->ifl_sds.ifsd_map[j]);
2209 fl->ifl_sds.ifsd_map[j]);
2212 bus_dma_tag_destroy(fl->ifl_buf_tag);
2213 fl->ifl_buf_tag = NULL;
2215 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2216 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2217 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2218 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2219 fl->ifl_sds.ifsd_m = NULL;
2220 fl->ifl_sds.ifsd_cl = NULL;
2221 fl->ifl_sds.ifsd_ba = NULL;
2222 fl->ifl_sds.ifsd_map = NULL;
2224 free(rxq->ifr_fl, M_IFLIB);
2226 free(rxq->ifr_ifdi, M_IFLIB);
2227 rxq->ifr_ifdi = NULL;
2228 rxq->ifr_cq_cidx = 0;
2236 iflib_timer(void *arg)
2238 iflib_txq_t txq = arg;
2239 if_ctx_t ctx = txq->ift_ctx;
2240 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2241 uint64_t this_tick = ticks;
2242 uint32_t reset_on = hz / 2;
2244 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2248 ** Check on the state of the TX queue(s), this
2249 ** can be done without the lock because its RO
2250 ** and the HUNG state will be static if set.
2252 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2253 txq->ift_last_timer_tick = this_tick;
2254 IFDI_TIMER(ctx, txq->ift_id);
2255 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2256 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2257 (sctx->isc_pause_frames == 0)))
2260 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2261 ifmp_ring_is_stalled(txq->ift_br)) {
2262 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2263 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2265 txq->ift_cleaned_prev = txq->ift_cleaned;
2268 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2269 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2271 /* handle any laggards */
2272 if (txq->ift_db_pending)
2273 GROUPTASK_ENQUEUE(&txq->ift_task);
2275 sctx->isc_pause_frames = 0;
2276 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2277 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2281 device_printf(ctx->ifc_dev,
2282 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2283 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2285 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2286 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2287 iflib_admin_intr_deferred(ctx);
2292 iflib_get_mbuf_size_for(unsigned int size)
2295 if (size <= MCLBYTES)
2298 return (MJUMPAGESIZE);
2302 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2304 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2307 * XXX don't set the max_frame_size to larger
2308 * than the hardware can handle
2310 ctx->ifc_rx_mbuf_sz =
2311 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2315 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2318 return (ctx->ifc_rx_mbuf_sz);
2322 iflib_init_locked(if_ctx_t ctx)
2324 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2325 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2326 if_t ifp = ctx->ifc_ifp;
2330 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2332 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2333 IFDI_INTR_DISABLE(ctx);
2335 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2336 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2337 /* Set hardware offload abilities */
2338 if_clearhwassist(ifp);
2339 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2340 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2341 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2342 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2343 if (if_getcapenable(ifp) & IFCAP_TSO4)
2344 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2345 if (if_getcapenable(ifp) & IFCAP_TSO6)
2346 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2348 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2350 callout_stop(&txq->ift_timer);
2351 CALLOUT_UNLOCK(txq);
2352 iflib_netmap_txq_init(ctx, txq);
2356 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2357 * that drivers can use the value when setting up the hardware receive
2360 iflib_calc_rx_mbuf_sz(ctx);
2363 i = if_getdrvflags(ifp);
2366 MPASS(if_getdrvflags(ifp) == i);
2367 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2368 /* XXX this should really be done on a per-queue basis */
2369 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2370 MPASS(rxq->ifr_id == i);
2371 iflib_netmap_rxq_init(ctx, rxq);
2374 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2375 if (iflib_fl_setup(fl)) {
2376 device_printf(ctx->ifc_dev,
2377 "setting up free list %d failed - "
2378 "check cluster settings\n", j);
2384 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2385 IFDI_INTR_ENABLE(ctx);
2386 txq = ctx->ifc_txqs;
2387 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2388 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2389 txq->ift_timer.c_cpu);
2393 iflib_media_change(if_t ifp)
2395 if_ctx_t ctx = if_getsoftc(ifp);
2399 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2400 iflib_init_locked(ctx);
2406 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2408 if_ctx_t ctx = if_getsoftc(ifp);
2411 IFDI_UPDATE_ADMIN_STATUS(ctx);
2412 IFDI_MEDIA_STATUS(ctx, ifmr);
2417 iflib_stop(if_ctx_t ctx)
2419 iflib_txq_t txq = ctx->ifc_txqs;
2420 iflib_rxq_t rxq = ctx->ifc_rxqs;
2421 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2422 if_shared_ctx_t sctx = ctx->ifc_sctx;
2423 iflib_dma_info_t di;
2427 /* Tell the stack that the interface is no longer active */
2428 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2430 IFDI_INTR_DISABLE(ctx);
2435 iflib_debug_reset();
2436 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2437 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2438 /* make sure all transmitters have completed before proceeding XXX */
2441 callout_stop(&txq->ift_timer);
2442 CALLOUT_UNLOCK(txq);
2444 /* clean any enqueued buffers */
2445 iflib_ifmp_purge(txq);
2446 /* Free any existing tx buffers. */
2447 for (j = 0; j < txq->ift_size; j++) {
2448 iflib_txsd_free(ctx, txq, j);
2450 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2451 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2452 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2453 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2454 txq->ift_pullups = 0;
2455 ifmp_ring_reset_stats(txq->ift_br);
2456 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2457 bzero((void *)di->idi_vaddr, di->idi_size);
2459 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2460 /* make sure all transmitters have completed before proceeding XXX */
2462 rxq->ifr_cq_cidx = 0;
2463 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2464 bzero((void *)di->idi_vaddr, di->idi_size);
2465 /* also resets the free lists pidx/cidx */
2466 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2467 iflib_fl_bufs_free(fl);
2471 static inline caddr_t
2472 calc_next_rxd(iflib_fl_t fl, int cidx)
2476 caddr_t start, end, cur, next;
2478 nrxd = fl->ifl_size;
2479 size = fl->ifl_rxd_size;
2480 start = fl->ifl_ifdi->idi_vaddr;
2482 if (__predict_false(size == 0))
2484 cur = start + size*cidx;
2485 end = start + size*nrxd;
2486 next = CACHE_PTR_NEXT(cur);
2487 return (next < end ? next : start);
2491 prefetch_pkts(iflib_fl_t fl, int cidx)
2494 int nrxd = fl->ifl_size;
2498 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2499 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2500 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2501 next_rxd = calc_next_rxd(fl, cidx);
2503 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2504 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2505 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2506 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2507 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2508 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2509 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2510 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2513 static struct mbuf *
2514 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2515 int *pf_rv, if_rxd_info_t ri)
2521 int flid, cidx, len, next;
2524 flid = irf->irf_flid;
2525 cidx = irf->irf_idx;
2526 fl = &rxq->ifr_fl[flid];
2528 m = fl->ifl_sds.ifsd_m[cidx];
2529 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2532 fl->ifl_m_dequeued++;
2534 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2535 prefetch_pkts(fl, cidx);
2536 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2537 prefetch(&fl->ifl_sds.ifsd_map[next]);
2538 map = fl->ifl_sds.ifsd_map[cidx];
2540 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2542 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2543 irf->irf_len != 0) {
2544 payload = *sd->ifsd_cl;
2545 payload += ri->iri_pad;
2546 len = ri->iri_len - ri->iri_pad;
2547 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2548 len | PFIL_MEMPTR | PFIL_IN, NULL);
2553 * The filter ate it. Everything is recycled.
2558 case PFIL_REALLOCED:
2560 * The filter copied it. Everything is recycled.
2562 m = pfil_mem2mbuf(payload);
2567 * Filter said it was OK, so receive like
2570 fl->ifl_sds.ifsd_m[cidx] = NULL;
2576 fl->ifl_sds.ifsd_m[cidx] = NULL;
2580 if (unload && irf->irf_len != 0)
2581 bus_dmamap_unload(fl->ifl_buf_tag, map);
2582 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2583 if (__predict_false(fl->ifl_cidx == 0))
2585 bit_clear(fl->ifl_rx_bitmap, cidx);
2589 static struct mbuf *
2590 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2592 struct mbuf *m, *mh, *mt;
2594 int *pf_rv_ptr, flags, i, padlen;
2603 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2606 MPASS(*sd->ifsd_cl != NULL);
2609 * Exclude zero-length frags & frags from
2610 * packets the filter has consumed or dropped
2612 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2613 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2615 /* everything saved here */
2620 /* XXX we can save the cluster here, but not the mbuf */
2621 m_init(m, M_NOWAIT, MT_DATA, 0);
2626 flags = M_PKTHDR|M_EXT;
2628 padlen = ri->iri_pad;
2633 /* assuming padding is only on the first fragment */
2637 *sd->ifsd_cl = NULL;
2639 /* Can these two be made one ? */
2640 m_init(m, M_NOWAIT, MT_DATA, flags);
2641 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2643 * These must follow m_init and m_cljset
2645 m->m_data += padlen;
2646 ri->iri_len -= padlen;
2647 m->m_len = ri->iri_frags[i].irf_len;
2648 } while (++i < ri->iri_nfrags);
2654 * Process one software descriptor
2656 static struct mbuf *
2657 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2663 /* should I merge this back in now that the two paths are basically duplicated? */
2664 if (ri->iri_nfrags == 1 &&
2665 ri->iri_frags[0].irf_len != 0 &&
2666 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2667 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2669 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2671 if (pf_rv == PFIL_PASS) {
2672 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2673 #ifndef __NO_STRICT_ALIGNMENT
2677 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2678 m->m_len = ri->iri_frags[0].irf_len;
2681 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2684 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2687 m->m_pkthdr.len = ri->iri_len;
2688 m->m_pkthdr.rcvif = ri->iri_ifp;
2689 m->m_flags |= ri->iri_flags;
2690 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2691 m->m_pkthdr.flowid = ri->iri_flowid;
2692 M_HASHTYPE_SET(m, ri->iri_rsstype);
2693 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2694 m->m_pkthdr.csum_data = ri->iri_csum_data;
2698 #if defined(INET6) || defined(INET)
2700 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2702 CURVNET_SET(lc->ifp->if_vnet);
2704 *v6 = V_ip6_forwarding;
2707 *v4 = V_ipforwarding;
2713 * Returns true if it's possible this packet could be LROed.
2714 * if it returns false, it is guaranteed that tcp_lro_rx()
2715 * would not return zero.
2718 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2720 struct ether_header *eh;
2722 eh = mtod(m, struct ether_header *);
2723 switch (eh->ether_type) {
2725 case htons(ETHERTYPE_IPV6):
2726 return (!v6_forwarding);
2729 case htons(ETHERTYPE_IP):
2730 return (!v4_forwarding);
2738 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2744 _task_fn_rx_watchdog(void *context)
2746 iflib_rxq_t rxq = context;
2748 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2752 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2755 if_ctx_t ctx = rxq->ifr_ctx;
2756 if_shared_ctx_t sctx = ctx->ifc_sctx;
2757 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2760 struct if_rxd_info ri;
2761 int err, budget_left, rx_bytes, rx_pkts;
2764 bool v4_forwarding, v6_forwarding, lro_possible;
2768 * XXX early demux data packets so that if_input processing only handles
2769 * acks in interrupt context
2771 struct mbuf *m, *mh, *mt, *mf;
2775 lro_possible = v4_forwarding = v6_forwarding = false;
2779 rx_pkts = rx_bytes = 0;
2780 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2781 cidxp = &rxq->ifr_cq_cidx;
2783 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2784 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2785 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2786 retval |= __iflib_fl_refill_all(ctx, fl);
2787 DBG_COUNTER_INC(rx_unavail);
2791 /* pfil needs the vnet to be set */
2792 CURVNET_SET_QUIET(ifp->if_vnet);
2793 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2794 if (__predict_false(!CTX_ACTIVE(ctx))) {
2795 DBG_COUNTER_INC(rx_ctx_inactive);
2799 * Reset client set fields to their default values
2802 ri.iri_qsidx = rxq->ifr_id;
2803 ri.iri_cidx = *cidxp;
2805 ri.iri_frags = rxq->ifr_frags;
2806 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2811 rx_bytes += ri.iri_len;
2812 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2813 *cidxp = ri.iri_cidx;
2814 /* Update our consumer index */
2815 /* XXX NB: shurd - check if this is still safe */
2816 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2817 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2818 /* was this only a completion queue message? */
2819 if (__predict_false(ri.iri_nfrags == 0))
2822 MPASS(ri.iri_nfrags != 0);
2823 MPASS(ri.iri_len != 0);
2825 /* will advance the cidx on the corresponding free lists */
2826 m = iflib_rxd_pkt_get(rxq, &ri);
2829 if (avail == 0 && budget_left)
2830 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2832 if (__predict_false(m == NULL))
2835 /* imm_pkt: -- cxgb */
2844 /* make sure that we can refill faster than drain */
2845 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2846 retval |= __iflib_fl_refill_all(ctx, fl);
2848 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2850 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2852 while (mh != NULL) {
2855 m->m_nextpkt = NULL;
2856 #ifndef __NO_STRICT_ALIGNMENT
2857 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2860 rx_bytes += m->m_pkthdr.len;
2862 #if defined(INET6) || defined(INET)
2864 if (!lro_possible) {
2865 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2866 if (lro_possible && mf != NULL) {
2867 ifp->if_input(ifp, mf);
2868 DBG_COUNTER_INC(rx_if_input);
2872 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2873 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2874 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2880 ifp->if_input(ifp, m);
2881 DBG_COUNTER_INC(rx_if_input);
2892 ifp->if_input(ifp, mf);
2893 DBG_COUNTER_INC(rx_if_input);
2896 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2897 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2900 * Flush any outstanding LRO work
2902 #if defined(INET6) || defined(INET)
2903 tcp_lro_flush_all(&rxq->ifr_lc);
2905 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2906 retval |= IFLIB_RXEOF_MORE;
2910 ctx->ifc_flags |= IFC_DO_RESET;
2911 iflib_admin_intr_deferred(ctx);
2916 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2917 static inline qidx_t
2918 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2920 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2921 qidx_t minthresh = txq->ift_size / 8;
2922 if (in_use > 4*minthresh)
2923 return (notify_count);
2924 if (in_use > 2*minthresh)
2925 return (notify_count >> 1);
2926 if (in_use > minthresh)
2927 return (notify_count >> 3);
2931 static inline qidx_t
2932 txq_max_rs_deferred(iflib_txq_t txq)
2934 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2935 qidx_t minthresh = txq->ift_size / 8;
2936 if (txq->ift_in_use > 4*minthresh)
2937 return (notify_count);
2938 if (txq->ift_in_use > 2*minthresh)
2939 return (notify_count >> 1);
2940 if (txq->ift_in_use > minthresh)
2941 return (notify_count >> 2);
2945 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2946 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2948 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2949 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2950 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2952 /* forward compatibility for cxgb */
2953 #define FIRST_QSET(ctx) 0
2954 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2955 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2956 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2957 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2959 /* XXX we should be setting this to something other than zero */
2960 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2961 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2962 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2965 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2971 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2972 if (ring || txq->ift_db_pending >= max) {
2973 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2974 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2976 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2977 txq->ift_db_pending = txq->ift_npending = 0;
2985 print_pkt(if_pkt_info_t pi)
2987 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2988 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2989 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2990 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2991 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2992 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2996 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2997 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2998 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2999 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3002 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3004 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3005 struct ether_vlan_header *eh;
3009 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3010 M_WRITABLE(m) == 0) {
3011 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3015 DBG_COUNTER_INC(tx_frees);
3021 * Determine where frame payload starts.
3022 * Jump over vlan headers if already present,
3023 * helpful for QinQ too.
3025 if (__predict_false(m->m_len < sizeof(*eh))) {
3027 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3030 eh = mtod(m, struct ether_vlan_header *);
3031 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3032 pi->ipi_etype = ntohs(eh->evl_proto);
3033 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3035 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3036 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3039 switch (pi->ipi_etype) {
3044 struct ip *ip = NULL;
3045 struct tcphdr *th = NULL;
3048 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3049 if (__predict_false(m->m_len < minthlen)) {
3051 * if this code bloat is causing too much of a hit
3052 * move it to a separate function and mark it noinline
3054 if (m->m_len == pi->ipi_ehdrlen) {
3057 if (n->m_len >= sizeof(*ip)) {
3058 ip = (struct ip *)n->m_data;
3059 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3060 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3063 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3065 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3069 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3071 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3072 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3073 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3076 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3077 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3078 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3080 pi->ipi_ip_hlen = ip->ip_hl << 2;
3081 pi->ipi_ipproto = ip->ip_p;
3082 pi->ipi_flags |= IPI_TX_IPV4;
3084 /* TCP checksum offload may require TCP header length */
3085 if (IS_TX_OFFLOAD4(pi)) {
3086 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3087 if (__predict_false(th == NULL)) {
3089 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3091 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3093 pi->ipi_tcp_hflags = th->th_flags;
3094 pi->ipi_tcp_hlen = th->th_off << 2;
3095 pi->ipi_tcp_seq = th->th_seq;
3098 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3101 * TSO always requires hardware checksum offload.
3103 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3104 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3105 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3106 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3107 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3109 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3113 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3120 case ETHERTYPE_IPV6:
3122 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3124 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3126 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3128 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3131 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3133 /* XXX-BZ this will go badly in case of ext hdrs. */
3134 pi->ipi_ipproto = ip6->ip6_nxt;
3135 pi->ipi_flags |= IPI_TX_IPV6;
3137 /* TCP checksum offload may require TCP header length */
3138 if (IS_TX_OFFLOAD6(pi)) {
3139 if (pi->ipi_ipproto == IPPROTO_TCP) {
3140 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3142 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3145 pi->ipi_tcp_hflags = th->th_flags;
3146 pi->ipi_tcp_hlen = th->th_off << 2;
3147 pi->ipi_tcp_seq = th->th_seq;
3150 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3153 * TSO always requires hardware checksum offload.
3155 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3156 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3157 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3164 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3165 pi->ipi_ip_hlen = 0;
3174 * If dodgy hardware rejects the scatter gather chain we've handed it
3175 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3178 static __noinline struct mbuf *
3179 iflib_remove_mbuf(iflib_txq_t txq)
3182 struct mbuf *m, **ifsd_m;
3184 ifsd_m = txq->ift_sds.ifsd_m;
3185 ntxd = txq->ift_size;
3186 pidx = txq->ift_pidx & (ntxd - 1);
3187 ifsd_m = txq->ift_sds.ifsd_m;
3189 ifsd_m[pidx] = NULL;
3190 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3191 if (txq->ift_sds.ifsd_tso_map != NULL)
3192 bus_dmamap_unload(txq->ift_tso_buf_tag,
3193 txq->ift_sds.ifsd_tso_map[pidx]);
3195 txq->ift_dequeued++;
3200 static inline caddr_t
3201 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3205 caddr_t start, end, cur, next;
3207 ntxd = txq->ift_size;
3208 size = txq->ift_txd_size[qid];
3209 start = txq->ift_ifdi[qid].idi_vaddr;
3211 if (__predict_false(size == 0))
3213 cur = start + size*cidx;
3214 end = start + size*ntxd;
3215 next = CACHE_PTR_NEXT(cur);
3216 return (next < end ? next : start);
3220 * Pad an mbuf to ensure a minimum ethernet frame size.
3221 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3223 static __noinline int
3224 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3227 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3228 * and ARP message is the smallest common payload I can think of
3230 static char pad[18]; /* just zeros */
3232 struct mbuf *new_head;
3234 if (!M_WRITABLE(*m_head)) {
3235 new_head = m_dup(*m_head, M_NOWAIT);
3236 if (new_head == NULL) {
3238 device_printf(dev, "cannot pad short frame, m_dup() failed");
3239 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3240 DBG_COUNTER_INC(tx_frees);
3247 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3248 n > 0; n -= sizeof(pad))
3249 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3254 device_printf(dev, "cannot pad short frame\n");
3255 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3256 DBG_COUNTER_INC(tx_frees);
3264 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3267 if_shared_ctx_t sctx;
3268 if_softc_ctx_t scctx;
3269 bus_dma_tag_t buf_tag;
3270 bus_dma_segment_t *segs;
3271 struct mbuf *m_head, **ifsd_m;
3274 struct if_pkt_info pi;
3276 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3279 sctx = ctx->ifc_sctx;
3280 scctx = &ctx->ifc_softc_ctx;
3281 segs = txq->ift_segs;
3282 ntxd = txq->ift_size;
3287 * If we're doing TSO the next descriptor to clean may be quite far ahead
3289 cidx = txq->ift_cidx;
3290 pidx = txq->ift_pidx;
3291 if (ctx->ifc_flags & IFC_PREFETCH) {
3292 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3293 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3294 next_txd = calc_next_txd(txq, cidx, 0);
3298 /* prefetch the next cache line of mbuf pointers and flags */
3299 prefetch(&txq->ift_sds.ifsd_m[next]);
3300 prefetch(&txq->ift_sds.ifsd_map[next]);
3301 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3303 map = txq->ift_sds.ifsd_map[pidx];
3304 ifsd_m = txq->ift_sds.ifsd_m;
3306 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3307 buf_tag = txq->ift_tso_buf_tag;
3308 max_segs = scctx->isc_tx_tso_segments_max;
3309 map = txq->ift_sds.ifsd_tso_map[pidx];
3310 MPASS(buf_tag != NULL);
3311 MPASS(max_segs > 0);
3313 buf_tag = txq->ift_buf_tag;
3314 max_segs = scctx->isc_tx_nsegments;
3315 map = txq->ift_sds.ifsd_map[pidx];
3317 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3318 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3319 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3321 DBG_COUNTER_INC(encap_txd_encap_fail);
3328 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3330 pi.ipi_qsidx = txq->ift_id;
3331 pi.ipi_len = m_head->m_pkthdr.len;
3332 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3333 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3335 /* deliberate bitwise OR to make one condition */
3336 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3337 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3338 DBG_COUNTER_INC(encap_txd_encap_fail);
3345 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3348 if (__predict_false(err)) {
3351 /* try collapse once and defrag once */
3353 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3354 /* try defrag if collapsing fails */
3359 txq->ift_mbuf_defrag++;
3360 m_head = m_defrag(*m_headp, M_NOWAIT);
3363 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3364 * failed to map an mbuf that was run through m_defrag
3367 if (__predict_false(m_head == NULL || remap > 1))
3374 txq->ift_no_tx_dma_setup++;
3377 txq->ift_no_tx_dma_setup++;
3379 DBG_COUNTER_INC(tx_frees);
3383 txq->ift_map_failed++;
3384 DBG_COUNTER_INC(encap_load_mbuf_fail);
3385 DBG_COUNTER_INC(encap_txd_encap_fail);
3388 ifsd_m[pidx] = m_head;
3390 * XXX assumes a 1 to 1 relationship between segments and
3391 * descriptors - this does not hold true on all drivers, e.g.
3394 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3395 txq->ift_no_desc_avail++;
3396 bus_dmamap_unload(buf_tag, map);
3397 DBG_COUNTER_INC(encap_txq_avail_fail);
3398 DBG_COUNTER_INC(encap_txd_encap_fail);
3399 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3400 GROUPTASK_ENQUEUE(&txq->ift_task);
3404 * On Intel cards we can greatly reduce the number of TX interrupts
3405 * we see by only setting report status on every Nth descriptor.
3406 * However, this also means that the driver will need to keep track
3407 * of the descriptors that RS was set on to check them for the DD bit.
3409 txq->ift_rs_pending += nsegs + 1;
3410 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3411 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3412 pi.ipi_flags |= IPI_TX_INTR;
3413 txq->ift_rs_pending = 0;
3417 pi.ipi_nsegs = nsegs;
3419 MPASS(pidx >= 0 && pidx < txq->ift_size);
3423 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3424 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3425 DBG_COUNTER_INC(tx_encap);
3426 MPASS(pi.ipi_new_pidx < txq->ift_size);
3428 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3429 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3430 ndesc += txq->ift_size;
3434 * drivers can need as many as
3437 MPASS(ndesc <= pi.ipi_nsegs + 2);
3438 MPASS(pi.ipi_new_pidx != pidx);
3440 txq->ift_in_use += ndesc;
3443 * We update the last software descriptor again here because there may
3444 * be a sentinel and/or there may be more mbufs than segments
3446 txq->ift_pidx = pi.ipi_new_pidx;
3447 txq->ift_npending += pi.ipi_ndescs;
3449 *m_headp = m_head = iflib_remove_mbuf(txq);
3451 txq->ift_txd_encap_efbig++;
3460 * err can't possibly be non-zero here, so we don't neet to test it
3461 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3466 txq->ift_mbuf_defrag_failed++;
3467 txq->ift_map_failed++;
3469 DBG_COUNTER_INC(tx_frees);
3471 DBG_COUNTER_INC(encap_txd_encap_fail);
3476 iflib_tx_desc_free(iflib_txq_t txq, int n)
3478 uint32_t qsize, cidx, mask, gen;
3479 struct mbuf *m, **ifsd_m;
3482 cidx = txq->ift_cidx;
3484 qsize = txq->ift_size;
3486 ifsd_m = txq->ift_sds.ifsd_m;
3487 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3491 prefetch(ifsd_m[(cidx + 3) & mask]);
3492 prefetch(ifsd_m[(cidx + 4) & mask]);
3494 if ((m = ifsd_m[cidx]) != NULL) {
3495 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3496 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3497 bus_dmamap_sync(txq->ift_tso_buf_tag,
3498 txq->ift_sds.ifsd_tso_map[cidx],
3499 BUS_DMASYNC_POSTWRITE);
3500 bus_dmamap_unload(txq->ift_tso_buf_tag,
3501 txq->ift_sds.ifsd_tso_map[cidx]);
3503 bus_dmamap_sync(txq->ift_buf_tag,
3504 txq->ift_sds.ifsd_map[cidx],
3505 BUS_DMASYNC_POSTWRITE);
3506 bus_dmamap_unload(txq->ift_buf_tag,
3507 txq->ift_sds.ifsd_map[cidx]);
3509 /* XXX we don't support any drivers that batch packets yet */
3510 MPASS(m->m_nextpkt == NULL);
3512 ifsd_m[cidx] = NULL;
3514 txq->ift_dequeued++;
3516 DBG_COUNTER_INC(tx_frees);
3518 if (__predict_false(++cidx == qsize)) {
3523 txq->ift_cidx = cidx;
3528 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3531 if_ctx_t ctx = txq->ift_ctx;
3533 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3534 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3537 * Need a rate-limiting check so that this isn't called every time
3539 iflib_tx_credits_update(ctx, txq);
3540 reclaim = DESC_RECLAIMABLE(txq);
3542 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3544 if (iflib_verbose_debug) {
3545 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3546 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3553 iflib_tx_desc_free(txq, reclaim);
3554 txq->ift_cleaned += reclaim;
3555 txq->ift_in_use -= reclaim;
3560 static struct mbuf **
3561 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3564 struct mbuf **items;
3567 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3568 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3570 prefetch(items[(cidx + offset) & (size-1)]);
3571 if (remaining > 1) {
3572 prefetch2cachelines(&items[next]);
3573 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3574 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3575 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3577 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3581 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3584 ifmp_ring_check_drainage(txq->ift_br, budget);
3588 iflib_txq_can_drain(struct ifmp_ring *r)
3590 iflib_txq_t txq = r->cookie;
3591 if_ctx_t ctx = txq->ift_ctx;
3593 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3595 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3596 BUS_DMASYNC_POSTREAD);
3597 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3602 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3604 iflib_txq_t txq = r->cookie;
3605 if_ctx_t ctx = txq->ift_ctx;
3606 if_t ifp = ctx->ifc_ifp;
3607 struct mbuf *m, **mp;
3608 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3609 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3610 bool do_prefetch, rang, ring;
3612 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3613 !LINK_ACTIVE(ctx))) {
3614 DBG_COUNTER_INC(txq_drain_notready);
3617 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3618 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3619 avail = IDXDIFF(pidx, cidx, r->size);
3620 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3621 DBG_COUNTER_INC(txq_drain_flushing);
3622 for (i = 0; i < avail; i++) {
3623 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3624 m_free(r->items[(cidx + i) & (r->size-1)]);
3625 r->items[(cidx + i) & (r->size-1)] = NULL;
3630 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3631 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3633 callout_stop(&txq->ift_timer);
3634 CALLOUT_UNLOCK(txq);
3635 DBG_COUNTER_INC(txq_drain_oactive);
3639 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3640 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3641 count = MIN(avail, TX_BATCH_SIZE);
3643 if (iflib_verbose_debug)
3644 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3645 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3647 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3648 txq_avail = TXQ_AVAIL(txq);
3650 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3651 int rem = do_prefetch ? count - i : 0;
3653 mp = _ring_peek_one(r, cidx, i, rem);
3654 MPASS(mp != NULL && *mp != NULL);
3655 if (__predict_false(*mp == (struct mbuf *)txq)) {
3659 in_use_prev = txq->ift_in_use;
3660 err = iflib_encap(txq, mp);
3661 if (__predict_false(err)) {
3662 /* no room - bail out */
3666 /* we can't send this packet - skip it */
3672 DBG_COUNTER_INC(tx_sent);
3673 bytes_sent += m->m_pkthdr.len;
3674 mcast_sent += !!(m->m_flags & M_MCAST);
3675 txq_avail = TXQ_AVAIL(txq);
3677 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3678 ETHER_BPF_MTAP(ifp, m);
3679 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3681 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3684 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3685 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3686 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3687 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3688 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3690 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3692 if (iflib_verbose_debug)
3693 printf("consumed=%d\n", consumed);
3699 iflib_txq_drain_always(struct ifmp_ring *r)
3705 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3713 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3715 callout_stop(&txq->ift_timer);
3716 CALLOUT_UNLOCK(txq);
3718 avail = IDXDIFF(pidx, cidx, r->size);
3719 for (i = 0; i < avail; i++) {
3720 mp = _ring_peek_one(r, cidx, i, avail - i);
3721 if (__predict_false(*mp == (struct mbuf *)txq))
3724 DBG_COUNTER_INC(tx_frees);
3726 MPASS(ifmp_ring_is_stalled(r) == 0);
3731 iflib_ifmp_purge(iflib_txq_t txq)
3733 struct ifmp_ring *r;
3736 r->drain = iflib_txq_drain_free;
3737 r->can_drain = iflib_txq_drain_always;
3739 ifmp_ring_check_drainage(r, r->size);
3741 r->drain = iflib_txq_drain;
3742 r->can_drain = iflib_txq_can_drain;
3746 _task_fn_tx(void *context)
3748 iflib_txq_t txq = context;
3749 if_ctx_t ctx = txq->ift_ctx;
3750 #if defined(ALTQ) || defined(DEV_NETMAP)
3751 if_t ifp = ctx->ifc_ifp;
3753 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3755 #ifdef IFLIB_DIAGNOSTICS
3756 txq->ift_cpu_exec_count[curcpu]++;
3758 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3761 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3762 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3763 BUS_DMASYNC_POSTREAD);
3764 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3765 netmap_tx_irq(ifp, txq->ift_id);
3766 if (ctx->ifc_flags & IFC_LEGACY)
3767 IFDI_INTR_ENABLE(ctx);
3769 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3774 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3775 iflib_altq_if_start(ifp);
3777 if (txq->ift_db_pending)
3778 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3780 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3782 * When abdicating, we always need to check drainage, not just when we don't enqueue
3785 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3786 if (ctx->ifc_flags & IFC_LEGACY)
3787 IFDI_INTR_ENABLE(ctx);
3789 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3793 _task_fn_rx(void *context)
3795 iflib_rxq_t rxq = context;
3796 if_ctx_t ctx = rxq->ifr_ctx;
3804 #ifdef IFLIB_DIAGNOSTICS
3805 rxq->ifr_cpu_exec_count[curcpu]++;
3807 DBG_COUNTER_INC(task_fn_rxs);
3808 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3811 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3812 if (nmirq != NM_IRQ_PASS) {
3813 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3817 budget = ctx->ifc_sysctl_rx_budget;
3819 budget = 16; /* XXX */
3820 more = iflib_rxeof(rxq, budget);
3824 if ((more & IFLIB_RXEOF_MORE) == 0) {
3825 if (ctx->ifc_flags & IFC_LEGACY)
3826 IFDI_INTR_ENABLE(ctx);
3828 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3829 DBG_COUNTER_INC(rx_intr_enables);
3831 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3834 if (more & IFLIB_RXEOF_MORE)
3835 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3836 else if (more & IFLIB_RXEOF_EMPTY)
3837 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3841 _task_fn_admin(void *context)
3843 if_ctx_t ctx = context;
3844 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3847 bool oactive, running, do_reset, do_watchdog, in_detach;
3848 uint32_t reset_on = hz / 2;
3851 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3852 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3853 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3854 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3855 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3856 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3859 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3865 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3867 callout_stop(&txq->ift_timer);
3868 CALLOUT_UNLOCK(txq);
3871 ctx->ifc_watchdog_events++;
3872 IFDI_WATCHDOG_RESET(ctx);
3874 IFDI_UPDATE_ADMIN_STATUS(ctx);
3875 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3878 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3879 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3881 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3883 IFDI_LINK_INTR_ENABLE(ctx);
3885 iflib_if_init_locked(ctx);
3888 if (LINK_ACTIVE(ctx) == 0)
3890 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3891 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3896 _task_fn_iov(void *context)
3898 if_ctx_t ctx = context;
3900 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3901 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3905 IFDI_VFLR_HANDLE(ctx);
3910 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3913 if_int_delay_info_t info;
3916 info = (if_int_delay_info_t)arg1;
3917 ctx = info->iidi_ctx;
3918 info->iidi_req = req;
3919 info->iidi_oidp = oidp;
3921 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3926 /*********************************************************************
3930 **********************************************************************/
3933 iflib_if_init_locked(if_ctx_t ctx)
3936 iflib_init_locked(ctx);
3941 iflib_if_init(void *arg)
3946 iflib_if_init_locked(ctx);
3951 iflib_if_transmit(if_t ifp, struct mbuf *m)
3953 if_ctx_t ctx = if_getsoftc(ifp);
3957 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3959 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3960 DBG_COUNTER_INC(tx_frees);
3965 MPASS(m->m_nextpkt == NULL);
3966 /* ALTQ-enabled interfaces always use queue 0. */
3968 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3969 qidx = QIDX(ctx, m);
3971 * XXX calculate buf_ring based on flowid (divvy up bits?)
3973 txq = &ctx->ifc_txqs[qidx];
3975 #ifdef DRIVER_BACKPRESSURE
3976 if (txq->ift_closed) {
3978 next = m->m_nextpkt;
3979 m->m_nextpkt = NULL;
3981 DBG_COUNTER_INC(tx_frees);
3993 next = next->m_nextpkt;
3994 } while (next != NULL);
3996 if (count > nitems(marr))
3997 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3998 /* XXX check nextpkt */
4000 /* XXX simplify for now */
4001 DBG_COUNTER_INC(tx_frees);
4004 for (next = m, i = 0; next != NULL; i++) {
4006 next = next->m_nextpkt;
4007 mp[i]->m_nextpkt = NULL;
4010 DBG_COUNTER_INC(tx_seen);
4011 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4014 GROUPTASK_ENQUEUE(&txq->ift_task);
4017 GROUPTASK_ENQUEUE(&txq->ift_task);
4018 /* support forthcoming later */
4019 #ifdef DRIVER_BACKPRESSURE
4020 txq->ift_closed = TRUE;
4022 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4024 DBG_COUNTER_INC(tx_frees);
4032 * The overall approach to integrating iflib with ALTQ is to continue to use
4033 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4034 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4035 * is redundant/unnecessary, but doing so minimizes the amount of
4036 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4037 * redundantly queueing to an intermediate mp_ring is swamped by the
4038 * performance limitations inherent in using ALTQ.
4040 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4041 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4042 * given interface. If ALTQ is enabled for an interface, then all
4043 * transmitted packets for that interface will be submitted to the ALTQ
4044 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4045 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4046 * update stats that the iflib machinery handles, and which is sensitve to
4047 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4048 * will be installed as the start routine for use by ALTQ facilities that
4049 * need to trigger queue drains on a scheduled basis.
4053 iflib_altq_if_start(if_t ifp)
4055 struct ifaltq *ifq = &ifp->if_snd;
4059 IFQ_DEQUEUE_NOLOCK(ifq, m);
4061 iflib_if_transmit(ifp, m);
4062 IFQ_DEQUEUE_NOLOCK(ifq, m);
4068 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4072 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4073 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4075 iflib_altq_if_start(ifp);
4077 err = iflib_if_transmit(ifp, m);
4084 iflib_if_qflush(if_t ifp)
4086 if_ctx_t ctx = if_getsoftc(ifp);
4087 iflib_txq_t txq = ctx->ifc_txqs;
4091 ctx->ifc_flags |= IFC_QFLUSH;
4093 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4094 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4095 iflib_txq_check_drain(txq, 0);
4097 ctx->ifc_flags &= ~IFC_QFLUSH;
4101 * When ALTQ is enabled, this will also take care of purging the
4108 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4109 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4110 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4111 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4114 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4116 if_ctx_t ctx = if_getsoftc(ifp);
4117 struct ifreq *ifr = (struct ifreq *)data;
4118 #if defined(INET) || defined(INET6)
4119 struct ifaddr *ifa = (struct ifaddr *)data;
4121 bool avoid_reset = false;
4122 int err = 0, reinit = 0, bits;
4127 if (ifa->ifa_addr->sa_family == AF_INET)
4131 if (ifa->ifa_addr->sa_family == AF_INET6)
4135 ** Calling init results in link renegotiation,
4136 ** so we avoid doing it when possible.
4139 if_setflagbits(ifp, IFF_UP,0);
4140 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4143 if (!(if_getflags(ifp) & IFF_NOARP))
4144 arp_ifinit(ifp, ifa);
4147 err = ether_ioctl(ifp, command, data);
4151 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4155 bits = if_getdrvflags(ifp);
4156 /* stop the driver and free any clusters before proceeding */
4159 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4161 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4162 ctx->ifc_flags |= IFC_MULTISEG;
4164 ctx->ifc_flags &= ~IFC_MULTISEG;
4166 err = if_setmtu(ifp, ifr->ifr_mtu);
4168 iflib_init_locked(ctx);
4170 if_setdrvflags(ifp, bits);
4176 if (if_getflags(ifp) & IFF_UP) {
4177 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4178 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4179 (IFF_PROMISC | IFF_ALLMULTI)) {
4180 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4184 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4187 ctx->ifc_if_flags = if_getflags(ifp);
4192 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4194 IFDI_INTR_DISABLE(ctx);
4195 IFDI_MULTI_SET(ctx);
4196 IFDI_INTR_ENABLE(ctx);
4202 IFDI_MEDIA_SET(ctx);
4207 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4211 struct ifi2creq i2c;
4213 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4216 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4220 if (i2c.len > sizeof(i2c.data)) {
4225 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4226 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4232 int mask, setmask, oldmask;
4234 oldmask = if_getcapenable(ifp);
4235 mask = ifr->ifr_reqcap ^ oldmask;
4236 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4239 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4241 setmask |= (mask & IFCAP_FLAGS);
4242 setmask |= (mask & IFCAP_WOL);
4245 * If any RX csum has changed, change all the ones that
4246 * are supported by the driver.
4248 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4249 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4250 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4254 * want to ensure that traffic has stopped before we change any of the flags
4258 bits = if_getdrvflags(ifp);
4259 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4262 if_togglecapenable(ifp, setmask);
4264 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4265 iflib_init_locked(ctx);
4267 if_setdrvflags(ifp, bits);
4274 case SIOCGPRIVATE_0:
4278 err = IFDI_PRIV_IOCTL(ctx, command, data);
4282 err = ether_ioctl(ifp, command, data);
4291 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4293 if_ctx_t ctx = if_getsoftc(ifp);
4295 return (IFDI_GET_COUNTER(ctx, cnt));
4298 /*********************************************************************
4300 * OTHER FUNCTIONS EXPORTED TO THE STACK
4302 **********************************************************************/
4305 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4307 if_ctx_t ctx = if_getsoftc(ifp);
4309 if ((void *)ctx != arg)
4312 if ((vtag == 0) || (vtag > 4095))
4315 if (iflib_in_detach(ctx))
4319 /* Driver may need all untagged packets to be flushed */
4320 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4322 IFDI_VLAN_REGISTER(ctx, vtag);
4323 /* Re-init to load the changes, if required */
4324 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4325 iflib_init_locked(ctx);
4330 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4332 if_ctx_t ctx = if_getsoftc(ifp);
4334 if ((void *)ctx != arg)
4337 if ((vtag == 0) || (vtag > 4095))
4341 /* Driver may need all tagged packets to be flushed */
4342 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4344 IFDI_VLAN_UNREGISTER(ctx, vtag);
4345 /* Re-init to load the changes, if required */
4346 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4347 iflib_init_locked(ctx);
4352 iflib_led_func(void *arg, int onoff)
4357 IFDI_LED_FUNC(ctx, onoff);
4361 /*********************************************************************
4363 * BUS FUNCTION DEFINITIONS
4365 **********************************************************************/
4368 iflib_device_probe(device_t dev)
4370 const pci_vendor_info_t *ent;
4371 if_shared_ctx_t sctx;
4372 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4373 uint16_t pci_vendor_id;
4375 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4378 pci_vendor_id = pci_get_vendor(dev);
4379 pci_device_id = pci_get_device(dev);
4380 pci_subvendor_id = pci_get_subvendor(dev);
4381 pci_subdevice_id = pci_get_subdevice(dev);
4382 pci_rev_id = pci_get_revid(dev);
4383 if (sctx->isc_parse_devinfo != NULL)
4384 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4386 ent = sctx->isc_vendor_info;
4387 while (ent->pvi_vendor_id != 0) {
4388 if (pci_vendor_id != ent->pvi_vendor_id) {
4392 if ((pci_device_id == ent->pvi_device_id) &&
4393 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4394 (ent->pvi_subvendor_id == 0)) &&
4395 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4396 (ent->pvi_subdevice_id == 0)) &&
4397 ((pci_rev_id == ent->pvi_rev_id) ||
4398 (ent->pvi_rev_id == 0))) {
4400 device_set_desc_copy(dev, ent->pvi_name);
4401 /* this needs to be changed to zero if the bus probing code
4402 * ever stops re-probing on best match because the sctx
4403 * may have its values over written by register calls
4404 * in subsequent probes
4406 return (BUS_PROBE_DEFAULT);
4414 iflib_device_probe_vendor(device_t dev)
4418 probe = iflib_device_probe(dev);
4419 if (probe == BUS_PROBE_DEFAULT)
4420 return (BUS_PROBE_VENDOR);
4426 iflib_reset_qvalues(if_ctx_t ctx)
4428 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4429 if_shared_ctx_t sctx = ctx->ifc_sctx;
4430 device_t dev = ctx->ifc_dev;
4433 if (ctx->ifc_sysctl_ntxqs != 0)
4434 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4435 if (ctx->ifc_sysctl_nrxqs != 0)
4436 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4438 for (i = 0; i < sctx->isc_ntxqs; i++) {
4439 if (ctx->ifc_sysctl_ntxds[i] != 0)
4440 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4442 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4445 for (i = 0; i < sctx->isc_nrxqs; i++) {
4446 if (ctx->ifc_sysctl_nrxds[i] != 0)
4447 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4449 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4452 for (i = 0; i < sctx->isc_nrxqs; i++) {
4453 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4454 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4455 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4456 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4458 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4459 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4460 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4461 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4463 if (!powerof2(scctx->isc_nrxd[i])) {
4464 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4465 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4466 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4470 for (i = 0; i < sctx->isc_ntxqs; i++) {
4471 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4472 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4473 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4474 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4476 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4477 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4478 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4479 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4481 if (!powerof2(scctx->isc_ntxd[i])) {
4482 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4483 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4484 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4490 iflib_add_pfil(if_ctx_t ctx)
4492 struct pfil_head *pfil;
4493 struct pfil_head_args pa;
4497 pa.pa_version = PFIL_VERSION;
4498 pa.pa_flags = PFIL_IN;
4499 pa.pa_type = PFIL_TYPE_ETHERNET;
4500 pa.pa_headname = ctx->ifc_ifp->if_xname;
4501 pfil = pfil_head_register(&pa);
4503 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4509 iflib_rem_pfil(if_ctx_t ctx)
4511 struct pfil_head *pfil;
4515 rxq = ctx->ifc_rxqs;
4517 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4520 pfil_head_unregister(pfil);
4524 get_ctx_core_offset(if_ctx_t ctx)
4526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4527 struct cpu_offset *op;
4529 uint16_t ret = ctx->ifc_sysctl_core_offset;
4531 if (ret != CORE_OFFSET_UNSPECIFIED)
4534 if (ctx->ifc_sysctl_separate_txrx)
4535 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4537 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4539 mtx_lock(&cpu_offset_mtx);
4540 SLIST_FOREACH(op, &cpu_offsets, entries) {
4541 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4544 MPASS(op->refcount < UINT_MAX);
4549 if (ret == CORE_OFFSET_UNSPECIFIED) {
4551 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4554 device_printf(ctx->ifc_dev,
4555 "allocation for cpu offset failed.\n");
4559 CPU_COPY(&ctx->ifc_cpus, &op->set);
4560 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4563 mtx_unlock(&cpu_offset_mtx);
4569 unref_ctx_core_offset(if_ctx_t ctx)
4571 struct cpu_offset *op, *top;
4573 mtx_lock(&cpu_offset_mtx);
4574 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4575 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4576 MPASS(op->refcount > 0);
4578 if (op->refcount == 0) {
4579 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4585 mtx_unlock(&cpu_offset_mtx);
4589 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4593 if_softc_ctx_t scctx;
4594 kobjop_desc_t kobj_desc;
4595 kobj_method_t *kobj_method;
4597 uint16_t main_rxq, main_txq;
4599 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4602 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4603 device_set_softc(dev, ctx);
4604 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4607 ctx->ifc_sctx = sctx;
4609 ctx->ifc_softc = sc;
4611 if ((err = iflib_register(ctx)) != 0) {
4612 device_printf(dev, "iflib_register failed %d\n", err);
4615 iflib_add_device_sysctl_pre(ctx);
4617 scctx = &ctx->ifc_softc_ctx;
4620 iflib_reset_qvalues(ctx);
4622 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4623 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4626 _iflib_pre_assert(scctx);
4627 ctx->ifc_txrx = *scctx->isc_txrx;
4629 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4630 ctx->ifc_mediap = scctx->isc_media;
4633 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4634 MPASS(scctx->isc_tx_csum_flags);
4637 if_setcapabilities(ifp,
4638 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4639 if_setcapenable(ifp,
4640 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4642 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4643 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4644 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4645 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4647 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4648 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4650 /* XXX change for per-queue sizes */
4651 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4652 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4654 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4655 MAX_SINGLE_PACKET_FRACTION)
4656 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4657 MAX_SINGLE_PACKET_FRACTION);
4658 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4659 MAX_SINGLE_PACKET_FRACTION)
4660 scctx->isc_tx_tso_segments_max = max(1,
4661 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4663 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4664 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4666 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4669 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4672 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4673 * into account. In the worst case, each of these calls will
4674 * add another mbuf and, thus, the requirement for another DMA
4675 * segment. So for best performance, it doesn't make sense to
4676 * advertize a maximum of TSO segments that typically will
4677 * require defragmentation in iflib_encap().
4679 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4680 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4682 if (scctx->isc_rss_table_size == 0)
4683 scctx->isc_rss_table_size = 64;
4684 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4686 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4687 /* XXX format name */
4688 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4689 NULL, NULL, "admin");
4691 /* Set up cpu set. If it fails, use the set of all CPUs. */
4692 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4693 device_printf(dev, "Unable to fetch CPU list\n");
4694 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4696 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4699 ** Now set up MSI or MSI-X, should return us the number of supported
4700 ** vectors (will be 1 for a legacy interrupt and MSI).
4702 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4703 msix = scctx->isc_vectors;
4704 } else if (scctx->isc_msix_bar != 0)
4706 * The simple fact that isc_msix_bar is not 0 does not mean we
4707 * we have a good value there that is known to work.
4709 msix = iflib_msix_init(ctx);
4711 scctx->isc_vectors = 1;
4712 scctx->isc_ntxqsets = 1;
4713 scctx->isc_nrxqsets = 1;
4714 scctx->isc_intr = IFLIB_INTR_LEGACY;
4717 /* Get memory for the station queues */
4718 if ((err = iflib_queues_alloc(ctx))) {
4719 device_printf(dev, "Unable to allocate queue memory\n");
4720 goto fail_intr_free;
4723 if ((err = iflib_qset_structures_setup(ctx)))
4727 * Now that we know how many queues there are, get the core offset.
4729 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4733 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4734 * aren't the default NULL implementation.
4736 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4737 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4739 if (kobj_method == &kobj_desc->deflt) {
4741 "MSI-X requires ifdi_rx_queue_intr_enable method");
4745 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4746 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4748 if (kobj_method == &kobj_desc->deflt) {
4750 "MSI-X requires ifdi_tx_queue_intr_enable method");
4756 * Assign the MSI-X vectors.
4757 * Note that the default NULL ifdi_msix_intr_assign method will
4760 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4762 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4766 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4768 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4772 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4773 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4778 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4780 goto fail_intr_free;
4783 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4785 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4786 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4791 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4792 * This must appear after the call to ether_ifattach() because
4793 * ether_ifattach() sets if_hdrlen to the default value.
4795 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4796 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4798 if ((err = iflib_netmap_attach(ctx))) {
4799 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4804 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4806 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4807 iflib_add_device_sysctl_post(ctx);
4808 iflib_add_pfil(ctx);
4809 ctx->ifc_flags |= IFC_INIT_DONE;
4815 ether_ifdetach(ctx->ifc_ifp);
4817 iflib_free_intr_mem(ctx);
4819 iflib_tx_structures_free(ctx);
4820 iflib_rx_structures_free(ctx);
4821 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4825 iflib_deregister(ctx);
4827 device_set_softc(ctx->ifc_dev, NULL);
4828 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4829 free(ctx->ifc_softc, M_IFLIB);
4835 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4836 struct iflib_cloneattach_ctx *clctx)
4841 if_softc_ctx_t scctx;
4847 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4848 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4849 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4850 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4851 ctx->ifc_flags |= IFC_PSEUDO;
4853 ctx->ifc_sctx = sctx;
4854 ctx->ifc_softc = sc;
4857 if ((err = iflib_register(ctx)) != 0) {
4858 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4861 iflib_add_device_sysctl_pre(ctx);
4863 scctx = &ctx->ifc_softc_ctx;
4866 iflib_reset_qvalues(ctx);
4868 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4869 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4872 if (sctx->isc_flags & IFLIB_GEN_MAC)
4873 ether_gen_addr(ifp, &ctx->ifc_mac);
4874 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4875 clctx->cc_params)) != 0) {
4876 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4880 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4881 MPASS(scctx->isc_tx_csum_flags);
4884 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4885 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4887 ifp->if_flags |= IFF_NOGROUP;
4888 if (sctx->isc_flags & IFLIB_PSEUDO) {
4889 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4890 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4891 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4892 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4894 if_attach(ctx->ifc_ifp);
4895 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4898 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4899 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4905 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4906 * This must appear after the call to ether_ifattach() because
4907 * ether_ifattach() sets if_hdrlen to the default value.
4909 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4910 if_setifheaderlen(ifp,
4911 sizeof(struct ether_vlan_header));
4913 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4914 iflib_add_device_sysctl_post(ctx);
4915 ctx->ifc_flags |= IFC_INIT_DONE;
4919 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4920 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4921 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4923 _iflib_pre_assert(scctx);
4924 ctx->ifc_txrx = *scctx->isc_txrx;
4926 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4927 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4928 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4929 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4931 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4932 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4934 /* XXX change for per-queue sizes */
4935 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4936 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4938 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4939 MAX_SINGLE_PACKET_FRACTION)
4940 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4941 MAX_SINGLE_PACKET_FRACTION);
4942 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4943 MAX_SINGLE_PACKET_FRACTION)
4944 scctx->isc_tx_tso_segments_max = max(1,
4945 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4947 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4948 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4950 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4953 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4956 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4957 * into account. In the worst case, each of these calls will
4958 * add another mbuf and, thus, the requirement for another DMA
4959 * segment. So for best performance, it doesn't make sense to
4960 * advertize a maximum of TSO segments that typically will
4961 * require defragmentation in iflib_encap().
4963 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4964 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4966 if (scctx->isc_rss_table_size == 0)
4967 scctx->isc_rss_table_size = 64;
4968 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4970 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4971 /* XXX format name */
4972 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4973 NULL, NULL, "admin");
4975 /* XXX --- can support > 1 -- but keep it simple for now */
4976 scctx->isc_intr = IFLIB_INTR_LEGACY;
4978 /* Get memory for the station queues */
4979 if ((err = iflib_queues_alloc(ctx))) {
4980 device_printf(dev, "Unable to allocate queue memory\n");
4981 goto fail_iflib_detach;
4984 if ((err = iflib_qset_structures_setup(ctx))) {
4985 device_printf(dev, "qset structure setup failed %d\n", err);
4990 * XXX What if anything do we want to do about interrupts?
4992 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4993 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4994 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4999 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5000 * This must appear after the call to ether_ifattach() because
5001 * ether_ifattach() sets if_hdrlen to the default value.
5003 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5004 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5006 /* XXX handle more than one queue */
5007 for (i = 0; i < scctx->isc_nrxqsets; i++)
5008 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5012 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5013 iflib_add_device_sysctl_post(ctx);
5014 ctx->ifc_flags |= IFC_INIT_DONE;
5019 ether_ifdetach(ctx->ifc_ifp);
5021 iflib_tx_structures_free(ctx);
5022 iflib_rx_structures_free(ctx);
5027 iflib_deregister(ctx);
5029 free(ctx->ifc_softc, M_IFLIB);
5035 iflib_pseudo_deregister(if_ctx_t ctx)
5037 if_t ifp = ctx->ifc_ifp;
5038 if_shared_ctx_t sctx = ctx->ifc_sctx;
5042 struct taskqgroup *tqg;
5045 /* Unregister VLAN event handlers early */
5046 iflib_unregister_vlan_handlers(ctx);
5048 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5049 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5053 ether_ifdetach(ifp);
5055 /* XXX drain any dependent tasks */
5056 tqg = qgroup_if_io_tqg;
5057 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5058 callout_drain(&txq->ift_timer);
5059 if (txq->ift_task.gt_uniq != NULL)
5060 taskqgroup_detach(tqg, &txq->ift_task);
5062 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5063 callout_drain(&rxq->ifr_watchdog);
5064 if (rxq->ifr_task.gt_uniq != NULL)
5065 taskqgroup_detach(tqg, &rxq->ifr_task);
5067 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5068 free(fl->ifl_rx_bitmap, M_IFLIB);
5070 tqg = qgroup_if_config_tqg;
5071 if (ctx->ifc_admin_task.gt_uniq != NULL)
5072 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5073 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5074 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5076 iflib_tx_structures_free(ctx);
5077 iflib_rx_structures_free(ctx);
5079 iflib_deregister(ctx);
5081 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5082 free(ctx->ifc_softc, M_IFLIB);
5088 iflib_device_attach(device_t dev)
5091 if_shared_ctx_t sctx;
5093 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5096 pci_enable_busmaster(dev);
5098 return (iflib_device_register(dev, NULL, sctx, &ctx));
5102 iflib_device_deregister(if_ctx_t ctx)
5104 if_t ifp = ctx->ifc_ifp;
5107 device_t dev = ctx->ifc_dev;
5109 struct taskqgroup *tqg;
5112 /* Make sure VLANS are not using driver */
5113 if (if_vlantrunkinuse(ifp)) {
5114 device_printf(dev, "Vlan in use, detach first\n");
5118 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5119 device_printf(dev, "SR-IOV in use; detach first.\n");
5125 ctx->ifc_flags |= IFC_IN_DETACH;
5128 /* Unregister VLAN handlers before calling iflib_stop() */
5129 iflib_unregister_vlan_handlers(ctx);
5131 iflib_netmap_detach(ifp);
5132 ether_ifdetach(ifp);
5138 iflib_rem_pfil(ctx);
5139 if (ctx->ifc_led_dev != NULL)
5140 led_destroy(ctx->ifc_led_dev);
5141 /* XXX drain any dependent tasks */
5142 tqg = qgroup_if_io_tqg;
5143 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5144 callout_drain(&txq->ift_timer);
5145 if (txq->ift_task.gt_uniq != NULL)
5146 taskqgroup_detach(tqg, &txq->ift_task);
5148 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5149 if (rxq->ifr_task.gt_uniq != NULL)
5150 taskqgroup_detach(tqg, &rxq->ifr_task);
5152 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5153 free(fl->ifl_rx_bitmap, M_IFLIB);
5155 tqg = qgroup_if_config_tqg;
5156 if (ctx->ifc_admin_task.gt_uniq != NULL)
5157 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5158 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5159 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5164 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5165 iflib_free_intr_mem(ctx);
5167 bus_generic_detach(dev);
5169 iflib_tx_structures_free(ctx);
5170 iflib_rx_structures_free(ctx);
5172 iflib_deregister(ctx);
5174 device_set_softc(ctx->ifc_dev, NULL);
5175 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5176 free(ctx->ifc_softc, M_IFLIB);
5177 unref_ctx_core_offset(ctx);
5183 iflib_free_intr_mem(if_ctx_t ctx)
5186 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5187 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5189 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5190 pci_release_msi(ctx->ifc_dev);
5192 if (ctx->ifc_msix_mem != NULL) {
5193 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5194 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5195 ctx->ifc_msix_mem = NULL;
5200 iflib_device_detach(device_t dev)
5202 if_ctx_t ctx = device_get_softc(dev);
5204 return (iflib_device_deregister(ctx));
5208 iflib_device_suspend(device_t dev)
5210 if_ctx_t ctx = device_get_softc(dev);
5216 return bus_generic_suspend(dev);
5219 iflib_device_shutdown(device_t dev)
5221 if_ctx_t ctx = device_get_softc(dev);
5227 return bus_generic_suspend(dev);
5232 iflib_device_resume(device_t dev)
5234 if_ctx_t ctx = device_get_softc(dev);
5235 iflib_txq_t txq = ctx->ifc_txqs;
5239 iflib_if_init_locked(ctx);
5241 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5242 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5244 return (bus_generic_resume(dev));
5248 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5251 if_ctx_t ctx = device_get_softc(dev);
5254 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5261 iflib_device_iov_uninit(device_t dev)
5263 if_ctx_t ctx = device_get_softc(dev);
5266 IFDI_IOV_UNINIT(ctx);
5271 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5274 if_ctx_t ctx = device_get_softc(dev);
5277 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5283 /*********************************************************************
5285 * MODULE FUNCTION DEFINITIONS
5287 **********************************************************************/
5290 * - Start a fast taskqueue thread for each core
5291 * - Start a taskqueue for control operations
5294 iflib_module_init(void)
5300 iflib_module_event_handler(module_t mod, int what, void *arg)
5306 if ((err = iflib_module_init()) != 0)
5312 return (EOPNOTSUPP);
5318 /*********************************************************************
5320 * PUBLIC FUNCTION DEFINITIONS
5321 * ordered as in iflib.h
5323 **********************************************************************/
5327 _iflib_assert(if_shared_ctx_t sctx)
5331 MPASS(sctx->isc_tx_maxsize);
5332 MPASS(sctx->isc_tx_maxsegsize);
5334 MPASS(sctx->isc_rx_maxsize);
5335 MPASS(sctx->isc_rx_nsegments);
5336 MPASS(sctx->isc_rx_maxsegsize);
5338 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5339 for (i = 0; i < sctx->isc_nrxqs; i++) {
5340 MPASS(sctx->isc_nrxd_min[i]);
5341 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5342 MPASS(sctx->isc_nrxd_max[i]);
5343 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5344 MPASS(sctx->isc_nrxd_default[i]);
5345 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5348 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5349 for (i = 0; i < sctx->isc_ntxqs; i++) {
5350 MPASS(sctx->isc_ntxd_min[i]);
5351 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5352 MPASS(sctx->isc_ntxd_max[i]);
5353 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5354 MPASS(sctx->isc_ntxd_default[i]);
5355 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5360 _iflib_pre_assert(if_softc_ctx_t scctx)
5363 MPASS(scctx->isc_txrx->ift_txd_encap);
5364 MPASS(scctx->isc_txrx->ift_txd_flush);
5365 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5366 MPASS(scctx->isc_txrx->ift_rxd_available);
5367 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5368 MPASS(scctx->isc_txrx->ift_rxd_refill);
5369 MPASS(scctx->isc_txrx->ift_rxd_flush);
5373 iflib_register(if_ctx_t ctx)
5375 if_shared_ctx_t sctx = ctx->ifc_sctx;
5376 driver_t *driver = sctx->isc_driver;
5377 device_t dev = ctx->ifc_dev;
5382 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5383 _iflib_assert(sctx);
5386 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5387 if (sctx->isc_flags & IFLIB_PSEUDO) {
5388 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5394 ifp = ctx->ifc_ifp = if_alloc(type);
5396 device_printf(dev, "can not allocate ifnet structure\n");
5401 * Initialize our context's device specific methods
5403 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5404 kobj_class_compile((kobj_class_t) driver);
5406 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5407 if_setsoftc(ifp, ctx);
5408 if_setdev(ifp, dev);
5409 if_setinitfn(ifp, iflib_if_init);
5410 if_setioctlfn(ifp, iflib_if_ioctl);
5412 if_setstartfn(ifp, iflib_altq_if_start);
5413 if_settransmitfn(ifp, iflib_altq_if_transmit);
5414 if_setsendqready(ifp);
5416 if_settransmitfn(ifp, iflib_if_transmit);
5418 if_setqflushfn(ifp, iflib_if_qflush);
5419 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5421 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5422 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5423 iflags |= IFF_POINTOPOINT;
5425 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5426 if_setflags(ifp, iflags);
5427 ctx->ifc_vlan_attach_event =
5428 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5429 EVENTHANDLER_PRI_FIRST);
5430 ctx->ifc_vlan_detach_event =
5431 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5432 EVENTHANDLER_PRI_FIRST);
5434 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5435 ctx->ifc_mediap = &ctx->ifc_media;
5436 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5437 iflib_media_change, iflib_media_status);
5443 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5445 /* Unregister VLAN events */
5446 if (ctx->ifc_vlan_attach_event != NULL) {
5447 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5448 ctx->ifc_vlan_attach_event = NULL;
5450 if (ctx->ifc_vlan_detach_event != NULL) {
5451 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5452 ctx->ifc_vlan_detach_event = NULL;
5458 iflib_deregister(if_ctx_t ctx)
5460 if_t ifp = ctx->ifc_ifp;
5462 /* Remove all media */
5463 ifmedia_removeall(&ctx->ifc_media);
5465 /* Ensure that VLAN event handlers are unregistered */
5466 iflib_unregister_vlan_handlers(ctx);
5468 /* Release kobject reference */
5469 kobj_delete((kobj_t) ctx, NULL);
5471 /* Free the ifnet structure */
5474 STATE_LOCK_DESTROY(ctx);
5476 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5477 CTX_LOCK_DESTROY(ctx);
5481 iflib_queues_alloc(if_ctx_t ctx)
5483 if_shared_ctx_t sctx = ctx->ifc_sctx;
5484 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5485 device_t dev = ctx->ifc_dev;
5486 int nrxqsets = scctx->isc_nrxqsets;
5487 int ntxqsets = scctx->isc_ntxqsets;
5490 iflib_fl_t fl = NULL;
5491 int i, j, cpu, err, txconf, rxconf;
5492 iflib_dma_info_t ifdip;
5493 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5494 uint32_t *txqsizes = scctx->isc_txqsizes;
5495 uint8_t nrxqs = sctx->isc_nrxqs;
5496 uint8_t ntxqs = sctx->isc_ntxqs;
5497 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5501 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5502 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5504 /* Allocate the TX ring struct memory */
5505 if (!(ctx->ifc_txqs =
5506 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5507 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5508 device_printf(dev, "Unable to allocate TX ring memory\n");
5513 /* Now allocate the RX */
5514 if (!(ctx->ifc_rxqs =
5515 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5516 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5517 device_printf(dev, "Unable to allocate RX ring memory\n");
5522 txq = ctx->ifc_txqs;
5523 rxq = ctx->ifc_rxqs;
5526 * XXX handle allocation failure
5528 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5529 /* Set up some basics */
5531 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5532 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5534 "Unable to allocate TX DMA info memory\n");
5538 txq->ift_ifdi = ifdip;
5539 for (j = 0; j < ntxqs; j++, ifdip++) {
5540 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5542 "Unable to allocate TX descriptors\n");
5546 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5547 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5551 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5552 txq->ift_br_offset = 1;
5554 txq->ift_br_offset = 0;
5557 txq->ift_timer.c_cpu = cpu;
5559 if (iflib_txsd_alloc(txq)) {
5560 device_printf(dev, "Critical Failure setting up TX buffers\n");
5565 /* Initialize the TX lock */
5566 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5567 device_get_nameunit(dev), txq->ift_id);
5568 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5569 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5571 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5572 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5574 /* XXX free any allocated rings */
5575 device_printf(dev, "Unable to allocate buf_ring\n");
5580 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5581 /* Set up some basics */
5582 callout_init(&rxq->ifr_watchdog, 1);
5584 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5585 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5587 "Unable to allocate RX DMA info memory\n");
5592 rxq->ifr_ifdi = ifdip;
5593 /* XXX this needs to be changed if #rx queues != #tx queues */
5594 rxq->ifr_ntxqirq = 1;
5595 rxq->ifr_txqid[0] = i;
5596 for (j = 0; j < nrxqs; j++, ifdip++) {
5597 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5599 "Unable to allocate RX descriptors\n");
5603 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5607 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5608 rxq->ifr_fl_offset = 1;
5610 rxq->ifr_fl_offset = 0;
5612 rxq->ifr_nfl = nfree_lists;
5614 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5615 device_printf(dev, "Unable to allocate free list memory\n");
5620 for (j = 0; j < nfree_lists; j++) {
5621 fl[j].ifl_rxq = rxq;
5623 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5624 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5626 /* Allocate receive buffers for the ring */
5627 if (iflib_rxsd_alloc(rxq)) {
5629 "Critical Failure setting up receive buffers\n");
5634 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5635 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5640 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5641 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5642 for (i = 0; i < ntxqsets; i++) {
5643 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5645 for (j = 0; j < ntxqs; j++, di++) {
5646 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5647 paddrs[i*ntxqs + j] = di->idi_paddr;
5650 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5651 device_printf(ctx->ifc_dev,
5652 "Unable to allocate device TX queue\n");
5653 iflib_tx_structures_free(ctx);
5654 free(vaddrs, M_IFLIB);
5655 free(paddrs, M_IFLIB);
5658 free(vaddrs, M_IFLIB);
5659 free(paddrs, M_IFLIB);
5662 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5663 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5664 for (i = 0; i < nrxqsets; i++) {
5665 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5667 for (j = 0; j < nrxqs; j++, di++) {
5668 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5669 paddrs[i*nrxqs + j] = di->idi_paddr;
5672 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5673 device_printf(ctx->ifc_dev,
5674 "Unable to allocate device RX queue\n");
5675 iflib_tx_structures_free(ctx);
5676 free(vaddrs, M_IFLIB);
5677 free(paddrs, M_IFLIB);
5680 free(vaddrs, M_IFLIB);
5681 free(paddrs, M_IFLIB);
5685 /* XXX handle allocation failure changes */
5689 if (ctx->ifc_rxqs != NULL)
5690 free(ctx->ifc_rxqs, M_IFLIB);
5691 ctx->ifc_rxqs = NULL;
5692 if (ctx->ifc_txqs != NULL)
5693 free(ctx->ifc_txqs, M_IFLIB);
5694 ctx->ifc_txqs = NULL;
5700 iflib_tx_structures_setup(if_ctx_t ctx)
5702 iflib_txq_t txq = ctx->ifc_txqs;
5705 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5706 iflib_txq_setup(txq);
5712 iflib_tx_structures_free(if_ctx_t ctx)
5714 iflib_txq_t txq = ctx->ifc_txqs;
5715 if_shared_ctx_t sctx = ctx->ifc_sctx;
5718 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5719 for (j = 0; j < sctx->isc_ntxqs; j++)
5720 iflib_dma_free(&txq->ift_ifdi[j]);
5721 iflib_txq_destroy(txq);
5723 free(ctx->ifc_txqs, M_IFLIB);
5724 ctx->ifc_txqs = NULL;
5725 IFDI_QUEUES_FREE(ctx);
5728 /*********************************************************************
5730 * Initialize all receive rings.
5732 **********************************************************************/
5734 iflib_rx_structures_setup(if_ctx_t ctx)
5736 iflib_rxq_t rxq = ctx->ifc_rxqs;
5738 #if defined(INET6) || defined(INET)
5742 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5743 #if defined(INET6) || defined(INET)
5744 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5745 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5746 TCP_LRO_ENTRIES, min(1024,
5747 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5749 device_printf(ctx->ifc_dev,
5750 "LRO Initialization failed!\n");
5755 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5758 #if defined(INET6) || defined(INET)
5761 * Free LRO resources allocated so far, we will only handle
5762 * the rings that completed, the failing case will have
5763 * cleaned up for itself. 'q' failed, so its the terminus.
5765 rxq = ctx->ifc_rxqs;
5766 for (i = 0; i < q; ++i, rxq++) {
5767 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5768 tcp_lro_free(&rxq->ifr_lc);
5774 /*********************************************************************
5776 * Free all receive rings.
5778 **********************************************************************/
5780 iflib_rx_structures_free(if_ctx_t ctx)
5782 iflib_rxq_t rxq = ctx->ifc_rxqs;
5783 if_shared_ctx_t sctx = ctx->ifc_sctx;
5786 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5787 for (j = 0; j < sctx->isc_nrxqs; j++)
5788 iflib_dma_free(&rxq->ifr_ifdi[j]);
5789 iflib_rx_sds_free(rxq);
5790 #if defined(INET6) || defined(INET)
5791 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5792 tcp_lro_free(&rxq->ifr_lc);
5795 free(ctx->ifc_rxqs, M_IFLIB);
5796 ctx->ifc_rxqs = NULL;
5800 iflib_qset_structures_setup(if_ctx_t ctx)
5805 * It is expected that the caller takes care of freeing queues if this
5808 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5809 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5813 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5814 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5820 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5821 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5824 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5829 find_nth(if_ctx_t ctx, int qid)
5832 int i, cpuid, eqid, count;
5834 CPU_COPY(&ctx->ifc_cpus, &cpus);
5835 count = CPU_COUNT(&cpus);
5837 /* clear up to the qid'th bit */
5838 for (i = 0; i < eqid; i++) {
5839 cpuid = CPU_FFS(&cpus);
5841 CPU_CLR(cpuid-1, &cpus);
5843 cpuid = CPU_FFS(&cpus);
5849 extern struct cpu_group *cpu_top; /* CPU topology */
5852 find_child_with_core(int cpu, struct cpu_group *grp)
5856 if (grp->cg_children == 0)
5859 MPASS(grp->cg_child);
5860 for (i = 0; i < grp->cg_children; i++) {
5861 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5869 * Find the nth "close" core to the specified core
5870 * "close" is defined as the deepest level that shares
5871 * at least an L2 cache. With threads, this will be
5872 * threads on the same core. If the shared cache is L3
5873 * or higher, simply returns the same core.
5876 find_close_core(int cpu, int core_offset)
5878 struct cpu_group *grp;
5887 while ((i = find_child_with_core(cpu, grp)) != -1) {
5888 /* If the child only has one cpu, don't descend */
5889 if (grp->cg_child[i].cg_count <= 1)
5891 grp = &grp->cg_child[i];
5894 /* If they don't share at least an L2 cache, use the same CPU */
5895 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5899 CPU_COPY(&grp->cg_mask, &cs);
5901 /* Add the selected CPU offset to core offset. */
5902 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5903 if (fcpu - 1 == cpu)
5905 CPU_CLR(fcpu - 1, &cs);
5911 CPU_COPY(&grp->cg_mask, &cs);
5912 for (i = core_offset % grp->cg_count; i > 0; i--) {
5913 MPASS(CPU_FFS(&cs));
5914 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5916 MPASS(CPU_FFS(&cs));
5917 return CPU_FFS(&cs) - 1;
5921 find_close_core(int cpu, int core_offset __unused)
5928 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5932 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5933 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5934 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5936 case IFLIB_INTR_RXTX:
5937 /* RX queues get the specified core */
5938 return qid / CPU_COUNT(&ctx->ifc_cpus);
5944 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5945 #define find_close_core(cpuid, tid) CPU_FIRST()
5946 #define find_nth(ctx, gid) CPU_FIRST()
5949 /* Just to avoid copy/paste */
5951 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5952 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5956 int co, cpuid, err, tid;
5959 co = ctx->ifc_sysctl_core_offset;
5960 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5961 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5962 cpuid = find_nth(ctx, qid + co);
5963 tid = get_core_offset(ctx, type, qid);
5965 device_printf(dev, "get_core_offset failed\n");
5966 return (EOPNOTSUPP);
5968 cpuid = find_close_core(cpuid, tid);
5969 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5972 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5976 if (cpuid > ctx->ifc_cpuid_highest)
5977 ctx->ifc_cpuid_highest = cpuid;
5983 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5984 iflib_intr_type_t type, driver_filter_t *filter,
5985 void *filter_arg, int qid, const char *name)
5988 struct grouptask *gtask;
5989 struct taskqgroup *tqg;
5990 iflib_filter_info_t info;
5993 driver_filter_t *intr_fast;
5996 info = &ctx->ifc_filter_info;
6000 /* XXX merge tx/rx for netmap? */
6002 q = &ctx->ifc_txqs[qid];
6003 info = &ctx->ifc_txqs[qid].ift_filter_info;
6004 gtask = &ctx->ifc_txqs[qid].ift_task;
6005 tqg = qgroup_if_io_tqg;
6007 intr_fast = iflib_fast_intr;
6008 GROUPTASK_INIT(gtask, 0, fn, q);
6009 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6012 q = &ctx->ifc_rxqs[qid];
6013 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6014 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6015 tqg = qgroup_if_io_tqg;
6017 intr_fast = iflib_fast_intr;
6018 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6020 case IFLIB_INTR_RXTX:
6021 q = &ctx->ifc_rxqs[qid];
6022 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6023 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6024 tqg = qgroup_if_io_tqg;
6026 intr_fast = iflib_fast_intr_rxtx;
6027 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6029 case IFLIB_INTR_ADMIN:
6032 info = &ctx->ifc_filter_info;
6033 gtask = &ctx->ifc_admin_task;
6034 tqg = qgroup_if_config_tqg;
6035 fn = _task_fn_admin;
6036 intr_fast = iflib_fast_intr_ctx;
6039 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6044 info->ifi_filter = filter;
6045 info->ifi_filter_arg = filter_arg;
6046 info->ifi_task = gtask;
6050 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6052 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6055 if (type == IFLIB_INTR_ADMIN)
6059 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6064 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6071 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6073 struct grouptask *gtask;
6074 struct taskqgroup *tqg;
6081 q = &ctx->ifc_txqs[qid];
6082 gtask = &ctx->ifc_txqs[qid].ift_task;
6083 tqg = qgroup_if_io_tqg;
6085 GROUPTASK_INIT(gtask, 0, fn, q);
6088 q = &ctx->ifc_rxqs[qid];
6089 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6090 tqg = qgroup_if_io_tqg;
6092 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6094 case IFLIB_INTR_IOV:
6096 gtask = &ctx->ifc_vflr_task;
6097 tqg = qgroup_if_config_tqg;
6099 GROUPTASK_INIT(gtask, 0, fn, q);
6102 panic("unknown net intr type");
6105 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6108 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6111 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6116 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6120 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6123 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6124 rman_get_rid(irq->ii_res), irq->ii_res);
6128 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6130 iflib_txq_t txq = ctx->ifc_txqs;
6131 iflib_rxq_t rxq = ctx->ifc_rxqs;
6132 if_irq_t irq = &ctx->ifc_legacy_irq;
6133 iflib_filter_info_t info;
6135 struct grouptask *gtask;
6136 struct resource *res;
6137 struct taskqgroup *tqg;
6142 q = &ctx->ifc_rxqs[0];
6143 info = &rxq[0].ifr_filter_info;
6144 gtask = &rxq[0].ifr_task;
6145 tqg = qgroup_if_io_tqg;
6147 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6149 ctx->ifc_flags |= IFC_LEGACY;
6150 info->ifi_filter = filter;
6151 info->ifi_filter_arg = filter_arg;
6152 info->ifi_task = gtask;
6153 info->ifi_ctx = rx_only ? ctx : q;
6156 /* We allocate a single interrupt resource */
6157 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6158 iflib_fast_intr_rxtx, NULL, info, name);
6161 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6163 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6165 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6166 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6172 iflib_led_create(if_ctx_t ctx)
6175 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6176 device_get_nameunit(ctx->ifc_dev));
6180 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6183 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6187 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6190 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6194 iflib_admin_intr_deferred(if_ctx_t ctx)
6197 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6198 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6202 iflib_iov_intr_deferred(if_ctx_t ctx)
6205 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6209 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6212 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6217 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6221 GROUPTASK_INIT(gtask, 0, fn, ctx);
6222 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6227 iflib_config_gtask_deinit(struct grouptask *gtask)
6230 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6234 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6236 if_t ifp = ctx->ifc_ifp;
6237 iflib_txq_t txq = ctx->ifc_txqs;
6239 if_setbaudrate(ifp, baudrate);
6240 if (baudrate >= IF_Gbps(10)) {
6242 ctx->ifc_flags |= IFC_PREFETCH;
6245 /* If link down, disable watchdog */
6246 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6247 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6248 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6250 ctx->ifc_link_state = link_state;
6251 if_link_state_change(ifp, link_state);
6255 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6259 int credits_pre = txq->ift_cidx_processed;
6262 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6263 BUS_DMASYNC_POSTREAD);
6264 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6267 txq->ift_processed += credits;
6268 txq->ift_cidx_processed += credits;
6270 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6271 if (txq->ift_cidx_processed >= txq->ift_size)
6272 txq->ift_cidx_processed -= txq->ift_size;
6277 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6282 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6283 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6284 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6285 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6290 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6291 const char *description, if_int_delay_info_t info,
6292 int offset, int value)
6294 info->iidi_ctx = ctx;
6295 info->iidi_offset = offset;
6296 info->iidi_value = value;
6297 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6298 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6299 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6300 info, 0, iflib_sysctl_int_delay, "I", description);
6304 iflib_ctx_lock_get(if_ctx_t ctx)
6307 return (&ctx->ifc_ctx_sx);
6311 iflib_msix_init(if_ctx_t ctx)
6313 device_t dev = ctx->ifc_dev;
6314 if_shared_ctx_t sctx = ctx->ifc_sctx;
6315 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6316 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6317 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6319 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6320 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6323 device_printf(dev, "msix_init qsets capped at %d\n",
6324 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6326 /* Override by tuneable */
6327 if (scctx->isc_disable_msix)
6330 /* First try MSI-X */
6331 if ((msgs = pci_msix_count(dev)) == 0) {
6333 device_printf(dev, "MSI-X not supported or disabled\n");
6337 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6339 * bar == -1 => "trust me I know what I'm doing"
6340 * Some drivers are for hardware that is so shoddily
6341 * documented that no one knows which bars are which
6342 * so the developer has to map all bars. This hack
6343 * allows shoddy garbage to use MSI-X in this framework.
6346 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6347 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6348 if (ctx->ifc_msix_mem == NULL) {
6349 device_printf(dev, "Unable to map MSI-X table\n");
6354 admincnt = sctx->isc_admin_intrcnt;
6356 /* use only 1 qset in debug mode */
6357 queuemsgs = min(msgs - admincnt, 1);
6359 queuemsgs = msgs - admincnt;
6362 queues = imin(queuemsgs, rss_getnumbuckets());
6366 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6369 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6370 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6372 /* If we're doing RSS, clamp at the number of RSS buckets */
6373 if (queues > rss_getnumbuckets())
6374 queues = rss_getnumbuckets();
6376 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6377 rx_queues = iflib_num_rx_queues;
6381 if (rx_queues > scctx->isc_nrxqsets)
6382 rx_queues = scctx->isc_nrxqsets;
6385 * We want this to be all logical CPUs by default
6387 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6388 tx_queues = iflib_num_tx_queues;
6390 tx_queues = mp_ncpus;
6392 if (tx_queues > scctx->isc_ntxqsets)
6393 tx_queues = scctx->isc_ntxqsets;
6395 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6397 if (tx_queues != rx_queues)
6399 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6400 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6402 tx_queues = min(rx_queues, tx_queues);
6403 rx_queues = min(rx_queues, tx_queues);
6406 vectors = rx_queues + admincnt;
6407 if (msgs < vectors) {
6409 "insufficient number of MSI-X vectors "
6410 "(supported %d, need %d)\n", msgs, vectors);
6414 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6417 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6418 if (vectors != msgs) {
6420 "Unable to allocate sufficient MSI-X vectors "
6421 "(got %d, need %d)\n", vectors, msgs);
6422 pci_release_msi(dev);
6424 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6426 ctx->ifc_msix_mem = NULL;
6430 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6432 scctx->isc_vectors = vectors;
6433 scctx->isc_nrxqsets = rx_queues;
6434 scctx->isc_ntxqsets = tx_queues;
6435 scctx->isc_intr = IFLIB_INTR_MSIX;
6440 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6443 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6445 ctx->ifc_msix_mem = NULL;
6450 vectors = pci_msi_count(dev);
6451 scctx->isc_nrxqsets = 1;
6452 scctx->isc_ntxqsets = 1;
6453 scctx->isc_vectors = vectors;
6454 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6455 device_printf(dev,"Using an MSI interrupt\n");
6456 scctx->isc_intr = IFLIB_INTR_MSI;
6458 scctx->isc_vectors = 1;
6459 device_printf(dev,"Using a Legacy interrupt\n");
6460 scctx->isc_intr = IFLIB_INTR_LEGACY;
6466 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6469 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6472 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6474 const char *ring_state = "UNKNOWN";
6477 rc = sysctl_wire_old_buffer(req, 0);
6481 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6486 ring_state = ring_states[state[3]];
6488 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6489 state[0], state[1], state[2], ring_state);
6490 rc = sbuf_finish(sb);
6495 enum iflib_ndesc_handler {
6501 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6503 if_ctx_t ctx = (void *)arg1;
6504 enum iflib_ndesc_handler type = arg2;
6505 char buf[256] = {0};
6512 case IFLIB_NTXD_HANDLER:
6513 ndesc = ctx->ifc_sysctl_ntxds;
6515 nqs = ctx->ifc_sctx->isc_ntxqs;
6517 case IFLIB_NRXD_HANDLER:
6518 ndesc = ctx->ifc_sysctl_nrxds;
6520 nqs = ctx->ifc_sctx->isc_nrxqs;
6523 printf("%s: unhandled type\n", __func__);
6529 for (i=0; i<8; i++) {
6534 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6537 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6538 if (rc || req->newptr == NULL)
6541 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6542 i++, p = strsep(&next, " ,")) {
6543 ndesc[i] = strtoul(p, NULL, 10);
6549 #define NAME_BUFLEN 32
6551 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6553 device_t dev = iflib_get_dev(ctx);
6554 struct sysctl_oid_list *child, *oid_list;
6555 struct sysctl_ctx_list *ctx_list;
6556 struct sysctl_oid *node;
6558 ctx_list = device_get_sysctl_ctx(dev);
6559 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6560 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6561 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6562 oid_list = SYSCTL_CHILDREN(node);
6564 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6565 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6568 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6569 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6570 "# of txqs to use, 0 => use default #");
6571 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6572 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6573 "# of rxqs to use, 0 => use default #");
6574 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6575 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6576 "permit #txq != #rxq");
6577 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6578 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6579 "disable MSI-X (default 0)");
6580 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6581 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6582 "set the RX budget");
6583 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6584 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6585 "cause TX to abdicate instead of running to completion");
6586 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6587 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6588 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6589 "offset to start using cores at");
6590 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6591 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6592 "use separate cores for TX and RX");
6594 /* XXX change for per-queue sizes */
6595 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6596 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6597 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6598 "list of # of TX descriptors to use, 0 = use default #");
6599 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6600 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6601 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6602 "list of # of RX descriptors to use, 0 = use default #");
6606 iflib_add_device_sysctl_post(if_ctx_t ctx)
6608 if_shared_ctx_t sctx = ctx->ifc_sctx;
6609 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6610 device_t dev = iflib_get_dev(ctx);
6611 struct sysctl_oid_list *child;
6612 struct sysctl_ctx_list *ctx_list;
6617 char namebuf[NAME_BUFLEN];
6619 struct sysctl_oid *queue_node, *fl_node, *node;
6620 struct sysctl_oid_list *queue_list, *fl_list;
6621 ctx_list = device_get_sysctl_ctx(dev);
6623 node = ctx->ifc_sysctl_node;
6624 child = SYSCTL_CHILDREN(node);
6626 if (scctx->isc_ntxqsets > 100)
6628 else if (scctx->isc_ntxqsets > 10)
6632 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6633 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6634 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6635 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6636 queue_list = SYSCTL_CHILDREN(queue_node);
6638 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6640 &txq->ift_dequeued, "total mbufs freed");
6641 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6643 &txq->ift_enqueued, "total mbufs enqueued");
6645 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6647 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6648 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6650 &txq->ift_pullups, "# of times m_pullup was called");
6651 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6653 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6654 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6656 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6657 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6659 &txq->ift_map_failed, "# of times DMA map failed");
6660 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6662 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6663 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6665 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6666 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6668 &txq->ift_pidx, 1, "Producer Index");
6669 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6671 &txq->ift_cidx, 1, "Consumer Index");
6672 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6674 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6675 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6677 &txq->ift_in_use, 1, "descriptors in use");
6678 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6680 &txq->ift_processed, "descriptors procesed for clean");
6681 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6683 &txq->ift_cleaned, "total cleaned");
6684 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6685 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6686 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6687 mp_ring_state_handler, "A", "soft ring state");
6688 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6689 CTLFLAG_RD, &txq->ift_br->enqueues,
6690 "# of enqueues to the mp_ring for this queue");
6691 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6692 CTLFLAG_RD, &txq->ift_br->drops,
6693 "# of drops in the mp_ring for this queue");
6694 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6695 CTLFLAG_RD, &txq->ift_br->starts,
6696 "# of normal consumer starts in the mp_ring for this queue");
6697 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6698 CTLFLAG_RD, &txq->ift_br->stalls,
6699 "# of consumer stalls in the mp_ring for this queue");
6700 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6701 CTLFLAG_RD, &txq->ift_br->restarts,
6702 "# of consumer restarts in the mp_ring for this queue");
6703 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6704 CTLFLAG_RD, &txq->ift_br->abdications,
6705 "# of consumer abdications in the mp_ring for this queue");
6708 if (scctx->isc_nrxqsets > 100)
6710 else if (scctx->isc_nrxqsets > 10)
6714 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6715 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6716 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6717 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6718 queue_list = SYSCTL_CHILDREN(queue_node);
6719 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6720 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6722 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6725 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6726 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6727 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6728 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6729 fl_list = SYSCTL_CHILDREN(fl_node);
6730 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6732 &fl->ifl_pidx, 1, "Producer Index");
6733 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6735 &fl->ifl_cidx, 1, "Consumer Index");
6736 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6738 &fl->ifl_credits, 1, "credits available");
6739 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6741 &fl->ifl_buf_size, 1, "buffer size");
6743 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6745 &fl->ifl_m_enqueued, "mbufs allocated");
6746 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6748 &fl->ifl_m_dequeued, "mbufs freed");
6749 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6751 &fl->ifl_cl_enqueued, "clusters allocated");
6752 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6754 &fl->ifl_cl_dequeued, "clusters freed");
6763 iflib_request_reset(if_ctx_t ctx)
6767 ctx->ifc_flags |= IFC_DO_RESET;
6771 #ifndef __NO_STRICT_ALIGNMENT
6772 static struct mbuf *
6773 iflib_fixup_rx(struct mbuf *m)
6777 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6778 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6779 m->m_data += ETHER_HDR_LEN;
6782 MGETHDR(n, M_NOWAIT, MT_DATA);
6787 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6788 m->m_data += ETHER_HDR_LEN;
6789 m->m_len -= ETHER_HDR_LEN;
6790 n->m_len = ETHER_HDR_LEN;
6791 M_MOVE_PKTHDR(n, m);
6800 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6804 ctx = if_getsoftc(ifp);
6806 *nrxr = NRXQSETS(ctx);
6807 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6808 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6813 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6816 if_softc_ctx_t scctx;
6821 ctx = if_getsoftc(ifp);
6822 scctx = &ctx->ifc_softc_ctx;
6825 case DEBUGNET_START:
6826 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6827 rxq = &ctx->ifc_rxqs[i];
6828 for (j = 0; j < rxq->ifr_nfl; j++) {
6830 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6833 iflib_no_tx_batch = 1;
6841 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6847 ctx = if_getsoftc(ifp);
6848 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6852 txq = &ctx->ifc_txqs[0];
6853 error = iflib_encap(txq, &m);
6855 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6860 iflib_debugnet_poll(if_t ifp, int count)
6862 struct epoch_tracker et;
6864 if_softc_ctx_t scctx;
6868 ctx = if_getsoftc(ifp);
6869 scctx = &ctx->ifc_softc_ctx;
6871 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6875 txq = &ctx->ifc_txqs[0];
6876 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6878 NET_EPOCH_ENTER(et);
6879 for (i = 0; i < scctx->isc_nrxqsets; i++)
6880 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6884 #endif /* DEBUGNET */