2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet/netdump/netdump.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
133 typedef struct iflib_txq *iflib_txq_t;
135 typedef struct iflib_rxq *iflib_rxq_t;
137 typedef struct iflib_fl *iflib_fl_t;
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
144 typedef struct iflib_filter_info {
145 driver_filter_t *ifi_filter;
146 void *ifi_filter_arg;
147 struct grouptask *ifi_task;
149 } *iflib_filter_info_t;
154 * Pointer to hardware driver's softc
161 if_shared_ctx_t ifc_sctx;
162 struct if_softc_ctx ifc_softc_ctx;
164 struct sx ifc_ctx_sx;
165 struct mtx ifc_state_mtx;
167 iflib_txq_t ifc_txqs;
168 iflib_rxq_t ifc_rxqs;
169 uint32_t ifc_if_flags;
171 uint32_t ifc_max_fl_buf_size;
172 uint32_t ifc_rx_mbuf_sz;
175 int ifc_watchdog_events;
176 struct cdev *ifc_led_dev;
177 struct resource *ifc_msix_mem;
179 struct if_irq ifc_legacy_irq;
180 struct grouptask ifc_admin_task;
181 struct grouptask ifc_vflr_task;
182 struct iflib_filter_info ifc_filter_info;
183 struct ifmedia ifc_media;
184 struct ifmedia *ifc_mediap;
186 struct sysctl_oid *ifc_sysctl_node;
187 uint16_t ifc_sysctl_ntxqs;
188 uint16_t ifc_sysctl_nrxqs;
189 uint16_t ifc_sysctl_qs_eq_override;
190 uint16_t ifc_sysctl_rx_budget;
191 uint16_t ifc_sysctl_tx_abdicate;
192 uint16_t ifc_sysctl_core_offset;
193 #define CORE_OFFSET_UNSPECIFIED 0xffff
194 uint8_t ifc_sysctl_separate_txrx;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 struct ether_addr ifc_mac;
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (ctx->ifc_mediap);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS 128
291 #define IFLIB_RX_COPY_THRESH 128
292 #define IFLIB_MAX_RX_REFRESH 32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC 16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
296 #define IFLIB_QUEUE_IDLE 0
297 #define IFLIB_QUEUE_HUNG 1
298 #define IFLIB_QUEUE_WORKING 2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR 4
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE 32
305 #define IFLIB_RESTART_BUDGET 8
307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
314 qidx_t ift_cidx_processed;
317 uint8_t ift_br_offset;
318 uint16_t ift_npending;
319 uint16_t ift_db_pending;
320 uint16_t ift_rs_pending;
322 uint8_t ift_txd_size[8];
323 uint64_t ift_processed;
324 uint64_t ift_cleaned;
325 uint64_t ift_cleaned_prev;
327 uint64_t ift_enqueued;
328 uint64_t ift_dequeued;
330 uint64_t ift_no_tx_dma_setup;
331 uint64_t ift_no_desc_avail;
332 uint64_t ift_mbuf_defrag_failed;
333 uint64_t ift_mbuf_defrag;
334 uint64_t ift_map_failed;
335 uint64_t ift_txd_encap_efbig;
336 uint64_t ift_pullups;
337 uint64_t ift_last_timer_tick;
340 struct mtx ift_db_mtx;
342 /* constant values */
344 struct ifmp_ring *ift_br;
345 struct grouptask ift_task;
348 struct callout ift_timer;
350 if_txsd_vec_t ift_sds;
353 uint8_t ift_update_freq;
354 struct iflib_filter_info ift_filter_info;
355 bus_dma_tag_t ift_buf_tag;
356 bus_dma_tag_t ift_tso_buf_tag;
357 iflib_dma_info_t ift_ifdi;
358 #define MTX_NAME_LEN 16
359 char ift_mtx_name[MTX_NAME_LEN];
360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 uint64_t ift_cpu_exec_count[256];
364 } __aligned(CACHE_LINE_SIZE);
371 uint8_t ifl_rxd_size;
373 uint64_t ifl_m_enqueued;
374 uint64_t ifl_m_dequeued;
375 uint64_t ifl_cl_enqueued;
376 uint64_t ifl_cl_dequeued;
379 bitstr_t *ifl_rx_bitmap;
383 uint16_t ifl_buf_size;
386 iflib_rxsd_array_t ifl_sds;
389 bus_dma_tag_t ifl_buf_tag;
390 iflib_dma_info_t ifl_ifdi;
391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the command queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct iflib_filter_info ifr_filter_info;
438 iflib_dma_info_t ifr_ifdi;
440 /* dynamically allocate if any drivers need a value substantially larger than this */
441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
442 #ifdef IFLIB_DIAGNOSTICS
443 uint64_t ifr_cpu_exec_count[256];
445 } __aligned(CACHE_LINE_SIZE);
447 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_init_locked(if_ctx_t ctx);
707 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
709 static void iflib_ifmp_purge(iflib_txq_t txq);
710 static void _iflib_pre_assert(if_softc_ctx_t scctx);
711 static void iflib_if_init_locked(if_ctx_t ctx);
712 static void iflib_free_intr_mem(if_ctx_t ctx);
713 #ifndef __NO_STRICT_ALIGNMENT
714 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
718 SLIST_HEAD_INITIALIZER(cpu_offsets);
720 SLIST_ENTRY(cpu_offset) entries;
722 unsigned int refcount;
725 static struct mtx cpu_offset_mtx;
726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
729 NETDUMP_DEFINE(iflib);
732 #include <sys/selinfo.h>
733 #include <net/netmap.h>
734 #include <dev/netmap/netmap_kern.h>
736 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
738 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
741 * device-specific sysctl variables:
743 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
744 * During regular operations the CRC is stripped, but on some
745 * hardware reception of frames not multiple of 64 is slower,
746 * so using crcstrip=0 helps in benchmarks.
748 * iflib_rx_miss, iflib_rx_miss_bufs:
749 * count packets that might be missed due to lost interrupts.
751 SYSCTL_DECL(_dev_netmap);
753 * The xl driver by default strips CRCs and we do not override it.
756 int iflib_crcstrip = 1;
757 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
758 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
760 int iflib_rx_miss, iflib_rx_miss_bufs;
761 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
762 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
764 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
767 * Register/unregister. We are already under netmap lock.
768 * Only called on the first register or the last unregister.
771 iflib_netmap_register(struct netmap_adapter *na, int onoff)
774 if_ctx_t ctx = ifp->if_softc;
778 IFDI_INTR_DISABLE(ctx);
780 /* Tell the stack that the interface is no longer active */
781 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
784 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
786 /* enable or disable flags and callbacks in na and ifp */
788 nm_set_native_flags(na);
790 nm_clear_native_flags(na);
793 iflib_init_locked(ctx);
794 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
795 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
797 nm_clear_native_flags(na);
803 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
805 struct netmap_adapter *na = kring->na;
806 u_int const lim = kring->nkr_num_slots - 1;
807 u_int head = kring->rhead;
808 struct netmap_ring *ring = kring->ring;
810 struct if_rxd_update iru;
811 if_ctx_t ctx = rxq->ifr_ctx;
812 iflib_fl_t fl = &rxq->ifr_fl[0];
813 uint32_t refill_pidx, nic_i;
814 #if IFLIB_DEBUG_COUNTERS
818 if (nm_i == head && __predict_true(!init))
820 iru_init(&iru, rxq, 0 /* flid */);
821 map = fl->ifl_sds.ifsd_map;
822 refill_pidx = netmap_idx_k2n(kring, nm_i);
824 * IMPORTANT: we must leave one free slot in the ring,
825 * so move head back by one unit
827 head = nm_prev(head, lim);
829 DBG_COUNTER_INC(fl_refills);
830 while (nm_i != head) {
831 #if IFLIB_DEBUG_COUNTERS
833 DBG_COUNTER_INC(fl_refills_large);
835 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
836 struct netmap_slot *slot = &ring->slot[nm_i];
837 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
838 uint32_t nic_i_dma = refill_pidx;
839 nic_i = netmap_idx_k2n(kring, nm_i);
841 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
843 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
844 return netmap_ring_reinit(kring);
846 fl->ifl_vm_addrs[tmp_pidx] = addr;
847 if (__predict_false(init)) {
848 netmap_load_map(na, fl->ifl_buf_tag,
850 } else if (slot->flags & NS_BUF_CHANGED) {
851 /* buffer has changed, reload map */
852 netmap_reload_map(na, fl->ifl_buf_tag,
855 slot->flags &= ~NS_BUF_CHANGED;
857 nm_i = nm_next(nm_i, lim);
858 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
859 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
862 iru.iru_pidx = refill_pidx;
863 iru.iru_count = tmp_pidx+1;
864 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
866 for (int n = 0; n < iru.iru_count; n++) {
867 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
868 BUS_DMASYNC_PREREAD);
869 /* XXX - change this to not use the netmap func*/
870 nic_i_dma = nm_next(nic_i_dma, lim);
874 kring->nr_hwcur = head;
876 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
878 if (__predict_true(nic_i != UINT_MAX)) {
879 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
880 DBG_COUNTER_INC(rxd_flush);
886 * Reconcile kernel and user view of the transmit ring.
888 * All information is in the kring.
889 * Userspace wants to send packets up to the one before kring->rhead,
890 * kernel knows kring->nr_hwcur is the first unsent packet.
892 * Here we push packets out (as many as possible), and possibly
893 * reclaim buffers from previously completed transmission.
895 * The caller (netmap) guarantees that there is only one instance
896 * running at any time. Any interference with other driver
897 * methods should be handled by the individual drivers.
900 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
902 struct netmap_adapter *na = kring->na;
904 struct netmap_ring *ring = kring->ring;
905 u_int nm_i; /* index into the netmap kring */
906 u_int nic_i; /* index into the NIC ring */
908 u_int const lim = kring->nkr_num_slots - 1;
909 u_int const head = kring->rhead;
910 struct if_pkt_info pi;
913 * interrupts on every tx packet are expensive so request
914 * them every half ring, or where NS_REPORT is set
916 u_int report_frequency = kring->nkr_num_slots >> 1;
917 /* device-specific */
918 if_ctx_t ctx = ifp->if_softc;
919 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
921 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
922 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
925 * First part: process new packets to send.
926 * nm_i is the current index in the netmap kring,
927 * nic_i is the corresponding index in the NIC ring.
929 * If we have packets to send (nm_i != head)
930 * iterate over the netmap ring, fetch length and update
931 * the corresponding slot in the NIC ring. Some drivers also
932 * need to update the buffer's physical address in the NIC slot
933 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
935 * The netmap_reload_map() calls is especially expensive,
936 * even when (as in this case) the tag is 0, so do only
937 * when the buffer has actually changed.
939 * If possible do not set the report/intr bit on all slots,
940 * but only a few times per ring or when NS_REPORT is set.
942 * Finally, on 10G and faster drivers, it might be useful
943 * to prefetch the next slot and txr entry.
946 nm_i = kring->nr_hwcur;
947 if (nm_i != head) { /* we have new packets to send */
949 pi.ipi_segs = txq->ift_segs;
950 pi.ipi_qsidx = kring->ring_id;
951 nic_i = netmap_idx_k2n(kring, nm_i);
953 __builtin_prefetch(&ring->slot[nm_i]);
954 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
955 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
957 for (n = 0; nm_i != head; n++) {
958 struct netmap_slot *slot = &ring->slot[nm_i];
959 u_int len = slot->len;
961 void *addr = PNMB(na, slot, &paddr);
962 int flags = (slot->flags & NS_REPORT ||
963 nic_i == 0 || nic_i == report_frequency) ?
966 /* device-specific */
968 pi.ipi_segs[0].ds_addr = paddr;
969 pi.ipi_segs[0].ds_len = len;
973 pi.ipi_flags = flags;
975 /* Fill the slot in the NIC ring. */
976 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
977 DBG_COUNTER_INC(tx_encap);
979 /* prefetch for next round */
980 __builtin_prefetch(&ring->slot[nm_i + 1]);
981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
982 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
984 NM_CHECK_ADDR_LEN(na, addr, len);
986 if (slot->flags & NS_BUF_CHANGED) {
987 /* buffer has changed, reload map */
988 netmap_reload_map(na, txq->ift_buf_tag,
989 txq->ift_sds.ifsd_map[nic_i], addr);
991 /* make sure changes to the buffer are synced */
992 bus_dmamap_sync(txq->ift_buf_tag,
993 txq->ift_sds.ifsd_map[nic_i],
994 BUS_DMASYNC_PREWRITE);
996 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
997 nm_i = nm_next(nm_i, lim);
998 nic_i = nm_next(nic_i, lim);
1000 kring->nr_hwcur = nm_i;
1002 /* synchronize the NIC ring */
1003 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1006 /* (re)start the tx unit up to slot nic_i (excluded) */
1007 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1011 * Second part: reclaim buffers for completed transmissions.
1013 * If there are unclaimed buffers, attempt to reclaim them.
1014 * If none are reclaimed, and TX IRQs are not in use, do an initial
1015 * minimal delay, then trigger the tx handler which will spin in the
1018 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1019 if (iflib_tx_credits_update(ctx, txq)) {
1020 /* some tx completed, increment avail */
1021 nic_i = txq->ift_cidx_processed;
1022 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1025 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1026 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1027 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1028 iflib_timer, txq, txq->ift_timer.c_cpu);
1034 * Reconcile kernel and user view of the receive ring.
1035 * Same as for the txsync, this routine must be efficient.
1036 * The caller guarantees a single invocations, but races against
1037 * the rest of the driver should be handled here.
1039 * On call, kring->rhead is the first packet that userspace wants
1040 * to keep, and kring->rcur is the wakeup point.
1041 * The kernel has previously reported packets up to kring->rtail.
1043 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1044 * of whether or not we received an interrupt.
1047 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1049 struct netmap_adapter *na = kring->na;
1050 struct netmap_ring *ring = kring->ring;
1053 uint32_t nm_i; /* index into the netmap ring */
1054 uint32_t nic_i; /* index into the NIC ring */
1056 u_int const lim = kring->nkr_num_slots - 1;
1057 u_int const head = kring->rhead;
1058 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1059 struct if_rxd_info ri;
1061 if_ctx_t ctx = ifp->if_softc;
1062 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1064 return netmap_ring_reinit(kring);
1067 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1070 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1071 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1072 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1076 * First part: import newly received packets.
1078 * nm_i is the index of the next free slot in the netmap ring,
1079 * nic_i is the index of the next received packet in the NIC ring,
1080 * and they may differ in case if_init() has been called while
1081 * in netmap mode. For the receive ring we have
1083 * nic_i = rxr->next_check;
1084 * nm_i = kring->nr_hwtail (previous)
1086 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1088 * rxr->next_check is set to 0 on a ring reinit
1090 if (netmap_no_pendintr || force_update) {
1091 int crclen = iflib_crcstrip ? 0 : 4;
1094 for (i = 0; i < rxq->ifr_nfl; i++) {
1095 fl = &rxq->ifr_fl[i];
1096 nic_i = fl->ifl_cidx;
1097 nm_i = netmap_idx_n2k(kring, nic_i);
1098 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1099 rxq->ifr_id, nic_i, USHRT_MAX);
1100 for (n = 0; avail > 0; n++, avail--) {
1102 ri.iri_frags = rxq->ifr_frags;
1103 ri.iri_qsidx = kring->ring_id;
1104 ri.iri_ifp = ctx->ifc_ifp;
1105 ri.iri_cidx = nic_i;
1107 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1108 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1109 ring->slot[nm_i].flags = 0;
1110 bus_dmamap_sync(fl->ifl_buf_tag,
1111 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1112 nm_i = nm_next(nm_i, lim);
1113 nic_i = nm_next(nic_i, lim);
1115 if (n) { /* update the state variables */
1116 if (netmap_no_pendintr && !force_update) {
1119 iflib_rx_miss_bufs += n;
1121 fl->ifl_cidx = nic_i;
1122 kring->nr_hwtail = nm_i;
1124 kring->nr_kflags &= ~NKR_PENDINTR;
1128 * Second part: skip past packets that userspace has released.
1129 * (kring->nr_hwcur to head excluded),
1130 * and make the buffers available for reception.
1131 * As usual nm_i is the index in the netmap ring,
1132 * nic_i is the index in the NIC ring, and
1133 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1135 /* XXX not sure how this will work with multiple free lists */
1136 nm_i = kring->nr_hwcur;
1138 return (netmap_fl_refill(rxq, kring, nm_i, false));
1142 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1144 if_ctx_t ctx = na->ifp->if_softc;
1148 IFDI_INTR_ENABLE(ctx);
1150 IFDI_INTR_DISABLE(ctx);
1157 iflib_netmap_attach(if_ctx_t ctx)
1159 struct netmap_adapter na;
1160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1162 bzero(&na, sizeof(na));
1164 na.ifp = ctx->ifc_ifp;
1165 na.na_flags = NAF_BDG_MAYSLEEP;
1166 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1167 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1169 na.num_tx_desc = scctx->isc_ntxd[0];
1170 na.num_rx_desc = scctx->isc_nrxd[0];
1171 na.nm_txsync = iflib_netmap_txsync;
1172 na.nm_rxsync = iflib_netmap_rxsync;
1173 na.nm_register = iflib_netmap_register;
1174 na.nm_intr = iflib_netmap_intr;
1175 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1176 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1177 return (netmap_attach(&na));
1181 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1183 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1184 struct netmap_slot *slot;
1186 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1189 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1192 * In netmap mode, set the map for the packet buffer.
1193 * NOTE: Some drivers (not this one) also need to set
1194 * the physical buffer address in the NIC ring.
1195 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1196 * netmap slot index, si
1198 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1199 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1200 NMB(na, slot + si));
1205 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1207 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1208 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1209 struct netmap_slot *slot;
1212 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1215 nm_i = netmap_idx_n2k(kring, 0);
1216 netmap_fl_refill(rxq, kring, nm_i, true);
1220 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1222 struct netmap_kring *kring;
1225 txqid = txq->ift_id;
1226 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1228 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1229 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1230 BUS_DMASYNC_POSTREAD);
1231 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1232 netmap_tx_irq(ctx->ifc_ifp, txqid);
1233 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1237 *reset_on = hz / 1000;
1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1245 #define iflib_netmap_txq_init(ctx, txq)
1246 #define iflib_netmap_rxq_init(ctx, rxq)
1247 #define iflib_netmap_detach(ifp)
1249 #define iflib_netmap_attach(ctx) (0)
1250 #define netmap_rx_irq(ifp, qid, budget) (0)
1251 #define netmap_tx_irq(ifp, qid) do {} while (0)
1252 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1255 #if defined(__i386__) || defined(__amd64__)
1256 static __inline void
1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1261 static __inline void
1262 prefetch2cachelines(void *x)
1264 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1265 #if (CACHE_LINE_SIZE < 128)
1266 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1271 #define prefetch2cachelines(x)
1275 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1279 fl = &rxq->ifr_fl[flid];
1280 iru->iru_paddrs = fl->ifl_bus_addrs;
1281 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1282 iru->iru_idxs = fl->ifl_rxd_idxs;
1283 iru->iru_qsidx = rxq->ifr_id;
1284 iru->iru_buf_size = fl->ifl_buf_size;
1285 iru->iru_flidx = fl->ifl_id;
1289 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1293 *(bus_addr_t *) arg = segs[0].ds_addr;
1297 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1300 device_t dev = ctx->ifc_dev;
1302 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1303 align, 0, /* alignment, bounds */
1304 BUS_SPACE_MAXADDR, /* lowaddr */
1305 BUS_SPACE_MAXADDR, /* highaddr */
1306 NULL, NULL, /* filter, filterarg */
1309 size, /* maxsegsize */
1310 BUS_DMA_ALLOCNOW, /* flags */
1311 NULL, /* lockfunc */
1316 "%s: bus_dma_tag_create failed: %d\n",
1321 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1322 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1325 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1326 __func__, (uintmax_t)size, err);
1330 dma->idi_paddr = IF_BAD_DMA;
1331 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1332 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1333 if (err || dma->idi_paddr == IF_BAD_DMA) {
1335 "%s: bus_dmamap_load failed: %d\n",
1340 dma->idi_size = size;
1344 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1346 bus_dma_tag_destroy(dma->idi_tag);
1348 dma->idi_tag = NULL;
1354 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1356 if_shared_ctx_t sctx = ctx->ifc_sctx;
1358 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1360 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1364 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1367 iflib_dma_info_t *dmaiter;
1370 for (i = 0; i < count; i++, dmaiter++) {
1371 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1375 iflib_dma_free_multi(dmalist, i);
1380 iflib_dma_free(iflib_dma_info_t dma)
1382 if (dma->idi_tag == NULL)
1384 if (dma->idi_paddr != IF_BAD_DMA) {
1385 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1386 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1387 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1388 dma->idi_paddr = IF_BAD_DMA;
1390 if (dma->idi_vaddr != NULL) {
1391 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1392 dma->idi_vaddr = NULL;
1394 bus_dma_tag_destroy(dma->idi_tag);
1395 dma->idi_tag = NULL;
1399 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1402 iflib_dma_info_t *dmaiter = dmalist;
1404 for (i = 0; i < count; i++, dmaiter++)
1405 iflib_dma_free(*dmaiter);
1408 #ifdef EARLY_AP_STARTUP
1409 static const int iflib_started = 1;
1412 * We used to abuse the smp_started flag to decide if the queues have been
1413 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1414 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1415 * is set. Run a SYSINIT() strictly after that to just set a usable
1419 static int iflib_started;
1422 iflib_record_started(void *arg)
1427 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1428 iflib_record_started, NULL);
1432 iflib_fast_intr(void *arg)
1434 iflib_filter_info_t info = arg;
1435 struct grouptask *gtask = info->ifi_task;
1439 return (FILTER_STRAY);
1441 DBG_COUNTER_INC(fast_intrs);
1442 if (info->ifi_filter != NULL) {
1443 result = info->ifi_filter(info->ifi_filter_arg);
1444 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1448 GROUPTASK_ENQUEUE(gtask);
1449 return (FILTER_HANDLED);
1453 iflib_fast_intr_rxtx(void *arg)
1455 iflib_filter_info_t info = arg;
1456 struct grouptask *gtask = info->ifi_task;
1458 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1461 int i, cidx, result;
1463 bool intr_enable, intr_legacy;
1466 return (FILTER_STRAY);
1468 DBG_COUNTER_INC(fast_intrs);
1469 if (info->ifi_filter != NULL) {
1470 result = info->ifi_filter(info->ifi_filter_arg);
1471 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1476 sc = ctx->ifc_softc;
1477 intr_enable = false;
1478 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1479 MPASS(rxq->ifr_ntxqirq);
1480 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1481 txqid = rxq->ifr_txqid[i];
1482 txq = &ctx->ifc_txqs[txqid];
1483 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1484 BUS_DMASYNC_POSTREAD);
1485 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1489 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1492 GROUPTASK_ENQUEUE(&txq->ift_task);
1494 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1495 cidx = rxq->ifr_cq_cidx;
1497 cidx = rxq->ifr_fl[0].ifl_cidx;
1498 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1499 GROUPTASK_ENQUEUE(gtask);
1504 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1505 DBG_COUNTER_INC(rx_intr_enables);
1508 IFDI_INTR_ENABLE(ctx);
1509 return (FILTER_HANDLED);
1514 iflib_fast_intr_ctx(void *arg)
1516 iflib_filter_info_t info = arg;
1517 struct grouptask *gtask = info->ifi_task;
1521 return (FILTER_STRAY);
1523 DBG_COUNTER_INC(fast_intrs);
1524 if (info->ifi_filter != NULL) {
1525 result = info->ifi_filter(info->ifi_filter_arg);
1526 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1530 GROUPTASK_ENQUEUE(gtask);
1531 return (FILTER_HANDLED);
1535 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1536 driver_filter_t filter, driver_intr_t handler, void *arg,
1539 struct resource *res;
1541 device_t dev = ctx->ifc_dev;
1545 if (ctx->ifc_flags & IFC_LEGACY)
1546 flags |= RF_SHAREABLE;
1549 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1552 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1556 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1557 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1558 filter, handler, arg, &tag);
1561 "failed to setup interrupt for rid %d, name %s: %d\n",
1562 rid, name ? name : "unknown", rc);
1565 bus_describe_intr(dev, res, tag, "%s", name);
1571 /*********************************************************************
1573 * Allocate DMA resources for TX buffers as well as memory for the TX
1574 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1575 * iflib_sw_tx_desc_array structure, storing all the information that
1576 * is needed to transmit a packet on the wire. This is called only
1577 * once at attach, setup is done every reset.
1579 **********************************************************************/
1581 iflib_txsd_alloc(iflib_txq_t txq)
1583 if_ctx_t ctx = txq->ift_ctx;
1584 if_shared_ctx_t sctx = ctx->ifc_sctx;
1585 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1586 device_t dev = ctx->ifc_dev;
1587 bus_size_t tsomaxsize;
1588 int err, nsegments, ntsosegments;
1591 nsegments = scctx->isc_tx_nsegments;
1592 ntsosegments = scctx->isc_tx_tso_segments_max;
1593 tsomaxsize = scctx->isc_tx_tso_size_max;
1594 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1595 tsomaxsize += sizeof(struct ether_vlan_header);
1596 MPASS(scctx->isc_ntxd[0] > 0);
1597 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1598 MPASS(nsegments > 0);
1599 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1600 MPASS(ntsosegments > 0);
1601 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1605 * Set up DMA tags for TX buffers.
1607 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1608 1, 0, /* alignment, bounds */
1609 BUS_SPACE_MAXADDR, /* lowaddr */
1610 BUS_SPACE_MAXADDR, /* highaddr */
1611 NULL, NULL, /* filter, filterarg */
1612 sctx->isc_tx_maxsize, /* maxsize */
1613 nsegments, /* nsegments */
1614 sctx->isc_tx_maxsegsize, /* maxsegsize */
1616 NULL, /* lockfunc */
1617 NULL, /* lockfuncarg */
1618 &txq->ift_buf_tag))) {
1619 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1620 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1621 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1624 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1625 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1626 1, 0, /* alignment, bounds */
1627 BUS_SPACE_MAXADDR, /* lowaddr */
1628 BUS_SPACE_MAXADDR, /* highaddr */
1629 NULL, NULL, /* filter, filterarg */
1630 tsomaxsize, /* maxsize */
1631 ntsosegments, /* nsegments */
1632 sctx->isc_tso_maxsegsize,/* maxsegsize */
1634 NULL, /* lockfunc */
1635 NULL, /* lockfuncarg */
1636 &txq->ift_tso_buf_tag))) {
1637 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1642 /* Allocate memory for the TX mbuf map. */
1643 if (!(txq->ift_sds.ifsd_m =
1644 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1645 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1646 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1652 * Create the DMA maps for TX buffers.
1654 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1655 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1656 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1658 "Unable to allocate TX buffer DMA map memory\n");
1662 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1663 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1664 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1666 "Unable to allocate TSO TX buffer map memory\n");
1670 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1671 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1672 &txq->ift_sds.ifsd_map[i]);
1674 device_printf(dev, "Unable to create TX DMA map\n");
1679 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1680 &txq->ift_sds.ifsd_tso_map[i]);
1682 device_printf(dev, "Unable to create TSO TX DMA map\n");
1688 /* We free all, it handles case where we are in the middle */
1689 iflib_tx_structures_free(ctx);
1694 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1699 if (txq->ift_sds.ifsd_map != NULL)
1700 map = txq->ift_sds.ifsd_map[i];
1702 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1703 bus_dmamap_unload(txq->ift_buf_tag, map);
1704 bus_dmamap_destroy(txq->ift_buf_tag, map);
1705 txq->ift_sds.ifsd_map[i] = NULL;
1709 if (txq->ift_sds.ifsd_tso_map != NULL)
1710 map = txq->ift_sds.ifsd_tso_map[i];
1712 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1713 BUS_DMASYNC_POSTWRITE);
1714 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1715 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1716 txq->ift_sds.ifsd_tso_map[i] = NULL;
1721 iflib_txq_destroy(iflib_txq_t txq)
1723 if_ctx_t ctx = txq->ift_ctx;
1725 for (int i = 0; i < txq->ift_size; i++)
1726 iflib_txsd_destroy(ctx, txq, i);
1727 if (txq->ift_sds.ifsd_map != NULL) {
1728 free(txq->ift_sds.ifsd_map, M_IFLIB);
1729 txq->ift_sds.ifsd_map = NULL;
1731 if (txq->ift_sds.ifsd_tso_map != NULL) {
1732 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1733 txq->ift_sds.ifsd_tso_map = NULL;
1735 if (txq->ift_sds.ifsd_m != NULL) {
1736 free(txq->ift_sds.ifsd_m, M_IFLIB);
1737 txq->ift_sds.ifsd_m = NULL;
1739 if (txq->ift_buf_tag != NULL) {
1740 bus_dma_tag_destroy(txq->ift_buf_tag);
1741 txq->ift_buf_tag = NULL;
1743 if (txq->ift_tso_buf_tag != NULL) {
1744 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1745 txq->ift_tso_buf_tag = NULL;
1750 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1754 mp = &txq->ift_sds.ifsd_m[i];
1758 if (txq->ift_sds.ifsd_map != NULL) {
1759 bus_dmamap_sync(txq->ift_buf_tag,
1760 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1761 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1763 if (txq->ift_sds.ifsd_tso_map != NULL) {
1764 bus_dmamap_sync(txq->ift_tso_buf_tag,
1765 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1766 bus_dmamap_unload(txq->ift_tso_buf_tag,
1767 txq->ift_sds.ifsd_tso_map[i]);
1770 DBG_COUNTER_INC(tx_frees);
1775 iflib_txq_setup(iflib_txq_t txq)
1777 if_ctx_t ctx = txq->ift_ctx;
1778 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1779 if_shared_ctx_t sctx = ctx->ifc_sctx;
1780 iflib_dma_info_t di;
1783 /* Set number of descriptors available */
1784 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1785 /* XXX make configurable */
1786 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1789 txq->ift_cidx_processed = 0;
1790 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1791 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1793 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1794 bzero((void *)di->idi_vaddr, di->idi_size);
1796 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1797 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1798 bus_dmamap_sync(di->idi_tag, di->idi_map,
1799 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1803 /*********************************************************************
1805 * Allocate DMA resources for RX buffers as well as memory for the RX
1806 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1807 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1808 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1809 * Since we use use one entry in iflib_sw_rx_desc_array per received
1810 * packet, the maximum number of entries we'll need is equal to the
1811 * number of hardware receive descriptors that we've allocated.
1813 **********************************************************************/
1815 iflib_rxsd_alloc(iflib_rxq_t rxq)
1817 if_ctx_t ctx = rxq->ifr_ctx;
1818 if_shared_ctx_t sctx = ctx->ifc_sctx;
1819 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1820 device_t dev = ctx->ifc_dev;
1824 MPASS(scctx->isc_nrxd[0] > 0);
1825 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1828 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1829 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1830 /* Set up DMA tag for RX buffers. */
1831 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1832 1, 0, /* alignment, bounds */
1833 BUS_SPACE_MAXADDR, /* lowaddr */
1834 BUS_SPACE_MAXADDR, /* highaddr */
1835 NULL, NULL, /* filter, filterarg */
1836 sctx->isc_rx_maxsize, /* maxsize */
1837 sctx->isc_rx_nsegments, /* nsegments */
1838 sctx->isc_rx_maxsegsize, /* maxsegsize */
1840 NULL, /* lockfunc */
1845 "Unable to allocate RX DMA tag: %d\n", err);
1849 /* Allocate memory for the RX mbuf map. */
1850 if (!(fl->ifl_sds.ifsd_m =
1851 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1852 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1854 "Unable to allocate RX mbuf map memory\n");
1859 /* Allocate memory for the direct RX cluster pointer map. */
1860 if (!(fl->ifl_sds.ifsd_cl =
1861 (caddr_t *) malloc(sizeof(caddr_t) *
1862 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1864 "Unable to allocate RX cluster map memory\n");
1869 /* Allocate memory for the RX cluster bus address map. */
1870 if (!(fl->ifl_sds.ifsd_ba =
1871 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1872 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1874 "Unable to allocate RX bus address map memory\n");
1880 * Create the DMA maps for RX buffers.
1882 if (!(fl->ifl_sds.ifsd_map =
1883 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1885 "Unable to allocate RX buffer DMA map memory\n");
1889 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1890 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1891 &fl->ifl_sds.ifsd_map[i]);
1893 device_printf(dev, "Unable to create RX buffer DMA map\n");
1901 iflib_rx_structures_free(ctx);
1907 * Internal service routines
1910 struct rxq_refill_cb_arg {
1912 bus_dma_segment_t seg;
1917 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1919 struct rxq_refill_cb_arg *cb_arg = arg;
1921 cb_arg->error = error;
1922 cb_arg->seg = segs[0];
1923 cb_arg->nseg = nseg;
1927 * _iflib_fl_refill - refill an rxq free-buffer list
1928 * @ctx: the iflib context
1929 * @fl: the free list to refill
1930 * @count: the number of new buffers to allocate
1932 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1933 * The caller must assure that @count does not exceed the queue's capacity.
1936 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1938 struct if_rxd_update iru;
1939 struct rxq_refill_cb_arg cb_arg;
1943 bus_dmamap_t *sd_map;
1944 bus_addr_t bus_addr, *sd_ba;
1945 int err, frag_idx, i, idx, n, pidx;
1948 sd_m = fl->ifl_sds.ifsd_m;
1949 sd_map = fl->ifl_sds.ifsd_map;
1950 sd_cl = fl->ifl_sds.ifsd_cl;
1951 sd_ba = fl->ifl_sds.ifsd_ba;
1952 pidx = fl->ifl_pidx;
1954 frag_idx = fl->ifl_fragidx;
1955 credits = fl->ifl_credits;
1960 MPASS(credits + n <= fl->ifl_size);
1962 if (pidx < fl->ifl_cidx)
1963 MPASS(pidx + n <= fl->ifl_cidx);
1964 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1965 MPASS(fl->ifl_gen == 0);
1966 if (pidx > fl->ifl_cidx)
1967 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1969 DBG_COUNTER_INC(fl_refills);
1971 DBG_COUNTER_INC(fl_refills_large);
1972 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1975 * We allocate an uninitialized mbuf + cluster, mbuf is
1976 * initialized after rx.
1978 * If the cluster is still set then we know a minimum sized packet was received
1980 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1983 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1984 MPASS(frag_idx >= 0);
1985 if ((cl = sd_cl[frag_idx]) == NULL) {
1986 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1990 MPASS(sd_map != NULL);
1991 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1992 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1994 if (err != 0 || cb_arg.error) {
1998 if (fl->ifl_zone == zone_pack)
1999 uma_zfree(fl->ifl_zone, cl);
2003 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2004 sd_cl[frag_idx] = cl;
2006 fl->ifl_cl_enqueued++;
2009 bus_addr = sd_ba[frag_idx];
2011 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2012 BUS_DMASYNC_PREREAD);
2014 if (sd_m[frag_idx] == NULL) {
2015 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2020 bit_set(fl->ifl_rx_bitmap, frag_idx);
2022 fl->ifl_m_enqueued++;
2025 DBG_COUNTER_INC(rx_allocs);
2026 fl->ifl_rxd_idxs[i] = frag_idx;
2027 fl->ifl_bus_addrs[i] = bus_addr;
2028 fl->ifl_vm_addrs[i] = cl;
2031 MPASS(credits <= fl->ifl_size);
2032 if (++idx == fl->ifl_size) {
2036 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2037 iru.iru_pidx = pidx;
2039 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2043 fl->ifl_credits = credits;
2048 iru.iru_pidx = pidx;
2050 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2052 fl->ifl_credits = credits;
2054 DBG_COUNTER_INC(rxd_flush);
2055 if (fl->ifl_pidx == 0)
2056 pidx = fl->ifl_size - 1;
2058 pidx = fl->ifl_pidx - 1;
2060 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2061 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2062 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2063 fl->ifl_fragidx = frag_idx;
2066 static __inline void
2067 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2069 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2070 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2072 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2075 MPASS(fl->ifl_credits <= fl->ifl_size);
2076 MPASS(reclaimable == delta);
2078 if (reclaimable > 0)
2079 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2083 iflib_in_detach(if_ctx_t ctx)
2088 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2094 iflib_fl_bufs_free(iflib_fl_t fl)
2096 iflib_dma_info_t idi = fl->ifl_ifdi;
2097 bus_dmamap_t sd_map;
2100 for (i = 0; i < fl->ifl_size; i++) {
2101 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2102 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2104 if (*sd_cl != NULL) {
2105 sd_map = fl->ifl_sds.ifsd_map[i];
2106 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2107 BUS_DMASYNC_POSTREAD);
2108 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2110 uma_zfree(fl->ifl_zone, *sd_cl);
2111 // XXX: Should this get moved out?
2112 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2113 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2114 if (*sd_m != NULL) {
2115 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2116 uma_zfree(zone_mbuf, *sd_m);
2119 MPASS(*sd_cl == NULL);
2120 MPASS(*sd_m == NULL);
2123 fl->ifl_m_dequeued++;
2124 fl->ifl_cl_dequeued++;
2130 for (i = 0; i < fl->ifl_size; i++) {
2131 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2132 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2136 * Reset free list values
2138 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2139 bzero(idi->idi_vaddr, idi->idi_size);
2142 /*********************************************************************
2144 * Initialize a free list and its buffers.
2146 **********************************************************************/
2148 iflib_fl_setup(iflib_fl_t fl)
2150 iflib_rxq_t rxq = fl->ifl_rxq;
2151 if_ctx_t ctx = rxq->ifr_ctx;
2153 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2155 ** Free current RX buffer structs and their mbufs
2157 iflib_fl_bufs_free(fl);
2158 /* Now replenish the mbufs */
2159 MPASS(fl->ifl_credits == 0);
2160 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2161 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2162 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2163 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2164 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2167 /* avoid pre-allocating zillions of clusters to an idle card
2168 * potentially speeding up attach
2170 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2171 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2172 if (min(128, fl->ifl_size) != fl->ifl_credits)
2178 MPASS(fl->ifl_ifdi != NULL);
2179 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2180 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2184 /*********************************************************************
2186 * Free receive ring data structures
2188 **********************************************************************/
2190 iflib_rx_sds_free(iflib_rxq_t rxq)
2195 if (rxq->ifr_fl != NULL) {
2196 for (i = 0; i < rxq->ifr_nfl; i++) {
2197 fl = &rxq->ifr_fl[i];
2198 if (fl->ifl_buf_tag != NULL) {
2199 if (fl->ifl_sds.ifsd_map != NULL) {
2200 for (j = 0; j < fl->ifl_size; j++) {
2201 if (fl->ifl_sds.ifsd_map[j] ==
2206 fl->ifl_sds.ifsd_map[j],
2207 BUS_DMASYNC_POSTREAD);
2210 fl->ifl_sds.ifsd_map[j]);
2213 bus_dma_tag_destroy(fl->ifl_buf_tag);
2214 fl->ifl_buf_tag = NULL;
2216 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2217 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2218 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2219 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2220 fl->ifl_sds.ifsd_m = NULL;
2221 fl->ifl_sds.ifsd_cl = NULL;
2222 fl->ifl_sds.ifsd_ba = NULL;
2223 fl->ifl_sds.ifsd_map = NULL;
2225 free(rxq->ifr_fl, M_IFLIB);
2227 rxq->ifr_cq_cidx = 0;
2235 iflib_timer(void *arg)
2237 iflib_txq_t txq = arg;
2238 if_ctx_t ctx = txq->ift_ctx;
2239 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2240 uint64_t this_tick = ticks;
2241 uint32_t reset_on = hz / 2;
2243 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2247 ** Check on the state of the TX queue(s), this
2248 ** can be done without the lock because its RO
2249 ** and the HUNG state will be static if set.
2251 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2252 txq->ift_last_timer_tick = this_tick;
2253 IFDI_TIMER(ctx, txq->ift_id);
2254 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2255 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2256 (sctx->isc_pause_frames == 0)))
2259 if (ifmp_ring_is_stalled(txq->ift_br))
2260 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2261 txq->ift_cleaned_prev = txq->ift_cleaned;
2264 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2265 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2267 /* handle any laggards */
2268 if (txq->ift_db_pending)
2269 GROUPTASK_ENQUEUE(&txq->ift_task);
2271 sctx->isc_pause_frames = 0;
2272 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2273 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2277 device_printf(ctx->ifc_dev,
2278 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2279 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2281 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2282 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2283 iflib_admin_intr_deferred(ctx);
2288 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2290 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2293 * XXX don't set the max_frame_size to larger
2294 * than the hardware can handle
2296 if (sctx->isc_max_frame_size <= MCLBYTES)
2297 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2299 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2303 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2306 return (ctx->ifc_rx_mbuf_sz);
2310 iflib_init_locked(if_ctx_t ctx)
2312 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2313 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2314 if_t ifp = ctx->ifc_ifp;
2318 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2320 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2321 IFDI_INTR_DISABLE(ctx);
2323 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2324 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2325 /* Set hardware offload abilities */
2326 if_clearhwassist(ifp);
2327 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2328 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2329 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2330 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2331 if (if_getcapenable(ifp) & IFCAP_TSO4)
2332 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2333 if (if_getcapenable(ifp) & IFCAP_TSO6)
2334 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2336 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2338 callout_stop(&txq->ift_timer);
2339 CALLOUT_UNLOCK(txq);
2340 iflib_netmap_txq_init(ctx, txq);
2344 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2345 * that drivers can use the value when setting up the hardware receive
2348 iflib_calc_rx_mbuf_sz(ctx);
2351 i = if_getdrvflags(ifp);
2354 MPASS(if_getdrvflags(ifp) == i);
2355 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2356 /* XXX this should really be done on a per-queue basis */
2357 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2358 MPASS(rxq->ifr_id == i);
2359 iflib_netmap_rxq_init(ctx, rxq);
2362 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2363 if (iflib_fl_setup(fl)) {
2364 device_printf(ctx->ifc_dev,
2365 "setting up free list %d failed - "
2366 "check cluster settings\n", j);
2372 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2373 IFDI_INTR_ENABLE(ctx);
2374 txq = ctx->ifc_txqs;
2375 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2376 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2377 txq->ift_timer.c_cpu);
2381 iflib_media_change(if_t ifp)
2383 if_ctx_t ctx = if_getsoftc(ifp);
2387 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2388 iflib_init_locked(ctx);
2394 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2396 if_ctx_t ctx = if_getsoftc(ifp);
2399 IFDI_UPDATE_ADMIN_STATUS(ctx);
2400 IFDI_MEDIA_STATUS(ctx, ifmr);
2405 iflib_stop(if_ctx_t ctx)
2407 iflib_txq_t txq = ctx->ifc_txqs;
2408 iflib_rxq_t rxq = ctx->ifc_rxqs;
2409 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2410 if_shared_ctx_t sctx = ctx->ifc_sctx;
2411 iflib_dma_info_t di;
2415 /* Tell the stack that the interface is no longer active */
2416 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2418 IFDI_INTR_DISABLE(ctx);
2423 iflib_debug_reset();
2424 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2425 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2426 /* make sure all transmitters have completed before proceeding XXX */
2429 callout_stop(&txq->ift_timer);
2430 CALLOUT_UNLOCK(txq);
2432 /* clean any enqueued buffers */
2433 iflib_ifmp_purge(txq);
2434 /* Free any existing tx buffers. */
2435 for (j = 0; j < txq->ift_size; j++) {
2436 iflib_txsd_free(ctx, txq, j);
2438 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2439 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2440 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2441 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2442 txq->ift_pullups = 0;
2443 ifmp_ring_reset_stats(txq->ift_br);
2444 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2445 bzero((void *)di->idi_vaddr, di->idi_size);
2447 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2448 /* make sure all transmitters have completed before proceeding XXX */
2450 rxq->ifr_cq_cidx = 0;
2451 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2452 bzero((void *)di->idi_vaddr, di->idi_size);
2453 /* also resets the free lists pidx/cidx */
2454 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2455 iflib_fl_bufs_free(fl);
2459 static inline caddr_t
2460 calc_next_rxd(iflib_fl_t fl, int cidx)
2464 caddr_t start, end, cur, next;
2466 nrxd = fl->ifl_size;
2467 size = fl->ifl_rxd_size;
2468 start = fl->ifl_ifdi->idi_vaddr;
2470 if (__predict_false(size == 0))
2472 cur = start + size*cidx;
2473 end = start + size*nrxd;
2474 next = CACHE_PTR_NEXT(cur);
2475 return (next < end ? next : start);
2479 prefetch_pkts(iflib_fl_t fl, int cidx)
2482 int nrxd = fl->ifl_size;
2486 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2487 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2488 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2489 next_rxd = calc_next_rxd(fl, cidx);
2491 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2494 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2495 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2498 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2501 static struct mbuf *
2502 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2503 int *pf_rv, if_rxd_info_t ri)
2509 int flid, cidx, len, next;
2512 flid = irf->irf_flid;
2513 cidx = irf->irf_idx;
2514 fl = &rxq->ifr_fl[flid];
2516 sd->ifsd_cidx = cidx;
2517 m = fl->ifl_sds.ifsd_m[cidx];
2518 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2521 fl->ifl_m_dequeued++;
2523 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2524 prefetch_pkts(fl, cidx);
2525 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2526 prefetch(&fl->ifl_sds.ifsd_map[next]);
2527 map = fl->ifl_sds.ifsd_map[cidx];
2528 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2530 /* not valid assert if bxe really does SGE from non-contiguous elements */
2531 MPASS(fl->ifl_cidx == cidx);
2532 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2534 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2535 payload = *sd->ifsd_cl;
2536 payload += ri->iri_pad;
2537 len = ri->iri_len - ri->iri_pad;
2538 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2539 len | PFIL_MEMPTR | PFIL_IN, NULL);
2544 * The filter ate it. Everything is recycled.
2549 case PFIL_REALLOCED:
2551 * The filter copied it. Everything is recycled.
2553 m = pfil_mem2mbuf(payload);
2558 * Filter said it was OK, so receive like
2561 fl->ifl_sds.ifsd_m[cidx] = NULL;
2567 fl->ifl_sds.ifsd_m[cidx] = NULL;
2572 bus_dmamap_unload(fl->ifl_buf_tag, map);
2573 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2574 if (__predict_false(fl->ifl_cidx == 0))
2576 bit_clear(fl->ifl_rx_bitmap, cidx);
2580 static struct mbuf *
2581 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2583 struct mbuf *m, *mh, *mt;
2585 int *pf_rv_ptr, flags, i, padlen;
2594 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2597 MPASS(*sd->ifsd_cl != NULL);
2600 * Exclude zero-length frags & frags from
2601 * packets the filter has consumed or dropped
2603 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2604 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2606 /* everything saved here */
2611 /* XXX we can save the cluster here, but not the mbuf */
2612 m_init(m, M_NOWAIT, MT_DATA, 0);
2617 flags = M_PKTHDR|M_EXT;
2619 padlen = ri->iri_pad;
2624 /* assuming padding is only on the first fragment */
2628 *sd->ifsd_cl = NULL;
2630 /* Can these two be made one ? */
2631 m_init(m, M_NOWAIT, MT_DATA, flags);
2632 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2634 * These must follow m_init and m_cljset
2636 m->m_data += padlen;
2637 ri->iri_len -= padlen;
2638 m->m_len = ri->iri_frags[i].irf_len;
2639 } while (++i < ri->iri_nfrags);
2645 * Process one software descriptor
2647 static struct mbuf *
2648 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2654 /* should I merge this back in now that the two paths are basically duplicated? */
2655 if (ri->iri_nfrags == 1 &&
2656 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2657 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2659 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2661 if (pf_rv == PFIL_PASS) {
2662 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2663 #ifndef __NO_STRICT_ALIGNMENT
2667 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2668 m->m_len = ri->iri_frags[0].irf_len;
2671 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2672 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2675 m->m_pkthdr.len = ri->iri_len;
2676 m->m_pkthdr.rcvif = ri->iri_ifp;
2677 m->m_flags |= ri->iri_flags;
2678 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2679 m->m_pkthdr.flowid = ri->iri_flowid;
2680 M_HASHTYPE_SET(m, ri->iri_rsstype);
2681 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2682 m->m_pkthdr.csum_data = ri->iri_csum_data;
2686 #if defined(INET6) || defined(INET)
2688 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2690 CURVNET_SET(lc->ifp->if_vnet);
2692 *v6 = V_ip6_forwarding;
2695 *v4 = V_ipforwarding;
2701 * Returns true if it's possible this packet could be LROed.
2702 * if it returns false, it is guaranteed that tcp_lro_rx()
2703 * would not return zero.
2706 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2708 struct ether_header *eh;
2710 eh = mtod(m, struct ether_header *);
2711 switch (eh->ether_type) {
2713 case htons(ETHERTYPE_IPV6):
2714 return (!v6_forwarding);
2717 case htons(ETHERTYPE_IP):
2718 return (!v4_forwarding);
2726 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2732 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2735 if_ctx_t ctx = rxq->ifr_ctx;
2736 if_shared_ctx_t sctx = ctx->ifc_sctx;
2737 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2740 struct if_rxd_info ri;
2741 int err, budget_left, rx_bytes, rx_pkts;
2744 bool v4_forwarding, v6_forwarding, lro_possible;
2747 * XXX early demux data packets so that if_input processing only handles
2748 * acks in interrupt context
2750 struct mbuf *m, *mh, *mt, *mf;
2752 lro_possible = v4_forwarding = v6_forwarding = false;
2756 rx_pkts = rx_bytes = 0;
2757 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2758 cidxp = &rxq->ifr_cq_cidx;
2760 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2761 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2762 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2763 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2764 DBG_COUNTER_INC(rx_unavail);
2768 /* pfil needs the vnet to be set */
2769 CURVNET_SET_QUIET(ifp->if_vnet);
2770 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2771 if (__predict_false(!CTX_ACTIVE(ctx))) {
2772 DBG_COUNTER_INC(rx_ctx_inactive);
2776 * Reset client set fields to their default values
2779 ri.iri_qsidx = rxq->ifr_id;
2780 ri.iri_cidx = *cidxp;
2782 ri.iri_frags = rxq->ifr_frags;
2783 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2788 rx_bytes += ri.iri_len;
2789 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2790 *cidxp = ri.iri_cidx;
2791 /* Update our consumer index */
2792 /* XXX NB: shurd - check if this is still safe */
2793 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2794 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2795 /* was this only a completion queue message? */
2796 if (__predict_false(ri.iri_nfrags == 0))
2799 MPASS(ri.iri_nfrags != 0);
2800 MPASS(ri.iri_len != 0);
2802 /* will advance the cidx on the corresponding free lists */
2803 m = iflib_rxd_pkt_get(rxq, &ri);
2806 if (avail == 0 && budget_left)
2807 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2809 if (__predict_false(m == NULL))
2812 /* imm_pkt: -- cxgb */
2821 /* make sure that we can refill faster than drain */
2822 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2823 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2825 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2827 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2829 while (mh != NULL) {
2832 m->m_nextpkt = NULL;
2833 #ifndef __NO_STRICT_ALIGNMENT
2834 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2837 rx_bytes += m->m_pkthdr.len;
2839 #if defined(INET6) || defined(INET)
2841 if (!lro_possible) {
2842 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2843 if (lro_possible && mf != NULL) {
2844 ifp->if_input(ifp, mf);
2845 DBG_COUNTER_INC(rx_if_input);
2849 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2850 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2851 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2857 ifp->if_input(ifp, m);
2858 DBG_COUNTER_INC(rx_if_input);
2869 ifp->if_input(ifp, mf);
2870 DBG_COUNTER_INC(rx_if_input);
2873 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2874 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2877 * Flush any outstanding LRO work
2879 #if defined(INET6) || defined(INET)
2880 tcp_lro_flush_all(&rxq->ifr_lc);
2884 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2887 ctx->ifc_flags |= IFC_DO_RESET;
2888 iflib_admin_intr_deferred(ctx);
2893 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2894 static inline qidx_t
2895 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2897 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2898 qidx_t minthresh = txq->ift_size / 8;
2899 if (in_use > 4*minthresh)
2900 return (notify_count);
2901 if (in_use > 2*minthresh)
2902 return (notify_count >> 1);
2903 if (in_use > minthresh)
2904 return (notify_count >> 3);
2908 static inline qidx_t
2909 txq_max_rs_deferred(iflib_txq_t txq)
2911 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2912 qidx_t minthresh = txq->ift_size / 8;
2913 if (txq->ift_in_use > 4*minthresh)
2914 return (notify_count);
2915 if (txq->ift_in_use > 2*minthresh)
2916 return (notify_count >> 1);
2917 if (txq->ift_in_use > minthresh)
2918 return (notify_count >> 2);
2922 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2923 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2925 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2926 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2927 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2929 /* forward compatibility for cxgb */
2930 #define FIRST_QSET(ctx) 0
2931 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2932 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2933 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2934 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2936 /* XXX we should be setting this to something other than zero */
2937 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2938 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2939 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2942 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2948 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2949 if (ring || txq->ift_db_pending >= max) {
2950 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2951 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2953 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2954 txq->ift_db_pending = txq->ift_npending = 0;
2962 print_pkt(if_pkt_info_t pi)
2964 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2965 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2966 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2967 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2968 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2969 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2973 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2974 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2975 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2976 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2979 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2981 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2982 struct ether_vlan_header *eh;
2986 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2987 M_WRITABLE(m) == 0) {
2988 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2992 DBG_COUNTER_INC(tx_frees);
2998 * Determine where frame payload starts.
2999 * Jump over vlan headers if already present,
3000 * helpful for QinQ too.
3002 if (__predict_false(m->m_len < sizeof(*eh))) {
3004 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3007 eh = mtod(m, struct ether_vlan_header *);
3008 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3009 pi->ipi_etype = ntohs(eh->evl_proto);
3010 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3012 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3013 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3016 switch (pi->ipi_etype) {
3021 struct ip *ip = NULL;
3022 struct tcphdr *th = NULL;
3025 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3026 if (__predict_false(m->m_len < minthlen)) {
3028 * if this code bloat is causing too much of a hit
3029 * move it to a separate function and mark it noinline
3031 if (m->m_len == pi->ipi_ehdrlen) {
3034 if (n->m_len >= sizeof(*ip)) {
3035 ip = (struct ip *)n->m_data;
3036 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3037 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3040 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3042 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3046 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3048 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3049 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3050 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3053 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3054 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3055 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3057 pi->ipi_ip_hlen = ip->ip_hl << 2;
3058 pi->ipi_ipproto = ip->ip_p;
3059 pi->ipi_flags |= IPI_TX_IPV4;
3061 /* TCP checksum offload may require TCP header length */
3062 if (IS_TX_OFFLOAD4(pi)) {
3063 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3064 if (__predict_false(th == NULL)) {
3066 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3068 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3070 pi->ipi_tcp_hflags = th->th_flags;
3071 pi->ipi_tcp_hlen = th->th_off << 2;
3072 pi->ipi_tcp_seq = th->th_seq;
3075 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3078 * TSO always requires hardware checksum offload.
3080 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3081 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3082 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3083 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3084 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3086 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3090 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3097 case ETHERTYPE_IPV6:
3099 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3101 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3103 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3105 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3108 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3110 /* XXX-BZ this will go badly in case of ext hdrs. */
3111 pi->ipi_ipproto = ip6->ip6_nxt;
3112 pi->ipi_flags |= IPI_TX_IPV6;
3114 /* TCP checksum offload may require TCP header length */
3115 if (IS_TX_OFFLOAD6(pi)) {
3116 if (pi->ipi_ipproto == IPPROTO_TCP) {
3117 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3119 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3122 pi->ipi_tcp_hflags = th->th_flags;
3123 pi->ipi_tcp_hlen = th->th_off << 2;
3124 pi->ipi_tcp_seq = th->th_seq;
3127 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3130 * TSO always requires hardware checksum offload.
3132 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3133 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3134 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3141 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3142 pi->ipi_ip_hlen = 0;
3151 * If dodgy hardware rejects the scatter gather chain we've handed it
3152 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3155 static __noinline struct mbuf *
3156 iflib_remove_mbuf(iflib_txq_t txq)
3159 struct mbuf *m, **ifsd_m;
3161 ifsd_m = txq->ift_sds.ifsd_m;
3162 ntxd = txq->ift_size;
3163 pidx = txq->ift_pidx & (ntxd - 1);
3164 ifsd_m = txq->ift_sds.ifsd_m;
3166 ifsd_m[pidx] = NULL;
3167 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3168 if (txq->ift_sds.ifsd_tso_map != NULL)
3169 bus_dmamap_unload(txq->ift_tso_buf_tag,
3170 txq->ift_sds.ifsd_tso_map[pidx]);
3172 txq->ift_dequeued++;
3177 static inline caddr_t
3178 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3182 caddr_t start, end, cur, next;
3184 ntxd = txq->ift_size;
3185 size = txq->ift_txd_size[qid];
3186 start = txq->ift_ifdi[qid].idi_vaddr;
3188 if (__predict_false(size == 0))
3190 cur = start + size*cidx;
3191 end = start + size*ntxd;
3192 next = CACHE_PTR_NEXT(cur);
3193 return (next < end ? next : start);
3197 * Pad an mbuf to ensure a minimum ethernet frame size.
3198 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3200 static __noinline int
3201 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3204 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3205 * and ARP message is the smallest common payload I can think of
3207 static char pad[18]; /* just zeros */
3209 struct mbuf *new_head;
3211 if (!M_WRITABLE(*m_head)) {
3212 new_head = m_dup(*m_head, M_NOWAIT);
3213 if (new_head == NULL) {
3215 device_printf(dev, "cannot pad short frame, m_dup() failed");
3216 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3217 DBG_COUNTER_INC(tx_frees);
3224 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3225 n > 0; n -= sizeof(pad))
3226 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3231 device_printf(dev, "cannot pad short frame\n");
3232 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3233 DBG_COUNTER_INC(tx_frees);
3241 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3244 if_shared_ctx_t sctx;
3245 if_softc_ctx_t scctx;
3246 bus_dma_tag_t buf_tag;
3247 bus_dma_segment_t *segs;
3248 struct mbuf *m_head, **ifsd_m;
3251 struct if_pkt_info pi;
3253 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3256 sctx = ctx->ifc_sctx;
3257 scctx = &ctx->ifc_softc_ctx;
3258 segs = txq->ift_segs;
3259 ntxd = txq->ift_size;
3264 * If we're doing TSO the next descriptor to clean may be quite far ahead
3266 cidx = txq->ift_cidx;
3267 pidx = txq->ift_pidx;
3268 if (ctx->ifc_flags & IFC_PREFETCH) {
3269 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3270 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3271 next_txd = calc_next_txd(txq, cidx, 0);
3275 /* prefetch the next cache line of mbuf pointers and flags */
3276 prefetch(&txq->ift_sds.ifsd_m[next]);
3277 prefetch(&txq->ift_sds.ifsd_map[next]);
3278 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3280 map = txq->ift_sds.ifsd_map[pidx];
3281 ifsd_m = txq->ift_sds.ifsd_m;
3283 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3284 buf_tag = txq->ift_tso_buf_tag;
3285 max_segs = scctx->isc_tx_tso_segments_max;
3286 map = txq->ift_sds.ifsd_tso_map[pidx];
3287 MPASS(buf_tag != NULL);
3288 MPASS(max_segs > 0);
3290 buf_tag = txq->ift_buf_tag;
3291 max_segs = scctx->isc_tx_nsegments;
3292 map = txq->ift_sds.ifsd_map[pidx];
3294 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3295 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3296 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3298 DBG_COUNTER_INC(encap_txd_encap_fail);
3305 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3307 pi.ipi_qsidx = txq->ift_id;
3308 pi.ipi_len = m_head->m_pkthdr.len;
3309 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3310 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3312 /* deliberate bitwise OR to make one condition */
3313 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3314 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3315 DBG_COUNTER_INC(encap_txd_encap_fail);
3322 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3325 if (__predict_false(err)) {
3328 /* try collapse once and defrag once */
3330 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3331 /* try defrag if collapsing fails */
3336 txq->ift_mbuf_defrag++;
3337 m_head = m_defrag(*m_headp, M_NOWAIT);
3340 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3341 * failed to map an mbuf that was run through m_defrag
3344 if (__predict_false(m_head == NULL || remap > 1))
3351 txq->ift_no_tx_dma_setup++;
3354 txq->ift_no_tx_dma_setup++;
3356 DBG_COUNTER_INC(tx_frees);
3360 txq->ift_map_failed++;
3361 DBG_COUNTER_INC(encap_load_mbuf_fail);
3362 DBG_COUNTER_INC(encap_txd_encap_fail);
3365 ifsd_m[pidx] = m_head;
3367 * XXX assumes a 1 to 1 relationship between segments and
3368 * descriptors - this does not hold true on all drivers, e.g.
3371 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3372 txq->ift_no_desc_avail++;
3373 bus_dmamap_unload(buf_tag, map);
3374 DBG_COUNTER_INC(encap_txq_avail_fail);
3375 DBG_COUNTER_INC(encap_txd_encap_fail);
3376 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3377 GROUPTASK_ENQUEUE(&txq->ift_task);
3381 * On Intel cards we can greatly reduce the number of TX interrupts
3382 * we see by only setting report status on every Nth descriptor.
3383 * However, this also means that the driver will need to keep track
3384 * of the descriptors that RS was set on to check them for the DD bit.
3386 txq->ift_rs_pending += nsegs + 1;
3387 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3388 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3389 pi.ipi_flags |= IPI_TX_INTR;
3390 txq->ift_rs_pending = 0;
3394 pi.ipi_nsegs = nsegs;
3396 MPASS(pidx >= 0 && pidx < txq->ift_size);
3400 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3401 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3402 DBG_COUNTER_INC(tx_encap);
3403 MPASS(pi.ipi_new_pidx < txq->ift_size);
3405 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3406 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3407 ndesc += txq->ift_size;
3411 * drivers can need as many as
3414 MPASS(ndesc <= pi.ipi_nsegs + 2);
3415 MPASS(pi.ipi_new_pidx != pidx);
3417 txq->ift_in_use += ndesc;
3420 * We update the last software descriptor again here because there may
3421 * be a sentinel and/or there may be more mbufs than segments
3423 txq->ift_pidx = pi.ipi_new_pidx;
3424 txq->ift_npending += pi.ipi_ndescs;
3426 *m_headp = m_head = iflib_remove_mbuf(txq);
3428 txq->ift_txd_encap_efbig++;
3437 * err can't possibly be non-zero here, so we don't neet to test it
3438 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3443 txq->ift_mbuf_defrag_failed++;
3444 txq->ift_map_failed++;
3446 DBG_COUNTER_INC(tx_frees);
3448 DBG_COUNTER_INC(encap_txd_encap_fail);
3453 iflib_tx_desc_free(iflib_txq_t txq, int n)
3455 uint32_t qsize, cidx, mask, gen;
3456 struct mbuf *m, **ifsd_m;
3459 cidx = txq->ift_cidx;
3461 qsize = txq->ift_size;
3463 ifsd_m = txq->ift_sds.ifsd_m;
3464 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3468 prefetch(ifsd_m[(cidx + 3) & mask]);
3469 prefetch(ifsd_m[(cidx + 4) & mask]);
3471 if ((m = ifsd_m[cidx]) != NULL) {
3472 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3473 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3474 bus_dmamap_sync(txq->ift_tso_buf_tag,
3475 txq->ift_sds.ifsd_tso_map[cidx],
3476 BUS_DMASYNC_POSTWRITE);
3477 bus_dmamap_unload(txq->ift_tso_buf_tag,
3478 txq->ift_sds.ifsd_tso_map[cidx]);
3480 bus_dmamap_sync(txq->ift_buf_tag,
3481 txq->ift_sds.ifsd_map[cidx],
3482 BUS_DMASYNC_POSTWRITE);
3483 bus_dmamap_unload(txq->ift_buf_tag,
3484 txq->ift_sds.ifsd_map[cidx]);
3486 /* XXX we don't support any drivers that batch packets yet */
3487 MPASS(m->m_nextpkt == NULL);
3489 ifsd_m[cidx] = NULL;
3491 txq->ift_dequeued++;
3493 DBG_COUNTER_INC(tx_frees);
3495 if (__predict_false(++cidx == qsize)) {
3500 txq->ift_cidx = cidx;
3505 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3508 if_ctx_t ctx = txq->ift_ctx;
3510 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3511 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3514 * Need a rate-limiting check so that this isn't called every time
3516 iflib_tx_credits_update(ctx, txq);
3517 reclaim = DESC_RECLAIMABLE(txq);
3519 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3521 if (iflib_verbose_debug) {
3522 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3523 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3530 iflib_tx_desc_free(txq, reclaim);
3531 txq->ift_cleaned += reclaim;
3532 txq->ift_in_use -= reclaim;
3537 static struct mbuf **
3538 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3541 struct mbuf **items;
3544 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3545 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3547 prefetch(items[(cidx + offset) & (size-1)]);
3548 if (remaining > 1) {
3549 prefetch2cachelines(&items[next]);
3550 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3551 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3552 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3554 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3558 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3561 ifmp_ring_check_drainage(txq->ift_br, budget);
3565 iflib_txq_can_drain(struct ifmp_ring *r)
3567 iflib_txq_t txq = r->cookie;
3568 if_ctx_t ctx = txq->ift_ctx;
3570 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3572 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3573 BUS_DMASYNC_POSTREAD);
3574 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3579 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3581 iflib_txq_t txq = r->cookie;
3582 if_ctx_t ctx = txq->ift_ctx;
3583 if_t ifp = ctx->ifc_ifp;
3584 struct mbuf *m, **mp;
3585 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3586 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3587 bool do_prefetch, rang, ring;
3589 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3590 !LINK_ACTIVE(ctx))) {
3591 DBG_COUNTER_INC(txq_drain_notready);
3594 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3595 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3596 avail = IDXDIFF(pidx, cidx, r->size);
3597 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3598 DBG_COUNTER_INC(txq_drain_flushing);
3599 for (i = 0; i < avail; i++) {
3600 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3601 m_free(r->items[(cidx + i) & (r->size-1)]);
3602 r->items[(cidx + i) & (r->size-1)] = NULL;
3607 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3608 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3610 callout_stop(&txq->ift_timer);
3611 CALLOUT_UNLOCK(txq);
3612 DBG_COUNTER_INC(txq_drain_oactive);
3616 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3617 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3618 count = MIN(avail, TX_BATCH_SIZE);
3620 if (iflib_verbose_debug)
3621 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3622 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3624 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3625 txq_avail = TXQ_AVAIL(txq);
3627 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3628 int rem = do_prefetch ? count - i : 0;
3630 mp = _ring_peek_one(r, cidx, i, rem);
3631 MPASS(mp != NULL && *mp != NULL);
3632 if (__predict_false(*mp == (struct mbuf *)txq)) {
3636 in_use_prev = txq->ift_in_use;
3637 err = iflib_encap(txq, mp);
3638 if (__predict_false(err)) {
3639 /* no room - bail out */
3643 /* we can't send this packet - skip it */
3649 DBG_COUNTER_INC(tx_sent);
3650 bytes_sent += m->m_pkthdr.len;
3651 mcast_sent += !!(m->m_flags & M_MCAST);
3652 txq_avail = TXQ_AVAIL(txq);
3654 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3655 ETHER_BPF_MTAP(ifp, m);
3656 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3658 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3661 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3662 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3663 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3664 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3665 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3667 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3669 if (iflib_verbose_debug)
3670 printf("consumed=%d\n", consumed);
3676 iflib_txq_drain_always(struct ifmp_ring *r)
3682 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3690 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3692 callout_stop(&txq->ift_timer);
3693 CALLOUT_UNLOCK(txq);
3695 avail = IDXDIFF(pidx, cidx, r->size);
3696 for (i = 0; i < avail; i++) {
3697 mp = _ring_peek_one(r, cidx, i, avail - i);
3698 if (__predict_false(*mp == (struct mbuf *)txq))
3701 DBG_COUNTER_INC(tx_frees);
3703 MPASS(ifmp_ring_is_stalled(r) == 0);
3708 iflib_ifmp_purge(iflib_txq_t txq)
3710 struct ifmp_ring *r;
3713 r->drain = iflib_txq_drain_free;
3714 r->can_drain = iflib_txq_drain_always;
3716 ifmp_ring_check_drainage(r, r->size);
3718 r->drain = iflib_txq_drain;
3719 r->can_drain = iflib_txq_can_drain;
3723 _task_fn_tx(void *context)
3725 iflib_txq_t txq = context;
3726 if_ctx_t ctx = txq->ift_ctx;
3727 #if defined(ALTQ) || defined(DEV_NETMAP)
3728 if_t ifp = ctx->ifc_ifp;
3730 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3732 #ifdef IFLIB_DIAGNOSTICS
3733 txq->ift_cpu_exec_count[curcpu]++;
3735 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3738 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3739 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3740 BUS_DMASYNC_POSTREAD);
3741 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3742 netmap_tx_irq(ifp, txq->ift_id);
3743 if (ctx->ifc_flags & IFC_LEGACY)
3744 IFDI_INTR_ENABLE(ctx);
3746 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3751 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3752 iflib_altq_if_start(ifp);
3754 if (txq->ift_db_pending)
3755 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3757 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3759 * When abdicating, we always need to check drainage, not just when we don't enqueue
3762 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3763 if (ctx->ifc_flags & IFC_LEGACY)
3764 IFDI_INTR_ENABLE(ctx);
3766 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3770 _task_fn_rx(void *context)
3772 iflib_rxq_t rxq = context;
3773 if_ctx_t ctx = rxq->ifr_ctx;
3777 #ifdef IFLIB_DIAGNOSTICS
3778 rxq->ifr_cpu_exec_count[curcpu]++;
3780 DBG_COUNTER_INC(task_fn_rxs);
3781 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3785 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3787 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3792 budget = ctx->ifc_sysctl_rx_budget;
3794 budget = 16; /* XXX */
3795 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3796 if (ctx->ifc_flags & IFC_LEGACY)
3797 IFDI_INTR_ENABLE(ctx);
3799 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3800 DBG_COUNTER_INC(rx_intr_enables);
3802 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3805 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3809 _task_fn_admin(void *context)
3811 if_ctx_t ctx = context;
3812 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3815 bool oactive, running, do_reset, do_watchdog, in_detach;
3816 uint32_t reset_on = hz / 2;
3819 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3820 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3821 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3822 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3823 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3824 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3827 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3833 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3835 callout_stop(&txq->ift_timer);
3836 CALLOUT_UNLOCK(txq);
3839 ctx->ifc_watchdog_events++;
3840 IFDI_WATCHDOG_RESET(ctx);
3842 IFDI_UPDATE_ADMIN_STATUS(ctx);
3843 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3846 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3847 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3849 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3851 IFDI_LINK_INTR_ENABLE(ctx);
3853 iflib_if_init_locked(ctx);
3856 if (LINK_ACTIVE(ctx) == 0)
3858 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3859 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3864 _task_fn_iov(void *context)
3866 if_ctx_t ctx = context;
3868 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3869 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3873 IFDI_VFLR_HANDLE(ctx);
3878 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3881 if_int_delay_info_t info;
3884 info = (if_int_delay_info_t)arg1;
3885 ctx = info->iidi_ctx;
3886 info->iidi_req = req;
3887 info->iidi_oidp = oidp;
3889 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3894 /*********************************************************************
3898 **********************************************************************/
3901 iflib_if_init_locked(if_ctx_t ctx)
3904 iflib_init_locked(ctx);
3909 iflib_if_init(void *arg)
3914 iflib_if_init_locked(ctx);
3919 iflib_if_transmit(if_t ifp, struct mbuf *m)
3921 if_ctx_t ctx = if_getsoftc(ifp);
3925 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3927 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3928 DBG_COUNTER_INC(tx_frees);
3933 MPASS(m->m_nextpkt == NULL);
3934 /* ALTQ-enabled interfaces always use queue 0. */
3936 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3937 qidx = QIDX(ctx, m);
3939 * XXX calculate buf_ring based on flowid (divvy up bits?)
3941 txq = &ctx->ifc_txqs[qidx];
3943 #ifdef DRIVER_BACKPRESSURE
3944 if (txq->ift_closed) {
3946 next = m->m_nextpkt;
3947 m->m_nextpkt = NULL;
3949 DBG_COUNTER_INC(tx_frees);
3961 next = next->m_nextpkt;
3962 } while (next != NULL);
3964 if (count > nitems(marr))
3965 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3966 /* XXX check nextpkt */
3968 /* XXX simplify for now */
3969 DBG_COUNTER_INC(tx_frees);
3972 for (next = m, i = 0; next != NULL; i++) {
3974 next = next->m_nextpkt;
3975 mp[i]->m_nextpkt = NULL;
3978 DBG_COUNTER_INC(tx_seen);
3979 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3982 GROUPTASK_ENQUEUE(&txq->ift_task);
3985 GROUPTASK_ENQUEUE(&txq->ift_task);
3986 /* support forthcoming later */
3987 #ifdef DRIVER_BACKPRESSURE
3988 txq->ift_closed = TRUE;
3990 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3992 DBG_COUNTER_INC(tx_frees);
4000 * The overall approach to integrating iflib with ALTQ is to continue to use
4001 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4002 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4003 * is redundant/unnecessary, but doing so minimizes the amount of
4004 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4005 * redundantly queueing to an intermediate mp_ring is swamped by the
4006 * performance limitations inherent in using ALTQ.
4008 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4009 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4010 * given interface. If ALTQ is enabled for an interface, then all
4011 * transmitted packets for that interface will be submitted to the ALTQ
4012 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4013 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4014 * update stats that the iflib machinery handles, and which is sensitve to
4015 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4016 * will be installed as the start routine for use by ALTQ facilities that
4017 * need to trigger queue drains on a scheduled basis.
4021 iflib_altq_if_start(if_t ifp)
4023 struct ifaltq *ifq = &ifp->if_snd;
4027 IFQ_DEQUEUE_NOLOCK(ifq, m);
4029 iflib_if_transmit(ifp, m);
4030 IFQ_DEQUEUE_NOLOCK(ifq, m);
4036 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4040 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4041 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4043 iflib_altq_if_start(ifp);
4045 err = iflib_if_transmit(ifp, m);
4052 iflib_if_qflush(if_t ifp)
4054 if_ctx_t ctx = if_getsoftc(ifp);
4055 iflib_txq_t txq = ctx->ifc_txqs;
4059 ctx->ifc_flags |= IFC_QFLUSH;
4061 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4062 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4063 iflib_txq_check_drain(txq, 0);
4065 ctx->ifc_flags &= ~IFC_QFLUSH;
4069 * When ALTQ is enabled, this will also take care of purging the
4076 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4077 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4078 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4079 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4082 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4084 if_ctx_t ctx = if_getsoftc(ifp);
4085 struct ifreq *ifr = (struct ifreq *)data;
4086 #if defined(INET) || defined(INET6)
4087 struct ifaddr *ifa = (struct ifaddr *)data;
4089 bool avoid_reset = false;
4090 int err = 0, reinit = 0, bits;
4095 if (ifa->ifa_addr->sa_family == AF_INET)
4099 if (ifa->ifa_addr->sa_family == AF_INET6)
4103 ** Calling init results in link renegotiation,
4104 ** so we avoid doing it when possible.
4107 if_setflagbits(ifp, IFF_UP,0);
4108 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4111 if (!(if_getflags(ifp) & IFF_NOARP))
4112 arp_ifinit(ifp, ifa);
4115 err = ether_ioctl(ifp, command, data);
4119 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4123 bits = if_getdrvflags(ifp);
4124 /* stop the driver and free any clusters before proceeding */
4127 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4129 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4130 ctx->ifc_flags |= IFC_MULTISEG;
4132 ctx->ifc_flags &= ~IFC_MULTISEG;
4134 err = if_setmtu(ifp, ifr->ifr_mtu);
4136 iflib_init_locked(ctx);
4138 if_setdrvflags(ifp, bits);
4144 if (if_getflags(ifp) & IFF_UP) {
4145 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4146 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4147 (IFF_PROMISC | IFF_ALLMULTI)) {
4148 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4152 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4155 ctx->ifc_if_flags = if_getflags(ifp);
4160 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4162 IFDI_INTR_DISABLE(ctx);
4163 IFDI_MULTI_SET(ctx);
4164 IFDI_INTR_ENABLE(ctx);
4170 IFDI_MEDIA_SET(ctx);
4175 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4179 struct ifi2creq i2c;
4181 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4184 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4188 if (i2c.len > sizeof(i2c.data)) {
4193 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4194 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4200 int mask, setmask, oldmask;
4202 oldmask = if_getcapenable(ifp);
4203 mask = ifr->ifr_reqcap ^ oldmask;
4204 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4207 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4209 setmask |= (mask & IFCAP_FLAGS);
4210 setmask |= (mask & IFCAP_WOL);
4213 * If any RX csum has changed, change all the ones that
4214 * are supported by the driver.
4216 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4217 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4218 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4222 * want to ensure that traffic has stopped before we change any of the flags
4226 bits = if_getdrvflags(ifp);
4227 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4230 if_togglecapenable(ifp, setmask);
4232 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4233 iflib_init_locked(ctx);
4235 if_setdrvflags(ifp, bits);
4242 case SIOCGPRIVATE_0:
4246 err = IFDI_PRIV_IOCTL(ctx, command, data);
4250 err = ether_ioctl(ifp, command, data);
4259 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4261 if_ctx_t ctx = if_getsoftc(ifp);
4263 return (IFDI_GET_COUNTER(ctx, cnt));
4266 /*********************************************************************
4268 * OTHER FUNCTIONS EXPORTED TO THE STACK
4270 **********************************************************************/
4273 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4275 if_ctx_t ctx = if_getsoftc(ifp);
4277 if ((void *)ctx != arg)
4280 if ((vtag == 0) || (vtag > 4095))
4283 if (iflib_in_detach(ctx))
4287 IFDI_VLAN_REGISTER(ctx, vtag);
4288 /* Re-init to load the changes */
4289 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4290 iflib_if_init_locked(ctx);
4295 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4297 if_ctx_t ctx = if_getsoftc(ifp);
4299 if ((void *)ctx != arg)
4302 if ((vtag == 0) || (vtag > 4095))
4306 IFDI_VLAN_UNREGISTER(ctx, vtag);
4307 /* Re-init to load the changes */
4308 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4309 iflib_if_init_locked(ctx);
4314 iflib_led_func(void *arg, int onoff)
4319 IFDI_LED_FUNC(ctx, onoff);
4323 /*********************************************************************
4325 * BUS FUNCTION DEFINITIONS
4327 **********************************************************************/
4330 iflib_device_probe(device_t dev)
4332 const pci_vendor_info_t *ent;
4333 if_shared_ctx_t sctx;
4334 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4335 uint16_t pci_vendor_id;
4337 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4340 pci_vendor_id = pci_get_vendor(dev);
4341 pci_device_id = pci_get_device(dev);
4342 pci_subvendor_id = pci_get_subvendor(dev);
4343 pci_subdevice_id = pci_get_subdevice(dev);
4344 pci_rev_id = pci_get_revid(dev);
4345 if (sctx->isc_parse_devinfo != NULL)
4346 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4348 ent = sctx->isc_vendor_info;
4349 while (ent->pvi_vendor_id != 0) {
4350 if (pci_vendor_id != ent->pvi_vendor_id) {
4354 if ((pci_device_id == ent->pvi_device_id) &&
4355 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4356 (ent->pvi_subvendor_id == 0)) &&
4357 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4358 (ent->pvi_subdevice_id == 0)) &&
4359 ((pci_rev_id == ent->pvi_rev_id) ||
4360 (ent->pvi_rev_id == 0))) {
4362 device_set_desc_copy(dev, ent->pvi_name);
4363 /* this needs to be changed to zero if the bus probing code
4364 * ever stops re-probing on best match because the sctx
4365 * may have its values over written by register calls
4366 * in subsequent probes
4368 return (BUS_PROBE_DEFAULT);
4376 iflib_device_probe_vendor(device_t dev)
4380 probe = iflib_device_probe(dev);
4381 if (probe == BUS_PROBE_DEFAULT)
4382 return (BUS_PROBE_VENDOR);
4388 iflib_reset_qvalues(if_ctx_t ctx)
4390 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4391 if_shared_ctx_t sctx = ctx->ifc_sctx;
4392 device_t dev = ctx->ifc_dev;
4395 if (ctx->ifc_sysctl_ntxqs != 0)
4396 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4397 if (ctx->ifc_sysctl_nrxqs != 0)
4398 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4400 for (i = 0; i < sctx->isc_ntxqs; i++) {
4401 if (ctx->ifc_sysctl_ntxds[i] != 0)
4402 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4404 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4407 for (i = 0; i < sctx->isc_nrxqs; i++) {
4408 if (ctx->ifc_sysctl_nrxds[i] != 0)
4409 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4411 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4414 for (i = 0; i < sctx->isc_nrxqs; i++) {
4415 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4416 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4417 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4418 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4420 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4421 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4422 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4423 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4425 if (!powerof2(scctx->isc_nrxd[i])) {
4426 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4427 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4428 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4432 for (i = 0; i < sctx->isc_ntxqs; i++) {
4433 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4434 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4435 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4436 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4438 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4439 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4440 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4441 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4443 if (!powerof2(scctx->isc_ntxd[i])) {
4444 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4445 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4446 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4452 iflib_add_pfil(if_ctx_t ctx)
4454 struct pfil_head *pfil;
4455 struct pfil_head_args pa;
4459 pa.pa_version = PFIL_VERSION;
4460 pa.pa_flags = PFIL_IN;
4461 pa.pa_type = PFIL_TYPE_ETHERNET;
4462 pa.pa_headname = ctx->ifc_ifp->if_xname;
4463 pfil = pfil_head_register(&pa);
4465 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4471 iflib_rem_pfil(if_ctx_t ctx)
4473 struct pfil_head *pfil;
4477 rxq = ctx->ifc_rxqs;
4479 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4482 pfil_head_unregister(pfil);
4486 get_ctx_core_offset(if_ctx_t ctx)
4488 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4489 struct cpu_offset *op;
4491 uint16_t ret = ctx->ifc_sysctl_core_offset;
4493 if (ret != CORE_OFFSET_UNSPECIFIED)
4496 if (ctx->ifc_sysctl_separate_txrx)
4497 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4499 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4501 mtx_lock(&cpu_offset_mtx);
4502 SLIST_FOREACH(op, &cpu_offsets, entries) {
4503 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4506 MPASS(op->refcount < UINT_MAX);
4511 if (ret == CORE_OFFSET_UNSPECIFIED) {
4513 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4516 device_printf(ctx->ifc_dev,
4517 "allocation for cpu offset failed.\n");
4521 CPU_COPY(&ctx->ifc_cpus, &op->set);
4522 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4525 mtx_unlock(&cpu_offset_mtx);
4531 unref_ctx_core_offset(if_ctx_t ctx)
4533 struct cpu_offset *op, *top;
4535 mtx_lock(&cpu_offset_mtx);
4536 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4537 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4538 MPASS(op->refcount > 0);
4540 if (op->refcount == 0) {
4541 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4547 mtx_unlock(&cpu_offset_mtx);
4551 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4555 if_softc_ctx_t scctx;
4556 kobjop_desc_t kobj_desc;
4557 kobj_method_t *kobj_method;
4559 uint16_t main_rxq, main_txq;
4561 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4564 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4565 device_set_softc(dev, ctx);
4566 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4569 ctx->ifc_sctx = sctx;
4571 ctx->ifc_softc = sc;
4573 if ((err = iflib_register(ctx)) != 0) {
4574 device_printf(dev, "iflib_register failed %d\n", err);
4577 iflib_add_device_sysctl_pre(ctx);
4579 scctx = &ctx->ifc_softc_ctx;
4582 iflib_reset_qvalues(ctx);
4584 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4585 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4588 _iflib_pre_assert(scctx);
4589 ctx->ifc_txrx = *scctx->isc_txrx;
4591 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4592 ctx->ifc_mediap = scctx->isc_media;
4595 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4596 MPASS(scctx->isc_tx_csum_flags);
4599 if_setcapabilities(ifp,
4600 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4601 if_setcapenable(ifp,
4602 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4604 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4605 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4606 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4607 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4609 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4610 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4612 /* XXX change for per-queue sizes */
4613 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4614 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4616 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4617 MAX_SINGLE_PACKET_FRACTION)
4618 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4619 MAX_SINGLE_PACKET_FRACTION);
4620 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4621 MAX_SINGLE_PACKET_FRACTION)
4622 scctx->isc_tx_tso_segments_max = max(1,
4623 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4625 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4626 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4628 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4631 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4634 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4635 * into account. In the worst case, each of these calls will
4636 * add another mbuf and, thus, the requirement for another DMA
4637 * segment. So for best performance, it doesn't make sense to
4638 * advertize a maximum of TSO segments that typically will
4639 * require defragmentation in iflib_encap().
4641 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4642 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4644 if (scctx->isc_rss_table_size == 0)
4645 scctx->isc_rss_table_size = 64;
4646 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4648 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4649 /* XXX format name */
4650 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4651 NULL, NULL, "admin");
4653 /* Set up cpu set. If it fails, use the set of all CPUs. */
4654 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4655 device_printf(dev, "Unable to fetch CPU list\n");
4656 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4658 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4661 ** Now set up MSI or MSI-X, should return us the number of supported
4662 ** vectors (will be 1 for a legacy interrupt and MSI).
4664 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4665 msix = scctx->isc_vectors;
4666 } else if (scctx->isc_msix_bar != 0)
4668 * The simple fact that isc_msix_bar is not 0 does not mean we
4669 * we have a good value there that is known to work.
4671 msix = iflib_msix_init(ctx);
4673 scctx->isc_vectors = 1;
4674 scctx->isc_ntxqsets = 1;
4675 scctx->isc_nrxqsets = 1;
4676 scctx->isc_intr = IFLIB_INTR_LEGACY;
4679 /* Get memory for the station queues */
4680 if ((err = iflib_queues_alloc(ctx))) {
4681 device_printf(dev, "Unable to allocate queue memory\n");
4682 goto fail_intr_free;
4685 if ((err = iflib_qset_structures_setup(ctx)))
4689 * Now that we know how many queues there are, get the core offset.
4691 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4694 * Group taskqueues aren't properly set up until SMP is started,
4695 * so we disable interrupts until we can handle them post
4698 * XXX: disabling interrupts doesn't actually work, at least for
4699 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4700 * we do null handling and depend on this not causing too large an
4703 IFDI_INTR_DISABLE(ctx);
4707 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4708 * aren't the default NULL implementation.
4710 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4711 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4713 if (kobj_method == &kobj_desc->deflt) {
4715 "MSI-X requires ifdi_rx_queue_intr_enable method");
4719 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4720 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4722 if (kobj_method == &kobj_desc->deflt) {
4724 "MSI-X requires ifdi_tx_queue_intr_enable method");
4730 * Assign the MSI-X vectors.
4731 * Note that the default NULL ifdi_msix_intr_assign method will
4734 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4736 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4740 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4742 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4746 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4747 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4752 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4754 goto fail_intr_free;
4757 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4759 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4760 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4765 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4766 * This must appear after the call to ether_ifattach() because
4767 * ether_ifattach() sets if_hdrlen to the default value.
4769 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4770 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4772 if ((err = iflib_netmap_attach(ctx))) {
4773 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4778 NETDUMP_SET(ctx->ifc_ifp, iflib);
4780 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4781 iflib_add_device_sysctl_post(ctx);
4782 iflib_add_pfil(ctx);
4783 ctx->ifc_flags |= IFC_INIT_DONE;
4789 ether_ifdetach(ctx->ifc_ifp);
4791 iflib_free_intr_mem(ctx);
4793 iflib_tx_structures_free(ctx);
4794 iflib_rx_structures_free(ctx);
4795 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4799 iflib_deregister(ctx);
4801 device_set_softc(ctx->ifc_dev, NULL);
4802 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4803 free(ctx->ifc_softc, M_IFLIB);
4809 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4810 struct iflib_cloneattach_ctx *clctx)
4815 if_softc_ctx_t scctx;
4821 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4822 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4823 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4824 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4825 ctx->ifc_flags |= IFC_PSEUDO;
4827 ctx->ifc_sctx = sctx;
4828 ctx->ifc_softc = sc;
4831 if ((err = iflib_register(ctx)) != 0) {
4832 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4835 iflib_add_device_sysctl_pre(ctx);
4837 scctx = &ctx->ifc_softc_ctx;
4840 iflib_reset_qvalues(ctx);
4842 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4843 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4846 if (sctx->isc_flags & IFLIB_GEN_MAC)
4847 ether_gen_addr(ifp, &ctx->ifc_mac);
4848 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4849 clctx->cc_params)) != 0) {
4850 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4853 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4854 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4855 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4858 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4859 MPASS(scctx->isc_tx_csum_flags);
4862 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4863 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4865 ifp->if_flags |= IFF_NOGROUP;
4866 if (sctx->isc_flags & IFLIB_PSEUDO) {
4867 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4869 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4870 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4876 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4877 * This must appear after the call to ether_ifattach() because
4878 * ether_ifattach() sets if_hdrlen to the default value.
4880 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4881 if_setifheaderlen(ifp,
4882 sizeof(struct ether_vlan_header));
4884 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4885 iflib_add_device_sysctl_post(ctx);
4886 ctx->ifc_flags |= IFC_INIT_DONE;
4889 _iflib_pre_assert(scctx);
4890 ctx->ifc_txrx = *scctx->isc_txrx;
4892 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4893 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4894 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4895 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4897 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4898 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4900 /* XXX change for per-queue sizes */
4901 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4902 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4904 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4905 MAX_SINGLE_PACKET_FRACTION)
4906 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4907 MAX_SINGLE_PACKET_FRACTION);
4908 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4909 MAX_SINGLE_PACKET_FRACTION)
4910 scctx->isc_tx_tso_segments_max = max(1,
4911 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4913 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4914 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4916 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4919 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4922 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4923 * into account. In the worst case, each of these calls will
4924 * add another mbuf and, thus, the requirement for another DMA
4925 * segment. So for best performance, it doesn't make sense to
4926 * advertize a maximum of TSO segments that typically will
4927 * require defragmentation in iflib_encap().
4929 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4930 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4932 if (scctx->isc_rss_table_size == 0)
4933 scctx->isc_rss_table_size = 64;
4934 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4936 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4937 /* XXX format name */
4938 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4939 NULL, NULL, "admin");
4941 /* XXX --- can support > 1 -- but keep it simple for now */
4942 scctx->isc_intr = IFLIB_INTR_LEGACY;
4944 /* Get memory for the station queues */
4945 if ((err = iflib_queues_alloc(ctx))) {
4946 device_printf(dev, "Unable to allocate queue memory\n");
4947 goto fail_iflib_detach;
4950 if ((err = iflib_qset_structures_setup(ctx))) {
4951 device_printf(dev, "qset structure setup failed %d\n", err);
4956 * XXX What if anything do we want to do about interrupts?
4958 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4959 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4960 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4965 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4966 * This must appear after the call to ether_ifattach() because
4967 * ether_ifattach() sets if_hdrlen to the default value.
4969 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4970 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4972 /* XXX handle more than one queue */
4973 for (i = 0; i < scctx->isc_nrxqsets; i++)
4974 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4978 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4979 iflib_add_device_sysctl_post(ctx);
4980 ctx->ifc_flags |= IFC_INIT_DONE;
4985 ether_ifdetach(ctx->ifc_ifp);
4987 iflib_tx_structures_free(ctx);
4988 iflib_rx_structures_free(ctx);
4993 iflib_deregister(ctx);
4995 free(ctx->ifc_softc, M_IFLIB);
5001 iflib_pseudo_deregister(if_ctx_t ctx)
5003 if_t ifp = ctx->ifc_ifp;
5007 struct taskqgroup *tqg;
5010 ether_ifdetach(ifp);
5011 /* XXX drain any dependent tasks */
5012 tqg = qgroup_if_io_tqg;
5013 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5014 callout_drain(&txq->ift_timer);
5015 if (txq->ift_task.gt_uniq != NULL)
5016 taskqgroup_detach(tqg, &txq->ift_task);
5018 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5019 if (rxq->ifr_task.gt_uniq != NULL)
5020 taskqgroup_detach(tqg, &rxq->ifr_task);
5022 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5023 free(fl->ifl_rx_bitmap, M_IFLIB);
5025 tqg = qgroup_if_config_tqg;
5026 if (ctx->ifc_admin_task.gt_uniq != NULL)
5027 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5028 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5029 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5031 iflib_tx_structures_free(ctx);
5032 iflib_rx_structures_free(ctx);
5034 iflib_deregister(ctx);
5036 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5037 free(ctx->ifc_softc, M_IFLIB);
5043 iflib_device_attach(device_t dev)
5046 if_shared_ctx_t sctx;
5048 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5051 pci_enable_busmaster(dev);
5053 return (iflib_device_register(dev, NULL, sctx, &ctx));
5057 iflib_device_deregister(if_ctx_t ctx)
5059 if_t ifp = ctx->ifc_ifp;
5062 device_t dev = ctx->ifc_dev;
5064 struct taskqgroup *tqg;
5067 /* Make sure VLANS are not using driver */
5068 if (if_vlantrunkinuse(ifp)) {
5069 device_printf(dev, "Vlan in use, detach first\n");
5073 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5074 device_printf(dev, "SR-IOV in use; detach first.\n");
5080 ctx->ifc_flags |= IFC_IN_DETACH;
5087 iflib_netmap_detach(ifp);
5088 ether_ifdetach(ifp);
5089 iflib_rem_pfil(ctx);
5090 if (ctx->ifc_led_dev != NULL)
5091 led_destroy(ctx->ifc_led_dev);
5092 /* XXX drain any dependent tasks */
5093 tqg = qgroup_if_io_tqg;
5094 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5095 callout_drain(&txq->ift_timer);
5096 if (txq->ift_task.gt_uniq != NULL)
5097 taskqgroup_detach(tqg, &txq->ift_task);
5099 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5100 if (rxq->ifr_task.gt_uniq != NULL)
5101 taskqgroup_detach(tqg, &rxq->ifr_task);
5103 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5104 free(fl->ifl_rx_bitmap, M_IFLIB);
5106 tqg = qgroup_if_config_tqg;
5107 if (ctx->ifc_admin_task.gt_uniq != NULL)
5108 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5109 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5110 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5115 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5116 iflib_free_intr_mem(ctx);
5118 bus_generic_detach(dev);
5120 iflib_tx_structures_free(ctx);
5121 iflib_rx_structures_free(ctx);
5123 iflib_deregister(ctx);
5125 device_set_softc(ctx->ifc_dev, NULL);
5126 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5127 free(ctx->ifc_softc, M_IFLIB);
5128 unref_ctx_core_offset(ctx);
5134 iflib_free_intr_mem(if_ctx_t ctx)
5137 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5138 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5140 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5141 pci_release_msi(ctx->ifc_dev);
5143 if (ctx->ifc_msix_mem != NULL) {
5144 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5145 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5146 ctx->ifc_msix_mem = NULL;
5151 iflib_device_detach(device_t dev)
5153 if_ctx_t ctx = device_get_softc(dev);
5155 return (iflib_device_deregister(ctx));
5159 iflib_device_suspend(device_t dev)
5161 if_ctx_t ctx = device_get_softc(dev);
5167 return bus_generic_suspend(dev);
5170 iflib_device_shutdown(device_t dev)
5172 if_ctx_t ctx = device_get_softc(dev);
5178 return bus_generic_suspend(dev);
5183 iflib_device_resume(device_t dev)
5185 if_ctx_t ctx = device_get_softc(dev);
5186 iflib_txq_t txq = ctx->ifc_txqs;
5190 iflib_if_init_locked(ctx);
5192 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5193 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5195 return (bus_generic_resume(dev));
5199 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5202 if_ctx_t ctx = device_get_softc(dev);
5205 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5212 iflib_device_iov_uninit(device_t dev)
5214 if_ctx_t ctx = device_get_softc(dev);
5217 IFDI_IOV_UNINIT(ctx);
5222 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5225 if_ctx_t ctx = device_get_softc(dev);
5228 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5234 /*********************************************************************
5236 * MODULE FUNCTION DEFINITIONS
5238 **********************************************************************/
5241 * - Start a fast taskqueue thread for each core
5242 * - Start a taskqueue for control operations
5245 iflib_module_init(void)
5251 iflib_module_event_handler(module_t mod, int what, void *arg)
5257 if ((err = iflib_module_init()) != 0)
5263 return (EOPNOTSUPP);
5269 /*********************************************************************
5271 * PUBLIC FUNCTION DEFINITIONS
5272 * ordered as in iflib.h
5274 **********************************************************************/
5278 _iflib_assert(if_shared_ctx_t sctx)
5282 MPASS(sctx->isc_tx_maxsize);
5283 MPASS(sctx->isc_tx_maxsegsize);
5285 MPASS(sctx->isc_rx_maxsize);
5286 MPASS(sctx->isc_rx_nsegments);
5287 MPASS(sctx->isc_rx_maxsegsize);
5289 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5290 for (i = 0; i < sctx->isc_nrxqs; i++) {
5291 MPASS(sctx->isc_nrxd_min[i]);
5292 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5293 MPASS(sctx->isc_nrxd_max[i]);
5294 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5295 MPASS(sctx->isc_nrxd_default[i]);
5296 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5299 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5300 for (i = 0; i < sctx->isc_ntxqs; i++) {
5301 MPASS(sctx->isc_ntxd_min[i]);
5302 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5303 MPASS(sctx->isc_ntxd_max[i]);
5304 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5305 MPASS(sctx->isc_ntxd_default[i]);
5306 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5311 _iflib_pre_assert(if_softc_ctx_t scctx)
5314 MPASS(scctx->isc_txrx->ift_txd_encap);
5315 MPASS(scctx->isc_txrx->ift_txd_flush);
5316 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5317 MPASS(scctx->isc_txrx->ift_rxd_available);
5318 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5319 MPASS(scctx->isc_txrx->ift_rxd_refill);
5320 MPASS(scctx->isc_txrx->ift_rxd_flush);
5324 iflib_register(if_ctx_t ctx)
5326 if_shared_ctx_t sctx = ctx->ifc_sctx;
5327 driver_t *driver = sctx->isc_driver;
5328 device_t dev = ctx->ifc_dev;
5331 _iflib_assert(sctx);
5334 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5335 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5337 device_printf(dev, "can not allocate ifnet structure\n");
5342 * Initialize our context's device specific methods
5344 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5345 kobj_class_compile((kobj_class_t) driver);
5347 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5348 if_setsoftc(ifp, ctx);
5349 if_setdev(ifp, dev);
5350 if_setinitfn(ifp, iflib_if_init);
5351 if_setioctlfn(ifp, iflib_if_ioctl);
5353 if_setstartfn(ifp, iflib_altq_if_start);
5354 if_settransmitfn(ifp, iflib_altq_if_transmit);
5355 if_setsendqready(ifp);
5357 if_settransmitfn(ifp, iflib_if_transmit);
5359 if_setqflushfn(ifp, iflib_if_qflush);
5360 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5362 ctx->ifc_vlan_attach_event =
5363 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5364 EVENTHANDLER_PRI_FIRST);
5365 ctx->ifc_vlan_detach_event =
5366 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5367 EVENTHANDLER_PRI_FIRST);
5369 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5370 ctx->ifc_mediap = &ctx->ifc_media;
5371 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5372 iflib_media_change, iflib_media_status);
5378 iflib_deregister(if_ctx_t ctx)
5380 if_t ifp = ctx->ifc_ifp;
5382 /* Remove all media */
5383 ifmedia_removeall(&ctx->ifc_media);
5385 /* Unregister VLAN events */
5386 if (ctx->ifc_vlan_attach_event != NULL) {
5387 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5388 ctx->ifc_vlan_attach_event = NULL;
5390 if (ctx->ifc_vlan_detach_event != NULL) {
5391 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5392 ctx->ifc_vlan_detach_event = NULL;
5395 /* Release kobject reference */
5396 kobj_delete((kobj_t) ctx, NULL);
5398 /* Free the ifnet structure */
5401 STATE_LOCK_DESTROY(ctx);
5403 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5404 CTX_LOCK_DESTROY(ctx);
5408 iflib_queues_alloc(if_ctx_t ctx)
5410 if_shared_ctx_t sctx = ctx->ifc_sctx;
5411 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5412 device_t dev = ctx->ifc_dev;
5413 int nrxqsets = scctx->isc_nrxqsets;
5414 int ntxqsets = scctx->isc_ntxqsets;
5417 iflib_fl_t fl = NULL;
5418 int i, j, cpu, err, txconf, rxconf;
5419 iflib_dma_info_t ifdip;
5420 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5421 uint32_t *txqsizes = scctx->isc_txqsizes;
5422 uint8_t nrxqs = sctx->isc_nrxqs;
5423 uint8_t ntxqs = sctx->isc_ntxqs;
5424 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5428 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5429 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5431 /* Allocate the TX ring struct memory */
5432 if (!(ctx->ifc_txqs =
5433 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5434 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5435 device_printf(dev, "Unable to allocate TX ring memory\n");
5440 /* Now allocate the RX */
5441 if (!(ctx->ifc_rxqs =
5442 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5443 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5444 device_printf(dev, "Unable to allocate RX ring memory\n");
5449 txq = ctx->ifc_txqs;
5450 rxq = ctx->ifc_rxqs;
5453 * XXX handle allocation failure
5455 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5456 /* Set up some basics */
5458 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5459 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5461 "Unable to allocate TX DMA info memory\n");
5465 txq->ift_ifdi = ifdip;
5466 for (j = 0; j < ntxqs; j++, ifdip++) {
5467 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5469 "Unable to allocate TX descriptors\n");
5473 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5474 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5478 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5479 txq->ift_br_offset = 1;
5481 txq->ift_br_offset = 0;
5484 txq->ift_timer.c_cpu = cpu;
5486 if (iflib_txsd_alloc(txq)) {
5487 device_printf(dev, "Critical Failure setting up TX buffers\n");
5492 /* Initialize the TX lock */
5493 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5494 device_get_nameunit(dev), txq->ift_id);
5495 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5496 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5498 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5499 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5501 /* XXX free any allocated rings */
5502 device_printf(dev, "Unable to allocate buf_ring\n");
5507 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5508 /* Set up some basics */
5510 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5511 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5513 "Unable to allocate RX DMA info memory\n");
5518 rxq->ifr_ifdi = ifdip;
5519 /* XXX this needs to be changed if #rx queues != #tx queues */
5520 rxq->ifr_ntxqirq = 1;
5521 rxq->ifr_txqid[0] = i;
5522 for (j = 0; j < nrxqs; j++, ifdip++) {
5523 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5525 "Unable to allocate RX descriptors\n");
5529 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5533 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5534 rxq->ifr_fl_offset = 1;
5536 rxq->ifr_fl_offset = 0;
5538 rxq->ifr_nfl = nfree_lists;
5540 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5541 device_printf(dev, "Unable to allocate free list memory\n");
5546 for (j = 0; j < nfree_lists; j++) {
5547 fl[j].ifl_rxq = rxq;
5549 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5550 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5552 /* Allocate receive buffers for the ring */
5553 if (iflib_rxsd_alloc(rxq)) {
5555 "Critical Failure setting up receive buffers\n");
5560 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5561 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5566 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5567 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5568 for (i = 0; i < ntxqsets; i++) {
5569 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5571 for (j = 0; j < ntxqs; j++, di++) {
5572 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5573 paddrs[i*ntxqs + j] = di->idi_paddr;
5576 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5577 device_printf(ctx->ifc_dev,
5578 "Unable to allocate device TX queue\n");
5579 iflib_tx_structures_free(ctx);
5580 free(vaddrs, M_IFLIB);
5581 free(paddrs, M_IFLIB);
5584 free(vaddrs, M_IFLIB);
5585 free(paddrs, M_IFLIB);
5588 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5589 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5590 for (i = 0; i < nrxqsets; i++) {
5591 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5593 for (j = 0; j < nrxqs; j++, di++) {
5594 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5595 paddrs[i*nrxqs + j] = di->idi_paddr;
5598 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5599 device_printf(ctx->ifc_dev,
5600 "Unable to allocate device RX queue\n");
5601 iflib_tx_structures_free(ctx);
5602 free(vaddrs, M_IFLIB);
5603 free(paddrs, M_IFLIB);
5606 free(vaddrs, M_IFLIB);
5607 free(paddrs, M_IFLIB);
5611 /* XXX handle allocation failure changes */
5615 if (ctx->ifc_rxqs != NULL)
5616 free(ctx->ifc_rxqs, M_IFLIB);
5617 ctx->ifc_rxqs = NULL;
5618 if (ctx->ifc_txqs != NULL)
5619 free(ctx->ifc_txqs, M_IFLIB);
5620 ctx->ifc_txqs = NULL;
5626 iflib_tx_structures_setup(if_ctx_t ctx)
5628 iflib_txq_t txq = ctx->ifc_txqs;
5631 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5632 iflib_txq_setup(txq);
5638 iflib_tx_structures_free(if_ctx_t ctx)
5640 iflib_txq_t txq = ctx->ifc_txqs;
5641 if_shared_ctx_t sctx = ctx->ifc_sctx;
5644 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5645 iflib_txq_destroy(txq);
5646 for (j = 0; j < sctx->isc_ntxqs; j++)
5647 iflib_dma_free(&txq->ift_ifdi[j]);
5649 free(ctx->ifc_txqs, M_IFLIB);
5650 ctx->ifc_txqs = NULL;
5651 IFDI_QUEUES_FREE(ctx);
5654 /*********************************************************************
5656 * Initialize all receive rings.
5658 **********************************************************************/
5660 iflib_rx_structures_setup(if_ctx_t ctx)
5662 iflib_rxq_t rxq = ctx->ifc_rxqs;
5664 #if defined(INET6) || defined(INET)
5668 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5669 #if defined(INET6) || defined(INET)
5670 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5671 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5672 TCP_LRO_ENTRIES, min(1024,
5673 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5675 device_printf(ctx->ifc_dev,
5676 "LRO Initialization failed!\n");
5681 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5684 #if defined(INET6) || defined(INET)
5687 * Free LRO resources allocated so far, we will only handle
5688 * the rings that completed, the failing case will have
5689 * cleaned up for itself. 'q' failed, so its the terminus.
5691 rxq = ctx->ifc_rxqs;
5692 for (i = 0; i < q; ++i, rxq++) {
5693 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5694 tcp_lro_free(&rxq->ifr_lc);
5700 /*********************************************************************
5702 * Free all receive rings.
5704 **********************************************************************/
5706 iflib_rx_structures_free(if_ctx_t ctx)
5708 iflib_rxq_t rxq = ctx->ifc_rxqs;
5711 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5712 iflib_rx_sds_free(rxq);
5713 #if defined(INET6) || defined(INET)
5714 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5715 tcp_lro_free(&rxq->ifr_lc);
5718 free(ctx->ifc_rxqs, M_IFLIB);
5719 ctx->ifc_rxqs = NULL;
5723 iflib_qset_structures_setup(if_ctx_t ctx)
5728 * It is expected that the caller takes care of freeing queues if this
5731 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5732 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5736 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5737 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5743 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5744 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5747 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5752 find_nth(if_ctx_t ctx, int qid)
5755 int i, cpuid, eqid, count;
5757 CPU_COPY(&ctx->ifc_cpus, &cpus);
5758 count = CPU_COUNT(&cpus);
5760 /* clear up to the qid'th bit */
5761 for (i = 0; i < eqid; i++) {
5762 cpuid = CPU_FFS(&cpus);
5764 CPU_CLR(cpuid-1, &cpus);
5766 cpuid = CPU_FFS(&cpus);
5772 extern struct cpu_group *cpu_top; /* CPU topology */
5775 find_child_with_core(int cpu, struct cpu_group *grp)
5779 if (grp->cg_children == 0)
5782 MPASS(grp->cg_child);
5783 for (i = 0; i < grp->cg_children; i++) {
5784 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5792 * Find the nth "close" core to the specified core
5793 * "close" is defined as the deepest level that shares
5794 * at least an L2 cache. With threads, this will be
5795 * threads on the same core. If the shared cache is L3
5796 * or higher, simply returns the same core.
5799 find_close_core(int cpu, int core_offset)
5801 struct cpu_group *grp;
5810 while ((i = find_child_with_core(cpu, grp)) != -1) {
5811 /* If the child only has one cpu, don't descend */
5812 if (grp->cg_child[i].cg_count <= 1)
5814 grp = &grp->cg_child[i];
5817 /* If they don't share at least an L2 cache, use the same CPU */
5818 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5822 CPU_COPY(&grp->cg_mask, &cs);
5824 /* Add the selected CPU offset to core offset. */
5825 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5826 if (fcpu - 1 == cpu)
5828 CPU_CLR(fcpu - 1, &cs);
5834 CPU_COPY(&grp->cg_mask, &cs);
5835 for (i = core_offset % grp->cg_count; i > 0; i--) {
5836 MPASS(CPU_FFS(&cs));
5837 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5839 MPASS(CPU_FFS(&cs));
5840 return CPU_FFS(&cs) - 1;
5844 find_close_core(int cpu, int core_offset __unused)
5851 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5855 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5856 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5857 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5859 case IFLIB_INTR_RXTX:
5860 /* RX queues get the specified core */
5861 return qid / CPU_COUNT(&ctx->ifc_cpus);
5867 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5868 #define find_close_core(cpuid, tid) CPU_FIRST()
5869 #define find_nth(ctx, gid) CPU_FIRST()
5872 /* Just to avoid copy/paste */
5874 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5875 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5879 int co, cpuid, err, tid;
5882 co = ctx->ifc_sysctl_core_offset;
5883 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5884 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5885 cpuid = find_nth(ctx, qid + co);
5886 tid = get_core_offset(ctx, type, qid);
5888 device_printf(dev, "get_core_offset failed\n");
5889 return (EOPNOTSUPP);
5891 cpuid = find_close_core(cpuid, tid);
5892 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5895 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5899 if (cpuid > ctx->ifc_cpuid_highest)
5900 ctx->ifc_cpuid_highest = cpuid;
5906 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5907 iflib_intr_type_t type, driver_filter_t *filter,
5908 void *filter_arg, int qid, const char *name)
5911 struct grouptask *gtask;
5912 struct taskqgroup *tqg;
5913 iflib_filter_info_t info;
5916 driver_filter_t *intr_fast;
5919 info = &ctx->ifc_filter_info;
5923 /* XXX merge tx/rx for netmap? */
5925 q = &ctx->ifc_txqs[qid];
5926 info = &ctx->ifc_txqs[qid].ift_filter_info;
5927 gtask = &ctx->ifc_txqs[qid].ift_task;
5928 tqg = qgroup_if_io_tqg;
5930 intr_fast = iflib_fast_intr;
5931 GROUPTASK_INIT(gtask, 0, fn, q);
5932 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5935 q = &ctx->ifc_rxqs[qid];
5936 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5937 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5938 tqg = qgroup_if_io_tqg;
5940 intr_fast = iflib_fast_intr;
5941 GROUPTASK_INIT(gtask, 0, fn, q);
5943 case IFLIB_INTR_RXTX:
5944 q = &ctx->ifc_rxqs[qid];
5945 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5946 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5947 tqg = qgroup_if_io_tqg;
5949 intr_fast = iflib_fast_intr_rxtx;
5950 GROUPTASK_INIT(gtask, 0, fn, q);
5952 case IFLIB_INTR_ADMIN:
5955 info = &ctx->ifc_filter_info;
5956 gtask = &ctx->ifc_admin_task;
5957 tqg = qgroup_if_config_tqg;
5958 fn = _task_fn_admin;
5959 intr_fast = iflib_fast_intr_ctx;
5962 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5967 info->ifi_filter = filter;
5968 info->ifi_filter_arg = filter_arg;
5969 info->ifi_task = gtask;
5973 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5975 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5978 if (type == IFLIB_INTR_ADMIN)
5982 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5987 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
5994 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5996 struct grouptask *gtask;
5997 struct taskqgroup *tqg;
6004 q = &ctx->ifc_txqs[qid];
6005 gtask = &ctx->ifc_txqs[qid].ift_task;
6006 tqg = qgroup_if_io_tqg;
6010 q = &ctx->ifc_rxqs[qid];
6011 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6012 tqg = qgroup_if_io_tqg;
6015 case IFLIB_INTR_IOV:
6017 gtask = &ctx->ifc_vflr_task;
6018 tqg = qgroup_if_config_tqg;
6022 panic("unknown net intr type");
6024 GROUPTASK_INIT(gtask, 0, fn, q);
6026 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6029 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6032 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6037 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6041 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6044 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6045 rman_get_rid(irq->ii_res), irq->ii_res);
6049 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6051 iflib_txq_t txq = ctx->ifc_txqs;
6052 iflib_rxq_t rxq = ctx->ifc_rxqs;
6053 if_irq_t irq = &ctx->ifc_legacy_irq;
6054 iflib_filter_info_t info;
6056 struct grouptask *gtask;
6057 struct resource *res;
6058 struct taskqgroup *tqg;
6064 q = &ctx->ifc_rxqs[0];
6065 info = &rxq[0].ifr_filter_info;
6066 gtask = &rxq[0].ifr_task;
6067 tqg = qgroup_if_io_tqg;
6070 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6072 ctx->ifc_flags |= IFC_LEGACY;
6073 info->ifi_filter = filter;
6074 info->ifi_filter_arg = filter_arg;
6075 info->ifi_task = gtask;
6076 info->ifi_ctx = rx_only ? ctx : q;
6079 /* We allocate a single interrupt resource */
6080 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6081 iflib_fast_intr_rxtx, NULL, info, name);
6084 GROUPTASK_INIT(gtask, 0, fn, q);
6086 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6088 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6089 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6095 iflib_led_create(if_ctx_t ctx)
6098 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6099 device_get_nameunit(ctx->ifc_dev));
6103 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6106 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6110 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6113 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6117 iflib_admin_intr_deferred(if_ctx_t ctx)
6120 struct grouptask *gtask;
6122 gtask = &ctx->ifc_admin_task;
6123 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6126 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6130 iflib_iov_intr_deferred(if_ctx_t ctx)
6133 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6137 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6140 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6145 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6149 GROUPTASK_INIT(gtask, 0, fn, ctx);
6150 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6155 iflib_config_gtask_deinit(struct grouptask *gtask)
6158 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6162 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6164 if_t ifp = ctx->ifc_ifp;
6165 iflib_txq_t txq = ctx->ifc_txqs;
6167 if_setbaudrate(ifp, baudrate);
6168 if (baudrate >= IF_Gbps(10)) {
6170 ctx->ifc_flags |= IFC_PREFETCH;
6173 /* If link down, disable watchdog */
6174 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6175 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6176 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6178 ctx->ifc_link_state = link_state;
6179 if_link_state_change(ifp, link_state);
6183 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6187 int credits_pre = txq->ift_cidx_processed;
6190 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6191 BUS_DMASYNC_POSTREAD);
6192 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6195 txq->ift_processed += credits;
6196 txq->ift_cidx_processed += credits;
6198 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6199 if (txq->ift_cidx_processed >= txq->ift_size)
6200 txq->ift_cidx_processed -= txq->ift_size;
6205 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6210 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6211 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6212 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6213 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6218 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6219 const char *description, if_int_delay_info_t info,
6220 int offset, int value)
6222 info->iidi_ctx = ctx;
6223 info->iidi_offset = offset;
6224 info->iidi_value = value;
6225 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6226 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6227 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6228 info, 0, iflib_sysctl_int_delay, "I", description);
6232 iflib_ctx_lock_get(if_ctx_t ctx)
6235 return (&ctx->ifc_ctx_sx);
6239 iflib_msix_init(if_ctx_t ctx)
6241 device_t dev = ctx->ifc_dev;
6242 if_shared_ctx_t sctx = ctx->ifc_sctx;
6243 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6244 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6245 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6247 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6248 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6251 device_printf(dev, "msix_init qsets capped at %d\n",
6252 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6254 /* Override by tuneable */
6255 if (scctx->isc_disable_msix)
6258 /* First try MSI-X */
6259 if ((msgs = pci_msix_count(dev)) == 0) {
6261 device_printf(dev, "MSI-X not supported or disabled\n");
6265 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6267 * bar == -1 => "trust me I know what I'm doing"
6268 * Some drivers are for hardware that is so shoddily
6269 * documented that no one knows which bars are which
6270 * so the developer has to map all bars. This hack
6271 * allows shoddy garbage to use MSI-X in this framework.
6274 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6275 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6276 if (ctx->ifc_msix_mem == NULL) {
6277 device_printf(dev, "Unable to map MSI-X table\n");
6282 admincnt = sctx->isc_admin_intrcnt;
6284 /* use only 1 qset in debug mode */
6285 queuemsgs = min(msgs - admincnt, 1);
6287 queuemsgs = msgs - admincnt;
6290 queues = imin(queuemsgs, rss_getnumbuckets());
6294 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6297 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6298 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6300 /* If we're doing RSS, clamp at the number of RSS buckets */
6301 if (queues > rss_getnumbuckets())
6302 queues = rss_getnumbuckets();
6304 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6305 rx_queues = iflib_num_rx_queues;
6309 if (rx_queues > scctx->isc_nrxqsets)
6310 rx_queues = scctx->isc_nrxqsets;
6313 * We want this to be all logical CPUs by default
6315 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6316 tx_queues = iflib_num_tx_queues;
6318 tx_queues = mp_ncpus;
6320 if (tx_queues > scctx->isc_ntxqsets)
6321 tx_queues = scctx->isc_ntxqsets;
6323 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6325 if (tx_queues != rx_queues)
6327 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6328 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6330 tx_queues = min(rx_queues, tx_queues);
6331 rx_queues = min(rx_queues, tx_queues);
6334 vectors = rx_queues + admincnt;
6335 if (msgs < vectors) {
6337 "insufficient number of MSI-X vectors "
6338 "(supported %d, need %d)\n", msgs, vectors);
6342 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6345 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6346 if (vectors != msgs) {
6348 "Unable to allocate sufficient MSI-X vectors "
6349 "(got %d, need %d)\n", vectors, msgs);
6350 pci_release_msi(dev);
6352 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6354 ctx->ifc_msix_mem = NULL;
6358 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6360 scctx->isc_vectors = vectors;
6361 scctx->isc_nrxqsets = rx_queues;
6362 scctx->isc_ntxqsets = tx_queues;
6363 scctx->isc_intr = IFLIB_INTR_MSIX;
6368 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6371 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6373 ctx->ifc_msix_mem = NULL;
6378 vectors = pci_msi_count(dev);
6379 scctx->isc_nrxqsets = 1;
6380 scctx->isc_ntxqsets = 1;
6381 scctx->isc_vectors = vectors;
6382 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6383 device_printf(dev,"Using an MSI interrupt\n");
6384 scctx->isc_intr = IFLIB_INTR_MSI;
6386 scctx->isc_vectors = 1;
6387 device_printf(dev,"Using a Legacy interrupt\n");
6388 scctx->isc_intr = IFLIB_INTR_LEGACY;
6394 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6397 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6400 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6402 const char *ring_state = "UNKNOWN";
6405 rc = sysctl_wire_old_buffer(req, 0);
6409 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6414 ring_state = ring_states[state[3]];
6416 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6417 state[0], state[1], state[2], ring_state);
6418 rc = sbuf_finish(sb);
6423 enum iflib_ndesc_handler {
6429 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6431 if_ctx_t ctx = (void *)arg1;
6432 enum iflib_ndesc_handler type = arg2;
6433 char buf[256] = {0};
6440 case IFLIB_NTXD_HANDLER:
6441 ndesc = ctx->ifc_sysctl_ntxds;
6443 nqs = ctx->ifc_sctx->isc_ntxqs;
6445 case IFLIB_NRXD_HANDLER:
6446 ndesc = ctx->ifc_sysctl_nrxds;
6448 nqs = ctx->ifc_sctx->isc_nrxqs;
6451 printf("%s: unhandled type\n", __func__);
6457 for (i=0; i<8; i++) {
6462 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6465 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6466 if (rc || req->newptr == NULL)
6469 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6470 i++, p = strsep(&next, " ,")) {
6471 ndesc[i] = strtoul(p, NULL, 10);
6477 #define NAME_BUFLEN 32
6479 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6481 device_t dev = iflib_get_dev(ctx);
6482 struct sysctl_oid_list *child, *oid_list;
6483 struct sysctl_ctx_list *ctx_list;
6484 struct sysctl_oid *node;
6486 ctx_list = device_get_sysctl_ctx(dev);
6487 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6488 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6489 CTLFLAG_RD, NULL, "IFLIB fields");
6490 oid_list = SYSCTL_CHILDREN(node);
6492 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6493 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6496 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6497 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6498 "# of txqs to use, 0 => use default #");
6499 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6500 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6501 "# of rxqs to use, 0 => use default #");
6502 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6503 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6504 "permit #txq != #rxq");
6505 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6506 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6507 "disable MSI-X (default 0)");
6508 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6509 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6510 "set the RX budget");
6511 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6512 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6513 "cause TX to abdicate instead of running to completion");
6514 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6515 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6516 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6517 "offset to start using cores at");
6518 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6519 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6520 "use separate cores for TX and RX");
6522 /* XXX change for per-queue sizes */
6523 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6524 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6525 mp_ndesc_handler, "A",
6526 "list of # of TX descriptors to use, 0 = use default #");
6527 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6528 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6529 mp_ndesc_handler, "A",
6530 "list of # of RX descriptors to use, 0 = use default #");
6534 iflib_add_device_sysctl_post(if_ctx_t ctx)
6536 if_shared_ctx_t sctx = ctx->ifc_sctx;
6537 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6538 device_t dev = iflib_get_dev(ctx);
6539 struct sysctl_oid_list *child;
6540 struct sysctl_ctx_list *ctx_list;
6545 char namebuf[NAME_BUFLEN];
6547 struct sysctl_oid *queue_node, *fl_node, *node;
6548 struct sysctl_oid_list *queue_list, *fl_list;
6549 ctx_list = device_get_sysctl_ctx(dev);
6551 node = ctx->ifc_sysctl_node;
6552 child = SYSCTL_CHILDREN(node);
6554 if (scctx->isc_ntxqsets > 100)
6556 else if (scctx->isc_ntxqsets > 10)
6560 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6561 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6562 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6563 CTLFLAG_RD, NULL, "Queue Name");
6564 queue_list = SYSCTL_CHILDREN(queue_node);
6566 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6568 &txq->ift_dequeued, "total mbufs freed");
6569 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6571 &txq->ift_enqueued, "total mbufs enqueued");
6573 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6575 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6576 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6578 &txq->ift_pullups, "# of times m_pullup was called");
6579 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6581 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6582 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6584 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6585 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6587 &txq->ift_map_failed, "# of times DMA map failed");
6588 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6590 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6591 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6593 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6594 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6596 &txq->ift_pidx, 1, "Producer Index");
6597 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6599 &txq->ift_cidx, 1, "Consumer Index");
6600 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6602 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6603 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6605 &txq->ift_in_use, 1, "descriptors in use");
6606 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6608 &txq->ift_processed, "descriptors procesed for clean");
6609 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6611 &txq->ift_cleaned, "total cleaned");
6612 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6613 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6614 0, mp_ring_state_handler, "A", "soft ring state");
6615 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6616 CTLFLAG_RD, &txq->ift_br->enqueues,
6617 "# of enqueues to the mp_ring for this queue");
6618 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6619 CTLFLAG_RD, &txq->ift_br->drops,
6620 "# of drops in the mp_ring for this queue");
6621 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6622 CTLFLAG_RD, &txq->ift_br->starts,
6623 "# of normal consumer starts in the mp_ring for this queue");
6624 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6625 CTLFLAG_RD, &txq->ift_br->stalls,
6626 "# of consumer stalls in the mp_ring for this queue");
6627 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6628 CTLFLAG_RD, &txq->ift_br->restarts,
6629 "# of consumer restarts in the mp_ring for this queue");
6630 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6631 CTLFLAG_RD, &txq->ift_br->abdications,
6632 "# of consumer abdications in the mp_ring for this queue");
6635 if (scctx->isc_nrxqsets > 100)
6637 else if (scctx->isc_nrxqsets > 10)
6641 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6642 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6643 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6644 CTLFLAG_RD, NULL, "Queue Name");
6645 queue_list = SYSCTL_CHILDREN(queue_node);
6646 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6647 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6649 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6652 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6653 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6654 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6655 CTLFLAG_RD, NULL, "freelist Name");
6656 fl_list = SYSCTL_CHILDREN(fl_node);
6657 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6659 &fl->ifl_pidx, 1, "Producer Index");
6660 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6662 &fl->ifl_cidx, 1, "Consumer Index");
6663 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6665 &fl->ifl_credits, 1, "credits available");
6667 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6669 &fl->ifl_m_enqueued, "mbufs allocated");
6670 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6672 &fl->ifl_m_dequeued, "mbufs freed");
6673 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6675 &fl->ifl_cl_enqueued, "clusters allocated");
6676 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6678 &fl->ifl_cl_dequeued, "clusters freed");
6687 iflib_request_reset(if_ctx_t ctx)
6691 ctx->ifc_flags |= IFC_DO_RESET;
6695 #ifndef __NO_STRICT_ALIGNMENT
6696 static struct mbuf *
6697 iflib_fixup_rx(struct mbuf *m)
6701 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6702 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6703 m->m_data += ETHER_HDR_LEN;
6706 MGETHDR(n, M_NOWAIT, MT_DATA);
6711 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6712 m->m_data += ETHER_HDR_LEN;
6713 m->m_len -= ETHER_HDR_LEN;
6714 n->m_len = ETHER_HDR_LEN;
6715 M_MOVE_PKTHDR(n, m);
6724 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6728 ctx = if_getsoftc(ifp);
6730 *nrxr = NRXQSETS(ctx);
6731 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6732 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6737 iflib_netdump_event(if_t ifp, enum netdump_ev event)
6740 if_softc_ctx_t scctx;
6745 ctx = if_getsoftc(ifp);
6746 scctx = &ctx->ifc_softc_ctx;
6750 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6751 rxq = &ctx->ifc_rxqs[i];
6752 for (j = 0; j < rxq->ifr_nfl; j++) {
6754 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6757 iflib_no_tx_batch = 1;
6765 iflib_netdump_transmit(if_t ifp, struct mbuf *m)
6771 ctx = if_getsoftc(ifp);
6772 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6776 txq = &ctx->ifc_txqs[0];
6777 error = iflib_encap(txq, &m);
6779 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6784 iflib_netdump_poll(if_t ifp, int count)
6787 if_softc_ctx_t scctx;
6791 ctx = if_getsoftc(ifp);
6792 scctx = &ctx->ifc_softc_ctx;
6794 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6798 txq = &ctx->ifc_txqs[0];
6799 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6801 for (i = 0; i < scctx->isc_nrxqsets; i++)
6802 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6805 #endif /* NETDUMP */