2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 struct ether_addr ifc_mac;
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (ctx->ifc_mediap);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_buf_tag;
357 bus_dma_tag_t ift_tso_buf_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 32
360 char ift_mtx_name[MTX_NAME_LEN];
361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 uint64_t ift_cpu_exec_count[256];
365 } __aligned(CACHE_LINE_SIZE);
372 uint8_t ifl_rxd_size;
374 uint64_t ifl_m_enqueued;
375 uint64_t ifl_m_dequeued;
376 uint64_t ifl_cl_enqueued;
377 uint64_t ifl_cl_dequeued;
380 bitstr_t *ifl_rx_bitmap;
384 uint16_t ifl_buf_size;
387 iflib_rxsd_array_t ifl_sds;
390 bus_dma_tag_t ifl_buf_tag;
391 iflib_dma_info_t ifl_ifdi;
392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the command queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct callout ifr_watchdog;
438 struct iflib_filter_info ifr_filter_info;
439 iflib_dma_info_t ifr_ifdi;
441 /* dynamically allocate if any drivers need a value substantially larger than this */
442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 uint64_t ifr_cpu_exec_count[256];
446 } __aligned(CACHE_LINE_SIZE);
448 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
708 static void iflib_init_locked(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
710 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
711 static void iflib_ifmp_purge(iflib_txq_t txq);
712 static void _iflib_pre_assert(if_softc_ctx_t scctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 static void iflib_free_intr_mem(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
720 SLIST_HEAD_INITIALIZER(cpu_offsets);
722 SLIST_ENTRY(cpu_offset) entries;
724 unsigned int refcount;
727 static struct mtx cpu_offset_mtx;
728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
731 DEBUGNET_DEFINE(iflib);
734 iflib_num_rx_descs(if_ctx_t ctx)
736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
737 if_shared_ctx_t sctx = ctx->ifc_sctx;
738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
740 return scctx->isc_nrxd[first_rxq];
744 iflib_num_tx_descs(if_ctx_t ctx)
746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
747 if_shared_ctx_t sctx = ctx->ifc_sctx;
748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
750 return scctx->isc_ntxd[first_txq];
754 #include <sys/selinfo.h>
755 #include <net/netmap.h>
756 #include <dev/netmap/netmap_kern.h>
758 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
763 * device-specific sysctl variables:
765 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
766 * During regular operations the CRC is stripped, but on some
767 * hardware reception of frames not multiple of 64 is slower,
768 * so using crcstrip=0 helps in benchmarks.
770 * iflib_rx_miss, iflib_rx_miss_bufs:
771 * count packets that might be missed due to lost interrupts.
773 SYSCTL_DECL(_dev_netmap);
775 * The xl driver by default strips CRCs and we do not override it.
778 int iflib_crcstrip = 1;
779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
780 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
782 int iflib_rx_miss, iflib_rx_miss_bufs;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
784 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
786 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
789 * Register/unregister. We are already under netmap lock.
790 * Only called on the first register or the last unregister.
793 iflib_netmap_register(struct netmap_adapter *na, int onoff)
796 if_ctx_t ctx = ifp->if_softc;
800 IFDI_INTR_DISABLE(ctx);
802 /* Tell the stack that the interface is no longer active */
803 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
811 * Enable (or disable) netmap flags, and intercept (or restore)
812 * ifp->if_transmit. This is done once the device has been stopped
813 * to prevent race conditions.
816 nm_set_native_flags(na);
818 nm_clear_native_flags(na);
821 iflib_init_locked(ctx);
822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
825 nm_clear_native_flags(na);
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
833 struct netmap_adapter *na = kring->na;
834 u_int const lim = kring->nkr_num_slots - 1;
835 u_int head = kring->rhead;
836 struct netmap_ring *ring = kring->ring;
838 struct if_rxd_update iru;
839 if_ctx_t ctx = rxq->ifr_ctx;
840 iflib_fl_t fl = &rxq->ifr_fl[0];
841 uint32_t refill_pidx, nic_i;
842 #if IFLIB_DEBUG_COUNTERS
846 if (nm_i == head && __predict_true(!init))
848 iru_init(&iru, rxq, 0 /* flid */);
849 map = fl->ifl_sds.ifsd_map;
850 refill_pidx = netmap_idx_k2n(kring, nm_i);
852 * IMPORTANT: we must leave one free slot in the ring,
853 * so move head back by one unit
855 head = nm_prev(head, lim);
857 DBG_COUNTER_INC(fl_refills);
858 while (nm_i != head) {
859 #if IFLIB_DEBUG_COUNTERS
861 DBG_COUNTER_INC(fl_refills_large);
863 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
864 struct netmap_slot *slot = &ring->slot[nm_i];
865 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
866 uint32_t nic_i_dma = refill_pidx;
867 nic_i = netmap_idx_k2n(kring, nm_i);
869 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
871 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
872 return netmap_ring_reinit(kring);
874 if (__predict_false(init)) {
875 netmap_load_map(na, fl->ifl_buf_tag,
877 } else if (slot->flags & NS_BUF_CHANGED) {
878 /* buffer has changed, reload map */
879 netmap_reload_map(na, fl->ifl_buf_tag,
882 slot->flags &= ~NS_BUF_CHANGED;
884 nm_i = nm_next(nm_i, lim);
885 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
886 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
889 iru.iru_pidx = refill_pidx;
890 iru.iru_count = tmp_pidx+1;
891 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
893 for (int n = 0; n < iru.iru_count; n++) {
894 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
895 BUS_DMASYNC_PREREAD);
896 /* XXX - change this to not use the netmap func*/
897 nic_i_dma = nm_next(nic_i_dma, lim);
901 kring->nr_hwcur = head;
903 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
904 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
905 if (__predict_true(nic_i != UINT_MAX)) {
906 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
907 DBG_COUNTER_INC(rxd_flush);
913 * Reconcile kernel and user view of the transmit ring.
915 * All information is in the kring.
916 * Userspace wants to send packets up to the one before kring->rhead,
917 * kernel knows kring->nr_hwcur is the first unsent packet.
919 * Here we push packets out (as many as possible), and possibly
920 * reclaim buffers from previously completed transmission.
922 * The caller (netmap) guarantees that there is only one instance
923 * running at any time. Any interference with other driver
924 * methods should be handled by the individual drivers.
927 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
929 struct netmap_adapter *na = kring->na;
931 struct netmap_ring *ring = kring->ring;
932 u_int nm_i; /* index into the netmap kring */
933 u_int nic_i; /* index into the NIC ring */
935 u_int const lim = kring->nkr_num_slots - 1;
936 u_int const head = kring->rhead;
937 struct if_pkt_info pi;
940 * interrupts on every tx packet are expensive so request
941 * them every half ring, or where NS_REPORT is set
943 u_int report_frequency = kring->nkr_num_slots >> 1;
944 /* device-specific */
945 if_ctx_t ctx = ifp->if_softc;
946 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
948 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
949 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
952 * First part: process new packets to send.
953 * nm_i is the current index in the netmap kring,
954 * nic_i is the corresponding index in the NIC ring.
956 * If we have packets to send (nm_i != head)
957 * iterate over the netmap ring, fetch length and update
958 * the corresponding slot in the NIC ring. Some drivers also
959 * need to update the buffer's physical address in the NIC slot
960 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
962 * The netmap_reload_map() calls is especially expensive,
963 * even when (as in this case) the tag is 0, so do only
964 * when the buffer has actually changed.
966 * If possible do not set the report/intr bit on all slots,
967 * but only a few times per ring or when NS_REPORT is set.
969 * Finally, on 10G and faster drivers, it might be useful
970 * to prefetch the next slot and txr entry.
973 nm_i = kring->nr_hwcur;
974 if (nm_i != head) { /* we have new packets to send */
976 pi.ipi_segs = txq->ift_segs;
977 pi.ipi_qsidx = kring->ring_id;
978 nic_i = netmap_idx_k2n(kring, nm_i);
980 __builtin_prefetch(&ring->slot[nm_i]);
981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
982 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
984 for (n = 0; nm_i != head; n++) {
985 struct netmap_slot *slot = &ring->slot[nm_i];
986 u_int len = slot->len;
988 void *addr = PNMB(na, slot, &paddr);
989 int flags = (slot->flags & NS_REPORT ||
990 nic_i == 0 || nic_i == report_frequency) ?
993 /* device-specific */
995 pi.ipi_segs[0].ds_addr = paddr;
996 pi.ipi_segs[0].ds_len = len;
1000 pi.ipi_flags = flags;
1002 /* Fill the slot in the NIC ring. */
1003 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1004 DBG_COUNTER_INC(tx_encap);
1006 /* prefetch for next round */
1007 __builtin_prefetch(&ring->slot[nm_i + 1]);
1008 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1009 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1011 NM_CHECK_ADDR_LEN(na, addr, len);
1013 if (slot->flags & NS_BUF_CHANGED) {
1014 /* buffer has changed, reload map */
1015 netmap_reload_map(na, txq->ift_buf_tag,
1016 txq->ift_sds.ifsd_map[nic_i], addr);
1018 /* make sure changes to the buffer are synced */
1019 bus_dmamap_sync(txq->ift_buf_tag,
1020 txq->ift_sds.ifsd_map[nic_i],
1021 BUS_DMASYNC_PREWRITE);
1023 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1024 nm_i = nm_next(nm_i, lim);
1025 nic_i = nm_next(nic_i, lim);
1027 kring->nr_hwcur = nm_i;
1029 /* synchronize the NIC ring */
1030 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1031 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1033 /* (re)start the tx unit up to slot nic_i (excluded) */
1034 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1038 * Second part: reclaim buffers for completed transmissions.
1040 * If there are unclaimed buffers, attempt to reclaim them.
1041 * If none are reclaimed, and TX IRQs are not in use, do an initial
1042 * minimal delay, then trigger the tx handler which will spin in the
1045 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1046 if (iflib_tx_credits_update(ctx, txq)) {
1047 /* some tx completed, increment avail */
1048 nic_i = txq->ift_cidx_processed;
1049 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1052 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1053 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1054 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1055 iflib_timer, txq, txq->ift_timer.c_cpu);
1061 * Reconcile kernel and user view of the receive ring.
1062 * Same as for the txsync, this routine must be efficient.
1063 * The caller guarantees a single invocations, but races against
1064 * the rest of the driver should be handled here.
1066 * On call, kring->rhead is the first packet that userspace wants
1067 * to keep, and kring->rcur is the wakeup point.
1068 * The kernel has previously reported packets up to kring->rtail.
1070 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1071 * of whether or not we received an interrupt.
1074 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1076 struct netmap_adapter *na = kring->na;
1077 struct netmap_ring *ring = kring->ring;
1079 uint32_t nm_i; /* index into the netmap ring */
1080 uint32_t nic_i; /* index into the NIC ring */
1082 u_int const lim = kring->nkr_num_slots - 1;
1083 u_int const head = kring->rhead;
1084 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1086 if_ctx_t ctx = ifp->if_softc;
1087 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1088 iflib_fl_t fl = &rxq->ifr_fl[0];
1089 struct if_rxd_info ri;
1092 return netmap_ring_reinit(kring);
1095 * netmap only uses free list 0, to avoid out of order consumption
1096 * of receive buffers
1099 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1100 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1103 * First part: import newly received packets.
1105 * nm_i is the index of the next free slot in the netmap ring,
1106 * nic_i is the index of the next received packet in the NIC ring,
1107 * and they may differ in case if_init() has been called while
1108 * in netmap mode. For the receive ring we have
1110 * nic_i = rxr->next_check;
1111 * nm_i = kring->nr_hwtail (previous)
1113 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1115 * rxr->next_check is set to 0 on a ring reinit
1117 if (netmap_no_pendintr || force_update) {
1118 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1119 int crclen = iflib_crcstrip ? 0 : 4;
1122 nic_i = fl->ifl_cidx;
1123 nm_i = netmap_idx_n2k(kring, nic_i);
1124 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1125 rxq->ifr_id, nic_i, USHRT_MAX);
1126 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1128 ri.iri_frags = rxq->ifr_frags;
1129 ri.iri_qsidx = kring->ring_id;
1130 ri.iri_ifp = ctx->ifc_ifp;
1131 ri.iri_cidx = nic_i;
1133 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1134 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1135 ring->slot[nm_i].flags = 0;
1136 bus_dmamap_sync(fl->ifl_buf_tag,
1137 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1138 nm_i = nm_next(nm_i, lim);
1139 nic_i = nm_next(nic_i, lim);
1141 if (n) { /* update the state variables */
1142 if (netmap_no_pendintr && !force_update) {
1145 iflib_rx_miss_bufs += n;
1147 fl->ifl_cidx = nic_i;
1148 kring->nr_hwtail = nm_i;
1150 kring->nr_kflags &= ~NKR_PENDINTR;
1153 * Second part: skip past packets that userspace has released.
1154 * (kring->nr_hwcur to head excluded),
1155 * and make the buffers available for reception.
1156 * As usual nm_i is the index in the netmap ring,
1157 * nic_i is the index in the NIC ring, and
1158 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1160 nm_i = kring->nr_hwcur;
1162 return (netmap_fl_refill(rxq, kring, nm_i, false));
1166 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1168 if_ctx_t ctx = na->ifp->if_softc;
1172 IFDI_INTR_ENABLE(ctx);
1174 IFDI_INTR_DISABLE(ctx);
1181 iflib_netmap_attach(if_ctx_t ctx)
1183 struct netmap_adapter na;
1185 bzero(&na, sizeof(na));
1187 na.ifp = ctx->ifc_ifp;
1188 na.na_flags = NAF_BDG_MAYSLEEP;
1189 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1190 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1192 na.num_tx_desc = iflib_num_tx_descs(ctx);
1193 na.num_rx_desc = iflib_num_rx_descs(ctx);
1194 na.nm_txsync = iflib_netmap_txsync;
1195 na.nm_rxsync = iflib_netmap_rxsync;
1196 na.nm_register = iflib_netmap_register;
1197 na.nm_intr = iflib_netmap_intr;
1198 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1199 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1200 return (netmap_attach(&na));
1204 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1206 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1207 struct netmap_slot *slot;
1209 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1212 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1215 * In netmap mode, set the map for the packet buffer.
1216 * NOTE: Some drivers (not this one) also need to set
1217 * the physical buffer address in the NIC ring.
1218 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1219 * netmap slot index, si
1221 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1222 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1223 NMB(na, slot + si));
1229 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1231 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1232 struct netmap_kring *kring;
1233 struct netmap_slot *slot;
1236 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1239 kring = na->rx_rings[rxq->ifr_id];
1240 nm_i = netmap_idx_n2k(kring, 0);
1241 netmap_fl_refill(rxq, kring, nm_i, true);
1246 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1248 struct netmap_kring *kring;
1251 txqid = txq->ift_id;
1252 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX);
1256 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1257 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1258 BUS_DMASYNC_POSTREAD);
1259 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1260 netmap_tx_irq(ctx->ifc_ifp, txqid);
1261 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1265 *reset_on = hz / 1000;
1270 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1273 #define iflib_netmap_txq_init(ctx, txq) (0)
1274 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1275 #define iflib_netmap_detach(ifp)
1277 #define iflib_netmap_attach(ctx) (0)
1278 #define netmap_rx_irq(ifp, qid, budget) (0)
1279 #define netmap_tx_irq(ifp, qid) do {} while (0)
1280 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1283 #if defined(__i386__) || defined(__amd64__)
1284 static __inline void
1287 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1289 static __inline void
1290 prefetch2cachelines(void *x)
1292 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1293 #if (CACHE_LINE_SIZE < 128)
1294 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1299 #define prefetch2cachelines(x)
1303 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1307 fl = &rxq->ifr_fl[flid];
1308 iru->iru_paddrs = fl->ifl_bus_addrs;
1309 iru->iru_idxs = fl->ifl_rxd_idxs;
1310 iru->iru_qsidx = rxq->ifr_id;
1311 iru->iru_buf_size = fl->ifl_buf_size;
1312 iru->iru_flidx = fl->ifl_id;
1316 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1320 *(bus_addr_t *) arg = segs[0].ds_addr;
1324 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1327 device_t dev = ctx->ifc_dev;
1329 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1330 align, 0, /* alignment, bounds */
1331 BUS_SPACE_MAXADDR, /* lowaddr */
1332 BUS_SPACE_MAXADDR, /* highaddr */
1333 NULL, NULL, /* filter, filterarg */
1336 size, /* maxsegsize */
1337 BUS_DMA_ALLOCNOW, /* flags */
1338 NULL, /* lockfunc */
1343 "%s: bus_dma_tag_create failed: %d\n",
1348 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1349 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1352 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1353 __func__, (uintmax_t)size, err);
1357 dma->idi_paddr = IF_BAD_DMA;
1358 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1359 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1360 if (err || dma->idi_paddr == IF_BAD_DMA) {
1362 "%s: bus_dmamap_load failed: %d\n",
1367 dma->idi_size = size;
1371 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1373 bus_dma_tag_destroy(dma->idi_tag);
1375 dma->idi_tag = NULL;
1381 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1383 if_shared_ctx_t sctx = ctx->ifc_sctx;
1385 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1387 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1391 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1394 iflib_dma_info_t *dmaiter;
1397 for (i = 0; i < count; i++, dmaiter++) {
1398 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1402 iflib_dma_free_multi(dmalist, i);
1407 iflib_dma_free(iflib_dma_info_t dma)
1409 if (dma->idi_tag == NULL)
1411 if (dma->idi_paddr != IF_BAD_DMA) {
1412 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1413 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1414 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1415 dma->idi_paddr = IF_BAD_DMA;
1417 if (dma->idi_vaddr != NULL) {
1418 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1419 dma->idi_vaddr = NULL;
1421 bus_dma_tag_destroy(dma->idi_tag);
1422 dma->idi_tag = NULL;
1426 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1429 iflib_dma_info_t *dmaiter = dmalist;
1431 for (i = 0; i < count; i++, dmaiter++)
1432 iflib_dma_free(*dmaiter);
1436 iflib_fast_intr(void *arg)
1438 iflib_filter_info_t info = arg;
1439 struct grouptask *gtask = info->ifi_task;
1442 DBG_COUNTER_INC(fast_intrs);
1443 if (info->ifi_filter != NULL) {
1444 result = info->ifi_filter(info->ifi_filter_arg);
1445 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1449 GROUPTASK_ENQUEUE(gtask);
1450 return (FILTER_HANDLED);
1454 iflib_fast_intr_rxtx(void *arg)
1456 iflib_filter_info_t info = arg;
1457 struct grouptask *gtask = info->ifi_task;
1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1462 int i, cidx, result;
1464 bool intr_enable, intr_legacy;
1466 DBG_COUNTER_INC(fast_intrs);
1467 if (info->ifi_filter != NULL) {
1468 result = info->ifi_filter(info->ifi_filter_arg);
1469 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1474 sc = ctx->ifc_softc;
1475 intr_enable = false;
1476 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1477 MPASS(rxq->ifr_ntxqirq);
1478 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1479 txqid = rxq->ifr_txqid[i];
1480 txq = &ctx->ifc_txqs[txqid];
1481 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1482 BUS_DMASYNC_POSTREAD);
1483 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1487 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1490 GROUPTASK_ENQUEUE(&txq->ift_task);
1492 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1493 cidx = rxq->ifr_cq_cidx;
1495 cidx = rxq->ifr_fl[0].ifl_cidx;
1496 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1497 GROUPTASK_ENQUEUE(gtask);
1502 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1503 DBG_COUNTER_INC(rx_intr_enables);
1506 IFDI_INTR_ENABLE(ctx);
1507 return (FILTER_HANDLED);
1512 iflib_fast_intr_ctx(void *arg)
1514 iflib_filter_info_t info = arg;
1515 struct grouptask *gtask = info->ifi_task;
1518 DBG_COUNTER_INC(fast_intrs);
1519 if (info->ifi_filter != NULL) {
1520 result = info->ifi_filter(info->ifi_filter_arg);
1521 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1525 GROUPTASK_ENQUEUE(gtask);
1526 return (FILTER_HANDLED);
1530 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1531 driver_filter_t filter, driver_intr_t handler, void *arg,
1534 struct resource *res;
1536 device_t dev = ctx->ifc_dev;
1540 if (ctx->ifc_flags & IFC_LEGACY)
1541 flags |= RF_SHAREABLE;
1544 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1547 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1551 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1552 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1553 filter, handler, arg, &tag);
1556 "failed to setup interrupt for rid %d, name %s: %d\n",
1557 rid, name ? name : "unknown", rc);
1560 bus_describe_intr(dev, res, tag, "%s", name);
1566 /*********************************************************************
1568 * Allocate DMA resources for TX buffers as well as memory for the TX
1569 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1570 * iflib_sw_tx_desc_array structure, storing all the information that
1571 * is needed to transmit a packet on the wire. This is called only
1572 * once at attach, setup is done every reset.
1574 **********************************************************************/
1576 iflib_txsd_alloc(iflib_txq_t txq)
1578 if_ctx_t ctx = txq->ift_ctx;
1579 if_shared_ctx_t sctx = ctx->ifc_sctx;
1580 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1581 device_t dev = ctx->ifc_dev;
1582 bus_size_t tsomaxsize;
1583 int err, nsegments, ntsosegments;
1586 nsegments = scctx->isc_tx_nsegments;
1587 ntsosegments = scctx->isc_tx_tso_segments_max;
1588 tsomaxsize = scctx->isc_tx_tso_size_max;
1589 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1590 tsomaxsize += sizeof(struct ether_vlan_header);
1591 MPASS(scctx->isc_ntxd[0] > 0);
1592 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1593 MPASS(nsegments > 0);
1594 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1595 MPASS(ntsosegments > 0);
1596 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1600 * Set up DMA tags for TX buffers.
1602 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1603 1, 0, /* alignment, bounds */
1604 BUS_SPACE_MAXADDR, /* lowaddr */
1605 BUS_SPACE_MAXADDR, /* highaddr */
1606 NULL, NULL, /* filter, filterarg */
1607 sctx->isc_tx_maxsize, /* maxsize */
1608 nsegments, /* nsegments */
1609 sctx->isc_tx_maxsegsize, /* maxsegsize */
1611 NULL, /* lockfunc */
1612 NULL, /* lockfuncarg */
1613 &txq->ift_buf_tag))) {
1614 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1615 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1616 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1619 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1620 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1621 1, 0, /* alignment, bounds */
1622 BUS_SPACE_MAXADDR, /* lowaddr */
1623 BUS_SPACE_MAXADDR, /* highaddr */
1624 NULL, NULL, /* filter, filterarg */
1625 tsomaxsize, /* maxsize */
1626 ntsosegments, /* nsegments */
1627 sctx->isc_tso_maxsegsize,/* maxsegsize */
1629 NULL, /* lockfunc */
1630 NULL, /* lockfuncarg */
1631 &txq->ift_tso_buf_tag))) {
1632 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1637 /* Allocate memory for the TX mbuf map. */
1638 if (!(txq->ift_sds.ifsd_m =
1639 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1640 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1641 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1647 * Create the DMA maps for TX buffers.
1649 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1650 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1651 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1653 "Unable to allocate TX buffer DMA map memory\n");
1657 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1658 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1659 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1661 "Unable to allocate TSO TX buffer map memory\n");
1665 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1666 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1667 &txq->ift_sds.ifsd_map[i]);
1669 device_printf(dev, "Unable to create TX DMA map\n");
1674 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1675 &txq->ift_sds.ifsd_tso_map[i]);
1677 device_printf(dev, "Unable to create TSO TX DMA map\n");
1683 /* We free all, it handles case where we are in the middle */
1684 iflib_tx_structures_free(ctx);
1689 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1693 if (txq->ift_sds.ifsd_map != NULL) {
1694 map = txq->ift_sds.ifsd_map[i];
1695 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1696 bus_dmamap_unload(txq->ift_buf_tag, map);
1697 bus_dmamap_destroy(txq->ift_buf_tag, map);
1698 txq->ift_sds.ifsd_map[i] = NULL;
1701 if (txq->ift_sds.ifsd_tso_map != NULL) {
1702 map = txq->ift_sds.ifsd_tso_map[i];
1703 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1704 BUS_DMASYNC_POSTWRITE);
1705 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1706 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1707 txq->ift_sds.ifsd_tso_map[i] = NULL;
1712 iflib_txq_destroy(iflib_txq_t txq)
1714 if_ctx_t ctx = txq->ift_ctx;
1716 for (int i = 0; i < txq->ift_size; i++)
1717 iflib_txsd_destroy(ctx, txq, i);
1719 if (txq->ift_br != NULL) {
1720 ifmp_ring_free(txq->ift_br);
1724 mtx_destroy(&txq->ift_mtx);
1726 if (txq->ift_sds.ifsd_map != NULL) {
1727 free(txq->ift_sds.ifsd_map, M_IFLIB);
1728 txq->ift_sds.ifsd_map = NULL;
1730 if (txq->ift_sds.ifsd_tso_map != NULL) {
1731 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1732 txq->ift_sds.ifsd_tso_map = NULL;
1734 if (txq->ift_sds.ifsd_m != NULL) {
1735 free(txq->ift_sds.ifsd_m, M_IFLIB);
1736 txq->ift_sds.ifsd_m = NULL;
1738 if (txq->ift_buf_tag != NULL) {
1739 bus_dma_tag_destroy(txq->ift_buf_tag);
1740 txq->ift_buf_tag = NULL;
1742 if (txq->ift_tso_buf_tag != NULL) {
1743 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1744 txq->ift_tso_buf_tag = NULL;
1746 if (txq->ift_ifdi != NULL) {
1747 free(txq->ift_ifdi, M_IFLIB);
1752 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1756 mp = &txq->ift_sds.ifsd_m[i];
1760 if (txq->ift_sds.ifsd_map != NULL) {
1761 bus_dmamap_sync(txq->ift_buf_tag,
1762 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1763 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1765 if (txq->ift_sds.ifsd_tso_map != NULL) {
1766 bus_dmamap_sync(txq->ift_tso_buf_tag,
1767 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1768 bus_dmamap_unload(txq->ift_tso_buf_tag,
1769 txq->ift_sds.ifsd_tso_map[i]);
1772 DBG_COUNTER_INC(tx_frees);
1777 iflib_txq_setup(iflib_txq_t txq)
1779 if_ctx_t ctx = txq->ift_ctx;
1780 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1781 if_shared_ctx_t sctx = ctx->ifc_sctx;
1782 iflib_dma_info_t di;
1785 /* Set number of descriptors available */
1786 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1787 /* XXX make configurable */
1788 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1791 txq->ift_cidx_processed = 0;
1792 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1793 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1795 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1796 bzero((void *)di->idi_vaddr, di->idi_size);
1798 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1799 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1800 bus_dmamap_sync(di->idi_tag, di->idi_map,
1801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1805 /*********************************************************************
1807 * Allocate DMA resources for RX buffers as well as memory for the RX
1808 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1809 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1810 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1811 * Since we use use one entry in iflib_sw_rx_desc_array per received
1812 * packet, the maximum number of entries we'll need is equal to the
1813 * number of hardware receive descriptors that we've allocated.
1815 **********************************************************************/
1817 iflib_rxsd_alloc(iflib_rxq_t rxq)
1819 if_ctx_t ctx = rxq->ifr_ctx;
1820 if_shared_ctx_t sctx = ctx->ifc_sctx;
1821 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1822 device_t dev = ctx->ifc_dev;
1826 MPASS(scctx->isc_nrxd[0] > 0);
1827 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1830 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1831 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1832 /* Set up DMA tag for RX buffers. */
1833 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1834 1, 0, /* alignment, bounds */
1835 BUS_SPACE_MAXADDR, /* lowaddr */
1836 BUS_SPACE_MAXADDR, /* highaddr */
1837 NULL, NULL, /* filter, filterarg */
1838 sctx->isc_rx_maxsize, /* maxsize */
1839 sctx->isc_rx_nsegments, /* nsegments */
1840 sctx->isc_rx_maxsegsize, /* maxsegsize */
1842 NULL, /* lockfunc */
1847 "Unable to allocate RX DMA tag: %d\n", err);
1851 /* Allocate memory for the RX mbuf map. */
1852 if (!(fl->ifl_sds.ifsd_m =
1853 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1854 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1856 "Unable to allocate RX mbuf map memory\n");
1861 /* Allocate memory for the direct RX cluster pointer map. */
1862 if (!(fl->ifl_sds.ifsd_cl =
1863 (caddr_t *) malloc(sizeof(caddr_t) *
1864 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1866 "Unable to allocate RX cluster map memory\n");
1871 /* Allocate memory for the RX cluster bus address map. */
1872 if (!(fl->ifl_sds.ifsd_ba =
1873 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1874 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1876 "Unable to allocate RX bus address map memory\n");
1882 * Create the DMA maps for RX buffers.
1884 if (!(fl->ifl_sds.ifsd_map =
1885 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1887 "Unable to allocate RX buffer DMA map memory\n");
1891 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1892 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1893 &fl->ifl_sds.ifsd_map[i]);
1895 device_printf(dev, "Unable to create RX buffer DMA map\n");
1903 iflib_rx_structures_free(ctx);
1909 * Internal service routines
1912 struct rxq_refill_cb_arg {
1914 bus_dma_segment_t seg;
1919 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1921 struct rxq_refill_cb_arg *cb_arg = arg;
1923 cb_arg->error = error;
1924 cb_arg->seg = segs[0];
1925 cb_arg->nseg = nseg;
1929 * iflib_fl_refill - refill an rxq free-buffer list
1930 * @ctx: the iflib context
1931 * @fl: the free list to refill
1932 * @count: the number of new buffers to allocate
1934 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1935 * The caller must assure that @count does not exceed the queue's capacity.
1938 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1940 struct if_rxd_update iru;
1941 struct rxq_refill_cb_arg cb_arg;
1945 bus_dmamap_t *sd_map;
1946 bus_addr_t bus_addr, *sd_ba;
1947 int err, frag_idx, i, idx, n, pidx;
1950 sd_m = fl->ifl_sds.ifsd_m;
1951 sd_map = fl->ifl_sds.ifsd_map;
1952 sd_cl = fl->ifl_sds.ifsd_cl;
1953 sd_ba = fl->ifl_sds.ifsd_ba;
1954 pidx = fl->ifl_pidx;
1956 frag_idx = fl->ifl_fragidx;
1957 credits = fl->ifl_credits;
1962 MPASS(credits + n <= fl->ifl_size);
1964 if (pidx < fl->ifl_cidx)
1965 MPASS(pidx + n <= fl->ifl_cidx);
1966 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1967 MPASS(fl->ifl_gen == 0);
1968 if (pidx > fl->ifl_cidx)
1969 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1971 DBG_COUNTER_INC(fl_refills);
1973 DBG_COUNTER_INC(fl_refills_large);
1974 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1977 * We allocate an uninitialized mbuf + cluster, mbuf is
1978 * initialized after rx.
1980 * If the cluster is still set then we know a minimum sized
1981 * packet was received
1983 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1986 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1987 MPASS(frag_idx >= 0);
1988 if ((cl = sd_cl[frag_idx]) == NULL) {
1989 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
1990 if (__predict_false(cl == NULL))
1994 MPASS(sd_map != NULL);
1995 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1996 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1998 if (__predict_false(err != 0 || cb_arg.error)) {
1999 uma_zfree(fl->ifl_zone, cl);
2003 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2004 sd_cl[frag_idx] = cl;
2006 fl->ifl_cl_enqueued++;
2009 bus_addr = sd_ba[frag_idx];
2011 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2012 BUS_DMASYNC_PREREAD);
2014 if (sd_m[frag_idx] == NULL) {
2015 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2016 if (__predict_false(m == NULL))
2020 bit_set(fl->ifl_rx_bitmap, frag_idx);
2022 fl->ifl_m_enqueued++;
2025 DBG_COUNTER_INC(rx_allocs);
2026 fl->ifl_rxd_idxs[i] = frag_idx;
2027 fl->ifl_bus_addrs[i] = bus_addr;
2030 MPASS(credits <= fl->ifl_size);
2031 if (++idx == fl->ifl_size) {
2037 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2038 iru.iru_pidx = pidx;
2040 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2042 fl->ifl_credits = credits;
2048 if (n < count - 1) {
2050 iru.iru_pidx = pidx;
2052 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2054 fl->ifl_credits = credits;
2056 DBG_COUNTER_INC(rxd_flush);
2057 if (fl->ifl_pidx == 0)
2058 pidx = fl->ifl_size - 1;
2060 pidx = fl->ifl_pidx - 1;
2062 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2063 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2064 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2066 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2067 fl->ifl_fragidx = frag_idx + 1;
2068 if (fl->ifl_fragidx == fl->ifl_size)
2069 fl->ifl_fragidx = 0;
2071 fl->ifl_fragidx = frag_idx;
2075 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2078 static inline uint8_t
2079 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2081 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2082 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2084 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2087 MPASS(fl->ifl_credits <= fl->ifl_size);
2088 MPASS(reclaimable == delta);
2090 if (reclaimable > 0)
2091 return (iflib_fl_refill(ctx, fl, reclaimable));
2096 iflib_in_detach(if_ctx_t ctx)
2101 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2107 iflib_fl_bufs_free(iflib_fl_t fl)
2109 iflib_dma_info_t idi = fl->ifl_ifdi;
2110 bus_dmamap_t sd_map;
2113 for (i = 0; i < fl->ifl_size; i++) {
2114 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2115 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2117 if (*sd_cl != NULL) {
2118 sd_map = fl->ifl_sds.ifsd_map[i];
2119 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2120 BUS_DMASYNC_POSTREAD);
2121 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2122 uma_zfree(fl->ifl_zone, *sd_cl);
2124 if (*sd_m != NULL) {
2125 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2126 uma_zfree(zone_mbuf, *sd_m);
2130 MPASS(*sd_m == NULL);
2133 fl->ifl_m_dequeued++;
2134 fl->ifl_cl_dequeued++;
2138 for (i = 0; i < fl->ifl_size; i++) {
2139 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2140 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2144 * Reset free list values
2146 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2147 bzero(idi->idi_vaddr, idi->idi_size);
2150 /*********************************************************************
2152 * Initialize a free list and its buffers.
2154 **********************************************************************/
2156 iflib_fl_setup(iflib_fl_t fl)
2158 iflib_rxq_t rxq = fl->ifl_rxq;
2159 if_ctx_t ctx = rxq->ifr_ctx;
2160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2163 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2165 ** Free current RX buffer structs and their mbufs
2167 iflib_fl_bufs_free(fl);
2168 /* Now replenish the mbufs */
2169 MPASS(fl->ifl_credits == 0);
2170 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2171 if (scctx->isc_rxd_buf_size[qidx] != 0)
2172 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2174 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2176 * ifl_buf_size may be a driver-supplied value, so pull it up
2177 * to the selected mbuf size.
2179 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2180 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2181 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2182 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2183 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2186 /* avoid pre-allocating zillions of clusters to an idle card
2187 * potentially speeding up attach
2189 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2190 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2191 if (min(128, fl->ifl_size) != fl->ifl_credits)
2197 MPASS(fl->ifl_ifdi != NULL);
2198 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2199 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2203 /*********************************************************************
2205 * Free receive ring data structures
2207 **********************************************************************/
2209 iflib_rx_sds_free(iflib_rxq_t rxq)
2214 if (rxq->ifr_fl != NULL) {
2215 for (i = 0; i < rxq->ifr_nfl; i++) {
2216 fl = &rxq->ifr_fl[i];
2217 if (fl->ifl_buf_tag != NULL) {
2218 if (fl->ifl_sds.ifsd_map != NULL) {
2219 for (j = 0; j < fl->ifl_size; j++) {
2222 fl->ifl_sds.ifsd_map[j],
2223 BUS_DMASYNC_POSTREAD);
2226 fl->ifl_sds.ifsd_map[j]);
2229 fl->ifl_sds.ifsd_map[j]);
2232 bus_dma_tag_destroy(fl->ifl_buf_tag);
2233 fl->ifl_buf_tag = NULL;
2235 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2236 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2237 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2238 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2239 fl->ifl_sds.ifsd_m = NULL;
2240 fl->ifl_sds.ifsd_cl = NULL;
2241 fl->ifl_sds.ifsd_ba = NULL;
2242 fl->ifl_sds.ifsd_map = NULL;
2244 free(rxq->ifr_fl, M_IFLIB);
2246 free(rxq->ifr_ifdi, M_IFLIB);
2247 rxq->ifr_ifdi = NULL;
2248 rxq->ifr_cq_cidx = 0;
2256 iflib_timer(void *arg)
2258 iflib_txq_t txq = arg;
2259 if_ctx_t ctx = txq->ift_ctx;
2260 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2261 uint64_t this_tick = ticks;
2262 uint32_t reset_on = hz / 2;
2264 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2268 ** Check on the state of the TX queue(s), this
2269 ** can be done without the lock because its RO
2270 ** and the HUNG state will be static if set.
2272 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2273 txq->ift_last_timer_tick = this_tick;
2274 IFDI_TIMER(ctx, txq->ift_id);
2275 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2276 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2277 (sctx->isc_pause_frames == 0)))
2280 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2281 ifmp_ring_is_stalled(txq->ift_br)) {
2282 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2283 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2285 txq->ift_cleaned_prev = txq->ift_cleaned;
2288 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2289 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2291 /* handle any laggards */
2292 if (txq->ift_db_pending)
2293 GROUPTASK_ENQUEUE(&txq->ift_task);
2295 sctx->isc_pause_frames = 0;
2296 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2297 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2301 device_printf(ctx->ifc_dev,
2302 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2303 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2305 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2306 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2307 iflib_admin_intr_deferred(ctx);
2312 iflib_get_mbuf_size_for(unsigned int size)
2315 if (size <= MCLBYTES)
2318 return (MJUMPAGESIZE);
2322 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2324 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2327 * XXX don't set the max_frame_size to larger
2328 * than the hardware can handle
2330 ctx->ifc_rx_mbuf_sz =
2331 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2335 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2338 return (ctx->ifc_rx_mbuf_sz);
2342 iflib_init_locked(if_ctx_t ctx)
2344 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2345 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2346 if_t ifp = ctx->ifc_ifp;
2350 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2352 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2353 IFDI_INTR_DISABLE(ctx);
2355 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2356 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2357 /* Set hardware offload abilities */
2358 if_clearhwassist(ifp);
2359 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2360 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2361 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2362 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2363 if (if_getcapenable(ifp) & IFCAP_TSO4)
2364 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2365 if (if_getcapenable(ifp) & IFCAP_TSO6)
2366 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2368 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2370 callout_stop(&txq->ift_timer);
2371 CALLOUT_UNLOCK(txq);
2372 iflib_netmap_txq_init(ctx, txq);
2376 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2377 * that drivers can use the value when setting up the hardware receive
2380 iflib_calc_rx_mbuf_sz(ctx);
2383 i = if_getdrvflags(ifp);
2386 MPASS(if_getdrvflags(ifp) == i);
2387 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2388 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2389 /* This rxq is in netmap mode. Skip normal init. */
2392 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2393 if (iflib_fl_setup(fl)) {
2394 device_printf(ctx->ifc_dev,
2395 "setting up free list %d failed - "
2396 "check cluster settings\n", j);
2402 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2403 IFDI_INTR_ENABLE(ctx);
2404 txq = ctx->ifc_txqs;
2405 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2406 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2407 txq->ift_timer.c_cpu);
2411 iflib_media_change(if_t ifp)
2413 if_ctx_t ctx = if_getsoftc(ifp);
2417 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2418 iflib_init_locked(ctx);
2424 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2426 if_ctx_t ctx = if_getsoftc(ifp);
2429 IFDI_UPDATE_ADMIN_STATUS(ctx);
2430 IFDI_MEDIA_STATUS(ctx, ifmr);
2435 iflib_stop(if_ctx_t ctx)
2437 iflib_txq_t txq = ctx->ifc_txqs;
2438 iflib_rxq_t rxq = ctx->ifc_rxqs;
2439 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2440 if_shared_ctx_t sctx = ctx->ifc_sctx;
2441 iflib_dma_info_t di;
2445 /* Tell the stack that the interface is no longer active */
2446 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2448 IFDI_INTR_DISABLE(ctx);
2453 iflib_debug_reset();
2454 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2455 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2456 /* make sure all transmitters have completed before proceeding XXX */
2459 callout_stop(&txq->ift_timer);
2460 CALLOUT_UNLOCK(txq);
2462 /* clean any enqueued buffers */
2463 iflib_ifmp_purge(txq);
2464 /* Free any existing tx buffers. */
2465 for (j = 0; j < txq->ift_size; j++) {
2466 iflib_txsd_free(ctx, txq, j);
2468 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2469 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2470 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2471 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2472 txq->ift_pullups = 0;
2473 ifmp_ring_reset_stats(txq->ift_br);
2474 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2475 bzero((void *)di->idi_vaddr, di->idi_size);
2477 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2478 /* make sure all transmitters have completed before proceeding XXX */
2480 rxq->ifr_cq_cidx = 0;
2481 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2482 bzero((void *)di->idi_vaddr, di->idi_size);
2483 /* also resets the free lists pidx/cidx */
2484 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2485 iflib_fl_bufs_free(fl);
2489 static inline caddr_t
2490 calc_next_rxd(iflib_fl_t fl, int cidx)
2494 caddr_t start, end, cur, next;
2496 nrxd = fl->ifl_size;
2497 size = fl->ifl_rxd_size;
2498 start = fl->ifl_ifdi->idi_vaddr;
2500 if (__predict_false(size == 0))
2502 cur = start + size*cidx;
2503 end = start + size*nrxd;
2504 next = CACHE_PTR_NEXT(cur);
2505 return (next < end ? next : start);
2509 prefetch_pkts(iflib_fl_t fl, int cidx)
2512 int nrxd = fl->ifl_size;
2516 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2517 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2518 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2519 next_rxd = calc_next_rxd(fl, cidx);
2521 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2522 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2523 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2524 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2525 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2526 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2527 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2528 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2531 static struct mbuf *
2532 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2533 int *pf_rv, if_rxd_info_t ri)
2539 int flid, cidx, len, next;
2542 flid = irf->irf_flid;
2543 cidx = irf->irf_idx;
2544 fl = &rxq->ifr_fl[flid];
2546 m = fl->ifl_sds.ifsd_m[cidx];
2547 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2550 fl->ifl_m_dequeued++;
2552 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2553 prefetch_pkts(fl, cidx);
2554 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2555 prefetch(&fl->ifl_sds.ifsd_map[next]);
2556 map = fl->ifl_sds.ifsd_map[cidx];
2558 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2560 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2561 irf->irf_len != 0) {
2562 payload = *sd->ifsd_cl;
2563 payload += ri->iri_pad;
2564 len = ri->iri_len - ri->iri_pad;
2565 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2566 len | PFIL_MEMPTR | PFIL_IN, NULL);
2571 * The filter ate it. Everything is recycled.
2576 case PFIL_REALLOCED:
2578 * The filter copied it. Everything is recycled.
2580 m = pfil_mem2mbuf(payload);
2585 * Filter said it was OK, so receive like
2588 fl->ifl_sds.ifsd_m[cidx] = NULL;
2594 fl->ifl_sds.ifsd_m[cidx] = NULL;
2598 if (unload && irf->irf_len != 0)
2599 bus_dmamap_unload(fl->ifl_buf_tag, map);
2600 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2601 if (__predict_false(fl->ifl_cidx == 0))
2603 bit_clear(fl->ifl_rx_bitmap, cidx);
2607 static struct mbuf *
2608 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2610 struct mbuf *m, *mh, *mt;
2612 int *pf_rv_ptr, flags, i, padlen;
2621 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2624 MPASS(*sd->ifsd_cl != NULL);
2627 * Exclude zero-length frags & frags from
2628 * packets the filter has consumed or dropped
2630 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2631 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2633 /* everything saved here */
2638 /* XXX we can save the cluster here, but not the mbuf */
2639 m_init(m, M_NOWAIT, MT_DATA, 0);
2644 flags = M_PKTHDR|M_EXT;
2646 padlen = ri->iri_pad;
2651 /* assuming padding is only on the first fragment */
2655 *sd->ifsd_cl = NULL;
2657 /* Can these two be made one ? */
2658 m_init(m, M_NOWAIT, MT_DATA, flags);
2659 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2661 * These must follow m_init and m_cljset
2663 m->m_data += padlen;
2664 ri->iri_len -= padlen;
2665 m->m_len = ri->iri_frags[i].irf_len;
2666 } while (++i < ri->iri_nfrags);
2672 * Process one software descriptor
2674 static struct mbuf *
2675 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2681 /* should I merge this back in now that the two paths are basically duplicated? */
2682 if (ri->iri_nfrags == 1 &&
2683 ri->iri_frags[0].irf_len != 0 &&
2684 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2685 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2687 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2689 if (pf_rv == PFIL_PASS) {
2690 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2691 #ifndef __NO_STRICT_ALIGNMENT
2695 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2696 m->m_len = ri->iri_frags[0].irf_len;
2699 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2702 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2705 m->m_pkthdr.len = ri->iri_len;
2706 m->m_pkthdr.rcvif = ri->iri_ifp;
2707 m->m_flags |= ri->iri_flags;
2708 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2709 m->m_pkthdr.flowid = ri->iri_flowid;
2710 M_HASHTYPE_SET(m, ri->iri_rsstype);
2711 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2712 m->m_pkthdr.csum_data = ri->iri_csum_data;
2716 #if defined(INET6) || defined(INET)
2718 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2720 CURVNET_SET(lc->ifp->if_vnet);
2722 *v6 = V_ip6_forwarding;
2725 *v4 = V_ipforwarding;
2731 * Returns true if it's possible this packet could be LROed.
2732 * if it returns false, it is guaranteed that tcp_lro_rx()
2733 * would not return zero.
2736 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2738 struct ether_header *eh;
2740 eh = mtod(m, struct ether_header *);
2741 switch (eh->ether_type) {
2743 case htons(ETHERTYPE_IPV6):
2744 return (!v6_forwarding);
2747 case htons(ETHERTYPE_IP):
2748 return (!v4_forwarding);
2756 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2762 _task_fn_rx_watchdog(void *context)
2764 iflib_rxq_t rxq = context;
2766 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2770 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2773 if_ctx_t ctx = rxq->ifr_ctx;
2774 if_shared_ctx_t sctx = ctx->ifc_sctx;
2775 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2778 struct if_rxd_info ri;
2779 int err, budget_left, rx_bytes, rx_pkts;
2782 bool v4_forwarding, v6_forwarding, lro_possible;
2786 * XXX early demux data packets so that if_input processing only handles
2787 * acks in interrupt context
2789 struct mbuf *m, *mh, *mt, *mf;
2793 lro_possible = v4_forwarding = v6_forwarding = false;
2797 rx_pkts = rx_bytes = 0;
2798 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2799 cidxp = &rxq->ifr_cq_cidx;
2801 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2802 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2803 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2804 retval |= iflib_fl_refill_all(ctx, fl);
2805 DBG_COUNTER_INC(rx_unavail);
2809 /* pfil needs the vnet to be set */
2810 CURVNET_SET_QUIET(ifp->if_vnet);
2811 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2812 if (__predict_false(!CTX_ACTIVE(ctx))) {
2813 DBG_COUNTER_INC(rx_ctx_inactive);
2817 * Reset client set fields to their default values
2820 ri.iri_qsidx = rxq->ifr_id;
2821 ri.iri_cidx = *cidxp;
2823 ri.iri_frags = rxq->ifr_frags;
2824 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2829 rx_bytes += ri.iri_len;
2830 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2831 *cidxp = ri.iri_cidx;
2832 /* Update our consumer index */
2833 /* XXX NB: shurd - check if this is still safe */
2834 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2835 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2836 /* was this only a completion queue message? */
2837 if (__predict_false(ri.iri_nfrags == 0))
2840 MPASS(ri.iri_nfrags != 0);
2841 MPASS(ri.iri_len != 0);
2843 /* will advance the cidx on the corresponding free lists */
2844 m = iflib_rxd_pkt_get(rxq, &ri);
2847 if (avail == 0 && budget_left)
2848 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2850 if (__predict_false(m == NULL))
2853 /* imm_pkt: -- cxgb */
2862 /* make sure that we can refill faster than drain */
2863 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2864 retval |= iflib_fl_refill_all(ctx, fl);
2866 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2868 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2870 while (mh != NULL) {
2873 m->m_nextpkt = NULL;
2874 #ifndef __NO_STRICT_ALIGNMENT
2875 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2878 rx_bytes += m->m_pkthdr.len;
2880 #if defined(INET6) || defined(INET)
2882 if (!lro_possible) {
2883 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2884 if (lro_possible && mf != NULL) {
2885 ifp->if_input(ifp, mf);
2886 DBG_COUNTER_INC(rx_if_input);
2890 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2891 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2892 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2898 ifp->if_input(ifp, m);
2899 DBG_COUNTER_INC(rx_if_input);
2910 ifp->if_input(ifp, mf);
2911 DBG_COUNTER_INC(rx_if_input);
2914 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2915 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2918 * Flush any outstanding LRO work
2920 #if defined(INET6) || defined(INET)
2921 tcp_lro_flush_all(&rxq->ifr_lc);
2923 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2924 retval |= IFLIB_RXEOF_MORE;
2928 ctx->ifc_flags |= IFC_DO_RESET;
2929 iflib_admin_intr_deferred(ctx);
2934 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2935 static inline qidx_t
2936 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2938 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2939 qidx_t minthresh = txq->ift_size / 8;
2940 if (in_use > 4*minthresh)
2941 return (notify_count);
2942 if (in_use > 2*minthresh)
2943 return (notify_count >> 1);
2944 if (in_use > minthresh)
2945 return (notify_count >> 3);
2949 static inline qidx_t
2950 txq_max_rs_deferred(iflib_txq_t txq)
2952 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2953 qidx_t minthresh = txq->ift_size / 8;
2954 if (txq->ift_in_use > 4*minthresh)
2955 return (notify_count);
2956 if (txq->ift_in_use > 2*minthresh)
2957 return (notify_count >> 1);
2958 if (txq->ift_in_use > minthresh)
2959 return (notify_count >> 2);
2963 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2964 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2966 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2967 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2968 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2970 /* forward compatibility for cxgb */
2971 #define FIRST_QSET(ctx) 0
2972 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2973 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2974 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2975 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2977 /* XXX we should be setting this to something other than zero */
2978 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2979 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2980 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2983 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2989 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2990 if (ring || txq->ift_db_pending >= max) {
2991 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2992 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2994 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2995 txq->ift_db_pending = txq->ift_npending = 0;
3003 print_pkt(if_pkt_info_t pi)
3005 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3006 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3007 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3008 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3009 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3010 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3014 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3015 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3016 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3017 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3020 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3022 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3023 struct ether_vlan_header *eh;
3027 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3028 M_WRITABLE(m) == 0) {
3029 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3033 DBG_COUNTER_INC(tx_frees);
3039 * Determine where frame payload starts.
3040 * Jump over vlan headers if already present,
3041 * helpful for QinQ too.
3043 if (__predict_false(m->m_len < sizeof(*eh))) {
3045 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3048 eh = mtod(m, struct ether_vlan_header *);
3049 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3050 pi->ipi_etype = ntohs(eh->evl_proto);
3051 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3053 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3054 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3057 switch (pi->ipi_etype) {
3062 struct ip *ip = NULL;
3063 struct tcphdr *th = NULL;
3066 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3067 if (__predict_false(m->m_len < minthlen)) {
3069 * if this code bloat is causing too much of a hit
3070 * move it to a separate function and mark it noinline
3072 if (m->m_len == pi->ipi_ehdrlen) {
3075 if (n->m_len >= sizeof(*ip)) {
3076 ip = (struct ip *)n->m_data;
3077 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3078 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3081 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3083 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3087 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3089 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3090 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3091 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3094 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3095 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3096 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3098 pi->ipi_ip_hlen = ip->ip_hl << 2;
3099 pi->ipi_ipproto = ip->ip_p;
3100 pi->ipi_flags |= IPI_TX_IPV4;
3102 /* TCP checksum offload may require TCP header length */
3103 if (IS_TX_OFFLOAD4(pi)) {
3104 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3105 if (__predict_false(th == NULL)) {
3107 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3109 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3111 pi->ipi_tcp_hflags = th->th_flags;
3112 pi->ipi_tcp_hlen = th->th_off << 2;
3113 pi->ipi_tcp_seq = th->th_seq;
3116 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3119 * TSO always requires hardware checksum offload.
3121 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3122 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3123 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3124 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3125 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3127 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3131 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3138 case ETHERTYPE_IPV6:
3140 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3142 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3144 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3146 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3149 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3151 /* XXX-BZ this will go badly in case of ext hdrs. */
3152 pi->ipi_ipproto = ip6->ip6_nxt;
3153 pi->ipi_flags |= IPI_TX_IPV6;
3155 /* TCP checksum offload may require TCP header length */
3156 if (IS_TX_OFFLOAD6(pi)) {
3157 if (pi->ipi_ipproto == IPPROTO_TCP) {
3158 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3160 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3163 pi->ipi_tcp_hflags = th->th_flags;
3164 pi->ipi_tcp_hlen = th->th_off << 2;
3165 pi->ipi_tcp_seq = th->th_seq;
3168 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3171 * TSO always requires hardware checksum offload.
3173 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3174 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3175 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3182 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3183 pi->ipi_ip_hlen = 0;
3192 * If dodgy hardware rejects the scatter gather chain we've handed it
3193 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3196 static __noinline struct mbuf *
3197 iflib_remove_mbuf(iflib_txq_t txq)
3200 struct mbuf *m, **ifsd_m;
3202 ifsd_m = txq->ift_sds.ifsd_m;
3203 ntxd = txq->ift_size;
3204 pidx = txq->ift_pidx & (ntxd - 1);
3205 ifsd_m = txq->ift_sds.ifsd_m;
3207 ifsd_m[pidx] = NULL;
3208 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3209 if (txq->ift_sds.ifsd_tso_map != NULL)
3210 bus_dmamap_unload(txq->ift_tso_buf_tag,
3211 txq->ift_sds.ifsd_tso_map[pidx]);
3213 txq->ift_dequeued++;
3218 static inline caddr_t
3219 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3223 caddr_t start, end, cur, next;
3225 ntxd = txq->ift_size;
3226 size = txq->ift_txd_size[qid];
3227 start = txq->ift_ifdi[qid].idi_vaddr;
3229 if (__predict_false(size == 0))
3231 cur = start + size*cidx;
3232 end = start + size*ntxd;
3233 next = CACHE_PTR_NEXT(cur);
3234 return (next < end ? next : start);
3238 * Pad an mbuf to ensure a minimum ethernet frame size.
3239 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3241 static __noinline int
3242 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3245 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3246 * and ARP message is the smallest common payload I can think of
3248 static char pad[18]; /* just zeros */
3250 struct mbuf *new_head;
3252 if (!M_WRITABLE(*m_head)) {
3253 new_head = m_dup(*m_head, M_NOWAIT);
3254 if (new_head == NULL) {
3256 device_printf(dev, "cannot pad short frame, m_dup() failed");
3257 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3258 DBG_COUNTER_INC(tx_frees);
3265 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3266 n > 0; n -= sizeof(pad))
3267 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3272 device_printf(dev, "cannot pad short frame\n");
3273 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3274 DBG_COUNTER_INC(tx_frees);
3282 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3285 if_shared_ctx_t sctx;
3286 if_softc_ctx_t scctx;
3287 bus_dma_tag_t buf_tag;
3288 bus_dma_segment_t *segs;
3289 struct mbuf *m_head, **ifsd_m;
3292 struct if_pkt_info pi;
3294 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3297 sctx = ctx->ifc_sctx;
3298 scctx = &ctx->ifc_softc_ctx;
3299 segs = txq->ift_segs;
3300 ntxd = txq->ift_size;
3305 * If we're doing TSO the next descriptor to clean may be quite far ahead
3307 cidx = txq->ift_cidx;
3308 pidx = txq->ift_pidx;
3309 if (ctx->ifc_flags & IFC_PREFETCH) {
3310 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3311 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3312 next_txd = calc_next_txd(txq, cidx, 0);
3316 /* prefetch the next cache line of mbuf pointers and flags */
3317 prefetch(&txq->ift_sds.ifsd_m[next]);
3318 prefetch(&txq->ift_sds.ifsd_map[next]);
3319 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3321 map = txq->ift_sds.ifsd_map[pidx];
3322 ifsd_m = txq->ift_sds.ifsd_m;
3324 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3325 buf_tag = txq->ift_tso_buf_tag;
3326 max_segs = scctx->isc_tx_tso_segments_max;
3327 map = txq->ift_sds.ifsd_tso_map[pidx];
3328 MPASS(buf_tag != NULL);
3329 MPASS(max_segs > 0);
3331 buf_tag = txq->ift_buf_tag;
3332 max_segs = scctx->isc_tx_nsegments;
3333 map = txq->ift_sds.ifsd_map[pidx];
3335 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3336 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3337 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3339 DBG_COUNTER_INC(encap_txd_encap_fail);
3346 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3348 pi.ipi_qsidx = txq->ift_id;
3349 pi.ipi_len = m_head->m_pkthdr.len;
3350 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3351 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3353 /* deliberate bitwise OR to make one condition */
3354 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3355 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3356 DBG_COUNTER_INC(encap_txd_encap_fail);
3363 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3366 if (__predict_false(err)) {
3369 /* try collapse once and defrag once */
3371 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3372 /* try defrag if collapsing fails */
3377 txq->ift_mbuf_defrag++;
3378 m_head = m_defrag(*m_headp, M_NOWAIT);
3381 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3382 * failed to map an mbuf that was run through m_defrag
3385 if (__predict_false(m_head == NULL || remap > 1))
3392 txq->ift_no_tx_dma_setup++;
3395 txq->ift_no_tx_dma_setup++;
3397 DBG_COUNTER_INC(tx_frees);
3401 txq->ift_map_failed++;
3402 DBG_COUNTER_INC(encap_load_mbuf_fail);
3403 DBG_COUNTER_INC(encap_txd_encap_fail);
3406 ifsd_m[pidx] = m_head;
3408 * XXX assumes a 1 to 1 relationship between segments and
3409 * descriptors - this does not hold true on all drivers, e.g.
3412 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3413 txq->ift_no_desc_avail++;
3414 bus_dmamap_unload(buf_tag, map);
3415 DBG_COUNTER_INC(encap_txq_avail_fail);
3416 DBG_COUNTER_INC(encap_txd_encap_fail);
3417 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3418 GROUPTASK_ENQUEUE(&txq->ift_task);
3422 * On Intel cards we can greatly reduce the number of TX interrupts
3423 * we see by only setting report status on every Nth descriptor.
3424 * However, this also means that the driver will need to keep track
3425 * of the descriptors that RS was set on to check them for the DD bit.
3427 txq->ift_rs_pending += nsegs + 1;
3428 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3429 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3430 pi.ipi_flags |= IPI_TX_INTR;
3431 txq->ift_rs_pending = 0;
3435 pi.ipi_nsegs = nsegs;
3437 MPASS(pidx >= 0 && pidx < txq->ift_size);
3441 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3442 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3443 DBG_COUNTER_INC(tx_encap);
3444 MPASS(pi.ipi_new_pidx < txq->ift_size);
3446 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3447 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3448 ndesc += txq->ift_size;
3452 * drivers can need as many as
3455 MPASS(ndesc <= pi.ipi_nsegs + 2);
3456 MPASS(pi.ipi_new_pidx != pidx);
3458 txq->ift_in_use += ndesc;
3461 * We update the last software descriptor again here because there may
3462 * be a sentinel and/or there may be more mbufs than segments
3464 txq->ift_pidx = pi.ipi_new_pidx;
3465 txq->ift_npending += pi.ipi_ndescs;
3467 *m_headp = m_head = iflib_remove_mbuf(txq);
3469 txq->ift_txd_encap_efbig++;
3478 * err can't possibly be non-zero here, so we don't neet to test it
3479 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3484 txq->ift_mbuf_defrag_failed++;
3485 txq->ift_map_failed++;
3487 DBG_COUNTER_INC(tx_frees);
3489 DBG_COUNTER_INC(encap_txd_encap_fail);
3494 iflib_tx_desc_free(iflib_txq_t txq, int n)
3496 uint32_t qsize, cidx, mask, gen;
3497 struct mbuf *m, **ifsd_m;
3500 cidx = txq->ift_cidx;
3502 qsize = txq->ift_size;
3504 ifsd_m = txq->ift_sds.ifsd_m;
3505 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3509 prefetch(ifsd_m[(cidx + 3) & mask]);
3510 prefetch(ifsd_m[(cidx + 4) & mask]);
3512 if ((m = ifsd_m[cidx]) != NULL) {
3513 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3514 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3515 bus_dmamap_sync(txq->ift_tso_buf_tag,
3516 txq->ift_sds.ifsd_tso_map[cidx],
3517 BUS_DMASYNC_POSTWRITE);
3518 bus_dmamap_unload(txq->ift_tso_buf_tag,
3519 txq->ift_sds.ifsd_tso_map[cidx]);
3521 bus_dmamap_sync(txq->ift_buf_tag,
3522 txq->ift_sds.ifsd_map[cidx],
3523 BUS_DMASYNC_POSTWRITE);
3524 bus_dmamap_unload(txq->ift_buf_tag,
3525 txq->ift_sds.ifsd_map[cidx]);
3527 /* XXX we don't support any drivers that batch packets yet */
3528 MPASS(m->m_nextpkt == NULL);
3530 ifsd_m[cidx] = NULL;
3532 txq->ift_dequeued++;
3534 DBG_COUNTER_INC(tx_frees);
3536 if (__predict_false(++cidx == qsize)) {
3541 txq->ift_cidx = cidx;
3546 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3549 if_ctx_t ctx = txq->ift_ctx;
3551 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3552 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3555 * Need a rate-limiting check so that this isn't called every time
3557 iflib_tx_credits_update(ctx, txq);
3558 reclaim = DESC_RECLAIMABLE(txq);
3560 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3562 if (iflib_verbose_debug) {
3563 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3564 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3571 iflib_tx_desc_free(txq, reclaim);
3572 txq->ift_cleaned += reclaim;
3573 txq->ift_in_use -= reclaim;
3578 static struct mbuf **
3579 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3582 struct mbuf **items;
3585 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3586 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3588 prefetch(items[(cidx + offset) & (size-1)]);
3589 if (remaining > 1) {
3590 prefetch2cachelines(&items[next]);
3591 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3592 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3593 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3595 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3599 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3602 ifmp_ring_check_drainage(txq->ift_br, budget);
3606 iflib_txq_can_drain(struct ifmp_ring *r)
3608 iflib_txq_t txq = r->cookie;
3609 if_ctx_t ctx = txq->ift_ctx;
3611 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3613 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3614 BUS_DMASYNC_POSTREAD);
3615 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3620 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3622 iflib_txq_t txq = r->cookie;
3623 if_ctx_t ctx = txq->ift_ctx;
3624 if_t ifp = ctx->ifc_ifp;
3625 struct mbuf *m, **mp;
3626 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3627 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3628 bool do_prefetch, rang, ring;
3630 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3631 !LINK_ACTIVE(ctx))) {
3632 DBG_COUNTER_INC(txq_drain_notready);
3635 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3636 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3637 avail = IDXDIFF(pidx, cidx, r->size);
3638 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3639 DBG_COUNTER_INC(txq_drain_flushing);
3640 for (i = 0; i < avail; i++) {
3641 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3642 m_free(r->items[(cidx + i) & (r->size-1)]);
3643 r->items[(cidx + i) & (r->size-1)] = NULL;
3648 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3649 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3651 callout_stop(&txq->ift_timer);
3652 CALLOUT_UNLOCK(txq);
3653 DBG_COUNTER_INC(txq_drain_oactive);
3657 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3658 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3659 count = MIN(avail, TX_BATCH_SIZE);
3661 if (iflib_verbose_debug)
3662 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3663 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3665 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3666 txq_avail = TXQ_AVAIL(txq);
3668 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3669 int rem = do_prefetch ? count - i : 0;
3671 mp = _ring_peek_one(r, cidx, i, rem);
3672 MPASS(mp != NULL && *mp != NULL);
3673 if (__predict_false(*mp == (struct mbuf *)txq)) {
3677 in_use_prev = txq->ift_in_use;
3678 err = iflib_encap(txq, mp);
3679 if (__predict_false(err)) {
3680 /* no room - bail out */
3684 /* we can't send this packet - skip it */
3690 DBG_COUNTER_INC(tx_sent);
3691 bytes_sent += m->m_pkthdr.len;
3692 mcast_sent += !!(m->m_flags & M_MCAST);
3693 txq_avail = TXQ_AVAIL(txq);
3695 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3696 ETHER_BPF_MTAP(ifp, m);
3697 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3699 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3702 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3703 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3704 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3705 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3706 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3708 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3710 if (iflib_verbose_debug)
3711 printf("consumed=%d\n", consumed);
3717 iflib_txq_drain_always(struct ifmp_ring *r)
3723 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3731 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3733 callout_stop(&txq->ift_timer);
3734 CALLOUT_UNLOCK(txq);
3736 avail = IDXDIFF(pidx, cidx, r->size);
3737 for (i = 0; i < avail; i++) {
3738 mp = _ring_peek_one(r, cidx, i, avail - i);
3739 if (__predict_false(*mp == (struct mbuf *)txq))
3742 DBG_COUNTER_INC(tx_frees);
3744 MPASS(ifmp_ring_is_stalled(r) == 0);
3749 iflib_ifmp_purge(iflib_txq_t txq)
3751 struct ifmp_ring *r;
3754 r->drain = iflib_txq_drain_free;
3755 r->can_drain = iflib_txq_drain_always;
3757 ifmp_ring_check_drainage(r, r->size);
3759 r->drain = iflib_txq_drain;
3760 r->can_drain = iflib_txq_can_drain;
3764 _task_fn_tx(void *context)
3766 iflib_txq_t txq = context;
3767 if_ctx_t ctx = txq->ift_ctx;
3768 if_t ifp = ctx->ifc_ifp;
3769 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3771 #ifdef IFLIB_DIAGNOSTICS
3772 txq->ift_cpu_exec_count[curcpu]++;
3774 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3777 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3778 netmap_tx_irq(ifp, txq->ift_id))
3782 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3783 iflib_altq_if_start(ifp);
3785 if (txq->ift_db_pending)
3786 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3788 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3790 * When abdicating, we always need to check drainage, not just when we don't enqueue
3793 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3797 if (ctx->ifc_flags & IFC_LEGACY)
3798 IFDI_INTR_ENABLE(ctx);
3800 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3804 _task_fn_rx(void *context)
3806 iflib_rxq_t rxq = context;
3807 if_ctx_t ctx = rxq->ifr_ctx;
3815 #ifdef IFLIB_DIAGNOSTICS
3816 rxq->ifr_cpu_exec_count[curcpu]++;
3818 DBG_COUNTER_INC(task_fn_rxs);
3819 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3822 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3823 if (nmirq != NM_IRQ_PASS) {
3824 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3828 budget = ctx->ifc_sysctl_rx_budget;
3830 budget = 16; /* XXX */
3831 more = iflib_rxeof(rxq, budget);
3835 if ((more & IFLIB_RXEOF_MORE) == 0) {
3836 if (ctx->ifc_flags & IFC_LEGACY)
3837 IFDI_INTR_ENABLE(ctx);
3839 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3840 DBG_COUNTER_INC(rx_intr_enables);
3842 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3845 if (more & IFLIB_RXEOF_MORE)
3846 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3847 else if (more & IFLIB_RXEOF_EMPTY)
3848 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3852 _task_fn_admin(void *context)
3854 if_ctx_t ctx = context;
3855 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3858 bool oactive, running, do_reset, do_watchdog, in_detach;
3859 uint32_t reset_on = hz / 2;
3862 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3863 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3864 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3865 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3866 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3867 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3870 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3876 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3878 callout_stop(&txq->ift_timer);
3879 CALLOUT_UNLOCK(txq);
3882 ctx->ifc_watchdog_events++;
3883 IFDI_WATCHDOG_RESET(ctx);
3885 IFDI_UPDATE_ADMIN_STATUS(ctx);
3886 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3889 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3890 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3892 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3894 IFDI_LINK_INTR_ENABLE(ctx);
3896 iflib_if_init_locked(ctx);
3899 if (LINK_ACTIVE(ctx) == 0)
3901 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3902 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3907 _task_fn_iov(void *context)
3909 if_ctx_t ctx = context;
3911 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3912 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3916 IFDI_VFLR_HANDLE(ctx);
3921 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3924 if_int_delay_info_t info;
3927 info = (if_int_delay_info_t)arg1;
3928 ctx = info->iidi_ctx;
3929 info->iidi_req = req;
3930 info->iidi_oidp = oidp;
3932 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3937 /*********************************************************************
3941 **********************************************************************/
3944 iflib_if_init_locked(if_ctx_t ctx)
3947 iflib_init_locked(ctx);
3952 iflib_if_init(void *arg)
3957 iflib_if_init_locked(ctx);
3962 iflib_if_transmit(if_t ifp, struct mbuf *m)
3964 if_ctx_t ctx = if_getsoftc(ifp);
3968 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3970 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3971 DBG_COUNTER_INC(tx_frees);
3976 MPASS(m->m_nextpkt == NULL);
3977 /* ALTQ-enabled interfaces always use queue 0. */
3979 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3980 qidx = QIDX(ctx, m);
3982 * XXX calculate buf_ring based on flowid (divvy up bits?)
3984 txq = &ctx->ifc_txqs[qidx];
3986 #ifdef DRIVER_BACKPRESSURE
3987 if (txq->ift_closed) {
3989 next = m->m_nextpkt;
3990 m->m_nextpkt = NULL;
3992 DBG_COUNTER_INC(tx_frees);
4004 next = next->m_nextpkt;
4005 } while (next != NULL);
4007 if (count > nitems(marr))
4008 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4009 /* XXX check nextpkt */
4011 /* XXX simplify for now */
4012 DBG_COUNTER_INC(tx_frees);
4015 for (next = m, i = 0; next != NULL; i++) {
4017 next = next->m_nextpkt;
4018 mp[i]->m_nextpkt = NULL;
4021 DBG_COUNTER_INC(tx_seen);
4022 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4025 GROUPTASK_ENQUEUE(&txq->ift_task);
4028 GROUPTASK_ENQUEUE(&txq->ift_task);
4029 /* support forthcoming later */
4030 #ifdef DRIVER_BACKPRESSURE
4031 txq->ift_closed = TRUE;
4033 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4035 DBG_COUNTER_INC(tx_frees);
4043 * The overall approach to integrating iflib with ALTQ is to continue to use
4044 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4045 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4046 * is redundant/unnecessary, but doing so minimizes the amount of
4047 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4048 * redundantly queueing to an intermediate mp_ring is swamped by the
4049 * performance limitations inherent in using ALTQ.
4051 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4052 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4053 * given interface. If ALTQ is enabled for an interface, then all
4054 * transmitted packets for that interface will be submitted to the ALTQ
4055 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4056 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4057 * update stats that the iflib machinery handles, and which is sensitve to
4058 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4059 * will be installed as the start routine for use by ALTQ facilities that
4060 * need to trigger queue drains on a scheduled basis.
4064 iflib_altq_if_start(if_t ifp)
4066 struct ifaltq *ifq = &ifp->if_snd;
4070 IFQ_DEQUEUE_NOLOCK(ifq, m);
4072 iflib_if_transmit(ifp, m);
4073 IFQ_DEQUEUE_NOLOCK(ifq, m);
4079 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4083 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4084 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4086 iflib_altq_if_start(ifp);
4088 err = iflib_if_transmit(ifp, m);
4095 iflib_if_qflush(if_t ifp)
4097 if_ctx_t ctx = if_getsoftc(ifp);
4098 iflib_txq_t txq = ctx->ifc_txqs;
4102 ctx->ifc_flags |= IFC_QFLUSH;
4104 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4105 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4106 iflib_txq_check_drain(txq, 0);
4108 ctx->ifc_flags &= ~IFC_QFLUSH;
4112 * When ALTQ is enabled, this will also take care of purging the
4119 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4120 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4121 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4122 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4125 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4127 if_ctx_t ctx = if_getsoftc(ifp);
4128 struct ifreq *ifr = (struct ifreq *)data;
4129 #if defined(INET) || defined(INET6)
4130 struct ifaddr *ifa = (struct ifaddr *)data;
4132 bool avoid_reset = false;
4133 int err = 0, reinit = 0, bits;
4138 if (ifa->ifa_addr->sa_family == AF_INET)
4142 if (ifa->ifa_addr->sa_family == AF_INET6)
4146 ** Calling init results in link renegotiation,
4147 ** so we avoid doing it when possible.
4150 if_setflagbits(ifp, IFF_UP,0);
4151 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4154 if (!(if_getflags(ifp) & IFF_NOARP))
4155 arp_ifinit(ifp, ifa);
4158 err = ether_ioctl(ifp, command, data);
4162 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4166 bits = if_getdrvflags(ifp);
4167 /* stop the driver and free any clusters before proceeding */
4170 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4172 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4173 ctx->ifc_flags |= IFC_MULTISEG;
4175 ctx->ifc_flags &= ~IFC_MULTISEG;
4177 err = if_setmtu(ifp, ifr->ifr_mtu);
4179 iflib_init_locked(ctx);
4181 if_setdrvflags(ifp, bits);
4187 if (if_getflags(ifp) & IFF_UP) {
4188 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4189 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4190 (IFF_PROMISC | IFF_ALLMULTI)) {
4192 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4197 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4200 ctx->ifc_if_flags = if_getflags(ifp);
4205 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4207 IFDI_INTR_DISABLE(ctx);
4208 IFDI_MULTI_SET(ctx);
4209 IFDI_INTR_ENABLE(ctx);
4215 IFDI_MEDIA_SET(ctx);
4220 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4224 struct ifi2creq i2c;
4226 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4229 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4233 if (i2c.len > sizeof(i2c.data)) {
4238 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4239 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4245 int mask, setmask, oldmask;
4247 oldmask = if_getcapenable(ifp);
4248 mask = ifr->ifr_reqcap ^ oldmask;
4249 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4252 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4254 setmask |= (mask & IFCAP_FLAGS);
4255 setmask |= (mask & IFCAP_WOL);
4258 * If any RX csum has changed, change all the ones that
4259 * are supported by the driver.
4261 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4262 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4263 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4267 * want to ensure that traffic has stopped before we change any of the flags
4271 bits = if_getdrvflags(ifp);
4272 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4275 if_togglecapenable(ifp, setmask);
4277 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4278 iflib_init_locked(ctx);
4280 if_setdrvflags(ifp, bits);
4287 case SIOCGPRIVATE_0:
4291 err = IFDI_PRIV_IOCTL(ctx, command, data);
4295 err = ether_ioctl(ifp, command, data);
4304 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4306 if_ctx_t ctx = if_getsoftc(ifp);
4308 return (IFDI_GET_COUNTER(ctx, cnt));
4311 /*********************************************************************
4313 * OTHER FUNCTIONS EXPORTED TO THE STACK
4315 **********************************************************************/
4318 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4320 if_ctx_t ctx = if_getsoftc(ifp);
4322 if ((void *)ctx != arg)
4325 if ((vtag == 0) || (vtag > 4095))
4328 if (iflib_in_detach(ctx))
4332 /* Driver may need all untagged packets to be flushed */
4333 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4335 IFDI_VLAN_REGISTER(ctx, vtag);
4336 /* Re-init to load the changes, if required */
4337 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4338 iflib_init_locked(ctx);
4343 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4345 if_ctx_t ctx = if_getsoftc(ifp);
4347 if ((void *)ctx != arg)
4350 if ((vtag == 0) || (vtag > 4095))
4354 /* Driver may need all tagged packets to be flushed */
4355 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4357 IFDI_VLAN_UNREGISTER(ctx, vtag);
4358 /* Re-init to load the changes, if required */
4359 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4360 iflib_init_locked(ctx);
4365 iflib_led_func(void *arg, int onoff)
4370 IFDI_LED_FUNC(ctx, onoff);
4374 /*********************************************************************
4376 * BUS FUNCTION DEFINITIONS
4378 **********************************************************************/
4381 iflib_device_probe(device_t dev)
4383 const pci_vendor_info_t *ent;
4384 if_shared_ctx_t sctx;
4385 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4386 uint16_t pci_vendor_id;
4388 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4391 pci_vendor_id = pci_get_vendor(dev);
4392 pci_device_id = pci_get_device(dev);
4393 pci_subvendor_id = pci_get_subvendor(dev);
4394 pci_subdevice_id = pci_get_subdevice(dev);
4395 pci_rev_id = pci_get_revid(dev);
4396 if (sctx->isc_parse_devinfo != NULL)
4397 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4399 ent = sctx->isc_vendor_info;
4400 while (ent->pvi_vendor_id != 0) {
4401 if (pci_vendor_id != ent->pvi_vendor_id) {
4405 if ((pci_device_id == ent->pvi_device_id) &&
4406 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4407 (ent->pvi_subvendor_id == 0)) &&
4408 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4409 (ent->pvi_subdevice_id == 0)) &&
4410 ((pci_rev_id == ent->pvi_rev_id) ||
4411 (ent->pvi_rev_id == 0))) {
4413 device_set_desc_copy(dev, ent->pvi_name);
4414 /* this needs to be changed to zero if the bus probing code
4415 * ever stops re-probing on best match because the sctx
4416 * may have its values over written by register calls
4417 * in subsequent probes
4419 return (BUS_PROBE_DEFAULT);
4427 iflib_device_probe_vendor(device_t dev)
4431 probe = iflib_device_probe(dev);
4432 if (probe == BUS_PROBE_DEFAULT)
4433 return (BUS_PROBE_VENDOR);
4439 iflib_reset_qvalues(if_ctx_t ctx)
4441 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4442 if_shared_ctx_t sctx = ctx->ifc_sctx;
4443 device_t dev = ctx->ifc_dev;
4446 if (ctx->ifc_sysctl_ntxqs != 0)
4447 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4448 if (ctx->ifc_sysctl_nrxqs != 0)
4449 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4451 for (i = 0; i < sctx->isc_ntxqs; i++) {
4452 if (ctx->ifc_sysctl_ntxds[i] != 0)
4453 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4455 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4458 for (i = 0; i < sctx->isc_nrxqs; i++) {
4459 if (ctx->ifc_sysctl_nrxds[i] != 0)
4460 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4462 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4465 for (i = 0; i < sctx->isc_nrxqs; i++) {
4466 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4467 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4468 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4469 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4471 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4472 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4473 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4474 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4476 if (!powerof2(scctx->isc_nrxd[i])) {
4477 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4478 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4479 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4483 for (i = 0; i < sctx->isc_ntxqs; i++) {
4484 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4485 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4486 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4487 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4489 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4490 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4491 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4492 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4494 if (!powerof2(scctx->isc_ntxd[i])) {
4495 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4496 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4497 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4503 iflib_add_pfil(if_ctx_t ctx)
4505 struct pfil_head *pfil;
4506 struct pfil_head_args pa;
4510 pa.pa_version = PFIL_VERSION;
4511 pa.pa_flags = PFIL_IN;
4512 pa.pa_type = PFIL_TYPE_ETHERNET;
4513 pa.pa_headname = ctx->ifc_ifp->if_xname;
4514 pfil = pfil_head_register(&pa);
4516 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4522 iflib_rem_pfil(if_ctx_t ctx)
4524 struct pfil_head *pfil;
4528 rxq = ctx->ifc_rxqs;
4530 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4533 pfil_head_unregister(pfil);
4537 get_ctx_core_offset(if_ctx_t ctx)
4539 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4540 struct cpu_offset *op;
4542 uint16_t ret = ctx->ifc_sysctl_core_offset;
4544 if (ret != CORE_OFFSET_UNSPECIFIED)
4547 if (ctx->ifc_sysctl_separate_txrx)
4548 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4550 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4552 mtx_lock(&cpu_offset_mtx);
4553 SLIST_FOREACH(op, &cpu_offsets, entries) {
4554 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4557 MPASS(op->refcount < UINT_MAX);
4562 if (ret == CORE_OFFSET_UNSPECIFIED) {
4564 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4567 device_printf(ctx->ifc_dev,
4568 "allocation for cpu offset failed.\n");
4572 CPU_COPY(&ctx->ifc_cpus, &op->set);
4573 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4576 mtx_unlock(&cpu_offset_mtx);
4582 unref_ctx_core_offset(if_ctx_t ctx)
4584 struct cpu_offset *op, *top;
4586 mtx_lock(&cpu_offset_mtx);
4587 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4588 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4589 MPASS(op->refcount > 0);
4591 if (op->refcount == 0) {
4592 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4598 mtx_unlock(&cpu_offset_mtx);
4602 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4606 if_softc_ctx_t scctx;
4607 kobjop_desc_t kobj_desc;
4608 kobj_method_t *kobj_method;
4610 int num_txd, num_rxd;
4612 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4615 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4616 device_set_softc(dev, ctx);
4617 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4620 ctx->ifc_sctx = sctx;
4622 ctx->ifc_softc = sc;
4624 if ((err = iflib_register(ctx)) != 0) {
4625 device_printf(dev, "iflib_register failed %d\n", err);
4628 iflib_add_device_sysctl_pre(ctx);
4630 scctx = &ctx->ifc_softc_ctx;
4633 iflib_reset_qvalues(ctx);
4635 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4636 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4639 _iflib_pre_assert(scctx);
4640 ctx->ifc_txrx = *scctx->isc_txrx;
4642 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4643 ctx->ifc_mediap = scctx->isc_media;
4646 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4647 MPASS(scctx->isc_tx_csum_flags);
4650 if_setcapabilities(ifp,
4651 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4652 if_setcapenable(ifp,
4653 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4655 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4656 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4657 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4658 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4660 num_txd = iflib_num_tx_descs(ctx);
4661 num_rxd = iflib_num_rx_descs(ctx);
4663 /* XXX change for per-queue sizes */
4664 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4667 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4668 scctx->isc_tx_nsegments = max(1, num_txd /
4669 MAX_SINGLE_PACKET_FRACTION);
4670 if (scctx->isc_tx_tso_segments_max > num_txd /
4671 MAX_SINGLE_PACKET_FRACTION)
4672 scctx->isc_tx_tso_segments_max = max(1,
4673 num_txd / MAX_SINGLE_PACKET_FRACTION);
4675 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4676 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4678 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4681 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4684 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4685 * into account. In the worst case, each of these calls will
4686 * add another mbuf and, thus, the requirement for another DMA
4687 * segment. So for best performance, it doesn't make sense to
4688 * advertize a maximum of TSO segments that typically will
4689 * require defragmentation in iflib_encap().
4691 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4692 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4694 if (scctx->isc_rss_table_size == 0)
4695 scctx->isc_rss_table_size = 64;
4696 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4698 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4699 /* XXX format name */
4700 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4701 NULL, NULL, "admin");
4703 /* Set up cpu set. If it fails, use the set of all CPUs. */
4704 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4705 device_printf(dev, "Unable to fetch CPU list\n");
4706 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4708 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4711 ** Now set up MSI or MSI-X, should return us the number of supported
4712 ** vectors (will be 1 for a legacy interrupt and MSI).
4714 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4715 msix = scctx->isc_vectors;
4716 } else if (scctx->isc_msix_bar != 0)
4718 * The simple fact that isc_msix_bar is not 0 does not mean we
4719 * we have a good value there that is known to work.
4721 msix = iflib_msix_init(ctx);
4723 scctx->isc_vectors = 1;
4724 scctx->isc_ntxqsets = 1;
4725 scctx->isc_nrxqsets = 1;
4726 scctx->isc_intr = IFLIB_INTR_LEGACY;
4729 /* Get memory for the station queues */
4730 if ((err = iflib_queues_alloc(ctx))) {
4731 device_printf(dev, "Unable to allocate queue memory\n");
4732 goto fail_intr_free;
4735 if ((err = iflib_qset_structures_setup(ctx)))
4739 * Now that we know how many queues there are, get the core offset.
4741 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4745 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4746 * aren't the default NULL implementation.
4748 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4749 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4751 if (kobj_method == &kobj_desc->deflt) {
4753 "MSI-X requires ifdi_rx_queue_intr_enable method");
4757 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4758 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4760 if (kobj_method == &kobj_desc->deflt) {
4762 "MSI-X requires ifdi_tx_queue_intr_enable method");
4768 * Assign the MSI-X vectors.
4769 * Note that the default NULL ifdi_msix_intr_assign method will
4772 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4774 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4778 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4780 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4784 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4785 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4790 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4792 goto fail_intr_free;
4795 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4797 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4798 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4803 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4804 * This must appear after the call to ether_ifattach() because
4805 * ether_ifattach() sets if_hdrlen to the default value.
4807 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4808 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4810 if ((err = iflib_netmap_attach(ctx))) {
4811 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4816 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4818 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4819 iflib_add_device_sysctl_post(ctx);
4820 iflib_add_pfil(ctx);
4821 ctx->ifc_flags |= IFC_INIT_DONE;
4827 ether_ifdetach(ctx->ifc_ifp);
4829 iflib_free_intr_mem(ctx);
4831 iflib_tx_structures_free(ctx);
4832 iflib_rx_structures_free(ctx);
4833 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4837 iflib_deregister(ctx);
4839 device_set_softc(ctx->ifc_dev, NULL);
4840 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4841 free(ctx->ifc_softc, M_IFLIB);
4847 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4848 struct iflib_cloneattach_ctx *clctx)
4850 int num_txd, num_rxd;
4854 if_softc_ctx_t scctx;
4858 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4859 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4860 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4861 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4862 ctx->ifc_flags |= IFC_PSEUDO;
4864 ctx->ifc_sctx = sctx;
4865 ctx->ifc_softc = sc;
4868 if ((err = iflib_register(ctx)) != 0) {
4869 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4872 iflib_add_device_sysctl_pre(ctx);
4874 scctx = &ctx->ifc_softc_ctx;
4877 iflib_reset_qvalues(ctx);
4879 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4880 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4883 if (sctx->isc_flags & IFLIB_GEN_MAC)
4884 ether_gen_addr(ifp, &ctx->ifc_mac);
4885 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4886 clctx->cc_params)) != 0) {
4887 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4891 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4892 MPASS(scctx->isc_tx_csum_flags);
4895 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4896 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4898 ifp->if_flags |= IFF_NOGROUP;
4899 if (sctx->isc_flags & IFLIB_PSEUDO) {
4900 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4901 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4902 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4903 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4905 if_attach(ctx->ifc_ifp);
4906 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4909 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4910 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4916 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4917 * This must appear after the call to ether_ifattach() because
4918 * ether_ifattach() sets if_hdrlen to the default value.
4920 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4921 if_setifheaderlen(ifp,
4922 sizeof(struct ether_vlan_header));
4924 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4925 iflib_add_device_sysctl_post(ctx);
4926 ctx->ifc_flags |= IFC_INIT_DONE;
4930 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4931 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4932 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4934 _iflib_pre_assert(scctx);
4935 ctx->ifc_txrx = *scctx->isc_txrx;
4937 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4938 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4939 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4940 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4942 num_txd = iflib_num_tx_descs(ctx);
4943 num_rxd = iflib_num_rx_descs(ctx);
4945 /* XXX change for per-queue sizes */
4946 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4949 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4950 scctx->isc_tx_nsegments = max(1, num_txd /
4951 MAX_SINGLE_PACKET_FRACTION);
4952 if (scctx->isc_tx_tso_segments_max > num_txd /
4953 MAX_SINGLE_PACKET_FRACTION)
4954 scctx->isc_tx_tso_segments_max = max(1,
4955 num_txd / MAX_SINGLE_PACKET_FRACTION);
4957 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4958 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4960 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4963 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4966 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4967 * into account. In the worst case, each of these calls will
4968 * add another mbuf and, thus, the requirement for another DMA
4969 * segment. So for best performance, it doesn't make sense to
4970 * advertize a maximum of TSO segments that typically will
4971 * require defragmentation in iflib_encap().
4973 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4974 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4976 if (scctx->isc_rss_table_size == 0)
4977 scctx->isc_rss_table_size = 64;
4978 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4980 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4981 /* XXX format name */
4982 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4983 NULL, NULL, "admin");
4985 /* XXX --- can support > 1 -- but keep it simple for now */
4986 scctx->isc_intr = IFLIB_INTR_LEGACY;
4988 /* Get memory for the station queues */
4989 if ((err = iflib_queues_alloc(ctx))) {
4990 device_printf(dev, "Unable to allocate queue memory\n");
4991 goto fail_iflib_detach;
4994 if ((err = iflib_qset_structures_setup(ctx))) {
4995 device_printf(dev, "qset structure setup failed %d\n", err);
5000 * XXX What if anything do we want to do about interrupts?
5002 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5003 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5004 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5009 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5010 * This must appear after the call to ether_ifattach() because
5011 * ether_ifattach() sets if_hdrlen to the default value.
5013 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5014 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5016 /* XXX handle more than one queue */
5017 for (i = 0; i < scctx->isc_nrxqsets; i++)
5018 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5022 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5023 iflib_add_device_sysctl_post(ctx);
5024 ctx->ifc_flags |= IFC_INIT_DONE;
5029 ether_ifdetach(ctx->ifc_ifp);
5031 iflib_tx_structures_free(ctx);
5032 iflib_rx_structures_free(ctx);
5037 iflib_deregister(ctx);
5039 free(ctx->ifc_softc, M_IFLIB);
5045 iflib_pseudo_deregister(if_ctx_t ctx)
5047 if_t ifp = ctx->ifc_ifp;
5048 if_shared_ctx_t sctx = ctx->ifc_sctx;
5052 struct taskqgroup *tqg;
5055 /* Unregister VLAN event handlers early */
5056 iflib_unregister_vlan_handlers(ctx);
5058 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5059 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5063 ether_ifdetach(ifp);
5065 /* XXX drain any dependent tasks */
5066 tqg = qgroup_if_io_tqg;
5067 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5068 callout_drain(&txq->ift_timer);
5069 if (txq->ift_task.gt_uniq != NULL)
5070 taskqgroup_detach(tqg, &txq->ift_task);
5072 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5073 callout_drain(&rxq->ifr_watchdog);
5074 if (rxq->ifr_task.gt_uniq != NULL)
5075 taskqgroup_detach(tqg, &rxq->ifr_task);
5077 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5078 free(fl->ifl_rx_bitmap, M_IFLIB);
5080 tqg = qgroup_if_config_tqg;
5081 if (ctx->ifc_admin_task.gt_uniq != NULL)
5082 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5083 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5084 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5086 iflib_tx_structures_free(ctx);
5087 iflib_rx_structures_free(ctx);
5089 iflib_deregister(ctx);
5091 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5092 free(ctx->ifc_softc, M_IFLIB);
5098 iflib_device_attach(device_t dev)
5101 if_shared_ctx_t sctx;
5103 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5106 pci_enable_busmaster(dev);
5108 return (iflib_device_register(dev, NULL, sctx, &ctx));
5112 iflib_device_deregister(if_ctx_t ctx)
5114 if_t ifp = ctx->ifc_ifp;
5117 device_t dev = ctx->ifc_dev;
5119 struct taskqgroup *tqg;
5122 /* Make sure VLANS are not using driver */
5123 if (if_vlantrunkinuse(ifp)) {
5124 device_printf(dev, "Vlan in use, detach first\n");
5128 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5129 device_printf(dev, "SR-IOV in use; detach first.\n");
5135 ctx->ifc_flags |= IFC_IN_DETACH;
5138 /* Unregister VLAN handlers before calling iflib_stop() */
5139 iflib_unregister_vlan_handlers(ctx);
5141 iflib_netmap_detach(ifp);
5142 ether_ifdetach(ifp);
5148 iflib_rem_pfil(ctx);
5149 if (ctx->ifc_led_dev != NULL)
5150 led_destroy(ctx->ifc_led_dev);
5151 /* XXX drain any dependent tasks */
5152 tqg = qgroup_if_io_tqg;
5153 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5154 callout_drain(&txq->ift_timer);
5155 if (txq->ift_task.gt_uniq != NULL)
5156 taskqgroup_detach(tqg, &txq->ift_task);
5158 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5159 if (rxq->ifr_task.gt_uniq != NULL)
5160 taskqgroup_detach(tqg, &rxq->ifr_task);
5162 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5163 free(fl->ifl_rx_bitmap, M_IFLIB);
5165 tqg = qgroup_if_config_tqg;
5166 if (ctx->ifc_admin_task.gt_uniq != NULL)
5167 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5168 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5169 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5174 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5175 iflib_free_intr_mem(ctx);
5177 bus_generic_detach(dev);
5179 iflib_tx_structures_free(ctx);
5180 iflib_rx_structures_free(ctx);
5182 iflib_deregister(ctx);
5184 device_set_softc(ctx->ifc_dev, NULL);
5185 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5186 free(ctx->ifc_softc, M_IFLIB);
5187 unref_ctx_core_offset(ctx);
5193 iflib_free_intr_mem(if_ctx_t ctx)
5196 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5197 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5199 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5200 pci_release_msi(ctx->ifc_dev);
5202 if (ctx->ifc_msix_mem != NULL) {
5203 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5204 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5205 ctx->ifc_msix_mem = NULL;
5210 iflib_device_detach(device_t dev)
5212 if_ctx_t ctx = device_get_softc(dev);
5214 return (iflib_device_deregister(ctx));
5218 iflib_device_suspend(device_t dev)
5220 if_ctx_t ctx = device_get_softc(dev);
5226 return bus_generic_suspend(dev);
5229 iflib_device_shutdown(device_t dev)
5231 if_ctx_t ctx = device_get_softc(dev);
5237 return bus_generic_suspend(dev);
5242 iflib_device_resume(device_t dev)
5244 if_ctx_t ctx = device_get_softc(dev);
5245 iflib_txq_t txq = ctx->ifc_txqs;
5249 iflib_if_init_locked(ctx);
5251 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5252 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5254 return (bus_generic_resume(dev));
5258 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5261 if_ctx_t ctx = device_get_softc(dev);
5264 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5271 iflib_device_iov_uninit(device_t dev)
5273 if_ctx_t ctx = device_get_softc(dev);
5276 IFDI_IOV_UNINIT(ctx);
5281 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5284 if_ctx_t ctx = device_get_softc(dev);
5287 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5293 /*********************************************************************
5295 * MODULE FUNCTION DEFINITIONS
5297 **********************************************************************/
5300 * - Start a fast taskqueue thread for each core
5301 * - Start a taskqueue for control operations
5304 iflib_module_init(void)
5310 iflib_module_event_handler(module_t mod, int what, void *arg)
5316 if ((err = iflib_module_init()) != 0)
5322 return (EOPNOTSUPP);
5328 /*********************************************************************
5330 * PUBLIC FUNCTION DEFINITIONS
5331 * ordered as in iflib.h
5333 **********************************************************************/
5337 _iflib_assert(if_shared_ctx_t sctx)
5341 MPASS(sctx->isc_tx_maxsize);
5342 MPASS(sctx->isc_tx_maxsegsize);
5344 MPASS(sctx->isc_rx_maxsize);
5345 MPASS(sctx->isc_rx_nsegments);
5346 MPASS(sctx->isc_rx_maxsegsize);
5348 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5349 for (i = 0; i < sctx->isc_nrxqs; i++) {
5350 MPASS(sctx->isc_nrxd_min[i]);
5351 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5352 MPASS(sctx->isc_nrxd_max[i]);
5353 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5354 MPASS(sctx->isc_nrxd_default[i]);
5355 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5358 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5359 for (i = 0; i < sctx->isc_ntxqs; i++) {
5360 MPASS(sctx->isc_ntxd_min[i]);
5361 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5362 MPASS(sctx->isc_ntxd_max[i]);
5363 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5364 MPASS(sctx->isc_ntxd_default[i]);
5365 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5370 _iflib_pre_assert(if_softc_ctx_t scctx)
5373 MPASS(scctx->isc_txrx->ift_txd_encap);
5374 MPASS(scctx->isc_txrx->ift_txd_flush);
5375 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5376 MPASS(scctx->isc_txrx->ift_rxd_available);
5377 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5378 MPASS(scctx->isc_txrx->ift_rxd_refill);
5379 MPASS(scctx->isc_txrx->ift_rxd_flush);
5383 iflib_register(if_ctx_t ctx)
5385 if_shared_ctx_t sctx = ctx->ifc_sctx;
5386 driver_t *driver = sctx->isc_driver;
5387 device_t dev = ctx->ifc_dev;
5392 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5393 _iflib_assert(sctx);
5396 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5397 if (sctx->isc_flags & IFLIB_PSEUDO) {
5398 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5404 ifp = ctx->ifc_ifp = if_alloc(type);
5406 device_printf(dev, "can not allocate ifnet structure\n");
5411 * Initialize our context's device specific methods
5413 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5414 kobj_class_compile((kobj_class_t) driver);
5416 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5417 if_setsoftc(ifp, ctx);
5418 if_setdev(ifp, dev);
5419 if_setinitfn(ifp, iflib_if_init);
5420 if_setioctlfn(ifp, iflib_if_ioctl);
5422 if_setstartfn(ifp, iflib_altq_if_start);
5423 if_settransmitfn(ifp, iflib_altq_if_transmit);
5424 if_setsendqready(ifp);
5426 if_settransmitfn(ifp, iflib_if_transmit);
5428 if_setqflushfn(ifp, iflib_if_qflush);
5429 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5431 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5432 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5433 iflags |= IFF_POINTOPOINT;
5435 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5436 if_setflags(ifp, iflags);
5437 ctx->ifc_vlan_attach_event =
5438 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5439 EVENTHANDLER_PRI_FIRST);
5440 ctx->ifc_vlan_detach_event =
5441 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5442 EVENTHANDLER_PRI_FIRST);
5444 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5445 ctx->ifc_mediap = &ctx->ifc_media;
5446 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5447 iflib_media_change, iflib_media_status);
5453 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5455 /* Unregister VLAN events */
5456 if (ctx->ifc_vlan_attach_event != NULL) {
5457 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5458 ctx->ifc_vlan_attach_event = NULL;
5460 if (ctx->ifc_vlan_detach_event != NULL) {
5461 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5462 ctx->ifc_vlan_detach_event = NULL;
5468 iflib_deregister(if_ctx_t ctx)
5470 if_t ifp = ctx->ifc_ifp;
5472 /* Remove all media */
5473 ifmedia_removeall(&ctx->ifc_media);
5475 /* Ensure that VLAN event handlers are unregistered */
5476 iflib_unregister_vlan_handlers(ctx);
5478 /* Release kobject reference */
5479 kobj_delete((kobj_t) ctx, NULL);
5481 /* Free the ifnet structure */
5484 STATE_LOCK_DESTROY(ctx);
5486 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5487 CTX_LOCK_DESTROY(ctx);
5491 iflib_queues_alloc(if_ctx_t ctx)
5493 if_shared_ctx_t sctx = ctx->ifc_sctx;
5494 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5495 device_t dev = ctx->ifc_dev;
5496 int nrxqsets = scctx->isc_nrxqsets;
5497 int ntxqsets = scctx->isc_ntxqsets;
5500 iflib_fl_t fl = NULL;
5501 int i, j, cpu, err, txconf, rxconf;
5502 iflib_dma_info_t ifdip;
5503 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5504 uint32_t *txqsizes = scctx->isc_txqsizes;
5505 uint8_t nrxqs = sctx->isc_nrxqs;
5506 uint8_t ntxqs = sctx->isc_ntxqs;
5507 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5511 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5512 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5514 /* Allocate the TX ring struct memory */
5515 if (!(ctx->ifc_txqs =
5516 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5517 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5518 device_printf(dev, "Unable to allocate TX ring memory\n");
5523 /* Now allocate the RX */
5524 if (!(ctx->ifc_rxqs =
5525 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5526 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5527 device_printf(dev, "Unable to allocate RX ring memory\n");
5532 txq = ctx->ifc_txqs;
5533 rxq = ctx->ifc_rxqs;
5536 * XXX handle allocation failure
5538 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5539 /* Set up some basics */
5541 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5542 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5544 "Unable to allocate TX DMA info memory\n");
5548 txq->ift_ifdi = ifdip;
5549 for (j = 0; j < ntxqs; j++, ifdip++) {
5550 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5552 "Unable to allocate TX descriptors\n");
5556 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5557 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5561 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5562 txq->ift_br_offset = 1;
5564 txq->ift_br_offset = 0;
5567 txq->ift_timer.c_cpu = cpu;
5569 if (iflib_txsd_alloc(txq)) {
5570 device_printf(dev, "Critical Failure setting up TX buffers\n");
5575 /* Initialize the TX lock */
5576 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5577 device_get_nameunit(dev), txq->ift_id);
5578 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5579 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5581 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5582 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5584 /* XXX free any allocated rings */
5585 device_printf(dev, "Unable to allocate buf_ring\n");
5590 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5591 /* Set up some basics */
5592 callout_init(&rxq->ifr_watchdog, 1);
5594 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5595 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5597 "Unable to allocate RX DMA info memory\n");
5602 rxq->ifr_ifdi = ifdip;
5603 /* XXX this needs to be changed if #rx queues != #tx queues */
5604 rxq->ifr_ntxqirq = 1;
5605 rxq->ifr_txqid[0] = i;
5606 for (j = 0; j < nrxqs; j++, ifdip++) {
5607 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5609 "Unable to allocate RX descriptors\n");
5613 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5617 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5618 rxq->ifr_fl_offset = 1;
5620 rxq->ifr_fl_offset = 0;
5622 rxq->ifr_nfl = nfree_lists;
5624 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5625 device_printf(dev, "Unable to allocate free list memory\n");
5630 for (j = 0; j < nfree_lists; j++) {
5631 fl[j].ifl_rxq = rxq;
5633 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5634 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5636 /* Allocate receive buffers for the ring */
5637 if (iflib_rxsd_alloc(rxq)) {
5639 "Critical Failure setting up receive buffers\n");
5644 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5645 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5650 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5651 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5652 for (i = 0; i < ntxqsets; i++) {
5653 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5655 for (j = 0; j < ntxqs; j++, di++) {
5656 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5657 paddrs[i*ntxqs + j] = di->idi_paddr;
5660 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5661 device_printf(ctx->ifc_dev,
5662 "Unable to allocate device TX queue\n");
5663 iflib_tx_structures_free(ctx);
5664 free(vaddrs, M_IFLIB);
5665 free(paddrs, M_IFLIB);
5668 free(vaddrs, M_IFLIB);
5669 free(paddrs, M_IFLIB);
5672 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5673 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5674 for (i = 0; i < nrxqsets; i++) {
5675 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5677 for (j = 0; j < nrxqs; j++, di++) {
5678 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5679 paddrs[i*nrxqs + j] = di->idi_paddr;
5682 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5683 device_printf(ctx->ifc_dev,
5684 "Unable to allocate device RX queue\n");
5685 iflib_tx_structures_free(ctx);
5686 free(vaddrs, M_IFLIB);
5687 free(paddrs, M_IFLIB);
5690 free(vaddrs, M_IFLIB);
5691 free(paddrs, M_IFLIB);
5695 /* XXX handle allocation failure changes */
5699 if (ctx->ifc_rxqs != NULL)
5700 free(ctx->ifc_rxqs, M_IFLIB);
5701 ctx->ifc_rxqs = NULL;
5702 if (ctx->ifc_txqs != NULL)
5703 free(ctx->ifc_txqs, M_IFLIB);
5704 ctx->ifc_txqs = NULL;
5710 iflib_tx_structures_setup(if_ctx_t ctx)
5712 iflib_txq_t txq = ctx->ifc_txqs;
5715 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5716 iflib_txq_setup(txq);
5722 iflib_tx_structures_free(if_ctx_t ctx)
5724 iflib_txq_t txq = ctx->ifc_txqs;
5725 if_shared_ctx_t sctx = ctx->ifc_sctx;
5728 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5729 for (j = 0; j < sctx->isc_ntxqs; j++)
5730 iflib_dma_free(&txq->ift_ifdi[j]);
5731 iflib_txq_destroy(txq);
5733 free(ctx->ifc_txqs, M_IFLIB);
5734 ctx->ifc_txqs = NULL;
5735 IFDI_QUEUES_FREE(ctx);
5738 /*********************************************************************
5740 * Initialize all receive rings.
5742 **********************************************************************/
5744 iflib_rx_structures_setup(if_ctx_t ctx)
5746 iflib_rxq_t rxq = ctx->ifc_rxqs;
5748 #if defined(INET6) || defined(INET)
5752 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5753 #if defined(INET6) || defined(INET)
5754 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5755 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5756 TCP_LRO_ENTRIES, min(1024,
5757 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5759 device_printf(ctx->ifc_dev,
5760 "LRO Initialization failed!\n");
5765 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5768 #if defined(INET6) || defined(INET)
5771 * Free LRO resources allocated so far, we will only handle
5772 * the rings that completed, the failing case will have
5773 * cleaned up for itself. 'q' failed, so its the terminus.
5775 rxq = ctx->ifc_rxqs;
5776 for (i = 0; i < q; ++i, rxq++) {
5777 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5778 tcp_lro_free(&rxq->ifr_lc);
5784 /*********************************************************************
5786 * Free all receive rings.
5788 **********************************************************************/
5790 iflib_rx_structures_free(if_ctx_t ctx)
5792 iflib_rxq_t rxq = ctx->ifc_rxqs;
5793 if_shared_ctx_t sctx = ctx->ifc_sctx;
5796 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5797 for (j = 0; j < sctx->isc_nrxqs; j++)
5798 iflib_dma_free(&rxq->ifr_ifdi[j]);
5799 iflib_rx_sds_free(rxq);
5800 #if defined(INET6) || defined(INET)
5801 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5802 tcp_lro_free(&rxq->ifr_lc);
5805 free(ctx->ifc_rxqs, M_IFLIB);
5806 ctx->ifc_rxqs = NULL;
5810 iflib_qset_structures_setup(if_ctx_t ctx)
5815 * It is expected that the caller takes care of freeing queues if this
5818 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5819 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5823 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5824 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5830 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5831 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5834 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5839 find_nth(if_ctx_t ctx, int qid)
5842 int i, cpuid, eqid, count;
5844 CPU_COPY(&ctx->ifc_cpus, &cpus);
5845 count = CPU_COUNT(&cpus);
5847 /* clear up to the qid'th bit */
5848 for (i = 0; i < eqid; i++) {
5849 cpuid = CPU_FFS(&cpus);
5851 CPU_CLR(cpuid-1, &cpus);
5853 cpuid = CPU_FFS(&cpus);
5859 extern struct cpu_group *cpu_top; /* CPU topology */
5862 find_child_with_core(int cpu, struct cpu_group *grp)
5866 if (grp->cg_children == 0)
5869 MPASS(grp->cg_child);
5870 for (i = 0; i < grp->cg_children; i++) {
5871 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5879 * Find the nth "close" core to the specified core
5880 * "close" is defined as the deepest level that shares
5881 * at least an L2 cache. With threads, this will be
5882 * threads on the same core. If the shared cache is L3
5883 * or higher, simply returns the same core.
5886 find_close_core(int cpu, int core_offset)
5888 struct cpu_group *grp;
5897 while ((i = find_child_with_core(cpu, grp)) != -1) {
5898 /* If the child only has one cpu, don't descend */
5899 if (grp->cg_child[i].cg_count <= 1)
5901 grp = &grp->cg_child[i];
5904 /* If they don't share at least an L2 cache, use the same CPU */
5905 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5909 CPU_COPY(&grp->cg_mask, &cs);
5911 /* Add the selected CPU offset to core offset. */
5912 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5913 if (fcpu - 1 == cpu)
5915 CPU_CLR(fcpu - 1, &cs);
5921 CPU_COPY(&grp->cg_mask, &cs);
5922 for (i = core_offset % grp->cg_count; i > 0; i--) {
5923 MPASS(CPU_FFS(&cs));
5924 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5926 MPASS(CPU_FFS(&cs));
5927 return CPU_FFS(&cs) - 1;
5931 find_close_core(int cpu, int core_offset __unused)
5938 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5942 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5943 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5944 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5946 case IFLIB_INTR_RXTX:
5947 /* RX queues get the specified core */
5948 return qid / CPU_COUNT(&ctx->ifc_cpus);
5954 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5955 #define find_close_core(cpuid, tid) CPU_FIRST()
5956 #define find_nth(ctx, gid) CPU_FIRST()
5959 /* Just to avoid copy/paste */
5961 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5962 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5966 int co, cpuid, err, tid;
5969 co = ctx->ifc_sysctl_core_offset;
5970 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5971 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5972 cpuid = find_nth(ctx, qid + co);
5973 tid = get_core_offset(ctx, type, qid);
5975 device_printf(dev, "get_core_offset failed\n");
5976 return (EOPNOTSUPP);
5978 cpuid = find_close_core(cpuid, tid);
5979 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5982 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5986 if (cpuid > ctx->ifc_cpuid_highest)
5987 ctx->ifc_cpuid_highest = cpuid;
5993 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5994 iflib_intr_type_t type, driver_filter_t *filter,
5995 void *filter_arg, int qid, const char *name)
5998 struct grouptask *gtask;
5999 struct taskqgroup *tqg;
6000 iflib_filter_info_t info;
6003 driver_filter_t *intr_fast;
6006 info = &ctx->ifc_filter_info;
6010 /* XXX merge tx/rx for netmap? */
6012 q = &ctx->ifc_txqs[qid];
6013 info = &ctx->ifc_txqs[qid].ift_filter_info;
6014 gtask = &ctx->ifc_txqs[qid].ift_task;
6015 tqg = qgroup_if_io_tqg;
6017 intr_fast = iflib_fast_intr;
6018 GROUPTASK_INIT(gtask, 0, fn, q);
6019 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6022 q = &ctx->ifc_rxqs[qid];
6023 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6024 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6025 tqg = qgroup_if_io_tqg;
6027 intr_fast = iflib_fast_intr;
6028 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6030 case IFLIB_INTR_RXTX:
6031 q = &ctx->ifc_rxqs[qid];
6032 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6033 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6034 tqg = qgroup_if_io_tqg;
6036 intr_fast = iflib_fast_intr_rxtx;
6037 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6039 case IFLIB_INTR_ADMIN:
6042 info = &ctx->ifc_filter_info;
6043 gtask = &ctx->ifc_admin_task;
6044 tqg = qgroup_if_config_tqg;
6045 fn = _task_fn_admin;
6046 intr_fast = iflib_fast_intr_ctx;
6049 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6054 info->ifi_filter = filter;
6055 info->ifi_filter_arg = filter_arg;
6056 info->ifi_task = gtask;
6060 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6062 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6065 if (type == IFLIB_INTR_ADMIN)
6069 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6074 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6081 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6083 struct grouptask *gtask;
6084 struct taskqgroup *tqg;
6091 q = &ctx->ifc_txqs[qid];
6092 gtask = &ctx->ifc_txqs[qid].ift_task;
6093 tqg = qgroup_if_io_tqg;
6095 GROUPTASK_INIT(gtask, 0, fn, q);
6098 q = &ctx->ifc_rxqs[qid];
6099 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6100 tqg = qgroup_if_io_tqg;
6102 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6104 case IFLIB_INTR_IOV:
6106 gtask = &ctx->ifc_vflr_task;
6107 tqg = qgroup_if_config_tqg;
6109 GROUPTASK_INIT(gtask, 0, fn, q);
6112 panic("unknown net intr type");
6115 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6118 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6121 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6126 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6130 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6133 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6134 rman_get_rid(irq->ii_res), irq->ii_res);
6138 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6140 iflib_txq_t txq = ctx->ifc_txqs;
6141 iflib_rxq_t rxq = ctx->ifc_rxqs;
6142 if_irq_t irq = &ctx->ifc_legacy_irq;
6143 iflib_filter_info_t info;
6145 struct grouptask *gtask;
6146 struct resource *res;
6147 struct taskqgroup *tqg;
6152 q = &ctx->ifc_rxqs[0];
6153 info = &rxq[0].ifr_filter_info;
6154 gtask = &rxq[0].ifr_task;
6155 tqg = qgroup_if_io_tqg;
6157 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6159 ctx->ifc_flags |= IFC_LEGACY;
6160 info->ifi_filter = filter;
6161 info->ifi_filter_arg = filter_arg;
6162 info->ifi_task = gtask;
6163 info->ifi_ctx = rx_only ? ctx : q;
6166 /* We allocate a single interrupt resource */
6167 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6168 iflib_fast_intr_rxtx, NULL, info, name);
6171 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6173 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6175 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6176 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6182 iflib_led_create(if_ctx_t ctx)
6185 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6186 device_get_nameunit(ctx->ifc_dev));
6190 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6193 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6197 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6200 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6204 iflib_admin_intr_deferred(if_ctx_t ctx)
6207 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6208 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6212 iflib_iov_intr_deferred(if_ctx_t ctx)
6215 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6219 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6222 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6227 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6231 GROUPTASK_INIT(gtask, 0, fn, ctx);
6232 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6237 iflib_config_gtask_deinit(struct grouptask *gtask)
6240 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6244 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6246 if_t ifp = ctx->ifc_ifp;
6247 iflib_txq_t txq = ctx->ifc_txqs;
6249 if_setbaudrate(ifp, baudrate);
6250 if (baudrate >= IF_Gbps(10)) {
6252 ctx->ifc_flags |= IFC_PREFETCH;
6255 /* If link down, disable watchdog */
6256 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6257 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6258 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6260 ctx->ifc_link_state = link_state;
6261 if_link_state_change(ifp, link_state);
6265 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6269 int credits_pre = txq->ift_cidx_processed;
6272 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6273 BUS_DMASYNC_POSTREAD);
6274 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6277 txq->ift_processed += credits;
6278 txq->ift_cidx_processed += credits;
6280 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6281 if (txq->ift_cidx_processed >= txq->ift_size)
6282 txq->ift_cidx_processed -= txq->ift_size;
6287 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6292 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6293 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6295 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6300 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6301 const char *description, if_int_delay_info_t info,
6302 int offset, int value)
6304 info->iidi_ctx = ctx;
6305 info->iidi_offset = offset;
6306 info->iidi_value = value;
6307 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6308 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6309 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6310 info, 0, iflib_sysctl_int_delay, "I", description);
6314 iflib_ctx_lock_get(if_ctx_t ctx)
6317 return (&ctx->ifc_ctx_sx);
6321 iflib_msix_init(if_ctx_t ctx)
6323 device_t dev = ctx->ifc_dev;
6324 if_shared_ctx_t sctx = ctx->ifc_sctx;
6325 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6326 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6327 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6329 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6330 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6333 device_printf(dev, "msix_init qsets capped at %d\n",
6334 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6336 /* Override by tuneable */
6337 if (scctx->isc_disable_msix)
6340 /* First try MSI-X */
6341 if ((msgs = pci_msix_count(dev)) == 0) {
6343 device_printf(dev, "MSI-X not supported or disabled\n");
6347 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6349 * bar == -1 => "trust me I know what I'm doing"
6350 * Some drivers are for hardware that is so shoddily
6351 * documented that no one knows which bars are which
6352 * so the developer has to map all bars. This hack
6353 * allows shoddy garbage to use MSI-X in this framework.
6356 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6357 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6358 if (ctx->ifc_msix_mem == NULL) {
6359 device_printf(dev, "Unable to map MSI-X table\n");
6364 admincnt = sctx->isc_admin_intrcnt;
6366 /* use only 1 qset in debug mode */
6367 queuemsgs = min(msgs - admincnt, 1);
6369 queuemsgs = msgs - admincnt;
6372 queues = imin(queuemsgs, rss_getnumbuckets());
6376 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6379 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6380 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6382 /* If we're doing RSS, clamp at the number of RSS buckets */
6383 if (queues > rss_getnumbuckets())
6384 queues = rss_getnumbuckets();
6386 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6387 rx_queues = iflib_num_rx_queues;
6391 if (rx_queues > scctx->isc_nrxqsets)
6392 rx_queues = scctx->isc_nrxqsets;
6395 * We want this to be all logical CPUs by default
6397 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6398 tx_queues = iflib_num_tx_queues;
6400 tx_queues = mp_ncpus;
6402 if (tx_queues > scctx->isc_ntxqsets)
6403 tx_queues = scctx->isc_ntxqsets;
6405 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6407 if (tx_queues != rx_queues)
6409 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6410 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6412 tx_queues = min(rx_queues, tx_queues);
6413 rx_queues = min(rx_queues, tx_queues);
6416 vectors = rx_queues + admincnt;
6417 if (msgs < vectors) {
6419 "insufficient number of MSI-X vectors "
6420 "(supported %d, need %d)\n", msgs, vectors);
6424 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6427 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6428 if (vectors != msgs) {
6430 "Unable to allocate sufficient MSI-X vectors "
6431 "(got %d, need %d)\n", vectors, msgs);
6432 pci_release_msi(dev);
6434 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6436 ctx->ifc_msix_mem = NULL;
6440 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6442 scctx->isc_vectors = vectors;
6443 scctx->isc_nrxqsets = rx_queues;
6444 scctx->isc_ntxqsets = tx_queues;
6445 scctx->isc_intr = IFLIB_INTR_MSIX;
6450 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6453 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6455 ctx->ifc_msix_mem = NULL;
6460 vectors = pci_msi_count(dev);
6461 scctx->isc_nrxqsets = 1;
6462 scctx->isc_ntxqsets = 1;
6463 scctx->isc_vectors = vectors;
6464 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6465 device_printf(dev,"Using an MSI interrupt\n");
6466 scctx->isc_intr = IFLIB_INTR_MSI;
6468 scctx->isc_vectors = 1;
6469 device_printf(dev,"Using a Legacy interrupt\n");
6470 scctx->isc_intr = IFLIB_INTR_LEGACY;
6476 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6479 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6482 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6484 const char *ring_state = "UNKNOWN";
6487 rc = sysctl_wire_old_buffer(req, 0);
6491 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6496 ring_state = ring_states[state[3]];
6498 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6499 state[0], state[1], state[2], ring_state);
6500 rc = sbuf_finish(sb);
6505 enum iflib_ndesc_handler {
6511 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6513 if_ctx_t ctx = (void *)arg1;
6514 enum iflib_ndesc_handler type = arg2;
6515 char buf[256] = {0};
6522 case IFLIB_NTXD_HANDLER:
6523 ndesc = ctx->ifc_sysctl_ntxds;
6525 nqs = ctx->ifc_sctx->isc_ntxqs;
6527 case IFLIB_NRXD_HANDLER:
6528 ndesc = ctx->ifc_sysctl_nrxds;
6530 nqs = ctx->ifc_sctx->isc_nrxqs;
6533 printf("%s: unhandled type\n", __func__);
6539 for (i=0; i<8; i++) {
6544 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6547 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6548 if (rc || req->newptr == NULL)
6551 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6552 i++, p = strsep(&next, " ,")) {
6553 ndesc[i] = strtoul(p, NULL, 10);
6559 #define NAME_BUFLEN 32
6561 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6563 device_t dev = iflib_get_dev(ctx);
6564 struct sysctl_oid_list *child, *oid_list;
6565 struct sysctl_ctx_list *ctx_list;
6566 struct sysctl_oid *node;
6568 ctx_list = device_get_sysctl_ctx(dev);
6569 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6570 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6571 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6572 oid_list = SYSCTL_CHILDREN(node);
6574 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6575 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6578 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6579 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6580 "# of txqs to use, 0 => use default #");
6581 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6582 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6583 "# of rxqs to use, 0 => use default #");
6584 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6585 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6586 "permit #txq != #rxq");
6587 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6588 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6589 "disable MSI-X (default 0)");
6590 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6591 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6592 "set the RX budget");
6593 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6594 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6595 "cause TX to abdicate instead of running to completion");
6596 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6597 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6598 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6599 "offset to start using cores at");
6600 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6601 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6602 "use separate cores for TX and RX");
6604 /* XXX change for per-queue sizes */
6605 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6606 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6607 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6608 "list of # of TX descriptors to use, 0 = use default #");
6609 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6610 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6611 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6612 "list of # of RX descriptors to use, 0 = use default #");
6616 iflib_add_device_sysctl_post(if_ctx_t ctx)
6618 if_shared_ctx_t sctx = ctx->ifc_sctx;
6619 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6620 device_t dev = iflib_get_dev(ctx);
6621 struct sysctl_oid_list *child;
6622 struct sysctl_ctx_list *ctx_list;
6627 char namebuf[NAME_BUFLEN];
6629 struct sysctl_oid *queue_node, *fl_node, *node;
6630 struct sysctl_oid_list *queue_list, *fl_list;
6631 ctx_list = device_get_sysctl_ctx(dev);
6633 node = ctx->ifc_sysctl_node;
6634 child = SYSCTL_CHILDREN(node);
6636 if (scctx->isc_ntxqsets > 100)
6638 else if (scctx->isc_ntxqsets > 10)
6642 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6643 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6644 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6645 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6646 queue_list = SYSCTL_CHILDREN(queue_node);
6648 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6650 &txq->ift_dequeued, "total mbufs freed");
6651 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6653 &txq->ift_enqueued, "total mbufs enqueued");
6655 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6657 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6658 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6660 &txq->ift_pullups, "# of times m_pullup was called");
6661 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6663 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6664 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6666 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6667 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6669 &txq->ift_map_failed, "# of times DMA map failed");
6670 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6672 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6673 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6675 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6676 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6678 &txq->ift_pidx, 1, "Producer Index");
6679 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6681 &txq->ift_cidx, 1, "Consumer Index");
6682 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6684 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6685 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6687 &txq->ift_in_use, 1, "descriptors in use");
6688 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6690 &txq->ift_processed, "descriptors procesed for clean");
6691 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6693 &txq->ift_cleaned, "total cleaned");
6694 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6695 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6696 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6697 mp_ring_state_handler, "A", "soft ring state");
6698 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6699 CTLFLAG_RD, &txq->ift_br->enqueues,
6700 "# of enqueues to the mp_ring for this queue");
6701 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6702 CTLFLAG_RD, &txq->ift_br->drops,
6703 "# of drops in the mp_ring for this queue");
6704 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6705 CTLFLAG_RD, &txq->ift_br->starts,
6706 "# of normal consumer starts in the mp_ring for this queue");
6707 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6708 CTLFLAG_RD, &txq->ift_br->stalls,
6709 "# of consumer stalls in the mp_ring for this queue");
6710 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6711 CTLFLAG_RD, &txq->ift_br->restarts,
6712 "# of consumer restarts in the mp_ring for this queue");
6713 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6714 CTLFLAG_RD, &txq->ift_br->abdications,
6715 "# of consumer abdications in the mp_ring for this queue");
6718 if (scctx->isc_nrxqsets > 100)
6720 else if (scctx->isc_nrxqsets > 10)
6724 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6725 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6726 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6727 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6728 queue_list = SYSCTL_CHILDREN(queue_node);
6729 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6730 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6732 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6735 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6736 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6737 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6738 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6739 fl_list = SYSCTL_CHILDREN(fl_node);
6740 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6742 &fl->ifl_pidx, 1, "Producer Index");
6743 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6745 &fl->ifl_cidx, 1, "Consumer Index");
6746 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6748 &fl->ifl_credits, 1, "credits available");
6749 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6751 &fl->ifl_buf_size, 1, "buffer size");
6753 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6755 &fl->ifl_m_enqueued, "mbufs allocated");
6756 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6758 &fl->ifl_m_dequeued, "mbufs freed");
6759 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6761 &fl->ifl_cl_enqueued, "clusters allocated");
6762 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6764 &fl->ifl_cl_dequeued, "clusters freed");
6773 iflib_request_reset(if_ctx_t ctx)
6777 ctx->ifc_flags |= IFC_DO_RESET;
6781 #ifndef __NO_STRICT_ALIGNMENT
6782 static struct mbuf *
6783 iflib_fixup_rx(struct mbuf *m)
6787 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6788 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6789 m->m_data += ETHER_HDR_LEN;
6792 MGETHDR(n, M_NOWAIT, MT_DATA);
6797 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6798 m->m_data += ETHER_HDR_LEN;
6799 m->m_len -= ETHER_HDR_LEN;
6800 n->m_len = ETHER_HDR_LEN;
6801 M_MOVE_PKTHDR(n, m);
6810 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6814 ctx = if_getsoftc(ifp);
6816 *nrxr = NRXQSETS(ctx);
6817 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6818 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6823 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6826 if_softc_ctx_t scctx;
6831 ctx = if_getsoftc(ifp);
6832 scctx = &ctx->ifc_softc_ctx;
6835 case DEBUGNET_START:
6836 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6837 rxq = &ctx->ifc_rxqs[i];
6838 for (j = 0; j < rxq->ifr_nfl; j++) {
6840 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6843 iflib_no_tx_batch = 1;
6851 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6857 ctx = if_getsoftc(ifp);
6858 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6862 txq = &ctx->ifc_txqs[0];
6863 error = iflib_encap(txq, &m);
6865 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6870 iflib_debugnet_poll(if_t ifp, int count)
6872 struct epoch_tracker et;
6874 if_softc_ctx_t scctx;
6878 ctx = if_getsoftc(ifp);
6879 scctx = &ctx->ifc_softc_ctx;
6881 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6885 txq = &ctx->ifc_txqs[0];
6886 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6888 NET_EPOCH_ENTER(et);
6889 for (i = 0; i < scctx->isc_nrxqsets; i++)
6890 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6894 #endif /* DEBUGNET */