2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
96 #include <dev/pci/pci_iov.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
174 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
188 struct sysctl_oid *ifc_sysctl_node;
189 uint16_t ifc_sysctl_ntxqs;
190 uint16_t ifc_sysctl_nrxqs;
191 uint16_t ifc_sysctl_qs_eq_override;
192 uint16_t ifc_sysctl_rx_budget;
193 uint16_t ifc_sysctl_tx_abdicate;
194 uint16_t ifc_sysctl_core_offset;
195 #define CORE_OFFSET_UNSPECIFIED 0xffff
196 uint8_t ifc_sysctl_separate_txrx;
198 qidx_t ifc_sysctl_ntxds[8];
199 qidx_t ifc_sysctl_nrxds[8];
200 struct if_txrx ifc_txrx;
201 #define isc_txd_encap ifc_txrx.ift_txd_encap
202 #define isc_txd_flush ifc_txrx.ift_txd_flush
203 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
204 #define isc_rxd_available ifc_txrx.ift_rxd_available
205 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
210 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
211 eventhandler_tag ifc_vlan_attach_event;
212 eventhandler_tag ifc_vlan_detach_event;
213 uint8_t ifc_mac[ETHER_ADDR_LEN];
214 char ifc_mtx_name[16];
219 iflib_get_softc(if_ctx_t ctx)
222 return (ctx->ifc_softc);
226 iflib_get_dev(if_ctx_t ctx)
229 return (ctx->ifc_dev);
233 iflib_get_ifp(if_ctx_t ctx)
236 return (ctx->ifc_ifp);
240 iflib_get_media(if_ctx_t ctx)
243 return (&ctx->ifc_media);
247 iflib_get_flags(if_ctx_t ctx)
249 return (ctx->ifc_flags);
253 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
256 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
260 iflib_get_softc_ctx(if_ctx_t ctx)
263 return (&ctx->ifc_softc_ctx);
267 iflib_get_sctx(if_ctx_t ctx)
270 return (ctx->ifc_sctx);
273 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
274 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
275 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
277 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
278 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
280 typedef struct iflib_sw_rx_desc_array {
281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
282 struct mbuf **ifsd_m; /* pkthdr mbufs */
283 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
284 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
285 } iflib_rxsd_array_t;
287 typedef struct iflib_sw_tx_desc_array {
288 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
289 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
290 struct mbuf **ifsd_m; /* pkthdr mbufs */
294 /* magic number that should be high enough for any hardware */
295 #define IFLIB_MAX_TX_SEGS 128
296 #define IFLIB_RX_COPY_THRESH 128
297 #define IFLIB_MAX_RX_REFRESH 32
298 /* The minimum descriptors per second before we start coalescing */
299 #define IFLIB_MIN_DESC_SEC 16384
300 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
301 #define IFLIB_QUEUE_IDLE 0
302 #define IFLIB_QUEUE_HUNG 1
303 #define IFLIB_QUEUE_WORKING 2
304 /* maximum number of txqs that can share an rx interrupt */
305 #define IFLIB_MAX_TX_SHARED_INTR 4
307 /* this should really scale with ring size - this is a fairly arbitrary value */
308 #define TX_BATCH_SIZE 32
310 #define IFLIB_RESTART_BUDGET 8
313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
319 qidx_t ift_cidx_processed;
322 uint8_t ift_br_offset;
323 uint16_t ift_npending;
324 uint16_t ift_db_pending;
325 uint16_t ift_rs_pending;
327 uint8_t ift_txd_size[8];
328 uint64_t ift_processed;
329 uint64_t ift_cleaned;
330 uint64_t ift_cleaned_prev;
332 uint64_t ift_enqueued;
333 uint64_t ift_dequeued;
335 uint64_t ift_no_tx_dma_setup;
336 uint64_t ift_no_desc_avail;
337 uint64_t ift_mbuf_defrag_failed;
338 uint64_t ift_mbuf_defrag;
339 uint64_t ift_map_failed;
340 uint64_t ift_txd_encap_efbig;
341 uint64_t ift_pullups;
342 uint64_t ift_last_timer_tick;
345 struct mtx ift_db_mtx;
347 /* constant values */
349 struct ifmp_ring *ift_br;
350 struct grouptask ift_task;
353 struct callout ift_timer;
355 if_txsd_vec_t ift_sds;
358 uint8_t ift_update_freq;
359 struct iflib_filter_info ift_filter_info;
360 bus_dma_tag_t ift_buf_tag;
361 bus_dma_tag_t ift_tso_buf_tag;
362 iflib_dma_info_t ift_ifdi;
363 #define MTX_NAME_LEN 16
364 char ift_mtx_name[MTX_NAME_LEN];
365 char ift_db_mtx_name[MTX_NAME_LEN];
366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
367 #ifdef IFLIB_DIAGNOSTICS
368 uint64_t ift_cpu_exec_count[256];
370 } __aligned(CACHE_LINE_SIZE);
377 uint8_t ifl_rxd_size;
379 uint64_t ifl_m_enqueued;
380 uint64_t ifl_m_dequeued;
381 uint64_t ifl_cl_enqueued;
382 uint64_t ifl_cl_dequeued;
386 bitstr_t *ifl_rx_bitmap;
390 uint16_t ifl_buf_size;
393 iflib_rxsd_array_t ifl_sds;
396 bus_dma_tag_t ifl_buf_tag;
397 iflib_dma_info_t ifl_ifdi;
398 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
399 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
400 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
401 } __aligned(CACHE_LINE_SIZE);
404 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
410 else if (pidx < cidx)
411 used = size - cidx + pidx;
412 else if (gen == 0 && pidx == cidx)
414 else if (gen == 1 && pidx == cidx)
422 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
424 #define IDXDIFF(head, tail, wrap) \
425 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
428 /* If there is a separate completion queue -
429 * these are the cq cidx and pidx. Otherwise
436 uint8_t ifr_fl_offset;
442 uint8_t ifr_lro_enabled;
445 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
446 struct lro_ctrl ifr_lc;
447 struct grouptask ifr_task;
448 struct iflib_filter_info ifr_filter_info;
449 iflib_dma_info_t ifr_ifdi;
451 /* dynamically allocate if any drivers need a value substantially larger than this */
452 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
453 #ifdef IFLIB_DIAGNOSTICS
454 uint64_t ifr_cpu_exec_count[256];
456 } __aligned(CACHE_LINE_SIZE);
458 typedef struct if_rxsd {
460 struct mbuf **ifsd_m;
465 /* multiple of word size */
467 #define PKT_INFO_SIZE 6
468 #define RXD_INFO_SIZE 5
469 #define PKT_TYPE uint64_t
471 #define PKT_INFO_SIZE 11
472 #define RXD_INFO_SIZE 8
473 #define PKT_TYPE uint32_t
475 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
476 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
478 typedef struct if_pkt_info_pad {
479 PKT_TYPE pkt_val[PKT_INFO_SIZE];
480 } *if_pkt_info_pad_t;
481 typedef struct if_rxd_info_pad {
482 PKT_TYPE rxd_val[RXD_INFO_SIZE];
483 } *if_rxd_info_pad_t;
485 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
486 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
490 pkt_info_zero(if_pkt_info_t pi)
492 if_pkt_info_pad_t pi_pad;
494 pi_pad = (if_pkt_info_pad_t)pi;
495 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
496 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
498 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
499 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
503 static device_method_t iflib_pseudo_methods[] = {
504 DEVMETHOD(device_attach, noop_attach),
505 DEVMETHOD(device_detach, iflib_pseudo_detach),
509 driver_t iflib_pseudodriver = {
510 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
514 rxd_info_zero(if_rxd_info_t ri)
516 if_rxd_info_pad_t ri_pad;
519 ri_pad = (if_rxd_info_pad_t)ri;
520 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
521 ri_pad->rxd_val[i] = 0;
522 ri_pad->rxd_val[i+1] = 0;
523 ri_pad->rxd_val[i+2] = 0;
524 ri_pad->rxd_val[i+3] = 0;
527 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
532 * Only allow a single packet to take up most 1/nth of the tx ring
534 #define MAX_SINGLE_PACKET_FRACTION 12
535 #define IF_BAD_DMA (bus_addr_t)-1
537 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
539 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
540 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
541 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
542 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
545 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
546 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
547 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
548 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
552 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
553 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
556 iflib_set_detach(if_ctx_t ctx)
559 ctx->ifc_flags |= IFC_IN_DETACH;
563 /* Our boot-time initialization hook */
564 static int iflib_module_event_handler(module_t, int, void *);
566 static moduledata_t iflib_moduledata = {
568 iflib_module_event_handler,
572 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
573 MODULE_VERSION(iflib, 1);
575 MODULE_DEPEND(iflib, pci, 1, 1, 1);
576 MODULE_DEPEND(iflib, ether, 1, 1, 1);
578 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
579 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
581 #ifndef IFLIB_DEBUG_COUNTERS
583 #define IFLIB_DEBUG_COUNTERS 1
585 #define IFLIB_DEBUG_COUNTERS 0
586 #endif /* !INVARIANTS */
589 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
590 "iflib driver parameters");
593 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
595 static int iflib_min_tx_latency = 0;
596 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
597 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
598 static int iflib_no_tx_batch = 0;
599 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
600 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
603 #if IFLIB_DEBUG_COUNTERS
605 static int iflib_tx_seen;
606 static int iflib_tx_sent;
607 static int iflib_tx_encap;
608 static int iflib_rx_allocs;
609 static int iflib_fl_refills;
610 static int iflib_fl_refills_large;
611 static int iflib_tx_frees;
613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
614 &iflib_tx_seen, 0, "# tx mbufs seen");
615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
616 &iflib_tx_sent, 0, "# tx mbufs sent");
617 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
618 &iflib_tx_encap, 0, "# tx mbufs encapped");
619 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
620 &iflib_tx_frees, 0, "# tx frees");
621 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
622 &iflib_rx_allocs, 0, "# rx allocations");
623 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
624 &iflib_fl_refills, 0, "# refills");
625 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
626 &iflib_fl_refills_large, 0, "# large refills");
629 static int iflib_txq_drain_flushing;
630 static int iflib_txq_drain_oactive;
631 static int iflib_txq_drain_notready;
633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
634 &iflib_txq_drain_flushing, 0, "# drain flushes");
635 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
636 &iflib_txq_drain_oactive, 0, "# drain oactives");
637 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
638 &iflib_txq_drain_notready, 0, "# drain notready");
641 static int iflib_encap_load_mbuf_fail;
642 static int iflib_encap_pad_mbuf_fail;
643 static int iflib_encap_txq_avail_fail;
644 static int iflib_encap_txd_encap_fail;
646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
647 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
649 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
650 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
651 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
652 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
653 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
655 static int iflib_task_fn_rxs;
656 static int iflib_rx_intr_enables;
657 static int iflib_fast_intrs;
658 static int iflib_rx_unavail;
659 static int iflib_rx_ctx_inactive;
660 static int iflib_rx_if_input;
661 static int iflib_rx_mbuf_null;
662 static int iflib_rxd_flush;
664 static int iflib_verbose_debug;
666 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
667 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
669 &iflib_rx_intr_enables, 0, "# rx intr enables");
670 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
671 &iflib_fast_intrs, 0, "# fast_intr calls");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
673 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
675 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
677 &iflib_rx_if_input, 0, "# times rxeof called if_input");
678 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
679 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
680 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
681 &iflib_rxd_flush, 0, "# times rxd_flush called");
682 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
683 &iflib_verbose_debug, 0, "enable verbose debugging");
685 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
687 iflib_debug_reset(void)
689 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
690 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
691 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
692 iflib_txq_drain_notready =
693 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
694 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
695 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
697 iflib_rx_ctx_inactive = iflib_rx_if_input =
698 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
702 #define DBG_COUNTER_INC(name)
703 static void iflib_debug_reset(void) {}
706 #define IFLIB_DEBUG 0
708 static void iflib_tx_structures_free(if_ctx_t ctx);
709 static void iflib_rx_structures_free(if_ctx_t ctx);
710 static int iflib_queues_alloc(if_ctx_t ctx);
711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
713 static int iflib_qset_structures_setup(if_ctx_t ctx);
714 static int iflib_msix_init(if_ctx_t ctx);
715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
719 static void iflib_altq_if_start(if_t ifp);
720 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
722 static int iflib_register(if_ctx_t);
723 static void iflib_init_locked(if_ctx_t ctx);
724 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
725 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
726 static void iflib_ifmp_purge(iflib_txq_t txq);
727 static void _iflib_pre_assert(if_softc_ctx_t scctx);
728 static void iflib_if_init_locked(if_ctx_t ctx);
729 static void iflib_free_intr_mem(if_ctx_t ctx);
730 #ifndef __NO_STRICT_ALIGNMENT
731 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
734 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
735 SLIST_HEAD_INITIALIZER(cpu_offsets);
737 SLIST_ENTRY(cpu_offset) entries;
739 unsigned int refcount;
742 static struct mtx cpu_offset_mtx;
743 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
746 NETDUMP_DEFINE(iflib);
749 #include <sys/selinfo.h>
750 #include <net/netmap.h>
751 #include <dev/netmap/netmap_kern.h>
753 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
755 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
758 * device-specific sysctl variables:
760 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
761 * During regular operations the CRC is stripped, but on some
762 * hardware reception of frames not multiple of 64 is slower,
763 * so using crcstrip=0 helps in benchmarks.
765 * iflib_rx_miss, iflib_rx_miss_bufs:
766 * count packets that might be missed due to lost interrupts.
768 SYSCTL_DECL(_dev_netmap);
770 * The xl driver by default strips CRCs and we do not override it.
773 int iflib_crcstrip = 1;
774 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
775 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
777 int iflib_rx_miss, iflib_rx_miss_bufs;
778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
779 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
781 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
784 * Register/unregister. We are already under netmap lock.
785 * Only called on the first register or the last unregister.
788 iflib_netmap_register(struct netmap_adapter *na, int onoff)
790 struct ifnet *ifp = na->ifp;
791 if_ctx_t ctx = ifp->if_softc;
795 IFDI_INTR_DISABLE(ctx);
797 /* Tell the stack that the interface is no longer active */
798 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
801 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
803 /* enable or disable flags and callbacks in na and ifp */
805 nm_set_native_flags(na);
807 nm_clear_native_flags(na);
810 iflib_init_locked(ctx);
811 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
812 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
814 nm_clear_native_flags(na);
820 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
822 struct netmap_adapter *na = kring->na;
823 u_int const lim = kring->nkr_num_slots - 1;
824 u_int head = kring->rhead;
825 struct netmap_ring *ring = kring->ring;
827 struct if_rxd_update iru;
828 if_ctx_t ctx = rxq->ifr_ctx;
829 iflib_fl_t fl = &rxq->ifr_fl[0];
830 uint32_t refill_pidx, nic_i;
831 #if IFLIB_DEBUG_COUNTERS
835 if (nm_i == head && __predict_true(!init))
837 iru_init(&iru, rxq, 0 /* flid */);
838 map = fl->ifl_sds.ifsd_map;
839 refill_pidx = netmap_idx_k2n(kring, nm_i);
841 * IMPORTANT: we must leave one free slot in the ring,
842 * so move head back by one unit
844 head = nm_prev(head, lim);
846 DBG_COUNTER_INC(fl_refills);
847 while (nm_i != head) {
848 #if IFLIB_DEBUG_COUNTERS
850 DBG_COUNTER_INC(fl_refills_large);
852 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
853 struct netmap_slot *slot = &ring->slot[nm_i];
854 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
855 uint32_t nic_i_dma = refill_pidx;
856 nic_i = netmap_idx_k2n(kring, nm_i);
858 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
860 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
861 return netmap_ring_reinit(kring);
863 fl->ifl_vm_addrs[tmp_pidx] = addr;
864 if (__predict_false(init) && map) {
865 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
866 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
867 /* buffer has changed, reload map */
868 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
870 slot->flags &= ~NS_BUF_CHANGED;
872 nm_i = nm_next(nm_i, lim);
873 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
874 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
877 iru.iru_pidx = refill_pidx;
878 iru.iru_count = tmp_pidx+1;
879 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
885 for (int n = 0; n < iru.iru_count; n++) {
886 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
887 BUS_DMASYNC_PREREAD);
888 /* XXX - change this to not use the netmap func*/
889 nic_i_dma = nm_next(nic_i_dma, lim);
893 kring->nr_hwcur = head;
896 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
897 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
898 if (__predict_true(nic_i != UINT_MAX)) {
899 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
900 DBG_COUNTER_INC(rxd_flush);
906 * Reconcile kernel and user view of the transmit ring.
908 * All information is in the kring.
909 * Userspace wants to send packets up to the one before kring->rhead,
910 * kernel knows kring->nr_hwcur is the first unsent packet.
912 * Here we push packets out (as many as possible), and possibly
913 * reclaim buffers from previously completed transmission.
915 * The caller (netmap) guarantees that there is only one instance
916 * running at any time. Any interference with other driver
917 * methods should be handled by the individual drivers.
920 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
922 struct netmap_adapter *na = kring->na;
923 struct ifnet *ifp = na->ifp;
924 struct netmap_ring *ring = kring->ring;
925 u_int nm_i; /* index into the netmap kring */
926 u_int nic_i; /* index into the NIC ring */
928 u_int const lim = kring->nkr_num_slots - 1;
929 u_int const head = kring->rhead;
930 struct if_pkt_info pi;
933 * interrupts on every tx packet are expensive so request
934 * them every half ring, or where NS_REPORT is set
936 u_int report_frequency = kring->nkr_num_slots >> 1;
937 /* device-specific */
938 if_ctx_t ctx = ifp->if_softc;
939 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
941 bus_dmamap_sync(txq->ift_buf_tag, txq->ift_ifdi->idi_map,
942 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
945 * First part: process new packets to send.
946 * nm_i is the current index in the netmap kring,
947 * nic_i is the corresponding index in the NIC ring.
949 * If we have packets to send (nm_i != head)
950 * iterate over the netmap ring, fetch length and update
951 * the corresponding slot in the NIC ring. Some drivers also
952 * need to update the buffer's physical address in the NIC slot
953 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
955 * The netmap_reload_map() calls is especially expensive,
956 * even when (as in this case) the tag is 0, so do only
957 * when the buffer has actually changed.
959 * If possible do not set the report/intr bit on all slots,
960 * but only a few times per ring or when NS_REPORT is set.
962 * Finally, on 10G and faster drivers, it might be useful
963 * to prefetch the next slot and txr entry.
966 nm_i = kring->nr_hwcur;
967 if (nm_i != head) { /* we have new packets to send */
969 pi.ipi_segs = txq->ift_segs;
970 pi.ipi_qsidx = kring->ring_id;
971 nic_i = netmap_idx_k2n(kring, nm_i);
973 __builtin_prefetch(&ring->slot[nm_i]);
974 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
975 if (txq->ift_sds.ifsd_map)
976 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
978 for (n = 0; nm_i != head; n++) {
979 struct netmap_slot *slot = &ring->slot[nm_i];
980 u_int len = slot->len;
982 void *addr = PNMB(na, slot, &paddr);
983 int flags = (slot->flags & NS_REPORT ||
984 nic_i == 0 || nic_i == report_frequency) ?
987 /* device-specific */
989 pi.ipi_segs[0].ds_addr = paddr;
990 pi.ipi_segs[0].ds_len = len;
994 pi.ipi_flags = flags;
996 /* Fill the slot in the NIC ring. */
997 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
998 DBG_COUNTER_INC(tx_encap);
1000 /* prefetch for next round */
1001 __builtin_prefetch(&ring->slot[nm_i + 1]);
1002 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1003 if (txq->ift_sds.ifsd_map) {
1004 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1006 NM_CHECK_ADDR_LEN(na, addr, len);
1008 if (slot->flags & NS_BUF_CHANGED) {
1009 /* buffer has changed, reload map */
1010 netmap_reload_map(na, txq->ift_buf_tag,
1011 txq->ift_sds.ifsd_map[nic_i], addr);
1013 /* make sure changes to the buffer are synced */
1014 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1015 BUS_DMASYNC_PREWRITE);
1017 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1018 nm_i = nm_next(nm_i, lim);
1019 nic_i = nm_next(nic_i, lim);
1021 kring->nr_hwcur = nm_i;
1023 /* synchronize the NIC ring */
1024 bus_dmamap_sync(txq->ift_buf_tag, txq->ift_ifdi->idi_map,
1025 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1027 /* (re)start the tx unit up to slot nic_i (excluded) */
1028 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1032 * Second part: reclaim buffers for completed transmissions.
1034 * If there are unclaimed buffers, attempt to reclaim them.
1035 * If none are reclaimed, and TX IRQs are not in use, do an initial
1036 * minimal delay, then trigger the tx handler which will spin in the
1039 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1040 if (iflib_tx_credits_update(ctx, txq)) {
1041 /* some tx completed, increment avail */
1042 nic_i = txq->ift_cidx_processed;
1043 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1046 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1047 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1048 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1049 iflib_timer, txq, txq->ift_timer.c_cpu);
1055 * Reconcile kernel and user view of the receive ring.
1056 * Same as for the txsync, this routine must be efficient.
1057 * The caller guarantees a single invocations, but races against
1058 * the rest of the driver should be handled here.
1060 * On call, kring->rhead is the first packet that userspace wants
1061 * to keep, and kring->rcur is the wakeup point.
1062 * The kernel has previously reported packets up to kring->rtail.
1064 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1065 * of whether or not we received an interrupt.
1068 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1070 struct netmap_adapter *na = kring->na;
1071 struct netmap_ring *ring = kring->ring;
1072 uint32_t nm_i; /* index into the netmap ring */
1073 uint32_t nic_i; /* index into the NIC ring */
1075 u_int const lim = kring->nkr_num_slots - 1;
1076 u_int const head = kring->rhead;
1077 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1078 struct if_rxd_info ri;
1080 struct ifnet *ifp = na->ifp;
1081 if_ctx_t ctx = ifp->if_softc;
1082 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1083 iflib_fl_t fl = rxq->ifr_fl;
1085 return netmap_ring_reinit(kring);
1087 /* XXX check sync modes */
1088 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1089 if (fl->ifl_sds.ifsd_map == NULL)
1091 bus_dmamap_sync(rxq->ifr_fl[i].ifl_buf_tag,
1092 fl->ifl_ifdi->idi_map,
1093 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1096 * First part: import newly received packets.
1098 * nm_i is the index of the next free slot in the netmap ring,
1099 * nic_i is the index of the next received packet in the NIC ring,
1100 * and they may differ in case if_init() has been called while
1101 * in netmap mode. For the receive ring we have
1103 * nic_i = rxr->next_check;
1104 * nm_i = kring->nr_hwtail (previous)
1106 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1108 * rxr->next_check is set to 0 on a ring reinit
1110 if (netmap_no_pendintr || force_update) {
1111 int crclen = iflib_crcstrip ? 0 : 4;
1114 for (i = 0; i < rxq->ifr_nfl; i++) {
1115 fl = &rxq->ifr_fl[i];
1116 nic_i = fl->ifl_cidx;
1117 nm_i = netmap_idx_n2k(kring, nic_i);
1118 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1119 for (n = 0; avail > 0; n++, avail--) {
1121 ri.iri_frags = rxq->ifr_frags;
1122 ri.iri_qsidx = kring->ring_id;
1123 ri.iri_ifp = ctx->ifc_ifp;
1124 ri.iri_cidx = nic_i;
1126 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1127 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1128 ring->slot[nm_i].flags = 0;
1129 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1130 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1131 nm_i = nm_next(nm_i, lim);
1132 nic_i = nm_next(nic_i, lim);
1134 if (n) { /* update the state variables */
1135 if (netmap_no_pendintr && !force_update) {
1138 iflib_rx_miss_bufs += n;
1140 fl->ifl_cidx = nic_i;
1141 kring->nr_hwtail = nm_i;
1143 kring->nr_kflags &= ~NKR_PENDINTR;
1147 * Second part: skip past packets that userspace has released.
1148 * (kring->nr_hwcur to head excluded),
1149 * and make the buffers available for reception.
1150 * As usual nm_i is the index in the netmap ring,
1151 * nic_i is the index in the NIC ring, and
1152 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1154 /* XXX not sure how this will work with multiple free lists */
1155 nm_i = kring->nr_hwcur;
1157 return (netmap_fl_refill(rxq, kring, nm_i, false));
1161 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1163 struct ifnet *ifp = na->ifp;
1164 if_ctx_t ctx = ifp->if_softc;
1168 IFDI_INTR_ENABLE(ctx);
1170 IFDI_INTR_DISABLE(ctx);
1177 iflib_netmap_attach(if_ctx_t ctx)
1179 struct netmap_adapter na;
1180 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1182 bzero(&na, sizeof(na));
1184 na.ifp = ctx->ifc_ifp;
1185 na.na_flags = NAF_BDG_MAYSLEEP;
1186 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1187 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1189 na.num_tx_desc = scctx->isc_ntxd[0];
1190 na.num_rx_desc = scctx->isc_nrxd[0];
1191 na.nm_txsync = iflib_netmap_txsync;
1192 na.nm_rxsync = iflib_netmap_rxsync;
1193 na.nm_register = iflib_netmap_register;
1194 na.nm_intr = iflib_netmap_intr;
1195 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1196 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1197 return (netmap_attach(&na));
1201 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1203 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1204 struct netmap_slot *slot;
1206 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1209 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1212 * In netmap mode, set the map for the packet buffer.
1213 * NOTE: Some drivers (not this one) also need to set
1214 * the physical buffer address in the NIC ring.
1215 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1216 * netmap slot index, si
1218 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1219 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1220 NMB(na, slot + si));
1225 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1227 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1228 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1229 struct netmap_slot *slot;
1232 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1235 nm_i = netmap_idx_n2k(kring, 0);
1236 netmap_fl_refill(rxq, kring, nm_i, true);
1240 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1242 struct netmap_kring *kring;
1244 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1246 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1247 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1248 netmap_tx_irq(ctx->ifc_ifp, txqid);
1249 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1253 *reset_on = hz / 1000;
1258 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1261 #define iflib_netmap_txq_init(ctx, txq)
1262 #define iflib_netmap_rxq_init(ctx, rxq)
1263 #define iflib_netmap_detach(ifp)
1265 #define iflib_netmap_attach(ctx) (0)
1266 #define netmap_rx_irq(ifp, qid, budget) (0)
1267 #define netmap_tx_irq(ifp, qid) do {} while (0)
1268 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1272 #if defined(__i386__) || defined(__amd64__)
1273 static __inline void
1276 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1278 static __inline void
1279 prefetch2cachelines(void *x)
1281 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1282 #if (CACHE_LINE_SIZE < 128)
1283 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1288 #define prefetch2cachelines(x)
1292 iflib_gen_mac(if_ctx_t ctx)
1296 char uuid[HOSTUUIDLEN+1];
1297 char buf[HOSTUUIDLEN+16];
1299 unsigned char digest[16];
1303 uuid[HOSTUUIDLEN] = 0;
1304 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1305 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1307 * Generate a pseudo-random, deterministic MAC
1308 * address based on the UUID and unit number.
1309 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1312 MD5Update(&mdctx, buf, strlen(buf));
1313 MD5Final(digest, &mdctx);
1324 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1328 fl = &rxq->ifr_fl[flid];
1329 iru->iru_paddrs = fl->ifl_bus_addrs;
1330 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1331 iru->iru_idxs = fl->ifl_rxd_idxs;
1332 iru->iru_qsidx = rxq->ifr_id;
1333 iru->iru_buf_size = fl->ifl_buf_size;
1334 iru->iru_flidx = fl->ifl_id;
1338 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1342 *(bus_addr_t *) arg = segs[0].ds_addr;
1346 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1349 device_t dev = ctx->ifc_dev;
1351 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1352 align, 0, /* alignment, bounds */
1353 BUS_SPACE_MAXADDR, /* lowaddr */
1354 BUS_SPACE_MAXADDR, /* highaddr */
1355 NULL, NULL, /* filter, filterarg */
1358 size, /* maxsegsize */
1359 BUS_DMA_ALLOCNOW, /* flags */
1360 NULL, /* lockfunc */
1365 "%s: bus_dma_tag_create failed: %d\n",
1370 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1371 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1374 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1375 __func__, (uintmax_t)size, err);
1379 dma->idi_paddr = IF_BAD_DMA;
1380 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1381 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1382 if (err || dma->idi_paddr == IF_BAD_DMA) {
1384 "%s: bus_dmamap_load failed: %d\n",
1389 dma->idi_size = size;
1393 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1395 bus_dma_tag_destroy(dma->idi_tag);
1397 dma->idi_tag = NULL;
1403 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1405 if_shared_ctx_t sctx = ctx->ifc_sctx;
1407 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1409 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1413 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1416 iflib_dma_info_t *dmaiter;
1419 for (i = 0; i < count; i++, dmaiter++) {
1420 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1424 iflib_dma_free_multi(dmalist, i);
1429 iflib_dma_free(iflib_dma_info_t dma)
1431 if (dma->idi_tag == NULL)
1433 if (dma->idi_paddr != IF_BAD_DMA) {
1434 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1435 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1436 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1437 dma->idi_paddr = IF_BAD_DMA;
1439 if (dma->idi_vaddr != NULL) {
1440 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1441 dma->idi_vaddr = NULL;
1443 bus_dma_tag_destroy(dma->idi_tag);
1444 dma->idi_tag = NULL;
1448 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1451 iflib_dma_info_t *dmaiter = dmalist;
1453 for (i = 0; i < count; i++, dmaiter++)
1454 iflib_dma_free(*dmaiter);
1457 #ifdef EARLY_AP_STARTUP
1458 static const int iflib_started = 1;
1461 * We used to abuse the smp_started flag to decide if the queues have been
1462 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1463 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1464 * is set. Run a SYSINIT() strictly after that to just set a usable
1468 static int iflib_started;
1471 iflib_record_started(void *arg)
1476 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1477 iflib_record_started, NULL);
1481 iflib_fast_intr(void *arg)
1483 iflib_filter_info_t info = arg;
1484 struct grouptask *gtask = info->ifi_task;
1488 return (FILTER_STRAY);
1490 DBG_COUNTER_INC(fast_intrs);
1491 if (info->ifi_filter != NULL) {
1492 result = info->ifi_filter(info->ifi_filter_arg);
1493 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1497 GROUPTASK_ENQUEUE(gtask);
1498 return (FILTER_HANDLED);
1502 iflib_fast_intr_rxtx(void *arg)
1504 iflib_filter_info_t info = arg;
1505 struct grouptask *gtask = info->ifi_task;
1506 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1507 if_ctx_t ctx = NULL;;
1508 int i, cidx, result;
1511 return (FILTER_STRAY);
1513 DBG_COUNTER_INC(fast_intrs);
1514 if (info->ifi_filter != NULL) {
1515 result = info->ifi_filter(info->ifi_filter_arg);
1516 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1520 MPASS(rxq->ifr_ntxqirq);
1521 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1522 qidx_t txqid = rxq->ifr_txqid[i];
1526 bus_dmamap_sync(rxq->ifr_ifdi->idi_tag, rxq->ifr_ifdi->idi_map,
1527 BUS_DMASYNC_POSTREAD);
1528 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1529 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1532 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1534 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1535 cidx = rxq->ifr_cq_cidx;
1537 cidx = rxq->ifr_fl[0].ifl_cidx;
1538 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1539 GROUPTASK_ENQUEUE(gtask);
1541 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1542 DBG_COUNTER_INC(rx_intr_enables);
1544 return (FILTER_HANDLED);
1549 iflib_fast_intr_ctx(void *arg)
1551 iflib_filter_info_t info = arg;
1552 struct grouptask *gtask = info->ifi_task;
1556 return (FILTER_STRAY);
1558 DBG_COUNTER_INC(fast_intrs);
1559 if (info->ifi_filter != NULL) {
1560 result = info->ifi_filter(info->ifi_filter_arg);
1561 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1565 GROUPTASK_ENQUEUE(gtask);
1566 return (FILTER_HANDLED);
1570 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1571 driver_filter_t filter, driver_intr_t handler, void *arg,
1575 struct resource *res;
1577 device_t dev = ctx->ifc_dev;
1580 if (ctx->ifc_flags & IFC_LEGACY)
1581 flags |= RF_SHAREABLE;
1584 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1587 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1591 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1592 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1593 filter, handler, arg, &tag);
1596 "failed to setup interrupt for rid %d, name %s: %d\n",
1597 rid, name ? name : "unknown", rc);
1600 bus_describe_intr(dev, res, tag, "%s", name);
1607 /*********************************************************************
1609 * Allocate DMA resources for TX buffers as well as memory for the TX
1610 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1611 * iflib_sw_tx_desc_array structure, storing all the information that
1612 * is needed to transmit a packet on the wire. This is called only
1613 * once at attach, setup is done every reset.
1615 **********************************************************************/
1617 iflib_txsd_alloc(iflib_txq_t txq)
1619 if_ctx_t ctx = txq->ift_ctx;
1620 if_shared_ctx_t sctx = ctx->ifc_sctx;
1621 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1622 device_t dev = ctx->ifc_dev;
1623 bus_size_t tsomaxsize;
1624 int err, nsegments, ntsosegments;
1627 nsegments = scctx->isc_tx_nsegments;
1628 ntsosegments = scctx->isc_tx_tso_segments_max;
1629 tsomaxsize = scctx->isc_tx_tso_size_max;
1630 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1631 tsomaxsize += sizeof(struct ether_vlan_header);
1632 MPASS(scctx->isc_ntxd[0] > 0);
1633 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1634 MPASS(nsegments > 0);
1635 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1636 MPASS(ntsosegments > 0);
1637 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1641 * Set up DMA tags for TX buffers.
1643 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1644 1, 0, /* alignment, bounds */
1645 BUS_SPACE_MAXADDR, /* lowaddr */
1646 BUS_SPACE_MAXADDR, /* highaddr */
1647 NULL, NULL, /* filter, filterarg */
1648 sctx->isc_tx_maxsize, /* maxsize */
1649 nsegments, /* nsegments */
1650 sctx->isc_tx_maxsegsize, /* maxsegsize */
1652 NULL, /* lockfunc */
1653 NULL, /* lockfuncarg */
1654 &txq->ift_buf_tag))) {
1655 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1656 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1657 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1660 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1661 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1662 1, 0, /* alignment, bounds */
1663 BUS_SPACE_MAXADDR, /* lowaddr */
1664 BUS_SPACE_MAXADDR, /* highaddr */
1665 NULL, NULL, /* filter, filterarg */
1666 tsomaxsize, /* maxsize */
1667 ntsosegments, /* nsegments */
1668 sctx->isc_tso_maxsegsize,/* maxsegsize */
1670 NULL, /* lockfunc */
1671 NULL, /* lockfuncarg */
1672 &txq->ift_tso_buf_tag))) {
1673 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1678 /* Allocate memory for the TX mbuf map. */
1679 if (!(txq->ift_sds.ifsd_m =
1680 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1681 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1682 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1688 * Create the DMA maps for TX buffers.
1690 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1691 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1692 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1694 "Unable to allocate TX buffer DMA map memory\n");
1698 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1699 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1700 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1702 "Unable to allocate TSO TX buffer map memory\n");
1706 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1707 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1708 &txq->ift_sds.ifsd_map[i]);
1710 device_printf(dev, "Unable to create TX DMA map\n");
1715 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1716 &txq->ift_sds.ifsd_tso_map[i]);
1718 device_printf(dev, "Unable to create TSO TX DMA map\n");
1724 /* We free all, it handles case where we are in the middle */
1725 iflib_tx_structures_free(ctx);
1730 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1735 if (txq->ift_sds.ifsd_map != NULL)
1736 map = txq->ift_sds.ifsd_map[i];
1738 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1739 bus_dmamap_unload(txq->ift_buf_tag, map);
1740 bus_dmamap_destroy(txq->ift_buf_tag, map);
1741 txq->ift_sds.ifsd_map[i] = NULL;
1745 if (txq->ift_sds.ifsd_tso_map != NULL)
1746 map = txq->ift_sds.ifsd_tso_map[i];
1748 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1749 BUS_DMASYNC_POSTWRITE);
1750 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1751 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1752 txq->ift_sds.ifsd_tso_map[i] = NULL;
1757 iflib_txq_destroy(iflib_txq_t txq)
1759 if_ctx_t ctx = txq->ift_ctx;
1761 for (int i = 0; i < txq->ift_size; i++)
1762 iflib_txsd_destroy(ctx, txq, i);
1763 if (txq->ift_sds.ifsd_map != NULL) {
1764 free(txq->ift_sds.ifsd_map, M_IFLIB);
1765 txq->ift_sds.ifsd_map = NULL;
1767 if (txq->ift_sds.ifsd_tso_map != NULL) {
1768 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1769 txq->ift_sds.ifsd_tso_map = NULL;
1771 if (txq->ift_sds.ifsd_m != NULL) {
1772 free(txq->ift_sds.ifsd_m, M_IFLIB);
1773 txq->ift_sds.ifsd_m = NULL;
1775 if (txq->ift_buf_tag != NULL) {
1776 bus_dma_tag_destroy(txq->ift_buf_tag);
1777 txq->ift_buf_tag = NULL;
1779 if (txq->ift_tso_buf_tag != NULL) {
1780 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1781 txq->ift_tso_buf_tag = NULL;
1786 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1790 mp = &txq->ift_sds.ifsd_m[i];
1794 if (txq->ift_sds.ifsd_map != NULL) {
1795 bus_dmamap_sync(txq->ift_buf_tag,
1796 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1797 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1799 if (txq->ift_sds.ifsd_tso_map != NULL) {
1800 bus_dmamap_sync(txq->ift_tso_buf_tag,
1801 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1802 bus_dmamap_unload(txq->ift_tso_buf_tag,
1803 txq->ift_sds.ifsd_tso_map[i]);
1806 DBG_COUNTER_INC(tx_frees);
1811 iflib_txq_setup(iflib_txq_t txq)
1813 if_ctx_t ctx = txq->ift_ctx;
1814 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1815 if_shared_ctx_t sctx = ctx->ifc_sctx;
1816 iflib_dma_info_t di;
1819 /* Set number of descriptors available */
1820 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1821 /* XXX make configurable */
1822 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1825 txq->ift_cidx_processed = 0;
1826 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1827 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1829 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1830 bzero((void *)di->idi_vaddr, di->idi_size);
1832 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1833 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1834 bus_dmamap_sync(di->idi_tag, di->idi_map,
1835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1839 /*********************************************************************
1841 * Allocate DMA resources for RX buffers as well as memory for the RX
1842 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1843 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1844 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1845 * Since we use use one entry in iflib_sw_rx_desc_array per received
1846 * packet, the maximum number of entries we'll need is equal to the
1847 * number of hardware receive descriptors that we've allocated.
1849 **********************************************************************/
1851 iflib_rxsd_alloc(iflib_rxq_t rxq)
1853 if_ctx_t ctx = rxq->ifr_ctx;
1854 if_shared_ctx_t sctx = ctx->ifc_sctx;
1855 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1856 device_t dev = ctx->ifc_dev;
1860 MPASS(scctx->isc_nrxd[0] > 0);
1861 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1864 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1865 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1866 /* Set up DMA tag for RX buffers. */
1867 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1868 1, 0, /* alignment, bounds */
1869 BUS_SPACE_MAXADDR, /* lowaddr */
1870 BUS_SPACE_MAXADDR, /* highaddr */
1871 NULL, NULL, /* filter, filterarg */
1872 sctx->isc_rx_maxsize, /* maxsize */
1873 sctx->isc_rx_nsegments, /* nsegments */
1874 sctx->isc_rx_maxsegsize, /* maxsegsize */
1876 NULL, /* lockfunc */
1881 "Unable to allocate RX DMA tag: %d\n", err);
1885 /* Allocate memory for the RX mbuf map. */
1886 if (!(fl->ifl_sds.ifsd_m =
1887 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1888 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1890 "Unable to allocate RX mbuf map memory\n");
1895 /* Allocate memory for the direct RX cluster pointer map. */
1896 if (!(fl->ifl_sds.ifsd_cl =
1897 (caddr_t *) malloc(sizeof(caddr_t) *
1898 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1900 "Unable to allocate RX cluster map memory\n");
1905 /* Allocate memory for the RX cluster bus address map. */
1906 if (!(fl->ifl_sds.ifsd_ba =
1907 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1908 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1910 "Unable to allocate RX bus address map memory\n");
1916 * Create the DMA maps for RX buffers.
1918 if (!(fl->ifl_sds.ifsd_map =
1919 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1921 "Unable to allocate RX buffer DMA map memory\n");
1925 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1926 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1927 &fl->ifl_sds.ifsd_map[i]);
1929 device_printf(dev, "Unable to create RX buffer DMA map\n");
1937 iflib_rx_structures_free(ctx);
1943 * Internal service routines
1946 struct rxq_refill_cb_arg {
1948 bus_dma_segment_t seg;
1953 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1955 struct rxq_refill_cb_arg *cb_arg = arg;
1957 cb_arg->error = error;
1958 cb_arg->seg = segs[0];
1959 cb_arg->nseg = nseg;
1963 * rxq_refill - refill an rxq free-buffer list
1964 * @ctx: the iflib context
1965 * @rxq: the free-list to refill
1966 * @n: the number of new buffers to allocate
1968 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1969 * The caller must assure that @n does not exceed the queue's capacity.
1972 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1974 struct if_rxd_update iru;
1975 struct rxq_refill_cb_arg cb_arg;
1979 bus_dmamap_t *sd_map;
1980 bus_addr_t bus_addr, *sd_ba;
1981 int err, frag_idx, i, idx, n, pidx;
1984 sd_m = fl->ifl_sds.ifsd_m;
1985 sd_map = fl->ifl_sds.ifsd_map;
1986 sd_cl = fl->ifl_sds.ifsd_cl;
1987 sd_ba = fl->ifl_sds.ifsd_ba;
1988 pidx = fl->ifl_pidx;
1990 frag_idx = fl->ifl_fragidx;
1991 credits = fl->ifl_credits;
1996 MPASS(credits + n <= fl->ifl_size);
1998 if (pidx < fl->ifl_cidx)
1999 MPASS(pidx + n <= fl->ifl_cidx);
2000 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2001 MPASS(fl->ifl_gen == 0);
2002 if (pidx > fl->ifl_cidx)
2003 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2005 DBG_COUNTER_INC(fl_refills);
2007 DBG_COUNTER_INC(fl_refills_large);
2008 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2011 * We allocate an uninitialized mbuf + cluster, mbuf is
2012 * initialized after rx.
2014 * If the cluster is still set then we know a minimum sized packet was received
2016 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2019 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2020 MPASS(frag_idx >= 0);
2021 if ((cl = sd_cl[frag_idx]) == NULL) {
2022 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
2026 MPASS(sd_map != NULL);
2027 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2028 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2030 if (err != 0 || cb_arg.error) {
2034 if (fl->ifl_zone == zone_pack)
2035 uma_zfree(fl->ifl_zone, cl);
2039 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2040 BUS_DMASYNC_PREREAD);
2041 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2042 sd_cl[frag_idx] = cl;
2044 fl->ifl_cl_enqueued++;
2047 bus_addr = sd_ba[frag_idx];
2050 MPASS(sd_m[frag_idx] == NULL);
2051 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2055 bit_set(fl->ifl_rx_bitmap, frag_idx);
2057 fl->ifl_m_enqueued++;
2060 DBG_COUNTER_INC(rx_allocs);
2061 fl->ifl_rxd_idxs[i] = frag_idx;
2062 fl->ifl_bus_addrs[i] = bus_addr;
2063 fl->ifl_vm_addrs[i] = cl;
2066 MPASS(credits <= fl->ifl_size);
2067 if (++idx == fl->ifl_size) {
2071 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2072 iru.iru_pidx = pidx;
2074 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2078 fl->ifl_credits = credits;
2083 iru.iru_pidx = pidx;
2085 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2087 fl->ifl_credits = credits;
2089 DBG_COUNTER_INC(rxd_flush);
2090 if (fl->ifl_pidx == 0)
2091 pidx = fl->ifl_size - 1;
2093 pidx = fl->ifl_pidx - 1;
2095 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2097 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2098 fl->ifl_fragidx = frag_idx;
2101 static __inline void
2102 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2104 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2105 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2107 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2110 MPASS(fl->ifl_credits <= fl->ifl_size);
2111 MPASS(reclaimable == delta);
2113 if (reclaimable > 0)
2114 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2118 iflib_in_detach(if_ctx_t ctx)
2122 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2128 iflib_fl_bufs_free(iflib_fl_t fl)
2130 iflib_dma_info_t idi = fl->ifl_ifdi;
2131 bus_dmamap_t sd_map;
2134 for (i = 0; i < fl->ifl_size; i++) {
2135 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2136 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2138 if (*sd_cl != NULL) {
2139 sd_map = fl->ifl_sds.ifsd_map[i];
2140 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2141 BUS_DMASYNC_POSTREAD);
2142 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2144 uma_zfree(fl->ifl_zone, *sd_cl);
2145 // XXX: Should this get moved out?
2146 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2147 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2148 if (*sd_m != NULL) {
2149 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2150 uma_zfree(zone_mbuf, *sd_m);
2153 MPASS(*sd_cl == NULL);
2154 MPASS(*sd_m == NULL);
2157 fl->ifl_m_dequeued++;
2158 fl->ifl_cl_dequeued++;
2164 for (i = 0; i < fl->ifl_size; i++) {
2165 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2166 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2170 * Reset free list values
2172 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2173 bzero(idi->idi_vaddr, idi->idi_size);
2176 /*********************************************************************
2178 * Initialize a receive ring and its buffers.
2180 **********************************************************************/
2182 iflib_fl_setup(iflib_fl_t fl)
2184 iflib_rxq_t rxq = fl->ifl_rxq;
2185 if_ctx_t ctx = rxq->ifr_ctx;
2187 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2189 ** Free current RX buffer structs and their mbufs
2191 iflib_fl_bufs_free(fl);
2192 /* Now replenish the mbufs */
2193 MPASS(fl->ifl_credits == 0);
2194 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2195 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2196 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2197 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2198 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2201 /* avoid pre-allocating zillions of clusters to an idle card
2202 * potentially speeding up attach
2204 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2205 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2206 if (min(128, fl->ifl_size) != fl->ifl_credits)
2212 MPASS(fl->ifl_ifdi != NULL);
2213 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2214 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2218 /*********************************************************************
2220 * Free receive ring data structures
2222 **********************************************************************/
2224 iflib_rx_sds_free(iflib_rxq_t rxq)
2229 if (rxq->ifr_fl != NULL) {
2230 for (i = 0; i < rxq->ifr_nfl; i++) {
2231 fl = &rxq->ifr_fl[i];
2232 if (fl->ifl_buf_tag != NULL) {
2233 if (fl->ifl_sds.ifsd_map != NULL) {
2234 for (j = 0; j < fl->ifl_size; j++) {
2235 if (fl->ifl_sds.ifsd_map[j] ==
2240 fl->ifl_sds.ifsd_map[j],
2241 BUS_DMASYNC_POSTREAD);
2244 fl->ifl_sds.ifsd_map[j]);
2247 bus_dma_tag_destroy(fl->ifl_buf_tag);
2248 fl->ifl_buf_tag = NULL;
2250 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2251 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2252 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2253 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2254 fl->ifl_sds.ifsd_m = NULL;
2255 fl->ifl_sds.ifsd_cl = NULL;
2256 fl->ifl_sds.ifsd_ba = NULL;
2257 fl->ifl_sds.ifsd_map = NULL;
2259 free(rxq->ifr_fl, M_IFLIB);
2261 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2266 * MI independent logic
2270 iflib_timer(void *arg)
2272 iflib_txq_t txq = arg;
2273 if_ctx_t ctx = txq->ift_ctx;
2274 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2275 uint64_t this_tick = ticks;
2276 uint32_t reset_on = hz / 2;
2278 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2281 ** Check on the state of the TX queue(s), this
2282 ** can be done without the lock because its RO
2283 ** and the HUNG state will be static if set.
2285 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2286 txq->ift_last_timer_tick = this_tick;
2287 IFDI_TIMER(ctx, txq->ift_id);
2288 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2289 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2290 (sctx->isc_pause_frames == 0)))
2293 if (ifmp_ring_is_stalled(txq->ift_br))
2294 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2295 txq->ift_cleaned_prev = txq->ift_cleaned;
2298 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2299 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2301 /* handle any laggards */
2302 if (txq->ift_db_pending)
2303 GROUPTASK_ENQUEUE(&txq->ift_task);
2305 sctx->isc_pause_frames = 0;
2306 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2307 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2310 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2311 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2313 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2314 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2315 iflib_admin_intr_deferred(ctx);
2320 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2322 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2325 * XXX don't set the max_frame_size to larger
2326 * than the hardware can handle
2328 if (sctx->isc_max_frame_size <= MCLBYTES)
2329 ctx->ifc_rx_mbuf_sz = MCLBYTES;
2331 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2335 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2337 return (ctx->ifc_rx_mbuf_sz);
2341 iflib_init_locked(if_ctx_t ctx)
2343 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2344 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2345 if_t ifp = ctx->ifc_ifp;
2349 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2352 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2353 IFDI_INTR_DISABLE(ctx);
2355 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2356 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2357 /* Set hardware offload abilities */
2358 if_clearhwassist(ifp);
2359 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2360 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2361 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2362 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2363 if (if_getcapenable(ifp) & IFCAP_TSO4)
2364 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2365 if (if_getcapenable(ifp) & IFCAP_TSO6)
2366 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2368 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2370 callout_stop(&txq->ift_timer);
2371 CALLOUT_UNLOCK(txq);
2372 iflib_netmap_txq_init(ctx, txq);
2376 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2377 * that drivers can use the value when setting up the hardware receive
2380 iflib_calc_rx_mbuf_sz(ctx);
2383 i = if_getdrvflags(ifp);
2386 MPASS(if_getdrvflags(ifp) == i);
2387 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2388 /* XXX this should really be done on a per-queue basis */
2389 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2390 MPASS(rxq->ifr_id == i);
2391 iflib_netmap_rxq_init(ctx, rxq);
2394 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2395 if (iflib_fl_setup(fl)) {
2396 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2402 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2403 IFDI_INTR_ENABLE(ctx);
2404 txq = ctx->ifc_txqs;
2405 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2406 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2407 txq->ift_timer.c_cpu);
2411 iflib_media_change(if_t ifp)
2413 if_ctx_t ctx = if_getsoftc(ifp);
2417 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2418 iflib_init_locked(ctx);
2424 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2426 if_ctx_t ctx = if_getsoftc(ifp);
2429 IFDI_UPDATE_ADMIN_STATUS(ctx);
2430 IFDI_MEDIA_STATUS(ctx, ifmr);
2435 iflib_stop(if_ctx_t ctx)
2437 iflib_txq_t txq = ctx->ifc_txqs;
2438 iflib_rxq_t rxq = ctx->ifc_rxqs;
2439 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2440 if_shared_ctx_t sctx = ctx->ifc_sctx;
2441 iflib_dma_info_t di;
2445 /* Tell the stack that the interface is no longer active */
2446 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2448 IFDI_INTR_DISABLE(ctx);
2453 iflib_debug_reset();
2454 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2455 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2456 /* make sure all transmitters have completed before proceeding XXX */
2459 callout_stop(&txq->ift_timer);
2460 CALLOUT_UNLOCK(txq);
2462 /* clean any enqueued buffers */
2463 iflib_ifmp_purge(txq);
2464 /* Free any existing tx buffers. */
2465 for (j = 0; j < txq->ift_size; j++) {
2466 iflib_txsd_free(ctx, txq, j);
2468 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2469 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2470 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2471 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2472 txq->ift_pullups = 0;
2473 ifmp_ring_reset_stats(txq->ift_br);
2474 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2475 bzero((void *)di->idi_vaddr, di->idi_size);
2477 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2478 /* make sure all transmitters have completed before proceeding XXX */
2480 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2481 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2482 bzero((void *)di->idi_vaddr, di->idi_size);
2483 /* also resets the free lists pidx/cidx */
2484 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2485 iflib_fl_bufs_free(fl);
2489 static inline caddr_t
2490 calc_next_rxd(iflib_fl_t fl, int cidx)
2494 caddr_t start, end, cur, next;
2496 nrxd = fl->ifl_size;
2497 size = fl->ifl_rxd_size;
2498 start = fl->ifl_ifdi->idi_vaddr;
2500 if (__predict_false(size == 0))
2502 cur = start + size*cidx;
2503 end = start + size*nrxd;
2504 next = CACHE_PTR_NEXT(cur);
2505 return (next < end ? next : start);
2509 prefetch_pkts(iflib_fl_t fl, int cidx)
2512 int nrxd = fl->ifl_size;
2516 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2517 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2518 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2519 next_rxd = calc_next_rxd(fl, cidx);
2521 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2522 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2523 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2524 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2525 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2526 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2527 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2528 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2532 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2537 iflib_dma_info_t di;
2541 flid = irf->irf_flid;
2542 cidx = irf->irf_idx;
2543 fl = &rxq->ifr_fl[flid];
2545 sd->ifsd_cidx = cidx;
2546 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2547 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2550 fl->ifl_m_dequeued++;
2552 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2553 prefetch_pkts(fl, cidx);
2554 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2555 prefetch(&fl->ifl_sds.ifsd_map[next]);
2556 map = fl->ifl_sds.ifsd_map[cidx];
2558 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2560 /* not valid assert if bxe really does SGE from non-contiguous elements */
2561 MPASS(fl->ifl_cidx == cidx);
2562 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2564 bus_dmamap_unload(fl->ifl_buf_tag, map);
2565 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2566 if (__predict_false(fl->ifl_cidx == 0))
2568 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2570 bit_clear(fl->ifl_rx_bitmap, cidx);
2573 static struct mbuf *
2574 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2576 int i, padlen , flags;
2577 struct mbuf *m, *mh, *mt;
2583 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2585 MPASS(*sd->ifsd_cl != NULL);
2586 MPASS(*sd->ifsd_m != NULL);
2588 /* Don't include zero-length frags */
2589 if (ri->iri_frags[i].irf_len == 0) {
2590 /* XXX we can save the cluster here, but not the mbuf */
2591 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2592 m_free(*sd->ifsd_m);
2599 flags = M_PKTHDR|M_EXT;
2601 padlen = ri->iri_pad;
2606 /* assuming padding is only on the first fragment */
2610 *sd->ifsd_cl = NULL;
2612 /* Can these two be made one ? */
2613 m_init(m, M_NOWAIT, MT_DATA, flags);
2614 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2616 * These must follow m_init and m_cljset
2618 m->m_data += padlen;
2619 ri->iri_len -= padlen;
2620 m->m_len = ri->iri_frags[i].irf_len;
2621 } while (++i < ri->iri_nfrags);
2627 * Process one software descriptor
2629 static struct mbuf *
2630 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2635 /* should I merge this back in now that the two paths are basically duplicated? */
2636 if (ri->iri_nfrags == 1 &&
2637 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2638 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2641 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2642 #ifndef __NO_STRICT_ALIGNMENT
2646 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2647 bus_dmamap_sync(rxq->ifr_fl->ifl_buf_tag,
2648 rxq->ifr_fl->ifl_sds.ifsd_map[ri->iri_frags[0].irf_idx],
2649 BUS_DMASYNC_PREREAD);
2650 m->m_len = ri->iri_frags[0].irf_len;
2652 m = assemble_segments(rxq, ri, &sd);
2654 m->m_pkthdr.len = ri->iri_len;
2655 m->m_pkthdr.rcvif = ri->iri_ifp;
2656 m->m_flags |= ri->iri_flags;
2657 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2658 m->m_pkthdr.flowid = ri->iri_flowid;
2659 M_HASHTYPE_SET(m, ri->iri_rsstype);
2660 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2661 m->m_pkthdr.csum_data = ri->iri_csum_data;
2665 #if defined(INET6) || defined(INET)
2667 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2669 CURVNET_SET(lc->ifp->if_vnet);
2671 *v6 = VNET(ip6_forwarding);
2674 *v4 = VNET(ipforwarding);
2680 * Returns true if it's possible this packet could be LROed.
2681 * if it returns false, it is guaranteed that tcp_lro_rx()
2682 * would not return zero.
2685 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2687 struct ether_header *eh;
2690 eh = mtod(m, struct ether_header *);
2691 eh_type = ntohs(eh->ether_type);
2694 case ETHERTYPE_IPV6:
2695 return !v6_forwarding;
2699 return !v4_forwarding;
2707 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2713 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2715 if_ctx_t ctx = rxq->ifr_ctx;
2716 if_shared_ctx_t sctx = ctx->ifc_sctx;
2717 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2718 iflib_dma_info_t di;
2721 struct if_rxd_info ri;
2722 int err, budget_left, rx_bytes, rx_pkts;
2726 bool v4_forwarding, v6_forwarding, lro_possible;
2729 * XXX early demux data packets so that if_input processing only handles
2730 * acks in interrupt context
2732 struct mbuf *m, *mh, *mt, *mf;
2734 lro_possible = v4_forwarding = v6_forwarding = false;
2738 rx_pkts = rx_bytes = 0;
2739 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2740 cidxp = &rxq->ifr_cq_cidx;
2742 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2743 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2744 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2745 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2746 DBG_COUNTER_INC(rx_unavail);
2750 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2751 if (__predict_false(!CTX_ACTIVE(ctx))) {
2752 DBG_COUNTER_INC(rx_ctx_inactive);
2756 * Reset client set fields to their default values
2759 ri.iri_qsidx = rxq->ifr_id;
2760 ri.iri_cidx = *cidxp;
2762 ri.iri_frags = rxq->ifr_frags;
2763 di = rxq->ifr_fl[rxq->ifr_frags[0].irf_flid].ifl_ifdi;
2764 bus_dmamap_sync(di->idi_tag, di->idi_map,
2765 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2766 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2770 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2771 *cidxp = ri.iri_cidx;
2772 /* Update our consumer index */
2773 /* XXX NB: shurd - check if this is still safe */
2774 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2775 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2776 rxq->ifr_cq_gen = 0;
2778 /* was this only a completion queue message? */
2779 if (__predict_false(ri.iri_nfrags == 0))
2782 MPASS(ri.iri_nfrags != 0);
2783 MPASS(ri.iri_len != 0);
2785 /* will advance the cidx on the corresponding free lists */
2786 m = iflib_rxd_pkt_get(rxq, &ri);
2789 if (avail == 0 && budget_left)
2790 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2792 if (__predict_false(m == NULL)) {
2793 DBG_COUNTER_INC(rx_mbuf_null);
2796 /* imm_pkt: -- cxgb */
2804 /* make sure that we can refill faster than drain */
2805 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2806 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2808 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2810 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2812 while (mh != NULL) {
2815 m->m_nextpkt = NULL;
2816 #ifndef __NO_STRICT_ALIGNMENT
2817 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2820 rx_bytes += m->m_pkthdr.len;
2822 #if defined(INET6) || defined(INET)
2824 if (!lro_possible) {
2825 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2826 if (lro_possible && mf != NULL) {
2827 ifp->if_input(ifp, mf);
2828 DBG_COUNTER_INC(rx_if_input);
2832 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2833 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2834 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2840 ifp->if_input(ifp, m);
2841 DBG_COUNTER_INC(rx_if_input);
2852 ifp->if_input(ifp, mf);
2853 DBG_COUNTER_INC(rx_if_input);
2856 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2857 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2860 * Flush any outstanding LRO work
2862 #if defined(INET6) || defined(INET)
2863 tcp_lro_flush_all(&rxq->ifr_lc);
2867 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2870 ctx->ifc_flags |= IFC_DO_RESET;
2871 iflib_admin_intr_deferred(ctx);
2876 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2877 static inline qidx_t
2878 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2880 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2881 qidx_t minthresh = txq->ift_size / 8;
2882 if (in_use > 4*minthresh)
2883 return (notify_count);
2884 if (in_use > 2*minthresh)
2885 return (notify_count >> 1);
2886 if (in_use > minthresh)
2887 return (notify_count >> 3);
2891 static inline qidx_t
2892 txq_max_rs_deferred(iflib_txq_t txq)
2894 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2895 qidx_t minthresh = txq->ift_size / 8;
2896 if (txq->ift_in_use > 4*minthresh)
2897 return (notify_count);
2898 if (txq->ift_in_use > 2*minthresh)
2899 return (notify_count >> 1);
2900 if (txq->ift_in_use > minthresh)
2901 return (notify_count >> 2);
2905 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2906 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2908 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2909 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2910 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2912 /* forward compatibility for cxgb */
2913 #define FIRST_QSET(ctx) 0
2914 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2915 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2916 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2917 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2919 /* XXX we should be setting this to something other than zero */
2920 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2921 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2922 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2925 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2931 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2932 if (ring || txq->ift_db_pending >= max) {
2933 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2934 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2935 txq->ift_db_pending = txq->ift_npending = 0;
2943 print_pkt(if_pkt_info_t pi)
2945 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2946 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2947 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2948 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2949 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2950 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2954 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2955 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2956 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2957 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2960 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2962 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2963 struct ether_vlan_header *eh;
2967 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2968 M_WRITABLE(m) == 0) {
2969 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2973 DBG_COUNTER_INC(tx_frees);
2979 * Determine where frame payload starts.
2980 * Jump over vlan headers if already present,
2981 * helpful for QinQ too.
2983 if (__predict_false(m->m_len < sizeof(*eh))) {
2985 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2988 eh = mtod(m, struct ether_vlan_header *);
2989 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2990 pi->ipi_etype = ntohs(eh->evl_proto);
2991 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2993 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2994 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2997 switch (pi->ipi_etype) {
3002 struct ip *ip = NULL;
3003 struct tcphdr *th = NULL;
3006 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3007 if (__predict_false(m->m_len < minthlen)) {
3009 * if this code bloat is causing too much of a hit
3010 * move it to a separate function and mark it noinline
3012 if (m->m_len == pi->ipi_ehdrlen) {
3015 if (n->m_len >= sizeof(*ip)) {
3016 ip = (struct ip *)n->m_data;
3017 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3018 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3021 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3023 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3027 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3029 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3030 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3031 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3034 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3035 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3036 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3038 pi->ipi_ip_hlen = ip->ip_hl << 2;
3039 pi->ipi_ipproto = ip->ip_p;
3040 pi->ipi_flags |= IPI_TX_IPV4;
3042 /* TCP checksum offload may require TCP header length */
3043 if (IS_TX_OFFLOAD4(pi)) {
3044 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3045 if (__predict_false(th == NULL)) {
3047 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3049 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3051 pi->ipi_tcp_hflags = th->th_flags;
3052 pi->ipi_tcp_hlen = th->th_off << 2;
3053 pi->ipi_tcp_seq = th->th_seq;
3056 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3059 * TSO always requires hardware checksum offload.
3061 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3062 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3063 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3064 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3065 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3067 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3071 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3078 case ETHERTYPE_IPV6:
3080 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3082 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3084 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3086 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3089 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3091 /* XXX-BZ this will go badly in case of ext hdrs. */
3092 pi->ipi_ipproto = ip6->ip6_nxt;
3093 pi->ipi_flags |= IPI_TX_IPV6;
3095 /* TCP checksum offload may require TCP header length */
3096 if (IS_TX_OFFLOAD6(pi)) {
3097 if (pi->ipi_ipproto == IPPROTO_TCP) {
3098 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3100 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3103 pi->ipi_tcp_hflags = th->th_flags;
3104 pi->ipi_tcp_hlen = th->th_off << 2;
3105 pi->ipi_tcp_seq = th->th_seq;
3108 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3111 * TSO always requires hardware checksum offload.
3113 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3114 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3115 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3122 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3123 pi->ipi_ip_hlen = 0;
3132 * If dodgy hardware rejects the scatter gather chain we've handed it
3133 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3136 static __noinline struct mbuf *
3137 iflib_remove_mbuf(iflib_txq_t txq)
3140 struct mbuf *m, **ifsd_m;
3142 ifsd_m = txq->ift_sds.ifsd_m;
3143 ntxd = txq->ift_size;
3144 pidx = txq->ift_pidx & (ntxd - 1);
3145 ifsd_m = txq->ift_sds.ifsd_m;
3147 ifsd_m[pidx] = NULL;
3148 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3149 if (txq->ift_sds.ifsd_tso_map != NULL)
3150 bus_dmamap_unload(txq->ift_tso_buf_tag,
3151 txq->ift_sds.ifsd_tso_map[pidx]);
3153 txq->ift_dequeued++;
3158 static inline caddr_t
3159 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3163 caddr_t start, end, cur, next;
3165 ntxd = txq->ift_size;
3166 size = txq->ift_txd_size[qid];
3167 start = txq->ift_ifdi[qid].idi_vaddr;
3169 if (__predict_false(size == 0))
3171 cur = start + size*cidx;
3172 end = start + size*ntxd;
3173 next = CACHE_PTR_NEXT(cur);
3174 return (next < end ? next : start);
3178 * Pad an mbuf to ensure a minimum ethernet frame size.
3179 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3181 static __noinline int
3182 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3185 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3186 * and ARP message is the smallest common payload I can think of
3188 static char pad[18]; /* just zeros */
3190 struct mbuf *new_head;
3192 if (!M_WRITABLE(*m_head)) {
3193 new_head = m_dup(*m_head, M_NOWAIT);
3194 if (new_head == NULL) {
3196 device_printf(dev, "cannot pad short frame, m_dup() failed");
3197 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3198 DBG_COUNTER_INC(tx_frees);
3205 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3206 n > 0; n -= sizeof(pad))
3207 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3212 device_printf(dev, "cannot pad short frame\n");
3213 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3214 DBG_COUNTER_INC(tx_frees);
3222 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3225 if_shared_ctx_t sctx;
3226 if_softc_ctx_t scctx;
3227 bus_dma_tag_t buf_tag;
3228 bus_dma_segment_t *segs;
3229 struct mbuf *m_head, **ifsd_m;
3232 struct if_pkt_info pi;
3234 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3237 sctx = ctx->ifc_sctx;
3238 scctx = &ctx->ifc_softc_ctx;
3239 segs = txq->ift_segs;
3240 ntxd = txq->ift_size;
3245 * If we're doing TSO the next descriptor to clean may be quite far ahead
3247 cidx = txq->ift_cidx;
3248 pidx = txq->ift_pidx;
3249 if (ctx->ifc_flags & IFC_PREFETCH) {
3250 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3251 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3252 next_txd = calc_next_txd(txq, cidx, 0);
3256 /* prefetch the next cache line of mbuf pointers and flags */
3257 prefetch(&txq->ift_sds.ifsd_m[next]);
3258 prefetch(&txq->ift_sds.ifsd_map[next]);
3259 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3261 map = txq->ift_sds.ifsd_map[pidx];
3262 ifsd_m = txq->ift_sds.ifsd_m;
3264 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3265 buf_tag = txq->ift_tso_buf_tag;
3266 max_segs = scctx->isc_tx_tso_segments_max;
3267 map = txq->ift_sds.ifsd_tso_map[pidx];
3268 MPASS(buf_tag != NULL);
3269 MPASS(max_segs > 0);
3271 buf_tag = txq->ift_buf_tag;
3272 max_segs = scctx->isc_tx_nsegments;
3273 map = txq->ift_sds.ifsd_map[pidx];
3275 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3276 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3277 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3279 DBG_COUNTER_INC(encap_txd_encap_fail);
3286 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3288 pi.ipi_qsidx = txq->ift_id;
3289 pi.ipi_len = m_head->m_pkthdr.len;
3290 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3291 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3293 /* deliberate bitwise OR to make one condition */
3294 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3295 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3296 DBG_COUNTER_INC(encap_txd_encap_fail);
3303 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3306 if (__predict_false(err)) {
3309 /* try collapse once and defrag once */
3311 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3312 /* try defrag if collapsing fails */
3317 txq->ift_mbuf_defrag++;
3318 m_head = m_defrag(*m_headp, M_NOWAIT);
3321 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3322 * failed to map an mbuf that was run through m_defrag
3325 if (__predict_false(m_head == NULL || remap > 1))
3332 txq->ift_no_tx_dma_setup++;
3335 txq->ift_no_tx_dma_setup++;
3337 DBG_COUNTER_INC(tx_frees);
3341 txq->ift_map_failed++;
3342 DBG_COUNTER_INC(encap_load_mbuf_fail);
3343 DBG_COUNTER_INC(encap_txd_encap_fail);
3346 ifsd_m[pidx] = m_head;
3348 * XXX assumes a 1 to 1 relationship between segments and
3349 * descriptors - this does not hold true on all drivers, e.g.
3352 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3353 txq->ift_no_desc_avail++;
3354 bus_dmamap_unload(buf_tag, map);
3355 DBG_COUNTER_INC(encap_txq_avail_fail);
3356 DBG_COUNTER_INC(encap_txd_encap_fail);
3357 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3358 GROUPTASK_ENQUEUE(&txq->ift_task);
3362 * On Intel cards we can greatly reduce the number of TX interrupts
3363 * we see by only setting report status on every Nth descriptor.
3364 * However, this also means that the driver will need to keep track
3365 * of the descriptors that RS was set on to check them for the DD bit.
3367 txq->ift_rs_pending += nsegs + 1;
3368 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3369 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3370 pi.ipi_flags |= IPI_TX_INTR;
3371 txq->ift_rs_pending = 0;
3375 pi.ipi_nsegs = nsegs;
3377 MPASS(pidx >= 0 && pidx < txq->ift_size);
3381 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3382 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3383 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3385 DBG_COUNTER_INC(tx_encap);
3386 MPASS(pi.ipi_new_pidx < txq->ift_size);
3388 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3389 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3390 ndesc += txq->ift_size;
3394 * drivers can need as many as
3397 MPASS(ndesc <= pi.ipi_nsegs + 2);
3398 MPASS(pi.ipi_new_pidx != pidx);
3400 txq->ift_in_use += ndesc;
3403 * We update the last software descriptor again here because there may
3404 * be a sentinel and/or there may be more mbufs than segments
3406 txq->ift_pidx = pi.ipi_new_pidx;
3407 txq->ift_npending += pi.ipi_ndescs;
3409 *m_headp = m_head = iflib_remove_mbuf(txq);
3411 txq->ift_txd_encap_efbig++;
3420 * err can't possibly be non-zero here, so we don't neet to test it
3421 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3426 txq->ift_mbuf_defrag_failed++;
3427 txq->ift_map_failed++;
3429 DBG_COUNTER_INC(tx_frees);
3431 DBG_COUNTER_INC(encap_txd_encap_fail);
3436 iflib_tx_desc_free(iflib_txq_t txq, int n)
3438 uint32_t qsize, cidx, mask, gen;
3439 struct mbuf *m, **ifsd_m;
3442 cidx = txq->ift_cidx;
3444 qsize = txq->ift_size;
3446 ifsd_m = txq->ift_sds.ifsd_m;
3447 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3451 prefetch(ifsd_m[(cidx + 3) & mask]);
3452 prefetch(ifsd_m[(cidx + 4) & mask]);
3454 if ((m = ifsd_m[cidx]) != NULL) {
3455 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3456 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3457 bus_dmamap_sync(txq->ift_tso_buf_tag,
3458 txq->ift_sds.ifsd_tso_map[cidx],
3459 BUS_DMASYNC_POSTWRITE);
3460 bus_dmamap_unload(txq->ift_tso_buf_tag,
3461 txq->ift_sds.ifsd_tso_map[cidx]);
3463 bus_dmamap_sync(txq->ift_buf_tag,
3464 txq->ift_sds.ifsd_map[cidx],
3465 BUS_DMASYNC_POSTWRITE);
3466 bus_dmamap_unload(txq->ift_buf_tag,
3467 txq->ift_sds.ifsd_map[cidx]);
3469 /* XXX we don't support any drivers that batch packets yet */
3470 MPASS(m->m_nextpkt == NULL);
3472 ifsd_m[cidx] = NULL;
3474 txq->ift_dequeued++;
3476 DBG_COUNTER_INC(tx_frees);
3478 if (__predict_false(++cidx == qsize)) {
3483 txq->ift_cidx = cidx;
3488 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3491 if_ctx_t ctx = txq->ift_ctx;
3493 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3494 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3497 * Need a rate-limiting check so that this isn't called every time
3499 iflib_tx_credits_update(ctx, txq);
3500 reclaim = DESC_RECLAIMABLE(txq);
3502 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3504 if (iflib_verbose_debug) {
3505 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3506 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3513 iflib_tx_desc_free(txq, reclaim);
3514 txq->ift_cleaned += reclaim;
3515 txq->ift_in_use -= reclaim;
3520 static struct mbuf **
3521 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3524 struct mbuf **items;
3527 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3528 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3530 prefetch(items[(cidx + offset) & (size-1)]);
3531 if (remaining > 1) {
3532 prefetch2cachelines(&items[next]);
3533 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3534 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3535 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3537 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3541 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3544 ifmp_ring_check_drainage(txq->ift_br, budget);
3548 iflib_txq_can_drain(struct ifmp_ring *r)
3550 iflib_txq_t txq = r->cookie;
3551 if_ctx_t ctx = txq->ift_ctx;
3553 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3554 BUS_DMASYNC_POSTREAD);
3555 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3556 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3560 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3562 iflib_txq_t txq = r->cookie;
3563 if_ctx_t ctx = txq->ift_ctx;
3564 struct ifnet *ifp = ctx->ifc_ifp;
3565 struct mbuf **mp, *m;
3566 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3567 int reclaimed, err, in_use_prev, desc_used;
3568 bool do_prefetch, ring, rang;
3570 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3571 !LINK_ACTIVE(ctx))) {
3572 DBG_COUNTER_INC(txq_drain_notready);
3575 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3576 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3577 avail = IDXDIFF(pidx, cidx, r->size);
3578 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3579 DBG_COUNTER_INC(txq_drain_flushing);
3580 for (i = 0; i < avail; i++) {
3581 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3582 m_free(r->items[(cidx + i) & (r->size-1)]);
3583 r->items[(cidx + i) & (r->size-1)] = NULL;
3588 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3589 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3591 callout_stop(&txq->ift_timer);
3592 CALLOUT_UNLOCK(txq);
3593 DBG_COUNTER_INC(txq_drain_oactive);
3597 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3598 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3599 count = MIN(avail, TX_BATCH_SIZE);
3601 if (iflib_verbose_debug)
3602 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3603 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3605 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3606 avail = TXQ_AVAIL(txq);
3608 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3609 int rem = do_prefetch ? count - i : 0;
3611 mp = _ring_peek_one(r, cidx, i, rem);
3612 MPASS(mp != NULL && *mp != NULL);
3613 if (__predict_false(*mp == (struct mbuf *)txq)) {
3618 in_use_prev = txq->ift_in_use;
3619 err = iflib_encap(txq, mp);
3620 if (__predict_false(err)) {
3621 /* no room - bail out */
3625 /* we can't send this packet - skip it */
3631 DBG_COUNTER_INC(tx_sent);
3632 bytes_sent += m->m_pkthdr.len;
3633 mcast_sent += !!(m->m_flags & M_MCAST);
3634 avail = TXQ_AVAIL(txq);
3636 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3637 desc_used += (txq->ift_in_use - in_use_prev);
3638 ETHER_BPF_MTAP(ifp, m);
3639 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3641 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3644 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3645 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3646 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3647 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3648 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3650 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3652 if (iflib_verbose_debug)
3653 printf("consumed=%d\n", consumed);
3659 iflib_txq_drain_always(struct ifmp_ring *r)
3665 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3673 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3675 callout_stop(&txq->ift_timer);
3676 CALLOUT_UNLOCK(txq);
3678 avail = IDXDIFF(pidx, cidx, r->size);
3679 for (i = 0; i < avail; i++) {
3680 mp = _ring_peek_one(r, cidx, i, avail - i);
3681 if (__predict_false(*mp == (struct mbuf *)txq))
3684 DBG_COUNTER_INC(tx_frees);
3686 MPASS(ifmp_ring_is_stalled(r) == 0);
3691 iflib_ifmp_purge(iflib_txq_t txq)
3693 struct ifmp_ring *r;
3696 r->drain = iflib_txq_drain_free;
3697 r->can_drain = iflib_txq_drain_always;
3699 ifmp_ring_check_drainage(r, r->size);
3701 r->drain = iflib_txq_drain;
3702 r->can_drain = iflib_txq_can_drain;
3706 _task_fn_tx(void *context)
3708 iflib_txq_t txq = context;
3709 if_ctx_t ctx = txq->ift_ctx;
3710 struct ifnet *ifp = ctx->ifc_ifp;
3711 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3713 #ifdef IFLIB_DIAGNOSTICS
3714 txq->ift_cpu_exec_count[curcpu]++;
3716 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3718 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3719 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3720 BUS_DMASYNC_POSTREAD);
3721 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3722 netmap_tx_irq(ifp, txq->ift_id);
3723 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3727 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3728 iflib_altq_if_start(ifp);
3730 if (txq->ift_db_pending)
3731 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3733 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3735 * When abdicating, we always need to check drainage, not just when we don't enqueue
3738 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3739 if (ctx->ifc_flags & IFC_LEGACY)
3740 IFDI_INTR_ENABLE(ctx);
3745 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3746 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3751 _task_fn_rx(void *context)
3753 iflib_rxq_t rxq = context;
3754 if_ctx_t ctx = rxq->ifr_ctx;
3758 #ifdef IFLIB_DIAGNOSTICS
3759 rxq->ifr_cpu_exec_count[curcpu]++;
3761 DBG_COUNTER_INC(task_fn_rxs);
3762 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3766 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3768 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3773 budget = ctx->ifc_sysctl_rx_budget;
3775 budget = 16; /* XXX */
3776 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3777 if (ctx->ifc_flags & IFC_LEGACY)
3778 IFDI_INTR_ENABLE(ctx);
3783 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3784 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3785 DBG_COUNTER_INC(rx_intr_enables);
3788 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3791 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3795 _task_fn_admin(void *context)
3797 if_ctx_t ctx = context;
3798 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3801 bool oactive, running, do_reset, do_watchdog, in_detach;
3802 uint32_t reset_on = hz / 2;
3805 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3806 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3807 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3808 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3809 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3810 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3813 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3819 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3821 callout_stop(&txq->ift_timer);
3822 CALLOUT_UNLOCK(txq);
3825 ctx->ifc_watchdog_events++;
3826 IFDI_WATCHDOG_RESET(ctx);
3828 IFDI_UPDATE_ADMIN_STATUS(ctx);
3829 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3832 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3833 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3835 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3837 IFDI_LINK_INTR_ENABLE(ctx);
3839 iflib_if_init_locked(ctx);
3842 if (LINK_ACTIVE(ctx) == 0)
3844 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3845 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3850 _task_fn_iov(void *context)
3852 if_ctx_t ctx = context;
3854 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3855 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3859 IFDI_VFLR_HANDLE(ctx);
3864 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3867 if_int_delay_info_t info;
3870 info = (if_int_delay_info_t)arg1;
3871 ctx = info->iidi_ctx;
3872 info->iidi_req = req;
3873 info->iidi_oidp = oidp;
3875 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3880 /*********************************************************************
3884 **********************************************************************/
3887 iflib_if_init_locked(if_ctx_t ctx)
3890 iflib_init_locked(ctx);
3895 iflib_if_init(void *arg)
3900 iflib_if_init_locked(ctx);
3905 iflib_if_transmit(if_t ifp, struct mbuf *m)
3907 if_ctx_t ctx = if_getsoftc(ifp);
3911 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3913 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3914 DBG_COUNTER_INC(tx_frees);
3919 MPASS(m->m_nextpkt == NULL);
3920 /* ALTQ-enabled interfaces always use queue 0. */
3922 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3923 qidx = QIDX(ctx, m);
3925 * XXX calculate buf_ring based on flowid (divvy up bits?)
3927 txq = &ctx->ifc_txqs[qidx];
3929 #ifdef DRIVER_BACKPRESSURE
3930 if (txq->ift_closed) {
3932 next = m->m_nextpkt;
3933 m->m_nextpkt = NULL;
3935 DBG_COUNTER_INC(tx_frees);
3947 next = next->m_nextpkt;
3948 } while (next != NULL);
3950 if (count > nitems(marr))
3951 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3952 /* XXX check nextpkt */
3954 /* XXX simplify for now */
3955 DBG_COUNTER_INC(tx_frees);
3958 for (next = m, i = 0; next != NULL; i++) {
3960 next = next->m_nextpkt;
3961 mp[i]->m_nextpkt = NULL;
3964 DBG_COUNTER_INC(tx_seen);
3965 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3968 GROUPTASK_ENQUEUE(&txq->ift_task);
3971 GROUPTASK_ENQUEUE(&txq->ift_task);
3972 /* support forthcoming later */
3973 #ifdef DRIVER_BACKPRESSURE
3974 txq->ift_closed = TRUE;
3976 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3978 DBG_COUNTER_INC(tx_frees);
3986 * The overall approach to integrating iflib with ALTQ is to continue to use
3987 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3988 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
3989 * is redundant/unnecessary, but doing so minimizes the amount of
3990 * ALTQ-specific code required in iflib. It is assumed that the overhead of
3991 * redundantly queueing to an intermediate mp_ring is swamped by the
3992 * performance limitations inherent in using ALTQ.
3994 * When ALTQ support is compiled in, all iflib drivers will use a transmit
3995 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
3996 * given interface. If ALTQ is enabled for an interface, then all
3997 * transmitted packets for that interface will be submitted to the ALTQ
3998 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
3999 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4000 * update stats that the iflib machinery handles, and which is sensitve to
4001 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4002 * will be installed as the start routine for use by ALTQ facilities that
4003 * need to trigger queue drains on a scheduled basis.
4007 iflib_altq_if_start(if_t ifp)
4009 struct ifaltq *ifq = &ifp->if_snd;
4013 IFQ_DEQUEUE_NOLOCK(ifq, m);
4015 iflib_if_transmit(ifp, m);
4016 IFQ_DEQUEUE_NOLOCK(ifq, m);
4022 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4026 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4027 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4029 iflib_altq_if_start(ifp);
4031 err = iflib_if_transmit(ifp, m);
4038 iflib_if_qflush(if_t ifp)
4040 if_ctx_t ctx = if_getsoftc(ifp);
4041 iflib_txq_t txq = ctx->ifc_txqs;
4045 ctx->ifc_flags |= IFC_QFLUSH;
4047 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4048 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4049 iflib_txq_check_drain(txq, 0);
4051 ctx->ifc_flags &= ~IFC_QFLUSH;
4055 * When ALTQ is enabled, this will also take care of purging the
4062 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4063 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4064 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4065 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4068 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4070 if_ctx_t ctx = if_getsoftc(ifp);
4071 struct ifreq *ifr = (struct ifreq *)data;
4072 #if defined(INET) || defined(INET6)
4073 struct ifaddr *ifa = (struct ifaddr *)data;
4075 bool avoid_reset = FALSE;
4076 int err = 0, reinit = 0, bits;
4081 if (ifa->ifa_addr->sa_family == AF_INET)
4085 if (ifa->ifa_addr->sa_family == AF_INET6)
4089 ** Calling init results in link renegotiation,
4090 ** so we avoid doing it when possible.
4093 if_setflagbits(ifp, IFF_UP,0);
4094 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4097 if (!(if_getflags(ifp) & IFF_NOARP))
4098 arp_ifinit(ifp, ifa);
4101 err = ether_ioctl(ifp, command, data);
4105 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4109 bits = if_getdrvflags(ifp);
4110 /* stop the driver and free any clusters before proceeding */
4113 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4115 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4116 ctx->ifc_flags |= IFC_MULTISEG;
4118 ctx->ifc_flags &= ~IFC_MULTISEG;
4120 err = if_setmtu(ifp, ifr->ifr_mtu);
4122 iflib_init_locked(ctx);
4124 if_setdrvflags(ifp, bits);
4130 if (if_getflags(ifp) & IFF_UP) {
4131 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4132 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4133 (IFF_PROMISC | IFF_ALLMULTI)) {
4134 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4138 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4141 ctx->ifc_if_flags = if_getflags(ifp);
4146 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4148 IFDI_INTR_DISABLE(ctx);
4149 IFDI_MULTI_SET(ctx);
4150 IFDI_INTR_ENABLE(ctx);
4156 IFDI_MEDIA_SET(ctx);
4161 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4165 struct ifi2creq i2c;
4167 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4170 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4174 if (i2c.len > sizeof(i2c.data)) {
4179 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4180 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4186 int mask, setmask, oldmask;
4188 oldmask = if_getcapenable(ifp);
4189 mask = ifr->ifr_reqcap ^ oldmask;
4190 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4193 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4195 setmask |= (mask & IFCAP_FLAGS);
4196 setmask |= (mask & IFCAP_WOL);
4199 * If any RX csum has changed, change all the ones that
4200 * are supported by the driver.
4202 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4203 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4204 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4208 * want to ensure that traffic has stopped before we change any of the flags
4212 bits = if_getdrvflags(ifp);
4213 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4216 if_togglecapenable(ifp, setmask);
4218 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4219 iflib_init_locked(ctx);
4221 if_setdrvflags(ifp, bits);
4228 case SIOCGPRIVATE_0:
4232 err = IFDI_PRIV_IOCTL(ctx, command, data);
4236 err = ether_ioctl(ifp, command, data);
4245 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4247 if_ctx_t ctx = if_getsoftc(ifp);
4249 return (IFDI_GET_COUNTER(ctx, cnt));
4252 /*********************************************************************
4254 * OTHER FUNCTIONS EXPORTED TO THE STACK
4256 **********************************************************************/
4259 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4261 if_ctx_t ctx = if_getsoftc(ifp);
4263 if ((void *)ctx != arg)
4266 if ((vtag == 0) || (vtag > 4095))
4270 IFDI_VLAN_REGISTER(ctx, vtag);
4271 /* Re-init to load the changes */
4272 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4273 iflib_if_init_locked(ctx);
4278 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4280 if_ctx_t ctx = if_getsoftc(ifp);
4282 if ((void *)ctx != arg)
4285 if ((vtag == 0) || (vtag > 4095))
4289 IFDI_VLAN_UNREGISTER(ctx, vtag);
4290 /* Re-init to load the changes */
4291 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4292 iflib_if_init_locked(ctx);
4297 iflib_led_func(void *arg, int onoff)
4302 IFDI_LED_FUNC(ctx, onoff);
4306 /*********************************************************************
4308 * BUS FUNCTION DEFINITIONS
4310 **********************************************************************/
4313 iflib_device_probe(device_t dev)
4315 pci_vendor_info_t *ent;
4317 uint16_t pci_vendor_id, pci_device_id;
4318 uint16_t pci_subvendor_id, pci_subdevice_id;
4319 uint16_t pci_rev_id;
4320 if_shared_ctx_t sctx;
4322 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4325 pci_vendor_id = pci_get_vendor(dev);
4326 pci_device_id = pci_get_device(dev);
4327 pci_subvendor_id = pci_get_subvendor(dev);
4328 pci_subdevice_id = pci_get_subdevice(dev);
4329 pci_rev_id = pci_get_revid(dev);
4330 if (sctx->isc_parse_devinfo != NULL)
4331 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4333 ent = sctx->isc_vendor_info;
4334 while (ent->pvi_vendor_id != 0) {
4335 if (pci_vendor_id != ent->pvi_vendor_id) {
4339 if ((pci_device_id == ent->pvi_device_id) &&
4340 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4341 (ent->pvi_subvendor_id == 0)) &&
4342 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4343 (ent->pvi_subdevice_id == 0)) &&
4344 ((pci_rev_id == ent->pvi_rev_id) ||
4345 (ent->pvi_rev_id == 0))) {
4347 device_set_desc_copy(dev, ent->pvi_name);
4348 /* this needs to be changed to zero if the bus probing code
4349 * ever stops re-probing on best match because the sctx
4350 * may have its values over written by register calls
4351 * in subsequent probes
4353 return (BUS_PROBE_DEFAULT);
4361 iflib_reset_qvalues(if_ctx_t ctx)
4363 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4364 if_shared_ctx_t sctx = ctx->ifc_sctx;
4365 device_t dev = ctx->ifc_dev;
4368 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4369 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4371 * XXX sanity check that ntxd & nrxd are a power of 2
4373 if (ctx->ifc_sysctl_ntxqs != 0)
4374 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4375 if (ctx->ifc_sysctl_nrxqs != 0)
4376 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4378 for (i = 0; i < sctx->isc_ntxqs; i++) {
4379 if (ctx->ifc_sysctl_ntxds[i] != 0)
4380 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4382 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4385 for (i = 0; i < sctx->isc_nrxqs; i++) {
4386 if (ctx->ifc_sysctl_nrxds[i] != 0)
4387 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4389 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4392 for (i = 0; i < sctx->isc_nrxqs; i++) {
4393 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4394 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4395 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4396 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4398 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4399 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4400 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4401 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4405 for (i = 0; i < sctx->isc_ntxqs; i++) {
4406 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4407 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4408 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4409 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4411 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4412 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4413 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4414 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4420 get_ctx_core_offset(if_ctx_t ctx)
4422 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4423 struct cpu_offset *op;
4425 uint16_t ret = ctx->ifc_sysctl_core_offset;
4427 if (ret != CORE_OFFSET_UNSPECIFIED)
4430 if (ctx->ifc_sysctl_separate_txrx)
4431 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4433 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4435 mtx_lock(&cpu_offset_mtx);
4436 SLIST_FOREACH(op, &cpu_offsets, entries) {
4437 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4440 MPASS(op->refcount < UINT_MAX);
4445 if (ret == CORE_OFFSET_UNSPECIFIED) {
4447 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4450 device_printf(ctx->ifc_dev,
4451 "allocation for cpu offset failed.\n");
4455 CPU_COPY(&ctx->ifc_cpus, &op->set);
4456 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4459 mtx_unlock(&cpu_offset_mtx);
4465 unref_ctx_core_offset(if_ctx_t ctx)
4467 struct cpu_offset *op, *top;
4469 mtx_lock(&cpu_offset_mtx);
4470 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4471 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4472 MPASS(op->refcount > 0);
4474 if (op->refcount == 0) {
4475 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4481 mtx_unlock(&cpu_offset_mtx);
4485 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4490 if_softc_ctx_t scctx;
4496 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4499 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4500 device_set_softc(dev, ctx);
4501 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4504 ctx->ifc_sctx = sctx;
4506 ctx->ifc_softc = sc;
4508 if ((err = iflib_register(ctx)) != 0) {
4509 device_printf(dev, "iflib_register failed %d\n", err);
4512 iflib_add_device_sysctl_pre(ctx);
4514 scctx = &ctx->ifc_softc_ctx;
4517 iflib_reset_qvalues(ctx);
4519 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4520 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4523 _iflib_pre_assert(scctx);
4524 ctx->ifc_txrx = *scctx->isc_txrx;
4527 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4528 MPASS(scctx->isc_tx_csum_flags);
4531 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4532 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4534 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4535 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4536 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4537 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4539 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4540 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4542 /* XXX change for per-queue sizes */
4543 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4544 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4545 for (i = 0; i < sctx->isc_nrxqs; i++) {
4546 if (!powerof2(scctx->isc_nrxd[i])) {
4547 /* round down instead? */
4548 device_printf(dev, "# rx descriptors must be a power of 2\n");
4550 goto fail_iflib_detach;
4553 for (i = 0; i < sctx->isc_ntxqs; i++) {
4554 if (!powerof2(scctx->isc_ntxd[i])) {
4556 "# tx descriptors must be a power of 2");
4558 goto fail_iflib_detach;
4562 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4563 MAX_SINGLE_PACKET_FRACTION)
4564 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4565 MAX_SINGLE_PACKET_FRACTION);
4566 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4567 MAX_SINGLE_PACKET_FRACTION)
4568 scctx->isc_tx_tso_segments_max = max(1,
4569 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4571 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4572 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4574 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4577 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4580 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4581 * into account. In the worst case, each of these calls will
4582 * add another mbuf and, thus, the requirement for another DMA
4583 * segment. So for best performance, it doesn't make sense to
4584 * advertize a maximum of TSO segments that typically will
4585 * require defragmentation in iflib_encap().
4587 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4588 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4590 if (scctx->isc_rss_table_size == 0)
4591 scctx->isc_rss_table_size = 64;
4592 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4594 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4595 /* XXX format name */
4596 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4598 /* Set up cpu set. If it fails, use the set of all CPUs. */
4599 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4600 device_printf(dev, "Unable to fetch CPU list\n");
4601 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4603 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4606 ** Now set up MSI or MSI-X, should return us the number of supported
4607 ** vectors (will be 1 for a legacy interrupt and MSI).
4609 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4610 msix = scctx->isc_vectors;
4611 } else if (scctx->isc_msix_bar != 0)
4613 * The simple fact that isc_msix_bar is not 0 does not mean we
4614 * we have a good value there that is known to work.
4616 msix = iflib_msix_init(ctx);
4618 scctx->isc_vectors = 1;
4619 scctx->isc_ntxqsets = 1;
4620 scctx->isc_nrxqsets = 1;
4621 scctx->isc_intr = IFLIB_INTR_LEGACY;
4624 /* Get memory for the station queues */
4625 if ((err = iflib_queues_alloc(ctx))) {
4626 device_printf(dev, "Unable to allocate queue memory\n");
4627 goto fail_intr_free;
4630 if ((err = iflib_qset_structures_setup(ctx)))
4634 * Now that we know how many queues there are, get the core offset.
4636 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4639 * Group taskqueues aren't properly set up until SMP is started,
4640 * so we disable interrupts until we can handle them post
4643 * XXX: disabling interrupts doesn't actually work, at least for
4644 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4645 * we do null handling and depend on this not causing too large an
4648 IFDI_INTR_DISABLE(ctx);
4649 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4650 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4655 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4659 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4660 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4665 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4667 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4668 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4673 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4674 * This must appear after the call to ether_ifattach() because
4675 * ether_ifattach() sets if_hdrlen to the default value.
4677 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4678 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4680 if ((err = iflib_netmap_attach(ctx))) {
4681 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4686 NETDUMP_SET(ctx->ifc_ifp, iflib);
4688 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4689 iflib_add_device_sysctl_post(ctx);
4690 ctx->ifc_flags |= IFC_INIT_DONE;
4695 ether_ifdetach(ctx->ifc_ifp);
4697 iflib_free_intr_mem(ctx);
4699 iflib_tx_structures_free(ctx);
4700 iflib_rx_structures_free(ctx);
4706 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4707 free(ctx->ifc_softc, M_IFLIB);
4713 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4714 struct iflib_cloneattach_ctx *clctx)
4719 if_softc_ctx_t scctx;
4725 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4726 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4727 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4728 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4729 ctx->ifc_flags |= IFC_PSEUDO;
4731 ctx->ifc_sctx = sctx;
4732 ctx->ifc_softc = sc;
4735 if ((err = iflib_register(ctx)) != 0) {
4736 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4739 iflib_add_device_sysctl_pre(ctx);
4741 scctx = &ctx->ifc_softc_ctx;
4745 * XXX sanity check that ntxd & nrxd are a power of 2
4747 iflib_reset_qvalues(ctx);
4749 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4750 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4753 if (sctx->isc_flags & IFLIB_GEN_MAC)
4755 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4756 clctx->cc_params)) != 0) {
4757 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4760 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4761 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4762 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4765 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4766 MPASS(scctx->isc_tx_csum_flags);
4769 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4770 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4772 ifp->if_flags |= IFF_NOGROUP;
4773 if (sctx->isc_flags & IFLIB_PSEUDO) {
4774 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4776 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4777 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4783 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4784 * This must appear after the call to ether_ifattach() because
4785 * ether_ifattach() sets if_hdrlen to the default value.
4787 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4788 if_setifheaderlen(ifp,
4789 sizeof(struct ether_vlan_header));
4791 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4792 iflib_add_device_sysctl_post(ctx);
4793 ctx->ifc_flags |= IFC_INIT_DONE;
4796 _iflib_pre_assert(scctx);
4797 ctx->ifc_txrx = *scctx->isc_txrx;
4799 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4800 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4801 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4802 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4804 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4805 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4807 /* XXX change for per-queue sizes */
4808 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4809 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4810 for (i = 0; i < sctx->isc_nrxqs; i++) {
4811 if (!powerof2(scctx->isc_nrxd[i])) {
4812 /* round down instead? */
4813 device_printf(dev, "# rx descriptors must be a power of 2\n");
4815 goto fail_iflib_detach;
4818 for (i = 0; i < sctx->isc_ntxqs; i++) {
4819 if (!powerof2(scctx->isc_ntxd[i])) {
4821 "# tx descriptors must be a power of 2");
4823 goto fail_iflib_detach;
4827 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4828 MAX_SINGLE_PACKET_FRACTION)
4829 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4830 MAX_SINGLE_PACKET_FRACTION);
4831 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4832 MAX_SINGLE_PACKET_FRACTION)
4833 scctx->isc_tx_tso_segments_max = max(1,
4834 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4836 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4837 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4839 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4842 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4845 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4846 * into account. In the worst case, each of these calls will
4847 * add another mbuf and, thus, the requirement for another DMA
4848 * segment. So for best performance, it doesn't make sense to
4849 * advertize a maximum of TSO segments that typically will
4850 * require defragmentation in iflib_encap().
4852 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4853 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4855 if (scctx->isc_rss_table_size == 0)
4856 scctx->isc_rss_table_size = 64;
4857 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4859 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4860 /* XXX format name */
4861 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4863 /* XXX --- can support > 1 -- but keep it simple for now */
4864 scctx->isc_intr = IFLIB_INTR_LEGACY;
4866 /* Get memory for the station queues */
4867 if ((err = iflib_queues_alloc(ctx))) {
4868 device_printf(dev, "Unable to allocate queue memory\n");
4869 goto fail_iflib_detach;
4872 if ((err = iflib_qset_structures_setup(ctx))) {
4873 device_printf(dev, "qset structure setup failed %d\n", err);
4878 * XXX What if anything do we want to do about interrupts?
4880 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4881 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4882 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4887 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4888 * This must appear after the call to ether_ifattach() because
4889 * ether_ifattach() sets if_hdrlen to the default value.
4891 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4892 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4894 /* XXX handle more than one queue */
4895 for (i = 0; i < scctx->isc_nrxqsets; i++)
4896 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4900 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4901 iflib_add_device_sysctl_post(ctx);
4902 ctx->ifc_flags |= IFC_INIT_DONE;
4906 ether_ifdetach(ctx->ifc_ifp);
4908 iflib_tx_structures_free(ctx);
4909 iflib_rx_structures_free(ctx);
4915 free(ctx->ifc_softc, M_IFLIB);
4921 iflib_pseudo_deregister(if_ctx_t ctx)
4923 if_t ifp = ctx->ifc_ifp;
4927 struct taskqgroup *tqg;
4930 /* Unregister VLAN events */
4931 if (ctx->ifc_vlan_attach_event != NULL)
4932 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4933 if (ctx->ifc_vlan_detach_event != NULL)
4934 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4936 ether_ifdetach(ifp);
4937 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4938 CTX_LOCK_DESTROY(ctx);
4939 /* XXX drain any dependent tasks */
4940 tqg = qgroup_if_io_tqg;
4941 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4942 callout_drain(&txq->ift_timer);
4943 if (txq->ift_task.gt_uniq != NULL)
4944 taskqgroup_detach(tqg, &txq->ift_task);
4946 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4947 if (rxq->ifr_task.gt_uniq != NULL)
4948 taskqgroup_detach(tqg, &rxq->ifr_task);
4950 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4951 free(fl->ifl_rx_bitmap, M_IFLIB);
4953 tqg = qgroup_if_config_tqg;
4954 if (ctx->ifc_admin_task.gt_uniq != NULL)
4955 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4956 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4957 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4961 iflib_tx_structures_free(ctx);
4962 iflib_rx_structures_free(ctx);
4963 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4964 free(ctx->ifc_softc, M_IFLIB);
4970 iflib_device_attach(device_t dev)
4973 if_shared_ctx_t sctx;
4975 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4978 pci_enable_busmaster(dev);
4980 return (iflib_device_register(dev, NULL, sctx, &ctx));
4984 iflib_device_deregister(if_ctx_t ctx)
4986 if_t ifp = ctx->ifc_ifp;
4989 device_t dev = ctx->ifc_dev;
4991 struct taskqgroup *tqg;
4994 /* Make sure VLANS are not using driver */
4995 if (if_vlantrunkinuse(ifp)) {
4996 device_printf(dev, "Vlan in use, detach first\n");
5000 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5001 device_printf(dev, "SR-IOV in use; detach first.\n");
5007 ctx->ifc_flags |= IFC_IN_DETACH;
5014 /* Unregister VLAN events */
5015 if (ctx->ifc_vlan_attach_event != NULL)
5016 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5017 if (ctx->ifc_vlan_detach_event != NULL)
5018 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5020 iflib_netmap_detach(ifp);
5021 ether_ifdetach(ifp);
5022 if (ctx->ifc_led_dev != NULL)
5023 led_destroy(ctx->ifc_led_dev);
5024 /* XXX drain any dependent tasks */
5025 tqg = qgroup_if_io_tqg;
5026 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5027 callout_drain(&txq->ift_timer);
5028 if (txq->ift_task.gt_uniq != NULL)
5029 taskqgroup_detach(tqg, &txq->ift_task);
5031 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5032 if (rxq->ifr_task.gt_uniq != NULL)
5033 taskqgroup_detach(tqg, &rxq->ifr_task);
5035 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5036 free(fl->ifl_rx_bitmap, M_IFLIB);
5038 tqg = qgroup_if_config_tqg;
5039 if (ctx->ifc_admin_task.gt_uniq != NULL)
5040 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5041 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5042 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5047 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5048 CTX_LOCK_DESTROY(ctx);
5049 device_set_softc(ctx->ifc_dev, NULL);
5050 iflib_free_intr_mem(ctx);
5052 bus_generic_detach(dev);
5055 iflib_tx_structures_free(ctx);
5056 iflib_rx_structures_free(ctx);
5057 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5058 free(ctx->ifc_softc, M_IFLIB);
5059 unref_ctx_core_offset(ctx);
5060 STATE_LOCK_DESTROY(ctx);
5066 iflib_free_intr_mem(if_ctx_t ctx)
5069 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5070 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5072 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5073 pci_release_msi(ctx->ifc_dev);
5075 if (ctx->ifc_msix_mem != NULL) {
5076 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5077 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5078 ctx->ifc_msix_mem = NULL;
5083 iflib_device_detach(device_t dev)
5085 if_ctx_t ctx = device_get_softc(dev);
5087 return (iflib_device_deregister(ctx));
5091 iflib_device_suspend(device_t dev)
5093 if_ctx_t ctx = device_get_softc(dev);
5099 return bus_generic_suspend(dev);
5102 iflib_device_shutdown(device_t dev)
5104 if_ctx_t ctx = device_get_softc(dev);
5110 return bus_generic_suspend(dev);
5115 iflib_device_resume(device_t dev)
5117 if_ctx_t ctx = device_get_softc(dev);
5118 iflib_txq_t txq = ctx->ifc_txqs;
5122 iflib_if_init_locked(ctx);
5124 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5125 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5127 return (bus_generic_resume(dev));
5131 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5134 if_ctx_t ctx = device_get_softc(dev);
5137 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5144 iflib_device_iov_uninit(device_t dev)
5146 if_ctx_t ctx = device_get_softc(dev);
5149 IFDI_IOV_UNINIT(ctx);
5154 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5157 if_ctx_t ctx = device_get_softc(dev);
5160 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5166 /*********************************************************************
5168 * MODULE FUNCTION DEFINITIONS
5170 **********************************************************************/
5173 * - Start a fast taskqueue thread for each core
5174 * - Start a taskqueue for control operations
5177 iflib_module_init(void)
5183 iflib_module_event_handler(module_t mod, int what, void *arg)
5189 if ((err = iflib_module_init()) != 0)
5195 return (EOPNOTSUPP);
5201 /*********************************************************************
5203 * PUBLIC FUNCTION DEFINITIONS
5204 * ordered as in iflib.h
5206 **********************************************************************/
5210 _iflib_assert(if_shared_ctx_t sctx)
5212 MPASS(sctx->isc_tx_maxsize);
5213 MPASS(sctx->isc_tx_maxsegsize);
5215 MPASS(sctx->isc_rx_maxsize);
5216 MPASS(sctx->isc_rx_nsegments);
5217 MPASS(sctx->isc_rx_maxsegsize);
5219 MPASS(sctx->isc_nrxd_min[0]);
5220 MPASS(sctx->isc_nrxd_max[0]);
5221 MPASS(sctx->isc_nrxd_default[0]);
5222 MPASS(sctx->isc_ntxd_min[0]);
5223 MPASS(sctx->isc_ntxd_max[0]);
5224 MPASS(sctx->isc_ntxd_default[0]);
5228 _iflib_pre_assert(if_softc_ctx_t scctx)
5231 MPASS(scctx->isc_txrx->ift_txd_encap);
5232 MPASS(scctx->isc_txrx->ift_txd_flush);
5233 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5234 MPASS(scctx->isc_txrx->ift_rxd_available);
5235 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5236 MPASS(scctx->isc_txrx->ift_rxd_refill);
5237 MPASS(scctx->isc_txrx->ift_rxd_flush);
5241 iflib_register(if_ctx_t ctx)
5243 if_shared_ctx_t sctx = ctx->ifc_sctx;
5244 driver_t *driver = sctx->isc_driver;
5245 device_t dev = ctx->ifc_dev;
5248 _iflib_assert(sctx);
5251 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5252 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5254 device_printf(dev, "can not allocate ifnet structure\n");
5259 * Initialize our context's device specific methods
5261 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5262 kobj_class_compile((kobj_class_t) driver);
5265 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5266 if_setsoftc(ifp, ctx);
5267 if_setdev(ifp, dev);
5268 if_setinitfn(ifp, iflib_if_init);
5269 if_setioctlfn(ifp, iflib_if_ioctl);
5271 if_setstartfn(ifp, iflib_altq_if_start);
5272 if_settransmitfn(ifp, iflib_altq_if_transmit);
5273 if_setsendqready(ifp);
5275 if_settransmitfn(ifp, iflib_if_transmit);
5277 if_setqflushfn(ifp, iflib_if_qflush);
5278 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5280 ctx->ifc_vlan_attach_event =
5281 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5282 EVENTHANDLER_PRI_FIRST);
5283 ctx->ifc_vlan_detach_event =
5284 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5285 EVENTHANDLER_PRI_FIRST);
5287 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5288 iflib_media_change, iflib_media_status);
5295 iflib_queues_alloc(if_ctx_t ctx)
5297 if_shared_ctx_t sctx = ctx->ifc_sctx;
5298 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5299 device_t dev = ctx->ifc_dev;
5300 int nrxqsets = scctx->isc_nrxqsets;
5301 int ntxqsets = scctx->isc_ntxqsets;
5304 iflib_fl_t fl = NULL;
5305 int i, j, cpu, err, txconf, rxconf;
5306 iflib_dma_info_t ifdip;
5307 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5308 uint32_t *txqsizes = scctx->isc_txqsizes;
5309 uint8_t nrxqs = sctx->isc_nrxqs;
5310 uint8_t ntxqs = sctx->isc_ntxqs;
5311 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5315 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5316 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5318 /* Allocate the TX ring struct memory */
5319 if (!(ctx->ifc_txqs =
5320 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5321 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5322 device_printf(dev, "Unable to allocate TX ring memory\n");
5327 /* Now allocate the RX */
5328 if (!(ctx->ifc_rxqs =
5329 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5330 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5331 device_printf(dev, "Unable to allocate RX ring memory\n");
5336 txq = ctx->ifc_txqs;
5337 rxq = ctx->ifc_rxqs;
5340 * XXX handle allocation failure
5342 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5343 /* Set up some basics */
5345 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5346 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5348 "Unable to allocate TX DMA info memory\n");
5352 txq->ift_ifdi = ifdip;
5353 for (j = 0; j < ntxqs; j++, ifdip++) {
5354 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5356 "Unable to allocate TX descriptors\n");
5360 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5361 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5365 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5366 txq->ift_br_offset = 1;
5368 txq->ift_br_offset = 0;
5371 txq->ift_timer.c_cpu = cpu;
5373 if (iflib_txsd_alloc(txq)) {
5374 device_printf(dev, "Critical Failure setting up TX buffers\n");
5379 /* Initialize the TX lock */
5380 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5381 device_get_nameunit(dev), txq->ift_id);
5382 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5383 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5385 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5386 device_get_nameunit(dev), txq->ift_id);
5388 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5389 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5391 /* XXX free any allocated rings */
5392 device_printf(dev, "Unable to allocate buf_ring\n");
5397 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5398 /* Set up some basics */
5400 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5401 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5403 "Unable to allocate RX DMA info memory\n");
5408 rxq->ifr_ifdi = ifdip;
5409 /* XXX this needs to be changed if #rx queues != #tx queues */
5410 rxq->ifr_ntxqirq = 1;
5411 rxq->ifr_txqid[0] = i;
5412 for (j = 0; j < nrxqs; j++, ifdip++) {
5413 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5415 "Unable to allocate RX descriptors\n");
5419 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5423 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5424 rxq->ifr_fl_offset = 1;
5426 rxq->ifr_fl_offset = 0;
5428 rxq->ifr_nfl = nfree_lists;
5430 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5431 device_printf(dev, "Unable to allocate free list memory\n");
5436 for (j = 0; j < nfree_lists; j++) {
5437 fl[j].ifl_rxq = rxq;
5439 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5440 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5442 /* Allocate receive buffers for the ring */
5443 if (iflib_rxsd_alloc(rxq)) {
5445 "Critical Failure setting up receive buffers\n");
5450 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5451 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5456 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5457 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5458 for (i = 0; i < ntxqsets; i++) {
5459 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5461 for (j = 0; j < ntxqs; j++, di++) {
5462 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5463 paddrs[i*ntxqs + j] = di->idi_paddr;
5466 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5467 device_printf(ctx->ifc_dev,
5468 "Unable to allocate device TX queue\n");
5469 iflib_tx_structures_free(ctx);
5470 free(vaddrs, M_IFLIB);
5471 free(paddrs, M_IFLIB);
5474 free(vaddrs, M_IFLIB);
5475 free(paddrs, M_IFLIB);
5478 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5479 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5480 for (i = 0; i < nrxqsets; i++) {
5481 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5483 for (j = 0; j < nrxqs; j++, di++) {
5484 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5485 paddrs[i*nrxqs + j] = di->idi_paddr;
5488 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5489 device_printf(ctx->ifc_dev,
5490 "Unable to allocate device RX queue\n");
5491 iflib_tx_structures_free(ctx);
5492 free(vaddrs, M_IFLIB);
5493 free(paddrs, M_IFLIB);
5496 free(vaddrs, M_IFLIB);
5497 free(paddrs, M_IFLIB);
5501 /* XXX handle allocation failure changes */
5505 if (ctx->ifc_rxqs != NULL)
5506 free(ctx->ifc_rxqs, M_IFLIB);
5507 ctx->ifc_rxqs = NULL;
5508 if (ctx->ifc_txqs != NULL)
5509 free(ctx->ifc_txqs, M_IFLIB);
5510 ctx->ifc_txqs = NULL;
5516 iflib_tx_structures_setup(if_ctx_t ctx)
5518 iflib_txq_t txq = ctx->ifc_txqs;
5521 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5522 iflib_txq_setup(txq);
5528 iflib_tx_structures_free(if_ctx_t ctx)
5530 iflib_txq_t txq = ctx->ifc_txqs;
5531 if_shared_ctx_t sctx = ctx->ifc_sctx;
5534 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5535 iflib_txq_destroy(txq);
5536 for (j = 0; j < sctx->isc_ntxqs; j++)
5537 iflib_dma_free(&txq->ift_ifdi[j]);
5539 free(ctx->ifc_txqs, M_IFLIB);
5540 ctx->ifc_txqs = NULL;
5541 IFDI_QUEUES_FREE(ctx);
5544 /*********************************************************************
5546 * Initialize all receive rings.
5548 **********************************************************************/
5550 iflib_rx_structures_setup(if_ctx_t ctx)
5552 iflib_rxq_t rxq = ctx->ifc_rxqs;
5554 #if defined(INET6) || defined(INET)
5558 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5559 #if defined(INET6) || defined(INET)
5560 tcp_lro_free(&rxq->ifr_lc);
5561 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5562 TCP_LRO_ENTRIES, min(1024,
5563 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5564 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5567 rxq->ifr_lro_enabled = TRUE;
5569 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5572 #if defined(INET6) || defined(INET)
5575 * Free RX software descriptors allocated so far, we will only handle
5576 * the rings that completed, the failing case will have
5577 * cleaned up for itself. 'q' failed, so its the terminus.
5579 rxq = ctx->ifc_rxqs;
5580 for (i = 0; i < q; ++i, rxq++) {
5581 iflib_rx_sds_free(rxq);
5582 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5588 /*********************************************************************
5590 * Free all receive rings.
5592 **********************************************************************/
5594 iflib_rx_structures_free(if_ctx_t ctx)
5596 iflib_rxq_t rxq = ctx->ifc_rxqs;
5598 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5599 iflib_rx_sds_free(rxq);
5601 free(ctx->ifc_rxqs, M_IFLIB);
5602 ctx->ifc_rxqs = NULL;
5606 iflib_qset_structures_setup(if_ctx_t ctx)
5611 * It is expected that the caller takes care of freeing queues if this
5614 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5615 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5619 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5620 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5626 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5627 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5630 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5635 find_nth(if_ctx_t ctx, int qid)
5638 int i, cpuid, eqid, count;
5640 CPU_COPY(&ctx->ifc_cpus, &cpus);
5641 count = CPU_COUNT(&cpus);
5643 /* clear up to the qid'th bit */
5644 for (i = 0; i < eqid; i++) {
5645 cpuid = CPU_FFS(&cpus);
5647 CPU_CLR(cpuid-1, &cpus);
5649 cpuid = CPU_FFS(&cpus);
5655 extern struct cpu_group *cpu_top; /* CPU topology */
5658 find_child_with_core(int cpu, struct cpu_group *grp)
5662 if (grp->cg_children == 0)
5665 MPASS(grp->cg_child);
5666 for (i = 0; i < grp->cg_children; i++) {
5667 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5675 * Find the nth "close" core to the specified core
5676 * "close" is defined as the deepest level that shares
5677 * at least an L2 cache. With threads, this will be
5678 * threads on the same core. If the shared cache is L3
5679 * or higher, simply returns the same core.
5682 find_close_core(int cpu, int core_offset)
5684 struct cpu_group *grp;
5693 while ((i = find_child_with_core(cpu, grp)) != -1) {
5694 /* If the child only has one cpu, don't descend */
5695 if (grp->cg_child[i].cg_count <= 1)
5697 grp = &grp->cg_child[i];
5700 /* If they don't share at least an L2 cache, use the same CPU */
5701 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5705 CPU_COPY(&grp->cg_mask, &cs);
5707 /* Add the selected CPU offset to core offset. */
5708 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5709 if (fcpu - 1 == cpu)
5711 CPU_CLR(fcpu - 1, &cs);
5717 CPU_COPY(&grp->cg_mask, &cs);
5718 for (i = core_offset % grp->cg_count; i > 0; i--) {
5719 MPASS(CPU_FFS(&cs));
5720 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5722 MPASS(CPU_FFS(&cs));
5723 return CPU_FFS(&cs) - 1;
5727 find_close_core(int cpu, int core_offset __unused)
5734 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5738 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5739 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5740 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5742 case IFLIB_INTR_RXTX:
5743 /* RX queues get the specified core */
5744 return qid / CPU_COUNT(&ctx->ifc_cpus);
5750 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5751 #define find_close_core(cpuid, tid) CPU_FIRST()
5752 #define find_nth(ctx, gid) CPU_FIRST()
5755 /* Just to avoid copy/paste */
5757 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5758 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5760 int co, cpuid, err, tid;
5762 co = ctx->ifc_sysctl_core_offset;
5763 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5764 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5765 cpuid = find_nth(ctx, qid + co);
5766 tid = get_core_offset(ctx, type, qid);
5768 cpuid = find_close_core(cpuid, tid);
5769 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5771 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5775 if (cpuid > ctx->ifc_cpuid_highest)
5776 ctx->ifc_cpuid_highest = cpuid;
5782 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5783 iflib_intr_type_t type, driver_filter_t *filter,
5784 void *filter_arg, int qid, const char *name)
5786 struct grouptask *gtask;
5787 struct taskqgroup *tqg;
5788 iflib_filter_info_t info;
5791 driver_filter_t *intr_fast;
5794 info = &ctx->ifc_filter_info;
5798 /* XXX merge tx/rx for netmap? */
5800 q = &ctx->ifc_txqs[qid];
5801 info = &ctx->ifc_txqs[qid].ift_filter_info;
5802 gtask = &ctx->ifc_txqs[qid].ift_task;
5803 tqg = qgroup_if_io_tqg;
5805 intr_fast = iflib_fast_intr;
5806 GROUPTASK_INIT(gtask, 0, fn, q);
5807 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5810 q = &ctx->ifc_rxqs[qid];
5811 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5812 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5813 tqg = qgroup_if_io_tqg;
5815 intr_fast = iflib_fast_intr;
5816 GROUPTASK_INIT(gtask, 0, fn, q);
5818 case IFLIB_INTR_RXTX:
5819 q = &ctx->ifc_rxqs[qid];
5820 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5821 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5822 tqg = qgroup_if_io_tqg;
5824 intr_fast = iflib_fast_intr_rxtx;
5825 GROUPTASK_INIT(gtask, 0, fn, q);
5827 case IFLIB_INTR_ADMIN:
5830 info = &ctx->ifc_filter_info;
5831 gtask = &ctx->ifc_admin_task;
5832 tqg = qgroup_if_config_tqg;
5833 fn = _task_fn_admin;
5834 intr_fast = iflib_fast_intr_ctx;
5837 panic("unknown net intr type");
5840 info->ifi_filter = filter;
5841 info->ifi_filter_arg = filter_arg;
5842 info->ifi_task = gtask;
5845 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5847 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5850 if (type == IFLIB_INTR_ADMIN)
5854 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5858 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5865 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5867 struct grouptask *gtask;
5868 struct taskqgroup *tqg;
5876 q = &ctx->ifc_txqs[qid];
5877 gtask = &ctx->ifc_txqs[qid].ift_task;
5878 tqg = qgroup_if_io_tqg;
5881 irq_num = rman_get_start(irq->ii_res);
5884 q = &ctx->ifc_rxqs[qid];
5885 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5886 tqg = qgroup_if_io_tqg;
5889 irq_num = rman_get_start(irq->ii_res);
5891 case IFLIB_INTR_IOV:
5893 gtask = &ctx->ifc_vflr_task;
5894 tqg = qgroup_if_config_tqg;
5898 panic("unknown net intr type");
5900 GROUPTASK_INIT(gtask, 0, fn, q);
5901 if (irq_num != -1) {
5902 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5904 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5907 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5912 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5916 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5919 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
5920 rman_get_rid(irq->ii_res), irq->ii_res);
5924 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5926 iflib_txq_t txq = ctx->ifc_txqs;
5927 iflib_rxq_t rxq = ctx->ifc_rxqs;
5928 if_irq_t irq = &ctx->ifc_legacy_irq;
5929 iflib_filter_info_t info;
5930 struct grouptask *gtask;
5931 struct taskqgroup *tqg;
5937 q = &ctx->ifc_rxqs[0];
5938 info = &rxq[0].ifr_filter_info;
5939 gtask = &rxq[0].ifr_task;
5940 tqg = qgroup_if_io_tqg;
5941 tqrid = irq->ii_rid = *rid;
5944 ctx->ifc_flags |= IFC_LEGACY;
5945 info->ifi_filter = filter;
5946 info->ifi_filter_arg = filter_arg;
5947 info->ifi_task = gtask;
5948 info->ifi_ctx = ctx;
5950 /* We allocate a single interrupt resource */
5951 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5953 GROUPTASK_INIT(gtask, 0, fn, q);
5954 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5956 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5957 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5962 iflib_led_create(if_ctx_t ctx)
5965 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5966 device_get_nameunit(ctx->ifc_dev));
5970 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5973 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5977 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5980 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5984 iflib_admin_intr_deferred(if_ctx_t ctx)
5987 struct grouptask *gtask;
5989 gtask = &ctx->ifc_admin_task;
5990 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5993 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5997 iflib_iov_intr_deferred(if_ctx_t ctx)
6000 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6004 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
6007 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
6011 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6015 GROUPTASK_INIT(gtask, 0, fn, ctx);
6016 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
6020 iflib_config_gtask_deinit(struct grouptask *gtask)
6023 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6027 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6029 if_t ifp = ctx->ifc_ifp;
6030 iflib_txq_t txq = ctx->ifc_txqs;
6032 if_setbaudrate(ifp, baudrate);
6033 if (baudrate >= IF_Gbps(10)) {
6035 ctx->ifc_flags |= IFC_PREFETCH;
6038 /* If link down, disable watchdog */
6039 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6040 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6041 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6043 ctx->ifc_link_state = link_state;
6044 if_link_state_change(ifp, link_state);
6048 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6052 int credits_pre = txq->ift_cidx_processed;
6055 if (ctx->isc_txd_credits_update == NULL)
6058 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6059 BUS_DMASYNC_POSTREAD);
6060 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6063 txq->ift_processed += credits;
6064 txq->ift_cidx_processed += credits;
6066 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6067 if (txq->ift_cidx_processed >= txq->ift_size)
6068 txq->ift_cidx_processed -= txq->ift_size;
6073 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6076 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6081 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6082 const char *description, if_int_delay_info_t info,
6083 int offset, int value)
6085 info->iidi_ctx = ctx;
6086 info->iidi_offset = offset;
6087 info->iidi_value = value;
6088 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6089 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6090 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6091 info, 0, iflib_sysctl_int_delay, "I", description);
6095 iflib_ctx_lock_get(if_ctx_t ctx)
6098 return (&ctx->ifc_ctx_sx);
6102 iflib_msix_init(if_ctx_t ctx)
6104 device_t dev = ctx->ifc_dev;
6105 if_shared_ctx_t sctx = ctx->ifc_sctx;
6106 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6107 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
6108 int iflib_num_tx_queues, iflib_num_rx_queues;
6109 int err, admincnt, bar;
6111 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6112 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6115 device_printf(dev, "msix_init qsets capped at %d\n",
6116 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6118 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6119 admincnt = sctx->isc_admin_intrcnt;
6120 /* Override by tuneable */
6121 if (scctx->isc_disable_msix)
6124 /* First try MSI-X */
6125 if ((msgs = pci_msix_count(dev)) == 0) {
6127 device_printf(dev, "MSI-X not supported or disabled\n");
6131 * bar == -1 => "trust me I know what I'm doing"
6132 * Some drivers are for hardware that is so shoddily
6133 * documented that no one knows which bars are which
6134 * so the developer has to map all bars. This hack
6135 * allows shoddy garbage to use MSI-X in this framework.
6138 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6139 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6140 if (ctx->ifc_msix_mem == NULL) {
6141 device_printf(dev, "Unable to map MSI-X table\n");
6146 /* use only 1 qset in debug mode */
6147 queuemsgs = min(msgs - admincnt, 1);
6149 queuemsgs = msgs - admincnt;
6152 queues = imin(queuemsgs, rss_getnumbuckets());
6156 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6159 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6160 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6162 /* If we're doing RSS, clamp at the number of RSS buckets */
6163 if (queues > rss_getnumbuckets())
6164 queues = rss_getnumbuckets();
6166 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6167 rx_queues = iflib_num_rx_queues;
6171 if (rx_queues > scctx->isc_nrxqsets)
6172 rx_queues = scctx->isc_nrxqsets;
6175 * We want this to be all logical CPUs by default
6177 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6178 tx_queues = iflib_num_tx_queues;
6180 tx_queues = mp_ncpus;
6182 if (tx_queues > scctx->isc_ntxqsets)
6183 tx_queues = scctx->isc_ntxqsets;
6185 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6187 if (tx_queues != rx_queues)
6189 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6190 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6192 tx_queues = min(rx_queues, tx_queues);
6193 rx_queues = min(rx_queues, tx_queues);
6196 device_printf(dev, "Using %d rx queues %d tx queues\n",
6197 rx_queues, tx_queues);
6199 vectors = rx_queues + admincnt;
6200 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6201 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6203 scctx->isc_vectors = vectors;
6204 scctx->isc_nrxqsets = rx_queues;
6205 scctx->isc_ntxqsets = tx_queues;
6206 scctx->isc_intr = IFLIB_INTR_MSIX;
6211 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n",
6213 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6215 ctx->ifc_msix_mem = NULL;
6218 vectors = pci_msi_count(dev);
6219 scctx->isc_nrxqsets = 1;
6220 scctx->isc_ntxqsets = 1;
6221 scctx->isc_vectors = vectors;
6222 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6223 device_printf(dev,"Using an MSI interrupt\n");
6224 scctx->isc_intr = IFLIB_INTR_MSI;
6226 scctx->isc_vectors = 1;
6227 device_printf(dev,"Using a Legacy interrupt\n");
6228 scctx->isc_intr = IFLIB_INTR_LEGACY;
6234 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6237 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6240 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6242 const char *ring_state = "UNKNOWN";
6245 rc = sysctl_wire_old_buffer(req, 0);
6249 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6254 ring_state = ring_states[state[3]];
6256 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6257 state[0], state[1], state[2], ring_state);
6258 rc = sbuf_finish(sb);
6263 enum iflib_ndesc_handler {
6269 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6271 if_ctx_t ctx = (void *)arg1;
6272 enum iflib_ndesc_handler type = arg2;
6273 char buf[256] = {0};
6278 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6282 case IFLIB_NTXD_HANDLER:
6283 ndesc = ctx->ifc_sysctl_ntxds;
6285 nqs = ctx->ifc_sctx->isc_ntxqs;
6287 case IFLIB_NRXD_HANDLER:
6288 ndesc = ctx->ifc_sysctl_nrxds;
6290 nqs = ctx->ifc_sctx->isc_nrxqs;
6293 panic("unhandled type");
6298 for (i=0; i<8; i++) {
6303 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6306 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6307 if (rc || req->newptr == NULL)
6310 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6311 i++, p = strsep(&next, " ,")) {
6312 ndesc[i] = strtoul(p, NULL, 10);
6318 #define NAME_BUFLEN 32
6320 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6322 device_t dev = iflib_get_dev(ctx);
6323 struct sysctl_oid_list *child, *oid_list;
6324 struct sysctl_ctx_list *ctx_list;
6325 struct sysctl_oid *node;
6327 ctx_list = device_get_sysctl_ctx(dev);
6328 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6329 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6330 CTLFLAG_RD, NULL, "IFLIB fields");
6331 oid_list = SYSCTL_CHILDREN(node);
6333 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6334 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6337 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6338 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6339 "# of txqs to use, 0 => use default #");
6340 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6341 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6342 "# of rxqs to use, 0 => use default #");
6343 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6344 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6345 "permit #txq != #rxq");
6346 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6347 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6348 "disable MSI-X (default 0)");
6349 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6350 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6351 "set the rx budget");
6352 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6353 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6354 "cause tx to abdicate instead of running to completion");
6355 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6356 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6357 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6358 "offset to start using cores at");
6359 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6360 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6361 "use separate cores for TX and RX");
6363 /* XXX change for per-queue sizes */
6364 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6365 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6366 mp_ndesc_handler, "A",
6367 "list of # of tx descriptors to use, 0 = use default #");
6368 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6369 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6370 mp_ndesc_handler, "A",
6371 "list of # of rx descriptors to use, 0 = use default #");
6375 iflib_add_device_sysctl_post(if_ctx_t ctx)
6377 if_shared_ctx_t sctx = ctx->ifc_sctx;
6378 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6379 device_t dev = iflib_get_dev(ctx);
6380 struct sysctl_oid_list *child;
6381 struct sysctl_ctx_list *ctx_list;
6386 char namebuf[NAME_BUFLEN];
6388 struct sysctl_oid *queue_node, *fl_node, *node;
6389 struct sysctl_oid_list *queue_list, *fl_list;
6390 ctx_list = device_get_sysctl_ctx(dev);
6392 node = ctx->ifc_sysctl_node;
6393 child = SYSCTL_CHILDREN(node);
6395 if (scctx->isc_ntxqsets > 100)
6397 else if (scctx->isc_ntxqsets > 10)
6401 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6402 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6403 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6404 CTLFLAG_RD, NULL, "Queue Name");
6405 queue_list = SYSCTL_CHILDREN(queue_node);
6407 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6409 &txq->ift_dequeued, "total mbufs freed");
6410 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6412 &txq->ift_enqueued, "total mbufs enqueued");
6414 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6416 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6417 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6419 &txq->ift_pullups, "# of times m_pullup was called");
6420 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6422 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6423 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6425 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6426 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6428 &txq->ift_map_failed, "# of times dma map failed");
6429 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6431 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6432 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6434 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6435 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6437 &txq->ift_pidx, 1, "Producer Index");
6438 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6440 &txq->ift_cidx, 1, "Consumer Index");
6441 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6443 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6444 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6446 &txq->ift_in_use, 1, "descriptors in use");
6447 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6449 &txq->ift_processed, "descriptors procesed for clean");
6450 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6452 &txq->ift_cleaned, "total cleaned");
6453 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6454 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6455 0, mp_ring_state_handler, "A", "soft ring state");
6456 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6457 CTLFLAG_RD, &txq->ift_br->enqueues,
6458 "# of enqueues to the mp_ring for this queue");
6459 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6460 CTLFLAG_RD, &txq->ift_br->drops,
6461 "# of drops in the mp_ring for this queue");
6462 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6463 CTLFLAG_RD, &txq->ift_br->starts,
6464 "# of normal consumer starts in the mp_ring for this queue");
6465 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6466 CTLFLAG_RD, &txq->ift_br->stalls,
6467 "# of consumer stalls in the mp_ring for this queue");
6468 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6469 CTLFLAG_RD, &txq->ift_br->restarts,
6470 "# of consumer restarts in the mp_ring for this queue");
6471 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6472 CTLFLAG_RD, &txq->ift_br->abdications,
6473 "# of consumer abdications in the mp_ring for this queue");
6476 if (scctx->isc_nrxqsets > 100)
6478 else if (scctx->isc_nrxqsets > 10)
6482 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6483 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6484 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6485 CTLFLAG_RD, NULL, "Queue Name");
6486 queue_list = SYSCTL_CHILDREN(queue_node);
6487 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6488 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6490 &rxq->ifr_cq_pidx, 1, "Producer Index");
6491 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6493 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6496 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6497 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6498 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6499 CTLFLAG_RD, NULL, "freelist Name");
6500 fl_list = SYSCTL_CHILDREN(fl_node);
6501 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6503 &fl->ifl_pidx, 1, "Producer Index");
6504 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6506 &fl->ifl_cidx, 1, "Consumer Index");
6507 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6509 &fl->ifl_credits, 1, "credits available");
6511 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6513 &fl->ifl_m_enqueued, "mbufs allocated");
6514 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6516 &fl->ifl_m_dequeued, "mbufs freed");
6517 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6519 &fl->ifl_cl_enqueued, "clusters allocated");
6520 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6522 &fl->ifl_cl_dequeued, "clusters freed");
6531 iflib_request_reset(if_ctx_t ctx)
6535 ctx->ifc_flags |= IFC_DO_RESET;
6539 #ifndef __NO_STRICT_ALIGNMENT
6540 static struct mbuf *
6541 iflib_fixup_rx(struct mbuf *m)
6545 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6546 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6547 m->m_data += ETHER_HDR_LEN;
6550 MGETHDR(n, M_NOWAIT, MT_DATA);
6555 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6556 m->m_data += ETHER_HDR_LEN;
6557 m->m_len -= ETHER_HDR_LEN;
6558 n->m_len = ETHER_HDR_LEN;
6559 M_MOVE_PKTHDR(n, m);
6568 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6572 ctx = if_getsoftc(ifp);
6574 *nrxr = NRXQSETS(ctx);
6575 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6576 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6581 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6584 if_softc_ctx_t scctx;
6589 ctx = if_getsoftc(ifp);
6590 scctx = &ctx->ifc_softc_ctx;
6594 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6595 rxq = &ctx->ifc_rxqs[i];
6596 for (j = 0; j < rxq->ifr_nfl; j++) {
6598 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6601 iflib_no_tx_batch = 1;
6609 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6615 ctx = if_getsoftc(ifp);
6616 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6620 txq = &ctx->ifc_txqs[0];
6621 error = iflib_encap(txq, &m);
6623 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6628 iflib_netdump_poll(struct ifnet *ifp, int count)
6631 if_softc_ctx_t scctx;
6635 ctx = if_getsoftc(ifp);
6636 scctx = &ctx->ifc_softc_ctx;
6638 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6642 txq = &ctx->ifc_txqs[0];
6643 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6645 for (i = 0; i < scctx->isc_nrxqsets; i++)
6646 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6649 #endif /* NETDUMP */