2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/sockio.h>
41 #include <sys/kernel.h>
43 #include <sys/mutex.h>
44 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
57 #include <net/if_var.h>
58 #include <net/if_types.h>
59 #include <net/if_media.h>
61 #include <net/ethernet.h>
62 #include <net/mp_ring.h>
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet6/ip6_var.h>
76 #include <machine/bus.h>
77 #include <machine/in_cksum.h>
82 #include <dev/led/led.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85 #include <dev/pci/pci_private.h>
87 #include <net/iflib.h>
91 #if defined(__i386__) || defined(__amd64__)
92 #include <sys/memdesc.h>
93 #include <machine/bus.h>
94 #include <machine/md_var.h>
95 #include <machine/specialreg.h>
96 #include <x86/include/busdma_impl.h>
97 #include <x86/iommu/busdma_dmar.h>
100 #include <sys/bitstring.h>
102 * enable accounting of every mbuf as it comes in to and goes out of
103 * iflib's software descriptor references
105 #define MEMORY_LOGGING 0
107 * Enable mbuf vectors for compressing long mbuf chains
112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
113 * we prefetch needs to be determined by the time spent in m_free vis a vis
114 * the cost of a prefetch. This will of course vary based on the workload:
115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
116 * is quite expensive, thus suggesting very little prefetch.
117 * - small packet forwarding which is just returning a single mbuf to
118 * UMA will typically be very fast vis a vis the cost of a memory
125 * - private structures
126 * - iflib private utility functions
128 * - vlan registry and other exported functions
129 * - iflib public core functions
133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
168 uint16_t ifc_nhwtxqs;
169 uint16_t ifc_nhwrxqs;
171 iflib_txq_t ifc_txqs;
172 iflib_rxq_t ifc_rxqs;
173 uint32_t ifc_if_flags;
175 uint32_t ifc_max_fl_buf_size;
180 int ifc_watchdog_events;
181 struct cdev *ifc_led_dev;
182 struct resource *ifc_msix_mem;
184 struct if_irq ifc_legacy_irq;
185 struct grouptask ifc_admin_task;
186 struct grouptask ifc_vflr_task;
187 struct iflib_filter_info ifc_filter_info;
188 struct ifmedia ifc_media;
190 struct sysctl_oid *ifc_sysctl_node;
191 uint16_t ifc_sysctl_ntxqs;
192 uint16_t ifc_sysctl_nrxqs;
193 uint16_t ifc_sysctl_qs_eq_override;
194 uint16_t ifc_sysctl_rx_budget;
196 qidx_t ifc_sysctl_ntxds[8];
197 qidx_t ifc_sysctl_nrxds[8];
198 struct if_txrx ifc_txrx;
199 #define isc_txd_encap ifc_txrx.ift_txd_encap
200 #define isc_txd_flush ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 eventhandler_tag ifc_vlan_attach_event;
210 eventhandler_tag ifc_vlan_detach_event;
211 uint8_t ifc_mac[ETHER_ADDR_LEN];
212 char ifc_mtx_name[16];
217 iflib_get_softc(if_ctx_t ctx)
220 return (ctx->ifc_softc);
224 iflib_get_dev(if_ctx_t ctx)
227 return (ctx->ifc_dev);
231 iflib_get_ifp(if_ctx_t ctx)
234 return (ctx->ifc_ifp);
238 iflib_get_media(if_ctx_t ctx)
241 return (&ctx->ifc_media);
245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
252 iflib_get_softc_ctx(if_ctx_t ctx)
255 return (&ctx->ifc_softc_ctx);
259 iflib_get_sctx(if_ctx_t ctx)
262 return (ctx->ifc_sctx);
265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
272 #define RX_SW_DESC_MAP_CREATED (1 << 0)
273 #define TX_SW_DESC_MAP_CREATED (1 << 1)
274 #define RX_SW_DESC_INUSE (1 << 3)
275 #define TX_SW_DESC_MAPPED (1 << 4)
277 #define M_TOOBIG M_PROTO1
279 typedef struct iflib_sw_rx_desc_array {
280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
281 struct mbuf **ifsd_m; /* pkthdr mbufs */
282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
284 } iflib_rxsd_array_t;
286 typedef struct iflib_sw_tx_desc_array {
287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
288 struct mbuf **ifsd_m; /* pkthdr mbufs */
293 /* magic number that should be high enough for any hardware */
294 #define IFLIB_MAX_TX_SEGS 128
295 /* bnxt supports 64 with hardware LRO enabled */
296 #define IFLIB_MAX_RX_SEGS 64
297 #define IFLIB_RX_COPY_THRESH 128
298 #define IFLIB_MAX_RX_REFRESH 32
299 /* The minimum descriptors per second before we start coalescing */
300 #define IFLIB_MIN_DESC_SEC 16384
301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
302 #define IFLIB_QUEUE_IDLE 0
303 #define IFLIB_QUEUE_HUNG 1
304 #define IFLIB_QUEUE_WORKING 2
305 /* maximum number of txqs that can share an rx interrupt */
306 #define IFLIB_MAX_TX_SHARED_INTR 4
308 /* this should really scale with ring size - this is a fairly arbitrary value */
309 #define TX_BATCH_SIZE 32
311 #define IFLIB_RESTART_BUDGET 8
313 #define IFC_LEGACY 0x001
314 #define IFC_QFLUSH 0x002
315 #define IFC_MULTISEG 0x004
316 #define IFC_DMAR 0x008
317 #define IFC_SC_ALLOCATED 0x010
318 #define IFC_INIT_DONE 0x020
319 #define IFC_PREFETCH 0x040
320 #define IFC_DO_RESET 0x080
321 #define IFC_CHECK_HUNG 0x100
323 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
324 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
325 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
329 qidx_t ift_cidx_processed;
332 uint8_t ift_br_offset;
333 uint16_t ift_npending;
334 uint16_t ift_db_pending;
335 uint16_t ift_rs_pending;
337 uint8_t ift_txd_size[8];
338 uint64_t ift_processed;
339 uint64_t ift_cleaned;
340 uint64_t ift_cleaned_prev;
342 uint64_t ift_enqueued;
343 uint64_t ift_dequeued;
345 uint64_t ift_no_tx_dma_setup;
346 uint64_t ift_no_desc_avail;
347 uint64_t ift_mbuf_defrag_failed;
348 uint64_t ift_mbuf_defrag;
349 uint64_t ift_map_failed;
350 uint64_t ift_txd_encap_efbig;
351 uint64_t ift_pullups;
354 struct mtx ift_db_mtx;
356 /* constant values */
358 struct ifmp_ring *ift_br;
359 struct grouptask ift_task;
362 struct callout ift_timer;
364 if_txsd_vec_t ift_sds;
367 uint8_t ift_update_freq;
368 struct iflib_filter_info ift_filter_info;
369 bus_dma_tag_t ift_desc_tag;
370 bus_dma_tag_t ift_tso_desc_tag;
371 iflib_dma_info_t ift_ifdi;
372 #define MTX_NAME_LEN 16
373 char ift_mtx_name[MTX_NAME_LEN];
374 char ift_db_mtx_name[MTX_NAME_LEN];
375 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
376 #ifdef IFLIB_DIAGNOSTICS
377 uint64_t ift_cpu_exec_count[256];
379 } __aligned(CACHE_LINE_SIZE);
386 uint8_t ifl_rxd_size;
388 uint64_t ifl_m_enqueued;
389 uint64_t ifl_m_dequeued;
390 uint64_t ifl_cl_enqueued;
391 uint64_t ifl_cl_dequeued;
395 bitstr_t *ifl_rx_bitmap;
399 uint16_t ifl_buf_size;
402 iflib_rxsd_array_t ifl_sds;
405 bus_dma_tag_t ifl_desc_tag;
406 iflib_dma_info_t ifl_ifdi;
407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
408 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
409 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
410 } __aligned(CACHE_LINE_SIZE);
413 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
419 else if (pidx < cidx)
420 used = size - cidx + pidx;
421 else if (gen == 0 && pidx == cidx)
423 else if (gen == 1 && pidx == cidx)
431 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
433 #define IDXDIFF(head, tail, wrap) \
434 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
437 /* If there is a separate completion queue -
438 * these are the cq cidx and pidx. Otherwise
445 uint8_t ifr_fl_offset;
451 uint8_t ifr_lro_enabled;
454 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
455 struct lro_ctrl ifr_lc;
456 struct grouptask ifr_task;
457 struct iflib_filter_info ifr_filter_info;
458 iflib_dma_info_t ifr_ifdi;
460 /* dynamically allocate if any drivers need a value substantially larger than this */
461 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
462 #ifdef IFLIB_DIAGNOSTICS
463 uint64_t ifr_cpu_exec_count[256];
465 } __aligned(CACHE_LINE_SIZE);
467 typedef struct if_rxsd {
469 struct mbuf **ifsd_m;
474 /* multiple of word size */
476 #define PKT_INFO_SIZE 6
477 #define RXD_INFO_SIZE 5
478 #define PKT_TYPE uint64_t
480 #define PKT_INFO_SIZE 11
481 #define RXD_INFO_SIZE 8
482 #define PKT_TYPE uint32_t
484 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
485 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
487 typedef struct if_pkt_info_pad {
488 PKT_TYPE pkt_val[PKT_INFO_SIZE];
489 } *if_pkt_info_pad_t;
490 typedef struct if_rxd_info_pad {
491 PKT_TYPE rxd_val[RXD_INFO_SIZE];
492 } *if_rxd_info_pad_t;
494 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
495 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
499 pkt_info_zero(if_pkt_info_t pi)
501 if_pkt_info_pad_t pi_pad;
503 pi_pad = (if_pkt_info_pad_t)pi;
504 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
505 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
507 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
508 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
513 rxd_info_zero(if_rxd_info_t ri)
515 if_rxd_info_pad_t ri_pad;
518 ri_pad = (if_rxd_info_pad_t)ri;
519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
520 ri_pad->rxd_val[i] = 0;
521 ri_pad->rxd_val[i+1] = 0;
522 ri_pad->rxd_val[i+2] = 0;
523 ri_pad->rxd_val[i+3] = 0;
526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
531 * Only allow a single packet to take up most 1/nth of the tx ring
533 #define MAX_SINGLE_PACKET_FRACTION 12
534 #define IF_BAD_DMA (bus_addr_t)-1
536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
538 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF)
540 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx)
541 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx)
542 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx)
545 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
546 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
549 /* Our boot-time initialization hook */
550 static int iflib_module_event_handler(module_t, int, void *);
552 static moduledata_t iflib_moduledata = {
554 iflib_module_event_handler,
558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
559 MODULE_VERSION(iflib, 1);
561 MODULE_DEPEND(iflib, pci, 1, 1, 1);
562 MODULE_DEPEND(iflib, ether, 1, 1, 1);
564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
567 #ifndef IFLIB_DEBUG_COUNTERS
569 #define IFLIB_DEBUG_COUNTERS 1
571 #define IFLIB_DEBUG_COUNTERS 0
572 #endif /* !INVARIANTS */
575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
576 "iflib driver parameters");
579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
581 static int iflib_min_tx_latency = 0;
582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
584 static int iflib_no_tx_batch = 0;
585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
589 #if IFLIB_DEBUG_COUNTERS
591 static int iflib_tx_seen;
592 static int iflib_tx_sent;
593 static int iflib_tx_encap;
594 static int iflib_rx_allocs;
595 static int iflib_fl_refills;
596 static int iflib_fl_refills_large;
597 static int iflib_tx_frees;
599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
600 &iflib_tx_seen, 0, "# tx mbufs seen");
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
602 &iflib_tx_sent, 0, "# tx mbufs sent");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
604 &iflib_tx_encap, 0, "# tx mbufs encapped");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
606 &iflib_tx_frees, 0, "# tx frees");
607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
608 &iflib_rx_allocs, 0, "# rx allocations");
609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
610 &iflib_fl_refills, 0, "# refills");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
612 &iflib_fl_refills_large, 0, "# large refills");
615 static int iflib_txq_drain_flushing;
616 static int iflib_txq_drain_oactive;
617 static int iflib_txq_drain_notready;
618 static int iflib_txq_drain_encapfail;
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
621 &iflib_txq_drain_flushing, 0, "# drain flushes");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
623 &iflib_txq_drain_oactive, 0, "# drain oactives");
624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
625 &iflib_txq_drain_notready, 0, "# drain notready");
626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD,
627 &iflib_txq_drain_encapfail, 0, "# drain encap fails");
630 static int iflib_encap_load_mbuf_fail;
631 static int iflib_encap_pad_mbuf_fail;
632 static int iflib_encap_txq_avail_fail;
633 static int iflib_encap_txd_encap_fail;
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
644 static int iflib_task_fn_rxs;
645 static int iflib_rx_intr_enables;
646 static int iflib_fast_intrs;
647 static int iflib_intr_link;
648 static int iflib_intr_msix;
649 static int iflib_rx_unavail;
650 static int iflib_rx_ctx_inactive;
651 static int iflib_rx_zero_len;
652 static int iflib_rx_if_input;
653 static int iflib_rx_mbuf_null;
654 static int iflib_rxd_flush;
656 static int iflib_verbose_debug;
658 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD,
659 &iflib_intr_link, 0, "# intr link calls");
660 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD,
661 &iflib_intr_msix, 0, "# intr msix calls");
662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
665 &iflib_rx_intr_enables, 0, "# rx intr enables");
666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
667 &iflib_fast_intrs, 0, "# fast_intr calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
669 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD,
673 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
675 &iflib_rx_if_input, 0, "# times rxeof called if_input");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
679 &iflib_rxd_flush, 0, "# times rxd_flush called");
680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
681 &iflib_verbose_debug, 0, "enable verbose debugging");
683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
685 iflib_debug_reset(void)
687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
689 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
690 iflib_txq_drain_notready = iflib_txq_drain_encapfail =
691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
694 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail =
695 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input =
696 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
700 #define DBG_COUNTER_INC(name)
701 static void iflib_debug_reset(void) {}
706 #define IFLIB_DEBUG 0
708 static void iflib_tx_structures_free(if_ctx_t ctx);
709 static void iflib_rx_structures_free(if_ctx_t ctx);
710 static int iflib_queues_alloc(if_ctx_t ctx);
711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
713 static int iflib_qset_structures_setup(if_ctx_t ctx);
714 static int iflib_msix_init(if_ctx_t ctx);
715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str);
716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
718 static int iflib_register(if_ctx_t);
719 static void iflib_init_locked(if_ctx_t ctx);
720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
721 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
722 static void iflib_ifmp_purge(iflib_txq_t txq);
723 static void _iflib_pre_assert(if_softc_ctx_t scctx);
724 static void iflib_stop(if_ctx_t ctx);
725 static void iflib_if_init_locked(if_ctx_t ctx);
726 #ifndef __NO_STRICT_ALIGNMENT
727 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
731 #include <sys/selinfo.h>
732 #include <net/netmap.h>
733 #include <dev/netmap/netmap_kern.h>
735 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
740 * device-specific sysctl variables:
742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
743 * During regular operations the CRC is stripped, but on some
744 * hardware reception of frames not multiple of 64 is slower,
745 * so using crcstrip=0 helps in benchmarks.
747 * iflib_rx_miss, iflib_rx_miss_bufs:
748 * count packets that might be missed due to lost interrupts.
750 SYSCTL_DECL(_dev_netmap);
752 * The xl driver by default strips CRCs and we do not override it.
755 int iflib_crcstrip = 1;
756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
759 int iflib_rx_miss, iflib_rx_miss_bufs;
760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
766 * Register/unregister. We are already under netmap lock.
767 * Only called on the first register or the last unregister.
770 iflib_netmap_register(struct netmap_adapter *na, int onoff)
772 struct ifnet *ifp = na->ifp;
773 if_ctx_t ctx = ifp->if_softc;
777 IFDI_INTR_DISABLE(ctx);
779 /* Tell the stack that the interface is no longer active */
780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
785 /* enable or disable flags and callbacks in na and ifp */
787 nm_set_native_flags(na);
789 nm_clear_native_flags(na);
792 iflib_init_locked(ctx);
793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
796 nm_clear_native_flags(na);
802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
804 struct netmap_adapter *na = kring->na;
805 u_int const lim = kring->nkr_num_slots - 1;
806 u_int head = kring->rhead;
807 struct netmap_ring *ring = kring->ring;
809 struct if_rxd_update iru;
810 if_ctx_t ctx = rxq->ifr_ctx;
811 iflib_fl_t fl = &rxq->ifr_fl[0];
812 uint32_t refill_pidx, nic_i;
814 if (nm_i == head && __predict_true(!init))
816 iru_init(&iru, rxq, 0 /* flid */);
817 map = fl->ifl_sds.ifsd_map;
818 refill_pidx = netmap_idx_k2n(kring, nm_i);
820 * IMPORTANT: we must leave one free slot in the ring,
821 * so move head back by one unit
823 head = nm_prev(head, lim);
824 while (nm_i != head) {
825 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
826 struct netmap_slot *slot = &ring->slot[nm_i];
827 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
828 uint32_t nic_i_dma = refill_pidx;
829 nic_i = netmap_idx_k2n(kring, nm_i);
831 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
833 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
834 return netmap_ring_reinit(kring);
836 fl->ifl_vm_addrs[tmp_pidx] = addr;
837 if (__predict_false(init) && map) {
838 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
839 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
840 /* buffer has changed, reload map */
841 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
843 slot->flags &= ~NS_BUF_CHANGED;
845 nm_i = nm_next(nm_i, lim);
846 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
847 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
850 iru.iru_pidx = refill_pidx;
851 iru.iru_count = tmp_pidx+1;
852 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
858 for (int n = 0; n < iru.iru_count; n++) {
859 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
860 BUS_DMASYNC_PREREAD);
861 /* XXX - change this to not use the netmap func*/
862 nic_i_dma = nm_next(nic_i_dma, lim);
866 kring->nr_hwcur = head;
869 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
871 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
876 * Reconcile kernel and user view of the transmit ring.
878 * All information is in the kring.
879 * Userspace wants to send packets up to the one before kring->rhead,
880 * kernel knows kring->nr_hwcur is the first unsent packet.
882 * Here we push packets out (as many as possible), and possibly
883 * reclaim buffers from previously completed transmission.
885 * The caller (netmap) guarantees that there is only one instance
886 * running at any time. Any interference with other driver
887 * methods should be handled by the individual drivers.
890 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
892 struct netmap_adapter *na = kring->na;
893 struct ifnet *ifp = na->ifp;
894 struct netmap_ring *ring = kring->ring;
895 u_int nm_i; /* index into the netmap ring */
896 u_int nic_i; /* index into the NIC ring */
898 u_int const lim = kring->nkr_num_slots - 1;
899 u_int const head = kring->rhead;
900 struct if_pkt_info pi;
903 * interrupts on every tx packet are expensive so request
904 * them every half ring, or where NS_REPORT is set
906 u_int report_frequency = kring->nkr_num_slots >> 1;
907 /* device-specific */
908 if_ctx_t ctx = ifp->if_softc;
909 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
911 if (txq->ift_sds.ifsd_map)
912 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
913 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
917 * First part: process new packets to send.
918 * nm_i is the current index in the netmap ring,
919 * nic_i is the corresponding index in the NIC ring.
921 * If we have packets to send (nm_i != head)
922 * iterate over the netmap ring, fetch length and update
923 * the corresponding slot in the NIC ring. Some drivers also
924 * need to update the buffer's physical address in the NIC slot
925 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
927 * The netmap_reload_map() calls is especially expensive,
928 * even when (as in this case) the tag is 0, so do only
929 * when the buffer has actually changed.
931 * If possible do not set the report/intr bit on all slots,
932 * but only a few times per ring or when NS_REPORT is set.
934 * Finally, on 10G and faster drivers, it might be useful
935 * to prefetch the next slot and txr entry.
938 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
940 pi.ipi_segs = txq->ift_segs;
941 pi.ipi_qsidx = kring->ring_id;
942 if (nm_i != head) { /* we have new packets to send */
943 nic_i = netmap_idx_k2n(kring, nm_i);
945 __builtin_prefetch(&ring->slot[nm_i]);
946 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
947 if (txq->ift_sds.ifsd_map)
948 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
950 for (n = 0; nm_i != head; n++) {
951 struct netmap_slot *slot = &ring->slot[nm_i];
952 u_int len = slot->len;
954 void *addr = PNMB(na, slot, &paddr);
955 int flags = (slot->flags & NS_REPORT ||
956 nic_i == 0 || nic_i == report_frequency) ?
959 /* device-specific */
961 pi.ipi_segs[0].ds_addr = paddr;
962 pi.ipi_segs[0].ds_len = len;
966 pi.ipi_flags = flags;
968 /* Fill the slot in the NIC ring. */
969 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
971 /* prefetch for next round */
972 __builtin_prefetch(&ring->slot[nm_i + 1]);
973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
974 if (txq->ift_sds.ifsd_map) {
975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
977 NM_CHECK_ADDR_LEN(na, addr, len);
979 if (slot->flags & NS_BUF_CHANGED) {
980 /* buffer has changed, reload map */
981 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
983 /* make sure changes to the buffer are synced */
984 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
985 BUS_DMASYNC_PREWRITE);
987 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
988 nm_i = nm_next(nm_i, lim);
989 nic_i = nm_next(nic_i, lim);
991 kring->nr_hwcur = head;
993 /* synchronize the NIC ring */
994 if (txq->ift_sds.ifsd_map)
995 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
998 /* (re)start the tx unit up to slot nic_i (excluded) */
999 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1003 * Second part: reclaim buffers for completed transmissions.
1005 if (iflib_tx_credits_update(ctx, txq)) {
1006 /* some tx completed, increment avail */
1007 nic_i = txq->ift_cidx_processed;
1008 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1014 * Reconcile kernel and user view of the receive ring.
1015 * Same as for the txsync, this routine must be efficient.
1016 * The caller guarantees a single invocations, but races against
1017 * the rest of the driver should be handled here.
1019 * On call, kring->rhead is the first packet that userspace wants
1020 * to keep, and kring->rcur is the wakeup point.
1021 * The kernel has previously reported packets up to kring->rtail.
1023 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1024 * of whether or not we received an interrupt.
1027 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1029 struct netmap_adapter *na = kring->na;
1030 struct netmap_ring *ring = kring->ring;
1031 uint32_t nm_i; /* index into the netmap ring */
1032 uint32_t nic_i; /* index into the NIC ring */
1034 u_int const lim = kring->nkr_num_slots - 1;
1035 u_int const head = netmap_idx_n2k(kring, kring->rhead);
1036 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1037 struct if_rxd_info ri;
1039 struct ifnet *ifp = na->ifp;
1040 if_ctx_t ctx = ifp->if_softc;
1041 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1042 iflib_fl_t fl = rxq->ifr_fl;
1044 return netmap_ring_reinit(kring);
1046 /* XXX check sync modes */
1047 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1048 if (fl->ifl_sds.ifsd_map == NULL)
1050 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1054 * First part: import newly received packets.
1056 * nm_i is the index of the next free slot in the netmap ring,
1057 * nic_i is the index of the next received packet in the NIC ring,
1058 * and they may differ in case if_init() has been called while
1059 * in netmap mode. For the receive ring we have
1061 * nic_i = rxr->next_check;
1062 * nm_i = kring->nr_hwtail (previous)
1064 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1066 * rxr->next_check is set to 0 on a ring reinit
1068 if (netmap_no_pendintr || force_update) {
1069 int crclen = iflib_crcstrip ? 0 : 4;
1071 uint16_t slot_flags = kring->nkr_slot_flags;
1073 for (i = 0; i < rxq->ifr_nfl; i++) {
1074 fl = &rxq->ifr_fl[i];
1075 nic_i = fl->ifl_cidx;
1076 nm_i = netmap_idx_n2k(kring, nic_i);
1077 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1078 for (n = 0; avail > 0; n++, avail--) {
1080 ri.iri_frags = rxq->ifr_frags;
1081 ri.iri_qsidx = kring->ring_id;
1082 ri.iri_ifp = ctx->ifc_ifp;
1083 ri.iri_cidx = nic_i;
1085 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1086 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1087 ring->slot[nm_i].flags = slot_flags;
1088 if (fl->ifl_sds.ifsd_map)
1089 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1090 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1091 nm_i = nm_next(nm_i, lim);
1092 nic_i = nm_next(nic_i, lim);
1094 if (n) { /* update the state variables */
1095 if (netmap_no_pendintr && !force_update) {
1098 iflib_rx_miss_bufs += n;
1100 fl->ifl_cidx = nic_i;
1101 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i);
1103 kring->nr_kflags &= ~NKR_PENDINTR;
1107 * Second part: skip past packets that userspace has released.
1108 * (kring->nr_hwcur to head excluded),
1109 * and make the buffers available for reception.
1110 * As usual nm_i is the index in the netmap ring,
1111 * nic_i is the index in the NIC ring, and
1112 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1114 /* XXX not sure how this will work with multiple free lists */
1115 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur);
1117 return (netmap_fl_refill(rxq, kring, nm_i, false));
1121 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1123 struct ifnet *ifp = na->ifp;
1124 if_ctx_t ctx = ifp->if_softc;
1128 IFDI_INTR_ENABLE(ctx);
1130 IFDI_INTR_DISABLE(ctx);
1137 iflib_netmap_attach(if_ctx_t ctx)
1139 struct netmap_adapter na;
1140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1142 bzero(&na, sizeof(na));
1144 na.ifp = ctx->ifc_ifp;
1145 na.na_flags = NAF_BDG_MAYSLEEP;
1146 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1147 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1149 na.num_tx_desc = scctx->isc_ntxd[0];
1150 na.num_rx_desc = scctx->isc_nrxd[0];
1151 na.nm_txsync = iflib_netmap_txsync;
1152 na.nm_rxsync = iflib_netmap_rxsync;
1153 na.nm_register = iflib_netmap_register;
1154 na.nm_intr = iflib_netmap_intr;
1155 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1156 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1157 return (netmap_attach(&na));
1161 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1163 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1164 struct netmap_slot *slot;
1166 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1169 if (txq->ift_sds.ifsd_map == NULL)
1172 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1175 * In netmap mode, set the map for the packet buffer.
1176 * NOTE: Some drivers (not this one) also need to set
1177 * the physical buffer address in the NIC ring.
1178 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1179 * netmap slot index, si
1181 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i);
1182 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1187 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1189 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1190 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id];
1191 struct netmap_slot *slot;
1194 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1197 nm_i = netmap_idx_n2k(kring, 0);
1198 netmap_fl_refill(rxq, kring, nm_i, true);
1201 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1204 #define iflib_netmap_txq_init(ctx, txq)
1205 #define iflib_netmap_rxq_init(ctx, rxq)
1206 #define iflib_netmap_detach(ifp)
1208 #define iflib_netmap_attach(ctx) (0)
1209 #define netmap_rx_irq(ifp, qid, budget) (0)
1210 #define netmap_tx_irq(ifp, qid) do {} while (0)
1214 #if defined(__i386__) || defined(__amd64__)
1215 static __inline void
1218 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1220 static __inline void
1221 prefetch2cachelines(void *x)
1223 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1224 #if (CACHE_LINE_SIZE < 128)
1225 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1230 #define prefetch2cachelines(x)
1234 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1238 fl = &rxq->ifr_fl[flid];
1239 iru->iru_paddrs = fl->ifl_bus_addrs;
1240 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1241 iru->iru_idxs = fl->ifl_rxd_idxs;
1242 iru->iru_qsidx = rxq->ifr_id;
1243 iru->iru_buf_size = fl->ifl_buf_size;
1244 iru->iru_flidx = fl->ifl_id;
1248 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1252 *(bus_addr_t *) arg = segs[0].ds_addr;
1256 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1259 if_shared_ctx_t sctx = ctx->ifc_sctx;
1260 device_t dev = ctx->ifc_dev;
1262 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1264 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1265 sctx->isc_q_align, 0, /* alignment, bounds */
1266 BUS_SPACE_MAXADDR, /* lowaddr */
1267 BUS_SPACE_MAXADDR, /* highaddr */
1268 NULL, NULL, /* filter, filterarg */
1271 size, /* maxsegsize */
1272 BUS_DMA_ALLOCNOW, /* flags */
1273 NULL, /* lockfunc */
1278 "%s: bus_dma_tag_create failed: %d\n",
1283 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1284 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1287 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1288 __func__, (uintmax_t)size, err);
1292 dma->idi_paddr = IF_BAD_DMA;
1293 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1294 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1295 if (err || dma->idi_paddr == IF_BAD_DMA) {
1297 "%s: bus_dmamap_load failed: %d\n",
1302 dma->idi_size = size;
1306 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1308 bus_dma_tag_destroy(dma->idi_tag);
1310 dma->idi_tag = NULL;
1316 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1319 iflib_dma_info_t *dmaiter;
1322 for (i = 0; i < count; i++, dmaiter++) {
1323 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1327 iflib_dma_free_multi(dmalist, i);
1332 iflib_dma_free(iflib_dma_info_t dma)
1334 if (dma->idi_tag == NULL)
1336 if (dma->idi_paddr != IF_BAD_DMA) {
1337 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1339 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1340 dma->idi_paddr = IF_BAD_DMA;
1342 if (dma->idi_vaddr != NULL) {
1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1344 dma->idi_vaddr = NULL;
1346 bus_dma_tag_destroy(dma->idi_tag);
1347 dma->idi_tag = NULL;
1351 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1354 iflib_dma_info_t *dmaiter = dmalist;
1356 for (i = 0; i < count; i++, dmaiter++)
1357 iflib_dma_free(*dmaiter);
1360 #ifdef EARLY_AP_STARTUP
1361 static const int iflib_started = 1;
1364 * We used to abuse the smp_started flag to decide if the queues have been
1365 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1366 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1367 * is set. Run a SYSINIT() strictly after that to just set a usable
1371 static int iflib_started;
1374 iflib_record_started(void *arg)
1379 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1380 iflib_record_started, NULL);
1384 iflib_fast_intr(void *arg)
1386 iflib_filter_info_t info = arg;
1387 struct grouptask *gtask = info->ifi_task;
1389 return (FILTER_HANDLED);
1391 DBG_COUNTER_INC(fast_intrs);
1392 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1393 return (FILTER_HANDLED);
1395 GROUPTASK_ENQUEUE(gtask);
1396 return (FILTER_HANDLED);
1400 iflib_fast_intr_rxtx(void *arg)
1402 iflib_filter_info_t info = arg;
1403 struct grouptask *gtask = info->ifi_task;
1404 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1409 return (FILTER_HANDLED);
1411 DBG_COUNTER_INC(fast_intrs);
1412 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1413 return (FILTER_HANDLED);
1415 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1416 qidx_t txqid = rxq->ifr_txqid[i];
1420 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1421 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1424 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1426 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1427 cidx = rxq->ifr_cq_cidx;
1429 cidx = rxq->ifr_fl[0].ifl_cidx;
1430 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1431 GROUPTASK_ENQUEUE(gtask);
1433 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1434 return (FILTER_HANDLED);
1439 iflib_fast_intr_ctx(void *arg)
1441 iflib_filter_info_t info = arg;
1442 struct grouptask *gtask = info->ifi_task;
1445 return (FILTER_HANDLED);
1447 DBG_COUNTER_INC(fast_intrs);
1448 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1449 return (FILTER_HANDLED);
1451 GROUPTASK_ENQUEUE(gtask);
1452 return (FILTER_HANDLED);
1456 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1457 driver_filter_t filter, driver_intr_t handler, void *arg,
1461 struct resource *res;
1463 device_t dev = ctx->ifc_dev;
1466 if (ctx->ifc_flags & IFC_LEGACY)
1467 flags |= RF_SHAREABLE;
1470 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1473 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1477 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1478 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1479 filter, handler, arg, &tag);
1482 "failed to setup interrupt for rid %d, name %s: %d\n",
1483 rid, name ? name : "unknown", rc);
1486 bus_describe_intr(dev, res, tag, "%s", name);
1493 /*********************************************************************
1495 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1496 * the information needed to transmit a packet on the wire. This is
1497 * called only once at attach, setup is done every reset.
1499 **********************************************************************/
1502 iflib_txsd_alloc(iflib_txq_t txq)
1504 if_ctx_t ctx = txq->ift_ctx;
1505 if_shared_ctx_t sctx = ctx->ifc_sctx;
1506 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1507 device_t dev = ctx->ifc_dev;
1508 int err, nsegments, ntsosegments;
1510 nsegments = scctx->isc_tx_nsegments;
1511 ntsosegments = scctx->isc_tx_tso_segments_max;
1512 MPASS(scctx->isc_ntxd[0] > 0);
1513 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1514 MPASS(nsegments > 0);
1515 MPASS(ntsosegments > 0);
1517 * Setup DMA descriptor areas.
1519 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1520 1, 0, /* alignment, bounds */
1521 BUS_SPACE_MAXADDR, /* lowaddr */
1522 BUS_SPACE_MAXADDR, /* highaddr */
1523 NULL, NULL, /* filter, filterarg */
1524 sctx->isc_tx_maxsize, /* maxsize */
1525 nsegments, /* nsegments */
1526 sctx->isc_tx_maxsegsize, /* maxsegsize */
1528 NULL, /* lockfunc */
1529 NULL, /* lockfuncarg */
1530 &txq->ift_desc_tag))) {
1531 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1532 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1533 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1536 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1537 1, 0, /* alignment, bounds */
1538 BUS_SPACE_MAXADDR, /* lowaddr */
1539 BUS_SPACE_MAXADDR, /* highaddr */
1540 NULL, NULL, /* filter, filterarg */
1541 scctx->isc_tx_tso_size_max, /* maxsize */
1542 ntsosegments, /* nsegments */
1543 scctx->isc_tx_tso_segsize_max, /* maxsegsize */
1545 NULL, /* lockfunc */
1546 NULL, /* lockfuncarg */
1547 &txq->ift_tso_desc_tag))) {
1548 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1552 if (!(txq->ift_sds.ifsd_flags =
1553 (uint8_t *) malloc(sizeof(uint8_t) *
1554 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1555 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1559 if (!(txq->ift_sds.ifsd_m =
1560 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1561 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1562 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1567 /* Create the descriptor buffer dma maps */
1568 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1569 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1572 if (!(txq->ift_sds.ifsd_map =
1573 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1574 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1579 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1580 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1582 device_printf(dev, "Unable to create TX DMA map\n");
1589 /* We free all, it handles case where we are in the middle */
1590 iflib_tx_structures_free(ctx);
1595 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1600 if (txq->ift_sds.ifsd_map != NULL)
1601 map = txq->ift_sds.ifsd_map[i];
1603 bus_dmamap_unload(txq->ift_desc_tag, map);
1604 bus_dmamap_destroy(txq->ift_desc_tag, map);
1605 txq->ift_sds.ifsd_map[i] = NULL;
1610 iflib_txq_destroy(iflib_txq_t txq)
1612 if_ctx_t ctx = txq->ift_ctx;
1614 for (int i = 0; i < txq->ift_size; i++)
1615 iflib_txsd_destroy(ctx, txq, i);
1616 if (txq->ift_sds.ifsd_map != NULL) {
1617 free(txq->ift_sds.ifsd_map, M_IFLIB);
1618 txq->ift_sds.ifsd_map = NULL;
1620 if (txq->ift_sds.ifsd_m != NULL) {
1621 free(txq->ift_sds.ifsd_m, M_IFLIB);
1622 txq->ift_sds.ifsd_m = NULL;
1624 if (txq->ift_sds.ifsd_flags != NULL) {
1625 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1626 txq->ift_sds.ifsd_flags = NULL;
1628 if (txq->ift_desc_tag != NULL) {
1629 bus_dma_tag_destroy(txq->ift_desc_tag);
1630 txq->ift_desc_tag = NULL;
1632 if (txq->ift_tso_desc_tag != NULL) {
1633 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1634 txq->ift_tso_desc_tag = NULL;
1639 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1643 mp = &txq->ift_sds.ifsd_m[i];
1647 if (txq->ift_sds.ifsd_map != NULL) {
1648 bus_dmamap_sync(txq->ift_desc_tag,
1649 txq->ift_sds.ifsd_map[i],
1650 BUS_DMASYNC_POSTWRITE);
1651 bus_dmamap_unload(txq->ift_desc_tag,
1652 txq->ift_sds.ifsd_map[i]);
1655 DBG_COUNTER_INC(tx_frees);
1660 iflib_txq_setup(iflib_txq_t txq)
1662 if_ctx_t ctx = txq->ift_ctx;
1663 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1664 iflib_dma_info_t di;
1667 /* Set number of descriptors available */
1668 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1669 /* XXX make configurable */
1670 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1673 txq->ift_cidx_processed = 0;
1674 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1675 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1677 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1678 bzero((void *)di->idi_vaddr, di->idi_size);
1680 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1681 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++)
1682 bus_dmamap_sync(di->idi_tag, di->idi_map,
1683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1687 /*********************************************************************
1689 * Allocate memory for rx_buffer structures. Since we use one
1690 * rx_buffer per received packet, the maximum number of rx_buffer's
1691 * that we'll need is equal to the number of receive descriptors
1692 * that we've allocated.
1694 **********************************************************************/
1696 iflib_rxsd_alloc(iflib_rxq_t rxq)
1698 if_ctx_t ctx = rxq->ifr_ctx;
1699 if_shared_ctx_t sctx = ctx->ifc_sctx;
1700 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1701 device_t dev = ctx->ifc_dev;
1705 MPASS(scctx->isc_nrxd[0] > 0);
1706 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1709 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1710 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1711 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1712 1, 0, /* alignment, bounds */
1713 BUS_SPACE_MAXADDR, /* lowaddr */
1714 BUS_SPACE_MAXADDR, /* highaddr */
1715 NULL, NULL, /* filter, filterarg */
1716 sctx->isc_rx_maxsize, /* maxsize */
1717 sctx->isc_rx_nsegments, /* nsegments */
1718 sctx->isc_rx_maxsegsize, /* maxsegsize */
1720 NULL, /* lockfunc */
1724 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1728 if (!(fl->ifl_sds.ifsd_flags =
1729 (uint8_t *) malloc(sizeof(uint8_t) *
1730 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1731 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1735 if (!(fl->ifl_sds.ifsd_m =
1736 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1737 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1738 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1742 if (!(fl->ifl_sds.ifsd_cl =
1743 (caddr_t *) malloc(sizeof(caddr_t) *
1744 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1745 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1750 /* Create the descriptor buffer dma maps */
1751 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1752 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1755 if (!(fl->ifl_sds.ifsd_map =
1756 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1757 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1762 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1763 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1765 device_printf(dev, "Unable to create RX buffer DMA map\n");
1774 iflib_rx_structures_free(ctx);
1780 * Internal service routines
1783 struct rxq_refill_cb_arg {
1785 bus_dma_segment_t seg;
1790 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1792 struct rxq_refill_cb_arg *cb_arg = arg;
1794 cb_arg->error = error;
1795 cb_arg->seg = segs[0];
1796 cb_arg->nseg = nseg;
1801 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1803 #define IS_DMAR(ctx) (0)
1807 * rxq_refill - refill an rxq free-buffer list
1808 * @ctx: the iflib context
1809 * @rxq: the free-list to refill
1810 * @n: the number of new buffers to allocate
1812 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1813 * The caller must assure that @n does not exceed the queue's capacity.
1816 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1819 int idx, frag_idx = fl->ifl_fragidx;
1820 int pidx = fl->ifl_pidx;
1824 struct if_rxd_update iru;
1825 bus_dmamap_t *sd_map;
1831 sd_m = fl->ifl_sds.ifsd_m;
1832 sd_map = fl->ifl_sds.ifsd_map;
1833 sd_cl = fl->ifl_sds.ifsd_cl;
1834 sd_flags = fl->ifl_sds.ifsd_flags;
1836 credits = fl->ifl_credits;
1840 MPASS(credits + n <= fl->ifl_size);
1842 if (pidx < fl->ifl_cidx)
1843 MPASS(pidx + n <= fl->ifl_cidx);
1844 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1845 MPASS(fl->ifl_gen == 0);
1846 if (pidx > fl->ifl_cidx)
1847 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1849 DBG_COUNTER_INC(fl_refills);
1851 DBG_COUNTER_INC(fl_refills_large);
1852 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1855 * We allocate an uninitialized mbuf + cluster, mbuf is
1856 * initialized after rx.
1858 * If the cluster is still set then we know a minimum sized packet was received
1860 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1861 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1862 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1863 if ((cl = sd_cl[frag_idx]) == NULL) {
1864 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1867 fl->ifl_cl_enqueued++;
1870 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1874 fl->ifl_m_enqueued++;
1877 DBG_COUNTER_INC(rx_allocs);
1878 #if defined(__i386__) || defined(__amd64__)
1879 if (!IS_DMAR(ctx)) {
1880 bus_addr = pmap_kextract((vm_offset_t)cl);
1884 struct rxq_refill_cb_arg cb_arg;
1889 MPASS(sd_map != NULL);
1890 MPASS(sd_map[frag_idx] != NULL);
1891 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1892 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
1893 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
1894 BUS_DMASYNC_PREREAD);
1896 if (err != 0 || cb_arg.error) {
1900 if (fl->ifl_zone == zone_pack)
1901 uma_zfree(fl->ifl_zone, cl);
1906 bus_addr = cb_arg.seg.ds_addr;
1908 bit_set(fl->ifl_rx_bitmap, frag_idx);
1909 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
1911 MPASS(sd_m[frag_idx] == NULL);
1912 sd_cl[frag_idx] = cl;
1914 fl->ifl_rxd_idxs[i] = frag_idx;
1915 fl->ifl_bus_addrs[i] = bus_addr;
1916 fl->ifl_vm_addrs[i] = cl;
1919 MPASS(credits <= fl->ifl_size);
1920 if (++idx == fl->ifl_size) {
1924 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
1925 iru.iru_pidx = pidx;
1927 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1931 fl->ifl_credits = credits;
1937 iru.iru_pidx = pidx;
1939 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
1941 fl->ifl_credits = credits;
1943 DBG_COUNTER_INC(rxd_flush);
1944 if (fl->ifl_pidx == 0)
1945 pidx = fl->ifl_size - 1;
1947 pidx = fl->ifl_pidx - 1;
1950 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1952 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
1953 fl->ifl_fragidx = frag_idx;
1956 static __inline void
1957 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
1959 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
1960 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
1962 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
1965 MPASS(fl->ifl_credits <= fl->ifl_size);
1966 MPASS(reclaimable == delta);
1968 if (reclaimable > 0)
1969 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
1973 iflib_fl_bufs_free(iflib_fl_t fl)
1975 iflib_dma_info_t idi = fl->ifl_ifdi;
1978 for (i = 0; i < fl->ifl_size; i++) {
1979 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
1980 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
1981 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
1983 if (*sd_flags & RX_SW_DESC_INUSE) {
1984 if (fl->ifl_sds.ifsd_map != NULL) {
1985 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
1986 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
1987 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach)
1988 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
1990 if (*sd_m != NULL) {
1991 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
1992 uma_zfree(zone_mbuf, *sd_m);
1995 uma_zfree(fl->ifl_zone, *sd_cl);
1998 MPASS(*sd_cl == NULL);
1999 MPASS(*sd_m == NULL);
2002 fl->ifl_m_dequeued++;
2003 fl->ifl_cl_dequeued++;
2009 for (i = 0; i < fl->ifl_size; i++) {
2010 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2011 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2012 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2016 * Reset free list values
2018 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2019 bzero(idi->idi_vaddr, idi->idi_size);
2022 /*********************************************************************
2024 * Initialize a receive ring and its buffers.
2026 **********************************************************************/
2028 iflib_fl_setup(iflib_fl_t fl)
2030 iflib_rxq_t rxq = fl->ifl_rxq;
2031 if_ctx_t ctx = rxq->ifr_ctx;
2032 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2034 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2036 ** Free current RX buffer structs and their mbufs
2038 iflib_fl_bufs_free(fl);
2039 /* Now replenish the mbufs */
2040 MPASS(fl->ifl_credits == 0);
2042 * XXX don't set the max_frame_size to larger
2043 * than the hardware can handle
2045 if (sctx->isc_max_frame_size <= 2048)
2046 fl->ifl_buf_size = MCLBYTES;
2047 #ifndef CONTIGMALLOC_WORKS
2049 fl->ifl_buf_size = MJUMPAGESIZE;
2051 else if (sctx->isc_max_frame_size <= 4096)
2052 fl->ifl_buf_size = MJUMPAGESIZE;
2053 else if (sctx->isc_max_frame_size <= 9216)
2054 fl->ifl_buf_size = MJUM9BYTES;
2056 fl->ifl_buf_size = MJUM16BYTES;
2058 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2059 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2060 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2061 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2064 /* avoid pre-allocating zillions of clusters to an idle card
2065 * potentially speeding up attach
2067 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2068 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2069 if (min(128, fl->ifl_size) != fl->ifl_credits)
2075 MPASS(fl->ifl_ifdi != NULL);
2076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2081 /*********************************************************************
2083 * Free receive ring data structures
2085 **********************************************************************/
2087 iflib_rx_sds_free(iflib_rxq_t rxq)
2092 if (rxq->ifr_fl != NULL) {
2093 for (i = 0; i < rxq->ifr_nfl; i++) {
2094 fl = &rxq->ifr_fl[i];
2095 if (fl->ifl_desc_tag != NULL) {
2096 bus_dma_tag_destroy(fl->ifl_desc_tag);
2097 fl->ifl_desc_tag = NULL;
2099 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2100 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2101 /* XXX destroy maps first */
2102 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2103 fl->ifl_sds.ifsd_m = NULL;
2104 fl->ifl_sds.ifsd_cl = NULL;
2105 fl->ifl_sds.ifsd_map = NULL;
2107 free(rxq->ifr_fl, M_IFLIB);
2109 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2114 * MI independent logic
2118 iflib_timer(void *arg)
2120 iflib_txq_t txq = arg;
2121 if_ctx_t ctx = txq->ift_ctx;
2122 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2124 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2127 ** Check on the state of the TX queue(s), this
2128 ** can be done without the lock because its RO
2129 ** and the HUNG state will be static if set.
2131 IFDI_TIMER(ctx, txq->ift_id);
2132 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2133 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2134 (sctx->isc_pause_frames == 0)))
2137 if (ifmp_ring_is_stalled(txq->ift_br))
2138 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2139 txq->ift_cleaned_prev = txq->ift_cleaned;
2140 /* handle any laggards */
2141 if (txq->ift_db_pending)
2142 GROUPTASK_ENQUEUE(&txq->ift_task);
2144 sctx->isc_pause_frames = 0;
2145 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2146 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
2150 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2151 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2152 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2154 IFDI_WATCHDOG_RESET(ctx);
2155 ctx->ifc_watchdog_events++;
2157 ctx->ifc_flags |= IFC_DO_RESET;
2158 iflib_admin_intr_deferred(ctx);
2163 iflib_init_locked(if_ctx_t ctx)
2165 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2166 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2167 if_t ifp = ctx->ifc_ifp;
2171 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2174 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2175 IFDI_INTR_DISABLE(ctx);
2177 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2178 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2179 /* Set hardware offload abilities */
2180 if_clearhwassist(ifp);
2181 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2182 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2183 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2184 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2185 if (if_getcapenable(ifp) & IFCAP_TSO4)
2186 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2187 if (if_getcapenable(ifp) & IFCAP_TSO6)
2188 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2190 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2192 callout_stop(&txq->ift_timer);
2193 CALLOUT_UNLOCK(txq);
2194 iflib_netmap_txq_init(ctx, txq);
2197 i = if_getdrvflags(ifp);
2200 MPASS(if_getdrvflags(ifp) == i);
2201 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2202 /* XXX this should really be done on a per-queue basis */
2203 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2204 MPASS(rxq->ifr_id == i);
2205 iflib_netmap_rxq_init(ctx, rxq);
2208 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2209 if (iflib_fl_setup(fl)) {
2210 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2216 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2217 IFDI_INTR_ENABLE(ctx);
2218 txq = ctx->ifc_txqs;
2219 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2220 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2221 txq->ift_timer.c_cpu);
2225 iflib_media_change(if_t ifp)
2227 if_ctx_t ctx = if_getsoftc(ifp);
2231 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2232 iflib_init_locked(ctx);
2238 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2240 if_ctx_t ctx = if_getsoftc(ifp);
2243 IFDI_UPDATE_ADMIN_STATUS(ctx);
2244 IFDI_MEDIA_STATUS(ctx, ifmr);
2249 iflib_stop(if_ctx_t ctx)
2251 iflib_txq_t txq = ctx->ifc_txqs;
2252 iflib_rxq_t rxq = ctx->ifc_rxqs;
2253 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2254 iflib_dma_info_t di;
2258 /* Tell the stack that the interface is no longer active */
2259 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2261 IFDI_INTR_DISABLE(ctx);
2266 iflib_debug_reset();
2267 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2268 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2269 /* make sure all transmitters have completed before proceeding XXX */
2271 /* clean any enqueued buffers */
2272 iflib_ifmp_purge(txq);
2273 /* Free any existing tx buffers. */
2274 for (j = 0; j < txq->ift_size; j++) {
2275 iflib_txsd_free(ctx, txq, j);
2277 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2278 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2279 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2280 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2281 txq->ift_pullups = 0;
2282 ifmp_ring_reset_stats(txq->ift_br);
2283 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++)
2284 bzero((void *)di->idi_vaddr, di->idi_size);
2286 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2287 /* make sure all transmitters have completed before proceeding XXX */
2289 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++)
2290 bzero((void *)di->idi_vaddr, di->idi_size);
2291 /* also resets the free lists pidx/cidx */
2292 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2293 iflib_fl_bufs_free(fl);
2297 static inline caddr_t
2298 calc_next_rxd(iflib_fl_t fl, int cidx)
2302 caddr_t start, end, cur, next;
2304 nrxd = fl->ifl_size;
2305 size = fl->ifl_rxd_size;
2306 start = fl->ifl_ifdi->idi_vaddr;
2308 if (__predict_false(size == 0))
2310 cur = start + size*cidx;
2311 end = start + size*nrxd;
2312 next = CACHE_PTR_NEXT(cur);
2313 return (next < end ? next : start);
2317 prefetch_pkts(iflib_fl_t fl, int cidx)
2320 int nrxd = fl->ifl_size;
2324 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2325 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2326 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2327 next_rxd = calc_next_rxd(fl, cidx);
2329 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2330 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2331 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2332 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2333 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2334 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2335 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2336 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2340 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2345 iflib_dma_info_t di;
2349 flid = irf->irf_flid;
2350 cidx = irf->irf_idx;
2351 fl = &rxq->ifr_fl[flid];
2353 sd->ifsd_cidx = cidx;
2354 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2355 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2358 fl->ifl_m_dequeued++;
2360 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2361 prefetch_pkts(fl, cidx);
2362 if (fl->ifl_sds.ifsd_map != NULL) {
2363 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2364 prefetch(&fl->ifl_sds.ifsd_map[next]);
2365 map = fl->ifl_sds.ifsd_map[cidx];
2367 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2368 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2369 bus_dmamap_sync(di->idi_tag, di->idi_map,
2370 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2372 /* not valid assert if bxe really does SGE from non-contiguous elements */
2373 MPASS(fl->ifl_cidx == cidx);
2375 bus_dmamap_unload(fl->ifl_desc_tag, map);
2377 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2378 if (__predict_false(fl->ifl_cidx == 0))
2381 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2383 bit_clear(fl->ifl_rx_bitmap, cidx);
2386 static struct mbuf *
2387 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2389 int i, padlen , flags;
2390 struct mbuf *m, *mh, *mt;
2396 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2398 MPASS(*sd->ifsd_cl != NULL);
2399 MPASS(*sd->ifsd_m != NULL);
2401 /* Don't include zero-length frags */
2402 if (ri->iri_frags[i].irf_len == 0) {
2403 /* XXX we can save the cluster here, but not the mbuf */
2404 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2405 m_free(*sd->ifsd_m);
2412 flags = M_PKTHDR|M_EXT;
2414 padlen = ri->iri_pad;
2419 /* assuming padding is only on the first fragment */
2423 *sd->ifsd_cl = NULL;
2425 /* Can these two be made one ? */
2426 m_init(m, M_NOWAIT, MT_DATA, flags);
2427 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2429 * These must follow m_init and m_cljset
2431 m->m_data += padlen;
2432 ri->iri_len -= padlen;
2433 m->m_len = ri->iri_frags[i].irf_len;
2434 } while (++i < ri->iri_nfrags);
2440 * Process one software descriptor
2442 static struct mbuf *
2443 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2448 /* should I merge this back in now that the two paths are basically duplicated? */
2449 if (ri->iri_nfrags == 1 &&
2450 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) {
2451 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2454 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2455 #ifndef __NO_STRICT_ALIGNMENT
2459 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2460 m->m_len = ri->iri_frags[0].irf_len;
2462 m = assemble_segments(rxq, ri, &sd);
2464 m->m_pkthdr.len = ri->iri_len;
2465 m->m_pkthdr.rcvif = ri->iri_ifp;
2466 m->m_flags |= ri->iri_flags;
2467 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2468 m->m_pkthdr.flowid = ri->iri_flowid;
2469 M_HASHTYPE_SET(m, ri->iri_rsstype);
2470 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2471 m->m_pkthdr.csum_data = ri->iri_csum_data;
2475 #if defined(INET6) || defined(INET)
2477 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2479 CURVNET_SET(lc->ifp->if_vnet);
2481 *v6 = VNET(ip6_forwarding);
2484 *v4 = VNET(ipforwarding);
2490 * Returns true if it's possible this packet could be LROed.
2491 * if it returns false, it is guaranteed that tcp_lro_rx()
2492 * would not return zero.
2495 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2497 struct ether_header *eh;
2500 eh = mtod(m, struct ether_header *);
2501 eh_type = ntohs(eh->ether_type);
2504 case ETHERTYPE_IPV6:
2505 return !v6_forwarding;
2509 return !v4_forwarding;
2517 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2523 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2525 if_ctx_t ctx = rxq->ifr_ctx;
2526 if_shared_ctx_t sctx = ctx->ifc_sctx;
2527 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2530 struct if_rxd_info ri;
2531 int err, budget_left, rx_bytes, rx_pkts;
2535 bool lro_possible = false;
2536 bool v4_forwarding, v6_forwarding;
2539 * XXX early demux data packets so that if_input processing only handles
2540 * acks in interrupt context
2542 struct mbuf *m, *mh, *mt, *mf;
2547 rx_pkts = rx_bytes = 0;
2548 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2549 cidxp = &rxq->ifr_cq_cidx;
2551 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2552 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2553 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2554 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2555 DBG_COUNTER_INC(rx_unavail);
2559 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) {
2560 if (__predict_false(!CTX_ACTIVE(ctx))) {
2561 DBG_COUNTER_INC(rx_ctx_inactive);
2565 * Reset client set fields to their default values
2568 ri.iri_qsidx = rxq->ifr_id;
2569 ri.iri_cidx = *cidxp;
2571 ri.iri_frags = rxq->ifr_frags;
2572 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2576 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2577 *cidxp = ri.iri_cidx;
2578 /* Update our consumer index */
2579 /* XXX NB: shurd - check if this is still safe */
2580 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2581 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2582 rxq->ifr_cq_gen = 0;
2584 /* was this only a completion queue message? */
2585 if (__predict_false(ri.iri_nfrags == 0))
2588 MPASS(ri.iri_nfrags != 0);
2589 MPASS(ri.iri_len != 0);
2591 /* will advance the cidx on the corresponding free lists */
2592 m = iflib_rxd_pkt_get(rxq, &ri);
2593 if (avail == 0 && budget_left)
2594 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2596 if (__predict_false(m == NULL)) {
2597 DBG_COUNTER_INC(rx_mbuf_null);
2600 /* imm_pkt: -- cxgb */
2608 /* make sure that we can refill faster than drain */
2609 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2610 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2612 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2614 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2616 while (mh != NULL) {
2619 m->m_nextpkt = NULL;
2620 #ifndef __NO_STRICT_ALIGNMENT
2621 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2624 rx_bytes += m->m_pkthdr.len;
2626 #if defined(INET6) || defined(INET)
2628 if (!lro_possible) {
2629 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2630 if (lro_possible && mf != NULL) {
2631 ifp->if_input(ifp, mf);
2632 DBG_COUNTER_INC(rx_if_input);
2636 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2637 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2638 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2644 ifp->if_input(ifp, m);
2645 DBG_COUNTER_INC(rx_if_input);
2656 ifp->if_input(ifp, mf);
2657 DBG_COUNTER_INC(rx_if_input);
2660 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2661 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2664 * Flush any outstanding LRO work
2666 #if defined(INET6) || defined(INET)
2667 tcp_lro_flush_all(&rxq->ifr_lc);
2671 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2674 ctx->ifc_flags |= IFC_DO_RESET;
2675 iflib_admin_intr_deferred(ctx);
2680 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2681 static inline qidx_t
2682 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2684 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2685 qidx_t minthresh = txq->ift_size / 8;
2686 if (in_use > 4*minthresh)
2687 return (notify_count);
2688 if (in_use > 2*minthresh)
2689 return (notify_count >> 1);
2690 if (in_use > minthresh)
2691 return (notify_count >> 3);
2695 static inline qidx_t
2696 txq_max_rs_deferred(iflib_txq_t txq)
2698 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2699 qidx_t minthresh = txq->ift_size / 8;
2700 if (txq->ift_in_use > 4*minthresh)
2701 return (notify_count);
2702 if (txq->ift_in_use > 2*minthresh)
2703 return (notify_count >> 1);
2704 if (txq->ift_in_use > minthresh)
2705 return (notify_count >> 2);
2709 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2710 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2712 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2713 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2714 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2716 /* forward compatibility for cxgb */
2717 #define FIRST_QSET(ctx) 0
2718 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2719 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2720 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2721 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2723 /* XXX we should be setting this to something other than zero */
2724 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2725 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max)
2728 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2734 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2735 if (ring || txq->ift_db_pending >= max) {
2736 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2737 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2738 txq->ift_db_pending = txq->ift_npending = 0;
2746 print_pkt(if_pkt_info_t pi)
2748 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2749 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2750 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2751 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2752 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2753 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2757 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2758 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2761 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2763 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2764 struct ether_vlan_header *eh;
2768 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2769 M_WRITABLE(m) == 0) {
2770 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2779 * Determine where frame payload starts.
2780 * Jump over vlan headers if already present,
2781 * helpful for QinQ too.
2783 if (__predict_false(m->m_len < sizeof(*eh))) {
2785 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2788 eh = mtod(m, struct ether_vlan_header *);
2789 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2790 pi->ipi_etype = ntohs(eh->evl_proto);
2791 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2793 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2794 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2797 switch (pi->ipi_etype) {
2801 struct ip *ip = NULL;
2802 struct tcphdr *th = NULL;
2805 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2806 if (__predict_false(m->m_len < minthlen)) {
2808 * if this code bloat is causing too much of a hit
2809 * move it to a separate function and mark it noinline
2811 if (m->m_len == pi->ipi_ehdrlen) {
2814 if (n->m_len >= sizeof(*ip)) {
2815 ip = (struct ip *)n->m_data;
2816 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2817 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2820 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2822 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2826 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2828 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2829 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2830 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2833 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2834 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2835 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2837 pi->ipi_ip_hlen = ip->ip_hl << 2;
2838 pi->ipi_ipproto = ip->ip_p;
2839 pi->ipi_flags |= IPI_TX_IPV4;
2841 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2845 if (pi->ipi_ipproto == IPPROTO_TCP) {
2846 if (__predict_false(th == NULL)) {
2848 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2850 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2852 pi->ipi_tcp_hflags = th->th_flags;
2853 pi->ipi_tcp_hlen = th->th_off << 2;
2854 pi->ipi_tcp_seq = th->th_seq;
2856 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2858 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2859 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2860 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2861 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
2863 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
2870 case ETHERTYPE_IPV6:
2872 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
2874 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
2876 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
2877 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
2880 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
2882 /* XXX-BZ this will go badly in case of ext hdrs. */
2883 pi->ipi_ipproto = ip6->ip6_nxt;
2884 pi->ipi_flags |= IPI_TX_IPV6;
2887 if (pi->ipi_ipproto == IPPROTO_TCP) {
2888 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
2889 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
2892 pi->ipi_tcp_hflags = th->th_flags;
2893 pi->ipi_tcp_hlen = th->th_off << 2;
2896 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
2899 * The corresponding flag is set by the stack in the IPv4
2900 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
2901 * So, set it here because the rest of the flow requires it.
2903 pi->ipi_csum_flags |= CSUM_TCP_IPV6;
2904 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
2905 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2911 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
2912 pi->ipi_ip_hlen = 0;
2920 static __noinline struct mbuf *
2921 collapse_pkthdr(struct mbuf *m0)
2923 struct mbuf *m, *m_next, *tmp;
2927 while (m_next != NULL && m_next->m_len == 0) {
2931 m_next = m_next->m_next;
2935 if ((m_next->m_flags & M_EXT) == 0) {
2936 m = m_defrag(m, M_NOWAIT);
2938 tmp = m_next->m_next;
2939 memcpy(m_next, m, MPKTHSIZE);
2947 * If dodgy hardware rejects the scatter gather chain we've handed it
2948 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
2951 static __noinline struct mbuf *
2952 iflib_remove_mbuf(iflib_txq_t txq)
2955 struct mbuf *m, *mh, **ifsd_m;
2957 pidx = txq->ift_pidx;
2958 ifsd_m = txq->ift_sds.ifsd_m;
2959 ntxd = txq->ift_size;
2960 mh = m = ifsd_m[pidx];
2961 ifsd_m[pidx] = NULL;
2963 txq->ift_dequeued++;
2968 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
2970 txq->ift_dequeued++;
2979 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
2980 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
2981 int max_segs, int flags)
2984 if_shared_ctx_t sctx;
2985 if_softc_ctx_t scctx;
2986 int i, next, pidx, err, ntxd, count;
2987 struct mbuf *m, *tmp, **ifsd_m;
2992 * Please don't ever do this
2994 if (__predict_false(m->m_len == 0))
2995 *m0 = m = collapse_pkthdr(m);
2998 sctx = ctx->ifc_sctx;
2999 scctx = &ctx->ifc_softc_ctx;
3000 ifsd_m = txq->ift_sds.ifsd_m;
3001 ntxd = txq->ift_size;
3002 pidx = txq->ift_pidx;
3004 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3006 err = bus_dmamap_load_mbuf_sg(tag, map,
3007 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3010 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3014 if (__predict_false(m->m_len <= 0)) {
3023 } while (m != NULL);
3024 if (count > *nsegs) {
3026 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3032 next = (pidx + count) & (ntxd-1);
3033 MPASS(ifsd_m[next] == NULL);
3038 } while (m != NULL);
3040 int buflen, sgsize, maxsegsz, max_sgsize;
3046 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3047 maxsegsz = scctx->isc_tx_tso_segsize_max;
3049 maxsegsz = sctx->isc_tx_maxsegsize;
3052 if (__predict_false(m->m_len <= 0)) {
3060 vaddr = (vm_offset_t)m->m_data;
3062 * see if we can't be smarter about physically
3063 * contiguous mappings
3065 next = (pidx + count) & (ntxd-1);
3066 MPASS(ifsd_m[next] == NULL);
3068 txq->ift_enqueued++;
3071 while (buflen > 0) {
3074 max_sgsize = MIN(buflen, maxsegsz);
3075 curaddr = pmap_kextract(vaddr);
3076 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3077 sgsize = MIN(sgsize, max_sgsize);
3078 segs[i].ds_addr = curaddr;
3079 segs[i].ds_len = sgsize;
3087 } while (m != NULL);
3092 *m0 = iflib_remove_mbuf(txq);
3096 static inline caddr_t
3097 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3101 caddr_t start, end, cur, next;
3103 ntxd = txq->ift_size;
3104 size = txq->ift_txd_size[qid];
3105 start = txq->ift_ifdi[qid].idi_vaddr;
3107 if (__predict_false(size == 0))
3109 cur = start + size*cidx;
3110 end = start + size*ntxd;
3111 next = CACHE_PTR_NEXT(cur);
3112 return (next < end ? next : start);
3116 * Pad an mbuf to ensure a minimum ethernet frame size.
3117 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3119 static __noinline int
3120 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3123 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3124 * and ARP message is the smallest common payload I can think of
3126 static char pad[18]; /* just zeros */
3128 struct mbuf *new_head;
3130 if (!M_WRITABLE(*m_head)) {
3131 new_head = m_dup(*m_head, M_NOWAIT);
3132 if (new_head == NULL) {
3134 device_printf(dev, "cannot pad short frame, m_dup() failed");
3135 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3142 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3143 n > 0; n -= sizeof(pad))
3144 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3149 device_printf(dev, "cannot pad short frame\n");
3150 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3158 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3161 if_shared_ctx_t sctx;
3162 if_softc_ctx_t scctx;
3163 bus_dma_segment_t *segs;
3164 struct mbuf *m_head;
3167 struct if_pkt_info pi;
3169 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3170 bus_dma_tag_t desc_tag;
3172 segs = txq->ift_segs;
3174 sctx = ctx->ifc_sctx;
3175 scctx = &ctx->ifc_softc_ctx;
3176 segs = txq->ift_segs;
3177 ntxd = txq->ift_size;
3182 * If we're doing TSO the next descriptor to clean may be quite far ahead
3184 cidx = txq->ift_cidx;
3185 pidx = txq->ift_pidx;
3186 if (ctx->ifc_flags & IFC_PREFETCH) {
3187 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3188 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3189 next_txd = calc_next_txd(txq, cidx, 0);
3193 /* prefetch the next cache line of mbuf pointers and flags */
3194 prefetch(&txq->ift_sds.ifsd_m[next]);
3195 if (txq->ift_sds.ifsd_map != NULL) {
3196 prefetch(&txq->ift_sds.ifsd_map[next]);
3197 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3198 prefetch(&txq->ift_sds.ifsd_flags[next]);
3200 } else if (txq->ift_sds.ifsd_map != NULL)
3201 map = txq->ift_sds.ifsd_map[pidx];
3203 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3204 desc_tag = txq->ift_tso_desc_tag;
3205 max_segs = scctx->isc_tx_tso_segments_max;
3207 desc_tag = txq->ift_desc_tag;
3208 max_segs = scctx->isc_tx_nsegments;
3210 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3211 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3212 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3219 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3221 pi.ipi_qsidx = txq->ift_id;
3222 pi.ipi_len = m_head->m_pkthdr.len;
3223 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3224 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3226 /* deliberate bitwise OR to make one condition */
3227 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3228 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0))
3234 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3236 if (__predict_false(err)) {
3239 /* try collapse once and defrag once */
3241 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3243 m_head = m_defrag(*m_headp, M_NOWAIT);
3245 if (__predict_false(m_head == NULL))
3247 txq->ift_mbuf_defrag++;
3252 txq->ift_no_tx_dma_setup++;
3255 txq->ift_no_tx_dma_setup++;
3257 DBG_COUNTER_INC(tx_frees);
3261 txq->ift_map_failed++;
3262 DBG_COUNTER_INC(encap_load_mbuf_fail);
3267 * XXX assumes a 1 to 1 relationship between segments and
3268 * descriptors - this does not hold true on all drivers, e.g.
3271 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3272 txq->ift_no_desc_avail++;
3274 bus_dmamap_unload(desc_tag, map);
3275 DBG_COUNTER_INC(encap_txq_avail_fail);
3276 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3277 GROUPTASK_ENQUEUE(&txq->ift_task);
3281 * On Intel cards we can greatly reduce the number of TX interrupts
3282 * we see by only setting report status on every Nth descriptor.
3283 * However, this also means that the driver will need to keep track
3284 * of the descriptors that RS was set on to check them for the DD bit.
3286 txq->ift_rs_pending += nsegs + 1;
3287 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3288 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) {
3289 pi.ipi_flags |= IPI_TX_INTR;
3290 txq->ift_rs_pending = 0;
3294 pi.ipi_nsegs = nsegs;
3296 MPASS(pidx >= 0 && pidx < txq->ift_size);
3301 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3302 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3304 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3305 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3306 DBG_COUNTER_INC(tx_encap);
3307 MPASS(pi.ipi_new_pidx < txq->ift_size);
3309 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3310 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3311 ndesc += txq->ift_size;
3315 * drivers can need as many as
3318 MPASS(ndesc <= pi.ipi_nsegs + 2);
3319 MPASS(pi.ipi_new_pidx != pidx);
3321 txq->ift_in_use += ndesc;
3324 * We update the last software descriptor again here because there may
3325 * be a sentinel and/or there may be more mbufs than segments
3327 txq->ift_pidx = pi.ipi_new_pidx;
3328 txq->ift_npending += pi.ipi_ndescs;
3329 } else if (__predict_false(err == EFBIG && remap < 2)) {
3330 *m_headp = m_head = iflib_remove_mbuf(txq);
3332 txq->ift_txd_encap_efbig++;
3335 DBG_COUNTER_INC(encap_txd_encap_fail);
3339 txq->ift_mbuf_defrag_failed++;
3340 txq->ift_map_failed++;
3342 DBG_COUNTER_INC(tx_frees);
3348 iflib_tx_desc_free(iflib_txq_t txq, int n)
3351 uint32_t qsize, cidx, mask, gen;
3352 struct mbuf *m, **ifsd_m;
3353 uint8_t *ifsd_flags;
3354 bus_dmamap_t *ifsd_map;
3357 cidx = txq->ift_cidx;
3359 qsize = txq->ift_size;
3361 hasmap = txq->ift_sds.ifsd_map != NULL;
3362 ifsd_flags = txq->ift_sds.ifsd_flags;
3363 ifsd_m = txq->ift_sds.ifsd_m;
3364 ifsd_map = txq->ift_sds.ifsd_map;
3365 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3369 prefetch(ifsd_m[(cidx + 3) & mask]);
3370 prefetch(ifsd_m[(cidx + 4) & mask]);
3372 if (ifsd_m[cidx] != NULL) {
3373 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3374 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3375 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3377 * does it matter if it's not the TSO tag? If so we'll
3378 * have to add the type to flags
3380 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3381 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3383 if ((m = ifsd_m[cidx]) != NULL) {
3384 /* XXX we don't support any drivers that batch packets yet */
3385 MPASS(m->m_nextpkt == NULL);
3386 /* if the number of clusters exceeds the number of segments
3387 * there won't be space on the ring to save a pointer to each
3388 * cluster so we simply free the list here
3390 if (m->m_flags & M_TOOBIG) {
3395 ifsd_m[cidx] = NULL;
3397 txq->ift_dequeued++;
3399 DBG_COUNTER_INC(tx_frees);
3402 if (__predict_false(++cidx == qsize)) {
3407 txq->ift_cidx = cidx;
3412 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3415 if_ctx_t ctx = txq->ift_ctx;
3417 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3418 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3421 * Need a rate-limiting check so that this isn't called every time
3423 iflib_tx_credits_update(ctx, txq);
3424 reclaim = DESC_RECLAIMABLE(txq);
3426 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3428 if (iflib_verbose_debug) {
3429 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3430 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3437 iflib_tx_desc_free(txq, reclaim);
3438 txq->ift_cleaned += reclaim;
3439 txq->ift_in_use -= reclaim;
3444 static struct mbuf **
3445 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3448 struct mbuf **items;
3451 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3452 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3454 prefetch(items[(cidx + offset) & (size-1)]);
3455 if (remaining > 1) {
3456 prefetch2cachelines(&items[next]);
3457 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3458 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3459 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3461 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3465 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3468 ifmp_ring_check_drainage(txq->ift_br, budget);
3472 iflib_txq_can_drain(struct ifmp_ring *r)
3474 iflib_txq_t txq = r->cookie;
3475 if_ctx_t ctx = txq->ift_ctx;
3477 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3478 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3482 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3484 iflib_txq_t txq = r->cookie;
3485 if_ctx_t ctx = txq->ift_ctx;
3486 struct ifnet *ifp = ctx->ifc_ifp;
3487 struct mbuf **mp, *m;
3488 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3489 int reclaimed, err, in_use_prev, desc_used;
3490 bool do_prefetch, ring, rang;
3492 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3493 !LINK_ACTIVE(ctx))) {
3494 DBG_COUNTER_INC(txq_drain_notready);
3497 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3498 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3499 avail = IDXDIFF(pidx, cidx, r->size);
3500 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3501 DBG_COUNTER_INC(txq_drain_flushing);
3502 for (i = 0; i < avail; i++) {
3503 m_free(r->items[(cidx + i) & (r->size-1)]);
3504 r->items[(cidx + i) & (r->size-1)] = NULL;
3509 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3510 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3512 callout_stop(&txq->ift_timer);
3513 CALLOUT_UNLOCK(txq);
3514 DBG_COUNTER_INC(txq_drain_oactive);
3518 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3519 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3520 count = MIN(avail, TX_BATCH_SIZE);
3522 if (iflib_verbose_debug)
3523 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3524 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3526 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3527 avail = TXQ_AVAIL(txq);
3528 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3529 int pidx_prev, rem = do_prefetch ? count - i : 0;
3531 mp = _ring_peek_one(r, cidx, i, rem);
3532 MPASS(mp != NULL && *mp != NULL);
3533 if (__predict_false(*mp == (struct mbuf *)txq)) {
3538 in_use_prev = txq->ift_in_use;
3539 pidx_prev = txq->ift_pidx;
3540 err = iflib_encap(txq, mp);
3541 if (__predict_false(err)) {
3542 DBG_COUNTER_INC(txq_drain_encapfail);
3543 /* no room - bail out */
3547 DBG_COUNTER_INC(txq_drain_encapfail);
3548 /* we can't send this packet - skip it */
3554 DBG_COUNTER_INC(tx_sent);
3555 bytes_sent += m->m_pkthdr.len;
3556 mcast_sent += !!(m->m_flags & M_MCAST);
3557 avail = TXQ_AVAIL(txq);
3559 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3560 desc_used += (txq->ift_in_use - in_use_prev);
3561 ETHER_BPF_MTAP(ifp, m);
3562 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3564 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3567 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3568 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3569 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3570 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3571 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3573 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3575 if (iflib_verbose_debug)
3576 printf("consumed=%d\n", consumed);
3582 iflib_txq_drain_always(struct ifmp_ring *r)
3588 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3596 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3598 callout_stop(&txq->ift_timer);
3599 CALLOUT_UNLOCK(txq);
3601 avail = IDXDIFF(pidx, cidx, r->size);
3602 for (i = 0; i < avail; i++) {
3603 mp = _ring_peek_one(r, cidx, i, avail - i);
3604 if (__predict_false(*mp == (struct mbuf *)txq))
3608 MPASS(ifmp_ring_is_stalled(r) == 0);
3613 iflib_ifmp_purge(iflib_txq_t txq)
3615 struct ifmp_ring *r;
3618 r->drain = iflib_txq_drain_free;
3619 r->can_drain = iflib_txq_drain_always;
3621 ifmp_ring_check_drainage(r, r->size);
3623 r->drain = iflib_txq_drain;
3624 r->can_drain = iflib_txq_can_drain;
3628 _task_fn_tx(void *context)
3630 iflib_txq_t txq = context;
3631 if_ctx_t ctx = txq->ift_ctx;
3632 struct ifnet *ifp = ctx->ifc_ifp;
3635 #ifdef IFLIB_DIAGNOSTICS
3636 txq->ift_cpu_exec_count[curcpu]++;
3638 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3640 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3641 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3642 netmap_tx_irq(ifp, txq->ift_id);
3643 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3646 if (txq->ift_db_pending)
3647 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE);
3648 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3649 if (ctx->ifc_flags & IFC_LEGACY)
3650 IFDI_INTR_ENABLE(ctx);
3652 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3653 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3658 _task_fn_rx(void *context)
3660 iflib_rxq_t rxq = context;
3661 if_ctx_t ctx = rxq->ifr_ctx;
3666 #ifdef IFLIB_DIAGNOSTICS
3667 rxq->ifr_cpu_exec_count[curcpu]++;
3669 DBG_COUNTER_INC(task_fn_rxs);
3670 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3674 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3676 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3681 budget = ctx->ifc_sysctl_rx_budget;
3683 budget = 16; /* XXX */
3684 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3685 if (ctx->ifc_flags & IFC_LEGACY)
3686 IFDI_INTR_ENABLE(ctx);
3688 DBG_COUNTER_INC(rx_intr_enables);
3689 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3690 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3693 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3696 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3700 _task_fn_admin(void *context)
3702 if_ctx_t ctx = context;
3703 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3707 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) {
3708 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3714 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3716 callout_stop(&txq->ift_timer);
3717 CALLOUT_UNLOCK(txq);
3719 IFDI_UPDATE_ADMIN_STATUS(ctx);
3720 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3721 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu);
3722 IFDI_LINK_INTR_ENABLE(ctx);
3723 if (ctx->ifc_flags & IFC_DO_RESET) {
3724 ctx->ifc_flags &= ~IFC_DO_RESET;
3725 iflib_if_init_locked(ctx);
3729 if (LINK_ACTIVE(ctx) == 0)
3731 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3732 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3737 _task_fn_iov(void *context)
3739 if_ctx_t ctx = context;
3741 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3745 IFDI_VFLR_HANDLE(ctx);
3750 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3753 if_int_delay_info_t info;
3756 info = (if_int_delay_info_t)arg1;
3757 ctx = info->iidi_ctx;
3758 info->iidi_req = req;
3759 info->iidi_oidp = oidp;
3761 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3766 /*********************************************************************
3770 **********************************************************************/
3773 iflib_if_init_locked(if_ctx_t ctx)
3776 iflib_init_locked(ctx);
3781 iflib_if_init(void *arg)
3786 iflib_if_init_locked(ctx);
3791 iflib_if_transmit(if_t ifp, struct mbuf *m)
3793 if_ctx_t ctx = if_getsoftc(ifp);
3798 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3799 DBG_COUNTER_INC(tx_frees);
3804 MPASS(m->m_nextpkt == NULL);
3806 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
3807 qidx = QIDX(ctx, m);
3809 * XXX calculate buf_ring based on flowid (divvy up bits?)
3811 txq = &ctx->ifc_txqs[qidx];
3813 #ifdef DRIVER_BACKPRESSURE
3814 if (txq->ift_closed) {
3816 next = m->m_nextpkt;
3817 m->m_nextpkt = NULL;
3830 next = next->m_nextpkt;
3831 } while (next != NULL);
3833 if (count > nitems(marr))
3834 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3835 /* XXX check nextpkt */
3837 /* XXX simplify for now */
3838 DBG_COUNTER_INC(tx_frees);
3841 for (next = m, i = 0; next != NULL; i++) {
3843 next = next->m_nextpkt;
3844 mp[i]->m_nextpkt = NULL;
3847 DBG_COUNTER_INC(tx_seen);
3848 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE);
3850 GROUPTASK_ENQUEUE(&txq->ift_task);
3852 /* support forthcoming later */
3853 #ifdef DRIVER_BACKPRESSURE
3854 txq->ift_closed = TRUE;
3856 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3864 iflib_if_qflush(if_t ifp)
3866 if_ctx_t ctx = if_getsoftc(ifp);
3867 iflib_txq_t txq = ctx->ifc_txqs;
3871 ctx->ifc_flags |= IFC_QFLUSH;
3873 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3874 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3875 iflib_txq_check_drain(txq, 0);
3877 ctx->ifc_flags &= ~IFC_QFLUSH;
3884 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
3885 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
3886 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO)
3889 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
3891 if_ctx_t ctx = if_getsoftc(ifp);
3892 struct ifreq *ifr = (struct ifreq *)data;
3893 #if defined(INET) || defined(INET6)
3894 struct ifaddr *ifa = (struct ifaddr *)data;
3896 bool avoid_reset = FALSE;
3897 int err = 0, reinit = 0, bits;
3902 if (ifa->ifa_addr->sa_family == AF_INET)
3906 if (ifa->ifa_addr->sa_family == AF_INET6)
3910 ** Calling init results in link renegotiation,
3911 ** so we avoid doing it when possible.
3914 if_setflagbits(ifp, IFF_UP,0);
3915 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING))
3918 if (!(if_getflags(ifp) & IFF_NOARP))
3919 arp_ifinit(ifp, ifa);
3922 err = ether_ioctl(ifp, command, data);
3926 if (ifr->ifr_mtu == if_getmtu(ifp)) {
3930 bits = if_getdrvflags(ifp);
3931 /* stop the driver and free any clusters before proceeding */
3934 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
3935 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
3936 ctx->ifc_flags |= IFC_MULTISEG;
3938 ctx->ifc_flags &= ~IFC_MULTISEG;
3939 err = if_setmtu(ifp, ifr->ifr_mtu);
3941 iflib_init_locked(ctx);
3942 if_setdrvflags(ifp, bits);
3947 if (if_getflags(ifp) & IFF_UP) {
3948 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3949 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
3950 (IFF_PROMISC | IFF_ALLMULTI)) {
3951 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
3955 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3958 ctx->ifc_if_flags = if_getflags(ifp);
3963 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3965 IFDI_INTR_DISABLE(ctx);
3966 IFDI_MULTI_SET(ctx);
3967 IFDI_INTR_ENABLE(ctx);
3973 IFDI_MEDIA_SET(ctx);
3978 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
3982 struct ifi2creq i2c;
3984 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
3987 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
3991 if (i2c.len > sizeof(i2c.data)) {
3996 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
3997 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
4004 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
4007 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4009 setmask |= (mask & IFCAP_FLAGS);
4011 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6))
4012 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4013 if ((mask & IFCAP_WOL) &&
4014 (if_getcapabilities(ifp) & IFCAP_WOL) != 0)
4015 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC));
4018 * want to ensure that traffic has stopped before we change any of the flags
4022 bits = if_getdrvflags(ifp);
4023 if (bits & IFF_DRV_RUNNING)
4025 if_togglecapenable(ifp, setmask);
4026 if (bits & IFF_DRV_RUNNING)
4027 iflib_init_locked(ctx);
4028 if_setdrvflags(ifp, bits);
4033 case SIOCGPRIVATE_0:
4037 err = IFDI_PRIV_IOCTL(ctx, command, data);
4041 err = ether_ioctl(ifp, command, data);
4050 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4052 if_ctx_t ctx = if_getsoftc(ifp);
4054 return (IFDI_GET_COUNTER(ctx, cnt));
4057 /*********************************************************************
4059 * OTHER FUNCTIONS EXPORTED TO THE STACK
4061 **********************************************************************/
4064 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4066 if_ctx_t ctx = if_getsoftc(ifp);
4068 if ((void *)ctx != arg)
4071 if ((vtag == 0) || (vtag > 4095))
4075 IFDI_VLAN_REGISTER(ctx, vtag);
4076 /* Re-init to load the changes */
4077 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4078 iflib_if_init_locked(ctx);
4083 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4085 if_ctx_t ctx = if_getsoftc(ifp);
4087 if ((void *)ctx != arg)
4090 if ((vtag == 0) || (vtag > 4095))
4094 IFDI_VLAN_UNREGISTER(ctx, vtag);
4095 /* Re-init to load the changes */
4096 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4097 iflib_if_init_locked(ctx);
4102 iflib_led_func(void *arg, int onoff)
4107 IFDI_LED_FUNC(ctx, onoff);
4111 /*********************************************************************
4113 * BUS FUNCTION DEFINITIONS
4115 **********************************************************************/
4118 iflib_device_probe(device_t dev)
4120 pci_vendor_info_t *ent;
4122 uint16_t pci_vendor_id, pci_device_id;
4123 uint16_t pci_subvendor_id, pci_subdevice_id;
4124 uint16_t pci_rev_id;
4125 if_shared_ctx_t sctx;
4127 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4130 pci_vendor_id = pci_get_vendor(dev);
4131 pci_device_id = pci_get_device(dev);
4132 pci_subvendor_id = pci_get_subvendor(dev);
4133 pci_subdevice_id = pci_get_subdevice(dev);
4134 pci_rev_id = pci_get_revid(dev);
4135 if (sctx->isc_parse_devinfo != NULL)
4136 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4138 ent = sctx->isc_vendor_info;
4139 while (ent->pvi_vendor_id != 0) {
4140 if (pci_vendor_id != ent->pvi_vendor_id) {
4144 if ((pci_device_id == ent->pvi_device_id) &&
4145 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4146 (ent->pvi_subvendor_id == 0)) &&
4147 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4148 (ent->pvi_subdevice_id == 0)) &&
4149 ((pci_rev_id == ent->pvi_rev_id) ||
4150 (ent->pvi_rev_id == 0))) {
4152 device_set_desc_copy(dev, ent->pvi_name);
4153 /* this needs to be changed to zero if the bus probing code
4154 * ever stops re-probing on best match because the sctx
4155 * may have its values over written by register calls
4156 * in subsequent probes
4158 return (BUS_PROBE_DEFAULT);
4166 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4168 int err, rid, msix, msix_bar;
4171 if_softc_ctx_t scctx;
4177 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4180 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4181 device_set_softc(dev, ctx);
4182 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4185 ctx->ifc_sctx = sctx;
4187 ctx->ifc_softc = sc;
4189 if ((err = iflib_register(ctx)) != 0) {
4190 device_printf(dev, "iflib_register failed %d\n", err);
4193 iflib_add_device_sysctl_pre(ctx);
4195 scctx = &ctx->ifc_softc_ctx;
4199 * XXX sanity check that ntxd & nrxd are a power of 2
4201 if (ctx->ifc_sysctl_ntxqs != 0)
4202 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4203 if (ctx->ifc_sysctl_nrxqs != 0)
4204 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4206 for (i = 0; i < sctx->isc_ntxqs; i++) {
4207 if (ctx->ifc_sysctl_ntxds[i] != 0)
4208 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4210 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4213 for (i = 0; i < sctx->isc_nrxqs; i++) {
4214 if (ctx->ifc_sysctl_nrxds[i] != 0)
4215 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4217 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4220 for (i = 0; i < sctx->isc_nrxqs; i++) {
4221 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4222 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4223 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4224 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4226 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4227 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4228 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4229 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4233 for (i = 0; i < sctx->isc_ntxqs; i++) {
4234 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4235 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4236 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4237 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4239 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4240 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4241 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4242 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4246 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4247 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4250 _iflib_pre_assert(scctx);
4251 ctx->ifc_txrx = *scctx->isc_txrx;
4254 MPASS(scctx->isc_capenable);
4255 if (scctx->isc_capenable & IFCAP_TXCSUM)
4256 MPASS(scctx->isc_tx_csum_flags);
4259 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4260 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4262 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4263 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4264 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4265 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4268 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4269 ctx->ifc_flags |= IFC_DMAR;
4270 #elif !(defined(__i386__) || defined(__amd64__))
4271 /* set unconditionally for !x86 */
4272 ctx->ifc_flags |= IFC_DMAR;
4275 msix_bar = scctx->isc_msix_bar;
4276 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4277 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4279 /* XXX change for per-queue sizes */
4280 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4281 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4282 for (i = 0; i < sctx->isc_nrxqs; i++) {
4283 if (!powerof2(scctx->isc_nrxd[i])) {
4284 /* round down instead? */
4285 device_printf(dev, "# rx descriptors must be a power of 2\n");
4290 for (i = 0; i < sctx->isc_ntxqs; i++) {
4291 if (!powerof2(scctx->isc_ntxd[i])) {
4293 "# tx descriptors must be a power of 2");
4299 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4300 MAX_SINGLE_PACKET_FRACTION)
4301 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4302 MAX_SINGLE_PACKET_FRACTION);
4303 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4304 MAX_SINGLE_PACKET_FRACTION)
4305 scctx->isc_tx_tso_segments_max = max(1,
4306 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4309 * Protect the stack against modern hardware
4311 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX)
4312 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX;
4314 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4315 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max;
4316 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max;
4317 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max;
4318 if (scctx->isc_rss_table_size == 0)
4319 scctx->isc_rss_table_size = 64;
4320 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4322 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4323 /* XXX format name */
4324 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4326 /* Set up cpu set. If it fails, use the set of all CPUs. */
4327 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4328 device_printf(dev, "Unable to fetch CPU list\n");
4329 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4331 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4334 ** Now setup MSI or MSI/X, should
4335 ** return us the number of supported
4336 ** vectors. (Will be 1 for MSI)
4338 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4339 msix = scctx->isc_vectors;
4340 } else if (scctx->isc_msix_bar != 0)
4342 * The simple fact that isc_msix_bar is not 0 does not mean we
4343 * we have a good value there that is known to work.
4345 msix = iflib_msix_init(ctx);
4347 scctx->isc_vectors = 1;
4348 scctx->isc_ntxqsets = 1;
4349 scctx->isc_nrxqsets = 1;
4350 scctx->isc_intr = IFLIB_INTR_LEGACY;
4353 /* Get memory for the station queues */
4354 if ((err = iflib_queues_alloc(ctx))) {
4355 device_printf(dev, "Unable to allocate queue memory\n");
4359 if ((err = iflib_qset_structures_setup(ctx))) {
4360 device_printf(dev, "qset structure setup failed %d\n", err);
4365 * Group taskqueues aren't properly set up until SMP is started,
4366 * so we disable interrupts until we can handle them post
4369 * XXX: disabling interrupts doesn't actually work, at least for
4370 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4371 * we do null handling and depend on this not causing too large an
4374 IFDI_INTR_DISABLE(ctx);
4375 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4376 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4377 goto fail_intr_free;
4381 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4385 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4386 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4387 goto fail_intr_free;
4390 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4391 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4392 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4395 if ((err = iflib_netmap_attach(ctx))) {
4396 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4401 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4402 iflib_add_device_sysctl_post(ctx);
4403 ctx->ifc_flags |= IFC_INIT_DONE;
4406 ether_ifdetach(ctx->ifc_ifp);
4408 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI)
4409 pci_release_msi(ctx->ifc_dev);
4411 /* XXX free queues */
4418 iflib_device_attach(device_t dev)
4421 if_shared_ctx_t sctx;
4423 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4426 pci_enable_busmaster(dev);
4428 return (iflib_device_register(dev, NULL, sctx, &ctx));
4432 iflib_device_deregister(if_ctx_t ctx)
4434 if_t ifp = ctx->ifc_ifp;
4437 device_t dev = ctx->ifc_dev;
4439 struct taskqgroup *tqg;
4442 /* Make sure VLANS are not using driver */
4443 if (if_vlantrunkinuse(ifp)) {
4444 device_printf(dev,"Vlan in use, detach first\n");
4449 ctx->ifc_in_detach = 1;
4453 /* Unregister VLAN events */
4454 if (ctx->ifc_vlan_attach_event != NULL)
4455 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4456 if (ctx->ifc_vlan_detach_event != NULL)
4457 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4459 iflib_netmap_detach(ifp);
4460 ether_ifdetach(ifp);
4461 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4462 CTX_LOCK_DESTROY(ctx);
4463 if (ctx->ifc_led_dev != NULL)
4464 led_destroy(ctx->ifc_led_dev);
4465 /* XXX drain any dependent tasks */
4466 tqg = qgroup_if_io_tqg;
4467 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4468 callout_drain(&txq->ift_timer);
4469 if (txq->ift_task.gt_uniq != NULL)
4470 taskqgroup_detach(tqg, &txq->ift_task);
4472 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4473 if (rxq->ifr_task.gt_uniq != NULL)
4474 taskqgroup_detach(tqg, &rxq->ifr_task);
4476 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4477 free(fl->ifl_rx_bitmap, M_IFLIB);
4480 tqg = qgroup_if_config_tqg;
4481 if (ctx->ifc_admin_task.gt_uniq != NULL)
4482 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4483 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4484 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4487 device_set_softc(ctx->ifc_dev, NULL);
4488 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4489 pci_release_msi(dev);
4491 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4492 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4494 if (ctx->ifc_msix_mem != NULL) {
4495 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4496 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
4497 ctx->ifc_msix_mem = NULL;
4500 bus_generic_detach(dev);
4503 iflib_tx_structures_free(ctx);
4504 iflib_rx_structures_free(ctx);
4505 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4506 free(ctx->ifc_softc, M_IFLIB);
4513 iflib_device_detach(device_t dev)
4515 if_ctx_t ctx = device_get_softc(dev);
4517 return (iflib_device_deregister(ctx));
4521 iflib_device_suspend(device_t dev)
4523 if_ctx_t ctx = device_get_softc(dev);
4529 return bus_generic_suspend(dev);
4532 iflib_device_shutdown(device_t dev)
4534 if_ctx_t ctx = device_get_softc(dev);
4540 return bus_generic_suspend(dev);
4545 iflib_device_resume(device_t dev)
4547 if_ctx_t ctx = device_get_softc(dev);
4548 iflib_txq_t txq = ctx->ifc_txqs;
4552 iflib_init_locked(ctx);
4554 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
4555 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4557 return (bus_generic_resume(dev));
4561 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
4564 if_ctx_t ctx = device_get_softc(dev);
4567 error = IFDI_IOV_INIT(ctx, num_vfs, params);
4574 iflib_device_iov_uninit(device_t dev)
4576 if_ctx_t ctx = device_get_softc(dev);
4579 IFDI_IOV_UNINIT(ctx);
4584 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
4587 if_ctx_t ctx = device_get_softc(dev);
4590 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
4596 /*********************************************************************
4598 * MODULE FUNCTION DEFINITIONS
4600 **********************************************************************/
4603 * - Start a fast taskqueue thread for each core
4604 * - Start a taskqueue for control operations
4607 iflib_module_init(void)
4613 iflib_module_event_handler(module_t mod, int what, void *arg)
4619 if ((err = iflib_module_init()) != 0)
4625 return (EOPNOTSUPP);
4631 /*********************************************************************
4633 * PUBLIC FUNCTION DEFINITIONS
4634 * ordered as in iflib.h
4636 **********************************************************************/
4640 _iflib_assert(if_shared_ctx_t sctx)
4642 MPASS(sctx->isc_tx_maxsize);
4643 MPASS(sctx->isc_tx_maxsegsize);
4645 MPASS(sctx->isc_rx_maxsize);
4646 MPASS(sctx->isc_rx_nsegments);
4647 MPASS(sctx->isc_rx_maxsegsize);
4649 MPASS(sctx->isc_nrxd_min[0]);
4650 MPASS(sctx->isc_nrxd_max[0]);
4651 MPASS(sctx->isc_nrxd_default[0]);
4652 MPASS(sctx->isc_ntxd_min[0]);
4653 MPASS(sctx->isc_ntxd_max[0]);
4654 MPASS(sctx->isc_ntxd_default[0]);
4658 _iflib_pre_assert(if_softc_ctx_t scctx)
4661 MPASS(scctx->isc_txrx->ift_txd_encap);
4662 MPASS(scctx->isc_txrx->ift_txd_flush);
4663 MPASS(scctx->isc_txrx->ift_txd_credits_update);
4664 MPASS(scctx->isc_txrx->ift_rxd_available);
4665 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
4666 MPASS(scctx->isc_txrx->ift_rxd_refill);
4667 MPASS(scctx->isc_txrx->ift_rxd_flush);
4671 iflib_register(if_ctx_t ctx)
4673 if_shared_ctx_t sctx = ctx->ifc_sctx;
4674 driver_t *driver = sctx->isc_driver;
4675 device_t dev = ctx->ifc_dev;
4678 _iflib_assert(sctx);
4680 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
4682 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER);
4684 device_printf(dev, "can not allocate ifnet structure\n");
4689 * Initialize our context's device specific methods
4691 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
4692 kobj_class_compile((kobj_class_t) driver);
4695 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4696 if_setsoftc(ifp, ctx);
4697 if_setdev(ifp, dev);
4698 if_setinitfn(ifp, iflib_if_init);
4699 if_setioctlfn(ifp, iflib_if_ioctl);
4700 if_settransmitfn(ifp, iflib_if_transmit);
4701 if_setqflushfn(ifp, iflib_if_qflush);
4702 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4704 ctx->ifc_vlan_attach_event =
4705 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
4706 EVENTHANDLER_PRI_FIRST);
4707 ctx->ifc_vlan_detach_event =
4708 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
4709 EVENTHANDLER_PRI_FIRST);
4711 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
4712 iflib_media_change, iflib_media_status);
4719 iflib_queues_alloc(if_ctx_t ctx)
4721 if_shared_ctx_t sctx = ctx->ifc_sctx;
4722 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4723 device_t dev = ctx->ifc_dev;
4724 int nrxqsets = scctx->isc_nrxqsets;
4725 int ntxqsets = scctx->isc_ntxqsets;
4728 iflib_fl_t fl = NULL;
4729 int i, j, cpu, err, txconf, rxconf;
4730 iflib_dma_info_t ifdip;
4731 uint32_t *rxqsizes = scctx->isc_rxqsizes;
4732 uint32_t *txqsizes = scctx->isc_txqsizes;
4733 uint8_t nrxqs = sctx->isc_nrxqs;
4734 uint8_t ntxqs = sctx->isc_ntxqs;
4735 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
4738 struct ifmp_ring **brscp;
4740 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
4741 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
4747 /* Allocate the TX ring struct memory */
4749 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
4750 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4751 device_printf(dev, "Unable to allocate TX ring memory\n");
4756 /* Now allocate the RX */
4758 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
4759 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
4760 device_printf(dev, "Unable to allocate RX ring memory\n");
4765 ctx->ifc_txqs = txq;
4766 ctx->ifc_rxqs = rxq;
4769 * XXX handle allocation failure
4771 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
4772 /* Set up some basics */
4774 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4775 device_printf(dev, "failed to allocate iflib_dma_info\n");
4779 txq->ift_ifdi = ifdip;
4780 for (j = 0; j < ntxqs; j++, ifdip++) {
4781 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4782 device_printf(dev, "Unable to allocate Descriptor memory\n");
4786 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
4787 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
4791 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
4792 txq->ift_br_offset = 1;
4794 txq->ift_br_offset = 0;
4797 txq->ift_timer.c_cpu = cpu;
4799 if (iflib_txsd_alloc(txq)) {
4800 device_printf(dev, "Critical Failure setting up TX buffers\n");
4805 /* Initialize the TX lock */
4806 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
4807 device_get_nameunit(dev), txq->ift_id);
4808 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
4809 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
4811 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
4812 device_get_nameunit(dev), txq->ift_id);
4814 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
4815 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
4817 /* XXX free any allocated rings */
4818 device_printf(dev, "Unable to allocate buf_ring\n");
4823 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
4824 /* Set up some basics */
4826 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
4827 device_printf(dev, "failed to allocate iflib_dma_info\n");
4832 rxq->ifr_ifdi = ifdip;
4833 /* XXX this needs to be changed if #rx queues != #tx queues */
4834 rxq->ifr_ntxqirq = 1;
4835 rxq->ifr_txqid[0] = i;
4836 for (j = 0; j < nrxqs; j++, ifdip++) {
4837 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
4838 device_printf(dev, "Unable to allocate Descriptor memory\n");
4842 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
4846 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
4847 rxq->ifr_fl_offset = 1;
4849 rxq->ifr_fl_offset = 0;
4851 rxq->ifr_nfl = nfree_lists;
4853 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
4854 device_printf(dev, "Unable to allocate free list memory\n");
4859 for (j = 0; j < nfree_lists; j++) {
4860 fl[j].ifl_rxq = rxq;
4862 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
4863 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
4865 /* Allocate receive buffers for the ring*/
4866 if (iflib_rxsd_alloc(rxq)) {
4868 "Critical Failure setting up receive buffers\n");
4873 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4874 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
4878 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4879 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
4880 for (i = 0; i < ntxqsets; i++) {
4881 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
4883 for (j = 0; j < ntxqs; j++, di++) {
4884 vaddrs[i*ntxqs + j] = di->idi_vaddr;
4885 paddrs[i*ntxqs + j] = di->idi_paddr;
4888 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
4889 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4890 iflib_tx_structures_free(ctx);
4891 free(vaddrs, M_IFLIB);
4892 free(paddrs, M_IFLIB);
4895 free(vaddrs, M_IFLIB);
4896 free(paddrs, M_IFLIB);
4899 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4900 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
4901 for (i = 0; i < nrxqsets; i++) {
4902 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
4904 for (j = 0; j < nrxqs; j++, di++) {
4905 vaddrs[i*nrxqs + j] = di->idi_vaddr;
4906 paddrs[i*nrxqs + j] = di->idi_paddr;
4909 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
4910 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
4911 iflib_tx_structures_free(ctx);
4912 free(vaddrs, M_IFLIB);
4913 free(paddrs, M_IFLIB);
4916 free(vaddrs, M_IFLIB);
4917 free(paddrs, M_IFLIB);
4921 /* XXX handle allocation failure changes */
4924 if (ctx->ifc_rxqs != NULL)
4925 free(ctx->ifc_rxqs, M_IFLIB);
4926 ctx->ifc_rxqs = NULL;
4927 if (ctx->ifc_txqs != NULL)
4928 free(ctx->ifc_txqs, M_IFLIB);
4929 ctx->ifc_txqs = NULL;
4932 free(brscp, M_IFLIB);
4942 iflib_tx_structures_setup(if_ctx_t ctx)
4944 iflib_txq_t txq = ctx->ifc_txqs;
4947 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4948 iflib_txq_setup(txq);
4954 iflib_tx_structures_free(if_ctx_t ctx)
4956 iflib_txq_t txq = ctx->ifc_txqs;
4959 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
4960 iflib_txq_destroy(txq);
4961 for (j = 0; j < ctx->ifc_nhwtxqs; j++)
4962 iflib_dma_free(&txq->ift_ifdi[j]);
4964 free(ctx->ifc_txqs, M_IFLIB);
4965 ctx->ifc_txqs = NULL;
4966 IFDI_QUEUES_FREE(ctx);
4969 /*********************************************************************
4971 * Initialize all receive rings.
4973 **********************************************************************/
4975 iflib_rx_structures_setup(if_ctx_t ctx)
4977 iflib_rxq_t rxq = ctx->ifc_rxqs;
4979 #if defined(INET6) || defined(INET)
4983 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
4984 #if defined(INET6) || defined(INET)
4985 tcp_lro_free(&rxq->ifr_lc);
4986 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
4987 TCP_LRO_ENTRIES, min(1024,
4988 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
4989 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
4992 rxq->ifr_lro_enabled = TRUE;
4994 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
4997 #if defined(INET6) || defined(INET)
5000 * Free RX software descriptors allocated so far, we will only handle
5001 * the rings that completed, the failing case will have
5002 * cleaned up for itself. 'q' failed, so its the terminus.
5004 rxq = ctx->ifc_rxqs;
5005 for (i = 0; i < q; ++i, rxq++) {
5006 iflib_rx_sds_free(rxq);
5007 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5013 /*********************************************************************
5015 * Free all receive rings.
5017 **********************************************************************/
5019 iflib_rx_structures_free(if_ctx_t ctx)
5021 iflib_rxq_t rxq = ctx->ifc_rxqs;
5023 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5024 iflib_rx_sds_free(rxq);
5029 iflib_qset_structures_setup(if_ctx_t ctx)
5033 if ((err = iflib_tx_structures_setup(ctx)) != 0)
5036 if ((err = iflib_rx_structures_setup(ctx)) != 0) {
5037 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5038 iflib_tx_structures_free(ctx);
5039 iflib_rx_structures_free(ctx);
5045 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5046 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name)
5049 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5054 find_nth(if_ctx_t ctx, int qid)
5057 int i, cpuid, eqid, count;
5059 CPU_COPY(&ctx->ifc_cpus, &cpus);
5060 count = CPU_COUNT(&cpus);
5062 /* clear up to the qid'th bit */
5063 for (i = 0; i < eqid; i++) {
5064 cpuid = CPU_FFS(&cpus);
5066 CPU_CLR(cpuid-1, &cpus);
5068 cpuid = CPU_FFS(&cpus);
5074 extern struct cpu_group *cpu_top; /* CPU topology */
5077 find_child_with_core(int cpu, struct cpu_group *grp)
5081 if (grp->cg_children == 0)
5084 MPASS(grp->cg_child);
5085 for (i = 0; i < grp->cg_children; i++) {
5086 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5094 * Find the nth thread on the specified core
5097 find_thread(int cpu, int thread_num)
5099 struct cpu_group *grp;
5107 while ((i = find_child_with_core(cpu, grp)) != -1) {
5108 /* If the child only has one cpu, don't descend */
5109 if (grp->cg_child[i].cg_count <= 1)
5111 grp = &grp->cg_child[i];
5114 /* If they don't share at least an L2 cache, use the same CPU */
5115 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5119 CPU_COPY(&grp->cg_mask, &cs);
5120 for (i = thread_num % grp->cg_count; i > 0; i--) {
5121 MPASS(CPU_FFS(&cs));
5122 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5124 MPASS(CPU_FFS(&cs));
5125 return CPU_FFS(&cs) - 1;
5129 find_thread(int cpu, int thread_num __unused)
5136 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5140 /* TX queues get threads on the same core as the corresponding RX queue */
5141 /* XXX handle multiple RX threads per core and more than two threads per core */
5142 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5144 case IFLIB_INTR_RXTX:
5145 /* RX queues get the first thread on their core */
5146 return qid / CPU_COUNT(&ctx->ifc_cpus);
5152 #define get_thread_num(ctx, type, qid) CPU_FIRST()
5153 #define find_thread(cpuid, tid) CPU_FIRST()
5154 #define find_nth(ctx, gid) CPU_FIRST()
5157 /* Just to avoid copy/paste */
5159 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5160 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name)
5165 cpuid = find_nth(ctx, qid);
5166 tid = get_thread_num(ctx, type, qid);
5168 cpuid = find_thread(cpuid, tid);
5169 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5171 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5175 if (cpuid > ctx->ifc_cpuid_highest)
5176 ctx->ifc_cpuid_highest = cpuid;
5182 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5183 iflib_intr_type_t type, driver_filter_t *filter,
5184 void *filter_arg, int qid, char *name)
5186 struct grouptask *gtask;
5187 struct taskqgroup *tqg;
5188 iflib_filter_info_t info;
5191 driver_filter_t *intr_fast;
5194 info = &ctx->ifc_filter_info;
5198 /* XXX merge tx/rx for netmap? */
5200 q = &ctx->ifc_txqs[qid];
5201 info = &ctx->ifc_txqs[qid].ift_filter_info;
5202 gtask = &ctx->ifc_txqs[qid].ift_task;
5203 tqg = qgroup_if_io_tqg;
5205 intr_fast = iflib_fast_intr;
5206 GROUPTASK_INIT(gtask, 0, fn, q);
5209 q = &ctx->ifc_rxqs[qid];
5210 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5211 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5212 tqg = qgroup_if_io_tqg;
5214 intr_fast = iflib_fast_intr;
5215 GROUPTASK_INIT(gtask, 0, fn, q);
5217 case IFLIB_INTR_RXTX:
5218 q = &ctx->ifc_rxqs[qid];
5219 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5220 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5221 tqg = qgroup_if_io_tqg;
5223 intr_fast = iflib_fast_intr_rxtx;
5224 GROUPTASK_INIT(gtask, 0, fn, q);
5226 case IFLIB_INTR_ADMIN:
5229 info = &ctx->ifc_filter_info;
5230 gtask = &ctx->ifc_admin_task;
5231 tqg = qgroup_if_config_tqg;
5232 fn = _task_fn_admin;
5233 intr_fast = iflib_fast_intr_ctx;
5236 panic("unknown net intr type");
5239 info->ifi_filter = filter;
5240 info->ifi_filter_arg = filter_arg;
5241 info->ifi_task = gtask;
5244 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5246 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5249 if (type == IFLIB_INTR_ADMIN)
5253 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5257 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5264 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name)
5266 struct grouptask *gtask;
5267 struct taskqgroup *tqg;
5275 q = &ctx->ifc_txqs[qid];
5276 gtask = &ctx->ifc_txqs[qid].ift_task;
5277 tqg = qgroup_if_io_tqg;
5280 irq_num = rman_get_start(irq->ii_res);
5283 q = &ctx->ifc_rxqs[qid];
5284 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5285 tqg = qgroup_if_io_tqg;
5288 irq_num = rman_get_start(irq->ii_res);
5290 case IFLIB_INTR_IOV:
5292 gtask = &ctx->ifc_vflr_task;
5293 tqg = qgroup_if_config_tqg;
5297 panic("unknown net intr type");
5299 GROUPTASK_INIT(gtask, 0, fn, q);
5300 if (irq_num != -1) {
5301 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5303 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5306 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5311 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5314 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5317 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5321 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name)
5323 iflib_txq_t txq = ctx->ifc_txqs;
5324 iflib_rxq_t rxq = ctx->ifc_rxqs;
5325 if_irq_t irq = &ctx->ifc_legacy_irq;
5326 iflib_filter_info_t info;
5327 struct grouptask *gtask;
5328 struct taskqgroup *tqg;
5334 q = &ctx->ifc_rxqs[0];
5335 info = &rxq[0].ifr_filter_info;
5336 gtask = &rxq[0].ifr_task;
5337 tqg = qgroup_if_io_tqg;
5338 tqrid = irq->ii_rid = *rid;
5341 ctx->ifc_flags |= IFC_LEGACY;
5342 info->ifi_filter = filter;
5343 info->ifi_filter_arg = filter_arg;
5344 info->ifi_task = gtask;
5345 info->ifi_ctx = ctx;
5347 /* We allocate a single interrupt resource */
5348 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5350 GROUPTASK_INIT(gtask, 0, fn, q);
5351 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5353 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5354 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5359 iflib_led_create(if_ctx_t ctx)
5362 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5363 device_get_nameunit(ctx->ifc_dev));
5367 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5370 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5374 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5377 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5381 iflib_admin_intr_deferred(if_ctx_t ctx)
5384 struct grouptask *gtask;
5386 gtask = &ctx->ifc_admin_task;
5387 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5390 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5394 iflib_iov_intr_deferred(if_ctx_t ctx)
5397 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5401 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5404 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5408 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn,
5412 GROUPTASK_INIT(gtask, 0, fn, ctx);
5413 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5417 iflib_config_gtask_deinit(struct grouptask *gtask)
5420 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5424 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5426 if_t ifp = ctx->ifc_ifp;
5427 iflib_txq_t txq = ctx->ifc_txqs;
5429 if_setbaudrate(ifp, baudrate);
5430 if (baudrate >= IF_Gbps(10))
5431 ctx->ifc_flags |= IFC_PREFETCH;
5433 /* If link down, disable watchdog */
5434 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5435 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5436 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5438 ctx->ifc_link_state = link_state;
5439 if_link_state_change(ifp, link_state);
5443 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5447 int credits_pre = txq->ift_cidx_processed;
5450 if (ctx->isc_txd_credits_update == NULL)
5453 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5456 txq->ift_processed += credits;
5457 txq->ift_cidx_processed += credits;
5459 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5460 if (txq->ift_cidx_processed >= txq->ift_size)
5461 txq->ift_cidx_processed -= txq->ift_size;
5466 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5469 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5474 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5475 const char *description, if_int_delay_info_t info,
5476 int offset, int value)
5478 info->iidi_ctx = ctx;
5479 info->iidi_offset = offset;
5480 info->iidi_value = value;
5481 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5482 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5483 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5484 info, 0, iflib_sysctl_int_delay, "I", description);
5488 iflib_ctx_lock_get(if_ctx_t ctx)
5491 return (&ctx->ifc_mtx);
5495 iflib_msix_init(if_ctx_t ctx)
5497 device_t dev = ctx->ifc_dev;
5498 if_shared_ctx_t sctx = ctx->ifc_sctx;
5499 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5500 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5501 int iflib_num_tx_queues, iflib_num_rx_queues;
5502 int err, admincnt, bar;
5504 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5505 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5507 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5509 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5510 admincnt = sctx->isc_admin_intrcnt;
5511 /* Override by global tuneable */
5514 size_t len = sizeof(i);
5515 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0);
5521 device_printf(dev, "unable to read hw.pci.enable_msix.");
5524 /* Override by tuneable */
5525 if (scctx->isc_disable_msix)
5529 ** When used in a virtualized environment
5530 ** PCI BUSMASTER capability may not be set
5531 ** so explicity set it here and rewrite
5532 ** the ENABLE in the MSIX control register
5533 ** at this point to cause the host to
5534 ** successfully initialize us.
5539 pci_enable_busmaster(dev);
5541 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) {
5542 rid += PCIR_MSIX_CTRL;
5543 msix_ctrl = pci_read_config(dev, rid, 2);
5544 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
5545 pci_write_config(dev, rid, msix_ctrl, 2);
5547 device_printf(dev, "PCIY_MSIX capability not found; "
5548 "or rid %d == 0.\n", rid);
5554 * bar == -1 => "trust me I know what I'm doing"
5555 * Some drivers are for hardware that is so shoddily
5556 * documented that no one knows which bars are which
5557 * so the developer has to map all bars. This hack
5558 * allows shoddy garbage to use msix in this framework.
5561 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
5562 SYS_RES_MEMORY, &bar, RF_ACTIVE);
5563 if (ctx->ifc_msix_mem == NULL) {
5564 /* May not be enabled */
5565 device_printf(dev, "Unable to map MSIX table \n");
5569 /* First try MSI/X */
5570 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
5571 device_printf(dev, "System has MSIX disabled \n");
5572 bus_release_resource(dev, SYS_RES_MEMORY,
5573 bar, ctx->ifc_msix_mem);
5574 ctx->ifc_msix_mem = NULL;
5578 /* use only 1 qset in debug mode */
5579 queuemsgs = min(msgs - admincnt, 1);
5581 queuemsgs = msgs - admincnt;
5584 queues = imin(queuemsgs, rss_getnumbuckets());
5588 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
5589 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
5590 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
5592 /* If we're doing RSS, clamp at the number of RSS buckets */
5593 if (queues > rss_getnumbuckets())
5594 queues = rss_getnumbuckets();
5596 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
5597 rx_queues = iflib_num_rx_queues;
5601 if (rx_queues > scctx->isc_nrxqsets)
5602 rx_queues = scctx->isc_nrxqsets;
5605 * We want this to be all logical CPUs by default
5607 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
5608 tx_queues = iflib_num_tx_queues;
5610 tx_queues = mp_ncpus;
5612 if (tx_queues > scctx->isc_ntxqsets)
5613 tx_queues = scctx->isc_ntxqsets;
5615 if (ctx->ifc_sysctl_qs_eq_override == 0) {
5617 if (tx_queues != rx_queues)
5618 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
5619 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
5621 tx_queues = min(rx_queues, tx_queues);
5622 rx_queues = min(rx_queues, tx_queues);
5625 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
5627 vectors = rx_queues + admincnt;
5628 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
5630 "Using MSIX interrupts with %d vectors\n", vectors);
5631 scctx->isc_vectors = vectors;
5632 scctx->isc_nrxqsets = rx_queues;
5633 scctx->isc_ntxqsets = tx_queues;
5634 scctx->isc_intr = IFLIB_INTR_MSIX;
5638 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
5641 vectors = pci_msi_count(dev);
5642 scctx->isc_nrxqsets = 1;
5643 scctx->isc_ntxqsets = 1;
5644 scctx->isc_vectors = vectors;
5645 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
5646 device_printf(dev,"Using an MSI interrupt\n");
5647 scctx->isc_intr = IFLIB_INTR_MSI;
5649 device_printf(dev,"Using a Legacy interrupt\n");
5650 scctx->isc_intr = IFLIB_INTR_LEGACY;
5656 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
5659 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
5662 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
5664 char *ring_state = "UNKNOWN";
5667 rc = sysctl_wire_old_buffer(req, 0);
5671 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
5676 ring_state = ring_states[state[3]];
5678 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
5679 state[0], state[1], state[2], ring_state);
5680 rc = sbuf_finish(sb);
5685 enum iflib_ndesc_handler {
5691 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
5693 if_ctx_t ctx = (void *)arg1;
5694 enum iflib_ndesc_handler type = arg2;
5695 char buf[256] = {0};
5700 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
5704 case IFLIB_NTXD_HANDLER:
5705 ndesc = ctx->ifc_sysctl_ntxds;
5707 nqs = ctx->ifc_sctx->isc_ntxqs;
5709 case IFLIB_NRXD_HANDLER:
5710 ndesc = ctx->ifc_sysctl_nrxds;
5712 nqs = ctx->ifc_sctx->isc_nrxqs;
5718 for (i=0; i<8; i++) {
5723 sprintf(strchr(buf, 0), "%d", ndesc[i]);
5726 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
5727 if (rc || req->newptr == NULL)
5730 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
5731 i++, p = strsep(&next, " ,")) {
5732 ndesc[i] = strtoul(p, NULL, 10);
5738 #define NAME_BUFLEN 32
5740 iflib_add_device_sysctl_pre(if_ctx_t ctx)
5742 device_t dev = iflib_get_dev(ctx);
5743 struct sysctl_oid_list *child, *oid_list;
5744 struct sysctl_ctx_list *ctx_list;
5745 struct sysctl_oid *node;
5747 ctx_list = device_get_sysctl_ctx(dev);
5748 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
5749 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
5750 CTLFLAG_RD, NULL, "IFLIB fields");
5751 oid_list = SYSCTL_CHILDREN(node);
5753 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
5754 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
5757 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
5758 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
5759 "# of txqs to use, 0 => use default #");
5760 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
5761 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
5762 "# of rxqs to use, 0 => use default #");
5763 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
5764 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
5765 "permit #txq != #rxq");
5766 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
5767 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
5768 "disable MSIX (default 0)");
5769 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
5770 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
5771 "set the rx budget");
5773 /* XXX change for per-queue sizes */
5774 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
5775 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
5776 mp_ndesc_handler, "A",
5777 "list of # of tx descriptors to use, 0 = use default #");
5778 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
5779 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
5780 mp_ndesc_handler, "A",
5781 "list of # of rx descriptors to use, 0 = use default #");
5785 iflib_add_device_sysctl_post(if_ctx_t ctx)
5787 if_shared_ctx_t sctx = ctx->ifc_sctx;
5788 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5789 device_t dev = iflib_get_dev(ctx);
5790 struct sysctl_oid_list *child;
5791 struct sysctl_ctx_list *ctx_list;
5796 char namebuf[NAME_BUFLEN];
5798 struct sysctl_oid *queue_node, *fl_node, *node;
5799 struct sysctl_oid_list *queue_list, *fl_list;
5800 ctx_list = device_get_sysctl_ctx(dev);
5802 node = ctx->ifc_sysctl_node;
5803 child = SYSCTL_CHILDREN(node);
5805 if (scctx->isc_ntxqsets > 100)
5807 else if (scctx->isc_ntxqsets > 10)
5811 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
5812 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5813 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5814 CTLFLAG_RD, NULL, "Queue Name");
5815 queue_list = SYSCTL_CHILDREN(queue_node);
5817 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
5819 &txq->ift_dequeued, "total mbufs freed");
5820 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
5822 &txq->ift_enqueued, "total mbufs enqueued");
5824 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
5826 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
5827 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
5829 &txq->ift_pullups, "# of times m_pullup was called");
5830 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
5832 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
5833 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
5835 &txq->ift_no_desc_avail, "# of times no descriptors were available");
5836 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
5838 &txq->ift_map_failed, "# of times dma map failed");
5839 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
5841 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
5842 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
5844 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
5845 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
5847 &txq->ift_pidx, 1, "Producer Index");
5848 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
5850 &txq->ift_cidx, 1, "Consumer Index");
5851 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
5853 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
5854 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
5856 &txq->ift_in_use, 1, "descriptors in use");
5857 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
5859 &txq->ift_processed, "descriptors procesed for clean");
5860 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
5862 &txq->ift_cleaned, "total cleaned");
5863 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
5864 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
5865 0, mp_ring_state_handler, "A", "soft ring state");
5866 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
5867 CTLFLAG_RD, &txq->ift_br->enqueues,
5868 "# of enqueues to the mp_ring for this queue");
5869 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
5870 CTLFLAG_RD, &txq->ift_br->drops,
5871 "# of drops in the mp_ring for this queue");
5872 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
5873 CTLFLAG_RD, &txq->ift_br->starts,
5874 "# of normal consumer starts in the mp_ring for this queue");
5875 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
5876 CTLFLAG_RD, &txq->ift_br->stalls,
5877 "# of consumer stalls in the mp_ring for this queue");
5878 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
5879 CTLFLAG_RD, &txq->ift_br->restarts,
5880 "# of consumer restarts in the mp_ring for this queue");
5881 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
5882 CTLFLAG_RD, &txq->ift_br->abdications,
5883 "# of consumer abdications in the mp_ring for this queue");
5886 if (scctx->isc_nrxqsets > 100)
5888 else if (scctx->isc_nrxqsets > 10)
5892 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
5893 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
5894 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
5895 CTLFLAG_RD, NULL, "Queue Name");
5896 queue_list = SYSCTL_CHILDREN(queue_node);
5897 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5898 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
5900 &rxq->ifr_cq_pidx, 1, "Producer Index");
5901 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
5903 &rxq->ifr_cq_cidx, 1, "Consumer Index");
5906 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
5907 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
5908 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
5909 CTLFLAG_RD, NULL, "freelist Name");
5910 fl_list = SYSCTL_CHILDREN(fl_node);
5911 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
5913 &fl->ifl_pidx, 1, "Producer Index");
5914 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
5916 &fl->ifl_cidx, 1, "Consumer Index");
5917 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
5919 &fl->ifl_credits, 1, "credits available");
5921 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
5923 &fl->ifl_m_enqueued, "mbufs allocated");
5924 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
5926 &fl->ifl_m_dequeued, "mbufs freed");
5927 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
5929 &fl->ifl_cl_enqueued, "clusters allocated");
5930 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
5932 &fl->ifl_cl_dequeued, "clusters freed");
5940 #ifndef __NO_STRICT_ALIGNMENT
5941 static struct mbuf *
5942 iflib_fixup_rx(struct mbuf *m)
5946 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
5947 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
5948 m->m_data += ETHER_HDR_LEN;
5951 MGETHDR(n, M_NOWAIT, MT_DATA);
5956 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
5957 m->m_data += ETHER_HDR_LEN;
5958 m->m_len -= ETHER_HDR_LEN;
5959 n->m_len = ETHER_HDR_LEN;
5960 M_MOVE_PKTHDR(n, m);