2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 struct ether_addr ifc_mac;
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (ctx->ifc_mediap);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_buf_tag;
357 bus_dma_tag_t ift_tso_buf_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 32
360 char ift_mtx_name[MTX_NAME_LEN];
361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 uint64_t ift_cpu_exec_count[256];
365 } __aligned(CACHE_LINE_SIZE);
372 uint8_t ifl_rxd_size;
374 uint64_t ifl_m_enqueued;
375 uint64_t ifl_m_dequeued;
376 uint64_t ifl_cl_enqueued;
377 uint64_t ifl_cl_dequeued;
380 bitstr_t *ifl_rx_bitmap;
384 uint16_t ifl_buf_size;
387 iflib_rxsd_array_t ifl_sds;
390 bus_dma_tag_t ifl_buf_tag;
391 iflib_dma_info_t ifl_ifdi;
392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the completion queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct callout ifr_watchdog;
438 struct iflib_filter_info ifr_filter_info;
439 iflib_dma_info_t ifr_ifdi;
441 /* dynamically allocate if any drivers need a value substantially larger than this */
442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 uint64_t ifr_cpu_exec_count[256];
446 } __aligned(CACHE_LINE_SIZE);
448 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
708 static void iflib_init_locked(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
710 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
711 static void iflib_ifmp_purge(iflib_txq_t txq);
712 static void _iflib_pre_assert(if_softc_ctx_t scctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 static void iflib_free_intr_mem(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
720 SLIST_HEAD_INITIALIZER(cpu_offsets);
722 SLIST_ENTRY(cpu_offset) entries;
724 unsigned int refcount;
727 static struct mtx cpu_offset_mtx;
728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
731 DEBUGNET_DEFINE(iflib);
734 iflib_num_rx_descs(if_ctx_t ctx)
736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
737 if_shared_ctx_t sctx = ctx->ifc_sctx;
738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
740 return scctx->isc_nrxd[first_rxq];
744 iflib_num_tx_descs(if_ctx_t ctx)
746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
747 if_shared_ctx_t sctx = ctx->ifc_sctx;
748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
750 return scctx->isc_ntxd[first_txq];
754 #include <sys/selinfo.h>
755 #include <net/netmap.h>
756 #include <dev/netmap/netmap_kern.h>
758 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
763 * device-specific sysctl variables:
765 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
766 * During regular operations the CRC is stripped, but on some
767 * hardware reception of frames not multiple of 64 is slower,
768 * so using crcstrip=0 helps in benchmarks.
770 * iflib_rx_miss, iflib_rx_miss_bufs:
771 * count packets that might be missed due to lost interrupts.
773 SYSCTL_DECL(_dev_netmap);
775 * The xl driver by default strips CRCs and we do not override it.
778 int iflib_crcstrip = 1;
779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
780 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
782 int iflib_rx_miss, iflib_rx_miss_bufs;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
784 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
786 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
789 * Register/unregister. We are already under netmap lock.
790 * Only called on the first register or the last unregister.
793 iflib_netmap_register(struct netmap_adapter *na, int onoff)
796 if_ctx_t ctx = ifp->if_softc;
800 IFDI_INTR_DISABLE(ctx);
802 /* Tell the stack that the interface is no longer active */
803 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
811 * Enable (or disable) netmap flags, and intercept (or restore)
812 * ifp->if_transmit. This is done once the device has been stopped
813 * to prevent race conditions.
816 nm_set_native_flags(na);
818 nm_clear_native_flags(na);
821 iflib_init_locked(ctx);
822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
825 nm_clear_native_flags(na);
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
833 struct netmap_adapter *na = kring->na;
834 u_int const lim = kring->nkr_num_slots - 1;
835 u_int head = kring->rhead;
836 struct netmap_ring *ring = kring->ring;
838 struct if_rxd_update iru;
839 if_ctx_t ctx = rxq->ifr_ctx;
840 iflib_fl_t fl = &rxq->ifr_fl[0];
841 uint32_t nic_i_first, nic_i;
843 #if IFLIB_DEBUG_COUNTERS
847 if (nm_i == head && __predict_true(!init))
850 iru_init(&iru, rxq, 0 /* flid */);
851 map = fl->ifl_sds.ifsd_map;
852 nic_i = netmap_idx_k2n(kring, nm_i);
854 * IMPORTANT: we must leave one free slot in the ring,
855 * so move head back by one unit
857 head = nm_prev(head, lim);
858 DBG_COUNTER_INC(fl_refills);
859 while (nm_i != head) {
860 #if IFLIB_DEBUG_COUNTERS
862 DBG_COUNTER_INC(fl_refills_large);
865 for (i = 0; i < IFLIB_MAX_RX_REFRESH && nm_i != head; i++) {
866 struct netmap_slot *slot = &ring->slot[nm_i];
867 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]);
869 MPASS(i < IFLIB_MAX_RX_REFRESH);
871 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
872 return netmap_ring_reinit(kring);
874 fl->ifl_rxd_idxs[i] = nic_i;
876 if (__predict_false(init)) {
877 netmap_load_map(na, fl->ifl_buf_tag,
879 } else if (slot->flags & NS_BUF_CHANGED) {
880 /* buffer has changed, reload map */
881 netmap_reload_map(na, fl->ifl_buf_tag,
884 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
885 BUS_DMASYNC_PREREAD);
886 slot->flags &= ~NS_BUF_CHANGED;
888 nm_i = nm_next(nm_i, lim);
889 nic_i = nm_next(nic_i, lim);
892 iru.iru_pidx = nic_i_first;
894 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
896 kring->nr_hwcur = head;
898 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
899 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
900 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
901 DBG_COUNTER_INC(rxd_flush);
907 * Reconcile kernel and user view of the transmit ring.
909 * All information is in the kring.
910 * Userspace wants to send packets up to the one before kring->rhead,
911 * kernel knows kring->nr_hwcur is the first unsent packet.
913 * Here we push packets out (as many as possible), and possibly
914 * reclaim buffers from previously completed transmission.
916 * The caller (netmap) guarantees that there is only one instance
917 * running at any time. Any interference with other driver
918 * methods should be handled by the individual drivers.
921 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
923 struct netmap_adapter *na = kring->na;
925 struct netmap_ring *ring = kring->ring;
926 u_int nm_i; /* index into the netmap kring */
927 u_int nic_i; /* index into the NIC ring */
929 u_int const lim = kring->nkr_num_slots - 1;
930 u_int const head = kring->rhead;
931 struct if_pkt_info pi;
934 * interrupts on every tx packet are expensive so request
935 * them every half ring, or where NS_REPORT is set
937 u_int report_frequency = kring->nkr_num_slots >> 1;
938 /* device-specific */
939 if_ctx_t ctx = ifp->if_softc;
940 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
942 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
943 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
946 * First part: process new packets to send.
947 * nm_i is the current index in the netmap kring,
948 * nic_i is the corresponding index in the NIC ring.
950 * If we have packets to send (nm_i != head)
951 * iterate over the netmap ring, fetch length and update
952 * the corresponding slot in the NIC ring. Some drivers also
953 * need to update the buffer's physical address in the NIC slot
954 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
956 * The netmap_reload_map() calls is especially expensive,
957 * even when (as in this case) the tag is 0, so do only
958 * when the buffer has actually changed.
960 * If possible do not set the report/intr bit on all slots,
961 * but only a few times per ring or when NS_REPORT is set.
963 * Finally, on 10G and faster drivers, it might be useful
964 * to prefetch the next slot and txr entry.
967 nm_i = kring->nr_hwcur;
968 if (nm_i != head) { /* we have new packets to send */
970 pi.ipi_segs = txq->ift_segs;
971 pi.ipi_qsidx = kring->ring_id;
972 nic_i = netmap_idx_k2n(kring, nm_i);
974 __builtin_prefetch(&ring->slot[nm_i]);
975 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
976 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
978 for (n = 0; nm_i != head; n++) {
979 struct netmap_slot *slot = &ring->slot[nm_i];
980 u_int len = slot->len;
982 void *addr = PNMB(na, slot, &paddr);
983 int flags = (slot->flags & NS_REPORT ||
984 nic_i == 0 || nic_i == report_frequency) ?
987 /* device-specific */
989 pi.ipi_segs[0].ds_addr = paddr;
990 pi.ipi_segs[0].ds_len = len;
994 pi.ipi_flags = flags;
996 /* Fill the slot in the NIC ring. */
997 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
998 DBG_COUNTER_INC(tx_encap);
1000 /* prefetch for next round */
1001 __builtin_prefetch(&ring->slot[nm_i + 1]);
1002 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1003 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1005 NM_CHECK_ADDR_LEN(na, addr, len);
1007 if (slot->flags & NS_BUF_CHANGED) {
1008 /* buffer has changed, reload map */
1009 netmap_reload_map(na, txq->ift_buf_tag,
1010 txq->ift_sds.ifsd_map[nic_i], addr);
1012 /* make sure changes to the buffer are synced */
1013 bus_dmamap_sync(txq->ift_buf_tag,
1014 txq->ift_sds.ifsd_map[nic_i],
1015 BUS_DMASYNC_PREWRITE);
1017 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1018 nm_i = nm_next(nm_i, lim);
1019 nic_i = nm_next(nic_i, lim);
1021 kring->nr_hwcur = nm_i;
1023 /* synchronize the NIC ring */
1024 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1025 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1027 /* (re)start the tx unit up to slot nic_i (excluded) */
1028 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1032 * Second part: reclaim buffers for completed transmissions.
1034 * If there are unclaimed buffers, attempt to reclaim them.
1035 * If none are reclaimed, and TX IRQs are not in use, do an initial
1036 * minimal delay, then trigger the tx handler which will spin in the
1039 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1040 if (iflib_tx_credits_update(ctx, txq)) {
1041 /* some tx completed, increment avail */
1042 nic_i = txq->ift_cidx_processed;
1043 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1046 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1047 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1048 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1049 iflib_timer, txq, txq->ift_timer.c_cpu);
1055 * Reconcile kernel and user view of the receive ring.
1056 * Same as for the txsync, this routine must be efficient.
1057 * The caller guarantees a single invocations, but races against
1058 * the rest of the driver should be handled here.
1060 * On call, kring->rhead is the first packet that userspace wants
1061 * to keep, and kring->rcur is the wakeup point.
1062 * The kernel has previously reported packets up to kring->rtail.
1064 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1065 * of whether or not we received an interrupt.
1068 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1070 struct netmap_adapter *na = kring->na;
1071 struct netmap_ring *ring = kring->ring;
1073 uint32_t nm_i; /* index into the netmap ring */
1074 uint32_t nic_i; /* index into the NIC ring */
1076 u_int const lim = kring->nkr_num_slots - 1;
1077 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1079 if_ctx_t ctx = ifp->if_softc;
1080 if_shared_ctx_t sctx = ctx->ifc_sctx;
1081 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1082 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1083 iflib_fl_t fl = &rxq->ifr_fl[0];
1084 struct if_rxd_info ri;
1088 * netmap only uses free list 0, to avoid out of order consumption
1089 * of receive buffers
1092 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1093 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1096 * First part: import newly received packets.
1098 * nm_i is the index of the next free slot in the netmap ring,
1099 * nic_i is the index of the next received packet in the NIC ring
1100 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1101 * differ in case if_init() has been called while
1102 * in netmap mode. For the receive ring we have
1104 * nic_i = fl->ifl_cidx;
1105 * nm_i = kring->nr_hwtail (previous)
1107 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1109 * fl->ifl_cidx is set to 0 on a ring reinit
1111 if (netmap_no_pendintr || force_update) {
1112 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1113 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1114 int crclen = iflib_crcstrip ? 0 : 4;
1118 * For the free list consumer index, we use the same
1119 * logic as in iflib_rxeof().
1122 cidxp = &rxq->ifr_cq_cidx;
1124 cidxp = &fl->ifl_cidx;
1125 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1126 rxq->ifr_id, *cidxp, USHRT_MAX);
1128 nic_i = fl->ifl_cidx;
1129 nm_i = netmap_idx_n2k(kring, nic_i);
1130 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1132 ri.iri_frags = rxq->ifr_frags;
1133 ri.iri_qsidx = kring->ring_id;
1134 ri.iri_ifp = ctx->ifc_ifp;
1135 ri.iri_cidx = *cidxp;
1137 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1138 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1139 ring->slot[nm_i].flags = 0;
1141 *cidxp = ri.iri_cidx;
1142 while (*cidxp >= scctx->isc_nrxd[0])
1143 *cidxp -= scctx->isc_nrxd[0];
1145 bus_dmamap_sync(fl->ifl_buf_tag,
1146 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1147 nm_i = nm_next(nm_i, lim);
1148 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1150 if (n) { /* update the state variables */
1151 if (netmap_no_pendintr && !force_update) {
1154 iflib_rx_miss_bufs += n;
1156 kring->nr_hwtail = nm_i;
1158 kring->nr_kflags &= ~NKR_PENDINTR;
1161 * Second part: skip past packets that userspace has released.
1162 * (kring->nr_hwcur to head excluded),
1163 * and make the buffers available for reception.
1164 * As usual nm_i is the index in the netmap ring,
1165 * nic_i is the index in the NIC ring, and
1166 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1168 nm_i = kring->nr_hwcur;
1170 return (netmap_fl_refill(rxq, kring, nm_i, false));
1174 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1176 if_ctx_t ctx = na->ifp->if_softc;
1180 IFDI_INTR_ENABLE(ctx);
1182 IFDI_INTR_DISABLE(ctx);
1189 iflib_netmap_attach(if_ctx_t ctx)
1191 struct netmap_adapter na;
1193 bzero(&na, sizeof(na));
1195 na.ifp = ctx->ifc_ifp;
1196 na.na_flags = NAF_BDG_MAYSLEEP;
1197 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1198 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1200 na.num_tx_desc = iflib_num_tx_descs(ctx);
1201 na.num_rx_desc = iflib_num_rx_descs(ctx);
1202 na.nm_txsync = iflib_netmap_txsync;
1203 na.nm_rxsync = iflib_netmap_rxsync;
1204 na.nm_register = iflib_netmap_register;
1205 na.nm_intr = iflib_netmap_intr;
1206 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1207 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1208 return (netmap_attach(&na));
1212 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1214 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1215 struct netmap_slot *slot;
1217 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1220 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1223 * In netmap mode, set the map for the packet buffer.
1224 * NOTE: Some drivers (not this one) also need to set
1225 * the physical buffer address in the NIC ring.
1226 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1227 * netmap slot index, si
1229 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1230 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1231 NMB(na, slot + si));
1237 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1239 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1240 struct netmap_kring *kring;
1241 struct netmap_slot *slot;
1244 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1247 kring = na->rx_rings[rxq->ifr_id];
1248 nm_i = netmap_idx_n2k(kring, 0);
1249 netmap_fl_refill(rxq, kring, nm_i, true);
1254 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1256 struct netmap_kring *kring;
1259 txqid = txq->ift_id;
1260 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX);
1264 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1265 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1266 BUS_DMASYNC_POSTREAD);
1267 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1268 netmap_tx_irq(ctx->ifc_ifp, txqid);
1269 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1273 *reset_on = hz / 1000;
1278 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1281 #define iflib_netmap_txq_init(ctx, txq) (0)
1282 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1283 #define iflib_netmap_detach(ifp)
1285 #define iflib_netmap_attach(ctx) (0)
1286 #define netmap_rx_irq(ifp, qid, budget) (0)
1287 #define netmap_tx_irq(ifp, qid) do {} while (0)
1288 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1291 #if defined(__i386__) || defined(__amd64__)
1292 static __inline void
1295 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1297 static __inline void
1298 prefetch2cachelines(void *x)
1300 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1301 #if (CACHE_LINE_SIZE < 128)
1302 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1307 #define prefetch2cachelines(x)
1311 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1315 fl = &rxq->ifr_fl[flid];
1316 iru->iru_paddrs = fl->ifl_bus_addrs;
1317 iru->iru_idxs = fl->ifl_rxd_idxs;
1318 iru->iru_qsidx = rxq->ifr_id;
1319 iru->iru_buf_size = fl->ifl_buf_size;
1320 iru->iru_flidx = fl->ifl_id;
1324 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1328 *(bus_addr_t *) arg = segs[0].ds_addr;
1332 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1335 device_t dev = ctx->ifc_dev;
1337 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1338 align, 0, /* alignment, bounds */
1339 BUS_SPACE_MAXADDR, /* lowaddr */
1340 BUS_SPACE_MAXADDR, /* highaddr */
1341 NULL, NULL, /* filter, filterarg */
1344 size, /* maxsegsize */
1345 BUS_DMA_ALLOCNOW, /* flags */
1346 NULL, /* lockfunc */
1351 "%s: bus_dma_tag_create failed: %d\n",
1356 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1357 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1360 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1361 __func__, (uintmax_t)size, err);
1365 dma->idi_paddr = IF_BAD_DMA;
1366 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1367 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1368 if (err || dma->idi_paddr == IF_BAD_DMA) {
1370 "%s: bus_dmamap_load failed: %d\n",
1375 dma->idi_size = size;
1379 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1381 bus_dma_tag_destroy(dma->idi_tag);
1383 dma->idi_tag = NULL;
1389 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1391 if_shared_ctx_t sctx = ctx->ifc_sctx;
1393 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1395 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1399 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1402 iflib_dma_info_t *dmaiter;
1405 for (i = 0; i < count; i++, dmaiter++) {
1406 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1410 iflib_dma_free_multi(dmalist, i);
1415 iflib_dma_free(iflib_dma_info_t dma)
1417 if (dma->idi_tag == NULL)
1419 if (dma->idi_paddr != IF_BAD_DMA) {
1420 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1421 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1422 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1423 dma->idi_paddr = IF_BAD_DMA;
1425 if (dma->idi_vaddr != NULL) {
1426 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1427 dma->idi_vaddr = NULL;
1429 bus_dma_tag_destroy(dma->idi_tag);
1430 dma->idi_tag = NULL;
1434 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1437 iflib_dma_info_t *dmaiter = dmalist;
1439 for (i = 0; i < count; i++, dmaiter++)
1440 iflib_dma_free(*dmaiter);
1444 iflib_fast_intr(void *arg)
1446 iflib_filter_info_t info = arg;
1447 struct grouptask *gtask = info->ifi_task;
1450 DBG_COUNTER_INC(fast_intrs);
1451 if (info->ifi_filter != NULL) {
1452 result = info->ifi_filter(info->ifi_filter_arg);
1453 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1457 GROUPTASK_ENQUEUE(gtask);
1458 return (FILTER_HANDLED);
1462 iflib_fast_intr_rxtx(void *arg)
1464 iflib_filter_info_t info = arg;
1465 struct grouptask *gtask = info->ifi_task;
1467 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1470 int i, cidx, result;
1472 bool intr_enable, intr_legacy;
1474 DBG_COUNTER_INC(fast_intrs);
1475 if (info->ifi_filter != NULL) {
1476 result = info->ifi_filter(info->ifi_filter_arg);
1477 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1482 sc = ctx->ifc_softc;
1483 intr_enable = false;
1484 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1485 MPASS(rxq->ifr_ntxqirq);
1486 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1487 txqid = rxq->ifr_txqid[i];
1488 txq = &ctx->ifc_txqs[txqid];
1489 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1490 BUS_DMASYNC_POSTREAD);
1491 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1495 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1498 GROUPTASK_ENQUEUE(&txq->ift_task);
1500 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1501 cidx = rxq->ifr_cq_cidx;
1503 cidx = rxq->ifr_fl[0].ifl_cidx;
1504 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1505 GROUPTASK_ENQUEUE(gtask);
1510 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1511 DBG_COUNTER_INC(rx_intr_enables);
1514 IFDI_INTR_ENABLE(ctx);
1515 return (FILTER_HANDLED);
1520 iflib_fast_intr_ctx(void *arg)
1522 iflib_filter_info_t info = arg;
1523 struct grouptask *gtask = info->ifi_task;
1526 DBG_COUNTER_INC(fast_intrs);
1527 if (info->ifi_filter != NULL) {
1528 result = info->ifi_filter(info->ifi_filter_arg);
1529 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1533 GROUPTASK_ENQUEUE(gtask);
1534 return (FILTER_HANDLED);
1538 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1539 driver_filter_t filter, driver_intr_t handler, void *arg,
1542 struct resource *res;
1544 device_t dev = ctx->ifc_dev;
1548 if (ctx->ifc_flags & IFC_LEGACY)
1549 flags |= RF_SHAREABLE;
1552 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1555 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1559 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1560 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1561 filter, handler, arg, &tag);
1564 "failed to setup interrupt for rid %d, name %s: %d\n",
1565 rid, name ? name : "unknown", rc);
1568 bus_describe_intr(dev, res, tag, "%s", name);
1574 /*********************************************************************
1576 * Allocate DMA resources for TX buffers as well as memory for the TX
1577 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1578 * iflib_sw_tx_desc_array structure, storing all the information that
1579 * is needed to transmit a packet on the wire. This is called only
1580 * once at attach, setup is done every reset.
1582 **********************************************************************/
1584 iflib_txsd_alloc(iflib_txq_t txq)
1586 if_ctx_t ctx = txq->ift_ctx;
1587 if_shared_ctx_t sctx = ctx->ifc_sctx;
1588 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1589 device_t dev = ctx->ifc_dev;
1590 bus_size_t tsomaxsize;
1591 int err, nsegments, ntsosegments;
1594 nsegments = scctx->isc_tx_nsegments;
1595 ntsosegments = scctx->isc_tx_tso_segments_max;
1596 tsomaxsize = scctx->isc_tx_tso_size_max;
1597 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1598 tsomaxsize += sizeof(struct ether_vlan_header);
1599 MPASS(scctx->isc_ntxd[0] > 0);
1600 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1601 MPASS(nsegments > 0);
1602 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1603 MPASS(ntsosegments > 0);
1604 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1608 * Set up DMA tags for TX buffers.
1610 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1611 1, 0, /* alignment, bounds */
1612 BUS_SPACE_MAXADDR, /* lowaddr */
1613 BUS_SPACE_MAXADDR, /* highaddr */
1614 NULL, NULL, /* filter, filterarg */
1615 sctx->isc_tx_maxsize, /* maxsize */
1616 nsegments, /* nsegments */
1617 sctx->isc_tx_maxsegsize, /* maxsegsize */
1619 NULL, /* lockfunc */
1620 NULL, /* lockfuncarg */
1621 &txq->ift_buf_tag))) {
1622 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1623 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1624 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1627 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1628 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1629 1, 0, /* alignment, bounds */
1630 BUS_SPACE_MAXADDR, /* lowaddr */
1631 BUS_SPACE_MAXADDR, /* highaddr */
1632 NULL, NULL, /* filter, filterarg */
1633 tsomaxsize, /* maxsize */
1634 ntsosegments, /* nsegments */
1635 sctx->isc_tso_maxsegsize,/* maxsegsize */
1637 NULL, /* lockfunc */
1638 NULL, /* lockfuncarg */
1639 &txq->ift_tso_buf_tag))) {
1640 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1645 /* Allocate memory for the TX mbuf map. */
1646 if (!(txq->ift_sds.ifsd_m =
1647 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1648 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1649 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1655 * Create the DMA maps for TX buffers.
1657 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1658 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1659 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1661 "Unable to allocate TX buffer DMA map memory\n");
1665 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1666 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1667 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1669 "Unable to allocate TSO TX buffer map memory\n");
1673 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1674 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1675 &txq->ift_sds.ifsd_map[i]);
1677 device_printf(dev, "Unable to create TX DMA map\n");
1682 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1683 &txq->ift_sds.ifsd_tso_map[i]);
1685 device_printf(dev, "Unable to create TSO TX DMA map\n");
1691 /* We free all, it handles case where we are in the middle */
1692 iflib_tx_structures_free(ctx);
1697 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1701 if (txq->ift_sds.ifsd_map != NULL) {
1702 map = txq->ift_sds.ifsd_map[i];
1703 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1704 bus_dmamap_unload(txq->ift_buf_tag, map);
1705 bus_dmamap_destroy(txq->ift_buf_tag, map);
1706 txq->ift_sds.ifsd_map[i] = NULL;
1709 if (txq->ift_sds.ifsd_tso_map != NULL) {
1710 map = txq->ift_sds.ifsd_tso_map[i];
1711 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1712 BUS_DMASYNC_POSTWRITE);
1713 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1714 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1715 txq->ift_sds.ifsd_tso_map[i] = NULL;
1720 iflib_txq_destroy(iflib_txq_t txq)
1722 if_ctx_t ctx = txq->ift_ctx;
1724 for (int i = 0; i < txq->ift_size; i++)
1725 iflib_txsd_destroy(ctx, txq, i);
1727 if (txq->ift_br != NULL) {
1728 ifmp_ring_free(txq->ift_br);
1732 mtx_destroy(&txq->ift_mtx);
1734 if (txq->ift_sds.ifsd_map != NULL) {
1735 free(txq->ift_sds.ifsd_map, M_IFLIB);
1736 txq->ift_sds.ifsd_map = NULL;
1738 if (txq->ift_sds.ifsd_tso_map != NULL) {
1739 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1740 txq->ift_sds.ifsd_tso_map = NULL;
1742 if (txq->ift_sds.ifsd_m != NULL) {
1743 free(txq->ift_sds.ifsd_m, M_IFLIB);
1744 txq->ift_sds.ifsd_m = NULL;
1746 if (txq->ift_buf_tag != NULL) {
1747 bus_dma_tag_destroy(txq->ift_buf_tag);
1748 txq->ift_buf_tag = NULL;
1750 if (txq->ift_tso_buf_tag != NULL) {
1751 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1752 txq->ift_tso_buf_tag = NULL;
1754 if (txq->ift_ifdi != NULL) {
1755 free(txq->ift_ifdi, M_IFLIB);
1760 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1764 mp = &txq->ift_sds.ifsd_m[i];
1768 if (txq->ift_sds.ifsd_map != NULL) {
1769 bus_dmamap_sync(txq->ift_buf_tag,
1770 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1771 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1773 if (txq->ift_sds.ifsd_tso_map != NULL) {
1774 bus_dmamap_sync(txq->ift_tso_buf_tag,
1775 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1776 bus_dmamap_unload(txq->ift_tso_buf_tag,
1777 txq->ift_sds.ifsd_tso_map[i]);
1780 DBG_COUNTER_INC(tx_frees);
1785 iflib_txq_setup(iflib_txq_t txq)
1787 if_ctx_t ctx = txq->ift_ctx;
1788 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1789 if_shared_ctx_t sctx = ctx->ifc_sctx;
1790 iflib_dma_info_t di;
1793 /* Set number of descriptors available */
1794 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1795 /* XXX make configurable */
1796 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1799 txq->ift_cidx_processed = 0;
1800 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1801 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1803 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1804 bzero((void *)di->idi_vaddr, di->idi_size);
1806 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1807 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1808 bus_dmamap_sync(di->idi_tag, di->idi_map,
1809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1813 /*********************************************************************
1815 * Allocate DMA resources for RX buffers as well as memory for the RX
1816 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1817 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1818 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1819 * Since we use use one entry in iflib_sw_rx_desc_array per received
1820 * packet, the maximum number of entries we'll need is equal to the
1821 * number of hardware receive descriptors that we've allocated.
1823 **********************************************************************/
1825 iflib_rxsd_alloc(iflib_rxq_t rxq)
1827 if_ctx_t ctx = rxq->ifr_ctx;
1828 if_shared_ctx_t sctx = ctx->ifc_sctx;
1829 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1830 device_t dev = ctx->ifc_dev;
1834 MPASS(scctx->isc_nrxd[0] > 0);
1835 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1838 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1839 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1840 /* Set up DMA tag for RX buffers. */
1841 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1842 1, 0, /* alignment, bounds */
1843 BUS_SPACE_MAXADDR, /* lowaddr */
1844 BUS_SPACE_MAXADDR, /* highaddr */
1845 NULL, NULL, /* filter, filterarg */
1846 sctx->isc_rx_maxsize, /* maxsize */
1847 sctx->isc_rx_nsegments, /* nsegments */
1848 sctx->isc_rx_maxsegsize, /* maxsegsize */
1850 NULL, /* lockfunc */
1855 "Unable to allocate RX DMA tag: %d\n", err);
1859 /* Allocate memory for the RX mbuf map. */
1860 if (!(fl->ifl_sds.ifsd_m =
1861 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1862 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1864 "Unable to allocate RX mbuf map memory\n");
1869 /* Allocate memory for the direct RX cluster pointer map. */
1870 if (!(fl->ifl_sds.ifsd_cl =
1871 (caddr_t *) malloc(sizeof(caddr_t) *
1872 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1874 "Unable to allocate RX cluster map memory\n");
1879 /* Allocate memory for the RX cluster bus address map. */
1880 if (!(fl->ifl_sds.ifsd_ba =
1881 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1882 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1884 "Unable to allocate RX bus address map memory\n");
1890 * Create the DMA maps for RX buffers.
1892 if (!(fl->ifl_sds.ifsd_map =
1893 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1895 "Unable to allocate RX buffer DMA map memory\n");
1899 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1900 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1901 &fl->ifl_sds.ifsd_map[i]);
1903 device_printf(dev, "Unable to create RX buffer DMA map\n");
1911 iflib_rx_structures_free(ctx);
1917 * Internal service routines
1920 struct rxq_refill_cb_arg {
1922 bus_dma_segment_t seg;
1927 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1929 struct rxq_refill_cb_arg *cb_arg = arg;
1931 cb_arg->error = error;
1932 cb_arg->seg = segs[0];
1933 cb_arg->nseg = nseg;
1937 * iflib_fl_refill - refill an rxq free-buffer list
1938 * @ctx: the iflib context
1939 * @fl: the free list to refill
1940 * @count: the number of new buffers to allocate
1942 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1943 * The caller must assure that @count does not exceed the queue's capacity.
1946 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1948 struct if_rxd_update iru;
1949 struct rxq_refill_cb_arg cb_arg;
1953 bus_dmamap_t *sd_map;
1954 bus_addr_t bus_addr, *sd_ba;
1955 int err, frag_idx, i, idx, n, pidx;
1958 sd_m = fl->ifl_sds.ifsd_m;
1959 sd_map = fl->ifl_sds.ifsd_map;
1960 sd_cl = fl->ifl_sds.ifsd_cl;
1961 sd_ba = fl->ifl_sds.ifsd_ba;
1962 pidx = fl->ifl_pidx;
1964 frag_idx = fl->ifl_fragidx;
1965 credits = fl->ifl_credits;
1970 MPASS(credits + n <= fl->ifl_size);
1972 if (pidx < fl->ifl_cidx)
1973 MPASS(pidx + n <= fl->ifl_cidx);
1974 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1975 MPASS(fl->ifl_gen == 0);
1976 if (pidx > fl->ifl_cidx)
1977 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1979 DBG_COUNTER_INC(fl_refills);
1981 DBG_COUNTER_INC(fl_refills_large);
1982 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1985 * We allocate an uninitialized mbuf + cluster, mbuf is
1986 * initialized after rx.
1988 * If the cluster is still set then we know a minimum sized
1989 * packet was received
1991 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1994 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1995 MPASS(frag_idx >= 0);
1996 if ((cl = sd_cl[frag_idx]) == NULL) {
1997 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
1998 if (__predict_false(cl == NULL))
2002 MPASS(sd_map != NULL);
2003 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2004 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2006 if (__predict_false(err != 0 || cb_arg.error)) {
2007 uma_zfree(fl->ifl_zone, cl);
2011 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2012 sd_cl[frag_idx] = cl;
2014 fl->ifl_cl_enqueued++;
2017 bus_addr = sd_ba[frag_idx];
2019 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2020 BUS_DMASYNC_PREREAD);
2022 if (sd_m[frag_idx] == NULL) {
2023 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2024 if (__predict_false(m == NULL))
2028 bit_set(fl->ifl_rx_bitmap, frag_idx);
2030 fl->ifl_m_enqueued++;
2033 DBG_COUNTER_INC(rx_allocs);
2034 fl->ifl_rxd_idxs[i] = frag_idx;
2035 fl->ifl_bus_addrs[i] = bus_addr;
2038 MPASS(credits <= fl->ifl_size);
2039 if (++idx == fl->ifl_size) {
2045 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2046 iru.iru_pidx = pidx;
2048 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2050 fl->ifl_credits = credits;
2056 if (n < count - 1) {
2058 iru.iru_pidx = pidx;
2060 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2062 fl->ifl_credits = credits;
2064 DBG_COUNTER_INC(rxd_flush);
2065 if (fl->ifl_pidx == 0)
2066 pidx = fl->ifl_size - 1;
2068 pidx = fl->ifl_pidx - 1;
2070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2072 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2074 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2075 fl->ifl_fragidx = frag_idx + 1;
2076 if (fl->ifl_fragidx == fl->ifl_size)
2077 fl->ifl_fragidx = 0;
2079 fl->ifl_fragidx = frag_idx;
2083 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2086 static inline uint8_t
2087 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2089 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2090 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2092 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2095 MPASS(fl->ifl_credits <= fl->ifl_size);
2096 MPASS(reclaimable == delta);
2098 if (reclaimable > 0)
2099 return (iflib_fl_refill(ctx, fl, reclaimable));
2104 iflib_in_detach(if_ctx_t ctx)
2109 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2115 iflib_fl_bufs_free(iflib_fl_t fl)
2117 iflib_dma_info_t idi = fl->ifl_ifdi;
2118 bus_dmamap_t sd_map;
2121 for (i = 0; i < fl->ifl_size; i++) {
2122 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2123 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2125 if (*sd_cl != NULL) {
2126 sd_map = fl->ifl_sds.ifsd_map[i];
2127 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2128 BUS_DMASYNC_POSTREAD);
2129 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2130 uma_zfree(fl->ifl_zone, *sd_cl);
2132 if (*sd_m != NULL) {
2133 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2134 uma_zfree(zone_mbuf, *sd_m);
2138 MPASS(*sd_m == NULL);
2141 fl->ifl_m_dequeued++;
2142 fl->ifl_cl_dequeued++;
2146 for (i = 0; i < fl->ifl_size; i++) {
2147 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2148 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2152 * Reset free list values
2154 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2155 bzero(idi->idi_vaddr, idi->idi_size);
2158 /*********************************************************************
2160 * Initialize a free list and its buffers.
2162 **********************************************************************/
2164 iflib_fl_setup(iflib_fl_t fl)
2166 iflib_rxq_t rxq = fl->ifl_rxq;
2167 if_ctx_t ctx = rxq->ifr_ctx;
2168 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2171 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2173 ** Free current RX buffer structs and their mbufs
2175 iflib_fl_bufs_free(fl);
2176 /* Now replenish the mbufs */
2177 MPASS(fl->ifl_credits == 0);
2178 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2179 if (scctx->isc_rxd_buf_size[qidx] != 0)
2180 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2182 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2184 * ifl_buf_size may be a driver-supplied value, so pull it up
2185 * to the selected mbuf size.
2187 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2188 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2189 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2190 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2191 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2194 /* avoid pre-allocating zillions of clusters to an idle card
2195 * potentially speeding up attach
2197 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2198 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2199 if (min(128, fl->ifl_size) != fl->ifl_credits)
2205 MPASS(fl->ifl_ifdi != NULL);
2206 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2207 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2211 /*********************************************************************
2213 * Free receive ring data structures
2215 **********************************************************************/
2217 iflib_rx_sds_free(iflib_rxq_t rxq)
2222 if (rxq->ifr_fl != NULL) {
2223 for (i = 0; i < rxq->ifr_nfl; i++) {
2224 fl = &rxq->ifr_fl[i];
2225 if (fl->ifl_buf_tag != NULL) {
2226 if (fl->ifl_sds.ifsd_map != NULL) {
2227 for (j = 0; j < fl->ifl_size; j++) {
2230 fl->ifl_sds.ifsd_map[j],
2231 BUS_DMASYNC_POSTREAD);
2234 fl->ifl_sds.ifsd_map[j]);
2237 fl->ifl_sds.ifsd_map[j]);
2240 bus_dma_tag_destroy(fl->ifl_buf_tag);
2241 fl->ifl_buf_tag = NULL;
2243 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2244 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2245 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2246 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2247 fl->ifl_sds.ifsd_m = NULL;
2248 fl->ifl_sds.ifsd_cl = NULL;
2249 fl->ifl_sds.ifsd_ba = NULL;
2250 fl->ifl_sds.ifsd_map = NULL;
2252 free(rxq->ifr_fl, M_IFLIB);
2254 free(rxq->ifr_ifdi, M_IFLIB);
2255 rxq->ifr_ifdi = NULL;
2256 rxq->ifr_cq_cidx = 0;
2264 iflib_timer(void *arg)
2266 iflib_txq_t txq = arg;
2267 if_ctx_t ctx = txq->ift_ctx;
2268 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2269 uint64_t this_tick = ticks;
2270 uint32_t reset_on = hz / 2;
2272 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2276 ** Check on the state of the TX queue(s), this
2277 ** can be done without the lock because its RO
2278 ** and the HUNG state will be static if set.
2280 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2281 txq->ift_last_timer_tick = this_tick;
2282 IFDI_TIMER(ctx, txq->ift_id);
2283 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2284 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2285 (sctx->isc_pause_frames == 0)))
2288 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2289 ifmp_ring_is_stalled(txq->ift_br)) {
2290 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2291 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2293 txq->ift_cleaned_prev = txq->ift_cleaned;
2296 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2297 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2299 /* handle any laggards */
2300 if (txq->ift_db_pending)
2301 GROUPTASK_ENQUEUE(&txq->ift_task);
2303 sctx->isc_pause_frames = 0;
2304 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2305 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2309 device_printf(ctx->ifc_dev,
2310 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2311 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2313 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2314 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2315 iflib_admin_intr_deferred(ctx);
2320 iflib_get_mbuf_size_for(unsigned int size)
2323 if (size <= MCLBYTES)
2326 return (MJUMPAGESIZE);
2330 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2332 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2335 * XXX don't set the max_frame_size to larger
2336 * than the hardware can handle
2338 ctx->ifc_rx_mbuf_sz =
2339 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2343 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2346 return (ctx->ifc_rx_mbuf_sz);
2350 iflib_init_locked(if_ctx_t ctx)
2352 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2353 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2354 if_t ifp = ctx->ifc_ifp;
2358 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2360 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2361 IFDI_INTR_DISABLE(ctx);
2363 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2364 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2365 /* Set hardware offload abilities */
2366 if_clearhwassist(ifp);
2367 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2368 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2369 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2370 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2371 if (if_getcapenable(ifp) & IFCAP_TSO4)
2372 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2373 if (if_getcapenable(ifp) & IFCAP_TSO6)
2374 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2376 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2378 callout_stop(&txq->ift_timer);
2379 CALLOUT_UNLOCK(txq);
2380 iflib_netmap_txq_init(ctx, txq);
2384 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2385 * that drivers can use the value when setting up the hardware receive
2388 iflib_calc_rx_mbuf_sz(ctx);
2391 i = if_getdrvflags(ifp);
2394 MPASS(if_getdrvflags(ifp) == i);
2395 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2396 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2397 /* This rxq is in netmap mode. Skip normal init. */
2400 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2401 if (iflib_fl_setup(fl)) {
2402 device_printf(ctx->ifc_dev,
2403 "setting up free list %d failed - "
2404 "check cluster settings\n", j);
2410 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2411 IFDI_INTR_ENABLE(ctx);
2412 txq = ctx->ifc_txqs;
2413 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2414 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2415 txq->ift_timer.c_cpu);
2419 iflib_media_change(if_t ifp)
2421 if_ctx_t ctx = if_getsoftc(ifp);
2425 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2426 iflib_init_locked(ctx);
2432 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2434 if_ctx_t ctx = if_getsoftc(ifp);
2437 IFDI_UPDATE_ADMIN_STATUS(ctx);
2438 IFDI_MEDIA_STATUS(ctx, ifmr);
2443 iflib_stop(if_ctx_t ctx)
2445 iflib_txq_t txq = ctx->ifc_txqs;
2446 iflib_rxq_t rxq = ctx->ifc_rxqs;
2447 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2448 if_shared_ctx_t sctx = ctx->ifc_sctx;
2449 iflib_dma_info_t di;
2453 /* Tell the stack that the interface is no longer active */
2454 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2456 IFDI_INTR_DISABLE(ctx);
2461 iflib_debug_reset();
2462 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2463 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2464 /* make sure all transmitters have completed before proceeding XXX */
2467 callout_stop(&txq->ift_timer);
2468 CALLOUT_UNLOCK(txq);
2470 /* clean any enqueued buffers */
2471 iflib_ifmp_purge(txq);
2472 /* Free any existing tx buffers. */
2473 for (j = 0; j < txq->ift_size; j++) {
2474 iflib_txsd_free(ctx, txq, j);
2476 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2477 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2478 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2479 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2480 txq->ift_pullups = 0;
2481 ifmp_ring_reset_stats(txq->ift_br);
2482 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2483 bzero((void *)di->idi_vaddr, di->idi_size);
2485 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2486 /* make sure all transmitters have completed before proceeding XXX */
2488 rxq->ifr_cq_cidx = 0;
2489 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2490 bzero((void *)di->idi_vaddr, di->idi_size);
2491 /* also resets the free lists pidx/cidx */
2492 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2493 iflib_fl_bufs_free(fl);
2497 static inline caddr_t
2498 calc_next_rxd(iflib_fl_t fl, int cidx)
2502 caddr_t start, end, cur, next;
2504 nrxd = fl->ifl_size;
2505 size = fl->ifl_rxd_size;
2506 start = fl->ifl_ifdi->idi_vaddr;
2508 if (__predict_false(size == 0))
2510 cur = start + size*cidx;
2511 end = start + size*nrxd;
2512 next = CACHE_PTR_NEXT(cur);
2513 return (next < end ? next : start);
2517 prefetch_pkts(iflib_fl_t fl, int cidx)
2520 int nrxd = fl->ifl_size;
2524 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2525 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2526 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2527 next_rxd = calc_next_rxd(fl, cidx);
2529 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2530 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2531 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2532 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2533 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2534 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2535 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2536 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2539 static struct mbuf *
2540 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2541 int *pf_rv, if_rxd_info_t ri)
2547 int flid, cidx, len, next;
2550 flid = irf->irf_flid;
2551 cidx = irf->irf_idx;
2552 fl = &rxq->ifr_fl[flid];
2554 m = fl->ifl_sds.ifsd_m[cidx];
2555 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2558 fl->ifl_m_dequeued++;
2560 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2561 prefetch_pkts(fl, cidx);
2562 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2563 prefetch(&fl->ifl_sds.ifsd_map[next]);
2564 map = fl->ifl_sds.ifsd_map[cidx];
2566 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2568 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2569 irf->irf_len != 0) {
2570 payload = *sd->ifsd_cl;
2571 payload += ri->iri_pad;
2572 len = ri->iri_len - ri->iri_pad;
2573 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2574 len | PFIL_MEMPTR | PFIL_IN, NULL);
2579 * The filter ate it. Everything is recycled.
2584 case PFIL_REALLOCED:
2586 * The filter copied it. Everything is recycled.
2588 m = pfil_mem2mbuf(payload);
2593 * Filter said it was OK, so receive like
2596 fl->ifl_sds.ifsd_m[cidx] = NULL;
2602 fl->ifl_sds.ifsd_m[cidx] = NULL;
2606 if (unload && irf->irf_len != 0)
2607 bus_dmamap_unload(fl->ifl_buf_tag, map);
2608 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2609 if (__predict_false(fl->ifl_cidx == 0))
2611 bit_clear(fl->ifl_rx_bitmap, cidx);
2615 static struct mbuf *
2616 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2618 struct mbuf *m, *mh, *mt;
2620 int *pf_rv_ptr, flags, i, padlen;
2629 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2632 MPASS(*sd->ifsd_cl != NULL);
2635 * Exclude zero-length frags & frags from
2636 * packets the filter has consumed or dropped
2638 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2639 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2641 /* everything saved here */
2646 /* XXX we can save the cluster here, but not the mbuf */
2647 m_init(m, M_NOWAIT, MT_DATA, 0);
2652 flags = M_PKTHDR|M_EXT;
2654 padlen = ri->iri_pad;
2659 /* assuming padding is only on the first fragment */
2663 *sd->ifsd_cl = NULL;
2665 /* Can these two be made one ? */
2666 m_init(m, M_NOWAIT, MT_DATA, flags);
2667 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2669 * These must follow m_init and m_cljset
2671 m->m_data += padlen;
2672 ri->iri_len -= padlen;
2673 m->m_len = ri->iri_frags[i].irf_len;
2674 } while (++i < ri->iri_nfrags);
2680 * Process one software descriptor
2682 static struct mbuf *
2683 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2689 /* should I merge this back in now that the two paths are basically duplicated? */
2690 if (ri->iri_nfrags == 1 &&
2691 ri->iri_frags[0].irf_len != 0 &&
2692 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2693 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2695 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2697 if (pf_rv == PFIL_PASS) {
2698 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2699 #ifndef __NO_STRICT_ALIGNMENT
2703 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2704 m->m_len = ri->iri_frags[0].irf_len;
2707 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2710 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2713 m->m_pkthdr.len = ri->iri_len;
2714 m->m_pkthdr.rcvif = ri->iri_ifp;
2715 m->m_flags |= ri->iri_flags;
2716 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2717 m->m_pkthdr.flowid = ri->iri_flowid;
2718 M_HASHTYPE_SET(m, ri->iri_rsstype);
2719 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2720 m->m_pkthdr.csum_data = ri->iri_csum_data;
2724 #if defined(INET6) || defined(INET)
2726 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2728 CURVNET_SET(lc->ifp->if_vnet);
2730 *v6 = V_ip6_forwarding;
2733 *v4 = V_ipforwarding;
2739 * Returns true if it's possible this packet could be LROed.
2740 * if it returns false, it is guaranteed that tcp_lro_rx()
2741 * would not return zero.
2744 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2746 struct ether_header *eh;
2748 eh = mtod(m, struct ether_header *);
2749 switch (eh->ether_type) {
2751 case htons(ETHERTYPE_IPV6):
2752 return (!v6_forwarding);
2755 case htons(ETHERTYPE_IP):
2756 return (!v4_forwarding);
2764 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2770 _task_fn_rx_watchdog(void *context)
2772 iflib_rxq_t rxq = context;
2774 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2778 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2781 if_ctx_t ctx = rxq->ifr_ctx;
2782 if_shared_ctx_t sctx = ctx->ifc_sctx;
2783 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2786 struct if_rxd_info ri;
2787 int err, budget_left, rx_bytes, rx_pkts;
2790 bool v4_forwarding, v6_forwarding, lro_possible;
2794 * XXX early demux data packets so that if_input processing only handles
2795 * acks in interrupt context
2797 struct mbuf *m, *mh, *mt, *mf;
2801 lro_possible = v4_forwarding = v6_forwarding = false;
2805 rx_pkts = rx_bytes = 0;
2806 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2807 cidxp = &rxq->ifr_cq_cidx;
2809 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2810 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2811 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2812 retval |= iflib_fl_refill_all(ctx, fl);
2813 DBG_COUNTER_INC(rx_unavail);
2817 /* pfil needs the vnet to be set */
2818 CURVNET_SET_QUIET(ifp->if_vnet);
2819 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2820 if (__predict_false(!CTX_ACTIVE(ctx))) {
2821 DBG_COUNTER_INC(rx_ctx_inactive);
2825 * Reset client set fields to their default values
2828 ri.iri_qsidx = rxq->ifr_id;
2829 ri.iri_cidx = *cidxp;
2831 ri.iri_frags = rxq->ifr_frags;
2832 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2837 rx_bytes += ri.iri_len;
2838 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2839 *cidxp = ri.iri_cidx;
2840 /* Update our consumer index */
2841 /* XXX NB: shurd - check if this is still safe */
2842 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2843 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2844 /* was this only a completion queue message? */
2845 if (__predict_false(ri.iri_nfrags == 0))
2848 MPASS(ri.iri_nfrags != 0);
2849 MPASS(ri.iri_len != 0);
2851 /* will advance the cidx on the corresponding free lists */
2852 m = iflib_rxd_pkt_get(rxq, &ri);
2855 if (avail == 0 && budget_left)
2856 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2858 if (__predict_false(m == NULL))
2861 /* imm_pkt: -- cxgb */
2870 /* make sure that we can refill faster than drain */
2871 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2872 retval |= iflib_fl_refill_all(ctx, fl);
2874 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2876 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2878 while (mh != NULL) {
2881 m->m_nextpkt = NULL;
2882 #ifndef __NO_STRICT_ALIGNMENT
2883 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2886 rx_bytes += m->m_pkthdr.len;
2888 #if defined(INET6) || defined(INET)
2890 if (!lro_possible) {
2891 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2892 if (lro_possible && mf != NULL) {
2893 ifp->if_input(ifp, mf);
2894 DBG_COUNTER_INC(rx_if_input);
2898 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2899 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2900 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2906 ifp->if_input(ifp, m);
2907 DBG_COUNTER_INC(rx_if_input);
2918 ifp->if_input(ifp, mf);
2919 DBG_COUNTER_INC(rx_if_input);
2922 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2923 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2926 * Flush any outstanding LRO work
2928 #if defined(INET6) || defined(INET)
2929 tcp_lro_flush_all(&rxq->ifr_lc);
2931 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2932 retval |= IFLIB_RXEOF_MORE;
2936 ctx->ifc_flags |= IFC_DO_RESET;
2937 iflib_admin_intr_deferred(ctx);
2942 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2943 static inline qidx_t
2944 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2946 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2947 qidx_t minthresh = txq->ift_size / 8;
2948 if (in_use > 4*minthresh)
2949 return (notify_count);
2950 if (in_use > 2*minthresh)
2951 return (notify_count >> 1);
2952 if (in_use > minthresh)
2953 return (notify_count >> 3);
2957 static inline qidx_t
2958 txq_max_rs_deferred(iflib_txq_t txq)
2960 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2961 qidx_t minthresh = txq->ift_size / 8;
2962 if (txq->ift_in_use > 4*minthresh)
2963 return (notify_count);
2964 if (txq->ift_in_use > 2*minthresh)
2965 return (notify_count >> 1);
2966 if (txq->ift_in_use > minthresh)
2967 return (notify_count >> 2);
2971 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2972 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2974 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2975 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2976 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2978 /* forward compatibility for cxgb */
2979 #define FIRST_QSET(ctx) 0
2980 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2981 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2982 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2983 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2985 /* XXX we should be setting this to something other than zero */
2986 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2987 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2988 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2991 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2997 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2998 if (ring || txq->ift_db_pending >= max) {
2999 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3000 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3001 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3002 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3003 txq->ift_db_pending = txq->ift_npending = 0;
3011 print_pkt(if_pkt_info_t pi)
3013 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3014 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3015 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3016 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3017 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3018 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3022 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3023 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3024 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3025 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3028 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3030 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3031 struct ether_vlan_header *eh;
3035 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3036 M_WRITABLE(m) == 0) {
3037 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3041 DBG_COUNTER_INC(tx_frees);
3047 * Determine where frame payload starts.
3048 * Jump over vlan headers if already present,
3049 * helpful for QinQ too.
3051 if (__predict_false(m->m_len < sizeof(*eh))) {
3053 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3056 eh = mtod(m, struct ether_vlan_header *);
3057 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3058 pi->ipi_etype = ntohs(eh->evl_proto);
3059 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3061 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3062 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3065 switch (pi->ipi_etype) {
3070 struct ip *ip = NULL;
3071 struct tcphdr *th = NULL;
3074 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3075 if (__predict_false(m->m_len < minthlen)) {
3077 * if this code bloat is causing too much of a hit
3078 * move it to a separate function and mark it noinline
3080 if (m->m_len == pi->ipi_ehdrlen) {
3083 if (n->m_len >= sizeof(*ip)) {
3084 ip = (struct ip *)n->m_data;
3085 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3086 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3089 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3091 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3095 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3097 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3098 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3099 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3102 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3103 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3104 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3106 pi->ipi_ip_hlen = ip->ip_hl << 2;
3107 pi->ipi_ipproto = ip->ip_p;
3108 pi->ipi_flags |= IPI_TX_IPV4;
3110 /* TCP checksum offload may require TCP header length */
3111 if (IS_TX_OFFLOAD4(pi)) {
3112 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3113 if (__predict_false(th == NULL)) {
3115 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3117 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3119 pi->ipi_tcp_hflags = th->th_flags;
3120 pi->ipi_tcp_hlen = th->th_off << 2;
3121 pi->ipi_tcp_seq = th->th_seq;
3124 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3127 * TSO always requires hardware checksum offload.
3129 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3130 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3131 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3132 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3133 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3135 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3139 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3146 case ETHERTYPE_IPV6:
3148 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3150 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3152 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3154 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3157 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3159 /* XXX-BZ this will go badly in case of ext hdrs. */
3160 pi->ipi_ipproto = ip6->ip6_nxt;
3161 pi->ipi_flags |= IPI_TX_IPV6;
3163 /* TCP checksum offload may require TCP header length */
3164 if (IS_TX_OFFLOAD6(pi)) {
3165 if (pi->ipi_ipproto == IPPROTO_TCP) {
3166 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3168 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3171 pi->ipi_tcp_hflags = th->th_flags;
3172 pi->ipi_tcp_hlen = th->th_off << 2;
3173 pi->ipi_tcp_seq = th->th_seq;
3176 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3179 * TSO always requires hardware checksum offload.
3181 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3182 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3183 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3190 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3191 pi->ipi_ip_hlen = 0;
3200 * If dodgy hardware rejects the scatter gather chain we've handed it
3201 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3204 static __noinline struct mbuf *
3205 iflib_remove_mbuf(iflib_txq_t txq)
3208 struct mbuf *m, **ifsd_m;
3210 ifsd_m = txq->ift_sds.ifsd_m;
3211 ntxd = txq->ift_size;
3212 pidx = txq->ift_pidx & (ntxd - 1);
3213 ifsd_m = txq->ift_sds.ifsd_m;
3215 ifsd_m[pidx] = NULL;
3216 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3217 if (txq->ift_sds.ifsd_tso_map != NULL)
3218 bus_dmamap_unload(txq->ift_tso_buf_tag,
3219 txq->ift_sds.ifsd_tso_map[pidx]);
3221 txq->ift_dequeued++;
3226 static inline caddr_t
3227 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3231 caddr_t start, end, cur, next;
3233 ntxd = txq->ift_size;
3234 size = txq->ift_txd_size[qid];
3235 start = txq->ift_ifdi[qid].idi_vaddr;
3237 if (__predict_false(size == 0))
3239 cur = start + size*cidx;
3240 end = start + size*ntxd;
3241 next = CACHE_PTR_NEXT(cur);
3242 return (next < end ? next : start);
3246 * Pad an mbuf to ensure a minimum ethernet frame size.
3247 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3249 static __noinline int
3250 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3253 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3254 * and ARP message is the smallest common payload I can think of
3256 static char pad[18]; /* just zeros */
3258 struct mbuf *new_head;
3260 if (!M_WRITABLE(*m_head)) {
3261 new_head = m_dup(*m_head, M_NOWAIT);
3262 if (new_head == NULL) {
3264 device_printf(dev, "cannot pad short frame, m_dup() failed");
3265 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3266 DBG_COUNTER_INC(tx_frees);
3273 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3274 n > 0; n -= sizeof(pad))
3275 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3280 device_printf(dev, "cannot pad short frame\n");
3281 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3282 DBG_COUNTER_INC(tx_frees);
3290 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3293 if_shared_ctx_t sctx;
3294 if_softc_ctx_t scctx;
3295 bus_dma_tag_t buf_tag;
3296 bus_dma_segment_t *segs;
3297 struct mbuf *m_head, **ifsd_m;
3300 struct if_pkt_info pi;
3302 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3305 sctx = ctx->ifc_sctx;
3306 scctx = &ctx->ifc_softc_ctx;
3307 segs = txq->ift_segs;
3308 ntxd = txq->ift_size;
3313 * If we're doing TSO the next descriptor to clean may be quite far ahead
3315 cidx = txq->ift_cidx;
3316 pidx = txq->ift_pidx;
3317 if (ctx->ifc_flags & IFC_PREFETCH) {
3318 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3319 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3320 next_txd = calc_next_txd(txq, cidx, 0);
3324 /* prefetch the next cache line of mbuf pointers and flags */
3325 prefetch(&txq->ift_sds.ifsd_m[next]);
3326 prefetch(&txq->ift_sds.ifsd_map[next]);
3327 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3329 map = txq->ift_sds.ifsd_map[pidx];
3330 ifsd_m = txq->ift_sds.ifsd_m;
3332 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3333 buf_tag = txq->ift_tso_buf_tag;
3334 max_segs = scctx->isc_tx_tso_segments_max;
3335 map = txq->ift_sds.ifsd_tso_map[pidx];
3336 MPASS(buf_tag != NULL);
3337 MPASS(max_segs > 0);
3339 buf_tag = txq->ift_buf_tag;
3340 max_segs = scctx->isc_tx_nsegments;
3341 map = txq->ift_sds.ifsd_map[pidx];
3343 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3344 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3345 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3347 DBG_COUNTER_INC(encap_txd_encap_fail);
3354 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3356 pi.ipi_qsidx = txq->ift_id;
3357 pi.ipi_len = m_head->m_pkthdr.len;
3358 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3359 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3361 /* deliberate bitwise OR to make one condition */
3362 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3363 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3364 DBG_COUNTER_INC(encap_txd_encap_fail);
3371 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3374 if (__predict_false(err)) {
3377 /* try collapse once and defrag once */
3379 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3380 /* try defrag if collapsing fails */
3385 txq->ift_mbuf_defrag++;
3386 m_head = m_defrag(*m_headp, M_NOWAIT);
3389 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3390 * failed to map an mbuf that was run through m_defrag
3393 if (__predict_false(m_head == NULL || remap > 1))
3400 txq->ift_no_tx_dma_setup++;
3403 txq->ift_no_tx_dma_setup++;
3405 DBG_COUNTER_INC(tx_frees);
3409 txq->ift_map_failed++;
3410 DBG_COUNTER_INC(encap_load_mbuf_fail);
3411 DBG_COUNTER_INC(encap_txd_encap_fail);
3414 ifsd_m[pidx] = m_head;
3416 * XXX assumes a 1 to 1 relationship between segments and
3417 * descriptors - this does not hold true on all drivers, e.g.
3420 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3421 txq->ift_no_desc_avail++;
3422 bus_dmamap_unload(buf_tag, map);
3423 DBG_COUNTER_INC(encap_txq_avail_fail);
3424 DBG_COUNTER_INC(encap_txd_encap_fail);
3425 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3426 GROUPTASK_ENQUEUE(&txq->ift_task);
3430 * On Intel cards we can greatly reduce the number of TX interrupts
3431 * we see by only setting report status on every Nth descriptor.
3432 * However, this also means that the driver will need to keep track
3433 * of the descriptors that RS was set on to check them for the DD bit.
3435 txq->ift_rs_pending += nsegs + 1;
3436 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3437 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3438 pi.ipi_flags |= IPI_TX_INTR;
3439 txq->ift_rs_pending = 0;
3443 pi.ipi_nsegs = nsegs;
3445 MPASS(pidx >= 0 && pidx < txq->ift_size);
3449 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3450 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3451 DBG_COUNTER_INC(tx_encap);
3452 MPASS(pi.ipi_new_pidx < txq->ift_size);
3454 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3455 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3456 ndesc += txq->ift_size;
3460 * drivers can need as many as
3463 MPASS(ndesc <= pi.ipi_nsegs + 2);
3464 MPASS(pi.ipi_new_pidx != pidx);
3466 txq->ift_in_use += ndesc;
3469 * We update the last software descriptor again here because there may
3470 * be a sentinel and/or there may be more mbufs than segments
3472 txq->ift_pidx = pi.ipi_new_pidx;
3473 txq->ift_npending += pi.ipi_ndescs;
3475 *m_headp = m_head = iflib_remove_mbuf(txq);
3477 txq->ift_txd_encap_efbig++;
3486 * err can't possibly be non-zero here, so we don't neet to test it
3487 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3492 txq->ift_mbuf_defrag_failed++;
3493 txq->ift_map_failed++;
3495 DBG_COUNTER_INC(tx_frees);
3497 DBG_COUNTER_INC(encap_txd_encap_fail);
3502 iflib_tx_desc_free(iflib_txq_t txq, int n)
3504 uint32_t qsize, cidx, mask, gen;
3505 struct mbuf *m, **ifsd_m;
3508 cidx = txq->ift_cidx;
3510 qsize = txq->ift_size;
3512 ifsd_m = txq->ift_sds.ifsd_m;
3513 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3517 prefetch(ifsd_m[(cidx + 3) & mask]);
3518 prefetch(ifsd_m[(cidx + 4) & mask]);
3520 if ((m = ifsd_m[cidx]) != NULL) {
3521 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3522 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3523 bus_dmamap_sync(txq->ift_tso_buf_tag,
3524 txq->ift_sds.ifsd_tso_map[cidx],
3525 BUS_DMASYNC_POSTWRITE);
3526 bus_dmamap_unload(txq->ift_tso_buf_tag,
3527 txq->ift_sds.ifsd_tso_map[cidx]);
3529 bus_dmamap_sync(txq->ift_buf_tag,
3530 txq->ift_sds.ifsd_map[cidx],
3531 BUS_DMASYNC_POSTWRITE);
3532 bus_dmamap_unload(txq->ift_buf_tag,
3533 txq->ift_sds.ifsd_map[cidx]);
3535 /* XXX we don't support any drivers that batch packets yet */
3536 MPASS(m->m_nextpkt == NULL);
3538 ifsd_m[cidx] = NULL;
3540 txq->ift_dequeued++;
3542 DBG_COUNTER_INC(tx_frees);
3544 if (__predict_false(++cidx == qsize)) {
3549 txq->ift_cidx = cidx;
3554 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3557 if_ctx_t ctx = txq->ift_ctx;
3559 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3560 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3563 * Need a rate-limiting check so that this isn't called every time
3565 iflib_tx_credits_update(ctx, txq);
3566 reclaim = DESC_RECLAIMABLE(txq);
3568 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3570 if (iflib_verbose_debug) {
3571 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3572 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3579 iflib_tx_desc_free(txq, reclaim);
3580 txq->ift_cleaned += reclaim;
3581 txq->ift_in_use -= reclaim;
3586 static struct mbuf **
3587 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3590 struct mbuf **items;
3593 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3594 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3596 prefetch(items[(cidx + offset) & (size-1)]);
3597 if (remaining > 1) {
3598 prefetch2cachelines(&items[next]);
3599 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3600 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3601 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3603 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3607 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3610 ifmp_ring_check_drainage(txq->ift_br, budget);
3614 iflib_txq_can_drain(struct ifmp_ring *r)
3616 iflib_txq_t txq = r->cookie;
3617 if_ctx_t ctx = txq->ift_ctx;
3619 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3621 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3622 BUS_DMASYNC_POSTREAD);
3623 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3628 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3630 iflib_txq_t txq = r->cookie;
3631 if_ctx_t ctx = txq->ift_ctx;
3632 if_t ifp = ctx->ifc_ifp;
3633 struct mbuf *m, **mp;
3634 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3635 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3636 bool do_prefetch, rang, ring;
3638 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3639 !LINK_ACTIVE(ctx))) {
3640 DBG_COUNTER_INC(txq_drain_notready);
3643 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3644 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3645 avail = IDXDIFF(pidx, cidx, r->size);
3646 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3647 DBG_COUNTER_INC(txq_drain_flushing);
3648 for (i = 0; i < avail; i++) {
3649 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3650 m_free(r->items[(cidx + i) & (r->size-1)]);
3651 r->items[(cidx + i) & (r->size-1)] = NULL;
3656 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3657 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3659 callout_stop(&txq->ift_timer);
3660 CALLOUT_UNLOCK(txq);
3661 DBG_COUNTER_INC(txq_drain_oactive);
3665 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3666 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3667 count = MIN(avail, TX_BATCH_SIZE);
3669 if (iflib_verbose_debug)
3670 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3671 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3673 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3674 txq_avail = TXQ_AVAIL(txq);
3676 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3677 int rem = do_prefetch ? count - i : 0;
3679 mp = _ring_peek_one(r, cidx, i, rem);
3680 MPASS(mp != NULL && *mp != NULL);
3681 if (__predict_false(*mp == (struct mbuf *)txq)) {
3685 in_use_prev = txq->ift_in_use;
3686 err = iflib_encap(txq, mp);
3687 if (__predict_false(err)) {
3688 /* no room - bail out */
3692 /* we can't send this packet - skip it */
3698 DBG_COUNTER_INC(tx_sent);
3699 bytes_sent += m->m_pkthdr.len;
3700 mcast_sent += !!(m->m_flags & M_MCAST);
3701 txq_avail = TXQ_AVAIL(txq);
3703 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3704 ETHER_BPF_MTAP(ifp, m);
3705 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3707 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3710 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3711 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3712 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3713 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3714 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3716 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3718 if (iflib_verbose_debug)
3719 printf("consumed=%d\n", consumed);
3725 iflib_txq_drain_always(struct ifmp_ring *r)
3731 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3739 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3741 callout_stop(&txq->ift_timer);
3742 CALLOUT_UNLOCK(txq);
3744 avail = IDXDIFF(pidx, cidx, r->size);
3745 for (i = 0; i < avail; i++) {
3746 mp = _ring_peek_one(r, cidx, i, avail - i);
3747 if (__predict_false(*mp == (struct mbuf *)txq))
3750 DBG_COUNTER_INC(tx_frees);
3752 MPASS(ifmp_ring_is_stalled(r) == 0);
3757 iflib_ifmp_purge(iflib_txq_t txq)
3759 struct ifmp_ring *r;
3762 r->drain = iflib_txq_drain_free;
3763 r->can_drain = iflib_txq_drain_always;
3765 ifmp_ring_check_drainage(r, r->size);
3767 r->drain = iflib_txq_drain;
3768 r->can_drain = iflib_txq_can_drain;
3772 _task_fn_tx(void *context)
3774 iflib_txq_t txq = context;
3775 if_ctx_t ctx = txq->ift_ctx;
3776 if_t ifp = ctx->ifc_ifp;
3777 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3779 #ifdef IFLIB_DIAGNOSTICS
3780 txq->ift_cpu_exec_count[curcpu]++;
3782 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3785 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3786 netmap_tx_irq(ifp, txq->ift_id))
3790 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3791 iflib_altq_if_start(ifp);
3793 if (txq->ift_db_pending)
3794 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3796 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3798 * When abdicating, we always need to check drainage, not just when we don't enqueue
3801 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3805 if (ctx->ifc_flags & IFC_LEGACY)
3806 IFDI_INTR_ENABLE(ctx);
3808 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3812 _task_fn_rx(void *context)
3814 iflib_rxq_t rxq = context;
3815 if_ctx_t ctx = rxq->ifr_ctx;
3823 #ifdef IFLIB_DIAGNOSTICS
3824 rxq->ifr_cpu_exec_count[curcpu]++;
3826 DBG_COUNTER_INC(task_fn_rxs);
3827 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3830 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3831 if (nmirq != NM_IRQ_PASS) {
3832 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3836 budget = ctx->ifc_sysctl_rx_budget;
3838 budget = 16; /* XXX */
3839 more = iflib_rxeof(rxq, budget);
3843 if ((more & IFLIB_RXEOF_MORE) == 0) {
3844 if (ctx->ifc_flags & IFC_LEGACY)
3845 IFDI_INTR_ENABLE(ctx);
3847 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3848 DBG_COUNTER_INC(rx_intr_enables);
3850 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3853 if (more & IFLIB_RXEOF_MORE)
3854 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3855 else if (more & IFLIB_RXEOF_EMPTY)
3856 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3860 _task_fn_admin(void *context)
3862 if_ctx_t ctx = context;
3863 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3866 bool oactive, running, do_reset, do_watchdog, in_detach;
3867 uint32_t reset_on = hz / 2;
3870 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3871 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3872 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3873 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3874 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3875 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3878 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3884 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3886 callout_stop(&txq->ift_timer);
3887 CALLOUT_UNLOCK(txq);
3890 ctx->ifc_watchdog_events++;
3891 IFDI_WATCHDOG_RESET(ctx);
3893 IFDI_UPDATE_ADMIN_STATUS(ctx);
3894 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3897 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3898 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3900 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3902 IFDI_LINK_INTR_ENABLE(ctx);
3904 iflib_if_init_locked(ctx);
3907 if (LINK_ACTIVE(ctx) == 0)
3909 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3910 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3915 _task_fn_iov(void *context)
3917 if_ctx_t ctx = context;
3919 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3920 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3924 IFDI_VFLR_HANDLE(ctx);
3929 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3932 if_int_delay_info_t info;
3935 info = (if_int_delay_info_t)arg1;
3936 ctx = info->iidi_ctx;
3937 info->iidi_req = req;
3938 info->iidi_oidp = oidp;
3940 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3945 /*********************************************************************
3949 **********************************************************************/
3952 iflib_if_init_locked(if_ctx_t ctx)
3955 iflib_init_locked(ctx);
3960 iflib_if_init(void *arg)
3965 iflib_if_init_locked(ctx);
3970 iflib_if_transmit(if_t ifp, struct mbuf *m)
3972 if_ctx_t ctx = if_getsoftc(ifp);
3976 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3978 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3979 DBG_COUNTER_INC(tx_frees);
3984 MPASS(m->m_nextpkt == NULL);
3985 /* ALTQ-enabled interfaces always use queue 0. */
3987 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3988 qidx = QIDX(ctx, m);
3990 * XXX calculate buf_ring based on flowid (divvy up bits?)
3992 txq = &ctx->ifc_txqs[qidx];
3994 #ifdef DRIVER_BACKPRESSURE
3995 if (txq->ift_closed) {
3997 next = m->m_nextpkt;
3998 m->m_nextpkt = NULL;
4000 DBG_COUNTER_INC(tx_frees);
4012 next = next->m_nextpkt;
4013 } while (next != NULL);
4015 if (count > nitems(marr))
4016 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4017 /* XXX check nextpkt */
4019 /* XXX simplify for now */
4020 DBG_COUNTER_INC(tx_frees);
4023 for (next = m, i = 0; next != NULL; i++) {
4025 next = next->m_nextpkt;
4026 mp[i]->m_nextpkt = NULL;
4029 DBG_COUNTER_INC(tx_seen);
4030 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4033 GROUPTASK_ENQUEUE(&txq->ift_task);
4036 GROUPTASK_ENQUEUE(&txq->ift_task);
4037 /* support forthcoming later */
4038 #ifdef DRIVER_BACKPRESSURE
4039 txq->ift_closed = TRUE;
4041 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4043 DBG_COUNTER_INC(tx_frees);
4051 * The overall approach to integrating iflib with ALTQ is to continue to use
4052 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4053 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4054 * is redundant/unnecessary, but doing so minimizes the amount of
4055 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4056 * redundantly queueing to an intermediate mp_ring is swamped by the
4057 * performance limitations inherent in using ALTQ.
4059 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4060 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4061 * given interface. If ALTQ is enabled for an interface, then all
4062 * transmitted packets for that interface will be submitted to the ALTQ
4063 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4064 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4065 * update stats that the iflib machinery handles, and which is sensitve to
4066 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4067 * will be installed as the start routine for use by ALTQ facilities that
4068 * need to trigger queue drains on a scheduled basis.
4072 iflib_altq_if_start(if_t ifp)
4074 struct ifaltq *ifq = &ifp->if_snd;
4078 IFQ_DEQUEUE_NOLOCK(ifq, m);
4080 iflib_if_transmit(ifp, m);
4081 IFQ_DEQUEUE_NOLOCK(ifq, m);
4087 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4091 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4092 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4094 iflib_altq_if_start(ifp);
4096 err = iflib_if_transmit(ifp, m);
4103 iflib_if_qflush(if_t ifp)
4105 if_ctx_t ctx = if_getsoftc(ifp);
4106 iflib_txq_t txq = ctx->ifc_txqs;
4110 ctx->ifc_flags |= IFC_QFLUSH;
4112 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4113 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4114 iflib_txq_check_drain(txq, 0);
4116 ctx->ifc_flags &= ~IFC_QFLUSH;
4120 * When ALTQ is enabled, this will also take care of purging the
4127 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4128 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4129 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4130 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4133 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4135 if_ctx_t ctx = if_getsoftc(ifp);
4136 struct ifreq *ifr = (struct ifreq *)data;
4137 #if defined(INET) || defined(INET6)
4138 struct ifaddr *ifa = (struct ifaddr *)data;
4140 bool avoid_reset = false;
4141 int err = 0, reinit = 0, bits;
4146 if (ifa->ifa_addr->sa_family == AF_INET)
4150 if (ifa->ifa_addr->sa_family == AF_INET6)
4154 ** Calling init results in link renegotiation,
4155 ** so we avoid doing it when possible.
4158 if_setflagbits(ifp, IFF_UP,0);
4159 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4162 if (!(if_getflags(ifp) & IFF_NOARP))
4163 arp_ifinit(ifp, ifa);
4166 err = ether_ioctl(ifp, command, data);
4170 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4174 bits = if_getdrvflags(ifp);
4175 /* stop the driver and free any clusters before proceeding */
4178 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4180 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4181 ctx->ifc_flags |= IFC_MULTISEG;
4183 ctx->ifc_flags &= ~IFC_MULTISEG;
4185 err = if_setmtu(ifp, ifr->ifr_mtu);
4187 iflib_init_locked(ctx);
4189 if_setdrvflags(ifp, bits);
4195 if (if_getflags(ifp) & IFF_UP) {
4196 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4197 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4198 (IFF_PROMISC | IFF_ALLMULTI)) {
4200 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4205 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4208 ctx->ifc_if_flags = if_getflags(ifp);
4213 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4215 IFDI_INTR_DISABLE(ctx);
4216 IFDI_MULTI_SET(ctx);
4217 IFDI_INTR_ENABLE(ctx);
4223 IFDI_MEDIA_SET(ctx);
4228 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4232 struct ifi2creq i2c;
4234 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4237 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4241 if (i2c.len > sizeof(i2c.data)) {
4246 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4247 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4253 int mask, setmask, oldmask;
4255 oldmask = if_getcapenable(ifp);
4256 mask = ifr->ifr_reqcap ^ oldmask;
4257 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4260 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4262 setmask |= (mask & IFCAP_FLAGS);
4263 setmask |= (mask & IFCAP_WOL);
4266 * If any RX csum has changed, change all the ones that
4267 * are supported by the driver.
4269 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4270 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4271 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4275 * want to ensure that traffic has stopped before we change any of the flags
4279 bits = if_getdrvflags(ifp);
4280 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4283 if_togglecapenable(ifp, setmask);
4285 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4286 iflib_init_locked(ctx);
4288 if_setdrvflags(ifp, bits);
4295 case SIOCGPRIVATE_0:
4299 err = IFDI_PRIV_IOCTL(ctx, command, data);
4303 err = ether_ioctl(ifp, command, data);
4312 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4314 if_ctx_t ctx = if_getsoftc(ifp);
4316 return (IFDI_GET_COUNTER(ctx, cnt));
4319 /*********************************************************************
4321 * OTHER FUNCTIONS EXPORTED TO THE STACK
4323 **********************************************************************/
4326 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4328 if_ctx_t ctx = if_getsoftc(ifp);
4330 if ((void *)ctx != arg)
4333 if ((vtag == 0) || (vtag > 4095))
4336 if (iflib_in_detach(ctx))
4340 /* Driver may need all untagged packets to be flushed */
4341 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4343 IFDI_VLAN_REGISTER(ctx, vtag);
4344 /* Re-init to load the changes, if required */
4345 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4346 iflib_init_locked(ctx);
4351 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4353 if_ctx_t ctx = if_getsoftc(ifp);
4355 if ((void *)ctx != arg)
4358 if ((vtag == 0) || (vtag > 4095))
4362 /* Driver may need all tagged packets to be flushed */
4363 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4365 IFDI_VLAN_UNREGISTER(ctx, vtag);
4366 /* Re-init to load the changes, if required */
4367 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4368 iflib_init_locked(ctx);
4373 iflib_led_func(void *arg, int onoff)
4378 IFDI_LED_FUNC(ctx, onoff);
4382 /*********************************************************************
4384 * BUS FUNCTION DEFINITIONS
4386 **********************************************************************/
4389 iflib_device_probe(device_t dev)
4391 const pci_vendor_info_t *ent;
4392 if_shared_ctx_t sctx;
4393 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4394 uint16_t pci_vendor_id;
4396 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4399 pci_vendor_id = pci_get_vendor(dev);
4400 pci_device_id = pci_get_device(dev);
4401 pci_subvendor_id = pci_get_subvendor(dev);
4402 pci_subdevice_id = pci_get_subdevice(dev);
4403 pci_rev_id = pci_get_revid(dev);
4404 if (sctx->isc_parse_devinfo != NULL)
4405 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4407 ent = sctx->isc_vendor_info;
4408 while (ent->pvi_vendor_id != 0) {
4409 if (pci_vendor_id != ent->pvi_vendor_id) {
4413 if ((pci_device_id == ent->pvi_device_id) &&
4414 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4415 (ent->pvi_subvendor_id == 0)) &&
4416 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4417 (ent->pvi_subdevice_id == 0)) &&
4418 ((pci_rev_id == ent->pvi_rev_id) ||
4419 (ent->pvi_rev_id == 0))) {
4421 device_set_desc_copy(dev, ent->pvi_name);
4422 /* this needs to be changed to zero if the bus probing code
4423 * ever stops re-probing on best match because the sctx
4424 * may have its values over written by register calls
4425 * in subsequent probes
4427 return (BUS_PROBE_DEFAULT);
4435 iflib_device_probe_vendor(device_t dev)
4439 probe = iflib_device_probe(dev);
4440 if (probe == BUS_PROBE_DEFAULT)
4441 return (BUS_PROBE_VENDOR);
4447 iflib_reset_qvalues(if_ctx_t ctx)
4449 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4450 if_shared_ctx_t sctx = ctx->ifc_sctx;
4451 device_t dev = ctx->ifc_dev;
4454 if (ctx->ifc_sysctl_ntxqs != 0)
4455 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4456 if (ctx->ifc_sysctl_nrxqs != 0)
4457 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4459 for (i = 0; i < sctx->isc_ntxqs; i++) {
4460 if (ctx->ifc_sysctl_ntxds[i] != 0)
4461 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4463 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4466 for (i = 0; i < sctx->isc_nrxqs; i++) {
4467 if (ctx->ifc_sysctl_nrxds[i] != 0)
4468 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4470 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4473 for (i = 0; i < sctx->isc_nrxqs; i++) {
4474 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4475 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4476 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4477 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4479 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4480 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4481 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4482 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4484 if (!powerof2(scctx->isc_nrxd[i])) {
4485 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4486 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4487 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4491 for (i = 0; i < sctx->isc_ntxqs; i++) {
4492 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4493 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4494 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4495 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4497 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4498 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4499 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4500 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4502 if (!powerof2(scctx->isc_ntxd[i])) {
4503 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4504 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4505 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4511 iflib_add_pfil(if_ctx_t ctx)
4513 struct pfil_head *pfil;
4514 struct pfil_head_args pa;
4518 pa.pa_version = PFIL_VERSION;
4519 pa.pa_flags = PFIL_IN;
4520 pa.pa_type = PFIL_TYPE_ETHERNET;
4521 pa.pa_headname = ctx->ifc_ifp->if_xname;
4522 pfil = pfil_head_register(&pa);
4524 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4530 iflib_rem_pfil(if_ctx_t ctx)
4532 struct pfil_head *pfil;
4536 rxq = ctx->ifc_rxqs;
4538 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4541 pfil_head_unregister(pfil);
4545 get_ctx_core_offset(if_ctx_t ctx)
4547 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4548 struct cpu_offset *op;
4550 uint16_t ret = ctx->ifc_sysctl_core_offset;
4552 if (ret != CORE_OFFSET_UNSPECIFIED)
4555 if (ctx->ifc_sysctl_separate_txrx)
4556 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4558 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4560 mtx_lock(&cpu_offset_mtx);
4561 SLIST_FOREACH(op, &cpu_offsets, entries) {
4562 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4565 MPASS(op->refcount < UINT_MAX);
4570 if (ret == CORE_OFFSET_UNSPECIFIED) {
4572 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4575 device_printf(ctx->ifc_dev,
4576 "allocation for cpu offset failed.\n");
4580 CPU_COPY(&ctx->ifc_cpus, &op->set);
4581 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4584 mtx_unlock(&cpu_offset_mtx);
4590 unref_ctx_core_offset(if_ctx_t ctx)
4592 struct cpu_offset *op, *top;
4594 mtx_lock(&cpu_offset_mtx);
4595 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4596 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4597 MPASS(op->refcount > 0);
4599 if (op->refcount == 0) {
4600 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4606 mtx_unlock(&cpu_offset_mtx);
4610 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4614 if_softc_ctx_t scctx;
4615 kobjop_desc_t kobj_desc;
4616 kobj_method_t *kobj_method;
4618 int num_txd, num_rxd;
4620 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4623 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4624 device_set_softc(dev, ctx);
4625 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4628 ctx->ifc_sctx = sctx;
4630 ctx->ifc_softc = sc;
4632 if ((err = iflib_register(ctx)) != 0) {
4633 device_printf(dev, "iflib_register failed %d\n", err);
4636 iflib_add_device_sysctl_pre(ctx);
4638 scctx = &ctx->ifc_softc_ctx;
4641 iflib_reset_qvalues(ctx);
4643 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4644 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4647 _iflib_pre_assert(scctx);
4648 ctx->ifc_txrx = *scctx->isc_txrx;
4650 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4651 ctx->ifc_mediap = scctx->isc_media;
4654 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4655 MPASS(scctx->isc_tx_csum_flags);
4658 if_setcapabilities(ifp,
4659 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4660 if_setcapenable(ifp,
4661 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4663 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4664 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4665 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4666 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4668 num_txd = iflib_num_tx_descs(ctx);
4669 num_rxd = iflib_num_rx_descs(ctx);
4671 /* XXX change for per-queue sizes */
4672 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4675 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4676 scctx->isc_tx_nsegments = max(1, num_txd /
4677 MAX_SINGLE_PACKET_FRACTION);
4678 if (scctx->isc_tx_tso_segments_max > num_txd /
4679 MAX_SINGLE_PACKET_FRACTION)
4680 scctx->isc_tx_tso_segments_max = max(1,
4681 num_txd / MAX_SINGLE_PACKET_FRACTION);
4683 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4684 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4686 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4689 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4692 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4693 * into account. In the worst case, each of these calls will
4694 * add another mbuf and, thus, the requirement for another DMA
4695 * segment. So for best performance, it doesn't make sense to
4696 * advertize a maximum of TSO segments that typically will
4697 * require defragmentation in iflib_encap().
4699 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4700 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4702 if (scctx->isc_rss_table_size == 0)
4703 scctx->isc_rss_table_size = 64;
4704 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4706 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4707 /* XXX format name */
4708 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4709 NULL, NULL, "admin");
4711 /* Set up cpu set. If it fails, use the set of all CPUs. */
4712 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4713 device_printf(dev, "Unable to fetch CPU list\n");
4714 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4716 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4719 ** Now set up MSI or MSI-X, should return us the number of supported
4720 ** vectors (will be 1 for a legacy interrupt and MSI).
4722 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4723 msix = scctx->isc_vectors;
4724 } else if (scctx->isc_msix_bar != 0)
4726 * The simple fact that isc_msix_bar is not 0 does not mean we
4727 * we have a good value there that is known to work.
4729 msix = iflib_msix_init(ctx);
4731 scctx->isc_vectors = 1;
4732 scctx->isc_ntxqsets = 1;
4733 scctx->isc_nrxqsets = 1;
4734 scctx->isc_intr = IFLIB_INTR_LEGACY;
4737 /* Get memory for the station queues */
4738 if ((err = iflib_queues_alloc(ctx))) {
4739 device_printf(dev, "Unable to allocate queue memory\n");
4740 goto fail_intr_free;
4743 if ((err = iflib_qset_structures_setup(ctx)))
4747 * Now that we know how many queues there are, get the core offset.
4749 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4753 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4754 * aren't the default NULL implementation.
4756 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4757 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4759 if (kobj_method == &kobj_desc->deflt) {
4761 "MSI-X requires ifdi_rx_queue_intr_enable method");
4765 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4766 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4768 if (kobj_method == &kobj_desc->deflt) {
4770 "MSI-X requires ifdi_tx_queue_intr_enable method");
4776 * Assign the MSI-X vectors.
4777 * Note that the default NULL ifdi_msix_intr_assign method will
4780 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4782 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4786 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4788 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4792 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4793 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4798 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4800 goto fail_intr_free;
4803 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4805 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4806 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4811 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4812 * This must appear after the call to ether_ifattach() because
4813 * ether_ifattach() sets if_hdrlen to the default value.
4815 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4816 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4818 if ((err = iflib_netmap_attach(ctx))) {
4819 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4824 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4826 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4827 iflib_add_device_sysctl_post(ctx);
4828 iflib_add_pfil(ctx);
4829 ctx->ifc_flags |= IFC_INIT_DONE;
4835 ether_ifdetach(ctx->ifc_ifp);
4837 iflib_free_intr_mem(ctx);
4839 iflib_tx_structures_free(ctx);
4840 iflib_rx_structures_free(ctx);
4841 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4845 iflib_deregister(ctx);
4847 device_set_softc(ctx->ifc_dev, NULL);
4848 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4849 free(ctx->ifc_softc, M_IFLIB);
4855 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4856 struct iflib_cloneattach_ctx *clctx)
4858 int num_txd, num_rxd;
4862 if_softc_ctx_t scctx;
4866 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4867 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4868 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4869 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4870 ctx->ifc_flags |= IFC_PSEUDO;
4872 ctx->ifc_sctx = sctx;
4873 ctx->ifc_softc = sc;
4876 if ((err = iflib_register(ctx)) != 0) {
4877 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4880 iflib_add_device_sysctl_pre(ctx);
4882 scctx = &ctx->ifc_softc_ctx;
4885 iflib_reset_qvalues(ctx);
4887 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4888 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4891 if (sctx->isc_flags & IFLIB_GEN_MAC)
4892 ether_gen_addr(ifp, &ctx->ifc_mac);
4893 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4894 clctx->cc_params)) != 0) {
4895 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4899 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4900 MPASS(scctx->isc_tx_csum_flags);
4903 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4904 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4906 ifp->if_flags |= IFF_NOGROUP;
4907 if (sctx->isc_flags & IFLIB_PSEUDO) {
4908 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4909 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4910 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4911 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4913 if_attach(ctx->ifc_ifp);
4914 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4917 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4918 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4924 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4925 * This must appear after the call to ether_ifattach() because
4926 * ether_ifattach() sets if_hdrlen to the default value.
4928 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4929 if_setifheaderlen(ifp,
4930 sizeof(struct ether_vlan_header));
4932 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4933 iflib_add_device_sysctl_post(ctx);
4934 ctx->ifc_flags |= IFC_INIT_DONE;
4938 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4939 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4940 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4942 _iflib_pre_assert(scctx);
4943 ctx->ifc_txrx = *scctx->isc_txrx;
4945 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4946 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4947 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4948 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4950 num_txd = iflib_num_tx_descs(ctx);
4951 num_rxd = iflib_num_rx_descs(ctx);
4953 /* XXX change for per-queue sizes */
4954 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4957 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4958 scctx->isc_tx_nsegments = max(1, num_txd /
4959 MAX_SINGLE_PACKET_FRACTION);
4960 if (scctx->isc_tx_tso_segments_max > num_txd /
4961 MAX_SINGLE_PACKET_FRACTION)
4962 scctx->isc_tx_tso_segments_max = max(1,
4963 num_txd / MAX_SINGLE_PACKET_FRACTION);
4965 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4966 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4968 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4971 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4974 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4975 * into account. In the worst case, each of these calls will
4976 * add another mbuf and, thus, the requirement for another DMA
4977 * segment. So for best performance, it doesn't make sense to
4978 * advertize a maximum of TSO segments that typically will
4979 * require defragmentation in iflib_encap().
4981 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4982 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4984 if (scctx->isc_rss_table_size == 0)
4985 scctx->isc_rss_table_size = 64;
4986 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4988 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4989 /* XXX format name */
4990 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4991 NULL, NULL, "admin");
4993 /* XXX --- can support > 1 -- but keep it simple for now */
4994 scctx->isc_intr = IFLIB_INTR_LEGACY;
4996 /* Get memory for the station queues */
4997 if ((err = iflib_queues_alloc(ctx))) {
4998 device_printf(dev, "Unable to allocate queue memory\n");
4999 goto fail_iflib_detach;
5002 if ((err = iflib_qset_structures_setup(ctx))) {
5003 device_printf(dev, "qset structure setup failed %d\n", err);
5008 * XXX What if anything do we want to do about interrupts?
5010 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5011 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5012 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5017 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5018 * This must appear after the call to ether_ifattach() because
5019 * ether_ifattach() sets if_hdrlen to the default value.
5021 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5022 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5024 /* XXX handle more than one queue */
5025 for (i = 0; i < scctx->isc_nrxqsets; i++)
5026 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5030 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5031 iflib_add_device_sysctl_post(ctx);
5032 ctx->ifc_flags |= IFC_INIT_DONE;
5037 ether_ifdetach(ctx->ifc_ifp);
5039 iflib_tx_structures_free(ctx);
5040 iflib_rx_structures_free(ctx);
5045 iflib_deregister(ctx);
5047 free(ctx->ifc_softc, M_IFLIB);
5053 iflib_pseudo_deregister(if_ctx_t ctx)
5055 if_t ifp = ctx->ifc_ifp;
5056 if_shared_ctx_t sctx = ctx->ifc_sctx;
5060 struct taskqgroup *tqg;
5063 /* Unregister VLAN event handlers early */
5064 iflib_unregister_vlan_handlers(ctx);
5066 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5067 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5071 ether_ifdetach(ifp);
5073 /* XXX drain any dependent tasks */
5074 tqg = qgroup_if_io_tqg;
5075 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5076 callout_drain(&txq->ift_timer);
5077 if (txq->ift_task.gt_uniq != NULL)
5078 taskqgroup_detach(tqg, &txq->ift_task);
5080 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5081 callout_drain(&rxq->ifr_watchdog);
5082 if (rxq->ifr_task.gt_uniq != NULL)
5083 taskqgroup_detach(tqg, &rxq->ifr_task);
5085 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5086 free(fl->ifl_rx_bitmap, M_IFLIB);
5088 tqg = qgroup_if_config_tqg;
5089 if (ctx->ifc_admin_task.gt_uniq != NULL)
5090 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5091 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5092 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5094 iflib_tx_structures_free(ctx);
5095 iflib_rx_structures_free(ctx);
5097 iflib_deregister(ctx);
5099 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5100 free(ctx->ifc_softc, M_IFLIB);
5106 iflib_device_attach(device_t dev)
5109 if_shared_ctx_t sctx;
5111 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5114 pci_enable_busmaster(dev);
5116 return (iflib_device_register(dev, NULL, sctx, &ctx));
5120 iflib_device_deregister(if_ctx_t ctx)
5122 if_t ifp = ctx->ifc_ifp;
5125 device_t dev = ctx->ifc_dev;
5127 struct taskqgroup *tqg;
5130 /* Make sure VLANS are not using driver */
5131 if (if_vlantrunkinuse(ifp)) {
5132 device_printf(dev, "Vlan in use, detach first\n");
5136 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5137 device_printf(dev, "SR-IOV in use; detach first.\n");
5143 ctx->ifc_flags |= IFC_IN_DETACH;
5146 /* Unregister VLAN handlers before calling iflib_stop() */
5147 iflib_unregister_vlan_handlers(ctx);
5149 iflib_netmap_detach(ifp);
5150 ether_ifdetach(ifp);
5156 iflib_rem_pfil(ctx);
5157 if (ctx->ifc_led_dev != NULL)
5158 led_destroy(ctx->ifc_led_dev);
5159 /* XXX drain any dependent tasks */
5160 tqg = qgroup_if_io_tqg;
5161 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5162 callout_drain(&txq->ift_timer);
5163 if (txq->ift_task.gt_uniq != NULL)
5164 taskqgroup_detach(tqg, &txq->ift_task);
5166 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5167 if (rxq->ifr_task.gt_uniq != NULL)
5168 taskqgroup_detach(tqg, &rxq->ifr_task);
5170 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5171 free(fl->ifl_rx_bitmap, M_IFLIB);
5173 tqg = qgroup_if_config_tqg;
5174 if (ctx->ifc_admin_task.gt_uniq != NULL)
5175 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5176 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5177 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5182 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5183 iflib_free_intr_mem(ctx);
5185 bus_generic_detach(dev);
5187 iflib_tx_structures_free(ctx);
5188 iflib_rx_structures_free(ctx);
5190 iflib_deregister(ctx);
5192 device_set_softc(ctx->ifc_dev, NULL);
5193 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5194 free(ctx->ifc_softc, M_IFLIB);
5195 unref_ctx_core_offset(ctx);
5201 iflib_free_intr_mem(if_ctx_t ctx)
5204 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5205 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5207 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5208 pci_release_msi(ctx->ifc_dev);
5210 if (ctx->ifc_msix_mem != NULL) {
5211 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5212 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5213 ctx->ifc_msix_mem = NULL;
5218 iflib_device_detach(device_t dev)
5220 if_ctx_t ctx = device_get_softc(dev);
5222 return (iflib_device_deregister(ctx));
5226 iflib_device_suspend(device_t dev)
5228 if_ctx_t ctx = device_get_softc(dev);
5234 return bus_generic_suspend(dev);
5237 iflib_device_shutdown(device_t dev)
5239 if_ctx_t ctx = device_get_softc(dev);
5245 return bus_generic_suspend(dev);
5250 iflib_device_resume(device_t dev)
5252 if_ctx_t ctx = device_get_softc(dev);
5253 iflib_txq_t txq = ctx->ifc_txqs;
5257 iflib_if_init_locked(ctx);
5259 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5260 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5262 return (bus_generic_resume(dev));
5266 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5269 if_ctx_t ctx = device_get_softc(dev);
5272 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5279 iflib_device_iov_uninit(device_t dev)
5281 if_ctx_t ctx = device_get_softc(dev);
5284 IFDI_IOV_UNINIT(ctx);
5289 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5292 if_ctx_t ctx = device_get_softc(dev);
5295 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5301 /*********************************************************************
5303 * MODULE FUNCTION DEFINITIONS
5305 **********************************************************************/
5308 * - Start a fast taskqueue thread for each core
5309 * - Start a taskqueue for control operations
5312 iflib_module_init(void)
5318 iflib_module_event_handler(module_t mod, int what, void *arg)
5324 if ((err = iflib_module_init()) != 0)
5330 return (EOPNOTSUPP);
5336 /*********************************************************************
5338 * PUBLIC FUNCTION DEFINITIONS
5339 * ordered as in iflib.h
5341 **********************************************************************/
5345 _iflib_assert(if_shared_ctx_t sctx)
5349 MPASS(sctx->isc_tx_maxsize);
5350 MPASS(sctx->isc_tx_maxsegsize);
5352 MPASS(sctx->isc_rx_maxsize);
5353 MPASS(sctx->isc_rx_nsegments);
5354 MPASS(sctx->isc_rx_maxsegsize);
5356 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5357 for (i = 0; i < sctx->isc_nrxqs; i++) {
5358 MPASS(sctx->isc_nrxd_min[i]);
5359 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5360 MPASS(sctx->isc_nrxd_max[i]);
5361 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5362 MPASS(sctx->isc_nrxd_default[i]);
5363 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5366 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5367 for (i = 0; i < sctx->isc_ntxqs; i++) {
5368 MPASS(sctx->isc_ntxd_min[i]);
5369 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5370 MPASS(sctx->isc_ntxd_max[i]);
5371 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5372 MPASS(sctx->isc_ntxd_default[i]);
5373 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5378 _iflib_pre_assert(if_softc_ctx_t scctx)
5381 MPASS(scctx->isc_txrx->ift_txd_encap);
5382 MPASS(scctx->isc_txrx->ift_txd_flush);
5383 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5384 MPASS(scctx->isc_txrx->ift_rxd_available);
5385 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5386 MPASS(scctx->isc_txrx->ift_rxd_refill);
5387 MPASS(scctx->isc_txrx->ift_rxd_flush);
5391 iflib_register(if_ctx_t ctx)
5393 if_shared_ctx_t sctx = ctx->ifc_sctx;
5394 driver_t *driver = sctx->isc_driver;
5395 device_t dev = ctx->ifc_dev;
5400 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5401 _iflib_assert(sctx);
5404 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5405 if (sctx->isc_flags & IFLIB_PSEUDO) {
5406 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5412 ifp = ctx->ifc_ifp = if_alloc(type);
5414 device_printf(dev, "can not allocate ifnet structure\n");
5419 * Initialize our context's device specific methods
5421 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5422 kobj_class_compile((kobj_class_t) driver);
5424 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5425 if_setsoftc(ifp, ctx);
5426 if_setdev(ifp, dev);
5427 if_setinitfn(ifp, iflib_if_init);
5428 if_setioctlfn(ifp, iflib_if_ioctl);
5430 if_setstartfn(ifp, iflib_altq_if_start);
5431 if_settransmitfn(ifp, iflib_altq_if_transmit);
5432 if_setsendqready(ifp);
5434 if_settransmitfn(ifp, iflib_if_transmit);
5436 if_setqflushfn(ifp, iflib_if_qflush);
5437 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5439 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5440 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5441 iflags |= IFF_POINTOPOINT;
5443 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5444 if_setflags(ifp, iflags);
5445 ctx->ifc_vlan_attach_event =
5446 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5447 EVENTHANDLER_PRI_FIRST);
5448 ctx->ifc_vlan_detach_event =
5449 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5450 EVENTHANDLER_PRI_FIRST);
5452 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5453 ctx->ifc_mediap = &ctx->ifc_media;
5454 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5455 iflib_media_change, iflib_media_status);
5461 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5463 /* Unregister VLAN events */
5464 if (ctx->ifc_vlan_attach_event != NULL) {
5465 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5466 ctx->ifc_vlan_attach_event = NULL;
5468 if (ctx->ifc_vlan_detach_event != NULL) {
5469 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5470 ctx->ifc_vlan_detach_event = NULL;
5476 iflib_deregister(if_ctx_t ctx)
5478 if_t ifp = ctx->ifc_ifp;
5480 /* Remove all media */
5481 ifmedia_removeall(&ctx->ifc_media);
5483 /* Ensure that VLAN event handlers are unregistered */
5484 iflib_unregister_vlan_handlers(ctx);
5486 /* Release kobject reference */
5487 kobj_delete((kobj_t) ctx, NULL);
5489 /* Free the ifnet structure */
5492 STATE_LOCK_DESTROY(ctx);
5494 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5495 CTX_LOCK_DESTROY(ctx);
5499 iflib_queues_alloc(if_ctx_t ctx)
5501 if_shared_ctx_t sctx = ctx->ifc_sctx;
5502 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5503 device_t dev = ctx->ifc_dev;
5504 int nrxqsets = scctx->isc_nrxqsets;
5505 int ntxqsets = scctx->isc_ntxqsets;
5508 iflib_fl_t fl = NULL;
5509 int i, j, cpu, err, txconf, rxconf;
5510 iflib_dma_info_t ifdip;
5511 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5512 uint32_t *txqsizes = scctx->isc_txqsizes;
5513 uint8_t nrxqs = sctx->isc_nrxqs;
5514 uint8_t ntxqs = sctx->isc_ntxqs;
5515 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5519 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5520 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5522 /* Allocate the TX ring struct memory */
5523 if (!(ctx->ifc_txqs =
5524 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5525 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5526 device_printf(dev, "Unable to allocate TX ring memory\n");
5531 /* Now allocate the RX */
5532 if (!(ctx->ifc_rxqs =
5533 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5534 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5535 device_printf(dev, "Unable to allocate RX ring memory\n");
5540 txq = ctx->ifc_txqs;
5541 rxq = ctx->ifc_rxqs;
5544 * XXX handle allocation failure
5546 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5547 /* Set up some basics */
5549 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5550 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5552 "Unable to allocate TX DMA info memory\n");
5556 txq->ift_ifdi = ifdip;
5557 for (j = 0; j < ntxqs; j++, ifdip++) {
5558 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5560 "Unable to allocate TX descriptors\n");
5564 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5565 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5569 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5570 txq->ift_br_offset = 1;
5572 txq->ift_br_offset = 0;
5575 txq->ift_timer.c_cpu = cpu;
5577 if (iflib_txsd_alloc(txq)) {
5578 device_printf(dev, "Critical Failure setting up TX buffers\n");
5583 /* Initialize the TX lock */
5584 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5585 device_get_nameunit(dev), txq->ift_id);
5586 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5587 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5589 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5590 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5592 /* XXX free any allocated rings */
5593 device_printf(dev, "Unable to allocate buf_ring\n");
5598 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5599 /* Set up some basics */
5600 callout_init(&rxq->ifr_watchdog, 1);
5602 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5603 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5605 "Unable to allocate RX DMA info memory\n");
5610 rxq->ifr_ifdi = ifdip;
5611 /* XXX this needs to be changed if #rx queues != #tx queues */
5612 rxq->ifr_ntxqirq = 1;
5613 rxq->ifr_txqid[0] = i;
5614 for (j = 0; j < nrxqs; j++, ifdip++) {
5615 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5617 "Unable to allocate RX descriptors\n");
5621 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5625 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5626 rxq->ifr_fl_offset = 1;
5628 rxq->ifr_fl_offset = 0;
5630 rxq->ifr_nfl = nfree_lists;
5632 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5633 device_printf(dev, "Unable to allocate free list memory\n");
5638 for (j = 0; j < nfree_lists; j++) {
5639 fl[j].ifl_rxq = rxq;
5641 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5642 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5644 /* Allocate receive buffers for the ring */
5645 if (iflib_rxsd_alloc(rxq)) {
5647 "Critical Failure setting up receive buffers\n");
5652 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5653 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5658 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5659 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5660 for (i = 0; i < ntxqsets; i++) {
5661 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5663 for (j = 0; j < ntxqs; j++, di++) {
5664 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5665 paddrs[i*ntxqs + j] = di->idi_paddr;
5668 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5669 device_printf(ctx->ifc_dev,
5670 "Unable to allocate device TX queue\n");
5671 iflib_tx_structures_free(ctx);
5672 free(vaddrs, M_IFLIB);
5673 free(paddrs, M_IFLIB);
5676 free(vaddrs, M_IFLIB);
5677 free(paddrs, M_IFLIB);
5680 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5681 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5682 for (i = 0; i < nrxqsets; i++) {
5683 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5685 for (j = 0; j < nrxqs; j++, di++) {
5686 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5687 paddrs[i*nrxqs + j] = di->idi_paddr;
5690 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5691 device_printf(ctx->ifc_dev,
5692 "Unable to allocate device RX queue\n");
5693 iflib_tx_structures_free(ctx);
5694 free(vaddrs, M_IFLIB);
5695 free(paddrs, M_IFLIB);
5698 free(vaddrs, M_IFLIB);
5699 free(paddrs, M_IFLIB);
5703 /* XXX handle allocation failure changes */
5707 if (ctx->ifc_rxqs != NULL)
5708 free(ctx->ifc_rxqs, M_IFLIB);
5709 ctx->ifc_rxqs = NULL;
5710 if (ctx->ifc_txqs != NULL)
5711 free(ctx->ifc_txqs, M_IFLIB);
5712 ctx->ifc_txqs = NULL;
5718 iflib_tx_structures_setup(if_ctx_t ctx)
5720 iflib_txq_t txq = ctx->ifc_txqs;
5723 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5724 iflib_txq_setup(txq);
5730 iflib_tx_structures_free(if_ctx_t ctx)
5732 iflib_txq_t txq = ctx->ifc_txqs;
5733 if_shared_ctx_t sctx = ctx->ifc_sctx;
5736 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5737 for (j = 0; j < sctx->isc_ntxqs; j++)
5738 iflib_dma_free(&txq->ift_ifdi[j]);
5739 iflib_txq_destroy(txq);
5741 free(ctx->ifc_txqs, M_IFLIB);
5742 ctx->ifc_txqs = NULL;
5743 IFDI_QUEUES_FREE(ctx);
5746 /*********************************************************************
5748 * Initialize all receive rings.
5750 **********************************************************************/
5752 iflib_rx_structures_setup(if_ctx_t ctx)
5754 iflib_rxq_t rxq = ctx->ifc_rxqs;
5756 #if defined(INET6) || defined(INET)
5760 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5761 #if defined(INET6) || defined(INET)
5762 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5763 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5764 TCP_LRO_ENTRIES, min(1024,
5765 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5767 device_printf(ctx->ifc_dev,
5768 "LRO Initialization failed!\n");
5773 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5776 #if defined(INET6) || defined(INET)
5779 * Free LRO resources allocated so far, we will only handle
5780 * the rings that completed, the failing case will have
5781 * cleaned up for itself. 'q' failed, so its the terminus.
5783 rxq = ctx->ifc_rxqs;
5784 for (i = 0; i < q; ++i, rxq++) {
5785 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5786 tcp_lro_free(&rxq->ifr_lc);
5792 /*********************************************************************
5794 * Free all receive rings.
5796 **********************************************************************/
5798 iflib_rx_structures_free(if_ctx_t ctx)
5800 iflib_rxq_t rxq = ctx->ifc_rxqs;
5801 if_shared_ctx_t sctx = ctx->ifc_sctx;
5804 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5805 for (j = 0; j < sctx->isc_nrxqs; j++)
5806 iflib_dma_free(&rxq->ifr_ifdi[j]);
5807 iflib_rx_sds_free(rxq);
5808 #if defined(INET6) || defined(INET)
5809 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5810 tcp_lro_free(&rxq->ifr_lc);
5813 free(ctx->ifc_rxqs, M_IFLIB);
5814 ctx->ifc_rxqs = NULL;
5818 iflib_qset_structures_setup(if_ctx_t ctx)
5823 * It is expected that the caller takes care of freeing queues if this
5826 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5827 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5831 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5832 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5838 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5839 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5842 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5847 find_nth(if_ctx_t ctx, int qid)
5850 int i, cpuid, eqid, count;
5852 CPU_COPY(&ctx->ifc_cpus, &cpus);
5853 count = CPU_COUNT(&cpus);
5855 /* clear up to the qid'th bit */
5856 for (i = 0; i < eqid; i++) {
5857 cpuid = CPU_FFS(&cpus);
5859 CPU_CLR(cpuid-1, &cpus);
5861 cpuid = CPU_FFS(&cpus);
5867 extern struct cpu_group *cpu_top; /* CPU topology */
5870 find_child_with_core(int cpu, struct cpu_group *grp)
5874 if (grp->cg_children == 0)
5877 MPASS(grp->cg_child);
5878 for (i = 0; i < grp->cg_children; i++) {
5879 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5887 * Find the nth "close" core to the specified core
5888 * "close" is defined as the deepest level that shares
5889 * at least an L2 cache. With threads, this will be
5890 * threads on the same core. If the shared cache is L3
5891 * or higher, simply returns the same core.
5894 find_close_core(int cpu, int core_offset)
5896 struct cpu_group *grp;
5905 while ((i = find_child_with_core(cpu, grp)) != -1) {
5906 /* If the child only has one cpu, don't descend */
5907 if (grp->cg_child[i].cg_count <= 1)
5909 grp = &grp->cg_child[i];
5912 /* If they don't share at least an L2 cache, use the same CPU */
5913 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5917 CPU_COPY(&grp->cg_mask, &cs);
5919 /* Add the selected CPU offset to core offset. */
5920 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5921 if (fcpu - 1 == cpu)
5923 CPU_CLR(fcpu - 1, &cs);
5929 CPU_COPY(&grp->cg_mask, &cs);
5930 for (i = core_offset % grp->cg_count; i > 0; i--) {
5931 MPASS(CPU_FFS(&cs));
5932 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5934 MPASS(CPU_FFS(&cs));
5935 return CPU_FFS(&cs) - 1;
5939 find_close_core(int cpu, int core_offset __unused)
5946 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5950 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5951 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5952 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5954 case IFLIB_INTR_RXTX:
5955 /* RX queues get the specified core */
5956 return qid / CPU_COUNT(&ctx->ifc_cpus);
5962 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5963 #define find_close_core(cpuid, tid) CPU_FIRST()
5964 #define find_nth(ctx, gid) CPU_FIRST()
5967 /* Just to avoid copy/paste */
5969 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5970 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5974 int co, cpuid, err, tid;
5977 co = ctx->ifc_sysctl_core_offset;
5978 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5979 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5980 cpuid = find_nth(ctx, qid + co);
5981 tid = get_core_offset(ctx, type, qid);
5983 device_printf(dev, "get_core_offset failed\n");
5984 return (EOPNOTSUPP);
5986 cpuid = find_close_core(cpuid, tid);
5987 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5990 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5994 if (cpuid > ctx->ifc_cpuid_highest)
5995 ctx->ifc_cpuid_highest = cpuid;
6001 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6002 iflib_intr_type_t type, driver_filter_t *filter,
6003 void *filter_arg, int qid, const char *name)
6006 struct grouptask *gtask;
6007 struct taskqgroup *tqg;
6008 iflib_filter_info_t info;
6011 driver_filter_t *intr_fast;
6014 info = &ctx->ifc_filter_info;
6018 /* XXX merge tx/rx for netmap? */
6020 q = &ctx->ifc_txqs[qid];
6021 info = &ctx->ifc_txqs[qid].ift_filter_info;
6022 gtask = &ctx->ifc_txqs[qid].ift_task;
6023 tqg = qgroup_if_io_tqg;
6025 intr_fast = iflib_fast_intr;
6026 GROUPTASK_INIT(gtask, 0, fn, q);
6027 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6030 q = &ctx->ifc_rxqs[qid];
6031 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6032 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6033 tqg = qgroup_if_io_tqg;
6035 intr_fast = iflib_fast_intr;
6036 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6038 case IFLIB_INTR_RXTX:
6039 q = &ctx->ifc_rxqs[qid];
6040 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6041 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6042 tqg = qgroup_if_io_tqg;
6044 intr_fast = iflib_fast_intr_rxtx;
6045 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6047 case IFLIB_INTR_ADMIN:
6050 info = &ctx->ifc_filter_info;
6051 gtask = &ctx->ifc_admin_task;
6052 tqg = qgroup_if_config_tqg;
6053 fn = _task_fn_admin;
6054 intr_fast = iflib_fast_intr_ctx;
6057 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6062 info->ifi_filter = filter;
6063 info->ifi_filter_arg = filter_arg;
6064 info->ifi_task = gtask;
6068 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6070 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6073 if (type == IFLIB_INTR_ADMIN)
6077 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6082 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6089 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6091 struct grouptask *gtask;
6092 struct taskqgroup *tqg;
6099 q = &ctx->ifc_txqs[qid];
6100 gtask = &ctx->ifc_txqs[qid].ift_task;
6101 tqg = qgroup_if_io_tqg;
6103 GROUPTASK_INIT(gtask, 0, fn, q);
6106 q = &ctx->ifc_rxqs[qid];
6107 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6108 tqg = qgroup_if_io_tqg;
6110 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6112 case IFLIB_INTR_IOV:
6114 gtask = &ctx->ifc_vflr_task;
6115 tqg = qgroup_if_config_tqg;
6117 GROUPTASK_INIT(gtask, 0, fn, q);
6120 panic("unknown net intr type");
6123 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6126 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6129 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6134 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6138 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6141 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6142 rman_get_rid(irq->ii_res), irq->ii_res);
6146 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6148 iflib_txq_t txq = ctx->ifc_txqs;
6149 iflib_rxq_t rxq = ctx->ifc_rxqs;
6150 if_irq_t irq = &ctx->ifc_legacy_irq;
6151 iflib_filter_info_t info;
6153 struct grouptask *gtask;
6154 struct resource *res;
6155 struct taskqgroup *tqg;
6160 q = &ctx->ifc_rxqs[0];
6161 info = &rxq[0].ifr_filter_info;
6162 gtask = &rxq[0].ifr_task;
6163 tqg = qgroup_if_io_tqg;
6165 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6167 ctx->ifc_flags |= IFC_LEGACY;
6168 info->ifi_filter = filter;
6169 info->ifi_filter_arg = filter_arg;
6170 info->ifi_task = gtask;
6171 info->ifi_ctx = rx_only ? ctx : q;
6174 /* We allocate a single interrupt resource */
6175 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6176 iflib_fast_intr_rxtx, NULL, info, name);
6179 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6181 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6183 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6184 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6190 iflib_led_create(if_ctx_t ctx)
6193 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6194 device_get_nameunit(ctx->ifc_dev));
6198 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6201 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6205 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6208 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6212 iflib_admin_intr_deferred(if_ctx_t ctx)
6215 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6216 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6220 iflib_iov_intr_deferred(if_ctx_t ctx)
6223 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6227 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6230 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6235 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6239 GROUPTASK_INIT(gtask, 0, fn, ctx);
6240 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6245 iflib_config_gtask_deinit(struct grouptask *gtask)
6248 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6252 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6254 if_t ifp = ctx->ifc_ifp;
6255 iflib_txq_t txq = ctx->ifc_txqs;
6257 if_setbaudrate(ifp, baudrate);
6258 if (baudrate >= IF_Gbps(10)) {
6260 ctx->ifc_flags |= IFC_PREFETCH;
6263 /* If link down, disable watchdog */
6264 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6265 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6266 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6268 ctx->ifc_link_state = link_state;
6269 if_link_state_change(ifp, link_state);
6273 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6277 int credits_pre = txq->ift_cidx_processed;
6280 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6281 BUS_DMASYNC_POSTREAD);
6282 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6285 txq->ift_processed += credits;
6286 txq->ift_cidx_processed += credits;
6288 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6289 if (txq->ift_cidx_processed >= txq->ift_size)
6290 txq->ift_cidx_processed -= txq->ift_size;
6295 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6300 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6301 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6302 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6303 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6308 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6309 const char *description, if_int_delay_info_t info,
6310 int offset, int value)
6312 info->iidi_ctx = ctx;
6313 info->iidi_offset = offset;
6314 info->iidi_value = value;
6315 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6316 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6317 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6318 info, 0, iflib_sysctl_int_delay, "I", description);
6322 iflib_ctx_lock_get(if_ctx_t ctx)
6325 return (&ctx->ifc_ctx_sx);
6329 iflib_msix_init(if_ctx_t ctx)
6331 device_t dev = ctx->ifc_dev;
6332 if_shared_ctx_t sctx = ctx->ifc_sctx;
6333 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6334 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6335 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6337 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6338 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6341 device_printf(dev, "msix_init qsets capped at %d\n",
6342 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6344 /* Override by tuneable */
6345 if (scctx->isc_disable_msix)
6348 /* First try MSI-X */
6349 if ((msgs = pci_msix_count(dev)) == 0) {
6351 device_printf(dev, "MSI-X not supported or disabled\n");
6355 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6357 * bar == -1 => "trust me I know what I'm doing"
6358 * Some drivers are for hardware that is so shoddily
6359 * documented that no one knows which bars are which
6360 * so the developer has to map all bars. This hack
6361 * allows shoddy garbage to use MSI-X in this framework.
6364 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6365 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6366 if (ctx->ifc_msix_mem == NULL) {
6367 device_printf(dev, "Unable to map MSI-X table\n");
6372 admincnt = sctx->isc_admin_intrcnt;
6374 /* use only 1 qset in debug mode */
6375 queuemsgs = min(msgs - admincnt, 1);
6377 queuemsgs = msgs - admincnt;
6380 queues = imin(queuemsgs, rss_getnumbuckets());
6384 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6387 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6388 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6390 /* If we're doing RSS, clamp at the number of RSS buckets */
6391 if (queues > rss_getnumbuckets())
6392 queues = rss_getnumbuckets();
6394 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6395 rx_queues = iflib_num_rx_queues;
6399 if (rx_queues > scctx->isc_nrxqsets)
6400 rx_queues = scctx->isc_nrxqsets;
6403 * We want this to be all logical CPUs by default
6405 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6406 tx_queues = iflib_num_tx_queues;
6408 tx_queues = mp_ncpus;
6410 if (tx_queues > scctx->isc_ntxqsets)
6411 tx_queues = scctx->isc_ntxqsets;
6413 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6415 if (tx_queues != rx_queues)
6417 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6418 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6420 tx_queues = min(rx_queues, tx_queues);
6421 rx_queues = min(rx_queues, tx_queues);
6424 vectors = rx_queues + admincnt;
6425 if (msgs < vectors) {
6427 "insufficient number of MSI-X vectors "
6428 "(supported %d, need %d)\n", msgs, vectors);
6432 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6435 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6436 if (vectors != msgs) {
6438 "Unable to allocate sufficient MSI-X vectors "
6439 "(got %d, need %d)\n", vectors, msgs);
6440 pci_release_msi(dev);
6442 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6444 ctx->ifc_msix_mem = NULL;
6448 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6450 scctx->isc_vectors = vectors;
6451 scctx->isc_nrxqsets = rx_queues;
6452 scctx->isc_ntxqsets = tx_queues;
6453 scctx->isc_intr = IFLIB_INTR_MSIX;
6458 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6461 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6463 ctx->ifc_msix_mem = NULL;
6468 vectors = pci_msi_count(dev);
6469 scctx->isc_nrxqsets = 1;
6470 scctx->isc_ntxqsets = 1;
6471 scctx->isc_vectors = vectors;
6472 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6473 device_printf(dev,"Using an MSI interrupt\n");
6474 scctx->isc_intr = IFLIB_INTR_MSI;
6476 scctx->isc_vectors = 1;
6477 device_printf(dev,"Using a Legacy interrupt\n");
6478 scctx->isc_intr = IFLIB_INTR_LEGACY;
6484 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6487 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6490 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6492 const char *ring_state = "UNKNOWN";
6495 rc = sysctl_wire_old_buffer(req, 0);
6499 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6504 ring_state = ring_states[state[3]];
6506 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6507 state[0], state[1], state[2], ring_state);
6508 rc = sbuf_finish(sb);
6513 enum iflib_ndesc_handler {
6519 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6521 if_ctx_t ctx = (void *)arg1;
6522 enum iflib_ndesc_handler type = arg2;
6523 char buf[256] = {0};
6530 case IFLIB_NTXD_HANDLER:
6531 ndesc = ctx->ifc_sysctl_ntxds;
6533 nqs = ctx->ifc_sctx->isc_ntxqs;
6535 case IFLIB_NRXD_HANDLER:
6536 ndesc = ctx->ifc_sysctl_nrxds;
6538 nqs = ctx->ifc_sctx->isc_nrxqs;
6541 printf("%s: unhandled type\n", __func__);
6547 for (i=0; i<8; i++) {
6552 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6555 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6556 if (rc || req->newptr == NULL)
6559 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6560 i++, p = strsep(&next, " ,")) {
6561 ndesc[i] = strtoul(p, NULL, 10);
6567 #define NAME_BUFLEN 32
6569 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6571 device_t dev = iflib_get_dev(ctx);
6572 struct sysctl_oid_list *child, *oid_list;
6573 struct sysctl_ctx_list *ctx_list;
6574 struct sysctl_oid *node;
6576 ctx_list = device_get_sysctl_ctx(dev);
6577 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6578 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6579 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6580 oid_list = SYSCTL_CHILDREN(node);
6582 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6583 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6586 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6587 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6588 "# of txqs to use, 0 => use default #");
6589 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6590 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6591 "# of rxqs to use, 0 => use default #");
6592 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6593 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6594 "permit #txq != #rxq");
6595 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6596 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6597 "disable MSI-X (default 0)");
6598 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6599 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6600 "set the RX budget");
6601 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6602 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6603 "cause TX to abdicate instead of running to completion");
6604 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6605 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6606 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6607 "offset to start using cores at");
6608 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6609 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6610 "use separate cores for TX and RX");
6612 /* XXX change for per-queue sizes */
6613 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6614 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6615 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6616 "list of # of TX descriptors to use, 0 = use default #");
6617 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6618 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6619 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6620 "list of # of RX descriptors to use, 0 = use default #");
6624 iflib_add_device_sysctl_post(if_ctx_t ctx)
6626 if_shared_ctx_t sctx = ctx->ifc_sctx;
6627 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6628 device_t dev = iflib_get_dev(ctx);
6629 struct sysctl_oid_list *child;
6630 struct sysctl_ctx_list *ctx_list;
6635 char namebuf[NAME_BUFLEN];
6637 struct sysctl_oid *queue_node, *fl_node, *node;
6638 struct sysctl_oid_list *queue_list, *fl_list;
6639 ctx_list = device_get_sysctl_ctx(dev);
6641 node = ctx->ifc_sysctl_node;
6642 child = SYSCTL_CHILDREN(node);
6644 if (scctx->isc_ntxqsets > 100)
6646 else if (scctx->isc_ntxqsets > 10)
6650 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6651 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6652 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6653 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6654 queue_list = SYSCTL_CHILDREN(queue_node);
6656 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6658 &txq->ift_dequeued, "total mbufs freed");
6659 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6661 &txq->ift_enqueued, "total mbufs enqueued");
6663 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6665 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6666 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6668 &txq->ift_pullups, "# of times m_pullup was called");
6669 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6671 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6672 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6674 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6675 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6677 &txq->ift_map_failed, "# of times DMA map failed");
6678 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6680 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6681 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6683 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6684 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6686 &txq->ift_pidx, 1, "Producer Index");
6687 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6689 &txq->ift_cidx, 1, "Consumer Index");
6690 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6692 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6693 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6695 &txq->ift_in_use, 1, "descriptors in use");
6696 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6698 &txq->ift_processed, "descriptors procesed for clean");
6699 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6701 &txq->ift_cleaned, "total cleaned");
6702 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6703 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6704 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6705 mp_ring_state_handler, "A", "soft ring state");
6706 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6707 CTLFLAG_RD, &txq->ift_br->enqueues,
6708 "# of enqueues to the mp_ring for this queue");
6709 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6710 CTLFLAG_RD, &txq->ift_br->drops,
6711 "# of drops in the mp_ring for this queue");
6712 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6713 CTLFLAG_RD, &txq->ift_br->starts,
6714 "# of normal consumer starts in the mp_ring for this queue");
6715 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6716 CTLFLAG_RD, &txq->ift_br->stalls,
6717 "# of consumer stalls in the mp_ring for this queue");
6718 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6719 CTLFLAG_RD, &txq->ift_br->restarts,
6720 "# of consumer restarts in the mp_ring for this queue");
6721 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6722 CTLFLAG_RD, &txq->ift_br->abdications,
6723 "# of consumer abdications in the mp_ring for this queue");
6726 if (scctx->isc_nrxqsets > 100)
6728 else if (scctx->isc_nrxqsets > 10)
6732 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6733 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6734 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6735 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6736 queue_list = SYSCTL_CHILDREN(queue_node);
6737 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6738 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6740 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6743 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6744 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6745 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6746 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6747 fl_list = SYSCTL_CHILDREN(fl_node);
6748 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6750 &fl->ifl_pidx, 1, "Producer Index");
6751 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6753 &fl->ifl_cidx, 1, "Consumer Index");
6754 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6756 &fl->ifl_credits, 1, "credits available");
6757 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6759 &fl->ifl_buf_size, 1, "buffer size");
6761 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6763 &fl->ifl_m_enqueued, "mbufs allocated");
6764 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6766 &fl->ifl_m_dequeued, "mbufs freed");
6767 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6769 &fl->ifl_cl_enqueued, "clusters allocated");
6770 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6772 &fl->ifl_cl_dequeued, "clusters freed");
6781 iflib_request_reset(if_ctx_t ctx)
6785 ctx->ifc_flags |= IFC_DO_RESET;
6789 #ifndef __NO_STRICT_ALIGNMENT
6790 static struct mbuf *
6791 iflib_fixup_rx(struct mbuf *m)
6795 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6796 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6797 m->m_data += ETHER_HDR_LEN;
6800 MGETHDR(n, M_NOWAIT, MT_DATA);
6805 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6806 m->m_data += ETHER_HDR_LEN;
6807 m->m_len -= ETHER_HDR_LEN;
6808 n->m_len = ETHER_HDR_LEN;
6809 M_MOVE_PKTHDR(n, m);
6818 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6822 ctx = if_getsoftc(ifp);
6824 *nrxr = NRXQSETS(ctx);
6825 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6826 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6831 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6834 if_softc_ctx_t scctx;
6839 ctx = if_getsoftc(ifp);
6840 scctx = &ctx->ifc_softc_ctx;
6843 case DEBUGNET_START:
6844 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6845 rxq = &ctx->ifc_rxqs[i];
6846 for (j = 0; j < rxq->ifr_nfl; j++) {
6848 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6851 iflib_no_tx_batch = 1;
6859 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6865 ctx = if_getsoftc(ifp);
6866 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6870 txq = &ctx->ifc_txqs[0];
6871 error = iflib_encap(txq, &m);
6873 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6878 iflib_debugnet_poll(if_t ifp, int count)
6880 struct epoch_tracker et;
6882 if_softc_ctx_t scctx;
6886 ctx = if_getsoftc(ifp);
6887 scctx = &ctx->ifc_softc_ctx;
6889 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6893 txq = &ctx->ifc_txqs[0];
6894 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6896 NET_EPOCH_ENTER(et);
6897 for (i = 0; i < scctx->isc_nrxqsets; i++)
6898 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6902 #endif /* DEBUGNET */