2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
96 #include <dev/pci/pci_iov.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
177 int ifc_watchdog_events;
178 struct cdev *ifc_led_dev;
179 struct resource *ifc_msix_mem;
181 struct if_irq ifc_legacy_irq;
182 struct grouptask ifc_admin_task;
183 struct grouptask ifc_vflr_task;
184 struct iflib_filter_info ifc_filter_info;
185 struct ifmedia ifc_media;
187 struct sysctl_oid *ifc_sysctl_node;
188 uint16_t ifc_sysctl_ntxqs;
189 uint16_t ifc_sysctl_nrxqs;
190 uint16_t ifc_sysctl_qs_eq_override;
191 uint16_t ifc_sysctl_rx_budget;
192 uint16_t ifc_sysctl_tx_abdicate;
194 qidx_t ifc_sysctl_ntxds[8];
195 qidx_t ifc_sysctl_nrxds[8];
196 struct if_txrx ifc_txrx;
197 #define isc_txd_encap ifc_txrx.ift_txd_encap
198 #define isc_txd_flush ifc_txrx.ift_txd_flush
199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
200 #define isc_rxd_available ifc_txrx.ift_rxd_available
201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
207 eventhandler_tag ifc_vlan_attach_event;
208 eventhandler_tag ifc_vlan_detach_event;
209 uint8_t ifc_mac[ETHER_ADDR_LEN];
210 char ifc_mtx_name[16];
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (&ctx->ifc_media);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 /* bnxt supports 64 with hardware LRO enabled */
293 #define IFLIB_MAX_RX_SEGS 64
294 #define IFLIB_RX_COPY_THRESH 128
295 #define IFLIB_MAX_RX_REFRESH 32
296 /* The minimum descriptors per second before we start coalescing */
297 #define IFLIB_MIN_DESC_SEC 16384
298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
299 #define IFLIB_QUEUE_IDLE 0
300 #define IFLIB_QUEUE_HUNG 1
301 #define IFLIB_QUEUE_WORKING 2
302 /* maximum number of txqs that can share an rx interrupt */
303 #define IFLIB_MAX_TX_SHARED_INTR 4
305 /* this should really scale with ring size - this is a fairly arbitrary value */
306 #define TX_BATCH_SIZE 32
308 #define IFLIB_RESTART_BUDGET 8
311 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
312 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
313 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
317 qidx_t ift_cidx_processed;
320 uint8_t ift_br_offset;
321 uint16_t ift_npending;
322 uint16_t ift_db_pending;
323 uint16_t ift_rs_pending;
325 uint8_t ift_txd_size[8];
326 uint64_t ift_processed;
327 uint64_t ift_cleaned;
328 uint64_t ift_cleaned_prev;
330 uint64_t ift_enqueued;
331 uint64_t ift_dequeued;
333 uint64_t ift_no_tx_dma_setup;
334 uint64_t ift_no_desc_avail;
335 uint64_t ift_mbuf_defrag_failed;
336 uint64_t ift_mbuf_defrag;
337 uint64_t ift_map_failed;
338 uint64_t ift_txd_encap_efbig;
339 uint64_t ift_pullups;
340 uint64_t ift_last_timer_tick;
343 struct mtx ift_db_mtx;
345 /* constant values */
347 struct ifmp_ring *ift_br;
348 struct grouptask ift_task;
351 struct callout ift_timer;
353 if_txsd_vec_t ift_sds;
356 uint8_t ift_update_freq;
357 struct iflib_filter_info ift_filter_info;
358 bus_dma_tag_t ift_buf_tag;
359 bus_dma_tag_t ift_tso_buf_tag;
360 iflib_dma_info_t ift_ifdi;
361 #define MTX_NAME_LEN 16
362 char ift_mtx_name[MTX_NAME_LEN];
363 char ift_db_mtx_name[MTX_NAME_LEN];
364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
365 #ifdef IFLIB_DIAGNOSTICS
366 uint64_t ift_cpu_exec_count[256];
368 } __aligned(CACHE_LINE_SIZE);
375 uint8_t ifl_rxd_size;
377 uint64_t ifl_m_enqueued;
378 uint64_t ifl_m_dequeued;
379 uint64_t ifl_cl_enqueued;
380 uint64_t ifl_cl_dequeued;
384 bitstr_t *ifl_rx_bitmap;
388 uint16_t ifl_buf_size;
391 iflib_rxsd_array_t ifl_sds;
394 bus_dma_tag_t ifl_buf_tag;
395 iflib_dma_info_t ifl_ifdi;
396 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
397 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
399 } __aligned(CACHE_LINE_SIZE);
402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
408 else if (pidx < cidx)
409 used = size - cidx + pidx;
410 else if (gen == 0 && pidx == cidx)
412 else if (gen == 1 && pidx == cidx)
420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
422 #define IDXDIFF(head, tail, wrap) \
423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
426 /* If there is a separate completion queue -
427 * these are the cq cidx and pidx. Otherwise
434 uint8_t ifr_fl_offset;
440 uint8_t ifr_lro_enabled;
443 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
444 struct lro_ctrl ifr_lc;
445 struct grouptask ifr_task;
446 struct iflib_filter_info ifr_filter_info;
447 iflib_dma_info_t ifr_ifdi;
449 /* dynamically allocate if any drivers need a value substantially larger than this */
450 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
451 #ifdef IFLIB_DIAGNOSTICS
452 uint64_t ifr_cpu_exec_count[256];
454 } __aligned(CACHE_LINE_SIZE);
456 typedef struct if_rxsd {
458 struct mbuf **ifsd_m;
463 /* multiple of word size */
465 #define PKT_INFO_SIZE 6
466 #define RXD_INFO_SIZE 5
467 #define PKT_TYPE uint64_t
469 #define PKT_INFO_SIZE 11
470 #define RXD_INFO_SIZE 8
471 #define PKT_TYPE uint32_t
473 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
474 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
476 typedef struct if_pkt_info_pad {
477 PKT_TYPE pkt_val[PKT_INFO_SIZE];
478 } *if_pkt_info_pad_t;
479 typedef struct if_rxd_info_pad {
480 PKT_TYPE rxd_val[RXD_INFO_SIZE];
481 } *if_rxd_info_pad_t;
483 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
484 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
488 pkt_info_zero(if_pkt_info_t pi)
490 if_pkt_info_pad_t pi_pad;
492 pi_pad = (if_pkt_info_pad_t)pi;
493 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
494 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
496 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
497 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
501 static device_method_t iflib_pseudo_methods[] = {
502 DEVMETHOD(device_attach, noop_attach),
503 DEVMETHOD(device_detach, iflib_pseudo_detach),
507 driver_t iflib_pseudodriver = {
508 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
512 rxd_info_zero(if_rxd_info_t ri)
514 if_rxd_info_pad_t ri_pad;
517 ri_pad = (if_rxd_info_pad_t)ri;
518 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
519 ri_pad->rxd_val[i] = 0;
520 ri_pad->rxd_val[i+1] = 0;
521 ri_pad->rxd_val[i+2] = 0;
522 ri_pad->rxd_val[i+3] = 0;
525 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
530 * Only allow a single packet to take up most 1/nth of the tx ring
532 #define MAX_SINGLE_PACKET_FRACTION 12
533 #define IF_BAD_DMA (bus_addr_t)-1
535 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
537 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
538 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
539 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
540 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
543 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
544 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
545 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
546 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
550 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
551 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
554 iflib_set_detach(if_ctx_t ctx)
557 ctx->ifc_flags |= IFC_IN_DETACH;
561 /* Our boot-time initialization hook */
562 static int iflib_module_event_handler(module_t, int, void *);
564 static moduledata_t iflib_moduledata = {
566 iflib_module_event_handler,
570 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
571 MODULE_VERSION(iflib, 1);
573 MODULE_DEPEND(iflib, pci, 1, 1, 1);
574 MODULE_DEPEND(iflib, ether, 1, 1, 1);
576 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
577 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
579 #ifndef IFLIB_DEBUG_COUNTERS
581 #define IFLIB_DEBUG_COUNTERS 1
583 #define IFLIB_DEBUG_COUNTERS 0
584 #endif /* !INVARIANTS */
587 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
588 "iflib driver parameters");
591 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
593 static int iflib_min_tx_latency = 0;
594 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
595 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
596 static int iflib_no_tx_batch = 0;
597 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
598 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
601 #if IFLIB_DEBUG_COUNTERS
603 static int iflib_tx_seen;
604 static int iflib_tx_sent;
605 static int iflib_tx_encap;
606 static int iflib_rx_allocs;
607 static int iflib_fl_refills;
608 static int iflib_fl_refills_large;
609 static int iflib_tx_frees;
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
612 &iflib_tx_seen, 0, "# tx mbufs seen");
613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
614 &iflib_tx_sent, 0, "# tx mbufs sent");
615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
616 &iflib_tx_encap, 0, "# tx mbufs encapped");
617 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
618 &iflib_tx_frees, 0, "# tx frees");
619 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
620 &iflib_rx_allocs, 0, "# rx allocations");
621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
622 &iflib_fl_refills, 0, "# refills");
623 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
624 &iflib_fl_refills_large, 0, "# large refills");
627 static int iflib_txq_drain_flushing;
628 static int iflib_txq_drain_oactive;
629 static int iflib_txq_drain_notready;
631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
632 &iflib_txq_drain_flushing, 0, "# drain flushes");
633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
634 &iflib_txq_drain_oactive, 0, "# drain oactives");
635 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
636 &iflib_txq_drain_notready, 0, "# drain notready");
639 static int iflib_encap_load_mbuf_fail;
640 static int iflib_encap_pad_mbuf_fail;
641 static int iflib_encap_txq_avail_fail;
642 static int iflib_encap_txd_encap_fail;
644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
645 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
647 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
649 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
650 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
651 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
653 static int iflib_task_fn_rxs;
654 static int iflib_rx_intr_enables;
655 static int iflib_fast_intrs;
656 static int iflib_rx_unavail;
657 static int iflib_rx_ctx_inactive;
658 static int iflib_rx_if_input;
659 static int iflib_rx_mbuf_null;
660 static int iflib_rxd_flush;
662 static int iflib_verbose_debug;
664 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
665 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
667 &iflib_rx_intr_enables, 0, "# rx intr enables");
668 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
669 &iflib_fast_intrs, 0, "# fast_intr calls");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
671 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
673 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
675 &iflib_rx_if_input, 0, "# times rxeof called if_input");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
679 &iflib_rxd_flush, 0, "# times rxd_flush called");
680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
681 &iflib_verbose_debug, 0, "enable verbose debugging");
683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
685 iflib_debug_reset(void)
687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
689 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
690 iflib_txq_drain_notready =
691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
695 iflib_rx_ctx_inactive = iflib_rx_if_input =
696 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
700 #define DBG_COUNTER_INC(name)
701 static void iflib_debug_reset(void) {}
704 #define IFLIB_DEBUG 0
706 static void iflib_tx_structures_free(if_ctx_t ctx);
707 static void iflib_rx_structures_free(if_ctx_t ctx);
708 static int iflib_queues_alloc(if_ctx_t ctx);
709 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
710 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
711 static int iflib_qset_structures_setup(if_ctx_t ctx);
712 static int iflib_msix_init(if_ctx_t ctx);
713 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
714 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
715 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
717 static void iflib_altq_if_start(if_t ifp);
718 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
720 static int iflib_register(if_ctx_t);
721 static void iflib_init_locked(if_ctx_t ctx);
722 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
723 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
724 static void iflib_ifmp_purge(iflib_txq_t txq);
725 static void _iflib_pre_assert(if_softc_ctx_t scctx);
726 static void iflib_if_init_locked(if_ctx_t ctx);
727 static void iflib_free_intr_mem(if_ctx_t ctx);
728 #ifndef __NO_STRICT_ALIGNMENT
729 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
732 NETDUMP_DEFINE(iflib);
735 #include <sys/selinfo.h>
736 #include <net/netmap.h>
737 #include <dev/netmap/netmap_kern.h>
739 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
741 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
744 * device-specific sysctl variables:
746 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
747 * During regular operations the CRC is stripped, but on some
748 * hardware reception of frames not multiple of 64 is slower,
749 * so using crcstrip=0 helps in benchmarks.
751 * iflib_rx_miss, iflib_rx_miss_bufs:
752 * count packets that might be missed due to lost interrupts.
754 SYSCTL_DECL(_dev_netmap);
756 * The xl driver by default strips CRCs and we do not override it.
759 int iflib_crcstrip = 1;
760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
761 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
763 int iflib_rx_miss, iflib_rx_miss_bufs;
764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
765 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
767 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
770 * Register/unregister. We are already under netmap lock.
771 * Only called on the first register or the last unregister.
774 iflib_netmap_register(struct netmap_adapter *na, int onoff)
776 struct ifnet *ifp = na->ifp;
777 if_ctx_t ctx = ifp->if_softc;
781 IFDI_INTR_DISABLE(ctx);
783 /* Tell the stack that the interface is no longer active */
784 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
787 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
789 /* enable or disable flags and callbacks in na and ifp */
791 nm_set_native_flags(na);
793 nm_clear_native_flags(na);
796 iflib_init_locked(ctx);
797 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
798 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
800 nm_clear_native_flags(na);
806 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
808 struct netmap_adapter *na = kring->na;
809 u_int const lim = kring->nkr_num_slots - 1;
810 u_int head = kring->rhead;
811 struct netmap_ring *ring = kring->ring;
813 struct if_rxd_update iru;
814 if_ctx_t ctx = rxq->ifr_ctx;
815 iflib_fl_t fl = &rxq->ifr_fl[0];
816 uint32_t refill_pidx, nic_i;
817 #if IFLIB_DEBUG_COUNTERS
821 if (nm_i == head && __predict_true(!init))
823 iru_init(&iru, rxq, 0 /* flid */);
824 map = fl->ifl_sds.ifsd_map;
825 refill_pidx = netmap_idx_k2n(kring, nm_i);
827 * IMPORTANT: we must leave one free slot in the ring,
828 * so move head back by one unit
830 head = nm_prev(head, lim);
832 DBG_COUNTER_INC(fl_refills);
833 while (nm_i != head) {
834 #if IFLIB_DEBUG_COUNTERS
836 DBG_COUNTER_INC(fl_refills_large);
838 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
839 struct netmap_slot *slot = &ring->slot[nm_i];
840 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
841 uint32_t nic_i_dma = refill_pidx;
842 nic_i = netmap_idx_k2n(kring, nm_i);
844 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
846 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
847 return netmap_ring_reinit(kring);
849 fl->ifl_vm_addrs[tmp_pidx] = addr;
850 if (__predict_false(init) && map) {
851 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
852 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
853 /* buffer has changed, reload map */
854 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
856 slot->flags &= ~NS_BUF_CHANGED;
858 nm_i = nm_next(nm_i, lim);
859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
863 iru.iru_pidx = refill_pidx;
864 iru.iru_count = tmp_pidx+1;
865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
871 for (int n = 0; n < iru.iru_count; n++) {
872 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
873 BUS_DMASYNC_PREREAD);
874 /* XXX - change this to not use the netmap func*/
875 nic_i_dma = nm_next(nic_i_dma, lim);
879 kring->nr_hwcur = head;
882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
884 if (__predict_true(nic_i != UINT_MAX)) {
885 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
886 DBG_COUNTER_INC(rxd_flush);
892 * Reconcile kernel and user view of the transmit ring.
894 * All information is in the kring.
895 * Userspace wants to send packets up to the one before kring->rhead,
896 * kernel knows kring->nr_hwcur is the first unsent packet.
898 * Here we push packets out (as many as possible), and possibly
899 * reclaim buffers from previously completed transmission.
901 * The caller (netmap) guarantees that there is only one instance
902 * running at any time. Any interference with other driver
903 * methods should be handled by the individual drivers.
906 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
908 struct netmap_adapter *na = kring->na;
909 struct ifnet *ifp = na->ifp;
910 struct netmap_ring *ring = kring->ring;
911 u_int nm_i; /* index into the netmap kring */
912 u_int nic_i; /* index into the NIC ring */
914 u_int const lim = kring->nkr_num_slots - 1;
915 u_int const head = kring->rhead;
916 struct if_pkt_info pi;
919 * interrupts on every tx packet are expensive so request
920 * them every half ring, or where NS_REPORT is set
922 u_int report_frequency = kring->nkr_num_slots >> 1;
923 /* device-specific */
924 if_ctx_t ctx = ifp->if_softc;
925 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
927 bus_dmamap_sync(txq->ift_buf_tag, txq->ift_ifdi->idi_map,
928 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
931 * First part: process new packets to send.
932 * nm_i is the current index in the netmap kring,
933 * nic_i is the corresponding index in the NIC ring.
935 * If we have packets to send (nm_i != head)
936 * iterate over the netmap ring, fetch length and update
937 * the corresponding slot in the NIC ring. Some drivers also
938 * need to update the buffer's physical address in the NIC slot
939 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
941 * The netmap_reload_map() calls is especially expensive,
942 * even when (as in this case) the tag is 0, so do only
943 * when the buffer has actually changed.
945 * If possible do not set the report/intr bit on all slots,
946 * but only a few times per ring or when NS_REPORT is set.
948 * Finally, on 10G and faster drivers, it might be useful
949 * to prefetch the next slot and txr entry.
952 nm_i = kring->nr_hwcur;
953 if (nm_i != head) { /* we have new packets to send */
955 pi.ipi_segs = txq->ift_segs;
956 pi.ipi_qsidx = kring->ring_id;
957 nic_i = netmap_idx_k2n(kring, nm_i);
959 __builtin_prefetch(&ring->slot[nm_i]);
960 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
961 if (txq->ift_sds.ifsd_map)
962 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
964 for (n = 0; nm_i != head; n++) {
965 struct netmap_slot *slot = &ring->slot[nm_i];
966 u_int len = slot->len;
968 void *addr = PNMB(na, slot, &paddr);
969 int flags = (slot->flags & NS_REPORT ||
970 nic_i == 0 || nic_i == report_frequency) ?
973 /* device-specific */
975 pi.ipi_segs[0].ds_addr = paddr;
976 pi.ipi_segs[0].ds_len = len;
980 pi.ipi_flags = flags;
982 /* Fill the slot in the NIC ring. */
983 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
984 DBG_COUNTER_INC(tx_encap);
986 /* prefetch for next round */
987 __builtin_prefetch(&ring->slot[nm_i + 1]);
988 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
989 if (txq->ift_sds.ifsd_map) {
990 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
992 NM_CHECK_ADDR_LEN(na, addr, len);
994 if (slot->flags & NS_BUF_CHANGED) {
995 /* buffer has changed, reload map */
996 netmap_reload_map(na, txq->ift_buf_tag,
997 txq->ift_sds.ifsd_map[nic_i], addr);
999 /* make sure changes to the buffer are synced */
1000 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1001 BUS_DMASYNC_PREWRITE);
1003 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1004 nm_i = nm_next(nm_i, lim);
1005 nic_i = nm_next(nic_i, lim);
1007 kring->nr_hwcur = nm_i;
1009 /* synchronize the NIC ring */
1010 bus_dmamap_sync(txq->ift_buf_tag, txq->ift_ifdi->idi_map,
1011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1013 /* (re)start the tx unit up to slot nic_i (excluded) */
1014 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1018 * Second part: reclaim buffers for completed transmissions.
1020 * If there are unclaimed buffers, attempt to reclaim them.
1021 * If none are reclaimed, and TX IRQs are not in use, do an initial
1022 * minimal delay, then trigger the tx handler which will spin in the
1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1026 if (iflib_tx_credits_update(ctx, txq)) {
1027 /* some tx completed, increment avail */
1028 nic_i = txq->ift_cidx_processed;
1029 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1032 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1033 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1034 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1035 iflib_timer, txq, txq->ift_timer.c_cpu);
1041 * Reconcile kernel and user view of the receive ring.
1042 * Same as for the txsync, this routine must be efficient.
1043 * The caller guarantees a single invocations, but races against
1044 * the rest of the driver should be handled here.
1046 * On call, kring->rhead is the first packet that userspace wants
1047 * to keep, and kring->rcur is the wakeup point.
1048 * The kernel has previously reported packets up to kring->rtail.
1050 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1051 * of whether or not we received an interrupt.
1054 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1056 struct netmap_adapter *na = kring->na;
1057 struct netmap_ring *ring = kring->ring;
1058 uint32_t nm_i; /* index into the netmap ring */
1059 uint32_t nic_i; /* index into the NIC ring */
1061 u_int const lim = kring->nkr_num_slots - 1;
1062 u_int const head = kring->rhead;
1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1064 struct if_rxd_info ri;
1066 struct ifnet *ifp = na->ifp;
1067 if_ctx_t ctx = ifp->if_softc;
1068 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1069 iflib_fl_t fl = rxq->ifr_fl;
1071 return netmap_ring_reinit(kring);
1073 /* XXX check sync modes */
1074 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1075 if (fl->ifl_sds.ifsd_map == NULL)
1077 bus_dmamap_sync(rxq->ifr_fl[i].ifl_buf_tag,
1078 fl->ifl_ifdi->idi_map,
1079 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1082 * First part: import newly received packets.
1084 * nm_i is the index of the next free slot in the netmap ring,
1085 * nic_i is the index of the next received packet in the NIC ring,
1086 * and they may differ in case if_init() has been called while
1087 * in netmap mode. For the receive ring we have
1089 * nic_i = rxr->next_check;
1090 * nm_i = kring->nr_hwtail (previous)
1092 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1094 * rxr->next_check is set to 0 on a ring reinit
1096 if (netmap_no_pendintr || force_update) {
1097 int crclen = iflib_crcstrip ? 0 : 4;
1100 for (i = 0; i < rxq->ifr_nfl; i++) {
1101 fl = &rxq->ifr_fl[i];
1102 nic_i = fl->ifl_cidx;
1103 nm_i = netmap_idx_n2k(kring, nic_i);
1104 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1105 for (n = 0; avail > 0; n++, avail--) {
1107 ri.iri_frags = rxq->ifr_frags;
1108 ri.iri_qsidx = kring->ring_id;
1109 ri.iri_ifp = ctx->ifc_ifp;
1110 ri.iri_cidx = nic_i;
1112 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1113 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1114 ring->slot[nm_i].flags = 0;
1115 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1116 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1117 nm_i = nm_next(nm_i, lim);
1118 nic_i = nm_next(nic_i, lim);
1120 if (n) { /* update the state variables */
1121 if (netmap_no_pendintr && !force_update) {
1124 iflib_rx_miss_bufs += n;
1126 fl->ifl_cidx = nic_i;
1127 kring->nr_hwtail = nm_i;
1129 kring->nr_kflags &= ~NKR_PENDINTR;
1133 * Second part: skip past packets that userspace has released.
1134 * (kring->nr_hwcur to head excluded),
1135 * and make the buffers available for reception.
1136 * As usual nm_i is the index in the netmap ring,
1137 * nic_i is the index in the NIC ring, and
1138 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1140 /* XXX not sure how this will work with multiple free lists */
1141 nm_i = kring->nr_hwcur;
1143 return (netmap_fl_refill(rxq, kring, nm_i, false));
1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1149 struct ifnet *ifp = na->ifp;
1150 if_ctx_t ctx = ifp->if_softc;
1154 IFDI_INTR_ENABLE(ctx);
1156 IFDI_INTR_DISABLE(ctx);
1163 iflib_netmap_attach(if_ctx_t ctx)
1165 struct netmap_adapter na;
1166 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1168 bzero(&na, sizeof(na));
1170 na.ifp = ctx->ifc_ifp;
1171 na.na_flags = NAF_BDG_MAYSLEEP;
1172 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1173 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1175 na.num_tx_desc = scctx->isc_ntxd[0];
1176 na.num_rx_desc = scctx->isc_nrxd[0];
1177 na.nm_txsync = iflib_netmap_txsync;
1178 na.nm_rxsync = iflib_netmap_rxsync;
1179 na.nm_register = iflib_netmap_register;
1180 na.nm_intr = iflib_netmap_intr;
1181 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1182 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1183 return (netmap_attach(&na));
1187 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1189 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1190 struct netmap_slot *slot;
1192 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1195 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1198 * In netmap mode, set the map for the packet buffer.
1199 * NOTE: Some drivers (not this one) also need to set
1200 * the physical buffer address in the NIC ring.
1201 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1202 * netmap slot index, si
1204 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1205 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1206 NMB(na, slot + si));
1211 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1213 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1214 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1215 struct netmap_slot *slot;
1218 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1221 nm_i = netmap_idx_n2k(kring, 0);
1222 netmap_fl_refill(rxq, kring, nm_i, true);
1226 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1228 struct netmap_kring *kring;
1230 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1232 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1233 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1234 netmap_tx_irq(ctx->ifc_ifp, txqid);
1235 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1239 *reset_on = hz / 1000;
1244 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1247 #define iflib_netmap_txq_init(ctx, txq)
1248 #define iflib_netmap_rxq_init(ctx, rxq)
1249 #define iflib_netmap_detach(ifp)
1251 #define iflib_netmap_attach(ctx) (0)
1252 #define netmap_rx_irq(ifp, qid, budget) (0)
1253 #define netmap_tx_irq(ifp, qid) do {} while (0)
1254 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1258 #if defined(__i386__) || defined(__amd64__)
1259 static __inline void
1262 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1264 static __inline void
1265 prefetch2cachelines(void *x)
1267 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1268 #if (CACHE_LINE_SIZE < 128)
1269 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1274 #define prefetch2cachelines(x)
1278 iflib_gen_mac(if_ctx_t ctx)
1282 char uuid[HOSTUUIDLEN+1];
1283 char buf[HOSTUUIDLEN+16];
1285 unsigned char digest[16];
1289 uuid[HOSTUUIDLEN] = 0;
1290 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1291 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1293 * Generate a pseudo-random, deterministic MAC
1294 * address based on the UUID and unit number.
1295 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1298 MD5Update(&mdctx, buf, strlen(buf));
1299 MD5Final(digest, &mdctx);
1310 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1314 fl = &rxq->ifr_fl[flid];
1315 iru->iru_paddrs = fl->ifl_bus_addrs;
1316 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1317 iru->iru_idxs = fl->ifl_rxd_idxs;
1318 iru->iru_qsidx = rxq->ifr_id;
1319 iru->iru_buf_size = fl->ifl_buf_size;
1320 iru->iru_flidx = fl->ifl_id;
1324 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1328 *(bus_addr_t *) arg = segs[0].ds_addr;
1332 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1335 if_shared_ctx_t sctx = ctx->ifc_sctx;
1336 device_t dev = ctx->ifc_dev;
1338 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1340 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1341 sctx->isc_q_align, 0, /* alignment, bounds */
1342 BUS_SPACE_MAXADDR, /* lowaddr */
1343 BUS_SPACE_MAXADDR, /* highaddr */
1344 NULL, NULL, /* filter, filterarg */
1347 size, /* maxsegsize */
1348 BUS_DMA_ALLOCNOW, /* flags */
1349 NULL, /* lockfunc */
1354 "%s: bus_dma_tag_create failed: %d\n",
1359 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1360 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1363 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1364 __func__, (uintmax_t)size, err);
1368 dma->idi_paddr = IF_BAD_DMA;
1369 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1370 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1371 if (err || dma->idi_paddr == IF_BAD_DMA) {
1373 "%s: bus_dmamap_load failed: %d\n",
1378 dma->idi_size = size;
1382 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1384 bus_dma_tag_destroy(dma->idi_tag);
1386 dma->idi_tag = NULL;
1392 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1395 iflib_dma_info_t *dmaiter;
1398 for (i = 0; i < count; i++, dmaiter++) {
1399 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1403 iflib_dma_free_multi(dmalist, i);
1408 iflib_dma_free(iflib_dma_info_t dma)
1410 if (dma->idi_tag == NULL)
1412 if (dma->idi_paddr != IF_BAD_DMA) {
1413 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1414 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1415 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1416 dma->idi_paddr = IF_BAD_DMA;
1418 if (dma->idi_vaddr != NULL) {
1419 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1420 dma->idi_vaddr = NULL;
1422 bus_dma_tag_destroy(dma->idi_tag);
1423 dma->idi_tag = NULL;
1427 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1430 iflib_dma_info_t *dmaiter = dmalist;
1432 for (i = 0; i < count; i++, dmaiter++)
1433 iflib_dma_free(*dmaiter);
1436 #ifdef EARLY_AP_STARTUP
1437 static const int iflib_started = 1;
1440 * We used to abuse the smp_started flag to decide if the queues have been
1441 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1442 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1443 * is set. Run a SYSINIT() strictly after that to just set a usable
1447 static int iflib_started;
1450 iflib_record_started(void *arg)
1455 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1456 iflib_record_started, NULL);
1460 iflib_fast_intr(void *arg)
1462 iflib_filter_info_t info = arg;
1463 struct grouptask *gtask = info->ifi_task;
1465 return (FILTER_HANDLED);
1467 DBG_COUNTER_INC(fast_intrs);
1468 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1469 return (FILTER_HANDLED);
1471 GROUPTASK_ENQUEUE(gtask);
1472 return (FILTER_HANDLED);
1476 iflib_fast_intr_rxtx(void *arg)
1478 iflib_filter_info_t info = arg;
1479 struct grouptask *gtask = info->ifi_task;
1480 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1481 if_ctx_t ctx = NULL;;
1485 return (FILTER_HANDLED);
1487 DBG_COUNTER_INC(fast_intrs);
1488 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1489 return (FILTER_HANDLED);
1491 MPASS(rxq->ifr_ntxqirq);
1492 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1493 qidx_t txqid = rxq->ifr_txqid[i];
1497 bus_dmamap_sync(rxq->ifr_ifdi->idi_tag, rxq->ifr_ifdi->idi_map,
1498 BUS_DMASYNC_POSTREAD);
1499 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1500 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1503 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1505 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1506 cidx = rxq->ifr_cq_cidx;
1508 cidx = rxq->ifr_fl[0].ifl_cidx;
1509 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1510 GROUPTASK_ENQUEUE(gtask);
1512 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1513 DBG_COUNTER_INC(rx_intr_enables);
1515 return (FILTER_HANDLED);
1520 iflib_fast_intr_ctx(void *arg)
1522 iflib_filter_info_t info = arg;
1523 struct grouptask *gtask = info->ifi_task;
1526 return (FILTER_HANDLED);
1528 DBG_COUNTER_INC(fast_intrs);
1529 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1530 return (FILTER_HANDLED);
1532 GROUPTASK_ENQUEUE(gtask);
1533 return (FILTER_HANDLED);
1537 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1538 driver_filter_t filter, driver_intr_t handler, void *arg,
1542 struct resource *res;
1544 device_t dev = ctx->ifc_dev;
1547 if (ctx->ifc_flags & IFC_LEGACY)
1548 flags |= RF_SHAREABLE;
1551 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1554 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1558 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1559 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1560 filter, handler, arg, &tag);
1563 "failed to setup interrupt for rid %d, name %s: %d\n",
1564 rid, name ? name : "unknown", rc);
1567 bus_describe_intr(dev, res, tag, "%s", name);
1574 /*********************************************************************
1576 * Allocate DMA resources for TX buffers as well as memory for the TX
1577 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1578 * iflib_sw_tx_desc_array structure, storing all the information that
1579 * is needed to transmit a packet on the wire. This is called only
1580 * once at attach, setup is done every reset.
1582 **********************************************************************/
1584 iflib_txsd_alloc(iflib_txq_t txq)
1586 if_ctx_t ctx = txq->ift_ctx;
1587 if_shared_ctx_t sctx = ctx->ifc_sctx;
1588 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1589 device_t dev = ctx->ifc_dev;
1590 bus_size_t tsomaxsize;
1591 int err, nsegments, ntsosegments;
1594 nsegments = scctx->isc_tx_nsegments;
1595 ntsosegments = scctx->isc_tx_tso_segments_max;
1596 tsomaxsize = scctx->isc_tx_tso_size_max;
1597 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1598 tsomaxsize += sizeof(struct ether_vlan_header);
1599 MPASS(scctx->isc_ntxd[0] > 0);
1600 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1601 MPASS(nsegments > 0);
1602 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1603 MPASS(ntsosegments > 0);
1604 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1608 * Set up DMA tags for TX buffers.
1610 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1611 1, 0, /* alignment, bounds */
1612 BUS_SPACE_MAXADDR, /* lowaddr */
1613 BUS_SPACE_MAXADDR, /* highaddr */
1614 NULL, NULL, /* filter, filterarg */
1615 sctx->isc_tx_maxsize, /* maxsize */
1616 nsegments, /* nsegments */
1617 sctx->isc_tx_maxsegsize, /* maxsegsize */
1619 NULL, /* lockfunc */
1620 NULL, /* lockfuncarg */
1621 &txq->ift_buf_tag))) {
1622 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1623 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1624 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1627 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1628 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1629 1, 0, /* alignment, bounds */
1630 BUS_SPACE_MAXADDR, /* lowaddr */
1631 BUS_SPACE_MAXADDR, /* highaddr */
1632 NULL, NULL, /* filter, filterarg */
1633 tsomaxsize, /* maxsize */
1634 ntsosegments, /* nsegments */
1635 sctx->isc_tso_maxsegsize,/* maxsegsize */
1637 NULL, /* lockfunc */
1638 NULL, /* lockfuncarg */
1639 &txq->ift_tso_buf_tag))) {
1640 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1645 /* Allocate memory for the TX mbuf map. */
1646 if (!(txq->ift_sds.ifsd_m =
1647 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1648 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1649 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1655 * Create the DMA maps for TX buffers.
1657 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1658 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1659 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1661 "Unable to allocate TX buffer DMA map memory\n");
1665 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1666 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1667 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1669 "Unable to allocate TSO TX buffer map memory\n");
1673 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1674 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1675 &txq->ift_sds.ifsd_map[i]);
1677 device_printf(dev, "Unable to create TX DMA map\n");
1682 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1683 &txq->ift_sds.ifsd_tso_map[i]);
1685 device_printf(dev, "Unable to create TSO TX DMA map\n");
1691 /* We free all, it handles case where we are in the middle */
1692 iflib_tx_structures_free(ctx);
1697 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1702 if (txq->ift_sds.ifsd_map != NULL)
1703 map = txq->ift_sds.ifsd_map[i];
1705 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1706 bus_dmamap_unload(txq->ift_buf_tag, map);
1707 bus_dmamap_destroy(txq->ift_buf_tag, map);
1708 txq->ift_sds.ifsd_map[i] = NULL;
1712 if (txq->ift_sds.ifsd_tso_map != NULL)
1713 map = txq->ift_sds.ifsd_tso_map[i];
1715 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1716 BUS_DMASYNC_POSTWRITE);
1717 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1718 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1719 txq->ift_sds.ifsd_tso_map[i] = NULL;
1724 iflib_txq_destroy(iflib_txq_t txq)
1726 if_ctx_t ctx = txq->ift_ctx;
1728 for (int i = 0; i < txq->ift_size; i++)
1729 iflib_txsd_destroy(ctx, txq, i);
1730 if (txq->ift_sds.ifsd_map != NULL) {
1731 free(txq->ift_sds.ifsd_map, M_IFLIB);
1732 txq->ift_sds.ifsd_map = NULL;
1734 if (txq->ift_sds.ifsd_tso_map != NULL) {
1735 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1736 txq->ift_sds.ifsd_tso_map = NULL;
1738 if (txq->ift_sds.ifsd_m != NULL) {
1739 free(txq->ift_sds.ifsd_m, M_IFLIB);
1740 txq->ift_sds.ifsd_m = NULL;
1742 if (txq->ift_buf_tag != NULL) {
1743 bus_dma_tag_destroy(txq->ift_buf_tag);
1744 txq->ift_buf_tag = NULL;
1746 if (txq->ift_tso_buf_tag != NULL) {
1747 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1748 txq->ift_tso_buf_tag = NULL;
1753 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1757 mp = &txq->ift_sds.ifsd_m[i];
1761 if (txq->ift_sds.ifsd_map != NULL) {
1762 bus_dmamap_sync(txq->ift_buf_tag,
1763 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1764 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1766 if (txq->ift_sds.ifsd_tso_map != NULL) {
1767 bus_dmamap_sync(txq->ift_tso_buf_tag,
1768 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1769 bus_dmamap_unload(txq->ift_tso_buf_tag,
1770 txq->ift_sds.ifsd_tso_map[i]);
1773 DBG_COUNTER_INC(tx_frees);
1778 iflib_txq_setup(iflib_txq_t txq)
1780 if_ctx_t ctx = txq->ift_ctx;
1781 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1782 if_shared_ctx_t sctx = ctx->ifc_sctx;
1783 iflib_dma_info_t di;
1786 /* Set number of descriptors available */
1787 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1788 /* XXX make configurable */
1789 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1792 txq->ift_cidx_processed = 0;
1793 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1794 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1796 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1797 bzero((void *)di->idi_vaddr, di->idi_size);
1799 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1800 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1801 bus_dmamap_sync(di->idi_tag, di->idi_map,
1802 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1806 /*********************************************************************
1808 * Allocate DMA resources for RX buffers as well as memory for the RX
1809 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1810 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1811 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1812 * Since we use use one entry in iflib_sw_rx_desc_array per received
1813 * packet, the maximum number of entries we'll need is equal to the
1814 * number of hardware receive descriptors that we've allocated.
1816 **********************************************************************/
1818 iflib_rxsd_alloc(iflib_rxq_t rxq)
1820 if_ctx_t ctx = rxq->ifr_ctx;
1821 if_shared_ctx_t sctx = ctx->ifc_sctx;
1822 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1823 device_t dev = ctx->ifc_dev;
1827 MPASS(scctx->isc_nrxd[0] > 0);
1828 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1831 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1832 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1833 /* Set up DMA tag for RX buffers. */
1834 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1835 1, 0, /* alignment, bounds */
1836 BUS_SPACE_MAXADDR, /* lowaddr */
1837 BUS_SPACE_MAXADDR, /* highaddr */
1838 NULL, NULL, /* filter, filterarg */
1839 sctx->isc_rx_maxsize, /* maxsize */
1840 sctx->isc_rx_nsegments, /* nsegments */
1841 sctx->isc_rx_maxsegsize, /* maxsegsize */
1843 NULL, /* lockfunc */
1848 "Unable to allocate RX DMA tag: %d\n", err);
1852 /* Allocate memory for the RX mbuf map. */
1853 if (!(fl->ifl_sds.ifsd_m =
1854 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1855 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1857 "Unable to allocate RX mbuf map memory\n");
1862 /* Allocate memory for the direct RX cluster pointer map. */
1863 if (!(fl->ifl_sds.ifsd_cl =
1864 (caddr_t *) malloc(sizeof(caddr_t) *
1865 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1867 "Unable to allocate RX cluster map memory\n");
1872 /* Allocate memory for the RX cluster bus address map. */
1873 if (!(fl->ifl_sds.ifsd_ba =
1874 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1875 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1877 "Unable to allocate RX bus address map memory\n");
1883 * Create the DMA maps for RX buffers.
1885 if (!(fl->ifl_sds.ifsd_map =
1886 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1888 "Unable to allocate RX buffer DMA map memory\n");
1892 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1893 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1894 &fl->ifl_sds.ifsd_map[i]);
1896 device_printf(dev, "Unable to create RX buffer DMA map\n");
1904 iflib_rx_structures_free(ctx);
1910 * Internal service routines
1913 struct rxq_refill_cb_arg {
1915 bus_dma_segment_t seg;
1920 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1922 struct rxq_refill_cb_arg *cb_arg = arg;
1924 cb_arg->error = error;
1925 cb_arg->seg = segs[0];
1926 cb_arg->nseg = nseg;
1930 * rxq_refill - refill an rxq free-buffer list
1931 * @ctx: the iflib context
1932 * @rxq: the free-list to refill
1933 * @n: the number of new buffers to allocate
1935 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1936 * The caller must assure that @n does not exceed the queue's capacity.
1939 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1941 struct if_rxd_update iru;
1942 struct rxq_refill_cb_arg cb_arg;
1946 bus_dmamap_t *sd_map;
1947 bus_addr_t bus_addr, *sd_ba;
1948 int err, frag_idx, i, idx, n, pidx;
1951 sd_m = fl->ifl_sds.ifsd_m;
1952 sd_map = fl->ifl_sds.ifsd_map;
1953 sd_cl = fl->ifl_sds.ifsd_cl;
1954 sd_ba = fl->ifl_sds.ifsd_ba;
1955 pidx = fl->ifl_pidx;
1957 frag_idx = fl->ifl_fragidx;
1958 credits = fl->ifl_credits;
1963 MPASS(credits + n <= fl->ifl_size);
1965 if (pidx < fl->ifl_cidx)
1966 MPASS(pidx + n <= fl->ifl_cidx);
1967 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1968 MPASS(fl->ifl_gen == 0);
1969 if (pidx > fl->ifl_cidx)
1970 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1972 DBG_COUNTER_INC(fl_refills);
1974 DBG_COUNTER_INC(fl_refills_large);
1975 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1978 * We allocate an uninitialized mbuf + cluster, mbuf is
1979 * initialized after rx.
1981 * If the cluster is still set then we know a minimum sized packet was received
1983 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1986 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1987 MPASS(frag_idx >= 0);
1988 if ((cl = sd_cl[frag_idx]) == NULL) {
1989 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1993 MPASS(sd_map != NULL);
1994 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1995 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1997 if (err != 0 || cb_arg.error) {
2001 if (fl->ifl_zone == zone_pack)
2002 uma_zfree(fl->ifl_zone, cl);
2006 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2007 BUS_DMASYNC_PREREAD);
2008 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2009 sd_cl[frag_idx] = cl;
2011 fl->ifl_cl_enqueued++;
2014 bus_addr = sd_ba[frag_idx];
2017 MPASS(sd_m[frag_idx] == NULL);
2018 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2022 bit_set(fl->ifl_rx_bitmap, frag_idx);
2024 fl->ifl_m_enqueued++;
2027 DBG_COUNTER_INC(rx_allocs);
2028 fl->ifl_rxd_idxs[i] = frag_idx;
2029 fl->ifl_bus_addrs[i] = bus_addr;
2030 fl->ifl_vm_addrs[i] = cl;
2033 MPASS(credits <= fl->ifl_size);
2034 if (++idx == fl->ifl_size) {
2038 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2039 iru.iru_pidx = pidx;
2041 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2045 fl->ifl_credits = credits;
2050 iru.iru_pidx = pidx;
2052 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2054 fl->ifl_credits = credits;
2056 DBG_COUNTER_INC(rxd_flush);
2057 if (fl->ifl_pidx == 0)
2058 pidx = fl->ifl_size - 1;
2060 pidx = fl->ifl_pidx - 1;
2062 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2063 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2064 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2065 fl->ifl_fragidx = frag_idx;
2068 static __inline void
2069 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2071 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2072 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2074 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2077 MPASS(fl->ifl_credits <= fl->ifl_size);
2078 MPASS(reclaimable == delta);
2080 if (reclaimable > 0)
2081 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2085 iflib_in_detach(if_ctx_t ctx)
2089 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2095 iflib_fl_bufs_free(iflib_fl_t fl)
2097 iflib_dma_info_t idi = fl->ifl_ifdi;
2098 bus_dmamap_t sd_map;
2101 for (i = 0; i < fl->ifl_size; i++) {
2102 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2103 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2105 if (*sd_cl != NULL) {
2106 sd_map = fl->ifl_sds.ifsd_map[i];
2107 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2108 BUS_DMASYNC_POSTREAD);
2109 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2111 uma_zfree(fl->ifl_zone, *sd_cl);
2112 // XXX: Should this get moved out?
2113 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2114 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2115 if (*sd_m != NULL) {
2116 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2117 uma_zfree(zone_mbuf, *sd_m);
2120 MPASS(*sd_cl == NULL);
2121 MPASS(*sd_m == NULL);
2124 fl->ifl_m_dequeued++;
2125 fl->ifl_cl_dequeued++;
2131 for (i = 0; i < fl->ifl_size; i++) {
2132 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2133 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2137 * Reset free list values
2139 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2140 bzero(idi->idi_vaddr, idi->idi_size);
2143 /*********************************************************************
2145 * Initialize a receive ring and its buffers.
2147 **********************************************************************/
2149 iflib_fl_setup(iflib_fl_t fl)
2151 iflib_rxq_t rxq = fl->ifl_rxq;
2152 if_ctx_t ctx = rxq->ifr_ctx;
2153 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2155 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2157 ** Free current RX buffer structs and their mbufs
2159 iflib_fl_bufs_free(fl);
2160 /* Now replenish the mbufs */
2161 MPASS(fl->ifl_credits == 0);
2163 * XXX don't set the max_frame_size to larger
2164 * than the hardware can handle
2166 if (sctx->isc_max_frame_size <= 2048)
2167 fl->ifl_buf_size = MCLBYTES;
2168 #ifndef CONTIGMALLOC_WORKS
2170 fl->ifl_buf_size = MJUMPAGESIZE;
2172 else if (sctx->isc_max_frame_size <= 4096)
2173 fl->ifl_buf_size = MJUMPAGESIZE;
2174 else if (sctx->isc_max_frame_size <= 9216)
2175 fl->ifl_buf_size = MJUM9BYTES;
2177 fl->ifl_buf_size = MJUM16BYTES;
2179 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2180 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2181 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2182 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2185 /* avoid pre-allocating zillions of clusters to an idle card
2186 * potentially speeding up attach
2188 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2189 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2190 if (min(128, fl->ifl_size) != fl->ifl_credits)
2196 MPASS(fl->ifl_ifdi != NULL);
2197 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2198 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2202 /*********************************************************************
2204 * Free receive ring data structures
2206 **********************************************************************/
2208 iflib_rx_sds_free(iflib_rxq_t rxq)
2213 if (rxq->ifr_fl != NULL) {
2214 for (i = 0; i < rxq->ifr_nfl; i++) {
2215 fl = &rxq->ifr_fl[i];
2216 if (fl->ifl_buf_tag != NULL) {
2217 if (fl->ifl_sds.ifsd_map != NULL) {
2218 for (j = 0; j < fl->ifl_size; j++) {
2219 if (fl->ifl_sds.ifsd_map[j] ==
2224 fl->ifl_sds.ifsd_map[j],
2225 BUS_DMASYNC_POSTREAD);
2228 fl->ifl_sds.ifsd_map[j]);
2231 bus_dma_tag_destroy(fl->ifl_buf_tag);
2232 fl->ifl_buf_tag = NULL;
2234 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2235 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2236 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2237 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2238 fl->ifl_sds.ifsd_m = NULL;
2239 fl->ifl_sds.ifsd_cl = NULL;
2240 fl->ifl_sds.ifsd_ba = NULL;
2241 fl->ifl_sds.ifsd_map = NULL;
2243 free(rxq->ifr_fl, M_IFLIB);
2245 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2250 * MI independent logic
2254 iflib_timer(void *arg)
2256 iflib_txq_t txq = arg;
2257 if_ctx_t ctx = txq->ift_ctx;
2258 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2259 uint64_t this_tick = ticks;
2260 uint32_t reset_on = hz / 2;
2262 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2265 ** Check on the state of the TX queue(s), this
2266 ** can be done without the lock because its RO
2267 ** and the HUNG state will be static if set.
2269 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2270 txq->ift_last_timer_tick = this_tick;
2271 IFDI_TIMER(ctx, txq->ift_id);
2272 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2273 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2274 (sctx->isc_pause_frames == 0)))
2277 if (ifmp_ring_is_stalled(txq->ift_br))
2278 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2279 txq->ift_cleaned_prev = txq->ift_cleaned;
2282 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2283 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2285 /* handle any laggards */
2286 if (txq->ift_db_pending)
2287 GROUPTASK_ENQUEUE(&txq->ift_task);
2289 sctx->isc_pause_frames = 0;
2290 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2291 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2294 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2295 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2297 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2298 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2299 iflib_admin_intr_deferred(ctx);
2304 iflib_init_locked(if_ctx_t ctx)
2306 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2307 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2308 if_t ifp = ctx->ifc_ifp;
2312 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2315 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2316 IFDI_INTR_DISABLE(ctx);
2318 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2319 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2320 /* Set hardware offload abilities */
2321 if_clearhwassist(ifp);
2322 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2323 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2324 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2325 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2326 if (if_getcapenable(ifp) & IFCAP_TSO4)
2327 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2328 if (if_getcapenable(ifp) & IFCAP_TSO6)
2329 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2331 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2333 callout_stop(&txq->ift_timer);
2334 CALLOUT_UNLOCK(txq);
2335 iflib_netmap_txq_init(ctx, txq);
2338 i = if_getdrvflags(ifp);
2341 MPASS(if_getdrvflags(ifp) == i);
2342 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2343 /* XXX this should really be done on a per-queue basis */
2344 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2345 MPASS(rxq->ifr_id == i);
2346 iflib_netmap_rxq_init(ctx, rxq);
2349 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2350 if (iflib_fl_setup(fl)) {
2351 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2357 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2358 IFDI_INTR_ENABLE(ctx);
2359 txq = ctx->ifc_txqs;
2360 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2361 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2362 txq->ift_timer.c_cpu);
2366 iflib_media_change(if_t ifp)
2368 if_ctx_t ctx = if_getsoftc(ifp);
2372 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2373 iflib_init_locked(ctx);
2379 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2381 if_ctx_t ctx = if_getsoftc(ifp);
2384 IFDI_UPDATE_ADMIN_STATUS(ctx);
2385 IFDI_MEDIA_STATUS(ctx, ifmr);
2390 iflib_stop(if_ctx_t ctx)
2392 iflib_txq_t txq = ctx->ifc_txqs;
2393 iflib_rxq_t rxq = ctx->ifc_rxqs;
2394 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2395 if_shared_ctx_t sctx = ctx->ifc_sctx;
2396 iflib_dma_info_t di;
2400 /* Tell the stack that the interface is no longer active */
2401 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2403 IFDI_INTR_DISABLE(ctx);
2408 iflib_debug_reset();
2409 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2410 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2411 /* make sure all transmitters have completed before proceeding XXX */
2414 callout_stop(&txq->ift_timer);
2415 CALLOUT_UNLOCK(txq);
2417 /* clean any enqueued buffers */
2418 iflib_ifmp_purge(txq);
2419 /* Free any existing tx buffers. */
2420 for (j = 0; j < txq->ift_size; j++) {
2421 iflib_txsd_free(ctx, txq, j);
2423 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2424 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2425 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2426 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2427 txq->ift_pullups = 0;
2428 ifmp_ring_reset_stats(txq->ift_br);
2429 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2430 bzero((void *)di->idi_vaddr, di->idi_size);
2432 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2433 /* make sure all transmitters have completed before proceeding XXX */
2435 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2436 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2437 bzero((void *)di->idi_vaddr, di->idi_size);
2438 /* also resets the free lists pidx/cidx */
2439 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2440 iflib_fl_bufs_free(fl);
2444 static inline caddr_t
2445 calc_next_rxd(iflib_fl_t fl, int cidx)
2449 caddr_t start, end, cur, next;
2451 nrxd = fl->ifl_size;
2452 size = fl->ifl_rxd_size;
2453 start = fl->ifl_ifdi->idi_vaddr;
2455 if (__predict_false(size == 0))
2457 cur = start + size*cidx;
2458 end = start + size*nrxd;
2459 next = CACHE_PTR_NEXT(cur);
2460 return (next < end ? next : start);
2464 prefetch_pkts(iflib_fl_t fl, int cidx)
2467 int nrxd = fl->ifl_size;
2471 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2472 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2473 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2474 next_rxd = calc_next_rxd(fl, cidx);
2476 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2477 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2478 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2479 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2480 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2481 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2482 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2483 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2487 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2492 iflib_dma_info_t di;
2496 flid = irf->irf_flid;
2497 cidx = irf->irf_idx;
2498 fl = &rxq->ifr_fl[flid];
2500 sd->ifsd_cidx = cidx;
2501 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2502 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2505 fl->ifl_m_dequeued++;
2507 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2508 prefetch_pkts(fl, cidx);
2509 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2510 prefetch(&fl->ifl_sds.ifsd_map[next]);
2511 map = fl->ifl_sds.ifsd_map[cidx];
2513 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2515 /* not valid assert if bxe really does SGE from non-contiguous elements */
2516 MPASS(fl->ifl_cidx == cidx);
2517 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2519 bus_dmamap_unload(fl->ifl_buf_tag, map);
2520 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2521 if (__predict_false(fl->ifl_cidx == 0))
2523 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2525 bit_clear(fl->ifl_rx_bitmap, cidx);
2528 static struct mbuf *
2529 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2531 int i, padlen , flags;
2532 struct mbuf *m, *mh, *mt;
2538 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2540 MPASS(*sd->ifsd_cl != NULL);
2541 MPASS(*sd->ifsd_m != NULL);
2543 /* Don't include zero-length frags */
2544 if (ri->iri_frags[i].irf_len == 0) {
2545 /* XXX we can save the cluster here, but not the mbuf */
2546 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2547 m_free(*sd->ifsd_m);
2554 flags = M_PKTHDR|M_EXT;
2556 padlen = ri->iri_pad;
2561 /* assuming padding is only on the first fragment */
2565 *sd->ifsd_cl = NULL;
2567 /* Can these two be made one ? */
2568 m_init(m, M_NOWAIT, MT_DATA, flags);
2569 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2571 * These must follow m_init and m_cljset
2573 m->m_data += padlen;
2574 ri->iri_len -= padlen;
2575 m->m_len = ri->iri_frags[i].irf_len;
2576 } while (++i < ri->iri_nfrags);
2582 * Process one software descriptor
2584 static struct mbuf *
2585 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2590 /* should I merge this back in now that the two paths are basically duplicated? */
2591 if (ri->iri_nfrags == 1 &&
2592 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2593 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2596 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2597 #ifndef __NO_STRICT_ALIGNMENT
2601 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2602 bus_dmamap_sync(rxq->ifr_fl->ifl_buf_tag,
2603 rxq->ifr_fl->ifl_sds.ifsd_map[ri->iri_frags[0].irf_idx],
2604 BUS_DMASYNC_PREREAD);
2605 m->m_len = ri->iri_frags[0].irf_len;
2607 m = assemble_segments(rxq, ri, &sd);
2609 m->m_pkthdr.len = ri->iri_len;
2610 m->m_pkthdr.rcvif = ri->iri_ifp;
2611 m->m_flags |= ri->iri_flags;
2612 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2613 m->m_pkthdr.flowid = ri->iri_flowid;
2614 M_HASHTYPE_SET(m, ri->iri_rsstype);
2615 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2616 m->m_pkthdr.csum_data = ri->iri_csum_data;
2620 #if defined(INET6) || defined(INET)
2622 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2624 CURVNET_SET(lc->ifp->if_vnet);
2626 *v6 = VNET(ip6_forwarding);
2629 *v4 = VNET(ipforwarding);
2635 * Returns true if it's possible this packet could be LROed.
2636 * if it returns false, it is guaranteed that tcp_lro_rx()
2637 * would not return zero.
2640 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2642 struct ether_header *eh;
2645 eh = mtod(m, struct ether_header *);
2646 eh_type = ntohs(eh->ether_type);
2649 case ETHERTYPE_IPV6:
2650 return !v6_forwarding;
2654 return !v4_forwarding;
2662 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2668 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2670 if_ctx_t ctx = rxq->ifr_ctx;
2671 if_shared_ctx_t sctx = ctx->ifc_sctx;
2672 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2673 iflib_dma_info_t di;
2676 struct if_rxd_info ri;
2677 int err, budget_left, rx_bytes, rx_pkts;
2681 bool v4_forwarding, v6_forwarding, lro_possible;
2684 * XXX early demux data packets so that if_input processing only handles
2685 * acks in interrupt context
2687 struct mbuf *m, *mh, *mt, *mf;
2689 lro_possible = v4_forwarding = v6_forwarding = false;
2693 rx_pkts = rx_bytes = 0;
2694 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2695 cidxp = &rxq->ifr_cq_cidx;
2697 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2698 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2699 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2700 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2701 DBG_COUNTER_INC(rx_unavail);
2705 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2706 if (__predict_false(!CTX_ACTIVE(ctx))) {
2707 DBG_COUNTER_INC(rx_ctx_inactive);
2711 * Reset client set fields to their default values
2714 ri.iri_qsidx = rxq->ifr_id;
2715 ri.iri_cidx = *cidxp;
2717 ri.iri_frags = rxq->ifr_frags;
2718 di = rxq->ifr_fl[rxq->ifr_frags[0].irf_flid].ifl_ifdi;
2719 bus_dmamap_sync(di->idi_tag, di->idi_map,
2720 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2721 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2725 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2726 *cidxp = ri.iri_cidx;
2727 /* Update our consumer index */
2728 /* XXX NB: shurd - check if this is still safe */
2729 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2730 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2731 rxq->ifr_cq_gen = 0;
2733 /* was this only a completion queue message? */
2734 if (__predict_false(ri.iri_nfrags == 0))
2737 MPASS(ri.iri_nfrags != 0);
2738 MPASS(ri.iri_len != 0);
2740 /* will advance the cidx on the corresponding free lists */
2741 m = iflib_rxd_pkt_get(rxq, &ri);
2744 if (avail == 0 && budget_left)
2745 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2747 if (__predict_false(m == NULL)) {
2748 DBG_COUNTER_INC(rx_mbuf_null);
2751 /* imm_pkt: -- cxgb */
2759 /* make sure that we can refill faster than drain */
2760 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2761 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2763 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2765 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2767 while (mh != NULL) {
2770 m->m_nextpkt = NULL;
2771 #ifndef __NO_STRICT_ALIGNMENT
2772 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2775 rx_bytes += m->m_pkthdr.len;
2777 #if defined(INET6) || defined(INET)
2779 if (!lro_possible) {
2780 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2781 if (lro_possible && mf != NULL) {
2782 ifp->if_input(ifp, mf);
2783 DBG_COUNTER_INC(rx_if_input);
2787 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2788 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2789 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2795 ifp->if_input(ifp, m);
2796 DBG_COUNTER_INC(rx_if_input);
2807 ifp->if_input(ifp, mf);
2808 DBG_COUNTER_INC(rx_if_input);
2811 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2812 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2815 * Flush any outstanding LRO work
2817 #if defined(INET6) || defined(INET)
2818 tcp_lro_flush_all(&rxq->ifr_lc);
2822 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2825 ctx->ifc_flags |= IFC_DO_RESET;
2826 iflib_admin_intr_deferred(ctx);
2831 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2832 static inline qidx_t
2833 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2835 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2836 qidx_t minthresh = txq->ift_size / 8;
2837 if (in_use > 4*minthresh)
2838 return (notify_count);
2839 if (in_use > 2*minthresh)
2840 return (notify_count >> 1);
2841 if (in_use > minthresh)
2842 return (notify_count >> 3);
2846 static inline qidx_t
2847 txq_max_rs_deferred(iflib_txq_t txq)
2849 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2850 qidx_t minthresh = txq->ift_size / 8;
2851 if (txq->ift_in_use > 4*minthresh)
2852 return (notify_count);
2853 if (txq->ift_in_use > 2*minthresh)
2854 return (notify_count >> 1);
2855 if (txq->ift_in_use > minthresh)
2856 return (notify_count >> 2);
2860 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2861 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2863 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2864 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2865 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2867 /* forward compatibility for cxgb */
2868 #define FIRST_QSET(ctx) 0
2869 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2870 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2871 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2872 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2874 /* XXX we should be setting this to something other than zero */
2875 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2876 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2877 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2880 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2886 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2887 if (ring || txq->ift_db_pending >= max) {
2888 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2889 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2890 txq->ift_db_pending = txq->ift_npending = 0;
2898 print_pkt(if_pkt_info_t pi)
2900 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2901 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2902 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2903 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2904 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2905 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2909 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2910 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2911 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2912 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2915 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2917 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2918 struct ether_vlan_header *eh;
2922 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2923 M_WRITABLE(m) == 0) {
2924 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2928 DBG_COUNTER_INC(tx_frees);
2934 * Determine where frame payload starts.
2935 * Jump over vlan headers if already present,
2936 * helpful for QinQ too.
2938 if (__predict_false(m->m_len < sizeof(*eh))) {
2940 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2943 eh = mtod(m, struct ether_vlan_header *);
2944 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2945 pi->ipi_etype = ntohs(eh->evl_proto);
2946 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2948 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2949 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2952 switch (pi->ipi_etype) {
2957 struct ip *ip = NULL;
2958 struct tcphdr *th = NULL;
2961 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2962 if (__predict_false(m->m_len < minthlen)) {
2964 * if this code bloat is causing too much of a hit
2965 * move it to a separate function and mark it noinline
2967 if (m->m_len == pi->ipi_ehdrlen) {
2970 if (n->m_len >= sizeof(*ip)) {
2971 ip = (struct ip *)n->m_data;
2972 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2973 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2976 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2978 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2982 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2984 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2985 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2986 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2989 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2990 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2991 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2993 pi->ipi_ip_hlen = ip->ip_hl << 2;
2994 pi->ipi_ipproto = ip->ip_p;
2995 pi->ipi_flags |= IPI_TX_IPV4;
2997 /* TCP checksum offload may require TCP header length */
2998 if (IS_TX_OFFLOAD4(pi)) {
2999 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3000 if (__predict_false(th == NULL)) {
3002 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3004 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3006 pi->ipi_tcp_hflags = th->th_flags;
3007 pi->ipi_tcp_hlen = th->th_off << 2;
3008 pi->ipi_tcp_seq = th->th_seq;
3011 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3014 * TSO always requires hardware checksum offload.
3016 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3017 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3018 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3019 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3020 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3022 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3026 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3033 case ETHERTYPE_IPV6:
3035 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3037 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3039 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3041 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3044 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3046 /* XXX-BZ this will go badly in case of ext hdrs. */
3047 pi->ipi_ipproto = ip6->ip6_nxt;
3048 pi->ipi_flags |= IPI_TX_IPV6;
3050 /* TCP checksum offload may require TCP header length */
3051 if (IS_TX_OFFLOAD6(pi)) {
3052 if (pi->ipi_ipproto == IPPROTO_TCP) {
3053 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3055 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3058 pi->ipi_tcp_hflags = th->th_flags;
3059 pi->ipi_tcp_hlen = th->th_off << 2;
3060 pi->ipi_tcp_seq = th->th_seq;
3063 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3066 * TSO always requires hardware checksum offload.
3068 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3069 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3070 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3077 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3078 pi->ipi_ip_hlen = 0;
3087 * If dodgy hardware rejects the scatter gather chain we've handed it
3088 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3091 static __noinline struct mbuf *
3092 iflib_remove_mbuf(iflib_txq_t txq)
3095 struct mbuf *m, **ifsd_m;
3097 ifsd_m = txq->ift_sds.ifsd_m;
3098 ntxd = txq->ift_size;
3099 pidx = txq->ift_pidx & (ntxd - 1);
3100 ifsd_m = txq->ift_sds.ifsd_m;
3102 ifsd_m[pidx] = NULL;
3103 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3104 if (txq->ift_sds.ifsd_tso_map != NULL)
3105 bus_dmamap_unload(txq->ift_tso_buf_tag,
3106 txq->ift_sds.ifsd_tso_map[pidx]);
3108 txq->ift_dequeued++;
3113 static inline caddr_t
3114 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3118 caddr_t start, end, cur, next;
3120 ntxd = txq->ift_size;
3121 size = txq->ift_txd_size[qid];
3122 start = txq->ift_ifdi[qid].idi_vaddr;
3124 if (__predict_false(size == 0))
3126 cur = start + size*cidx;
3127 end = start + size*ntxd;
3128 next = CACHE_PTR_NEXT(cur);
3129 return (next < end ? next : start);
3133 * Pad an mbuf to ensure a minimum ethernet frame size.
3134 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3136 static __noinline int
3137 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3140 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3141 * and ARP message is the smallest common payload I can think of
3143 static char pad[18]; /* just zeros */
3145 struct mbuf *new_head;
3147 if (!M_WRITABLE(*m_head)) {
3148 new_head = m_dup(*m_head, M_NOWAIT);
3149 if (new_head == NULL) {
3151 device_printf(dev, "cannot pad short frame, m_dup() failed");
3152 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3153 DBG_COUNTER_INC(tx_frees);
3160 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3161 n > 0; n -= sizeof(pad))
3162 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3167 device_printf(dev, "cannot pad short frame\n");
3168 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3169 DBG_COUNTER_INC(tx_frees);
3177 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3180 if_shared_ctx_t sctx;
3181 if_softc_ctx_t scctx;
3182 bus_dma_tag_t buf_tag;
3183 bus_dma_segment_t *segs;
3184 struct mbuf *m_head, **ifsd_m;
3187 struct if_pkt_info pi;
3189 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3192 sctx = ctx->ifc_sctx;
3193 scctx = &ctx->ifc_softc_ctx;
3194 segs = txq->ift_segs;
3195 ntxd = txq->ift_size;
3200 * If we're doing TSO the next descriptor to clean may be quite far ahead
3202 cidx = txq->ift_cidx;
3203 pidx = txq->ift_pidx;
3204 if (ctx->ifc_flags & IFC_PREFETCH) {
3205 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3206 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3207 next_txd = calc_next_txd(txq, cidx, 0);
3211 /* prefetch the next cache line of mbuf pointers and flags */
3212 prefetch(&txq->ift_sds.ifsd_m[next]);
3213 prefetch(&txq->ift_sds.ifsd_map[next]);
3214 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3216 map = txq->ift_sds.ifsd_map[pidx];
3217 ifsd_m = txq->ift_sds.ifsd_m;
3219 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3220 buf_tag = txq->ift_tso_buf_tag;
3221 max_segs = scctx->isc_tx_tso_segments_max;
3222 map = txq->ift_sds.ifsd_tso_map[pidx];
3223 MPASS(buf_tag != NULL);
3224 MPASS(max_segs > 0);
3226 buf_tag = txq->ift_buf_tag;
3227 max_segs = scctx->isc_tx_nsegments;
3228 map = txq->ift_sds.ifsd_map[pidx];
3230 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3231 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3232 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3234 DBG_COUNTER_INC(encap_txd_encap_fail);
3241 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3243 pi.ipi_qsidx = txq->ift_id;
3244 pi.ipi_len = m_head->m_pkthdr.len;
3245 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3246 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3248 /* deliberate bitwise OR to make one condition */
3249 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3250 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3251 DBG_COUNTER_INC(encap_txd_encap_fail);
3258 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3261 if (__predict_false(err)) {
3264 /* try collapse once and defrag once */
3266 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3267 /* try defrag if collapsing fails */
3272 txq->ift_mbuf_defrag++;
3273 m_head = m_defrag(*m_headp, M_NOWAIT);
3276 if (__predict_false(m_head == NULL))
3282 txq->ift_no_tx_dma_setup++;
3285 txq->ift_no_tx_dma_setup++;
3287 DBG_COUNTER_INC(tx_frees);
3291 txq->ift_map_failed++;
3292 DBG_COUNTER_INC(encap_load_mbuf_fail);
3293 DBG_COUNTER_INC(encap_txd_encap_fail);
3296 ifsd_m[pidx] = m_head;
3298 * XXX assumes a 1 to 1 relationship between segments and
3299 * descriptors - this does not hold true on all drivers, e.g.
3302 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3303 txq->ift_no_desc_avail++;
3304 bus_dmamap_unload(buf_tag, map);
3305 DBG_COUNTER_INC(encap_txq_avail_fail);
3306 DBG_COUNTER_INC(encap_txd_encap_fail);
3307 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3308 GROUPTASK_ENQUEUE(&txq->ift_task);
3312 * On Intel cards we can greatly reduce the number of TX interrupts
3313 * we see by only setting report status on every Nth descriptor.
3314 * However, this also means that the driver will need to keep track
3315 * of the descriptors that RS was set on to check them for the DD bit.
3317 txq->ift_rs_pending += nsegs + 1;
3318 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3319 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3320 pi.ipi_flags |= IPI_TX_INTR;
3321 txq->ift_rs_pending = 0;
3325 pi.ipi_nsegs = nsegs;
3327 MPASS(pidx >= 0 && pidx < txq->ift_size);
3331 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3332 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3333 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3335 DBG_COUNTER_INC(tx_encap);
3336 MPASS(pi.ipi_new_pidx < txq->ift_size);
3338 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3339 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3340 ndesc += txq->ift_size;
3344 * drivers can need as many as
3347 MPASS(ndesc <= pi.ipi_nsegs + 2);
3348 MPASS(pi.ipi_new_pidx != pidx);
3350 txq->ift_in_use += ndesc;
3353 * We update the last software descriptor again here because there may
3354 * be a sentinel and/or there may be more mbufs than segments
3356 txq->ift_pidx = pi.ipi_new_pidx;
3357 txq->ift_npending += pi.ipi_ndescs;
3359 *m_headp = m_head = iflib_remove_mbuf(txq);
3361 txq->ift_txd_encap_efbig++;
3370 * err can't possibly be non-zero here, so we don't neet to test it
3371 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3376 txq->ift_mbuf_defrag_failed++;
3377 txq->ift_map_failed++;
3379 DBG_COUNTER_INC(tx_frees);
3381 DBG_COUNTER_INC(encap_txd_encap_fail);
3386 iflib_tx_desc_free(iflib_txq_t txq, int n)
3388 uint32_t qsize, cidx, mask, gen;
3389 struct mbuf *m, **ifsd_m;
3392 cidx = txq->ift_cidx;
3394 qsize = txq->ift_size;
3396 ifsd_m = txq->ift_sds.ifsd_m;
3397 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3401 prefetch(ifsd_m[(cidx + 3) & mask]);
3402 prefetch(ifsd_m[(cidx + 4) & mask]);
3404 if ((m = ifsd_m[cidx]) != NULL) {
3405 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3406 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3407 bus_dmamap_sync(txq->ift_tso_buf_tag,
3408 txq->ift_sds.ifsd_tso_map[cidx],
3409 BUS_DMASYNC_POSTWRITE);
3410 bus_dmamap_unload(txq->ift_tso_buf_tag,
3411 txq->ift_sds.ifsd_tso_map[cidx]);
3413 bus_dmamap_sync(txq->ift_buf_tag,
3414 txq->ift_sds.ifsd_map[cidx],
3415 BUS_DMASYNC_POSTWRITE);
3416 bus_dmamap_unload(txq->ift_buf_tag,
3417 txq->ift_sds.ifsd_map[cidx]);
3419 /* XXX we don't support any drivers that batch packets yet */
3420 MPASS(m->m_nextpkt == NULL);
3422 ifsd_m[cidx] = NULL;
3424 txq->ift_dequeued++;
3426 DBG_COUNTER_INC(tx_frees);
3428 if (__predict_false(++cidx == qsize)) {
3433 txq->ift_cidx = cidx;
3438 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3441 if_ctx_t ctx = txq->ift_ctx;
3443 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3444 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3447 * Need a rate-limiting check so that this isn't called every time
3449 iflib_tx_credits_update(ctx, txq);
3450 reclaim = DESC_RECLAIMABLE(txq);
3452 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3454 if (iflib_verbose_debug) {
3455 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3456 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3463 iflib_tx_desc_free(txq, reclaim);
3464 txq->ift_cleaned += reclaim;
3465 txq->ift_in_use -= reclaim;
3470 static struct mbuf **
3471 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3474 struct mbuf **items;
3477 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3478 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3480 prefetch(items[(cidx + offset) & (size-1)]);
3481 if (remaining > 1) {
3482 prefetch2cachelines(&items[next]);
3483 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3484 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3485 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3487 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3491 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3494 ifmp_ring_check_drainage(txq->ift_br, budget);
3498 iflib_txq_can_drain(struct ifmp_ring *r)
3500 iflib_txq_t txq = r->cookie;
3501 if_ctx_t ctx = txq->ift_ctx;
3503 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3504 BUS_DMASYNC_POSTREAD);
3505 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3506 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3510 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3512 iflib_txq_t txq = r->cookie;
3513 if_ctx_t ctx = txq->ift_ctx;
3514 struct ifnet *ifp = ctx->ifc_ifp;
3515 struct mbuf **mp, *m;
3516 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3517 int reclaimed, err, in_use_prev, desc_used;
3518 bool do_prefetch, ring, rang;
3520 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3521 !LINK_ACTIVE(ctx))) {
3522 DBG_COUNTER_INC(txq_drain_notready);
3525 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3526 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3527 avail = IDXDIFF(pidx, cidx, r->size);
3528 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3529 DBG_COUNTER_INC(txq_drain_flushing);
3530 for (i = 0; i < avail; i++) {
3531 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3532 m_free(r->items[(cidx + i) & (r->size-1)]);
3533 r->items[(cidx + i) & (r->size-1)] = NULL;
3538 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3539 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3541 callout_stop(&txq->ift_timer);
3542 CALLOUT_UNLOCK(txq);
3543 DBG_COUNTER_INC(txq_drain_oactive);
3547 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3548 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3549 count = MIN(avail, TX_BATCH_SIZE);
3551 if (iflib_verbose_debug)
3552 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3553 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3555 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3556 avail = TXQ_AVAIL(txq);
3558 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3559 int rem = do_prefetch ? count - i : 0;
3561 mp = _ring_peek_one(r, cidx, i, rem);
3562 MPASS(mp != NULL && *mp != NULL);
3563 if (__predict_false(*mp == (struct mbuf *)txq)) {
3568 in_use_prev = txq->ift_in_use;
3569 err = iflib_encap(txq, mp);
3570 if (__predict_false(err)) {
3571 /* no room - bail out */
3575 /* we can't send this packet - skip it */
3581 DBG_COUNTER_INC(tx_sent);
3582 bytes_sent += m->m_pkthdr.len;
3583 mcast_sent += !!(m->m_flags & M_MCAST);
3584 avail = TXQ_AVAIL(txq);
3586 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3587 desc_used += (txq->ift_in_use - in_use_prev);
3588 ETHER_BPF_MTAP(ifp, m);
3589 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3591 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3594 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3595 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3596 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3597 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3598 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3600 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3602 if (iflib_verbose_debug)
3603 printf("consumed=%d\n", consumed);
3609 iflib_txq_drain_always(struct ifmp_ring *r)
3615 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3623 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3625 callout_stop(&txq->ift_timer);
3626 CALLOUT_UNLOCK(txq);
3628 avail = IDXDIFF(pidx, cidx, r->size);
3629 for (i = 0; i < avail; i++) {
3630 mp = _ring_peek_one(r, cidx, i, avail - i);
3631 if (__predict_false(*mp == (struct mbuf *)txq))
3634 DBG_COUNTER_INC(tx_frees);
3636 MPASS(ifmp_ring_is_stalled(r) == 0);
3641 iflib_ifmp_purge(iflib_txq_t txq)
3643 struct ifmp_ring *r;
3646 r->drain = iflib_txq_drain_free;
3647 r->can_drain = iflib_txq_drain_always;
3649 ifmp_ring_check_drainage(r, r->size);
3651 r->drain = iflib_txq_drain;
3652 r->can_drain = iflib_txq_can_drain;
3656 _task_fn_tx(void *context)
3658 iflib_txq_t txq = context;
3659 if_ctx_t ctx = txq->ift_ctx;
3660 struct ifnet *ifp = ctx->ifc_ifp;
3661 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3663 #ifdef IFLIB_DIAGNOSTICS
3664 txq->ift_cpu_exec_count[curcpu]++;
3666 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3668 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3669 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3670 BUS_DMASYNC_POSTREAD);
3671 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3672 netmap_tx_irq(ifp, txq->ift_id);
3673 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3677 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3678 iflib_altq_if_start(ifp);
3680 if (txq->ift_db_pending)
3681 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3683 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3685 * When abdicating, we always need to check drainage, not just when we don't enqueue
3688 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3689 if (ctx->ifc_flags & IFC_LEGACY)
3690 IFDI_INTR_ENABLE(ctx);
3695 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3696 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3701 _task_fn_rx(void *context)
3703 iflib_rxq_t rxq = context;
3704 if_ctx_t ctx = rxq->ifr_ctx;
3708 #ifdef IFLIB_DIAGNOSTICS
3709 rxq->ifr_cpu_exec_count[curcpu]++;
3711 DBG_COUNTER_INC(task_fn_rxs);
3712 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3716 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3718 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3723 budget = ctx->ifc_sysctl_rx_budget;
3725 budget = 16; /* XXX */
3726 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3727 if (ctx->ifc_flags & IFC_LEGACY)
3728 IFDI_INTR_ENABLE(ctx);
3733 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3734 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3735 DBG_COUNTER_INC(rx_intr_enables);
3738 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3741 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3745 _task_fn_admin(void *context)
3747 if_ctx_t ctx = context;
3748 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3751 bool oactive, running, do_reset, do_watchdog, in_detach;
3752 uint32_t reset_on = hz / 2;
3755 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3756 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3757 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3758 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3759 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3760 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3763 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3769 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3771 callout_stop(&txq->ift_timer);
3772 CALLOUT_UNLOCK(txq);
3775 ctx->ifc_watchdog_events++;
3776 IFDI_WATCHDOG_RESET(ctx);
3778 IFDI_UPDATE_ADMIN_STATUS(ctx);
3779 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3782 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3783 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3785 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3787 IFDI_LINK_INTR_ENABLE(ctx);
3789 iflib_if_init_locked(ctx);
3792 if (LINK_ACTIVE(ctx) == 0)
3794 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3795 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3800 _task_fn_iov(void *context)
3802 if_ctx_t ctx = context;
3804 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3805 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3809 IFDI_VFLR_HANDLE(ctx);
3814 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3817 if_int_delay_info_t info;
3820 info = (if_int_delay_info_t)arg1;
3821 ctx = info->iidi_ctx;
3822 info->iidi_req = req;
3823 info->iidi_oidp = oidp;
3825 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3830 /*********************************************************************
3834 **********************************************************************/
3837 iflib_if_init_locked(if_ctx_t ctx)
3840 iflib_init_locked(ctx);
3845 iflib_if_init(void *arg)
3850 iflib_if_init_locked(ctx);
3855 iflib_if_transmit(if_t ifp, struct mbuf *m)
3857 if_ctx_t ctx = if_getsoftc(ifp);
3861 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3863 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3864 DBG_COUNTER_INC(tx_frees);
3869 MPASS(m->m_nextpkt == NULL);
3870 /* ALTQ-enabled interfaces always use queue 0. */
3872 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3873 qidx = QIDX(ctx, m);
3875 * XXX calculate buf_ring based on flowid (divvy up bits?)
3877 txq = &ctx->ifc_txqs[qidx];
3879 #ifdef DRIVER_BACKPRESSURE
3880 if (txq->ift_closed) {
3882 next = m->m_nextpkt;
3883 m->m_nextpkt = NULL;
3885 DBG_COUNTER_INC(tx_frees);
3897 next = next->m_nextpkt;
3898 } while (next != NULL);
3900 if (count > nitems(marr))
3901 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3902 /* XXX check nextpkt */
3904 /* XXX simplify for now */
3905 DBG_COUNTER_INC(tx_frees);
3908 for (next = m, i = 0; next != NULL; i++) {
3910 next = next->m_nextpkt;
3911 mp[i]->m_nextpkt = NULL;
3914 DBG_COUNTER_INC(tx_seen);
3915 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3918 GROUPTASK_ENQUEUE(&txq->ift_task);
3921 GROUPTASK_ENQUEUE(&txq->ift_task);
3922 /* support forthcoming later */
3923 #ifdef DRIVER_BACKPRESSURE
3924 txq->ift_closed = TRUE;
3926 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3928 DBG_COUNTER_INC(tx_frees);
3936 * The overall approach to integrating iflib with ALTQ is to continue to use
3937 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3938 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
3939 * is redundant/unnecessary, but doing so minimizes the amount of
3940 * ALTQ-specific code required in iflib. It is assumed that the overhead of
3941 * redundantly queueing to an intermediate mp_ring is swamped by the
3942 * performance limitations inherent in using ALTQ.
3944 * When ALTQ support is compiled in, all iflib drivers will use a transmit
3945 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
3946 * given interface. If ALTQ is enabled for an interface, then all
3947 * transmitted packets for that interface will be submitted to the ALTQ
3948 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
3949 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
3950 * update stats that the iflib machinery handles, and which is sensitve to
3951 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
3952 * will be installed as the start routine for use by ALTQ facilities that
3953 * need to trigger queue drains on a scheduled basis.
3957 iflib_altq_if_start(if_t ifp)
3959 struct ifaltq *ifq = &ifp->if_snd;
3963 IFQ_DEQUEUE_NOLOCK(ifq, m);
3965 iflib_if_transmit(ifp, m);
3966 IFQ_DEQUEUE_NOLOCK(ifq, m);
3972 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
3976 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
3977 IFQ_ENQUEUE(&ifp->if_snd, m, err);
3979 iflib_altq_if_start(ifp);
3981 err = iflib_if_transmit(ifp, m);
3988 iflib_if_qflush(if_t ifp)
3990 if_ctx_t ctx = if_getsoftc(ifp);
3991 iflib_txq_t txq = ctx->ifc_txqs;
3995 ctx->ifc_flags |= IFC_QFLUSH;
3997 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
3998 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
3999 iflib_txq_check_drain(txq, 0);
4001 ctx->ifc_flags &= ~IFC_QFLUSH;
4005 * When ALTQ is enabled, this will also take care of purging the
4012 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4013 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4014 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4015 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4018 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4020 if_ctx_t ctx = if_getsoftc(ifp);
4021 struct ifreq *ifr = (struct ifreq *)data;
4022 #if defined(INET) || defined(INET6)
4023 struct ifaddr *ifa = (struct ifaddr *)data;
4025 bool avoid_reset = FALSE;
4026 int err = 0, reinit = 0, bits;
4031 if (ifa->ifa_addr->sa_family == AF_INET)
4035 if (ifa->ifa_addr->sa_family == AF_INET6)
4039 ** Calling init results in link renegotiation,
4040 ** so we avoid doing it when possible.
4043 if_setflagbits(ifp, IFF_UP,0);
4044 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4047 if (!(if_getflags(ifp) & IFF_NOARP))
4048 arp_ifinit(ifp, ifa);
4051 err = ether_ioctl(ifp, command, data);
4055 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4059 bits = if_getdrvflags(ifp);
4060 /* stop the driver and free any clusters before proceeding */
4063 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4065 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4066 ctx->ifc_flags |= IFC_MULTISEG;
4068 ctx->ifc_flags &= ~IFC_MULTISEG;
4070 err = if_setmtu(ifp, ifr->ifr_mtu);
4072 iflib_init_locked(ctx);
4074 if_setdrvflags(ifp, bits);
4080 if (if_getflags(ifp) & IFF_UP) {
4081 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4082 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4083 (IFF_PROMISC | IFF_ALLMULTI)) {
4084 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4088 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4091 ctx->ifc_if_flags = if_getflags(ifp);
4096 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4098 IFDI_INTR_DISABLE(ctx);
4099 IFDI_MULTI_SET(ctx);
4100 IFDI_INTR_ENABLE(ctx);
4106 IFDI_MEDIA_SET(ctx);
4111 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4115 struct ifi2creq i2c;
4117 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4120 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4124 if (i2c.len > sizeof(i2c.data)) {
4129 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4130 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4136 int mask, setmask, oldmask;
4138 oldmask = if_getcapenable(ifp);
4139 mask = ifr->ifr_reqcap ^ oldmask;
4140 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4143 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4145 setmask |= (mask & IFCAP_FLAGS);
4146 setmask |= (mask & IFCAP_WOL);
4149 * If any RX csum has changed, change all the ones that
4150 * are supported by the driver.
4152 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4153 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4154 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4158 * want to ensure that traffic has stopped before we change any of the flags
4162 bits = if_getdrvflags(ifp);
4163 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4166 if_togglecapenable(ifp, setmask);
4168 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4169 iflib_init_locked(ctx);
4171 if_setdrvflags(ifp, bits);
4178 case SIOCGPRIVATE_0:
4182 err = IFDI_PRIV_IOCTL(ctx, command, data);
4186 err = ether_ioctl(ifp, command, data);
4195 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4197 if_ctx_t ctx = if_getsoftc(ifp);
4199 return (IFDI_GET_COUNTER(ctx, cnt));
4202 /*********************************************************************
4204 * OTHER FUNCTIONS EXPORTED TO THE STACK
4206 **********************************************************************/
4209 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4211 if_ctx_t ctx = if_getsoftc(ifp);
4213 if ((void *)ctx != arg)
4216 if ((vtag == 0) || (vtag > 4095))
4220 IFDI_VLAN_REGISTER(ctx, vtag);
4221 /* Re-init to load the changes */
4222 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4223 iflib_if_init_locked(ctx);
4228 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4230 if_ctx_t ctx = if_getsoftc(ifp);
4232 if ((void *)ctx != arg)
4235 if ((vtag == 0) || (vtag > 4095))
4239 IFDI_VLAN_UNREGISTER(ctx, vtag);
4240 /* Re-init to load the changes */
4241 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4242 iflib_if_init_locked(ctx);
4247 iflib_led_func(void *arg, int onoff)
4252 IFDI_LED_FUNC(ctx, onoff);
4256 /*********************************************************************
4258 * BUS FUNCTION DEFINITIONS
4260 **********************************************************************/
4263 iflib_device_probe(device_t dev)
4265 pci_vendor_info_t *ent;
4267 uint16_t pci_vendor_id, pci_device_id;
4268 uint16_t pci_subvendor_id, pci_subdevice_id;
4269 uint16_t pci_rev_id;
4270 if_shared_ctx_t sctx;
4272 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4275 pci_vendor_id = pci_get_vendor(dev);
4276 pci_device_id = pci_get_device(dev);
4277 pci_subvendor_id = pci_get_subvendor(dev);
4278 pci_subdevice_id = pci_get_subdevice(dev);
4279 pci_rev_id = pci_get_revid(dev);
4280 if (sctx->isc_parse_devinfo != NULL)
4281 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4283 ent = sctx->isc_vendor_info;
4284 while (ent->pvi_vendor_id != 0) {
4285 if (pci_vendor_id != ent->pvi_vendor_id) {
4289 if ((pci_device_id == ent->pvi_device_id) &&
4290 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4291 (ent->pvi_subvendor_id == 0)) &&
4292 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4293 (ent->pvi_subdevice_id == 0)) &&
4294 ((pci_rev_id == ent->pvi_rev_id) ||
4295 (ent->pvi_rev_id == 0))) {
4297 device_set_desc_copy(dev, ent->pvi_name);
4298 /* this needs to be changed to zero if the bus probing code
4299 * ever stops re-probing on best match because the sctx
4300 * may have its values over written by register calls
4301 * in subsequent probes
4303 return (BUS_PROBE_DEFAULT);
4311 iflib_reset_qvalues(if_ctx_t ctx)
4313 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4314 if_shared_ctx_t sctx = ctx->ifc_sctx;
4315 device_t dev = ctx->ifc_dev;
4318 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4319 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4321 * XXX sanity check that ntxd & nrxd are a power of 2
4323 if (ctx->ifc_sysctl_ntxqs != 0)
4324 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4325 if (ctx->ifc_sysctl_nrxqs != 0)
4326 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4328 for (i = 0; i < sctx->isc_ntxqs; i++) {
4329 if (ctx->ifc_sysctl_ntxds[i] != 0)
4330 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4332 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4335 for (i = 0; i < sctx->isc_nrxqs; i++) {
4336 if (ctx->ifc_sysctl_nrxds[i] != 0)
4337 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4339 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4342 for (i = 0; i < sctx->isc_nrxqs; i++) {
4343 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4344 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4345 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4346 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4348 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4349 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4350 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4351 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4355 for (i = 0; i < sctx->isc_ntxqs; i++) {
4356 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4357 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4358 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4359 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4361 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4362 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4363 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4364 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4370 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4375 if_softc_ctx_t scctx;
4381 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4384 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4385 device_set_softc(dev, ctx);
4386 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4389 ctx->ifc_sctx = sctx;
4391 ctx->ifc_softc = sc;
4393 if ((err = iflib_register(ctx)) != 0) {
4394 device_printf(dev, "iflib_register failed %d\n", err);
4397 iflib_add_device_sysctl_pre(ctx);
4399 scctx = &ctx->ifc_softc_ctx;
4402 iflib_reset_qvalues(ctx);
4404 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4405 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4408 _iflib_pre_assert(scctx);
4409 ctx->ifc_txrx = *scctx->isc_txrx;
4412 MPASS(scctx->isc_capabilities);
4413 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4414 MPASS(scctx->isc_tx_csum_flags);
4417 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4418 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4420 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4421 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4422 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4423 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4425 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4426 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4428 /* XXX change for per-queue sizes */
4429 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4430 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4431 for (i = 0; i < sctx->isc_nrxqs; i++) {
4432 if (!powerof2(scctx->isc_nrxd[i])) {
4433 /* round down instead? */
4434 device_printf(dev, "# rx descriptors must be a power of 2\n");
4436 goto fail_iflib_detach;
4439 for (i = 0; i < sctx->isc_ntxqs; i++) {
4440 if (!powerof2(scctx->isc_ntxd[i])) {
4442 "# tx descriptors must be a power of 2");
4444 goto fail_iflib_detach;
4448 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4449 MAX_SINGLE_PACKET_FRACTION)
4450 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4451 MAX_SINGLE_PACKET_FRACTION);
4452 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4453 MAX_SINGLE_PACKET_FRACTION)
4454 scctx->isc_tx_tso_segments_max = max(1,
4455 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4457 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4458 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4460 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4463 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4466 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4467 * into account. In the worst case, each of these calls will
4468 * add another mbuf and, thus, the requirement for another DMA
4469 * segment. So for best performance, it doesn't make sense to
4470 * advertize a maximum of TSO segments that typically will
4471 * require defragmentation in iflib_encap().
4473 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4474 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4476 if (scctx->isc_rss_table_size == 0)
4477 scctx->isc_rss_table_size = 64;
4478 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4480 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4481 /* XXX format name */
4482 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4484 /* Set up cpu set. If it fails, use the set of all CPUs. */
4485 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4486 device_printf(dev, "Unable to fetch CPU list\n");
4487 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4489 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4492 ** Now set up MSI or MSI-X, should return us the number of supported
4493 ** vectors (will be 1 for a legacy interrupt and MSI).
4495 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4496 msix = scctx->isc_vectors;
4497 } else if (scctx->isc_msix_bar != 0)
4499 * The simple fact that isc_msix_bar is not 0 does not mean we
4500 * we have a good value there that is known to work.
4502 msix = iflib_msix_init(ctx);
4504 scctx->isc_vectors = 1;
4505 scctx->isc_ntxqsets = 1;
4506 scctx->isc_nrxqsets = 1;
4507 scctx->isc_intr = IFLIB_INTR_LEGACY;
4510 /* Get memory for the station queues */
4511 if ((err = iflib_queues_alloc(ctx))) {
4512 device_printf(dev, "Unable to allocate queue memory\n");
4513 goto fail_intr_free;
4516 if ((err = iflib_qset_structures_setup(ctx)))
4520 * Group taskqueues aren't properly set up until SMP is started,
4521 * so we disable interrupts until we can handle them post
4524 * XXX: disabling interrupts doesn't actually work, at least for
4525 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4526 * we do null handling and depend on this not causing too large an
4529 IFDI_INTR_DISABLE(ctx);
4530 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4531 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4536 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4540 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4541 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4546 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4548 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4549 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4554 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4555 * This must appear after the call to ether_ifattach() because
4556 * ether_ifattach() sets if_hdrlen to the default value.
4558 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4559 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4561 if ((err = iflib_netmap_attach(ctx))) {
4562 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4567 NETDUMP_SET(ctx->ifc_ifp, iflib);
4569 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4570 iflib_add_device_sysctl_post(ctx);
4571 ctx->ifc_flags |= IFC_INIT_DONE;
4576 ether_ifdetach(ctx->ifc_ifp);
4578 iflib_free_intr_mem(ctx);
4580 iflib_tx_structures_free(ctx);
4581 iflib_rx_structures_free(ctx);
4587 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4588 free(ctx->ifc_softc, M_IFLIB);
4594 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4595 struct iflib_cloneattach_ctx *clctx)
4600 if_softc_ctx_t scctx;
4606 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4607 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4608 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4609 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4610 ctx->ifc_flags |= IFC_PSEUDO;
4612 ctx->ifc_sctx = sctx;
4613 ctx->ifc_softc = sc;
4616 if ((err = iflib_register(ctx)) != 0) {
4617 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4620 iflib_add_device_sysctl_pre(ctx);
4622 scctx = &ctx->ifc_softc_ctx;
4626 * XXX sanity check that ntxd & nrxd are a power of 2
4628 iflib_reset_qvalues(ctx);
4630 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4631 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4634 if (sctx->isc_flags & IFLIB_GEN_MAC)
4636 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4637 clctx->cc_params)) != 0) {
4638 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4641 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4642 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4643 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4646 MPASS(scctx->isc_capabilities);
4647 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4648 MPASS(scctx->isc_tx_csum_flags);
4651 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4652 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4654 ifp->if_flags |= IFF_NOGROUP;
4655 if (sctx->isc_flags & IFLIB_PSEUDO) {
4656 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4658 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4659 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4665 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4666 * This must appear after the call to ether_ifattach() because
4667 * ether_ifattach() sets if_hdrlen to the default value.
4669 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4670 if_setifheaderlen(ifp,
4671 sizeof(struct ether_vlan_header));
4673 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4674 iflib_add_device_sysctl_post(ctx);
4675 ctx->ifc_flags |= IFC_INIT_DONE;
4678 _iflib_pre_assert(scctx);
4679 ctx->ifc_txrx = *scctx->isc_txrx;
4681 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4682 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4683 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4684 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4686 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4687 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4689 /* XXX change for per-queue sizes */
4690 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4691 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4692 for (i = 0; i < sctx->isc_nrxqs; i++) {
4693 if (!powerof2(scctx->isc_nrxd[i])) {
4694 /* round down instead? */
4695 device_printf(dev, "# rx descriptors must be a power of 2\n");
4697 goto fail_iflib_detach;
4700 for (i = 0; i < sctx->isc_ntxqs; i++) {
4701 if (!powerof2(scctx->isc_ntxd[i])) {
4703 "# tx descriptors must be a power of 2");
4705 goto fail_iflib_detach;
4709 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4710 MAX_SINGLE_PACKET_FRACTION)
4711 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4712 MAX_SINGLE_PACKET_FRACTION);
4713 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4714 MAX_SINGLE_PACKET_FRACTION)
4715 scctx->isc_tx_tso_segments_max = max(1,
4716 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4718 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4719 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4721 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4724 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4727 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4728 * into account. In the worst case, each of these calls will
4729 * add another mbuf and, thus, the requirement for another DMA
4730 * segment. So for best performance, it doesn't make sense to
4731 * advertize a maximum of TSO segments that typically will
4732 * require defragmentation in iflib_encap().
4734 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4735 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4737 if (scctx->isc_rss_table_size == 0)
4738 scctx->isc_rss_table_size = 64;
4739 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4741 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4742 /* XXX format name */
4743 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4745 /* XXX --- can support > 1 -- but keep it simple for now */
4746 scctx->isc_intr = IFLIB_INTR_LEGACY;
4748 /* Get memory for the station queues */
4749 if ((err = iflib_queues_alloc(ctx))) {
4750 device_printf(dev, "Unable to allocate queue memory\n");
4751 goto fail_iflib_detach;
4754 if ((err = iflib_qset_structures_setup(ctx))) {
4755 device_printf(dev, "qset structure setup failed %d\n", err);
4760 * XXX What if anything do we want to do about interrupts?
4762 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4763 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4764 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4769 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4770 * This must appear after the call to ether_ifattach() because
4771 * ether_ifattach() sets if_hdrlen to the default value.
4773 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4774 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4776 /* XXX handle more than one queue */
4777 for (i = 0; i < scctx->isc_nrxqsets; i++)
4778 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4782 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4783 iflib_add_device_sysctl_post(ctx);
4784 ctx->ifc_flags |= IFC_INIT_DONE;
4787 ether_ifdetach(ctx->ifc_ifp);
4789 iflib_tx_structures_free(ctx);
4790 iflib_rx_structures_free(ctx);
4794 free(ctx->ifc_softc, M_IFLIB);
4800 iflib_pseudo_deregister(if_ctx_t ctx)
4802 if_t ifp = ctx->ifc_ifp;
4806 struct taskqgroup *tqg;
4809 /* Unregister VLAN events */
4810 if (ctx->ifc_vlan_attach_event != NULL)
4811 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4812 if (ctx->ifc_vlan_detach_event != NULL)
4813 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4815 ether_ifdetach(ifp);
4816 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4817 CTX_LOCK_DESTROY(ctx);
4818 /* XXX drain any dependent tasks */
4819 tqg = qgroup_if_io_tqg;
4820 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4821 callout_drain(&txq->ift_timer);
4822 if (txq->ift_task.gt_uniq != NULL)
4823 taskqgroup_detach(tqg, &txq->ift_task);
4825 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4826 if (rxq->ifr_task.gt_uniq != NULL)
4827 taskqgroup_detach(tqg, &rxq->ifr_task);
4829 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4830 free(fl->ifl_rx_bitmap, M_IFLIB);
4832 tqg = qgroup_if_config_tqg;
4833 if (ctx->ifc_admin_task.gt_uniq != NULL)
4834 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4835 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4836 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4840 iflib_tx_structures_free(ctx);
4841 iflib_rx_structures_free(ctx);
4842 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4843 free(ctx->ifc_softc, M_IFLIB);
4849 iflib_device_attach(device_t dev)
4852 if_shared_ctx_t sctx;
4854 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4857 pci_enable_busmaster(dev);
4859 return (iflib_device_register(dev, NULL, sctx, &ctx));
4863 iflib_device_deregister(if_ctx_t ctx)
4865 if_t ifp = ctx->ifc_ifp;
4868 device_t dev = ctx->ifc_dev;
4870 struct taskqgroup *tqg;
4873 /* Make sure VLANS are not using driver */
4874 if (if_vlantrunkinuse(ifp)) {
4875 device_printf(dev, "Vlan in use, detach first\n");
4879 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
4880 device_printf(dev, "SR-IOV in use; detach first.\n");
4886 ctx->ifc_flags |= IFC_IN_DETACH;
4893 /* Unregister VLAN events */
4894 if (ctx->ifc_vlan_attach_event != NULL)
4895 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4896 if (ctx->ifc_vlan_detach_event != NULL)
4897 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4899 iflib_netmap_detach(ifp);
4900 ether_ifdetach(ifp);
4901 if (ctx->ifc_led_dev != NULL)
4902 led_destroy(ctx->ifc_led_dev);
4903 /* XXX drain any dependent tasks */
4904 tqg = qgroup_if_io_tqg;
4905 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4906 callout_drain(&txq->ift_timer);
4907 if (txq->ift_task.gt_uniq != NULL)
4908 taskqgroup_detach(tqg, &txq->ift_task);
4910 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4911 if (rxq->ifr_task.gt_uniq != NULL)
4912 taskqgroup_detach(tqg, &rxq->ifr_task);
4914 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4915 free(fl->ifl_rx_bitmap, M_IFLIB);
4917 tqg = qgroup_if_config_tqg;
4918 if (ctx->ifc_admin_task.gt_uniq != NULL)
4919 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4920 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4921 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4926 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4927 CTX_LOCK_DESTROY(ctx);
4928 device_set_softc(ctx->ifc_dev, NULL);
4929 iflib_free_intr_mem(ctx);
4931 bus_generic_detach(dev);
4934 iflib_tx_structures_free(ctx);
4935 iflib_rx_structures_free(ctx);
4936 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4937 free(ctx->ifc_softc, M_IFLIB);
4938 STATE_LOCK_DESTROY(ctx);
4944 iflib_free_intr_mem(if_ctx_t ctx)
4947 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4948 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4950 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4951 pci_release_msi(ctx->ifc_dev);
4953 if (ctx->ifc_msix_mem != NULL) {
4954 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4955 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
4956 ctx->ifc_msix_mem = NULL;
4961 iflib_device_detach(device_t dev)
4963 if_ctx_t ctx = device_get_softc(dev);
4965 return (iflib_device_deregister(ctx));
4969 iflib_device_suspend(device_t dev)
4971 if_ctx_t ctx = device_get_softc(dev);
4977 return bus_generic_suspend(dev);
4980 iflib_device_shutdown(device_t dev)
4982 if_ctx_t ctx = device_get_softc(dev);
4988 return bus_generic_suspend(dev);
4993 iflib_device_resume(device_t dev)
4995 if_ctx_t ctx = device_get_softc(dev);
4996 iflib_txq_t txq = ctx->ifc_txqs;
5000 iflib_if_init_locked(ctx);
5002 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5003 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5005 return (bus_generic_resume(dev));
5009 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5012 if_ctx_t ctx = device_get_softc(dev);
5015 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5022 iflib_device_iov_uninit(device_t dev)
5024 if_ctx_t ctx = device_get_softc(dev);
5027 IFDI_IOV_UNINIT(ctx);
5032 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5035 if_ctx_t ctx = device_get_softc(dev);
5038 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5044 /*********************************************************************
5046 * MODULE FUNCTION DEFINITIONS
5048 **********************************************************************/
5051 * - Start a fast taskqueue thread for each core
5052 * - Start a taskqueue for control operations
5055 iflib_module_init(void)
5061 iflib_module_event_handler(module_t mod, int what, void *arg)
5067 if ((err = iflib_module_init()) != 0)
5073 return (EOPNOTSUPP);
5079 /*********************************************************************
5081 * PUBLIC FUNCTION DEFINITIONS
5082 * ordered as in iflib.h
5084 **********************************************************************/
5088 _iflib_assert(if_shared_ctx_t sctx)
5090 MPASS(sctx->isc_tx_maxsize);
5091 MPASS(sctx->isc_tx_maxsegsize);
5093 MPASS(sctx->isc_rx_maxsize);
5094 MPASS(sctx->isc_rx_nsegments);
5095 MPASS(sctx->isc_rx_maxsegsize);
5097 MPASS(sctx->isc_nrxd_min[0]);
5098 MPASS(sctx->isc_nrxd_max[0]);
5099 MPASS(sctx->isc_nrxd_default[0]);
5100 MPASS(sctx->isc_ntxd_min[0]);
5101 MPASS(sctx->isc_ntxd_max[0]);
5102 MPASS(sctx->isc_ntxd_default[0]);
5106 _iflib_pre_assert(if_softc_ctx_t scctx)
5109 MPASS(scctx->isc_txrx->ift_txd_encap);
5110 MPASS(scctx->isc_txrx->ift_txd_flush);
5111 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5112 MPASS(scctx->isc_txrx->ift_rxd_available);
5113 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5114 MPASS(scctx->isc_txrx->ift_rxd_refill);
5115 MPASS(scctx->isc_txrx->ift_rxd_flush);
5119 iflib_register(if_ctx_t ctx)
5121 if_shared_ctx_t sctx = ctx->ifc_sctx;
5122 driver_t *driver = sctx->isc_driver;
5123 device_t dev = ctx->ifc_dev;
5126 _iflib_assert(sctx);
5129 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5130 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5132 device_printf(dev, "can not allocate ifnet structure\n");
5137 * Initialize our context's device specific methods
5139 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5140 kobj_class_compile((kobj_class_t) driver);
5143 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5144 if_setsoftc(ifp, ctx);
5145 if_setdev(ifp, dev);
5146 if_setinitfn(ifp, iflib_if_init);
5147 if_setioctlfn(ifp, iflib_if_ioctl);
5149 if_setstartfn(ifp, iflib_altq_if_start);
5150 if_settransmitfn(ifp, iflib_altq_if_transmit);
5151 if_setsendqready(ifp);
5153 if_settransmitfn(ifp, iflib_if_transmit);
5155 if_setqflushfn(ifp, iflib_if_qflush);
5156 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5158 ctx->ifc_vlan_attach_event =
5159 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5160 EVENTHANDLER_PRI_FIRST);
5161 ctx->ifc_vlan_detach_event =
5162 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5163 EVENTHANDLER_PRI_FIRST);
5165 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5166 iflib_media_change, iflib_media_status);
5173 iflib_queues_alloc(if_ctx_t ctx)
5175 if_shared_ctx_t sctx = ctx->ifc_sctx;
5176 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5177 device_t dev = ctx->ifc_dev;
5178 int nrxqsets = scctx->isc_nrxqsets;
5179 int ntxqsets = scctx->isc_ntxqsets;
5182 iflib_fl_t fl = NULL;
5183 int i, j, cpu, err, txconf, rxconf;
5184 iflib_dma_info_t ifdip;
5185 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5186 uint32_t *txqsizes = scctx->isc_txqsizes;
5187 uint8_t nrxqs = sctx->isc_nrxqs;
5188 uint8_t ntxqs = sctx->isc_ntxqs;
5189 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5193 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5194 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5196 /* Allocate the TX ring struct memory */
5197 if (!(ctx->ifc_txqs =
5198 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5199 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5200 device_printf(dev, "Unable to allocate TX ring memory\n");
5205 /* Now allocate the RX */
5206 if (!(ctx->ifc_rxqs =
5207 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5208 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5209 device_printf(dev, "Unable to allocate RX ring memory\n");
5214 txq = ctx->ifc_txqs;
5215 rxq = ctx->ifc_rxqs;
5218 * XXX handle allocation failure
5220 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5221 /* Set up some basics */
5223 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5224 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5226 "Unable to allocate TX DMA info memory\n");
5230 txq->ift_ifdi = ifdip;
5231 for (j = 0; j < ntxqs; j++, ifdip++) {
5232 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5234 "Unable to allocate TX descriptors\n");
5238 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5239 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5243 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5244 txq->ift_br_offset = 1;
5246 txq->ift_br_offset = 0;
5249 txq->ift_timer.c_cpu = cpu;
5251 if (iflib_txsd_alloc(txq)) {
5252 device_printf(dev, "Critical Failure setting up TX buffers\n");
5257 /* Initialize the TX lock */
5258 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5259 device_get_nameunit(dev), txq->ift_id);
5260 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5261 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5263 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5264 device_get_nameunit(dev), txq->ift_id);
5266 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5267 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5269 /* XXX free any allocated rings */
5270 device_printf(dev, "Unable to allocate buf_ring\n");
5275 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5276 /* Set up some basics */
5278 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5279 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5281 "Unable to allocate RX DMA info memory\n");
5286 rxq->ifr_ifdi = ifdip;
5287 /* XXX this needs to be changed if #rx queues != #tx queues */
5288 rxq->ifr_ntxqirq = 1;
5289 rxq->ifr_txqid[0] = i;
5290 for (j = 0; j < nrxqs; j++, ifdip++) {
5291 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5293 "Unable to allocate RX descriptors\n");
5297 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5301 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5302 rxq->ifr_fl_offset = 1;
5304 rxq->ifr_fl_offset = 0;
5306 rxq->ifr_nfl = nfree_lists;
5308 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5309 device_printf(dev, "Unable to allocate free list memory\n");
5314 for (j = 0; j < nfree_lists; j++) {
5315 fl[j].ifl_rxq = rxq;
5317 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5318 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5320 /* Allocate receive buffers for the ring */
5321 if (iflib_rxsd_alloc(rxq)) {
5323 "Critical Failure setting up receive buffers\n");
5328 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5329 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5334 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5335 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5336 for (i = 0; i < ntxqsets; i++) {
5337 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5339 for (j = 0; j < ntxqs; j++, di++) {
5340 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5341 paddrs[i*ntxqs + j] = di->idi_paddr;
5344 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5345 device_printf(ctx->ifc_dev,
5346 "Unable to allocate device TX queue\n");
5347 iflib_tx_structures_free(ctx);
5348 free(vaddrs, M_IFLIB);
5349 free(paddrs, M_IFLIB);
5352 free(vaddrs, M_IFLIB);
5353 free(paddrs, M_IFLIB);
5356 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5357 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5358 for (i = 0; i < nrxqsets; i++) {
5359 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5361 for (j = 0; j < nrxqs; j++, di++) {
5362 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5363 paddrs[i*nrxqs + j] = di->idi_paddr;
5366 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5367 device_printf(ctx->ifc_dev,
5368 "Unable to allocate device RX queue\n");
5369 iflib_tx_structures_free(ctx);
5370 free(vaddrs, M_IFLIB);
5371 free(paddrs, M_IFLIB);
5374 free(vaddrs, M_IFLIB);
5375 free(paddrs, M_IFLIB);
5379 /* XXX handle allocation failure changes */
5383 if (ctx->ifc_rxqs != NULL)
5384 free(ctx->ifc_rxqs, M_IFLIB);
5385 ctx->ifc_rxqs = NULL;
5386 if (ctx->ifc_txqs != NULL)
5387 free(ctx->ifc_txqs, M_IFLIB);
5388 ctx->ifc_txqs = NULL;
5394 iflib_tx_structures_setup(if_ctx_t ctx)
5396 iflib_txq_t txq = ctx->ifc_txqs;
5399 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5400 iflib_txq_setup(txq);
5406 iflib_tx_structures_free(if_ctx_t ctx)
5408 iflib_txq_t txq = ctx->ifc_txqs;
5409 if_shared_ctx_t sctx = ctx->ifc_sctx;
5412 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5413 iflib_txq_destroy(txq);
5414 for (j = 0; j < sctx->isc_ntxqs; j++)
5415 iflib_dma_free(&txq->ift_ifdi[j]);
5417 free(ctx->ifc_txqs, M_IFLIB);
5418 ctx->ifc_txqs = NULL;
5419 IFDI_QUEUES_FREE(ctx);
5422 /*********************************************************************
5424 * Initialize all receive rings.
5426 **********************************************************************/
5428 iflib_rx_structures_setup(if_ctx_t ctx)
5430 iflib_rxq_t rxq = ctx->ifc_rxqs;
5432 #if defined(INET6) || defined(INET)
5436 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5437 #if defined(INET6) || defined(INET)
5438 tcp_lro_free(&rxq->ifr_lc);
5439 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5440 TCP_LRO_ENTRIES, min(1024,
5441 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5442 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5445 rxq->ifr_lro_enabled = TRUE;
5447 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5450 #if defined(INET6) || defined(INET)
5453 * Free RX software descriptors allocated so far, we will only handle
5454 * the rings that completed, the failing case will have
5455 * cleaned up for itself. 'q' failed, so its the terminus.
5457 rxq = ctx->ifc_rxqs;
5458 for (i = 0; i < q; ++i, rxq++) {
5459 iflib_rx_sds_free(rxq);
5460 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5466 /*********************************************************************
5468 * Free all receive rings.
5470 **********************************************************************/
5472 iflib_rx_structures_free(if_ctx_t ctx)
5474 iflib_rxq_t rxq = ctx->ifc_rxqs;
5476 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5477 iflib_rx_sds_free(rxq);
5479 free(ctx->ifc_rxqs, M_IFLIB);
5480 ctx->ifc_rxqs = NULL;
5484 iflib_qset_structures_setup(if_ctx_t ctx)
5489 * It is expected that the caller takes care of freeing queues if this
5492 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5493 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5497 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5498 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5504 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5505 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5508 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5513 find_nth(if_ctx_t ctx, int qid)
5516 int i, cpuid, eqid, count;
5518 CPU_COPY(&ctx->ifc_cpus, &cpus);
5519 count = CPU_COUNT(&cpus);
5521 /* clear up to the qid'th bit */
5522 for (i = 0; i < eqid; i++) {
5523 cpuid = CPU_FFS(&cpus);
5525 CPU_CLR(cpuid-1, &cpus);
5527 cpuid = CPU_FFS(&cpus);
5533 extern struct cpu_group *cpu_top; /* CPU topology */
5536 find_child_with_core(int cpu, struct cpu_group *grp)
5540 if (grp->cg_children == 0)
5543 MPASS(grp->cg_child);
5544 for (i = 0; i < grp->cg_children; i++) {
5545 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5553 * Find the nth "close" core to the specified core
5554 * "close" is defined as the deepest level that shares
5555 * at least an L2 cache. With threads, this will be
5556 * threads on the same core. If the sahred cache is L3
5557 * or higher, simply returns the same core.
5560 find_close_core(int cpu, int core_offset)
5562 struct cpu_group *grp;
5571 while ((i = find_child_with_core(cpu, grp)) != -1) {
5572 /* If the child only has one cpu, don't descend */
5573 if (grp->cg_child[i].cg_count <= 1)
5575 grp = &grp->cg_child[i];
5578 /* If they don't share at least an L2 cache, use the same CPU */
5579 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5583 CPU_COPY(&grp->cg_mask, &cs);
5585 /* Add the selected CPU offset to core offset. */
5586 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5587 if (fcpu - 1 == cpu)
5589 CPU_CLR(fcpu - 1, &cs);
5595 CPU_COPY(&grp->cg_mask, &cs);
5596 for (i = core_offset % grp->cg_count; i > 0; i--) {
5597 MPASS(CPU_FFS(&cs));
5598 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5600 MPASS(CPU_FFS(&cs));
5601 return CPU_FFS(&cs) - 1;
5605 find_close_core(int cpu, int core_offset __unused)
5612 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5616 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5617 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5618 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5620 case IFLIB_INTR_RXTX:
5621 /* RX queues get the specified core */
5622 return qid / CPU_COUNT(&ctx->ifc_cpus);
5628 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5629 #define find_close_core(cpuid, tid) CPU_FIRST()
5630 #define find_nth(ctx, gid) CPU_FIRST()
5633 /* Just to avoid copy/paste */
5635 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5636 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5641 cpuid = find_nth(ctx, qid);
5642 tid = get_core_offset(ctx, type, qid);
5644 cpuid = find_close_core(cpuid, tid);
5645 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5647 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5651 if (cpuid > ctx->ifc_cpuid_highest)
5652 ctx->ifc_cpuid_highest = cpuid;
5658 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5659 iflib_intr_type_t type, driver_filter_t *filter,
5660 void *filter_arg, int qid, const char *name)
5662 struct grouptask *gtask;
5663 struct taskqgroup *tqg;
5664 iflib_filter_info_t info;
5667 driver_filter_t *intr_fast;
5670 info = &ctx->ifc_filter_info;
5674 /* XXX merge tx/rx for netmap? */
5676 q = &ctx->ifc_txqs[qid];
5677 info = &ctx->ifc_txqs[qid].ift_filter_info;
5678 gtask = &ctx->ifc_txqs[qid].ift_task;
5679 tqg = qgroup_if_io_tqg;
5681 intr_fast = iflib_fast_intr;
5682 GROUPTASK_INIT(gtask, 0, fn, q);
5683 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5686 q = &ctx->ifc_rxqs[qid];
5687 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5688 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5689 tqg = qgroup_if_io_tqg;
5691 intr_fast = iflib_fast_intr;
5692 GROUPTASK_INIT(gtask, 0, fn, q);
5694 case IFLIB_INTR_RXTX:
5695 q = &ctx->ifc_rxqs[qid];
5696 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5697 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5698 tqg = qgroup_if_io_tqg;
5700 intr_fast = iflib_fast_intr_rxtx;
5701 GROUPTASK_INIT(gtask, 0, fn, q);
5703 case IFLIB_INTR_ADMIN:
5706 info = &ctx->ifc_filter_info;
5707 gtask = &ctx->ifc_admin_task;
5708 tqg = qgroup_if_config_tqg;
5709 fn = _task_fn_admin;
5710 intr_fast = iflib_fast_intr_ctx;
5713 panic("unknown net intr type");
5716 info->ifi_filter = filter;
5717 info->ifi_filter_arg = filter_arg;
5718 info->ifi_task = gtask;
5721 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5723 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5726 if (type == IFLIB_INTR_ADMIN)
5730 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5734 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5741 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5743 struct grouptask *gtask;
5744 struct taskqgroup *tqg;
5752 q = &ctx->ifc_txqs[qid];
5753 gtask = &ctx->ifc_txqs[qid].ift_task;
5754 tqg = qgroup_if_io_tqg;
5757 irq_num = rman_get_start(irq->ii_res);
5760 q = &ctx->ifc_rxqs[qid];
5761 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5762 tqg = qgroup_if_io_tqg;
5765 irq_num = rman_get_start(irq->ii_res);
5767 case IFLIB_INTR_IOV:
5769 gtask = &ctx->ifc_vflr_task;
5770 tqg = qgroup_if_config_tqg;
5774 panic("unknown net intr type");
5776 GROUPTASK_INIT(gtask, 0, fn, q);
5777 if (irq_num != -1) {
5778 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5780 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5783 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5788 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5792 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5795 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
5796 rman_get_rid(irq->ii_res), irq->ii_res);
5800 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5802 iflib_txq_t txq = ctx->ifc_txqs;
5803 iflib_rxq_t rxq = ctx->ifc_rxqs;
5804 if_irq_t irq = &ctx->ifc_legacy_irq;
5805 iflib_filter_info_t info;
5806 struct grouptask *gtask;
5807 struct taskqgroup *tqg;
5813 q = &ctx->ifc_rxqs[0];
5814 info = &rxq[0].ifr_filter_info;
5815 gtask = &rxq[0].ifr_task;
5816 tqg = qgroup_if_io_tqg;
5817 tqrid = irq->ii_rid = *rid;
5820 ctx->ifc_flags |= IFC_LEGACY;
5821 info->ifi_filter = filter;
5822 info->ifi_filter_arg = filter_arg;
5823 info->ifi_task = gtask;
5824 info->ifi_ctx = ctx;
5826 /* We allocate a single interrupt resource */
5827 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5829 GROUPTASK_INIT(gtask, 0, fn, q);
5830 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5832 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5833 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5838 iflib_led_create(if_ctx_t ctx)
5841 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5842 device_get_nameunit(ctx->ifc_dev));
5846 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5849 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5853 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5856 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5860 iflib_admin_intr_deferred(if_ctx_t ctx)
5863 struct grouptask *gtask;
5865 gtask = &ctx->ifc_admin_task;
5866 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5869 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5873 iflib_iov_intr_deferred(if_ctx_t ctx)
5876 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5880 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5883 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5887 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5891 GROUPTASK_INIT(gtask, 0, fn, ctx);
5892 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
5896 iflib_config_gtask_deinit(struct grouptask *gtask)
5899 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5903 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5905 if_t ifp = ctx->ifc_ifp;
5906 iflib_txq_t txq = ctx->ifc_txqs;
5908 if_setbaudrate(ifp, baudrate);
5909 if (baudrate >= IF_Gbps(10)) {
5911 ctx->ifc_flags |= IFC_PREFETCH;
5914 /* If link down, disable watchdog */
5915 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5916 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5917 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5919 ctx->ifc_link_state = link_state;
5920 if_link_state_change(ifp, link_state);
5924 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5928 int credits_pre = txq->ift_cidx_processed;
5931 if (ctx->isc_txd_credits_update == NULL)
5934 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
5935 BUS_DMASYNC_POSTREAD);
5936 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5939 txq->ift_processed += credits;
5940 txq->ift_cidx_processed += credits;
5942 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5943 if (txq->ift_cidx_processed >= txq->ift_size)
5944 txq->ift_cidx_processed -= txq->ift_size;
5949 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5952 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5957 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5958 const char *description, if_int_delay_info_t info,
5959 int offset, int value)
5961 info->iidi_ctx = ctx;
5962 info->iidi_offset = offset;
5963 info->iidi_value = value;
5964 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5965 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5966 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
5967 info, 0, iflib_sysctl_int_delay, "I", description);
5971 iflib_ctx_lock_get(if_ctx_t ctx)
5974 return (&ctx->ifc_ctx_sx);
5978 iflib_msix_init(if_ctx_t ctx)
5980 device_t dev = ctx->ifc_dev;
5981 if_shared_ctx_t sctx = ctx->ifc_sctx;
5982 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5983 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
5984 int iflib_num_tx_queues, iflib_num_rx_queues;
5985 int err, admincnt, bar;
5987 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
5988 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
5991 device_printf(dev, "msix_init qsets capped at %d\n",
5992 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
5994 bar = ctx->ifc_softc_ctx.isc_msix_bar;
5995 admincnt = sctx->isc_admin_intrcnt;
5996 /* Override by tuneable */
5997 if (scctx->isc_disable_msix)
6000 /* First try MSI-X */
6001 if ((msgs = pci_msix_count(dev)) == 0) {
6003 device_printf(dev, "MSI-X not supported or disabled\n");
6007 * bar == -1 => "trust me I know what I'm doing"
6008 * Some drivers are for hardware that is so shoddily
6009 * documented that no one knows which bars are which
6010 * so the developer has to map all bars. This hack
6011 * allows shoddy garbage to use MSI-X in this framework.
6014 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6015 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6016 if (ctx->ifc_msix_mem == NULL) {
6017 device_printf(dev, "Unable to map MSI-X table\n");
6022 /* use only 1 qset in debug mode */
6023 queuemsgs = min(msgs - admincnt, 1);
6025 queuemsgs = msgs - admincnt;
6028 queues = imin(queuemsgs, rss_getnumbuckets());
6032 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6035 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6036 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6038 /* If we're doing RSS, clamp at the number of RSS buckets */
6039 if (queues > rss_getnumbuckets())
6040 queues = rss_getnumbuckets();
6042 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6043 rx_queues = iflib_num_rx_queues;
6047 if (rx_queues > scctx->isc_nrxqsets)
6048 rx_queues = scctx->isc_nrxqsets;
6051 * We want this to be all logical CPUs by default
6053 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6054 tx_queues = iflib_num_tx_queues;
6056 tx_queues = mp_ncpus;
6058 if (tx_queues > scctx->isc_ntxqsets)
6059 tx_queues = scctx->isc_ntxqsets;
6061 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6063 if (tx_queues != rx_queues)
6065 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6066 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6068 tx_queues = min(rx_queues, tx_queues);
6069 rx_queues = min(rx_queues, tx_queues);
6072 device_printf(dev, "Using %d rx queues %d tx queues\n",
6073 rx_queues, tx_queues);
6075 vectors = rx_queues + admincnt;
6076 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6077 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6079 scctx->isc_vectors = vectors;
6080 scctx->isc_nrxqsets = rx_queues;
6081 scctx->isc_ntxqsets = tx_queues;
6082 scctx->isc_intr = IFLIB_INTR_MSIX;
6087 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n",
6089 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6091 ctx->ifc_msix_mem = NULL;
6094 vectors = pci_msi_count(dev);
6095 scctx->isc_nrxqsets = 1;
6096 scctx->isc_ntxqsets = 1;
6097 scctx->isc_vectors = vectors;
6098 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6099 device_printf(dev,"Using an MSI interrupt\n");
6100 scctx->isc_intr = IFLIB_INTR_MSI;
6102 scctx->isc_vectors = 1;
6103 device_printf(dev,"Using a Legacy interrupt\n");
6104 scctx->isc_intr = IFLIB_INTR_LEGACY;
6110 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6113 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6116 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6118 const char *ring_state = "UNKNOWN";
6121 rc = sysctl_wire_old_buffer(req, 0);
6125 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6130 ring_state = ring_states[state[3]];
6132 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6133 state[0], state[1], state[2], ring_state);
6134 rc = sbuf_finish(sb);
6139 enum iflib_ndesc_handler {
6145 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6147 if_ctx_t ctx = (void *)arg1;
6148 enum iflib_ndesc_handler type = arg2;
6149 char buf[256] = {0};
6154 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6158 case IFLIB_NTXD_HANDLER:
6159 ndesc = ctx->ifc_sysctl_ntxds;
6161 nqs = ctx->ifc_sctx->isc_ntxqs;
6163 case IFLIB_NRXD_HANDLER:
6164 ndesc = ctx->ifc_sysctl_nrxds;
6166 nqs = ctx->ifc_sctx->isc_nrxqs;
6169 panic("unhandled type");
6174 for (i=0; i<8; i++) {
6179 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6182 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6183 if (rc || req->newptr == NULL)
6186 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6187 i++, p = strsep(&next, " ,")) {
6188 ndesc[i] = strtoul(p, NULL, 10);
6194 #define NAME_BUFLEN 32
6196 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6198 device_t dev = iflib_get_dev(ctx);
6199 struct sysctl_oid_list *child, *oid_list;
6200 struct sysctl_ctx_list *ctx_list;
6201 struct sysctl_oid *node;
6203 ctx_list = device_get_sysctl_ctx(dev);
6204 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6205 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6206 CTLFLAG_RD, NULL, "IFLIB fields");
6207 oid_list = SYSCTL_CHILDREN(node);
6209 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6210 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6213 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6214 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6215 "# of txqs to use, 0 => use default #");
6216 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6217 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6218 "# of rxqs to use, 0 => use default #");
6219 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6220 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6221 "permit #txq != #rxq");
6222 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6223 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6224 "disable MSI-X (default 0)");
6225 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6226 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6227 "set the rx budget");
6228 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6229 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6230 "cause tx to abdicate instead of running to completion");
6232 /* XXX change for per-queue sizes */
6233 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6234 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6235 mp_ndesc_handler, "A",
6236 "list of # of tx descriptors to use, 0 = use default #");
6237 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6238 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6239 mp_ndesc_handler, "A",
6240 "list of # of rx descriptors to use, 0 = use default #");
6244 iflib_add_device_sysctl_post(if_ctx_t ctx)
6246 if_shared_ctx_t sctx = ctx->ifc_sctx;
6247 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6248 device_t dev = iflib_get_dev(ctx);
6249 struct sysctl_oid_list *child;
6250 struct sysctl_ctx_list *ctx_list;
6255 char namebuf[NAME_BUFLEN];
6257 struct sysctl_oid *queue_node, *fl_node, *node;
6258 struct sysctl_oid_list *queue_list, *fl_list;
6259 ctx_list = device_get_sysctl_ctx(dev);
6261 node = ctx->ifc_sysctl_node;
6262 child = SYSCTL_CHILDREN(node);
6264 if (scctx->isc_ntxqsets > 100)
6266 else if (scctx->isc_ntxqsets > 10)
6270 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6271 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6272 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6273 CTLFLAG_RD, NULL, "Queue Name");
6274 queue_list = SYSCTL_CHILDREN(queue_node);
6276 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6278 &txq->ift_dequeued, "total mbufs freed");
6279 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6281 &txq->ift_enqueued, "total mbufs enqueued");
6283 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6285 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6286 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6288 &txq->ift_pullups, "# of times m_pullup was called");
6289 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6291 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6292 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6294 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6295 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6297 &txq->ift_map_failed, "# of times dma map failed");
6298 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6300 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6301 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6303 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6304 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6306 &txq->ift_pidx, 1, "Producer Index");
6307 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6309 &txq->ift_cidx, 1, "Consumer Index");
6310 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6312 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6313 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6315 &txq->ift_in_use, 1, "descriptors in use");
6316 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6318 &txq->ift_processed, "descriptors procesed for clean");
6319 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6321 &txq->ift_cleaned, "total cleaned");
6322 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6323 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6324 0, mp_ring_state_handler, "A", "soft ring state");
6325 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6326 CTLFLAG_RD, &txq->ift_br->enqueues,
6327 "# of enqueues to the mp_ring for this queue");
6328 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6329 CTLFLAG_RD, &txq->ift_br->drops,
6330 "# of drops in the mp_ring for this queue");
6331 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6332 CTLFLAG_RD, &txq->ift_br->starts,
6333 "# of normal consumer starts in the mp_ring for this queue");
6334 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6335 CTLFLAG_RD, &txq->ift_br->stalls,
6336 "# of consumer stalls in the mp_ring for this queue");
6337 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6338 CTLFLAG_RD, &txq->ift_br->restarts,
6339 "# of consumer restarts in the mp_ring for this queue");
6340 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6341 CTLFLAG_RD, &txq->ift_br->abdications,
6342 "# of consumer abdications in the mp_ring for this queue");
6345 if (scctx->isc_nrxqsets > 100)
6347 else if (scctx->isc_nrxqsets > 10)
6351 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6352 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6353 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6354 CTLFLAG_RD, NULL, "Queue Name");
6355 queue_list = SYSCTL_CHILDREN(queue_node);
6356 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6357 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6359 &rxq->ifr_cq_pidx, 1, "Producer Index");
6360 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6362 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6365 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6366 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6367 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6368 CTLFLAG_RD, NULL, "freelist Name");
6369 fl_list = SYSCTL_CHILDREN(fl_node);
6370 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6372 &fl->ifl_pidx, 1, "Producer Index");
6373 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6375 &fl->ifl_cidx, 1, "Consumer Index");
6376 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6378 &fl->ifl_credits, 1, "credits available");
6380 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6382 &fl->ifl_m_enqueued, "mbufs allocated");
6383 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6385 &fl->ifl_m_dequeued, "mbufs freed");
6386 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6388 &fl->ifl_cl_enqueued, "clusters allocated");
6389 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6391 &fl->ifl_cl_dequeued, "clusters freed");
6400 iflib_request_reset(if_ctx_t ctx)
6404 ctx->ifc_flags |= IFC_DO_RESET;
6408 #ifndef __NO_STRICT_ALIGNMENT
6409 static struct mbuf *
6410 iflib_fixup_rx(struct mbuf *m)
6414 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6415 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6416 m->m_data += ETHER_HDR_LEN;
6419 MGETHDR(n, M_NOWAIT, MT_DATA);
6424 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6425 m->m_data += ETHER_HDR_LEN;
6426 m->m_len -= ETHER_HDR_LEN;
6427 n->m_len = ETHER_HDR_LEN;
6428 M_MOVE_PKTHDR(n, m);
6437 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6441 ctx = if_getsoftc(ifp);
6443 *nrxr = NRXQSETS(ctx);
6444 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6445 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6450 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6453 if_softc_ctx_t scctx;
6458 ctx = if_getsoftc(ifp);
6459 scctx = &ctx->ifc_softc_ctx;
6463 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6464 rxq = &ctx->ifc_rxqs[i];
6465 for (j = 0; j < rxq->ifr_nfl; j++) {
6467 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6470 iflib_no_tx_batch = 1;
6478 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6484 ctx = if_getsoftc(ifp);
6485 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6489 txq = &ctx->ifc_txqs[0];
6490 error = iflib_encap(txq, &m);
6492 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6497 iflib_netdump_poll(struct ifnet *ifp, int count)
6500 if_softc_ctx_t scctx;
6504 ctx = if_getsoftc(ifp);
6505 scctx = &ctx->ifc_softc_ctx;
6507 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6511 txq = &ctx->ifc_txqs[0];
6512 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6514 for (i = 0; i < scctx->isc_nrxqsets; i++)
6515 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6518 #endif /* NETDUMP */