2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
96 #include <dev/pci/pci_iov.h>
99 #include <sys/bitstring.h>
101 * enable accounting of every mbuf as it comes in to and goes out of
102 * iflib's software descriptor references
104 #define MEMORY_LOGGING 0
106 * Enable mbuf vectors for compressing long mbuf chains
111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
112 * we prefetch needs to be determined by the time spent in m_free vis a vis
113 * the cost of a prefetch. This will of course vary based on the workload:
114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
115 * is quite expensive, thus suggesting very little prefetch.
116 * - small packet forwarding which is just returning a single mbuf to
117 * UMA will typically be very fast vis a vis the cost of a memory
124 * - private structures
125 * - iflib private utility functions
127 * - vlan registry and other exported functions
128 * - iflib public core functions
132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
135 typedef struct iflib_txq *iflib_txq_t;
137 typedef struct iflib_rxq *iflib_rxq_t;
139 typedef struct iflib_fl *iflib_fl_t;
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
146 typedef struct iflib_filter_info {
147 driver_filter_t *ifi_filter;
148 void *ifi_filter_arg;
149 struct grouptask *ifi_task;
151 } *iflib_filter_info_t;
156 * Pointer to hardware driver's softc
163 if_shared_ctx_t ifc_sctx;
164 struct if_softc_ctx ifc_softc_ctx;
166 struct sx ifc_ctx_sx;
167 struct mtx ifc_state_mtx;
169 iflib_txq_t ifc_txqs;
170 iflib_rxq_t ifc_rxqs;
171 uint32_t ifc_if_flags;
173 uint32_t ifc_max_fl_buf_size;
177 int ifc_watchdog_events;
178 struct cdev *ifc_led_dev;
179 struct resource *ifc_msix_mem;
181 struct if_irq ifc_legacy_irq;
182 struct grouptask ifc_admin_task;
183 struct grouptask ifc_vflr_task;
184 struct iflib_filter_info ifc_filter_info;
185 struct ifmedia ifc_media;
187 struct sysctl_oid *ifc_sysctl_node;
188 uint16_t ifc_sysctl_ntxqs;
189 uint16_t ifc_sysctl_nrxqs;
190 uint16_t ifc_sysctl_qs_eq_override;
191 uint16_t ifc_sysctl_rx_budget;
192 uint16_t ifc_sysctl_tx_abdicate;
194 qidx_t ifc_sysctl_ntxds[8];
195 qidx_t ifc_sysctl_nrxds[8];
196 struct if_txrx ifc_txrx;
197 #define isc_txd_encap ifc_txrx.ift_txd_encap
198 #define isc_txd_flush ifc_txrx.ift_txd_flush
199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
200 #define isc_rxd_available ifc_txrx.ift_rxd_available
201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
207 eventhandler_tag ifc_vlan_attach_event;
208 eventhandler_tag ifc_vlan_detach_event;
209 uint8_t ifc_mac[ETHER_ADDR_LEN];
210 char ifc_mtx_name[16];
215 iflib_get_softc(if_ctx_t ctx)
218 return (ctx->ifc_softc);
222 iflib_get_dev(if_ctx_t ctx)
225 return (ctx->ifc_dev);
229 iflib_get_ifp(if_ctx_t ctx)
232 return (ctx->ifc_ifp);
236 iflib_get_media(if_ctx_t ctx)
239 return (&ctx->ifc_media);
243 iflib_get_flags(if_ctx_t ctx)
245 return (ctx->ifc_flags);
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
256 iflib_get_softc_ctx(if_ctx_t ctx)
259 return (&ctx->ifc_softc_ctx);
263 iflib_get_sctx(if_ctx_t ctx)
266 return (ctx->ifc_sctx);
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 typedef struct iflib_sw_rx_desc_array {
277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
278 struct mbuf **ifsd_m; /* pkthdr mbufs */
279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
283 typedef struct iflib_sw_tx_desc_array {
284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
286 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
309 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
310 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
311 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_buf_tag;
357 bus_dma_tag_t ift_tso_buf_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 16
360 char ift_mtx_name[MTX_NAME_LEN];
361 char ift_db_mtx_name[MTX_NAME_LEN];
362 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
363 #ifdef IFLIB_DIAGNOSTICS
364 uint64_t ift_cpu_exec_count[256];
366 } __aligned(CACHE_LINE_SIZE);
373 uint8_t ifl_rxd_size;
375 uint64_t ifl_m_enqueued;
376 uint64_t ifl_m_dequeued;
377 uint64_t ifl_cl_enqueued;
378 uint64_t ifl_cl_dequeued;
382 bitstr_t *ifl_rx_bitmap;
386 uint16_t ifl_buf_size;
389 iflib_rxsd_array_t ifl_sds;
392 bus_dma_tag_t ifl_buf_tag;
393 iflib_dma_info_t ifl_ifdi;
394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 } __aligned(CACHE_LINE_SIZE);
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
406 else if (pidx < cidx)
407 used = size - cidx + pidx;
408 else if (gen == 0 && pidx == cidx)
410 else if (gen == 1 && pidx == cidx)
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
420 #define IDXDIFF(head, tail, wrap) \
421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 /* If there is a separate completion queue -
425 * these are the cq cidx and pidx. Otherwise
432 uint8_t ifr_fl_offset;
438 uint8_t ifr_lro_enabled;
441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
442 struct lro_ctrl ifr_lc;
443 struct grouptask ifr_task;
444 struct iflib_filter_info ifr_filter_info;
445 iflib_dma_info_t ifr_ifdi;
447 /* dynamically allocate if any drivers need a value substantially larger than this */
448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
449 #ifdef IFLIB_DIAGNOSTICS
450 uint64_t ifr_cpu_exec_count[256];
452 } __aligned(CACHE_LINE_SIZE);
454 typedef struct if_rxsd {
456 struct mbuf **ifsd_m;
461 /* multiple of word size */
463 #define PKT_INFO_SIZE 6
464 #define RXD_INFO_SIZE 5
465 #define PKT_TYPE uint64_t
467 #define PKT_INFO_SIZE 11
468 #define RXD_INFO_SIZE 8
469 #define PKT_TYPE uint32_t
471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
474 typedef struct if_pkt_info_pad {
475 PKT_TYPE pkt_val[PKT_INFO_SIZE];
476 } *if_pkt_info_pad_t;
477 typedef struct if_rxd_info_pad {
478 PKT_TYPE rxd_val[RXD_INFO_SIZE];
479 } *if_rxd_info_pad_t;
481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
486 pkt_info_zero(if_pkt_info_t pi)
488 if_pkt_info_pad_t pi_pad;
490 pi_pad = (if_pkt_info_pad_t)pi;
491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
499 static device_method_t iflib_pseudo_methods[] = {
500 DEVMETHOD(device_attach, noop_attach),
501 DEVMETHOD(device_detach, iflib_pseudo_detach),
505 driver_t iflib_pseudodriver = {
506 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
510 rxd_info_zero(if_rxd_info_t ri)
512 if_rxd_info_pad_t ri_pad;
515 ri_pad = (if_rxd_info_pad_t)ri;
516 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
517 ri_pad->rxd_val[i] = 0;
518 ri_pad->rxd_val[i+1] = 0;
519 ri_pad->rxd_val[i+2] = 0;
520 ri_pad->rxd_val[i+3] = 0;
523 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
528 * Only allow a single packet to take up most 1/nth of the tx ring
530 #define MAX_SINGLE_PACKET_FRACTION 12
531 #define IF_BAD_DMA (bus_addr_t)-1
533 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
535 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
536 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
537 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
538 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
541 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
542 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
543 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
544 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
548 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
549 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
552 iflib_set_detach(if_ctx_t ctx)
555 ctx->ifc_flags |= IFC_IN_DETACH;
559 /* Our boot-time initialization hook */
560 static int iflib_module_event_handler(module_t, int, void *);
562 static moduledata_t iflib_moduledata = {
564 iflib_module_event_handler,
568 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
569 MODULE_VERSION(iflib, 1);
571 MODULE_DEPEND(iflib, pci, 1, 1, 1);
572 MODULE_DEPEND(iflib, ether, 1, 1, 1);
574 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
575 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
577 #ifndef IFLIB_DEBUG_COUNTERS
579 #define IFLIB_DEBUG_COUNTERS 1
581 #define IFLIB_DEBUG_COUNTERS 0
582 #endif /* !INVARIANTS */
585 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
586 "iflib driver parameters");
589 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
591 static int iflib_min_tx_latency = 0;
592 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
593 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
594 static int iflib_no_tx_batch = 0;
595 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
596 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
599 #if IFLIB_DEBUG_COUNTERS
601 static int iflib_tx_seen;
602 static int iflib_tx_sent;
603 static int iflib_tx_encap;
604 static int iflib_rx_allocs;
605 static int iflib_fl_refills;
606 static int iflib_fl_refills_large;
607 static int iflib_tx_frees;
609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
610 &iflib_tx_seen, 0, "# tx mbufs seen");
611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
612 &iflib_tx_sent, 0, "# tx mbufs sent");
613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
614 &iflib_tx_encap, 0, "# tx mbufs encapped");
615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
616 &iflib_tx_frees, 0, "# tx frees");
617 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
618 &iflib_rx_allocs, 0, "# rx allocations");
619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
620 &iflib_fl_refills, 0, "# refills");
621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
622 &iflib_fl_refills_large, 0, "# large refills");
625 static int iflib_txq_drain_flushing;
626 static int iflib_txq_drain_oactive;
627 static int iflib_txq_drain_notready;
629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
630 &iflib_txq_drain_flushing, 0, "# drain flushes");
631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
632 &iflib_txq_drain_oactive, 0, "# drain oactives");
633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
634 &iflib_txq_drain_notready, 0, "# drain notready");
637 static int iflib_encap_load_mbuf_fail;
638 static int iflib_encap_pad_mbuf_fail;
639 static int iflib_encap_txq_avail_fail;
640 static int iflib_encap_txd_encap_fail;
642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
643 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
645 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
647 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
649 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
651 static int iflib_task_fn_rxs;
652 static int iflib_rx_intr_enables;
653 static int iflib_fast_intrs;
654 static int iflib_rx_unavail;
655 static int iflib_rx_ctx_inactive;
656 static int iflib_rx_if_input;
657 static int iflib_rx_mbuf_null;
658 static int iflib_rxd_flush;
660 static int iflib_verbose_debug;
662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
665 &iflib_rx_intr_enables, 0, "# rx intr enables");
666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
667 &iflib_fast_intrs, 0, "# fast_intr calls");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
669 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
673 &iflib_rx_if_input, 0, "# times rxeof called if_input");
674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
675 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
676 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
677 &iflib_rxd_flush, 0, "# times rxd_flush called");
678 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
679 &iflib_verbose_debug, 0, "enable verbose debugging");
681 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
683 iflib_debug_reset(void)
685 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
686 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
687 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
688 iflib_txq_drain_notready =
689 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
690 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
691 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
693 iflib_rx_ctx_inactive = iflib_rx_if_input =
694 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
698 #define DBG_COUNTER_INC(name)
699 static void iflib_debug_reset(void) {}
702 #define IFLIB_DEBUG 0
704 static void iflib_tx_structures_free(if_ctx_t ctx);
705 static void iflib_rx_structures_free(if_ctx_t ctx);
706 static int iflib_queues_alloc(if_ctx_t ctx);
707 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
708 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
709 static int iflib_qset_structures_setup(if_ctx_t ctx);
710 static int iflib_msix_init(if_ctx_t ctx);
711 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
712 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
713 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
715 static void iflib_altq_if_start(if_t ifp);
716 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
718 static int iflib_register(if_ctx_t);
719 static void iflib_init_locked(if_ctx_t ctx);
720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
721 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
722 static void iflib_ifmp_purge(iflib_txq_t txq);
723 static void _iflib_pre_assert(if_softc_ctx_t scctx);
724 static void iflib_if_init_locked(if_ctx_t ctx);
725 static void iflib_free_intr_mem(if_ctx_t ctx);
726 #ifndef __NO_STRICT_ALIGNMENT
727 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
730 NETDUMP_DEFINE(iflib);
733 #include <sys/selinfo.h>
734 #include <net/netmap.h>
735 #include <dev/netmap/netmap_kern.h>
737 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
742 * device-specific sysctl variables:
744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
745 * During regular operations the CRC is stripped, but on some
746 * hardware reception of frames not multiple of 64 is slower,
747 * so using crcstrip=0 helps in benchmarks.
749 * iflib_rx_miss, iflib_rx_miss_bufs:
750 * count packets that might be missed due to lost interrupts.
752 SYSCTL_DECL(_dev_netmap);
754 * The xl driver by default strips CRCs and we do not override it.
757 int iflib_crcstrip = 1;
758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
761 int iflib_rx_miss, iflib_rx_miss_bufs;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
768 * Register/unregister. We are already under netmap lock.
769 * Only called on the first register or the last unregister.
772 iflib_netmap_register(struct netmap_adapter *na, int onoff)
774 struct ifnet *ifp = na->ifp;
775 if_ctx_t ctx = ifp->if_softc;
779 IFDI_INTR_DISABLE(ctx);
781 /* Tell the stack that the interface is no longer active */
782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
787 /* enable or disable flags and callbacks in na and ifp */
789 nm_set_native_flags(na);
791 nm_clear_native_flags(na);
794 iflib_init_locked(ctx);
795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
798 nm_clear_native_flags(na);
804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
806 struct netmap_adapter *na = kring->na;
807 u_int const lim = kring->nkr_num_slots - 1;
808 u_int head = kring->rhead;
809 struct netmap_ring *ring = kring->ring;
811 struct if_rxd_update iru;
812 if_ctx_t ctx = rxq->ifr_ctx;
813 iflib_fl_t fl = &rxq->ifr_fl[0];
814 uint32_t refill_pidx, nic_i;
815 #if IFLIB_DEBUG_COUNTERS
819 if (nm_i == head && __predict_true(!init))
821 iru_init(&iru, rxq, 0 /* flid */);
822 map = fl->ifl_sds.ifsd_map;
823 refill_pidx = netmap_idx_k2n(kring, nm_i);
825 * IMPORTANT: we must leave one free slot in the ring,
826 * so move head back by one unit
828 head = nm_prev(head, lim);
830 DBG_COUNTER_INC(fl_refills);
831 while (nm_i != head) {
832 #if IFLIB_DEBUG_COUNTERS
834 DBG_COUNTER_INC(fl_refills_large);
836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
837 struct netmap_slot *slot = &ring->slot[nm_i];
838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
839 uint32_t nic_i_dma = refill_pidx;
840 nic_i = netmap_idx_k2n(kring, nm_i);
842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
845 return netmap_ring_reinit(kring);
847 fl->ifl_vm_addrs[tmp_pidx] = addr;
848 if (__predict_false(init)) {
849 netmap_load_map(na, fl->ifl_buf_tag,
851 } else if (slot->flags & NS_BUF_CHANGED) {
852 /* buffer has changed, reload map */
853 netmap_reload_map(na, fl->ifl_buf_tag,
856 slot->flags &= ~NS_BUF_CHANGED;
858 nm_i = nm_next(nm_i, lim);
859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
863 iru.iru_pidx = refill_pidx;
864 iru.iru_count = tmp_pidx+1;
865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
867 for (int n = 0; n < iru.iru_count; n++) {
868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
869 BUS_DMASYNC_PREREAD);
870 /* XXX - change this to not use the netmap func*/
871 nic_i_dma = nm_next(nic_i_dma, lim);
875 kring->nr_hwcur = head;
877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
879 if (__predict_true(nic_i != UINT_MAX)) {
880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
881 DBG_COUNTER_INC(rxd_flush);
887 * Reconcile kernel and user view of the transmit ring.
889 * All information is in the kring.
890 * Userspace wants to send packets up to the one before kring->rhead,
891 * kernel knows kring->nr_hwcur is the first unsent packet.
893 * Here we push packets out (as many as possible), and possibly
894 * reclaim buffers from previously completed transmission.
896 * The caller (netmap) guarantees that there is only one instance
897 * running at any time. Any interference with other driver
898 * methods should be handled by the individual drivers.
901 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
903 struct netmap_adapter *na = kring->na;
904 struct ifnet *ifp = na->ifp;
905 struct netmap_ring *ring = kring->ring;
906 u_int nm_i; /* index into the netmap kring */
907 u_int nic_i; /* index into the NIC ring */
909 u_int const lim = kring->nkr_num_slots - 1;
910 u_int const head = kring->rhead;
911 struct if_pkt_info pi;
914 * interrupts on every tx packet are expensive so request
915 * them every half ring, or where NS_REPORT is set
917 u_int report_frequency = kring->nkr_num_slots >> 1;
918 /* device-specific */
919 if_ctx_t ctx = ifp->if_softc;
920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
926 * First part: process new packets to send.
927 * nm_i is the current index in the netmap kring,
928 * nic_i is the corresponding index in the NIC ring.
930 * If we have packets to send (nm_i != head)
931 * iterate over the netmap ring, fetch length and update
932 * the corresponding slot in the NIC ring. Some drivers also
933 * need to update the buffer's physical address in the NIC slot
934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
936 * The netmap_reload_map() calls is especially expensive,
937 * even when (as in this case) the tag is 0, so do only
938 * when the buffer has actually changed.
940 * If possible do not set the report/intr bit on all slots,
941 * but only a few times per ring or when NS_REPORT is set.
943 * Finally, on 10G and faster drivers, it might be useful
944 * to prefetch the next slot and txr entry.
947 nm_i = kring->nr_hwcur;
948 if (nm_i != head) { /* we have new packets to send */
950 pi.ipi_segs = txq->ift_segs;
951 pi.ipi_qsidx = kring->ring_id;
952 nic_i = netmap_idx_k2n(kring, nm_i);
954 __builtin_prefetch(&ring->slot[nm_i]);
955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
958 for (n = 0; nm_i != head; n++) {
959 struct netmap_slot *slot = &ring->slot[nm_i];
960 u_int len = slot->len;
962 void *addr = PNMB(na, slot, &paddr);
963 int flags = (slot->flags & NS_REPORT ||
964 nic_i == 0 || nic_i == report_frequency) ?
967 /* device-specific */
969 pi.ipi_segs[0].ds_addr = paddr;
970 pi.ipi_segs[0].ds_len = len;
974 pi.ipi_flags = flags;
976 /* Fill the slot in the NIC ring. */
977 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
978 DBG_COUNTER_INC(tx_encap);
980 /* prefetch for next round */
981 __builtin_prefetch(&ring->slot[nm_i + 1]);
982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
985 NM_CHECK_ADDR_LEN(na, addr, len);
987 if (slot->flags & NS_BUF_CHANGED) {
988 /* buffer has changed, reload map */
989 netmap_reload_map(na, txq->ift_buf_tag,
990 txq->ift_sds.ifsd_map[nic_i], addr);
992 /* make sure changes to the buffer are synced */
993 bus_dmamap_sync(txq->ift_buf_tag,
994 txq->ift_sds.ifsd_map[nic_i],
995 BUS_DMASYNC_PREWRITE);
997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
998 nm_i = nm_next(nm_i, lim);
999 nic_i = nm_next(nic_i, lim);
1001 kring->nr_hwcur = nm_i;
1003 /* synchronize the NIC ring */
1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1007 /* (re)start the tx unit up to slot nic_i (excluded) */
1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1012 * Second part: reclaim buffers for completed transmissions.
1014 * If there are unclaimed buffers, attempt to reclaim them.
1015 * If none are reclaimed, and TX IRQs are not in use, do an initial
1016 * minimal delay, then trigger the tx handler which will spin in the
1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1020 if (iflib_tx_credits_update(ctx, txq)) {
1021 /* some tx completed, increment avail */
1022 nic_i = txq->ift_cidx_processed;
1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1029 iflib_timer, txq, txq->ift_timer.c_cpu);
1035 * Reconcile kernel and user view of the receive ring.
1036 * Same as for the txsync, this routine must be efficient.
1037 * The caller guarantees a single invocations, but races against
1038 * the rest of the driver should be handled here.
1040 * On call, kring->rhead is the first packet that userspace wants
1041 * to keep, and kring->rcur is the wakeup point.
1042 * The kernel has previously reported packets up to kring->rtail.
1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1045 * of whether or not we received an interrupt.
1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1050 struct netmap_adapter *na = kring->na;
1051 struct netmap_ring *ring = kring->ring;
1053 uint32_t nm_i; /* index into the netmap ring */
1054 uint32_t nic_i; /* index into the NIC ring */
1056 u_int const lim = kring->nkr_num_slots - 1;
1057 u_int const head = kring->rhead;
1058 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1059 struct if_rxd_info ri;
1061 struct ifnet *ifp = na->ifp;
1062 if_ctx_t ctx = ifp->if_softc;
1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1065 return netmap_ring_reinit(kring);
1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1077 * First part: import newly received packets.
1079 * nm_i is the index of the next free slot in the netmap ring,
1080 * nic_i is the index of the next received packet in the NIC ring,
1081 * and they may differ in case if_init() has been called while
1082 * in netmap mode. For the receive ring we have
1084 * nic_i = rxr->next_check;
1085 * nm_i = kring->nr_hwtail (previous)
1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1089 * rxr->next_check is set to 0 on a ring reinit
1091 if (netmap_no_pendintr || force_update) {
1092 int crclen = iflib_crcstrip ? 0 : 4;
1095 for (i = 0; i < rxq->ifr_nfl; i++) {
1096 fl = &rxq->ifr_fl[i];
1097 nic_i = fl->ifl_cidx;
1098 nm_i = netmap_idx_n2k(kring, nic_i);
1099 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1100 rxq->ifr_id, nic_i, USHRT_MAX);
1101 for (n = 0; avail > 0; n++, avail--) {
1103 ri.iri_frags = rxq->ifr_frags;
1104 ri.iri_qsidx = kring->ring_id;
1105 ri.iri_ifp = ctx->ifc_ifp;
1106 ri.iri_cidx = nic_i;
1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1110 ring->slot[nm_i].flags = 0;
1111 bus_dmamap_sync(fl->ifl_buf_tag,
1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1113 nm_i = nm_next(nm_i, lim);
1114 nic_i = nm_next(nic_i, lim);
1116 if (n) { /* update the state variables */
1117 if (netmap_no_pendintr && !force_update) {
1120 iflib_rx_miss_bufs += n;
1122 fl->ifl_cidx = nic_i;
1123 kring->nr_hwtail = nm_i;
1125 kring->nr_kflags &= ~NKR_PENDINTR;
1129 * Second part: skip past packets that userspace has released.
1130 * (kring->nr_hwcur to head excluded),
1131 * and make the buffers available for reception.
1132 * As usual nm_i is the index in the netmap ring,
1133 * nic_i is the index in the NIC ring, and
1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1136 /* XXX not sure how this will work with multiple free lists */
1137 nm_i = kring->nr_hwcur;
1139 return (netmap_fl_refill(rxq, kring, nm_i, false));
1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1145 struct ifnet *ifp = na->ifp;
1146 if_ctx_t ctx = ifp->if_softc;
1150 IFDI_INTR_ENABLE(ctx);
1152 IFDI_INTR_DISABLE(ctx);
1159 iflib_netmap_attach(if_ctx_t ctx)
1161 struct netmap_adapter na;
1162 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1164 bzero(&na, sizeof(na));
1166 na.ifp = ctx->ifc_ifp;
1167 na.na_flags = NAF_BDG_MAYSLEEP;
1168 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1169 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1171 na.num_tx_desc = scctx->isc_ntxd[0];
1172 na.num_rx_desc = scctx->isc_nrxd[0];
1173 na.nm_txsync = iflib_netmap_txsync;
1174 na.nm_rxsync = iflib_netmap_rxsync;
1175 na.nm_register = iflib_netmap_register;
1176 na.nm_intr = iflib_netmap_intr;
1177 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1178 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1179 return (netmap_attach(&na));
1183 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1185 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1186 struct netmap_slot *slot;
1188 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1191 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1194 * In netmap mode, set the map for the packet buffer.
1195 * NOTE: Some drivers (not this one) also need to set
1196 * the physical buffer address in the NIC ring.
1197 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1198 * netmap slot index, si
1200 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1201 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1202 NMB(na, slot + si));
1207 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1209 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1210 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1211 struct netmap_slot *slot;
1214 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1217 nm_i = netmap_idx_n2k(kring, 0);
1218 netmap_fl_refill(rxq, kring, nm_i, true);
1222 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1224 struct netmap_kring *kring;
1227 txqid = txq->ift_id;
1228 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1230 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1231 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1232 BUS_DMASYNC_POSTREAD);
1233 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1234 netmap_tx_irq(ctx->ifc_ifp, txqid);
1235 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1239 *reset_on = hz / 1000;
1244 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1247 #define iflib_netmap_txq_init(ctx, txq)
1248 #define iflib_netmap_rxq_init(ctx, rxq)
1249 #define iflib_netmap_detach(ifp)
1251 #define iflib_netmap_attach(ctx) (0)
1252 #define netmap_rx_irq(ifp, qid, budget) (0)
1253 #define netmap_tx_irq(ifp, qid) do {} while (0)
1254 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1258 #if defined(__i386__) || defined(__amd64__)
1259 static __inline void
1262 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1264 static __inline void
1265 prefetch2cachelines(void *x)
1267 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1268 #if (CACHE_LINE_SIZE < 128)
1269 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1274 #define prefetch2cachelines(x)
1278 iflib_gen_mac(if_ctx_t ctx)
1282 char uuid[HOSTUUIDLEN+1];
1283 char buf[HOSTUUIDLEN+16];
1285 unsigned char digest[16];
1289 uuid[HOSTUUIDLEN] = 0;
1290 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1291 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1293 * Generate a pseudo-random, deterministic MAC
1294 * address based on the UUID and unit number.
1295 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1298 MD5Update(&mdctx, buf, strlen(buf));
1299 MD5Final(digest, &mdctx);
1310 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1314 fl = &rxq->ifr_fl[flid];
1315 iru->iru_paddrs = fl->ifl_bus_addrs;
1316 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1317 iru->iru_idxs = fl->ifl_rxd_idxs;
1318 iru->iru_qsidx = rxq->ifr_id;
1319 iru->iru_buf_size = fl->ifl_buf_size;
1320 iru->iru_flidx = fl->ifl_id;
1324 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1328 *(bus_addr_t *) arg = segs[0].ds_addr;
1332 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1335 device_t dev = ctx->ifc_dev;
1337 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1338 align, 0, /* alignment, bounds */
1339 BUS_SPACE_MAXADDR, /* lowaddr */
1340 BUS_SPACE_MAXADDR, /* highaddr */
1341 NULL, NULL, /* filter, filterarg */
1344 size, /* maxsegsize */
1345 BUS_DMA_ALLOCNOW, /* flags */
1346 NULL, /* lockfunc */
1351 "%s: bus_dma_tag_create failed: %d\n",
1356 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1357 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1360 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1361 __func__, (uintmax_t)size, err);
1365 dma->idi_paddr = IF_BAD_DMA;
1366 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1367 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1368 if (err || dma->idi_paddr == IF_BAD_DMA) {
1370 "%s: bus_dmamap_load failed: %d\n",
1375 dma->idi_size = size;
1379 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1381 bus_dma_tag_destroy(dma->idi_tag);
1383 dma->idi_tag = NULL;
1389 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1391 if_shared_ctx_t sctx = ctx->ifc_sctx;
1393 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1395 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1399 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1402 iflib_dma_info_t *dmaiter;
1405 for (i = 0; i < count; i++, dmaiter++) {
1406 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1410 iflib_dma_free_multi(dmalist, i);
1415 iflib_dma_free(iflib_dma_info_t dma)
1417 if (dma->idi_tag == NULL)
1419 if (dma->idi_paddr != IF_BAD_DMA) {
1420 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1421 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1422 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1423 dma->idi_paddr = IF_BAD_DMA;
1425 if (dma->idi_vaddr != NULL) {
1426 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1427 dma->idi_vaddr = NULL;
1429 bus_dma_tag_destroy(dma->idi_tag);
1430 dma->idi_tag = NULL;
1434 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1437 iflib_dma_info_t *dmaiter = dmalist;
1439 for (i = 0; i < count; i++, dmaiter++)
1440 iflib_dma_free(*dmaiter);
1443 #ifdef EARLY_AP_STARTUP
1444 static const int iflib_started = 1;
1447 * We used to abuse the smp_started flag to decide if the queues have been
1448 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1449 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1450 * is set. Run a SYSINIT() strictly after that to just set a usable
1454 static int iflib_started;
1457 iflib_record_started(void *arg)
1462 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1463 iflib_record_started, NULL);
1467 iflib_fast_intr(void *arg)
1469 iflib_filter_info_t info = arg;
1470 struct grouptask *gtask = info->ifi_task;
1474 return (FILTER_STRAY);
1476 DBG_COUNTER_INC(fast_intrs);
1477 if (info->ifi_filter != NULL) {
1478 result = info->ifi_filter(info->ifi_filter_arg);
1479 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1483 GROUPTASK_ENQUEUE(gtask);
1484 return (FILTER_HANDLED);
1488 iflib_fast_intr_rxtx(void *arg)
1490 iflib_filter_info_t info = arg;
1491 struct grouptask *gtask = info->ifi_task;
1493 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1496 int i, cidx, result;
1500 return (FILTER_STRAY);
1502 DBG_COUNTER_INC(fast_intrs);
1503 if (info->ifi_filter != NULL) {
1504 result = info->ifi_filter(info->ifi_filter_arg);
1505 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1510 sc = ctx->ifc_softc;
1511 MPASS(rxq->ifr_ntxqirq);
1512 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1513 txqid = rxq->ifr_txqid[i];
1514 txq = &ctx->ifc_txqs[txqid];
1515 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1516 BUS_DMASYNC_POSTREAD);
1517 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1518 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1521 GROUPTASK_ENQUEUE(&txq->ift_task);
1523 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1524 cidx = rxq->ifr_cq_cidx;
1526 cidx = rxq->ifr_fl[0].ifl_cidx;
1527 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1528 GROUPTASK_ENQUEUE(gtask);
1530 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1531 DBG_COUNTER_INC(rx_intr_enables);
1533 return (FILTER_HANDLED);
1538 iflib_fast_intr_ctx(void *arg)
1540 iflib_filter_info_t info = arg;
1541 struct grouptask *gtask = info->ifi_task;
1545 return (FILTER_STRAY);
1547 DBG_COUNTER_INC(fast_intrs);
1548 if (info->ifi_filter != NULL) {
1549 result = info->ifi_filter(info->ifi_filter_arg);
1550 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1554 GROUPTASK_ENQUEUE(gtask);
1555 return (FILTER_HANDLED);
1559 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1560 driver_filter_t filter, driver_intr_t handler, void *arg,
1564 struct resource *res;
1566 device_t dev = ctx->ifc_dev;
1569 if (ctx->ifc_flags & IFC_LEGACY)
1570 flags |= RF_SHAREABLE;
1573 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1576 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1580 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1581 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1582 filter, handler, arg, &tag);
1585 "failed to setup interrupt for rid %d, name %s: %d\n",
1586 rid, name ? name : "unknown", rc);
1589 bus_describe_intr(dev, res, tag, "%s", name);
1596 /*********************************************************************
1598 * Allocate DMA resources for TX buffers as well as memory for the TX
1599 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1600 * iflib_sw_tx_desc_array structure, storing all the information that
1601 * is needed to transmit a packet on the wire. This is called only
1602 * once at attach, setup is done every reset.
1604 **********************************************************************/
1606 iflib_txsd_alloc(iflib_txq_t txq)
1608 if_ctx_t ctx = txq->ift_ctx;
1609 if_shared_ctx_t sctx = ctx->ifc_sctx;
1610 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1611 device_t dev = ctx->ifc_dev;
1612 bus_size_t tsomaxsize;
1613 int err, nsegments, ntsosegments;
1616 nsegments = scctx->isc_tx_nsegments;
1617 ntsosegments = scctx->isc_tx_tso_segments_max;
1618 tsomaxsize = scctx->isc_tx_tso_size_max;
1619 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1620 tsomaxsize += sizeof(struct ether_vlan_header);
1621 MPASS(scctx->isc_ntxd[0] > 0);
1622 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1623 MPASS(nsegments > 0);
1624 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1625 MPASS(ntsosegments > 0);
1626 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1630 * Set up DMA tags for TX buffers.
1632 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1633 1, 0, /* alignment, bounds */
1634 BUS_SPACE_MAXADDR, /* lowaddr */
1635 BUS_SPACE_MAXADDR, /* highaddr */
1636 NULL, NULL, /* filter, filterarg */
1637 sctx->isc_tx_maxsize, /* maxsize */
1638 nsegments, /* nsegments */
1639 sctx->isc_tx_maxsegsize, /* maxsegsize */
1641 NULL, /* lockfunc */
1642 NULL, /* lockfuncarg */
1643 &txq->ift_buf_tag))) {
1644 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1645 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1646 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1649 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1650 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1651 1, 0, /* alignment, bounds */
1652 BUS_SPACE_MAXADDR, /* lowaddr */
1653 BUS_SPACE_MAXADDR, /* highaddr */
1654 NULL, NULL, /* filter, filterarg */
1655 tsomaxsize, /* maxsize */
1656 ntsosegments, /* nsegments */
1657 sctx->isc_tso_maxsegsize,/* maxsegsize */
1659 NULL, /* lockfunc */
1660 NULL, /* lockfuncarg */
1661 &txq->ift_tso_buf_tag))) {
1662 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1667 /* Allocate memory for the TX mbuf map. */
1668 if (!(txq->ift_sds.ifsd_m =
1669 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1670 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1671 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1677 * Create the DMA maps for TX buffers.
1679 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1680 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1681 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1683 "Unable to allocate TX buffer DMA map memory\n");
1687 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1688 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1689 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1691 "Unable to allocate TSO TX buffer map memory\n");
1695 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1696 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1697 &txq->ift_sds.ifsd_map[i]);
1699 device_printf(dev, "Unable to create TX DMA map\n");
1704 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1705 &txq->ift_sds.ifsd_tso_map[i]);
1707 device_printf(dev, "Unable to create TSO TX DMA map\n");
1713 /* We free all, it handles case where we are in the middle */
1714 iflib_tx_structures_free(ctx);
1719 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1724 if (txq->ift_sds.ifsd_map != NULL)
1725 map = txq->ift_sds.ifsd_map[i];
1727 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1728 bus_dmamap_unload(txq->ift_buf_tag, map);
1729 bus_dmamap_destroy(txq->ift_buf_tag, map);
1730 txq->ift_sds.ifsd_map[i] = NULL;
1734 if (txq->ift_sds.ifsd_tso_map != NULL)
1735 map = txq->ift_sds.ifsd_tso_map[i];
1737 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1738 BUS_DMASYNC_POSTWRITE);
1739 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1740 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1741 txq->ift_sds.ifsd_tso_map[i] = NULL;
1746 iflib_txq_destroy(iflib_txq_t txq)
1748 if_ctx_t ctx = txq->ift_ctx;
1750 for (int i = 0; i < txq->ift_size; i++)
1751 iflib_txsd_destroy(ctx, txq, i);
1752 if (txq->ift_sds.ifsd_map != NULL) {
1753 free(txq->ift_sds.ifsd_map, M_IFLIB);
1754 txq->ift_sds.ifsd_map = NULL;
1756 if (txq->ift_sds.ifsd_tso_map != NULL) {
1757 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1758 txq->ift_sds.ifsd_tso_map = NULL;
1760 if (txq->ift_sds.ifsd_m != NULL) {
1761 free(txq->ift_sds.ifsd_m, M_IFLIB);
1762 txq->ift_sds.ifsd_m = NULL;
1764 if (txq->ift_buf_tag != NULL) {
1765 bus_dma_tag_destroy(txq->ift_buf_tag);
1766 txq->ift_buf_tag = NULL;
1768 if (txq->ift_tso_buf_tag != NULL) {
1769 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1770 txq->ift_tso_buf_tag = NULL;
1775 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1779 mp = &txq->ift_sds.ifsd_m[i];
1783 if (txq->ift_sds.ifsd_map != NULL) {
1784 bus_dmamap_sync(txq->ift_buf_tag,
1785 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1786 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1788 if (txq->ift_sds.ifsd_tso_map != NULL) {
1789 bus_dmamap_sync(txq->ift_tso_buf_tag,
1790 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1791 bus_dmamap_unload(txq->ift_tso_buf_tag,
1792 txq->ift_sds.ifsd_tso_map[i]);
1795 DBG_COUNTER_INC(tx_frees);
1800 iflib_txq_setup(iflib_txq_t txq)
1802 if_ctx_t ctx = txq->ift_ctx;
1803 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1804 if_shared_ctx_t sctx = ctx->ifc_sctx;
1805 iflib_dma_info_t di;
1808 /* Set number of descriptors available */
1809 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1810 /* XXX make configurable */
1811 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1814 txq->ift_cidx_processed = 0;
1815 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1816 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1818 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1819 bzero((void *)di->idi_vaddr, di->idi_size);
1821 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1822 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1823 bus_dmamap_sync(di->idi_tag, di->idi_map,
1824 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1828 /*********************************************************************
1830 * Allocate DMA resources for RX buffers as well as memory for the RX
1831 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1832 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1833 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1834 * Since we use use one entry in iflib_sw_rx_desc_array per received
1835 * packet, the maximum number of entries we'll need is equal to the
1836 * number of hardware receive descriptors that we've allocated.
1838 **********************************************************************/
1840 iflib_rxsd_alloc(iflib_rxq_t rxq)
1842 if_ctx_t ctx = rxq->ifr_ctx;
1843 if_shared_ctx_t sctx = ctx->ifc_sctx;
1844 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1845 device_t dev = ctx->ifc_dev;
1849 MPASS(scctx->isc_nrxd[0] > 0);
1850 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1853 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1854 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1855 /* Set up DMA tag for RX buffers. */
1856 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1857 1, 0, /* alignment, bounds */
1858 BUS_SPACE_MAXADDR, /* lowaddr */
1859 BUS_SPACE_MAXADDR, /* highaddr */
1860 NULL, NULL, /* filter, filterarg */
1861 sctx->isc_rx_maxsize, /* maxsize */
1862 sctx->isc_rx_nsegments, /* nsegments */
1863 sctx->isc_rx_maxsegsize, /* maxsegsize */
1865 NULL, /* lockfunc */
1870 "Unable to allocate RX DMA tag: %d\n", err);
1874 /* Allocate memory for the RX mbuf map. */
1875 if (!(fl->ifl_sds.ifsd_m =
1876 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1877 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1879 "Unable to allocate RX mbuf map memory\n");
1884 /* Allocate memory for the direct RX cluster pointer map. */
1885 if (!(fl->ifl_sds.ifsd_cl =
1886 (caddr_t *) malloc(sizeof(caddr_t) *
1887 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1889 "Unable to allocate RX cluster map memory\n");
1894 /* Allocate memory for the RX cluster bus address map. */
1895 if (!(fl->ifl_sds.ifsd_ba =
1896 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1897 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1899 "Unable to allocate RX bus address map memory\n");
1905 * Create the DMA maps for RX buffers.
1907 if (!(fl->ifl_sds.ifsd_map =
1908 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1910 "Unable to allocate RX buffer DMA map memory\n");
1914 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1915 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1916 &fl->ifl_sds.ifsd_map[i]);
1918 device_printf(dev, "Unable to create RX buffer DMA map\n");
1926 iflib_rx_structures_free(ctx);
1932 * Internal service routines
1935 struct rxq_refill_cb_arg {
1937 bus_dma_segment_t seg;
1942 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1944 struct rxq_refill_cb_arg *cb_arg = arg;
1946 cb_arg->error = error;
1947 cb_arg->seg = segs[0];
1948 cb_arg->nseg = nseg;
1952 * rxq_refill - refill an rxq free-buffer list
1953 * @ctx: the iflib context
1954 * @rxq: the free-list to refill
1955 * @n: the number of new buffers to allocate
1957 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1958 * The caller must assure that @n does not exceed the queue's capacity.
1961 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1963 struct if_rxd_update iru;
1964 struct rxq_refill_cb_arg cb_arg;
1968 bus_dmamap_t *sd_map;
1969 bus_addr_t bus_addr, *sd_ba;
1970 int err, frag_idx, i, idx, n, pidx;
1973 sd_m = fl->ifl_sds.ifsd_m;
1974 sd_map = fl->ifl_sds.ifsd_map;
1975 sd_cl = fl->ifl_sds.ifsd_cl;
1976 sd_ba = fl->ifl_sds.ifsd_ba;
1977 pidx = fl->ifl_pidx;
1979 frag_idx = fl->ifl_fragidx;
1980 credits = fl->ifl_credits;
1985 MPASS(credits + n <= fl->ifl_size);
1987 if (pidx < fl->ifl_cidx)
1988 MPASS(pidx + n <= fl->ifl_cidx);
1989 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1990 MPASS(fl->ifl_gen == 0);
1991 if (pidx > fl->ifl_cidx)
1992 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1994 DBG_COUNTER_INC(fl_refills);
1996 DBG_COUNTER_INC(fl_refills_large);
1997 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2000 * We allocate an uninitialized mbuf + cluster, mbuf is
2001 * initialized after rx.
2003 * If the cluster is still set then we know a minimum sized packet was received
2005 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2008 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2009 MPASS(frag_idx >= 0);
2010 if ((cl = sd_cl[frag_idx]) == NULL) {
2011 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
2015 MPASS(sd_map != NULL);
2016 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2017 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2019 if (err != 0 || cb_arg.error) {
2023 if (fl->ifl_zone == zone_pack)
2024 uma_zfree(fl->ifl_zone, cl);
2028 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2029 sd_cl[frag_idx] = cl;
2031 fl->ifl_cl_enqueued++;
2034 bus_addr = sd_ba[frag_idx];
2036 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2037 BUS_DMASYNC_PREREAD);
2039 MPASS(sd_m[frag_idx] == NULL);
2040 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2044 bit_set(fl->ifl_rx_bitmap, frag_idx);
2046 fl->ifl_m_enqueued++;
2049 DBG_COUNTER_INC(rx_allocs);
2050 fl->ifl_rxd_idxs[i] = frag_idx;
2051 fl->ifl_bus_addrs[i] = bus_addr;
2052 fl->ifl_vm_addrs[i] = cl;
2055 MPASS(credits <= fl->ifl_size);
2056 if (++idx == fl->ifl_size) {
2060 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2061 iru.iru_pidx = pidx;
2063 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2067 fl->ifl_credits = credits;
2072 iru.iru_pidx = pidx;
2074 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2076 fl->ifl_credits = credits;
2078 DBG_COUNTER_INC(rxd_flush);
2079 if (fl->ifl_pidx == 0)
2080 pidx = fl->ifl_size - 1;
2082 pidx = fl->ifl_pidx - 1;
2084 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2086 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2087 fl->ifl_fragidx = frag_idx;
2090 static __inline void
2091 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2093 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2094 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2096 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2099 MPASS(fl->ifl_credits <= fl->ifl_size);
2100 MPASS(reclaimable == delta);
2102 if (reclaimable > 0)
2103 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2107 iflib_in_detach(if_ctx_t ctx)
2111 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2117 iflib_fl_bufs_free(iflib_fl_t fl)
2119 iflib_dma_info_t idi = fl->ifl_ifdi;
2120 bus_dmamap_t sd_map;
2123 for (i = 0; i < fl->ifl_size; i++) {
2124 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2125 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2127 if (*sd_cl != NULL) {
2128 sd_map = fl->ifl_sds.ifsd_map[i];
2129 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2130 BUS_DMASYNC_POSTREAD);
2131 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2133 uma_zfree(fl->ifl_zone, *sd_cl);
2134 // XXX: Should this get moved out?
2135 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2136 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2137 if (*sd_m != NULL) {
2138 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2139 uma_zfree(zone_mbuf, *sd_m);
2142 MPASS(*sd_cl == NULL);
2143 MPASS(*sd_m == NULL);
2146 fl->ifl_m_dequeued++;
2147 fl->ifl_cl_dequeued++;
2153 for (i = 0; i < fl->ifl_size; i++) {
2154 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2155 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2159 * Reset free list values
2161 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2162 bzero(idi->idi_vaddr, idi->idi_size);
2165 /*********************************************************************
2167 * Initialize a receive ring and its buffers.
2169 **********************************************************************/
2171 iflib_fl_setup(iflib_fl_t fl)
2173 iflib_rxq_t rxq = fl->ifl_rxq;
2174 if_ctx_t ctx = rxq->ifr_ctx;
2175 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2177 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2179 ** Free current RX buffer structs and their mbufs
2181 iflib_fl_bufs_free(fl);
2182 /* Now replenish the mbufs */
2183 MPASS(fl->ifl_credits == 0);
2185 * XXX don't set the max_frame_size to larger
2186 * than the hardware can handle
2188 if (sctx->isc_max_frame_size <= 2048)
2189 fl->ifl_buf_size = MCLBYTES;
2190 #ifndef CONTIGMALLOC_WORKS
2192 fl->ifl_buf_size = MJUMPAGESIZE;
2194 else if (sctx->isc_max_frame_size <= 4096)
2195 fl->ifl_buf_size = MJUMPAGESIZE;
2196 else if (sctx->isc_max_frame_size <= 9216)
2197 fl->ifl_buf_size = MJUM9BYTES;
2199 fl->ifl_buf_size = MJUM16BYTES;
2201 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2202 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2203 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2204 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2207 /* avoid pre-allocating zillions of clusters to an idle card
2208 * potentially speeding up attach
2210 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2211 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2212 if (min(128, fl->ifl_size) != fl->ifl_credits)
2218 MPASS(fl->ifl_ifdi != NULL);
2219 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2220 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2224 /*********************************************************************
2226 * Free receive ring data structures
2228 **********************************************************************/
2230 iflib_rx_sds_free(iflib_rxq_t rxq)
2235 if (rxq->ifr_fl != NULL) {
2236 for (i = 0; i < rxq->ifr_nfl; i++) {
2237 fl = &rxq->ifr_fl[i];
2238 if (fl->ifl_buf_tag != NULL) {
2239 if (fl->ifl_sds.ifsd_map != NULL) {
2240 for (j = 0; j < fl->ifl_size; j++) {
2241 if (fl->ifl_sds.ifsd_map[j] ==
2246 fl->ifl_sds.ifsd_map[j],
2247 BUS_DMASYNC_POSTREAD);
2250 fl->ifl_sds.ifsd_map[j]);
2253 bus_dma_tag_destroy(fl->ifl_buf_tag);
2254 fl->ifl_buf_tag = NULL;
2256 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2257 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2258 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2259 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2260 fl->ifl_sds.ifsd_m = NULL;
2261 fl->ifl_sds.ifsd_cl = NULL;
2262 fl->ifl_sds.ifsd_ba = NULL;
2263 fl->ifl_sds.ifsd_map = NULL;
2265 free(rxq->ifr_fl, M_IFLIB);
2267 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2272 * MI independent logic
2276 iflib_timer(void *arg)
2278 iflib_txq_t txq = arg;
2279 if_ctx_t ctx = txq->ift_ctx;
2280 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2281 uint64_t this_tick = ticks;
2282 uint32_t reset_on = hz / 2;
2284 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2287 ** Check on the state of the TX queue(s), this
2288 ** can be done without the lock because its RO
2289 ** and the HUNG state will be static if set.
2291 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2292 txq->ift_last_timer_tick = this_tick;
2293 IFDI_TIMER(ctx, txq->ift_id);
2294 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2295 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2296 (sctx->isc_pause_frames == 0)))
2299 if (ifmp_ring_is_stalled(txq->ift_br))
2300 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2301 txq->ift_cleaned_prev = txq->ift_cleaned;
2304 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2305 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2307 /* handle any laggards */
2308 if (txq->ift_db_pending)
2309 GROUPTASK_ENQUEUE(&txq->ift_task);
2311 sctx->isc_pause_frames = 0;
2312 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2313 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2316 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2317 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2319 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2320 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2321 iflib_admin_intr_deferred(ctx);
2326 iflib_init_locked(if_ctx_t ctx)
2328 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2329 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2330 if_t ifp = ctx->ifc_ifp;
2334 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2337 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2338 IFDI_INTR_DISABLE(ctx);
2340 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2341 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2342 /* Set hardware offload abilities */
2343 if_clearhwassist(ifp);
2344 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2345 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2346 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2347 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2348 if (if_getcapenable(ifp) & IFCAP_TSO4)
2349 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2350 if (if_getcapenable(ifp) & IFCAP_TSO6)
2351 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2353 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2355 callout_stop(&txq->ift_timer);
2356 CALLOUT_UNLOCK(txq);
2357 iflib_netmap_txq_init(ctx, txq);
2360 i = if_getdrvflags(ifp);
2363 MPASS(if_getdrvflags(ifp) == i);
2364 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2365 /* XXX this should really be done on a per-queue basis */
2366 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2367 MPASS(rxq->ifr_id == i);
2368 iflib_netmap_rxq_init(ctx, rxq);
2371 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2372 if (iflib_fl_setup(fl)) {
2373 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2379 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2380 IFDI_INTR_ENABLE(ctx);
2381 txq = ctx->ifc_txqs;
2382 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2383 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2384 txq->ift_timer.c_cpu);
2388 iflib_media_change(if_t ifp)
2390 if_ctx_t ctx = if_getsoftc(ifp);
2394 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2395 iflib_init_locked(ctx);
2401 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2403 if_ctx_t ctx = if_getsoftc(ifp);
2406 IFDI_UPDATE_ADMIN_STATUS(ctx);
2407 IFDI_MEDIA_STATUS(ctx, ifmr);
2412 iflib_stop(if_ctx_t ctx)
2414 iflib_txq_t txq = ctx->ifc_txqs;
2415 iflib_rxq_t rxq = ctx->ifc_rxqs;
2416 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2417 if_shared_ctx_t sctx = ctx->ifc_sctx;
2418 iflib_dma_info_t di;
2422 /* Tell the stack that the interface is no longer active */
2423 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2425 IFDI_INTR_DISABLE(ctx);
2430 iflib_debug_reset();
2431 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2432 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2433 /* make sure all transmitters have completed before proceeding XXX */
2436 callout_stop(&txq->ift_timer);
2437 CALLOUT_UNLOCK(txq);
2439 /* clean any enqueued buffers */
2440 iflib_ifmp_purge(txq);
2441 /* Free any existing tx buffers. */
2442 for (j = 0; j < txq->ift_size; j++) {
2443 iflib_txsd_free(ctx, txq, j);
2445 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2446 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2447 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2448 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2449 txq->ift_pullups = 0;
2450 ifmp_ring_reset_stats(txq->ift_br);
2451 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2452 bzero((void *)di->idi_vaddr, di->idi_size);
2454 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2455 /* make sure all transmitters have completed before proceeding XXX */
2457 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2458 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2459 bzero((void *)di->idi_vaddr, di->idi_size);
2460 /* also resets the free lists pidx/cidx */
2461 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2462 iflib_fl_bufs_free(fl);
2466 static inline caddr_t
2467 calc_next_rxd(iflib_fl_t fl, int cidx)
2471 caddr_t start, end, cur, next;
2473 nrxd = fl->ifl_size;
2474 size = fl->ifl_rxd_size;
2475 start = fl->ifl_ifdi->idi_vaddr;
2477 if (__predict_false(size == 0))
2479 cur = start + size*cidx;
2480 end = start + size*nrxd;
2481 next = CACHE_PTR_NEXT(cur);
2482 return (next < end ? next : start);
2486 prefetch_pkts(iflib_fl_t fl, int cidx)
2489 int nrxd = fl->ifl_size;
2493 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2494 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2495 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2496 next_rxd = calc_next_rxd(fl, cidx);
2498 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2499 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2500 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2501 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2502 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2503 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2504 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2505 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2509 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2517 flid = irf->irf_flid;
2518 cidx = irf->irf_idx;
2519 fl = &rxq->ifr_fl[flid];
2521 sd->ifsd_cidx = cidx;
2522 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2523 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2526 fl->ifl_m_dequeued++;
2528 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2529 prefetch_pkts(fl, cidx);
2530 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2531 prefetch(&fl->ifl_sds.ifsd_map[next]);
2532 map = fl->ifl_sds.ifsd_map[cidx];
2533 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2535 /* not valid assert if bxe really does SGE from non-contiguous elements */
2536 MPASS(fl->ifl_cidx == cidx);
2537 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2539 bus_dmamap_unload(fl->ifl_buf_tag, map);
2540 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2541 if (__predict_false(fl->ifl_cidx == 0))
2543 bit_clear(fl->ifl_rx_bitmap, cidx);
2546 static struct mbuf *
2547 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2549 int i, padlen , flags;
2550 struct mbuf *m, *mh, *mt;
2556 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2558 MPASS(*sd->ifsd_cl != NULL);
2559 MPASS(*sd->ifsd_m != NULL);
2561 /* Don't include zero-length frags */
2562 if (ri->iri_frags[i].irf_len == 0) {
2563 /* XXX we can save the cluster here, but not the mbuf */
2564 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2565 m_free(*sd->ifsd_m);
2572 flags = M_PKTHDR|M_EXT;
2574 padlen = ri->iri_pad;
2579 /* assuming padding is only on the first fragment */
2583 *sd->ifsd_cl = NULL;
2585 /* Can these two be made one ? */
2586 m_init(m, M_NOWAIT, MT_DATA, flags);
2587 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2589 * These must follow m_init and m_cljset
2591 m->m_data += padlen;
2592 ri->iri_len -= padlen;
2593 m->m_len = ri->iri_frags[i].irf_len;
2594 } while (++i < ri->iri_nfrags);
2600 * Process one software descriptor
2602 static struct mbuf *
2603 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2608 /* should I merge this back in now that the two paths are basically duplicated? */
2609 if (ri->iri_nfrags == 1 &&
2610 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2611 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2614 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2615 #ifndef __NO_STRICT_ALIGNMENT
2619 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2620 m->m_len = ri->iri_frags[0].irf_len;
2622 m = assemble_segments(rxq, ri, &sd);
2624 m->m_pkthdr.len = ri->iri_len;
2625 m->m_pkthdr.rcvif = ri->iri_ifp;
2626 m->m_flags |= ri->iri_flags;
2627 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2628 m->m_pkthdr.flowid = ri->iri_flowid;
2629 M_HASHTYPE_SET(m, ri->iri_rsstype);
2630 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2631 m->m_pkthdr.csum_data = ri->iri_csum_data;
2635 #if defined(INET6) || defined(INET)
2637 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2639 CURVNET_SET(lc->ifp->if_vnet);
2641 *v6 = VNET(ip6_forwarding);
2644 *v4 = VNET(ipforwarding);
2650 * Returns true if it's possible this packet could be LROed.
2651 * if it returns false, it is guaranteed that tcp_lro_rx()
2652 * would not return zero.
2655 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2657 struct ether_header *eh;
2660 eh = mtod(m, struct ether_header *);
2661 eh_type = ntohs(eh->ether_type);
2664 case ETHERTYPE_IPV6:
2665 return !v6_forwarding;
2669 return !v4_forwarding;
2677 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2683 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2685 if_ctx_t ctx = rxq->ifr_ctx;
2686 if_shared_ctx_t sctx = ctx->ifc_sctx;
2687 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2690 struct if_rxd_info ri;
2691 int err, budget_left, rx_bytes, rx_pkts;
2695 bool v4_forwarding, v6_forwarding, lro_possible;
2698 * XXX early demux data packets so that if_input processing only handles
2699 * acks in interrupt context
2701 struct mbuf *m, *mh, *mt, *mf;
2703 lro_possible = v4_forwarding = v6_forwarding = false;
2707 rx_pkts = rx_bytes = 0;
2708 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2709 cidxp = &rxq->ifr_cq_cidx;
2711 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2712 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2713 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2714 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2715 DBG_COUNTER_INC(rx_unavail);
2719 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2720 if (__predict_false(!CTX_ACTIVE(ctx))) {
2721 DBG_COUNTER_INC(rx_ctx_inactive);
2725 * Reset client set fields to their default values
2728 ri.iri_qsidx = rxq->ifr_id;
2729 ri.iri_cidx = *cidxp;
2731 ri.iri_frags = rxq->ifr_frags;
2732 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2736 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2737 *cidxp = ri.iri_cidx;
2738 /* Update our consumer index */
2739 /* XXX NB: shurd - check if this is still safe */
2740 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2741 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2742 rxq->ifr_cq_gen = 0;
2744 /* was this only a completion queue message? */
2745 if (__predict_false(ri.iri_nfrags == 0))
2748 MPASS(ri.iri_nfrags != 0);
2749 MPASS(ri.iri_len != 0);
2751 /* will advance the cidx on the corresponding free lists */
2752 m = iflib_rxd_pkt_get(rxq, &ri);
2755 if (avail == 0 && budget_left)
2756 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2758 if (__predict_false(m == NULL)) {
2759 DBG_COUNTER_INC(rx_mbuf_null);
2762 /* imm_pkt: -- cxgb */
2770 /* make sure that we can refill faster than drain */
2771 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2772 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2774 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2776 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2778 while (mh != NULL) {
2781 m->m_nextpkt = NULL;
2782 #ifndef __NO_STRICT_ALIGNMENT
2783 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2786 rx_bytes += m->m_pkthdr.len;
2788 #if defined(INET6) || defined(INET)
2790 if (!lro_possible) {
2791 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2792 if (lro_possible && mf != NULL) {
2793 ifp->if_input(ifp, mf);
2794 DBG_COUNTER_INC(rx_if_input);
2798 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2799 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2800 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2806 ifp->if_input(ifp, m);
2807 DBG_COUNTER_INC(rx_if_input);
2818 ifp->if_input(ifp, mf);
2819 DBG_COUNTER_INC(rx_if_input);
2822 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2823 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2826 * Flush any outstanding LRO work
2828 #if defined(INET6) || defined(INET)
2829 tcp_lro_flush_all(&rxq->ifr_lc);
2833 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2836 ctx->ifc_flags |= IFC_DO_RESET;
2837 iflib_admin_intr_deferred(ctx);
2842 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2843 static inline qidx_t
2844 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2846 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2847 qidx_t minthresh = txq->ift_size / 8;
2848 if (in_use > 4*minthresh)
2849 return (notify_count);
2850 if (in_use > 2*minthresh)
2851 return (notify_count >> 1);
2852 if (in_use > minthresh)
2853 return (notify_count >> 3);
2857 static inline qidx_t
2858 txq_max_rs_deferred(iflib_txq_t txq)
2860 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2861 qidx_t minthresh = txq->ift_size / 8;
2862 if (txq->ift_in_use > 4*minthresh)
2863 return (notify_count);
2864 if (txq->ift_in_use > 2*minthresh)
2865 return (notify_count >> 1);
2866 if (txq->ift_in_use > minthresh)
2867 return (notify_count >> 2);
2871 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2872 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2874 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2875 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2876 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2878 /* forward compatibility for cxgb */
2879 #define FIRST_QSET(ctx) 0
2880 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2881 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2882 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2883 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2885 /* XXX we should be setting this to something other than zero */
2886 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2887 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2888 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2891 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2897 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2898 if (ring || txq->ift_db_pending >= max) {
2899 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2900 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2902 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2903 txq->ift_db_pending = txq->ift_npending = 0;
2911 print_pkt(if_pkt_info_t pi)
2913 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2914 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2915 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2916 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2917 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2918 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2922 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2923 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2924 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2925 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2928 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2930 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2931 struct ether_vlan_header *eh;
2935 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2936 M_WRITABLE(m) == 0) {
2937 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2941 DBG_COUNTER_INC(tx_frees);
2947 * Determine where frame payload starts.
2948 * Jump over vlan headers if already present,
2949 * helpful for QinQ too.
2951 if (__predict_false(m->m_len < sizeof(*eh))) {
2953 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2956 eh = mtod(m, struct ether_vlan_header *);
2957 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2958 pi->ipi_etype = ntohs(eh->evl_proto);
2959 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2961 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2962 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2965 switch (pi->ipi_etype) {
2970 struct ip *ip = NULL;
2971 struct tcphdr *th = NULL;
2974 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2975 if (__predict_false(m->m_len < minthlen)) {
2977 * if this code bloat is causing too much of a hit
2978 * move it to a separate function and mark it noinline
2980 if (m->m_len == pi->ipi_ehdrlen) {
2983 if (n->m_len >= sizeof(*ip)) {
2984 ip = (struct ip *)n->m_data;
2985 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2986 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2989 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2991 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2995 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2997 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2998 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2999 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3002 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3003 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3004 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3006 pi->ipi_ip_hlen = ip->ip_hl << 2;
3007 pi->ipi_ipproto = ip->ip_p;
3008 pi->ipi_flags |= IPI_TX_IPV4;
3010 /* TCP checksum offload may require TCP header length */
3011 if (IS_TX_OFFLOAD4(pi)) {
3012 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3013 if (__predict_false(th == NULL)) {
3015 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3017 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3019 pi->ipi_tcp_hflags = th->th_flags;
3020 pi->ipi_tcp_hlen = th->th_off << 2;
3021 pi->ipi_tcp_seq = th->th_seq;
3024 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3027 * TSO always requires hardware checksum offload.
3029 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3030 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3031 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3032 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3033 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3035 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3039 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3046 case ETHERTYPE_IPV6:
3048 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3050 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3052 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3054 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3057 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3059 /* XXX-BZ this will go badly in case of ext hdrs. */
3060 pi->ipi_ipproto = ip6->ip6_nxt;
3061 pi->ipi_flags |= IPI_TX_IPV6;
3063 /* TCP checksum offload may require TCP header length */
3064 if (IS_TX_OFFLOAD6(pi)) {
3065 if (pi->ipi_ipproto == IPPROTO_TCP) {
3066 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3068 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3071 pi->ipi_tcp_hflags = th->th_flags;
3072 pi->ipi_tcp_hlen = th->th_off << 2;
3073 pi->ipi_tcp_seq = th->th_seq;
3076 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3079 * TSO always requires hardware checksum offload.
3081 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3082 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3083 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3090 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3091 pi->ipi_ip_hlen = 0;
3100 * If dodgy hardware rejects the scatter gather chain we've handed it
3101 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3104 static __noinline struct mbuf *
3105 iflib_remove_mbuf(iflib_txq_t txq)
3108 struct mbuf *m, **ifsd_m;
3110 ifsd_m = txq->ift_sds.ifsd_m;
3111 ntxd = txq->ift_size;
3112 pidx = txq->ift_pidx & (ntxd - 1);
3113 ifsd_m = txq->ift_sds.ifsd_m;
3115 ifsd_m[pidx] = NULL;
3116 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3117 if (txq->ift_sds.ifsd_tso_map != NULL)
3118 bus_dmamap_unload(txq->ift_tso_buf_tag,
3119 txq->ift_sds.ifsd_tso_map[pidx]);
3121 txq->ift_dequeued++;
3126 static inline caddr_t
3127 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3131 caddr_t start, end, cur, next;
3133 ntxd = txq->ift_size;
3134 size = txq->ift_txd_size[qid];
3135 start = txq->ift_ifdi[qid].idi_vaddr;
3137 if (__predict_false(size == 0))
3139 cur = start + size*cidx;
3140 end = start + size*ntxd;
3141 next = CACHE_PTR_NEXT(cur);
3142 return (next < end ? next : start);
3146 * Pad an mbuf to ensure a minimum ethernet frame size.
3147 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3149 static __noinline int
3150 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3153 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3154 * and ARP message is the smallest common payload I can think of
3156 static char pad[18]; /* just zeros */
3158 struct mbuf *new_head;
3160 if (!M_WRITABLE(*m_head)) {
3161 new_head = m_dup(*m_head, M_NOWAIT);
3162 if (new_head == NULL) {
3164 device_printf(dev, "cannot pad short frame, m_dup() failed");
3165 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3166 DBG_COUNTER_INC(tx_frees);
3173 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3174 n > 0; n -= sizeof(pad))
3175 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3180 device_printf(dev, "cannot pad short frame\n");
3181 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3182 DBG_COUNTER_INC(tx_frees);
3190 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3193 if_shared_ctx_t sctx;
3194 if_softc_ctx_t scctx;
3195 bus_dma_tag_t buf_tag;
3196 bus_dma_segment_t *segs;
3197 struct mbuf *m_head, **ifsd_m;
3200 struct if_pkt_info pi;
3202 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3205 sctx = ctx->ifc_sctx;
3206 scctx = &ctx->ifc_softc_ctx;
3207 segs = txq->ift_segs;
3208 ntxd = txq->ift_size;
3213 * If we're doing TSO the next descriptor to clean may be quite far ahead
3215 cidx = txq->ift_cidx;
3216 pidx = txq->ift_pidx;
3217 if (ctx->ifc_flags & IFC_PREFETCH) {
3218 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3219 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3220 next_txd = calc_next_txd(txq, cidx, 0);
3224 /* prefetch the next cache line of mbuf pointers and flags */
3225 prefetch(&txq->ift_sds.ifsd_m[next]);
3226 prefetch(&txq->ift_sds.ifsd_map[next]);
3227 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3229 map = txq->ift_sds.ifsd_map[pidx];
3230 ifsd_m = txq->ift_sds.ifsd_m;
3232 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3233 buf_tag = txq->ift_tso_buf_tag;
3234 max_segs = scctx->isc_tx_tso_segments_max;
3235 map = txq->ift_sds.ifsd_tso_map[pidx];
3236 MPASS(buf_tag != NULL);
3237 MPASS(max_segs > 0);
3239 buf_tag = txq->ift_buf_tag;
3240 max_segs = scctx->isc_tx_nsegments;
3241 map = txq->ift_sds.ifsd_map[pidx];
3243 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3244 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3245 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3247 DBG_COUNTER_INC(encap_txd_encap_fail);
3254 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3256 pi.ipi_qsidx = txq->ift_id;
3257 pi.ipi_len = m_head->m_pkthdr.len;
3258 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3259 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3261 /* deliberate bitwise OR to make one condition */
3262 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3263 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3264 DBG_COUNTER_INC(encap_txd_encap_fail);
3271 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3274 if (__predict_false(err)) {
3277 /* try collapse once and defrag once */
3279 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3280 /* try defrag if collapsing fails */
3285 txq->ift_mbuf_defrag++;
3286 m_head = m_defrag(*m_headp, M_NOWAIT);
3289 if (__predict_false(m_head == NULL))
3295 txq->ift_no_tx_dma_setup++;
3298 txq->ift_no_tx_dma_setup++;
3300 DBG_COUNTER_INC(tx_frees);
3304 txq->ift_map_failed++;
3305 DBG_COUNTER_INC(encap_load_mbuf_fail);
3306 DBG_COUNTER_INC(encap_txd_encap_fail);
3309 ifsd_m[pidx] = m_head;
3311 * XXX assumes a 1 to 1 relationship between segments and
3312 * descriptors - this does not hold true on all drivers, e.g.
3315 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3316 txq->ift_no_desc_avail++;
3317 bus_dmamap_unload(buf_tag, map);
3318 DBG_COUNTER_INC(encap_txq_avail_fail);
3319 DBG_COUNTER_INC(encap_txd_encap_fail);
3320 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3321 GROUPTASK_ENQUEUE(&txq->ift_task);
3325 * On Intel cards we can greatly reduce the number of TX interrupts
3326 * we see by only setting report status on every Nth descriptor.
3327 * However, this also means that the driver will need to keep track
3328 * of the descriptors that RS was set on to check them for the DD bit.
3330 txq->ift_rs_pending += nsegs + 1;
3331 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3332 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3333 pi.ipi_flags |= IPI_TX_INTR;
3334 txq->ift_rs_pending = 0;
3338 pi.ipi_nsegs = nsegs;
3340 MPASS(pidx >= 0 && pidx < txq->ift_size);
3344 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3345 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3346 DBG_COUNTER_INC(tx_encap);
3347 MPASS(pi.ipi_new_pidx < txq->ift_size);
3349 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3350 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3351 ndesc += txq->ift_size;
3355 * drivers can need as many as
3358 MPASS(ndesc <= pi.ipi_nsegs + 2);
3359 MPASS(pi.ipi_new_pidx != pidx);
3361 txq->ift_in_use += ndesc;
3364 * We update the last software descriptor again here because there may
3365 * be a sentinel and/or there may be more mbufs than segments
3367 txq->ift_pidx = pi.ipi_new_pidx;
3368 txq->ift_npending += pi.ipi_ndescs;
3370 *m_headp = m_head = iflib_remove_mbuf(txq);
3372 txq->ift_txd_encap_efbig++;
3381 * err can't possibly be non-zero here, so we don't neet to test it
3382 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3387 txq->ift_mbuf_defrag_failed++;
3388 txq->ift_map_failed++;
3390 DBG_COUNTER_INC(tx_frees);
3392 DBG_COUNTER_INC(encap_txd_encap_fail);
3397 iflib_tx_desc_free(iflib_txq_t txq, int n)
3399 uint32_t qsize, cidx, mask, gen;
3400 struct mbuf *m, **ifsd_m;
3403 cidx = txq->ift_cidx;
3405 qsize = txq->ift_size;
3407 ifsd_m = txq->ift_sds.ifsd_m;
3408 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3412 prefetch(ifsd_m[(cidx + 3) & mask]);
3413 prefetch(ifsd_m[(cidx + 4) & mask]);
3415 if ((m = ifsd_m[cidx]) != NULL) {
3416 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3417 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3418 bus_dmamap_sync(txq->ift_tso_buf_tag,
3419 txq->ift_sds.ifsd_tso_map[cidx],
3420 BUS_DMASYNC_POSTWRITE);
3421 bus_dmamap_unload(txq->ift_tso_buf_tag,
3422 txq->ift_sds.ifsd_tso_map[cidx]);
3424 bus_dmamap_sync(txq->ift_buf_tag,
3425 txq->ift_sds.ifsd_map[cidx],
3426 BUS_DMASYNC_POSTWRITE);
3427 bus_dmamap_unload(txq->ift_buf_tag,
3428 txq->ift_sds.ifsd_map[cidx]);
3430 /* XXX we don't support any drivers that batch packets yet */
3431 MPASS(m->m_nextpkt == NULL);
3433 ifsd_m[cidx] = NULL;
3435 txq->ift_dequeued++;
3437 DBG_COUNTER_INC(tx_frees);
3439 if (__predict_false(++cidx == qsize)) {
3444 txq->ift_cidx = cidx;
3449 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3452 if_ctx_t ctx = txq->ift_ctx;
3454 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3455 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3458 * Need a rate-limiting check so that this isn't called every time
3460 iflib_tx_credits_update(ctx, txq);
3461 reclaim = DESC_RECLAIMABLE(txq);
3463 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3465 if (iflib_verbose_debug) {
3466 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3467 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3474 iflib_tx_desc_free(txq, reclaim);
3475 txq->ift_cleaned += reclaim;
3476 txq->ift_in_use -= reclaim;
3481 static struct mbuf **
3482 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3485 struct mbuf **items;
3488 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3489 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3491 prefetch(items[(cidx + offset) & (size-1)]);
3492 if (remaining > 1) {
3493 prefetch2cachelines(&items[next]);
3494 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3495 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3496 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3498 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3502 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3505 ifmp_ring_check_drainage(txq->ift_br, budget);
3509 iflib_txq_can_drain(struct ifmp_ring *r)
3511 iflib_txq_t txq = r->cookie;
3512 if_ctx_t ctx = txq->ift_ctx;
3514 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3516 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3517 BUS_DMASYNC_POSTREAD);
3518 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3523 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3525 iflib_txq_t txq = r->cookie;
3526 if_ctx_t ctx = txq->ift_ctx;
3527 struct ifnet *ifp = ctx->ifc_ifp;
3528 struct mbuf **mp, *m;
3529 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3530 int reclaimed, err, in_use_prev, desc_used;
3531 bool do_prefetch, ring, rang;
3533 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3534 !LINK_ACTIVE(ctx))) {
3535 DBG_COUNTER_INC(txq_drain_notready);
3538 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3539 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3540 avail = IDXDIFF(pidx, cidx, r->size);
3541 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3542 DBG_COUNTER_INC(txq_drain_flushing);
3543 for (i = 0; i < avail; i++) {
3544 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3545 m_free(r->items[(cidx + i) & (r->size-1)]);
3546 r->items[(cidx + i) & (r->size-1)] = NULL;
3551 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3552 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3554 callout_stop(&txq->ift_timer);
3555 CALLOUT_UNLOCK(txq);
3556 DBG_COUNTER_INC(txq_drain_oactive);
3560 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3561 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3562 count = MIN(avail, TX_BATCH_SIZE);
3564 if (iflib_verbose_debug)
3565 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3566 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3568 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3569 avail = TXQ_AVAIL(txq);
3571 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3572 int rem = do_prefetch ? count - i : 0;
3574 mp = _ring_peek_one(r, cidx, i, rem);
3575 MPASS(mp != NULL && *mp != NULL);
3576 if (__predict_false(*mp == (struct mbuf *)txq)) {
3581 in_use_prev = txq->ift_in_use;
3582 err = iflib_encap(txq, mp);
3583 if (__predict_false(err)) {
3584 /* no room - bail out */
3588 /* we can't send this packet - skip it */
3594 DBG_COUNTER_INC(tx_sent);
3595 bytes_sent += m->m_pkthdr.len;
3596 mcast_sent += !!(m->m_flags & M_MCAST);
3597 avail = TXQ_AVAIL(txq);
3599 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3600 desc_used += (txq->ift_in_use - in_use_prev);
3601 ETHER_BPF_MTAP(ifp, m);
3602 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3604 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3607 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3608 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3609 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3610 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3611 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3613 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3615 if (iflib_verbose_debug)
3616 printf("consumed=%d\n", consumed);
3622 iflib_txq_drain_always(struct ifmp_ring *r)
3628 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3636 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3638 callout_stop(&txq->ift_timer);
3639 CALLOUT_UNLOCK(txq);
3641 avail = IDXDIFF(pidx, cidx, r->size);
3642 for (i = 0; i < avail; i++) {
3643 mp = _ring_peek_one(r, cidx, i, avail - i);
3644 if (__predict_false(*mp == (struct mbuf *)txq))
3647 DBG_COUNTER_INC(tx_frees);
3649 MPASS(ifmp_ring_is_stalled(r) == 0);
3654 iflib_ifmp_purge(iflib_txq_t txq)
3656 struct ifmp_ring *r;
3659 r->drain = iflib_txq_drain_free;
3660 r->can_drain = iflib_txq_drain_always;
3662 ifmp_ring_check_drainage(r, r->size);
3664 r->drain = iflib_txq_drain;
3665 r->can_drain = iflib_txq_can_drain;
3669 _task_fn_tx(void *context)
3671 iflib_txq_t txq = context;
3672 if_ctx_t ctx = txq->ift_ctx;
3673 #if defined(ALTQ) || defined(DEV_NETMAP)
3674 if_t ifp = ctx->ifc_ifp;
3676 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3678 #ifdef IFLIB_DIAGNOSTICS
3679 txq->ift_cpu_exec_count[curcpu]++;
3681 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3684 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3685 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3686 BUS_DMASYNC_POSTREAD);
3687 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3688 netmap_tx_irq(ifp, txq->ift_id);
3689 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3694 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3695 iflib_altq_if_start(ifp);
3697 if (txq->ift_db_pending)
3698 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3700 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3702 * When abdicating, we always need to check drainage, not just when we don't enqueue
3705 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3706 if (ctx->ifc_flags & IFC_LEGACY)
3707 IFDI_INTR_ENABLE(ctx);
3712 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3713 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3718 _task_fn_rx(void *context)
3720 iflib_rxq_t rxq = context;
3721 if_ctx_t ctx = rxq->ifr_ctx;
3725 #ifdef IFLIB_DIAGNOSTICS
3726 rxq->ifr_cpu_exec_count[curcpu]++;
3728 DBG_COUNTER_INC(task_fn_rxs);
3729 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3733 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3735 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3740 budget = ctx->ifc_sysctl_rx_budget;
3742 budget = 16; /* XXX */
3743 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3744 if (ctx->ifc_flags & IFC_LEGACY)
3745 IFDI_INTR_ENABLE(ctx);
3750 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3751 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3752 DBG_COUNTER_INC(rx_intr_enables);
3755 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3758 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3762 _task_fn_admin(void *context)
3764 if_ctx_t ctx = context;
3765 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3768 bool oactive, running, do_reset, do_watchdog, in_detach;
3769 uint32_t reset_on = hz / 2;
3772 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3773 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3774 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3775 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3776 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3777 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3780 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3786 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3788 callout_stop(&txq->ift_timer);
3789 CALLOUT_UNLOCK(txq);
3792 ctx->ifc_watchdog_events++;
3793 IFDI_WATCHDOG_RESET(ctx);
3795 IFDI_UPDATE_ADMIN_STATUS(ctx);
3796 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3799 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3800 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3802 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3804 IFDI_LINK_INTR_ENABLE(ctx);
3806 iflib_if_init_locked(ctx);
3809 if (LINK_ACTIVE(ctx) == 0)
3811 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3812 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3817 _task_fn_iov(void *context)
3819 if_ctx_t ctx = context;
3821 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3822 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3826 IFDI_VFLR_HANDLE(ctx);
3831 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3834 if_int_delay_info_t info;
3837 info = (if_int_delay_info_t)arg1;
3838 ctx = info->iidi_ctx;
3839 info->iidi_req = req;
3840 info->iidi_oidp = oidp;
3842 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3847 /*********************************************************************
3851 **********************************************************************/
3854 iflib_if_init_locked(if_ctx_t ctx)
3857 iflib_init_locked(ctx);
3862 iflib_if_init(void *arg)
3867 iflib_if_init_locked(ctx);
3872 iflib_if_transmit(if_t ifp, struct mbuf *m)
3874 if_ctx_t ctx = if_getsoftc(ifp);
3878 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3880 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3881 DBG_COUNTER_INC(tx_frees);
3886 MPASS(m->m_nextpkt == NULL);
3887 /* ALTQ-enabled interfaces always use queue 0. */
3889 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3890 qidx = QIDX(ctx, m);
3892 * XXX calculate buf_ring based on flowid (divvy up bits?)
3894 txq = &ctx->ifc_txqs[qidx];
3896 #ifdef DRIVER_BACKPRESSURE
3897 if (txq->ift_closed) {
3899 next = m->m_nextpkt;
3900 m->m_nextpkt = NULL;
3902 DBG_COUNTER_INC(tx_frees);
3914 next = next->m_nextpkt;
3915 } while (next != NULL);
3917 if (count > nitems(marr))
3918 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3919 /* XXX check nextpkt */
3921 /* XXX simplify for now */
3922 DBG_COUNTER_INC(tx_frees);
3925 for (next = m, i = 0; next != NULL; i++) {
3927 next = next->m_nextpkt;
3928 mp[i]->m_nextpkt = NULL;
3931 DBG_COUNTER_INC(tx_seen);
3932 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3935 GROUPTASK_ENQUEUE(&txq->ift_task);
3938 GROUPTASK_ENQUEUE(&txq->ift_task);
3939 /* support forthcoming later */
3940 #ifdef DRIVER_BACKPRESSURE
3941 txq->ift_closed = TRUE;
3943 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3945 DBG_COUNTER_INC(tx_frees);
3953 * The overall approach to integrating iflib with ALTQ is to continue to use
3954 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
3955 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
3956 * is redundant/unnecessary, but doing so minimizes the amount of
3957 * ALTQ-specific code required in iflib. It is assumed that the overhead of
3958 * redundantly queueing to an intermediate mp_ring is swamped by the
3959 * performance limitations inherent in using ALTQ.
3961 * When ALTQ support is compiled in, all iflib drivers will use a transmit
3962 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
3963 * given interface. If ALTQ is enabled for an interface, then all
3964 * transmitted packets for that interface will be submitted to the ALTQ
3965 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
3966 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
3967 * update stats that the iflib machinery handles, and which is sensitve to
3968 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
3969 * will be installed as the start routine for use by ALTQ facilities that
3970 * need to trigger queue drains on a scheduled basis.
3974 iflib_altq_if_start(if_t ifp)
3976 struct ifaltq *ifq = &ifp->if_snd;
3980 IFQ_DEQUEUE_NOLOCK(ifq, m);
3982 iflib_if_transmit(ifp, m);
3983 IFQ_DEQUEUE_NOLOCK(ifq, m);
3989 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
3993 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
3994 IFQ_ENQUEUE(&ifp->if_snd, m, err);
3996 iflib_altq_if_start(ifp);
3998 err = iflib_if_transmit(ifp, m);
4005 iflib_if_qflush(if_t ifp)
4007 if_ctx_t ctx = if_getsoftc(ifp);
4008 iflib_txq_t txq = ctx->ifc_txqs;
4012 ctx->ifc_flags |= IFC_QFLUSH;
4014 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4015 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4016 iflib_txq_check_drain(txq, 0);
4018 ctx->ifc_flags &= ~IFC_QFLUSH;
4022 * When ALTQ is enabled, this will also take care of purging the
4029 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4030 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4031 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4032 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4035 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4037 if_ctx_t ctx = if_getsoftc(ifp);
4038 struct ifreq *ifr = (struct ifreq *)data;
4039 #if defined(INET) || defined(INET6)
4040 struct ifaddr *ifa = (struct ifaddr *)data;
4042 bool avoid_reset = FALSE;
4043 int err = 0, reinit = 0, bits;
4048 if (ifa->ifa_addr->sa_family == AF_INET)
4052 if (ifa->ifa_addr->sa_family == AF_INET6)
4056 ** Calling init results in link renegotiation,
4057 ** so we avoid doing it when possible.
4060 if_setflagbits(ifp, IFF_UP,0);
4061 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4064 if (!(if_getflags(ifp) & IFF_NOARP))
4065 arp_ifinit(ifp, ifa);
4068 err = ether_ioctl(ifp, command, data);
4072 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4076 bits = if_getdrvflags(ifp);
4077 /* stop the driver and free any clusters before proceeding */
4080 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4082 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4083 ctx->ifc_flags |= IFC_MULTISEG;
4085 ctx->ifc_flags &= ~IFC_MULTISEG;
4087 err = if_setmtu(ifp, ifr->ifr_mtu);
4089 iflib_init_locked(ctx);
4091 if_setdrvflags(ifp, bits);
4097 if (if_getflags(ifp) & IFF_UP) {
4098 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4099 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4100 (IFF_PROMISC | IFF_ALLMULTI)) {
4101 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4105 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4108 ctx->ifc_if_flags = if_getflags(ifp);
4113 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4115 IFDI_INTR_DISABLE(ctx);
4116 IFDI_MULTI_SET(ctx);
4117 IFDI_INTR_ENABLE(ctx);
4123 IFDI_MEDIA_SET(ctx);
4128 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4132 struct ifi2creq i2c;
4134 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4137 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4141 if (i2c.len > sizeof(i2c.data)) {
4146 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4147 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4153 int mask, setmask, oldmask;
4155 oldmask = if_getcapenable(ifp);
4156 mask = ifr->ifr_reqcap ^ oldmask;
4157 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4160 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4162 setmask |= (mask & IFCAP_FLAGS);
4163 setmask |= (mask & IFCAP_WOL);
4166 * If any RX csum has changed, change all the ones that
4167 * are supported by the driver.
4169 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4170 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4171 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4175 * want to ensure that traffic has stopped before we change any of the flags
4179 bits = if_getdrvflags(ifp);
4180 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4183 if_togglecapenable(ifp, setmask);
4185 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4186 iflib_init_locked(ctx);
4188 if_setdrvflags(ifp, bits);
4195 case SIOCGPRIVATE_0:
4199 err = IFDI_PRIV_IOCTL(ctx, command, data);
4203 err = ether_ioctl(ifp, command, data);
4212 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4214 if_ctx_t ctx = if_getsoftc(ifp);
4216 return (IFDI_GET_COUNTER(ctx, cnt));
4219 /*********************************************************************
4221 * OTHER FUNCTIONS EXPORTED TO THE STACK
4223 **********************************************************************/
4226 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4228 if_ctx_t ctx = if_getsoftc(ifp);
4230 if ((void *)ctx != arg)
4233 if ((vtag == 0) || (vtag > 4095))
4237 IFDI_VLAN_REGISTER(ctx, vtag);
4238 /* Re-init to load the changes */
4239 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4240 iflib_if_init_locked(ctx);
4245 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4247 if_ctx_t ctx = if_getsoftc(ifp);
4249 if ((void *)ctx != arg)
4252 if ((vtag == 0) || (vtag > 4095))
4256 IFDI_VLAN_UNREGISTER(ctx, vtag);
4257 /* Re-init to load the changes */
4258 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4259 iflib_if_init_locked(ctx);
4264 iflib_led_func(void *arg, int onoff)
4269 IFDI_LED_FUNC(ctx, onoff);
4273 /*********************************************************************
4275 * BUS FUNCTION DEFINITIONS
4277 **********************************************************************/
4280 iflib_device_probe(device_t dev)
4282 pci_vendor_info_t *ent;
4284 uint16_t pci_vendor_id, pci_device_id;
4285 uint16_t pci_subvendor_id, pci_subdevice_id;
4286 uint16_t pci_rev_id;
4287 if_shared_ctx_t sctx;
4289 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4292 pci_vendor_id = pci_get_vendor(dev);
4293 pci_device_id = pci_get_device(dev);
4294 pci_subvendor_id = pci_get_subvendor(dev);
4295 pci_subdevice_id = pci_get_subdevice(dev);
4296 pci_rev_id = pci_get_revid(dev);
4297 if (sctx->isc_parse_devinfo != NULL)
4298 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4300 ent = sctx->isc_vendor_info;
4301 while (ent->pvi_vendor_id != 0) {
4302 if (pci_vendor_id != ent->pvi_vendor_id) {
4306 if ((pci_device_id == ent->pvi_device_id) &&
4307 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4308 (ent->pvi_subvendor_id == 0)) &&
4309 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4310 (ent->pvi_subdevice_id == 0)) &&
4311 ((pci_rev_id == ent->pvi_rev_id) ||
4312 (ent->pvi_rev_id == 0))) {
4314 device_set_desc_copy(dev, ent->pvi_name);
4315 /* this needs to be changed to zero if the bus probing code
4316 * ever stops re-probing on best match because the sctx
4317 * may have its values over written by register calls
4318 * in subsequent probes
4320 return (BUS_PROBE_DEFAULT);
4328 iflib_reset_qvalues(if_ctx_t ctx)
4330 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4331 if_shared_ctx_t sctx = ctx->ifc_sctx;
4332 device_t dev = ctx->ifc_dev;
4335 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4336 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4338 * XXX sanity check that ntxd & nrxd are a power of 2
4340 if (ctx->ifc_sysctl_ntxqs != 0)
4341 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4342 if (ctx->ifc_sysctl_nrxqs != 0)
4343 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4345 for (i = 0; i < sctx->isc_ntxqs; i++) {
4346 if (ctx->ifc_sysctl_ntxds[i] != 0)
4347 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4349 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4352 for (i = 0; i < sctx->isc_nrxqs; i++) {
4353 if (ctx->ifc_sysctl_nrxds[i] != 0)
4354 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4356 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4359 for (i = 0; i < sctx->isc_nrxqs; i++) {
4360 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4361 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4362 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4363 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4365 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4366 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4367 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4368 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4372 for (i = 0; i < sctx->isc_ntxqs; i++) {
4373 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4374 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4375 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4376 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4378 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4379 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4380 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4381 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4387 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4392 if_softc_ctx_t scctx;
4398 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4401 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4402 device_set_softc(dev, ctx);
4403 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4406 ctx->ifc_sctx = sctx;
4408 ctx->ifc_softc = sc;
4410 if ((err = iflib_register(ctx)) != 0) {
4411 device_printf(dev, "iflib_register failed %d\n", err);
4414 iflib_add_device_sysctl_pre(ctx);
4416 scctx = &ctx->ifc_softc_ctx;
4419 iflib_reset_qvalues(ctx);
4421 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4422 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4425 _iflib_pre_assert(scctx);
4426 ctx->ifc_txrx = *scctx->isc_txrx;
4429 MPASS(scctx->isc_capabilities);
4430 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4431 MPASS(scctx->isc_tx_csum_flags);
4434 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4435 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4437 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4438 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4439 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4440 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4442 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4443 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4445 /* XXX change for per-queue sizes */
4446 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4447 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4448 for (i = 0; i < sctx->isc_nrxqs; i++) {
4449 if (!powerof2(scctx->isc_nrxd[i])) {
4450 /* round down instead? */
4451 device_printf(dev, "# rx descriptors must be a power of 2\n");
4453 goto fail_iflib_detach;
4456 for (i = 0; i < sctx->isc_ntxqs; i++) {
4457 if (!powerof2(scctx->isc_ntxd[i])) {
4459 "# tx descriptors must be a power of 2");
4461 goto fail_iflib_detach;
4465 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4466 MAX_SINGLE_PACKET_FRACTION)
4467 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4468 MAX_SINGLE_PACKET_FRACTION);
4469 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4470 MAX_SINGLE_PACKET_FRACTION)
4471 scctx->isc_tx_tso_segments_max = max(1,
4472 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4474 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4475 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4477 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4480 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4483 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4484 * into account. In the worst case, each of these calls will
4485 * add another mbuf and, thus, the requirement for another DMA
4486 * segment. So for best performance, it doesn't make sense to
4487 * advertize a maximum of TSO segments that typically will
4488 * require defragmentation in iflib_encap().
4490 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4491 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4493 if (scctx->isc_rss_table_size == 0)
4494 scctx->isc_rss_table_size = 64;
4495 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4497 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4498 /* XXX format name */
4499 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4500 NULL, NULL, "admin");
4502 /* Set up cpu set. If it fails, use the set of all CPUs. */
4503 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4504 device_printf(dev, "Unable to fetch CPU list\n");
4505 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4507 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4510 ** Now set up MSI or MSI-X, should return us the number of supported
4511 ** vectors (will be 1 for a legacy interrupt and MSI).
4513 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4514 msix = scctx->isc_vectors;
4515 } else if (scctx->isc_msix_bar != 0)
4517 * The simple fact that isc_msix_bar is not 0 does not mean we
4518 * we have a good value there that is known to work.
4520 msix = iflib_msix_init(ctx);
4522 scctx->isc_vectors = 1;
4523 scctx->isc_ntxqsets = 1;
4524 scctx->isc_nrxqsets = 1;
4525 scctx->isc_intr = IFLIB_INTR_LEGACY;
4528 /* Get memory for the station queues */
4529 if ((err = iflib_queues_alloc(ctx))) {
4530 device_printf(dev, "Unable to allocate queue memory\n");
4531 goto fail_intr_free;
4534 if ((err = iflib_qset_structures_setup(ctx)))
4538 * Group taskqueues aren't properly set up until SMP is started,
4539 * so we disable interrupts until we can handle them post
4542 * XXX: disabling interrupts doesn't actually work, at least for
4543 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4544 * we do null handling and depend on this not causing too large an
4547 IFDI_INTR_DISABLE(ctx);
4548 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4549 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4554 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4558 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4559 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4564 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4566 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4567 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4572 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4573 * This must appear after the call to ether_ifattach() because
4574 * ether_ifattach() sets if_hdrlen to the default value.
4576 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4577 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4579 if ((err = iflib_netmap_attach(ctx))) {
4580 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4585 NETDUMP_SET(ctx->ifc_ifp, iflib);
4587 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4588 iflib_add_device_sysctl_post(ctx);
4589 ctx->ifc_flags |= IFC_INIT_DONE;
4594 ether_ifdetach(ctx->ifc_ifp);
4596 iflib_free_intr_mem(ctx);
4598 iflib_tx_structures_free(ctx);
4599 iflib_rx_structures_free(ctx);
4605 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4606 free(ctx->ifc_softc, M_IFLIB);
4612 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4613 struct iflib_cloneattach_ctx *clctx)
4618 if_softc_ctx_t scctx;
4624 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4625 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4626 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4627 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4628 ctx->ifc_flags |= IFC_PSEUDO;
4630 ctx->ifc_sctx = sctx;
4631 ctx->ifc_softc = sc;
4634 if ((err = iflib_register(ctx)) != 0) {
4635 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4638 iflib_add_device_sysctl_pre(ctx);
4640 scctx = &ctx->ifc_softc_ctx;
4644 * XXX sanity check that ntxd & nrxd are a power of 2
4646 iflib_reset_qvalues(ctx);
4648 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4649 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4652 if (sctx->isc_flags & IFLIB_GEN_MAC)
4654 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4655 clctx->cc_params)) != 0) {
4656 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4659 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4660 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4661 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4664 MPASS(scctx->isc_capabilities);
4665 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4666 MPASS(scctx->isc_tx_csum_flags);
4669 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4670 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4672 ifp->if_flags |= IFF_NOGROUP;
4673 if (sctx->isc_flags & IFLIB_PSEUDO) {
4674 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4676 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4677 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4683 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4684 * This must appear after the call to ether_ifattach() because
4685 * ether_ifattach() sets if_hdrlen to the default value.
4687 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4688 if_setifheaderlen(ifp,
4689 sizeof(struct ether_vlan_header));
4691 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4692 iflib_add_device_sysctl_post(ctx);
4693 ctx->ifc_flags |= IFC_INIT_DONE;
4696 _iflib_pre_assert(scctx);
4697 ctx->ifc_txrx = *scctx->isc_txrx;
4699 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4700 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4701 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4702 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4704 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4705 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4707 /* XXX change for per-queue sizes */
4708 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n",
4709 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4710 for (i = 0; i < sctx->isc_nrxqs; i++) {
4711 if (!powerof2(scctx->isc_nrxd[i])) {
4712 /* round down instead? */
4713 device_printf(dev, "# rx descriptors must be a power of 2\n");
4715 goto fail_iflib_detach;
4718 for (i = 0; i < sctx->isc_ntxqs; i++) {
4719 if (!powerof2(scctx->isc_ntxd[i])) {
4721 "# tx descriptors must be a power of 2");
4723 goto fail_iflib_detach;
4727 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4728 MAX_SINGLE_PACKET_FRACTION)
4729 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4730 MAX_SINGLE_PACKET_FRACTION);
4731 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4732 MAX_SINGLE_PACKET_FRACTION)
4733 scctx->isc_tx_tso_segments_max = max(1,
4734 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4736 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4737 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4739 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4742 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4745 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4746 * into account. In the worst case, each of these calls will
4747 * add another mbuf and, thus, the requirement for another DMA
4748 * segment. So for best performance, it doesn't make sense to
4749 * advertize a maximum of TSO segments that typically will
4750 * require defragmentation in iflib_encap().
4752 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4753 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4755 if (scctx->isc_rss_table_size == 0)
4756 scctx->isc_rss_table_size = 64;
4757 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4759 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4760 /* XXX format name */
4761 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4762 NULL, NULL, "admin");
4764 /* XXX --- can support > 1 -- but keep it simple for now */
4765 scctx->isc_intr = IFLIB_INTR_LEGACY;
4767 /* Get memory for the station queues */
4768 if ((err = iflib_queues_alloc(ctx))) {
4769 device_printf(dev, "Unable to allocate queue memory\n");
4770 goto fail_iflib_detach;
4773 if ((err = iflib_qset_structures_setup(ctx))) {
4774 device_printf(dev, "qset structure setup failed %d\n", err);
4779 * XXX What if anything do we want to do about interrupts?
4781 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4782 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4783 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4788 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4789 * This must appear after the call to ether_ifattach() because
4790 * ether_ifattach() sets if_hdrlen to the default value.
4792 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4793 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4795 /* XXX handle more than one queue */
4796 for (i = 0; i < scctx->isc_nrxqsets; i++)
4797 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4801 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4802 iflib_add_device_sysctl_post(ctx);
4803 ctx->ifc_flags |= IFC_INIT_DONE;
4806 ether_ifdetach(ctx->ifc_ifp);
4808 iflib_tx_structures_free(ctx);
4809 iflib_rx_structures_free(ctx);
4813 free(ctx->ifc_softc, M_IFLIB);
4819 iflib_pseudo_deregister(if_ctx_t ctx)
4821 if_t ifp = ctx->ifc_ifp;
4825 struct taskqgroup *tqg;
4828 /* Unregister VLAN events */
4829 if (ctx->ifc_vlan_attach_event != NULL)
4830 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4831 if (ctx->ifc_vlan_detach_event != NULL)
4832 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4834 ether_ifdetach(ifp);
4835 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4836 CTX_LOCK_DESTROY(ctx);
4837 /* XXX drain any dependent tasks */
4838 tqg = qgroup_if_io_tqg;
4839 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4840 callout_drain(&txq->ift_timer);
4841 if (txq->ift_task.gt_uniq != NULL)
4842 taskqgroup_detach(tqg, &txq->ift_task);
4844 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4845 if (rxq->ifr_task.gt_uniq != NULL)
4846 taskqgroup_detach(tqg, &rxq->ifr_task);
4848 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4849 free(fl->ifl_rx_bitmap, M_IFLIB);
4851 tqg = qgroup_if_config_tqg;
4852 if (ctx->ifc_admin_task.gt_uniq != NULL)
4853 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4854 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4855 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4859 iflib_tx_structures_free(ctx);
4860 iflib_rx_structures_free(ctx);
4861 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4862 free(ctx->ifc_softc, M_IFLIB);
4868 iflib_device_attach(device_t dev)
4871 if_shared_ctx_t sctx;
4873 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4876 pci_enable_busmaster(dev);
4878 return (iflib_device_register(dev, NULL, sctx, &ctx));
4882 iflib_device_deregister(if_ctx_t ctx)
4884 if_t ifp = ctx->ifc_ifp;
4887 device_t dev = ctx->ifc_dev;
4889 struct taskqgroup *tqg;
4892 /* Make sure VLANS are not using driver */
4893 if (if_vlantrunkinuse(ifp)) {
4894 device_printf(dev, "Vlan in use, detach first\n");
4898 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
4899 device_printf(dev, "SR-IOV in use; detach first.\n");
4905 ctx->ifc_flags |= IFC_IN_DETACH;
4912 /* Unregister VLAN events */
4913 if (ctx->ifc_vlan_attach_event != NULL)
4914 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4915 if (ctx->ifc_vlan_detach_event != NULL)
4916 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4918 iflib_netmap_detach(ifp);
4919 ether_ifdetach(ifp);
4920 if (ctx->ifc_led_dev != NULL)
4921 led_destroy(ctx->ifc_led_dev);
4922 /* XXX drain any dependent tasks */
4923 tqg = qgroup_if_io_tqg;
4924 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4925 callout_drain(&txq->ift_timer);
4926 if (txq->ift_task.gt_uniq != NULL)
4927 taskqgroup_detach(tqg, &txq->ift_task);
4929 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4930 if (rxq->ifr_task.gt_uniq != NULL)
4931 taskqgroup_detach(tqg, &rxq->ifr_task);
4933 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4934 free(fl->ifl_rx_bitmap, M_IFLIB);
4936 tqg = qgroup_if_config_tqg;
4937 if (ctx->ifc_admin_task.gt_uniq != NULL)
4938 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4939 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4940 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4945 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4946 CTX_LOCK_DESTROY(ctx);
4947 device_set_softc(ctx->ifc_dev, NULL);
4948 iflib_free_intr_mem(ctx);
4950 bus_generic_detach(dev);
4953 iflib_tx_structures_free(ctx);
4954 iflib_rx_structures_free(ctx);
4955 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4956 free(ctx->ifc_softc, M_IFLIB);
4957 STATE_LOCK_DESTROY(ctx);
4963 iflib_free_intr_mem(if_ctx_t ctx)
4966 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
4967 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
4969 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
4970 pci_release_msi(ctx->ifc_dev);
4972 if (ctx->ifc_msix_mem != NULL) {
4973 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
4974 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
4975 ctx->ifc_msix_mem = NULL;
4980 iflib_device_detach(device_t dev)
4982 if_ctx_t ctx = device_get_softc(dev);
4984 return (iflib_device_deregister(ctx));
4988 iflib_device_suspend(device_t dev)
4990 if_ctx_t ctx = device_get_softc(dev);
4996 return bus_generic_suspend(dev);
4999 iflib_device_shutdown(device_t dev)
5001 if_ctx_t ctx = device_get_softc(dev);
5007 return bus_generic_suspend(dev);
5012 iflib_device_resume(device_t dev)
5014 if_ctx_t ctx = device_get_softc(dev);
5015 iflib_txq_t txq = ctx->ifc_txqs;
5019 iflib_if_init_locked(ctx);
5021 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5022 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5024 return (bus_generic_resume(dev));
5028 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5031 if_ctx_t ctx = device_get_softc(dev);
5034 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5041 iflib_device_iov_uninit(device_t dev)
5043 if_ctx_t ctx = device_get_softc(dev);
5046 IFDI_IOV_UNINIT(ctx);
5051 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5054 if_ctx_t ctx = device_get_softc(dev);
5057 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5063 /*********************************************************************
5065 * MODULE FUNCTION DEFINITIONS
5067 **********************************************************************/
5070 * - Start a fast taskqueue thread for each core
5071 * - Start a taskqueue for control operations
5074 iflib_module_init(void)
5080 iflib_module_event_handler(module_t mod, int what, void *arg)
5086 if ((err = iflib_module_init()) != 0)
5092 return (EOPNOTSUPP);
5098 /*********************************************************************
5100 * PUBLIC FUNCTION DEFINITIONS
5101 * ordered as in iflib.h
5103 **********************************************************************/
5107 _iflib_assert(if_shared_ctx_t sctx)
5109 MPASS(sctx->isc_tx_maxsize);
5110 MPASS(sctx->isc_tx_maxsegsize);
5112 MPASS(sctx->isc_rx_maxsize);
5113 MPASS(sctx->isc_rx_nsegments);
5114 MPASS(sctx->isc_rx_maxsegsize);
5116 MPASS(sctx->isc_nrxd_min[0]);
5117 MPASS(sctx->isc_nrxd_max[0]);
5118 MPASS(sctx->isc_nrxd_default[0]);
5119 MPASS(sctx->isc_ntxd_min[0]);
5120 MPASS(sctx->isc_ntxd_max[0]);
5121 MPASS(sctx->isc_ntxd_default[0]);
5125 _iflib_pre_assert(if_softc_ctx_t scctx)
5128 MPASS(scctx->isc_txrx->ift_txd_encap);
5129 MPASS(scctx->isc_txrx->ift_txd_flush);
5130 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5131 MPASS(scctx->isc_txrx->ift_rxd_available);
5132 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5133 MPASS(scctx->isc_txrx->ift_rxd_refill);
5134 MPASS(scctx->isc_txrx->ift_rxd_flush);
5138 iflib_register(if_ctx_t ctx)
5140 if_shared_ctx_t sctx = ctx->ifc_sctx;
5141 driver_t *driver = sctx->isc_driver;
5142 device_t dev = ctx->ifc_dev;
5145 _iflib_assert(sctx);
5148 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5149 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5151 device_printf(dev, "can not allocate ifnet structure\n");
5156 * Initialize our context's device specific methods
5158 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5159 kobj_class_compile((kobj_class_t) driver);
5162 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5163 if_setsoftc(ifp, ctx);
5164 if_setdev(ifp, dev);
5165 if_setinitfn(ifp, iflib_if_init);
5166 if_setioctlfn(ifp, iflib_if_ioctl);
5168 if_setstartfn(ifp, iflib_altq_if_start);
5169 if_settransmitfn(ifp, iflib_altq_if_transmit);
5170 if_setsendqready(ifp);
5172 if_settransmitfn(ifp, iflib_if_transmit);
5174 if_setqflushfn(ifp, iflib_if_qflush);
5175 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5177 ctx->ifc_vlan_attach_event =
5178 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5179 EVENTHANDLER_PRI_FIRST);
5180 ctx->ifc_vlan_detach_event =
5181 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5182 EVENTHANDLER_PRI_FIRST);
5184 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5185 iflib_media_change, iflib_media_status);
5192 iflib_queues_alloc(if_ctx_t ctx)
5194 if_shared_ctx_t sctx = ctx->ifc_sctx;
5195 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5196 device_t dev = ctx->ifc_dev;
5197 int nrxqsets = scctx->isc_nrxqsets;
5198 int ntxqsets = scctx->isc_ntxqsets;
5201 iflib_fl_t fl = NULL;
5202 int i, j, cpu, err, txconf, rxconf;
5203 iflib_dma_info_t ifdip;
5204 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5205 uint32_t *txqsizes = scctx->isc_txqsizes;
5206 uint8_t nrxqs = sctx->isc_nrxqs;
5207 uint8_t ntxqs = sctx->isc_ntxqs;
5208 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5212 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5213 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5215 /* Allocate the TX ring struct memory */
5216 if (!(ctx->ifc_txqs =
5217 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5218 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5219 device_printf(dev, "Unable to allocate TX ring memory\n");
5224 /* Now allocate the RX */
5225 if (!(ctx->ifc_rxqs =
5226 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5227 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5228 device_printf(dev, "Unable to allocate RX ring memory\n");
5233 txq = ctx->ifc_txqs;
5234 rxq = ctx->ifc_rxqs;
5237 * XXX handle allocation failure
5239 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5240 /* Set up some basics */
5242 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5243 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5245 "Unable to allocate TX DMA info memory\n");
5249 txq->ift_ifdi = ifdip;
5250 for (j = 0; j < ntxqs; j++, ifdip++) {
5251 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5253 "Unable to allocate TX descriptors\n");
5257 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5258 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5262 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5263 txq->ift_br_offset = 1;
5265 txq->ift_br_offset = 0;
5268 txq->ift_timer.c_cpu = cpu;
5270 if (iflib_txsd_alloc(txq)) {
5271 device_printf(dev, "Critical Failure setting up TX buffers\n");
5276 /* Initialize the TX lock */
5277 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5278 device_get_nameunit(dev), txq->ift_id);
5279 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5280 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5282 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5283 device_get_nameunit(dev), txq->ift_id);
5285 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5286 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5288 /* XXX free any allocated rings */
5289 device_printf(dev, "Unable to allocate buf_ring\n");
5294 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5295 /* Set up some basics */
5297 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5298 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5300 "Unable to allocate RX DMA info memory\n");
5305 rxq->ifr_ifdi = ifdip;
5306 /* XXX this needs to be changed if #rx queues != #tx queues */
5307 rxq->ifr_ntxqirq = 1;
5308 rxq->ifr_txqid[0] = i;
5309 for (j = 0; j < nrxqs; j++, ifdip++) {
5310 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5312 "Unable to allocate RX descriptors\n");
5316 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5320 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5321 rxq->ifr_fl_offset = 1;
5323 rxq->ifr_fl_offset = 0;
5325 rxq->ifr_nfl = nfree_lists;
5327 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5328 device_printf(dev, "Unable to allocate free list memory\n");
5333 for (j = 0; j < nfree_lists; j++) {
5334 fl[j].ifl_rxq = rxq;
5336 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5337 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5339 /* Allocate receive buffers for the ring */
5340 if (iflib_rxsd_alloc(rxq)) {
5342 "Critical Failure setting up receive buffers\n");
5347 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5348 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5353 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5354 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5355 for (i = 0; i < ntxqsets; i++) {
5356 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5358 for (j = 0; j < ntxqs; j++, di++) {
5359 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5360 paddrs[i*ntxqs + j] = di->idi_paddr;
5363 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5364 device_printf(ctx->ifc_dev,
5365 "Unable to allocate device TX queue\n");
5366 iflib_tx_structures_free(ctx);
5367 free(vaddrs, M_IFLIB);
5368 free(paddrs, M_IFLIB);
5371 free(vaddrs, M_IFLIB);
5372 free(paddrs, M_IFLIB);
5375 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5376 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5377 for (i = 0; i < nrxqsets; i++) {
5378 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5380 for (j = 0; j < nrxqs; j++, di++) {
5381 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5382 paddrs[i*nrxqs + j] = di->idi_paddr;
5385 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5386 device_printf(ctx->ifc_dev,
5387 "Unable to allocate device RX queue\n");
5388 iflib_tx_structures_free(ctx);
5389 free(vaddrs, M_IFLIB);
5390 free(paddrs, M_IFLIB);
5393 free(vaddrs, M_IFLIB);
5394 free(paddrs, M_IFLIB);
5398 /* XXX handle allocation failure changes */
5402 if (ctx->ifc_rxqs != NULL)
5403 free(ctx->ifc_rxqs, M_IFLIB);
5404 ctx->ifc_rxqs = NULL;
5405 if (ctx->ifc_txqs != NULL)
5406 free(ctx->ifc_txqs, M_IFLIB);
5407 ctx->ifc_txqs = NULL;
5413 iflib_tx_structures_setup(if_ctx_t ctx)
5415 iflib_txq_t txq = ctx->ifc_txqs;
5418 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5419 iflib_txq_setup(txq);
5425 iflib_tx_structures_free(if_ctx_t ctx)
5427 iflib_txq_t txq = ctx->ifc_txqs;
5428 if_shared_ctx_t sctx = ctx->ifc_sctx;
5431 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5432 iflib_txq_destroy(txq);
5433 for (j = 0; j < sctx->isc_ntxqs; j++)
5434 iflib_dma_free(&txq->ift_ifdi[j]);
5436 free(ctx->ifc_txqs, M_IFLIB);
5437 ctx->ifc_txqs = NULL;
5438 IFDI_QUEUES_FREE(ctx);
5441 /*********************************************************************
5443 * Initialize all receive rings.
5445 **********************************************************************/
5447 iflib_rx_structures_setup(if_ctx_t ctx)
5449 iflib_rxq_t rxq = ctx->ifc_rxqs;
5451 #if defined(INET6) || defined(INET)
5455 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5456 #if defined(INET6) || defined(INET)
5457 tcp_lro_free(&rxq->ifr_lc);
5458 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5459 TCP_LRO_ENTRIES, min(1024,
5460 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5461 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5464 rxq->ifr_lro_enabled = TRUE;
5466 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5469 #if defined(INET6) || defined(INET)
5472 * Free RX software descriptors allocated so far, we will only handle
5473 * the rings that completed, the failing case will have
5474 * cleaned up for itself. 'q' failed, so its the terminus.
5476 rxq = ctx->ifc_rxqs;
5477 for (i = 0; i < q; ++i, rxq++) {
5478 iflib_rx_sds_free(rxq);
5479 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5485 /*********************************************************************
5487 * Free all receive rings.
5489 **********************************************************************/
5491 iflib_rx_structures_free(if_ctx_t ctx)
5493 iflib_rxq_t rxq = ctx->ifc_rxqs;
5495 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5496 iflib_rx_sds_free(rxq);
5498 free(ctx->ifc_rxqs, M_IFLIB);
5499 ctx->ifc_rxqs = NULL;
5503 iflib_qset_structures_setup(if_ctx_t ctx)
5508 * It is expected that the caller takes care of freeing queues if this
5511 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5512 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5516 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5517 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5523 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5524 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5527 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5532 find_nth(if_ctx_t ctx, int qid)
5535 int i, cpuid, eqid, count;
5537 CPU_COPY(&ctx->ifc_cpus, &cpus);
5538 count = CPU_COUNT(&cpus);
5540 /* clear up to the qid'th bit */
5541 for (i = 0; i < eqid; i++) {
5542 cpuid = CPU_FFS(&cpus);
5544 CPU_CLR(cpuid-1, &cpus);
5546 cpuid = CPU_FFS(&cpus);
5552 extern struct cpu_group *cpu_top; /* CPU topology */
5555 find_child_with_core(int cpu, struct cpu_group *grp)
5559 if (grp->cg_children == 0)
5562 MPASS(grp->cg_child);
5563 for (i = 0; i < grp->cg_children; i++) {
5564 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5572 * Find the nth "close" core to the specified core
5573 * "close" is defined as the deepest level that shares
5574 * at least an L2 cache. With threads, this will be
5575 * threads on the same core. If the sahred cache is L3
5576 * or higher, simply returns the same core.
5579 find_close_core(int cpu, int core_offset)
5581 struct cpu_group *grp;
5590 while ((i = find_child_with_core(cpu, grp)) != -1) {
5591 /* If the child only has one cpu, don't descend */
5592 if (grp->cg_child[i].cg_count <= 1)
5594 grp = &grp->cg_child[i];
5597 /* If they don't share at least an L2 cache, use the same CPU */
5598 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5602 CPU_COPY(&grp->cg_mask, &cs);
5604 /* Add the selected CPU offset to core offset. */
5605 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5606 if (fcpu - 1 == cpu)
5608 CPU_CLR(fcpu - 1, &cs);
5614 CPU_COPY(&grp->cg_mask, &cs);
5615 for (i = core_offset % grp->cg_count; i > 0; i--) {
5616 MPASS(CPU_FFS(&cs));
5617 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5619 MPASS(CPU_FFS(&cs));
5620 return CPU_FFS(&cs) - 1;
5624 find_close_core(int cpu, int core_offset __unused)
5631 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5635 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5636 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5637 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5639 case IFLIB_INTR_RXTX:
5640 /* RX queues get the specified core */
5641 return qid / CPU_COUNT(&ctx->ifc_cpus);
5647 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5648 #define find_close_core(cpuid, tid) CPU_FIRST()
5649 #define find_nth(ctx, gid) CPU_FIRST()
5652 /* Just to avoid copy/paste */
5654 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5655 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5659 int err, cpuid, tid;
5662 cpuid = find_nth(ctx, qid);
5663 tid = get_core_offset(ctx, type, qid);
5665 cpuid = find_close_core(cpuid, tid);
5666 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5669 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5673 if (cpuid > ctx->ifc_cpuid_highest)
5674 ctx->ifc_cpuid_highest = cpuid;
5680 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5681 iflib_intr_type_t type, driver_filter_t *filter,
5682 void *filter_arg, int qid, const char *name)
5685 struct grouptask *gtask;
5686 struct taskqgroup *tqg;
5687 iflib_filter_info_t info;
5690 driver_filter_t *intr_fast;
5693 info = &ctx->ifc_filter_info;
5697 /* XXX merge tx/rx for netmap? */
5699 q = &ctx->ifc_txqs[qid];
5700 info = &ctx->ifc_txqs[qid].ift_filter_info;
5701 gtask = &ctx->ifc_txqs[qid].ift_task;
5702 tqg = qgroup_if_io_tqg;
5704 intr_fast = iflib_fast_intr;
5705 GROUPTASK_INIT(gtask, 0, fn, q);
5706 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5709 q = &ctx->ifc_rxqs[qid];
5710 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5711 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5712 tqg = qgroup_if_io_tqg;
5714 intr_fast = iflib_fast_intr;
5715 GROUPTASK_INIT(gtask, 0, fn, q);
5717 case IFLIB_INTR_RXTX:
5718 q = &ctx->ifc_rxqs[qid];
5719 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5720 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5721 tqg = qgroup_if_io_tqg;
5723 intr_fast = iflib_fast_intr_rxtx;
5724 GROUPTASK_INIT(gtask, 0, fn, q);
5726 case IFLIB_INTR_ADMIN:
5729 info = &ctx->ifc_filter_info;
5730 gtask = &ctx->ifc_admin_task;
5731 tqg = qgroup_if_config_tqg;
5732 fn = _task_fn_admin;
5733 intr_fast = iflib_fast_intr_ctx;
5736 panic("unknown net intr type");
5739 info->ifi_filter = filter;
5740 info->ifi_filter_arg = filter_arg;
5741 info->ifi_task = gtask;
5745 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5747 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5750 if (type == IFLIB_INTR_ADMIN)
5754 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5759 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
5766 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5768 struct grouptask *gtask;
5769 struct taskqgroup *tqg;
5776 q = &ctx->ifc_txqs[qid];
5777 gtask = &ctx->ifc_txqs[qid].ift_task;
5778 tqg = qgroup_if_io_tqg;
5782 q = &ctx->ifc_rxqs[qid];
5783 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5784 tqg = qgroup_if_io_tqg;
5787 case IFLIB_INTR_IOV:
5789 gtask = &ctx->ifc_vflr_task;
5790 tqg = qgroup_if_config_tqg;
5794 panic("unknown net intr type");
5796 GROUPTASK_INIT(gtask, 0, fn, q);
5798 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5801 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
5804 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
5809 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5813 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5816 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
5817 rman_get_rid(irq->ii_res), irq->ii_res);
5821 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5823 iflib_txq_t txq = ctx->ifc_txqs;
5824 iflib_rxq_t rxq = ctx->ifc_rxqs;
5825 if_irq_t irq = &ctx->ifc_legacy_irq;
5826 iflib_filter_info_t info;
5828 struct grouptask *gtask;
5829 struct resource *res;
5830 struct taskqgroup *tqg;
5836 q = &ctx->ifc_rxqs[0];
5837 info = &rxq[0].ifr_filter_info;
5838 gtask = &rxq[0].ifr_task;
5839 tqg = qgroup_if_io_tqg;
5840 tqrid = irq->ii_rid = *rid;
5843 ctx->ifc_flags |= IFC_LEGACY;
5844 info->ifi_filter = filter;
5845 info->ifi_filter_arg = filter_arg;
5846 info->ifi_task = gtask;
5847 info->ifi_ctx = ctx;
5850 /* We allocate a single interrupt resource */
5851 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5853 GROUPTASK_INIT(gtask, 0, fn, q);
5855 taskqgroup_attach(tqg, gtask, q, dev, res, name);
5857 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5858 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
5864 iflib_led_create(if_ctx_t ctx)
5867 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5868 device_get_nameunit(ctx->ifc_dev));
5872 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5875 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5879 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5882 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5886 iflib_admin_intr_deferred(if_ctx_t ctx)
5889 struct grouptask *gtask;
5891 gtask = &ctx->ifc_admin_task;
5892 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5895 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5899 iflib_iov_intr_deferred(if_ctx_t ctx)
5902 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5906 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5909 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
5914 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
5918 GROUPTASK_INIT(gtask, 0, fn, ctx);
5919 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
5924 iflib_config_gtask_deinit(struct grouptask *gtask)
5927 taskqgroup_detach(qgroup_if_config_tqg, gtask);
5931 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
5933 if_t ifp = ctx->ifc_ifp;
5934 iflib_txq_t txq = ctx->ifc_txqs;
5936 if_setbaudrate(ifp, baudrate);
5937 if (baudrate >= IF_Gbps(10)) {
5939 ctx->ifc_flags |= IFC_PREFETCH;
5942 /* If link down, disable watchdog */
5943 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
5944 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
5945 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
5947 ctx->ifc_link_state = link_state;
5948 if_link_state_change(ifp, link_state);
5952 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
5956 int credits_pre = txq->ift_cidx_processed;
5959 if (ctx->isc_txd_credits_update == NULL)
5962 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
5963 BUS_DMASYNC_POSTREAD);
5964 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
5967 txq->ift_processed += credits;
5968 txq->ift_cidx_processed += credits;
5970 MPASS(credits_pre + credits == txq->ift_cidx_processed);
5971 if (txq->ift_cidx_processed >= txq->ift_size)
5972 txq->ift_cidx_processed -= txq->ift_size;
5977 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
5982 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
5983 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
5984 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
5985 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
5990 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
5991 const char *description, if_int_delay_info_t info,
5992 int offset, int value)
5994 info->iidi_ctx = ctx;
5995 info->iidi_offset = offset;
5996 info->iidi_value = value;
5997 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
5998 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
5999 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6000 info, 0, iflib_sysctl_int_delay, "I", description);
6004 iflib_ctx_lock_get(if_ctx_t ctx)
6007 return (&ctx->ifc_ctx_sx);
6011 iflib_msix_init(if_ctx_t ctx)
6013 device_t dev = ctx->ifc_dev;
6014 if_shared_ctx_t sctx = ctx->ifc_sctx;
6015 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6016 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
6017 int iflib_num_tx_queues, iflib_num_rx_queues;
6018 int err, admincnt, bar;
6020 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6021 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6024 device_printf(dev, "msix_init qsets capped at %d\n",
6025 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6027 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6028 admincnt = sctx->isc_admin_intrcnt;
6029 /* Override by tuneable */
6030 if (scctx->isc_disable_msix)
6033 /* First try MSI-X */
6034 if ((msgs = pci_msix_count(dev)) == 0) {
6036 device_printf(dev, "MSI-X not supported or disabled\n");
6040 * bar == -1 => "trust me I know what I'm doing"
6041 * Some drivers are for hardware that is so shoddily
6042 * documented that no one knows which bars are which
6043 * so the developer has to map all bars. This hack
6044 * allows shoddy garbage to use MSI-X in this framework.
6047 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6048 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6049 if (ctx->ifc_msix_mem == NULL) {
6050 device_printf(dev, "Unable to map MSI-X table\n");
6055 /* use only 1 qset in debug mode */
6056 queuemsgs = min(msgs - admincnt, 1);
6058 queuemsgs = msgs - admincnt;
6061 queues = imin(queuemsgs, rss_getnumbuckets());
6065 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6068 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6069 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6071 /* If we're doing RSS, clamp at the number of RSS buckets */
6072 if (queues > rss_getnumbuckets())
6073 queues = rss_getnumbuckets();
6075 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6076 rx_queues = iflib_num_rx_queues;
6080 if (rx_queues > scctx->isc_nrxqsets)
6081 rx_queues = scctx->isc_nrxqsets;
6084 * We want this to be all logical CPUs by default
6086 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6087 tx_queues = iflib_num_tx_queues;
6089 tx_queues = mp_ncpus;
6091 if (tx_queues > scctx->isc_ntxqsets)
6092 tx_queues = scctx->isc_ntxqsets;
6094 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6096 if (tx_queues != rx_queues)
6098 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6099 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6101 tx_queues = min(rx_queues, tx_queues);
6102 rx_queues = min(rx_queues, tx_queues);
6105 device_printf(dev, "Using %d rx queues %d tx queues\n",
6106 rx_queues, tx_queues);
6108 vectors = rx_queues + admincnt;
6109 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6110 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6112 scctx->isc_vectors = vectors;
6113 scctx->isc_nrxqsets = rx_queues;
6114 scctx->isc_ntxqsets = tx_queues;
6115 scctx->isc_intr = IFLIB_INTR_MSIX;
6120 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n",
6122 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6124 ctx->ifc_msix_mem = NULL;
6127 vectors = pci_msi_count(dev);
6128 scctx->isc_nrxqsets = 1;
6129 scctx->isc_ntxqsets = 1;
6130 scctx->isc_vectors = vectors;
6131 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6132 device_printf(dev,"Using an MSI interrupt\n");
6133 scctx->isc_intr = IFLIB_INTR_MSI;
6135 scctx->isc_vectors = 1;
6136 device_printf(dev,"Using a Legacy interrupt\n");
6137 scctx->isc_intr = IFLIB_INTR_LEGACY;
6143 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6146 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6149 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6151 const char *ring_state = "UNKNOWN";
6154 rc = sysctl_wire_old_buffer(req, 0);
6158 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6163 ring_state = ring_states[state[3]];
6165 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6166 state[0], state[1], state[2], ring_state);
6167 rc = sbuf_finish(sb);
6172 enum iflib_ndesc_handler {
6178 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6180 if_ctx_t ctx = (void *)arg1;
6181 enum iflib_ndesc_handler type = arg2;
6182 char buf[256] = {0};
6187 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6191 case IFLIB_NTXD_HANDLER:
6192 ndesc = ctx->ifc_sysctl_ntxds;
6194 nqs = ctx->ifc_sctx->isc_ntxqs;
6196 case IFLIB_NRXD_HANDLER:
6197 ndesc = ctx->ifc_sysctl_nrxds;
6199 nqs = ctx->ifc_sctx->isc_nrxqs;
6202 panic("unhandled type");
6207 for (i=0; i<8; i++) {
6212 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6215 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6216 if (rc || req->newptr == NULL)
6219 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6220 i++, p = strsep(&next, " ,")) {
6221 ndesc[i] = strtoul(p, NULL, 10);
6227 #define NAME_BUFLEN 32
6229 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6231 device_t dev = iflib_get_dev(ctx);
6232 struct sysctl_oid_list *child, *oid_list;
6233 struct sysctl_ctx_list *ctx_list;
6234 struct sysctl_oid *node;
6236 ctx_list = device_get_sysctl_ctx(dev);
6237 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6238 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6239 CTLFLAG_RD, NULL, "IFLIB fields");
6240 oid_list = SYSCTL_CHILDREN(node);
6242 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6243 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6246 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6247 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6248 "# of txqs to use, 0 => use default #");
6249 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6250 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6251 "# of rxqs to use, 0 => use default #");
6252 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6253 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6254 "permit #txq != #rxq");
6255 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6256 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6257 "disable MSI-X (default 0)");
6258 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6259 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6260 "set the rx budget");
6261 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6262 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6263 "cause tx to abdicate instead of running to completion");
6265 /* XXX change for per-queue sizes */
6266 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6267 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6268 mp_ndesc_handler, "A",
6269 "list of # of tx descriptors to use, 0 = use default #");
6270 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6271 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6272 mp_ndesc_handler, "A",
6273 "list of # of rx descriptors to use, 0 = use default #");
6277 iflib_add_device_sysctl_post(if_ctx_t ctx)
6279 if_shared_ctx_t sctx = ctx->ifc_sctx;
6280 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6281 device_t dev = iflib_get_dev(ctx);
6282 struct sysctl_oid_list *child;
6283 struct sysctl_ctx_list *ctx_list;
6288 char namebuf[NAME_BUFLEN];
6290 struct sysctl_oid *queue_node, *fl_node, *node;
6291 struct sysctl_oid_list *queue_list, *fl_list;
6292 ctx_list = device_get_sysctl_ctx(dev);
6294 node = ctx->ifc_sysctl_node;
6295 child = SYSCTL_CHILDREN(node);
6297 if (scctx->isc_ntxqsets > 100)
6299 else if (scctx->isc_ntxqsets > 10)
6303 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6304 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6305 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6306 CTLFLAG_RD, NULL, "Queue Name");
6307 queue_list = SYSCTL_CHILDREN(queue_node);
6309 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6311 &txq->ift_dequeued, "total mbufs freed");
6312 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6314 &txq->ift_enqueued, "total mbufs enqueued");
6316 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6318 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6319 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6321 &txq->ift_pullups, "# of times m_pullup was called");
6322 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6324 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6325 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6327 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6328 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6330 &txq->ift_map_failed, "# of times dma map failed");
6331 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6333 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6334 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6336 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6337 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6339 &txq->ift_pidx, 1, "Producer Index");
6340 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6342 &txq->ift_cidx, 1, "Consumer Index");
6343 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6345 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6346 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6348 &txq->ift_in_use, 1, "descriptors in use");
6349 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6351 &txq->ift_processed, "descriptors procesed for clean");
6352 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6354 &txq->ift_cleaned, "total cleaned");
6355 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6356 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6357 0, mp_ring_state_handler, "A", "soft ring state");
6358 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6359 CTLFLAG_RD, &txq->ift_br->enqueues,
6360 "# of enqueues to the mp_ring for this queue");
6361 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6362 CTLFLAG_RD, &txq->ift_br->drops,
6363 "# of drops in the mp_ring for this queue");
6364 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6365 CTLFLAG_RD, &txq->ift_br->starts,
6366 "# of normal consumer starts in the mp_ring for this queue");
6367 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6368 CTLFLAG_RD, &txq->ift_br->stalls,
6369 "# of consumer stalls in the mp_ring for this queue");
6370 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6371 CTLFLAG_RD, &txq->ift_br->restarts,
6372 "# of consumer restarts in the mp_ring for this queue");
6373 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6374 CTLFLAG_RD, &txq->ift_br->abdications,
6375 "# of consumer abdications in the mp_ring for this queue");
6378 if (scctx->isc_nrxqsets > 100)
6380 else if (scctx->isc_nrxqsets > 10)
6384 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6385 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6386 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6387 CTLFLAG_RD, NULL, "Queue Name");
6388 queue_list = SYSCTL_CHILDREN(queue_node);
6389 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6390 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6392 &rxq->ifr_cq_pidx, 1, "Producer Index");
6393 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6395 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6398 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6399 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6400 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6401 CTLFLAG_RD, NULL, "freelist Name");
6402 fl_list = SYSCTL_CHILDREN(fl_node);
6403 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6405 &fl->ifl_pidx, 1, "Producer Index");
6406 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6408 &fl->ifl_cidx, 1, "Consumer Index");
6409 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6411 &fl->ifl_credits, 1, "credits available");
6413 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6415 &fl->ifl_m_enqueued, "mbufs allocated");
6416 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6418 &fl->ifl_m_dequeued, "mbufs freed");
6419 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6421 &fl->ifl_cl_enqueued, "clusters allocated");
6422 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6424 &fl->ifl_cl_dequeued, "clusters freed");
6433 iflib_request_reset(if_ctx_t ctx)
6437 ctx->ifc_flags |= IFC_DO_RESET;
6441 #ifndef __NO_STRICT_ALIGNMENT
6442 static struct mbuf *
6443 iflib_fixup_rx(struct mbuf *m)
6447 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6448 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6449 m->m_data += ETHER_HDR_LEN;
6452 MGETHDR(n, M_NOWAIT, MT_DATA);
6457 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6458 m->m_data += ETHER_HDR_LEN;
6459 m->m_len -= ETHER_HDR_LEN;
6460 n->m_len = ETHER_HDR_LEN;
6461 M_MOVE_PKTHDR(n, m);
6470 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6474 ctx = if_getsoftc(ifp);
6476 *nrxr = NRXQSETS(ctx);
6477 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6478 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6483 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6486 if_softc_ctx_t scctx;
6491 ctx = if_getsoftc(ifp);
6492 scctx = &ctx->ifc_softc_ctx;
6496 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6497 rxq = &ctx->ifc_rxqs[i];
6498 for (j = 0; j < rxq->ifr_nfl; j++) {
6500 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6503 iflib_no_tx_batch = 1;
6511 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6517 ctx = if_getsoftc(ifp);
6518 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6522 txq = &ctx->ifc_txqs[0];
6523 error = iflib_encap(txq, &m);
6525 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6530 iflib_netdump_poll(struct ifnet *ifp, int count)
6533 if_softc_ctx_t scctx;
6537 ctx = if_getsoftc(ifp);
6538 scctx = &ctx->ifc_softc_ctx;
6540 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6544 txq = &ctx->ifc_txqs[0];
6545 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6547 for (i = 0; i < scctx->isc_nrxqsets; i++)
6548 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6551 #endif /* NETDUMP */