2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_private.h>
58 #include <net/if_types.h>
59 #include <net/if_media.h>
61 #include <net/ethernet.h>
62 #include <net/mp_ring.h>
63 #include <net/debugnet.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet6/ip6_var.h>
78 #include <machine/bus.h>
79 #include <machine/in_cksum.h>
84 #include <dev/led/led.h>
85 #include <dev/pci/pcireg.h>
86 #include <dev/pci/pcivar.h>
87 #include <dev/pci/pci_private.h>
89 #include <net/iflib.h>
90 #include <net/iflib_private.h>
95 #include <dev/pci/pci_iov.h>
98 #include <sys/bitstring.h>
100 * enable accounting of every mbuf as it comes in to and goes out of
101 * iflib's software descriptor references
103 #define MEMORY_LOGGING 0
105 * Enable mbuf vectors for compressing long mbuf chains
110 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
111 * we prefetch needs to be determined by the time spent in m_free vis a vis
112 * the cost of a prefetch. This will of course vary based on the workload:
113 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
114 * is quite expensive, thus suggesting very little prefetch.
115 * - small packet forwarding which is just returning a single mbuf to
116 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
146 static void iflib_tqg_detach(if_ctx_t ctx);
148 typedef struct iflib_filter_info {
149 driver_filter_t *ifi_filter;
150 void *ifi_filter_arg;
151 struct grouptask *ifi_task;
153 } *iflib_filter_info_t;
158 * Pointer to hardware driver's softc
165 if_shared_ctx_t ifc_sctx;
166 struct if_softc_ctx ifc_softc_ctx;
168 struct sx ifc_ctx_sx;
169 struct mtx ifc_state_mtx;
171 iflib_txq_t ifc_txqs;
172 iflib_rxq_t ifc_rxqs;
173 uint32_t ifc_if_flags;
175 uint32_t ifc_max_fl_buf_size;
176 uint32_t ifc_rx_mbuf_sz;
179 int ifc_watchdog_events;
180 struct cdev *ifc_led_dev;
181 struct resource *ifc_msix_mem;
183 struct if_irq ifc_legacy_irq;
184 struct grouptask ifc_admin_task;
185 struct grouptask ifc_vflr_task;
186 struct iflib_filter_info ifc_filter_info;
187 struct ifmedia ifc_media;
188 struct ifmedia *ifc_mediap;
190 struct sysctl_oid *ifc_sysctl_node;
191 uint16_t ifc_sysctl_ntxqs;
192 uint16_t ifc_sysctl_nrxqs;
193 uint16_t ifc_sysctl_qs_eq_override;
194 uint16_t ifc_sysctl_rx_budget;
195 uint16_t ifc_sysctl_tx_abdicate;
196 uint16_t ifc_sysctl_core_offset;
197 #define CORE_OFFSET_UNSPECIFIED 0xffff
198 uint8_t ifc_sysctl_separate_txrx;
199 uint8_t ifc_sysctl_use_logical_cores;
200 bool ifc_cpus_are_physical_cores;
202 qidx_t ifc_sysctl_ntxds[8];
203 qidx_t ifc_sysctl_nrxds[8];
204 struct if_txrx ifc_txrx;
205 #define isc_txd_encap ifc_txrx.ift_txd_encap
206 #define isc_txd_flush ifc_txrx.ift_txd_flush
207 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
208 #define isc_rxd_available ifc_txrx.ift_rxd_available
209 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
213 #define isc_txq_select ifc_txrx.ift_txq_select
214 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2
215 eventhandler_tag ifc_vlan_attach_event;
216 eventhandler_tag ifc_vlan_detach_event;
217 struct ether_addr ifc_mac;
221 iflib_get_softc(if_ctx_t ctx)
224 return (ctx->ifc_softc);
228 iflib_get_dev(if_ctx_t ctx)
231 return (ctx->ifc_dev);
235 iflib_get_ifp(if_ctx_t ctx)
238 return (ctx->ifc_ifp);
242 iflib_get_media(if_ctx_t ctx)
245 return (ctx->ifc_mediap);
249 iflib_get_flags(if_ctx_t ctx)
251 return (ctx->ifc_flags);
255 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
258 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
262 iflib_get_softc_ctx(if_ctx_t ctx)
265 return (&ctx->ifc_softc_ctx);
269 iflib_get_sctx(if_ctx_t ctx)
272 return (ctx->ifc_sctx);
275 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
276 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
277 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
279 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
280 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
282 typedef struct iflib_sw_rx_desc_array {
283 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
284 struct mbuf **ifsd_m; /* pkthdr mbufs */
285 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
286 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
287 } iflib_rxsd_array_t;
289 typedef struct iflib_sw_tx_desc_array {
290 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
291 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
292 struct mbuf **ifsd_m; /* pkthdr mbufs */
295 /* magic number that should be high enough for any hardware */
296 #define IFLIB_MAX_TX_SEGS 128
297 #define IFLIB_RX_COPY_THRESH 128
298 #define IFLIB_MAX_RX_REFRESH 32
299 /* The minimum descriptors per second before we start coalescing */
300 #define IFLIB_MIN_DESC_SEC 16384
301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
302 #define IFLIB_QUEUE_IDLE 0
303 #define IFLIB_QUEUE_HUNG 1
304 #define IFLIB_QUEUE_WORKING 2
305 /* maximum number of txqs that can share an rx interrupt */
306 #define IFLIB_MAX_TX_SHARED_INTR 4
308 /* this should really scale with ring size - this is a fairly arbitrary value */
309 #define TX_BATCH_SIZE 32
311 #define IFLIB_RESTART_BUDGET 8
313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
320 qidx_t ift_cidx_processed;
323 uint8_t ift_br_offset;
324 uint16_t ift_npending;
325 uint16_t ift_db_pending;
326 uint16_t ift_rs_pending;
328 uint8_t ift_txd_size[8];
329 uint64_t ift_processed;
330 uint64_t ift_cleaned;
331 uint64_t ift_cleaned_prev;
333 uint64_t ift_enqueued;
334 uint64_t ift_dequeued;
336 uint64_t ift_no_tx_dma_setup;
337 uint64_t ift_no_desc_avail;
338 uint64_t ift_mbuf_defrag_failed;
339 uint64_t ift_mbuf_defrag;
340 uint64_t ift_map_failed;
341 uint64_t ift_txd_encap_efbig;
342 uint64_t ift_pullups;
343 uint64_t ift_last_timer_tick;
346 struct mtx ift_db_mtx;
348 /* constant values */
350 struct ifmp_ring *ift_br;
351 struct grouptask ift_task;
354 struct callout ift_timer;
356 struct callout ift_netmap_timer;
357 #endif /* DEV_NETMAP */
359 if_txsd_vec_t ift_sds;
362 uint8_t ift_update_freq;
363 struct iflib_filter_info ift_filter_info;
364 bus_dma_tag_t ift_buf_tag;
365 bus_dma_tag_t ift_tso_buf_tag;
366 iflib_dma_info_t ift_ifdi;
367 #define MTX_NAME_LEN 32
368 char ift_mtx_name[MTX_NAME_LEN];
369 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
370 #ifdef IFLIB_DIAGNOSTICS
371 uint64_t ift_cpu_exec_count[256];
373 } __aligned(CACHE_LINE_SIZE);
380 uint8_t ifl_rxd_size;
382 uint64_t ifl_m_enqueued;
383 uint64_t ifl_m_dequeued;
384 uint64_t ifl_cl_enqueued;
385 uint64_t ifl_cl_dequeued;
388 bitstr_t *ifl_rx_bitmap;
392 uint16_t ifl_buf_size;
395 iflib_rxsd_array_t ifl_sds;
398 bus_dma_tag_t ifl_buf_tag;
399 iflib_dma_info_t ifl_ifdi;
400 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
401 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
402 } __aligned(CACHE_LINE_SIZE);
405 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
411 else if (pidx < cidx)
412 used = size - cidx + pidx;
413 else if (gen == 0 && pidx == cidx)
415 else if (gen == 1 && pidx == cidx)
423 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
425 #define IDXDIFF(head, tail, wrap) \
426 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
432 struct pfil_head *pfil;
434 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
435 * the completion queue consumer index. Otherwise it's unused.
441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
442 uint8_t ifr_fl_offset;
443 struct lro_ctrl ifr_lc;
444 struct grouptask ifr_task;
445 struct callout ifr_watchdog;
446 struct iflib_filter_info ifr_filter_info;
447 iflib_dma_info_t ifr_ifdi;
449 /* dynamically allocate if any drivers need a value substantially larger than this */
450 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
451 #ifdef IFLIB_DIAGNOSTICS
452 uint64_t ifr_cpu_exec_count[256];
454 } __aligned(CACHE_LINE_SIZE);
456 typedef struct if_rxsd {
461 /* multiple of word size */
463 #define PKT_INFO_SIZE 6
464 #define RXD_INFO_SIZE 5
465 #define PKT_TYPE uint64_t
467 #define PKT_INFO_SIZE 11
468 #define RXD_INFO_SIZE 8
469 #define PKT_TYPE uint32_t
471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
474 typedef struct if_pkt_info_pad {
475 PKT_TYPE pkt_val[PKT_INFO_SIZE];
476 } *if_pkt_info_pad_t;
477 typedef struct if_rxd_info_pad {
478 PKT_TYPE rxd_val[RXD_INFO_SIZE];
479 } *if_rxd_info_pad_t;
481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
485 pkt_info_zero(if_pkt_info_t pi)
487 if_pkt_info_pad_t pi_pad;
489 pi_pad = (if_pkt_info_pad_t)pi;
490 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
491 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
493 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
494 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
498 static device_method_t iflib_pseudo_methods[] = {
499 DEVMETHOD(device_attach, noop_attach),
500 DEVMETHOD(device_detach, iflib_pseudo_detach),
504 driver_t iflib_pseudodriver = {
505 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
509 rxd_info_zero(if_rxd_info_t ri)
511 if_rxd_info_pad_t ri_pad;
514 ri_pad = (if_rxd_info_pad_t)ri;
515 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
516 ri_pad->rxd_val[i] = 0;
517 ri_pad->rxd_val[i+1] = 0;
518 ri_pad->rxd_val[i+2] = 0;
519 ri_pad->rxd_val[i+3] = 0;
522 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
527 * Only allow a single packet to take up most 1/nth of the tx ring
529 #define MAX_SINGLE_PACKET_FRACTION 12
530 #define IF_BAD_DMA (bus_addr_t)-1
532 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
534 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
535 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
536 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
537 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
539 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
540 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
541 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
542 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
544 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
545 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
548 iflib_set_detach(if_ctx_t ctx)
551 ctx->ifc_flags |= IFC_IN_DETACH;
555 /* Our boot-time initialization hook */
556 static int iflib_module_event_handler(module_t, int, void *);
558 static moduledata_t iflib_moduledata = {
560 iflib_module_event_handler,
564 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
565 MODULE_VERSION(iflib, 1);
567 MODULE_DEPEND(iflib, pci, 1, 1, 1);
568 MODULE_DEPEND(iflib, ether, 1, 1, 1);
570 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
571 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
573 #ifndef IFLIB_DEBUG_COUNTERS
575 #define IFLIB_DEBUG_COUNTERS 1
577 #define IFLIB_DEBUG_COUNTERS 0
578 #endif /* !INVARIANTS */
581 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
582 "iflib driver parameters");
585 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
587 static int iflib_min_tx_latency = 0;
588 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
589 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
590 static int iflib_no_tx_batch = 0;
591 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
592 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
593 static int iflib_timer_default = 1000;
594 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
595 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
598 #if IFLIB_DEBUG_COUNTERS
600 static int iflib_tx_seen;
601 static int iflib_tx_sent;
602 static int iflib_tx_encap;
603 static int iflib_rx_allocs;
604 static int iflib_fl_refills;
605 static int iflib_fl_refills_large;
606 static int iflib_tx_frees;
608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
609 &iflib_tx_seen, 0, "# TX mbufs seen");
610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
611 &iflib_tx_sent, 0, "# TX mbufs sent");
612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
613 &iflib_tx_encap, 0, "# TX mbufs encapped");
614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
615 &iflib_tx_frees, 0, "# TX frees");
616 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
617 &iflib_rx_allocs, 0, "# RX allocations");
618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
619 &iflib_fl_refills, 0, "# refills");
620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
621 &iflib_fl_refills_large, 0, "# large refills");
623 static int iflib_txq_drain_flushing;
624 static int iflib_txq_drain_oactive;
625 static int iflib_txq_drain_notready;
627 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
628 &iflib_txq_drain_flushing, 0, "# drain flushes");
629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
630 &iflib_txq_drain_oactive, 0, "# drain oactives");
631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
632 &iflib_txq_drain_notready, 0, "# drain notready");
634 static int iflib_encap_load_mbuf_fail;
635 static int iflib_encap_pad_mbuf_fail;
636 static int iflib_encap_txq_avail_fail;
637 static int iflib_encap_txd_encap_fail;
639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
640 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
642 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
644 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
646 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
648 static int iflib_task_fn_rxs;
649 static int iflib_rx_intr_enables;
650 static int iflib_fast_intrs;
651 static int iflib_rx_unavail;
652 static int iflib_rx_ctx_inactive;
653 static int iflib_rx_if_input;
654 static int iflib_rxd_flush;
656 static int iflib_verbose_debug;
658 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
659 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
661 &iflib_rx_intr_enables, 0, "# RX intr enables");
662 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
663 &iflib_fast_intrs, 0, "# fast_intr calls");
664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
665 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
667 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
669 &iflib_rx_if_input, 0, "# times rxeof called if_input");
670 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
671 &iflib_rxd_flush, 0, "# times rxd_flush called");
672 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
673 &iflib_verbose_debug, 0, "enable verbose debugging");
675 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
677 iflib_debug_reset(void)
679 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
680 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
681 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
682 iflib_txq_drain_notready =
683 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
684 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
685 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
687 iflib_rx_ctx_inactive = iflib_rx_if_input =
692 #define DBG_COUNTER_INC(name)
693 static void iflib_debug_reset(void) {}
696 #define IFLIB_DEBUG 0
698 static void iflib_tx_structures_free(if_ctx_t ctx);
699 static void iflib_rx_structures_free(if_ctx_t ctx);
700 static int iflib_queues_alloc(if_ctx_t ctx);
701 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
702 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
703 static int iflib_qset_structures_setup(if_ctx_t ctx);
704 static int iflib_msix_init(if_ctx_t ctx);
705 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
706 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
707 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
709 static void iflib_altq_if_start(if_t ifp);
710 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
712 static int iflib_register(if_ctx_t);
713 static void iflib_deregister(if_ctx_t);
714 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
715 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
716 static void iflib_init_locked(if_ctx_t ctx);
717 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
718 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
719 static void iflib_ifmp_purge(iflib_txq_t txq);
720 static void _iflib_pre_assert(if_softc_ctx_t scctx);
721 static void iflib_if_init_locked(if_ctx_t ctx);
722 static void iflib_free_intr_mem(if_ctx_t ctx);
723 #ifndef __NO_STRICT_ALIGNMENT
724 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
727 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
728 SLIST_HEAD_INITIALIZER(cpu_offsets);
730 SLIST_ENTRY(cpu_offset) entries;
732 unsigned int refcount;
735 static struct mtx cpu_offset_mtx;
736 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
739 DEBUGNET_DEFINE(iflib);
742 iflib_num_rx_descs(if_ctx_t ctx)
744 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
745 if_shared_ctx_t sctx = ctx->ifc_sctx;
746 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
748 return scctx->isc_nrxd[first_rxq];
752 iflib_num_tx_descs(if_ctx_t ctx)
754 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
755 if_shared_ctx_t sctx = ctx->ifc_sctx;
756 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
758 return scctx->isc_ntxd[first_txq];
762 #include <sys/selinfo.h>
763 #include <net/netmap.h>
764 #include <dev/netmap/netmap_kern.h>
766 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
768 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
769 static void iflib_netmap_timer(void *arg);
772 * device-specific sysctl variables:
774 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
775 * During regular operations the CRC is stripped, but on some
776 * hardware reception of frames not multiple of 64 is slower,
777 * so using crcstrip=0 helps in benchmarks.
779 * iflib_rx_miss, iflib_rx_miss_bufs:
780 * count packets that might be missed due to lost interrupts.
782 SYSCTL_DECL(_dev_netmap);
784 * The xl driver by default strips CRCs and we do not override it.
787 int iflib_crcstrip = 1;
788 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
789 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
791 int iflib_rx_miss, iflib_rx_miss_bufs;
792 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
793 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
794 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
795 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
798 * Register/unregister. We are already under netmap lock.
799 * Only called on the first register or the last unregister.
802 iflib_netmap_register(struct netmap_adapter *na, int onoff)
805 if_ctx_t ctx = if_getsoftc(ifp);
810 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
815 * Enable (or disable) netmap flags, and intercept (or restore)
816 * ifp->if_transmit. This is done once the device has been stopped
817 * to prevent race conditions. Also, this must be done after
818 * calling netmap_disable_all_rings() and before calling
819 * netmap_enable_all_rings(), so that these two functions see the
820 * updated state of the NAF_NETMAP_ON bit.
823 nm_set_native_flags(na);
825 nm_clear_native_flags(na);
828 iflib_init_locked(ctx);
829 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
830 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1;
832 nm_clear_native_flags(na);
838 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
841 if_ctx_t ctx = if_getsoftc(ifp);
842 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
843 iflib_fl_t fl = &rxq->ifr_fl[0];
845 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
846 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
847 info->num_tx_descs = iflib_num_tx_descs(ctx);
848 info->num_rx_descs = iflib_num_rx_descs(ctx);
849 info->rx_buf_maxsize = fl->ifl_buf_size;
850 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
851 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
852 info->num_rx_descs, info->rx_buf_maxsize);
858 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
860 struct netmap_adapter *na = kring->na;
861 u_int const lim = kring->nkr_num_slots - 1;
862 struct netmap_ring *ring = kring->ring;
864 struct if_rxd_update iru;
865 if_ctx_t ctx = rxq->ifr_ctx;
866 iflib_fl_t fl = &rxq->ifr_fl[0];
867 u_int nic_i_first, nic_i;
870 #if IFLIB_DEBUG_COUNTERS
875 * This function is used both at initialization and in rxsync.
876 * At initialization we need to prepare (with isc_rxd_refill())
877 * all the netmap buffers currently owned by the kernel, in
878 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
879 * (except for kring->nkr_hwofs). These may be less than
880 * kring->nkr_num_slots if netmap_reset() was called while
881 * an application using the kring that still owned some
883 * At rxsync time, both indexes point to the next buffer to be
885 * In any case we publish (with isc_rxd_flush()) up to
886 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
887 * pointer to overrun the head/cons pointer, although this is
888 * not necessary for some NICs (e.g. vmx).
890 if (__predict_false(init)) {
891 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
893 n = kring->rhead - kring->nr_hwcur;
895 return (0); /* Nothing to do. */
897 n += kring->nkr_num_slots;
900 iru_init(&iru, rxq, 0 /* flid */);
901 map = fl->ifl_sds.ifsd_map;
902 nic_i = fl->ifl_pidx;
903 nm_i = netmap_idx_n2k(kring, nic_i);
904 if (__predict_false(init)) {
906 * On init/reset, nic_i must be 0, and we must
907 * start to refill from hwtail (see netmap_reset()).
910 MPASS(nm_i == kring->nr_hwtail);
912 MPASS(nm_i == kring->nr_hwcur);
913 DBG_COUNTER_INC(fl_refills);
915 #if IFLIB_DEBUG_COUNTERS
917 DBG_COUNTER_INC(fl_refills_large);
920 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
921 struct netmap_slot *slot = &ring->slot[nm_i];
923 void *addr = PNMB(na, slot, &paddr);
925 MPASS(i < IFLIB_MAX_RX_REFRESH);
927 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
928 return netmap_ring_reinit(kring);
930 fl->ifl_bus_addrs[i] = paddr +
931 nm_get_offset(kring, slot);
932 fl->ifl_rxd_idxs[i] = nic_i;
934 if (__predict_false(init)) {
935 netmap_load_map(na, fl->ifl_buf_tag,
937 } else if (slot->flags & NS_BUF_CHANGED) {
938 /* buffer has changed, reload map */
939 netmap_reload_map(na, fl->ifl_buf_tag,
942 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
943 BUS_DMASYNC_PREREAD);
944 slot->flags &= ~NS_BUF_CHANGED;
946 nm_i = nm_next(nm_i, lim);
947 nic_i = nm_next(nic_i, lim);
950 iru.iru_pidx = nic_i_first;
952 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
954 fl->ifl_pidx = nic_i;
956 * At the end of the loop we must have refilled everything
957 * we could possibly refill.
959 MPASS(nm_i == kring->rhead);
960 kring->nr_hwcur = nm_i;
962 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
963 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
964 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
965 nm_prev(nic_i, lim));
966 DBG_COUNTER_INC(rxd_flush);
971 #define NETMAP_TX_TIMER_US 90
974 * Reconcile kernel and user view of the transmit ring.
976 * All information is in the kring.
977 * Userspace wants to send packets up to the one before kring->rhead,
978 * kernel knows kring->nr_hwcur is the first unsent packet.
980 * Here we push packets out (as many as possible), and possibly
981 * reclaim buffers from previously completed transmission.
983 * The caller (netmap) guarantees that there is only one instance
984 * running at any time. Any interference with other driver
985 * methods should be handled by the individual drivers.
988 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
990 struct netmap_adapter *na = kring->na;
992 struct netmap_ring *ring = kring->ring;
993 u_int nm_i; /* index into the netmap kring */
994 u_int nic_i; /* index into the NIC ring */
995 u_int const lim = kring->nkr_num_slots - 1;
996 u_int const head = kring->rhead;
997 struct if_pkt_info pi;
998 int tx_pkts = 0, tx_bytes = 0;
1001 * interrupts on every tx packet are expensive so request
1002 * them every half ring, or where NS_REPORT is set
1004 u_int report_frequency = kring->nkr_num_slots >> 1;
1005 /* device-specific */
1006 if_ctx_t ctx = if_getsoftc(ifp);
1007 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
1009 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1013 * First part: process new packets to send.
1014 * nm_i is the current index in the netmap kring,
1015 * nic_i is the corresponding index in the NIC ring.
1017 * If we have packets to send (nm_i != head)
1018 * iterate over the netmap ring, fetch length and update
1019 * the corresponding slot in the NIC ring. Some drivers also
1020 * need to update the buffer's physical address in the NIC slot
1021 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1023 * The netmap_reload_map() calls is especially expensive,
1024 * even when (as in this case) the tag is 0, so do only
1025 * when the buffer has actually changed.
1027 * If possible do not set the report/intr bit on all slots,
1028 * but only a few times per ring or when NS_REPORT is set.
1030 * Finally, on 10G and faster drivers, it might be useful
1031 * to prefetch the next slot and txr entry.
1034 nm_i = kring->nr_hwcur;
1035 if (nm_i != head) { /* we have new packets to send */
1036 uint32_t pkt_len = 0, seg_idx = 0;
1037 int nic_i_start = -1, flags = 0;
1039 pi.ipi_segs = txq->ift_segs;
1040 pi.ipi_qsidx = kring->ring_id;
1041 nic_i = netmap_idx_k2n(kring, nm_i);
1043 __builtin_prefetch(&ring->slot[nm_i]);
1044 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1045 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1047 while (nm_i != head) {
1048 struct netmap_slot *slot = &ring->slot[nm_i];
1049 uint64_t offset = nm_get_offset(kring, slot);
1050 u_int len = slot->len;
1052 void *addr = PNMB(na, slot, &paddr);
1054 flags |= (slot->flags & NS_REPORT ||
1055 nic_i == 0 || nic_i == report_frequency) ?
1059 * If this is the first packet fragment, save the
1060 * index of the first NIC slot for later.
1062 if (nic_i_start < 0)
1063 nic_i_start = nic_i;
1065 pi.ipi_segs[seg_idx].ds_addr = paddr + offset;
1066 pi.ipi_segs[seg_idx].ds_len = len;
1072 if (!(slot->flags & NS_MOREFRAG)) {
1073 pi.ipi_len = pkt_len;
1074 pi.ipi_nsegs = seg_idx;
1075 pi.ipi_pidx = nic_i_start;
1077 pi.ipi_flags = flags;
1079 /* Prepare the NIC TX ring. */
1080 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1081 DBG_COUNTER_INC(tx_encap);
1083 /* Update transmit counters */
1084 tx_bytes += pi.ipi_len;
1087 /* Reinit per-packet info for the next one. */
1088 flags = seg_idx = pkt_len = 0;
1092 /* prefetch for next round */
1093 __builtin_prefetch(&ring->slot[nm_i + 1]);
1094 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1095 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1097 NM_CHECK_ADDR_LEN_OFF(na, len, offset);
1099 if (slot->flags & NS_BUF_CHANGED) {
1100 /* buffer has changed, reload map */
1101 netmap_reload_map(na, txq->ift_buf_tag,
1102 txq->ift_sds.ifsd_map[nic_i], addr);
1104 /* make sure changes to the buffer are synced */
1105 bus_dmamap_sync(txq->ift_buf_tag,
1106 txq->ift_sds.ifsd_map[nic_i],
1107 BUS_DMASYNC_PREWRITE);
1109 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1110 nm_i = nm_next(nm_i, lim);
1111 nic_i = nm_next(nic_i, lim);
1113 kring->nr_hwcur = nm_i;
1115 /* synchronize the NIC ring */
1116 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1119 /* (re)start the tx unit up to slot nic_i (excluded) */
1120 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1124 * Second part: reclaim buffers for completed transmissions.
1126 * If there are unclaimed buffers, attempt to reclaim them.
1127 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1128 * trigger a per-tx-queue timer to try again later.
1130 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1131 if (iflib_tx_credits_update(ctx, txq)) {
1132 /* some tx completed, increment avail */
1133 nic_i = txq->ift_cidx_processed;
1134 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1138 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1139 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1140 callout_reset_sbt_on(&txq->ift_netmap_timer,
1141 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1142 iflib_netmap_timer, txq,
1143 txq->ift_netmap_timer.c_cpu, 0);
1146 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes);
1147 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts);
1153 * Reconcile kernel and user view of the receive ring.
1154 * Same as for the txsync, this routine must be efficient.
1155 * The caller guarantees a single invocations, but races against
1156 * the rest of the driver should be handled here.
1158 * On call, kring->rhead is the first packet that userspace wants
1159 * to keep, and kring->rcur is the wakeup point.
1160 * The kernel has previously reported packets up to kring->rtail.
1162 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1163 * of whether or not we received an interrupt.
1166 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1168 struct netmap_adapter *na = kring->na;
1169 struct netmap_ring *ring = kring->ring;
1171 uint32_t nm_i; /* index into the netmap ring */
1172 uint32_t nic_i; /* index into the NIC ring */
1174 u_int const lim = kring->nkr_num_slots - 1;
1175 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1176 int i = 0, rx_bytes = 0, rx_pkts = 0;
1178 if_ctx_t ctx = if_getsoftc(ifp);
1179 if_shared_ctx_t sctx = ctx->ifc_sctx;
1180 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1181 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1182 iflib_fl_t fl = &rxq->ifr_fl[0];
1183 struct if_rxd_info ri;
1187 * netmap only uses free list 0, to avoid out of order consumption
1188 * of receive buffers
1191 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1192 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1195 * First part: import newly received packets.
1197 * nm_i is the index of the next free slot in the netmap ring,
1198 * nic_i is the index of the next received packet in the NIC ring
1199 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1200 * differ in case if_init() has been called while
1201 * in netmap mode. For the receive ring we have
1203 * nic_i = fl->ifl_cidx;
1204 * nm_i = kring->nr_hwtail (previous)
1206 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1208 * fl->ifl_cidx is set to 0 on a ring reinit
1210 if (netmap_no_pendintr || force_update) {
1211 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1212 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1213 int crclen = iflib_crcstrip ? 0 : 4;
1217 * For the free list consumer index, we use the same
1218 * logic as in iflib_rxeof().
1221 cidxp = &rxq->ifr_cq_cidx;
1223 cidxp = &fl->ifl_cidx;
1224 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1225 rxq->ifr_id, *cidxp, USHRT_MAX);
1227 nic_i = fl->ifl_cidx;
1228 nm_i = netmap_idx_n2k(kring, nic_i);
1229 MPASS(nm_i == kring->nr_hwtail);
1230 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1232 ri.iri_frags = rxq->ifr_frags;
1233 ri.iri_qsidx = kring->ring_id;
1234 ri.iri_ifp = ctx->ifc_ifp;
1235 ri.iri_cidx = *cidxp;
1237 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1238 for (i = 0; i < ri.iri_nfrags; i++) {
1240 ring->slot[nm_i].len = 0;
1241 ring->slot[nm_i].flags = 0;
1243 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1244 if (i == (ri.iri_nfrags - 1)) {
1245 ring->slot[nm_i].len -= crclen;
1246 ring->slot[nm_i].flags = 0;
1248 /* Update receive counters */
1249 rx_bytes += ri.iri_len;
1252 ring->slot[nm_i].flags = NS_MOREFRAG;
1255 bus_dmamap_sync(fl->ifl_buf_tag,
1256 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1257 nm_i = nm_next(nm_i, lim);
1258 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1262 *cidxp = ri.iri_cidx;
1263 while (*cidxp >= scctx->isc_nrxd[0])
1264 *cidxp -= scctx->isc_nrxd[0];
1268 if (n) { /* update the state variables */
1269 if (netmap_no_pendintr && !force_update) {
1272 iflib_rx_miss_bufs += n;
1274 kring->nr_hwtail = nm_i;
1276 kring->nr_kflags &= ~NKR_PENDINTR;
1279 * Second part: skip past packets that userspace has released.
1280 * (kring->nr_hwcur to head excluded),
1281 * and make the buffers available for reception.
1282 * As usual nm_i is the index in the netmap ring,
1283 * nic_i is the index in the NIC ring, and
1284 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1286 netmap_fl_refill(rxq, kring, false);
1288 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
1289 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
1295 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1297 if_ctx_t ctx = if_getsoftc(na->ifp);
1301 IFDI_INTR_ENABLE(ctx);
1303 IFDI_INTR_DISABLE(ctx);
1309 iflib_netmap_attach(if_ctx_t ctx)
1311 struct netmap_adapter na;
1313 bzero(&na, sizeof(na));
1315 na.ifp = ctx->ifc_ifp;
1316 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS;
1317 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1318 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1320 na.num_tx_desc = iflib_num_tx_descs(ctx);
1321 na.num_rx_desc = iflib_num_rx_descs(ctx);
1322 na.nm_txsync = iflib_netmap_txsync;
1323 na.nm_rxsync = iflib_netmap_rxsync;
1324 na.nm_register = iflib_netmap_register;
1325 na.nm_intr = iflib_netmap_intr;
1326 na.nm_config = iflib_netmap_config;
1327 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1328 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1329 return (netmap_attach(&na));
1333 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1335 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1336 struct netmap_slot *slot;
1338 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1341 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1343 * In netmap mode, set the map for the packet buffer.
1344 * NOTE: Some drivers (not this one) also need to set
1345 * the physical buffer address in the NIC ring.
1346 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1347 * netmap slot index, si
1349 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1350 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1351 NMB(na, slot + si));
1357 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1359 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1360 struct netmap_kring *kring;
1361 struct netmap_slot *slot;
1363 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1366 kring = na->rx_rings[rxq->ifr_id];
1367 netmap_fl_refill(rxq, kring, true);
1372 iflib_netmap_timer(void *arg)
1374 iflib_txq_t txq = arg;
1375 if_ctx_t ctx = txq->ift_ctx;
1378 * Wake up the netmap application, to give it a chance to
1379 * call txsync and reclaim more completed TX buffers.
1381 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1384 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1387 #define iflib_netmap_txq_init(ctx, txq) (0)
1388 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1389 #define iflib_netmap_detach(ifp)
1390 #define netmap_enable_all_rings(ifp)
1391 #define netmap_disable_all_rings(ifp)
1393 #define iflib_netmap_attach(ctx) (0)
1394 #define netmap_rx_irq(ifp, qid, budget) (0)
1397 #if defined(__i386__) || defined(__amd64__)
1398 static __inline void
1401 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1404 static __inline void
1405 prefetch2cachelines(void *x)
1407 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1408 #if (CACHE_LINE_SIZE < 128)
1409 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1413 static __inline void
1418 static __inline void
1419 prefetch2cachelines(void *x)
1425 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1429 fl = &rxq->ifr_fl[flid];
1430 iru->iru_paddrs = fl->ifl_bus_addrs;
1431 iru->iru_idxs = fl->ifl_rxd_idxs;
1432 iru->iru_qsidx = rxq->ifr_id;
1433 iru->iru_buf_size = fl->ifl_buf_size;
1434 iru->iru_flidx = fl->ifl_id;
1438 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1442 *(bus_addr_t *) arg = segs[0].ds_addr;
1445 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \
1446 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \
1447 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL)
1450 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1453 device_t dev = ctx->ifc_dev;
1456 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width);
1458 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1459 align, 0, /* alignment, bounds */
1460 lowaddr, /* lowaddr */
1461 BUS_SPACE_MAXADDR, /* highaddr */
1462 NULL, NULL, /* filter, filterarg */
1465 size, /* maxsegsize */
1466 BUS_DMA_ALLOCNOW, /* flags */
1467 NULL, /* lockfunc */
1472 "%s: bus_dma_tag_create failed: %d\n",
1477 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1478 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1481 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1482 __func__, (uintmax_t)size, err);
1486 dma->idi_paddr = IF_BAD_DMA;
1487 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1488 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1489 if (err || dma->idi_paddr == IF_BAD_DMA) {
1491 "%s: bus_dmamap_load failed: %d\n",
1496 dma->idi_size = size;
1500 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1502 bus_dma_tag_destroy(dma->idi_tag);
1504 dma->idi_tag = NULL;
1510 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1512 if_shared_ctx_t sctx = ctx->ifc_sctx;
1514 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1516 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1520 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1523 iflib_dma_info_t *dmaiter;
1526 for (i = 0; i < count; i++, dmaiter++) {
1527 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1531 iflib_dma_free_multi(dmalist, i);
1536 iflib_dma_free(iflib_dma_info_t dma)
1538 if (dma->idi_tag == NULL)
1540 if (dma->idi_paddr != IF_BAD_DMA) {
1541 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1542 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1543 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1544 dma->idi_paddr = IF_BAD_DMA;
1546 if (dma->idi_vaddr != NULL) {
1547 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1548 dma->idi_vaddr = NULL;
1550 bus_dma_tag_destroy(dma->idi_tag);
1551 dma->idi_tag = NULL;
1555 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1558 iflib_dma_info_t *dmaiter = dmalist;
1560 for (i = 0; i < count; i++, dmaiter++)
1561 iflib_dma_free(*dmaiter);
1565 iflib_fast_intr(void *arg)
1567 iflib_filter_info_t info = arg;
1568 struct grouptask *gtask = info->ifi_task;
1571 DBG_COUNTER_INC(fast_intrs);
1572 if (info->ifi_filter != NULL) {
1573 result = info->ifi_filter(info->ifi_filter_arg);
1574 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1578 GROUPTASK_ENQUEUE(gtask);
1579 return (FILTER_HANDLED);
1583 iflib_fast_intr_rxtx(void *arg)
1585 iflib_filter_info_t info = arg;
1586 struct grouptask *gtask = info->ifi_task;
1588 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1591 int i, cidx, result;
1593 bool intr_enable, intr_legacy;
1595 DBG_COUNTER_INC(fast_intrs);
1596 if (info->ifi_filter != NULL) {
1597 result = info->ifi_filter(info->ifi_filter_arg);
1598 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1603 sc = ctx->ifc_softc;
1604 intr_enable = false;
1605 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1606 MPASS(rxq->ifr_ntxqirq);
1607 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1608 txqid = rxq->ifr_txqid[i];
1609 txq = &ctx->ifc_txqs[txqid];
1610 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1611 BUS_DMASYNC_POSTREAD);
1612 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1616 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1619 GROUPTASK_ENQUEUE(&txq->ift_task);
1621 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1622 cidx = rxq->ifr_cq_cidx;
1624 cidx = rxq->ifr_fl[0].ifl_cidx;
1625 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1626 GROUPTASK_ENQUEUE(gtask);
1631 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1632 DBG_COUNTER_INC(rx_intr_enables);
1635 IFDI_INTR_ENABLE(ctx);
1636 return (FILTER_HANDLED);
1640 iflib_fast_intr_ctx(void *arg)
1642 iflib_filter_info_t info = arg;
1643 struct grouptask *gtask = info->ifi_task;
1646 DBG_COUNTER_INC(fast_intrs);
1647 if (info->ifi_filter != NULL) {
1648 result = info->ifi_filter(info->ifi_filter_arg);
1649 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1653 GROUPTASK_ENQUEUE(gtask);
1654 return (FILTER_HANDLED);
1658 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1659 driver_filter_t filter, driver_intr_t handler, void *arg,
1662 struct resource *res;
1664 device_t dev = ctx->ifc_dev;
1668 if (ctx->ifc_flags & IFC_LEGACY)
1669 flags |= RF_SHAREABLE;
1672 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1675 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1679 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1680 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1681 filter, handler, arg, &tag);
1684 "failed to setup interrupt for rid %d, name %s: %d\n",
1685 rid, name ? name : "unknown", rc);
1688 bus_describe_intr(dev, res, tag, "%s", name);
1694 /*********************************************************************
1696 * Allocate DMA resources for TX buffers as well as memory for the TX
1697 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1698 * iflib_sw_tx_desc_array structure, storing all the information that
1699 * is needed to transmit a packet on the wire. This is called only
1700 * once at attach, setup is done every reset.
1702 **********************************************************************/
1704 iflib_txsd_alloc(iflib_txq_t txq)
1706 if_ctx_t ctx = txq->ift_ctx;
1707 if_shared_ctx_t sctx = ctx->ifc_sctx;
1708 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1709 device_t dev = ctx->ifc_dev;
1710 bus_size_t tsomaxsize;
1712 int err, nsegments, ntsosegments;
1715 nsegments = scctx->isc_tx_nsegments;
1716 ntsosegments = scctx->isc_tx_tso_segments_max;
1717 tsomaxsize = scctx->isc_tx_tso_size_max;
1718 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1719 tsomaxsize += sizeof(struct ether_vlan_header);
1720 MPASS(scctx->isc_ntxd[0] > 0);
1721 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1722 MPASS(nsegments > 0);
1723 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1724 MPASS(ntsosegments > 0);
1725 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1728 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1731 * Set up DMA tags for TX buffers.
1733 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1734 1, 0, /* alignment, bounds */
1735 lowaddr, /* lowaddr */
1736 BUS_SPACE_MAXADDR, /* highaddr */
1737 NULL, NULL, /* filter, filterarg */
1738 sctx->isc_tx_maxsize, /* maxsize */
1739 nsegments, /* nsegments */
1740 sctx->isc_tx_maxsegsize, /* maxsegsize */
1742 NULL, /* lockfunc */
1743 NULL, /* lockfuncarg */
1744 &txq->ift_buf_tag))) {
1745 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1746 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1747 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1750 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1751 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1752 1, 0, /* alignment, bounds */
1753 lowaddr, /* lowaddr */
1754 BUS_SPACE_MAXADDR, /* highaddr */
1755 NULL, NULL, /* filter, filterarg */
1756 tsomaxsize, /* maxsize */
1757 ntsosegments, /* nsegments */
1758 sctx->isc_tso_maxsegsize,/* maxsegsize */
1760 NULL, /* lockfunc */
1761 NULL, /* lockfuncarg */
1762 &txq->ift_tso_buf_tag))) {
1763 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1768 /* Allocate memory for the TX mbuf map. */
1769 if (!(txq->ift_sds.ifsd_m =
1770 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1771 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1772 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1778 * Create the DMA maps for TX buffers.
1780 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1781 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1782 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1784 "Unable to allocate TX buffer DMA map memory\n");
1788 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1789 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1790 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1792 "Unable to allocate TSO TX buffer map memory\n");
1796 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1797 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1798 &txq->ift_sds.ifsd_map[i]);
1800 device_printf(dev, "Unable to create TX DMA map\n");
1805 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1806 &txq->ift_sds.ifsd_tso_map[i]);
1808 device_printf(dev, "Unable to create TSO TX DMA map\n");
1814 /* We free all, it handles case where we are in the middle */
1815 iflib_tx_structures_free(ctx);
1820 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1824 if (txq->ift_sds.ifsd_map != NULL) {
1825 map = txq->ift_sds.ifsd_map[i];
1826 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1827 bus_dmamap_unload(txq->ift_buf_tag, map);
1828 bus_dmamap_destroy(txq->ift_buf_tag, map);
1829 txq->ift_sds.ifsd_map[i] = NULL;
1832 if (txq->ift_sds.ifsd_tso_map != NULL) {
1833 map = txq->ift_sds.ifsd_tso_map[i];
1834 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1835 BUS_DMASYNC_POSTWRITE);
1836 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1837 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1838 txq->ift_sds.ifsd_tso_map[i] = NULL;
1843 iflib_txq_destroy(iflib_txq_t txq)
1845 if_ctx_t ctx = txq->ift_ctx;
1847 for (int i = 0; i < txq->ift_size; i++)
1848 iflib_txsd_destroy(ctx, txq, i);
1850 if (txq->ift_br != NULL) {
1851 ifmp_ring_free(txq->ift_br);
1855 mtx_destroy(&txq->ift_mtx);
1857 if (txq->ift_sds.ifsd_map != NULL) {
1858 free(txq->ift_sds.ifsd_map, M_IFLIB);
1859 txq->ift_sds.ifsd_map = NULL;
1861 if (txq->ift_sds.ifsd_tso_map != NULL) {
1862 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1863 txq->ift_sds.ifsd_tso_map = NULL;
1865 if (txq->ift_sds.ifsd_m != NULL) {
1866 free(txq->ift_sds.ifsd_m, M_IFLIB);
1867 txq->ift_sds.ifsd_m = NULL;
1869 if (txq->ift_buf_tag != NULL) {
1870 bus_dma_tag_destroy(txq->ift_buf_tag);
1871 txq->ift_buf_tag = NULL;
1873 if (txq->ift_tso_buf_tag != NULL) {
1874 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1875 txq->ift_tso_buf_tag = NULL;
1877 if (txq->ift_ifdi != NULL) {
1878 free(txq->ift_ifdi, M_IFLIB);
1883 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1887 mp = &txq->ift_sds.ifsd_m[i];
1891 if (txq->ift_sds.ifsd_map != NULL) {
1892 bus_dmamap_sync(txq->ift_buf_tag,
1893 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1894 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1896 if (txq->ift_sds.ifsd_tso_map != NULL) {
1897 bus_dmamap_sync(txq->ift_tso_buf_tag,
1898 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1899 bus_dmamap_unload(txq->ift_tso_buf_tag,
1900 txq->ift_sds.ifsd_tso_map[i]);
1903 DBG_COUNTER_INC(tx_frees);
1908 iflib_txq_setup(iflib_txq_t txq)
1910 if_ctx_t ctx = txq->ift_ctx;
1911 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1912 if_shared_ctx_t sctx = ctx->ifc_sctx;
1913 iflib_dma_info_t di;
1916 /* Set number of descriptors available */
1917 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1918 /* XXX make configurable */
1919 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1922 txq->ift_cidx_processed = 0;
1923 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1924 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1926 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1927 bzero((void *)di->idi_vaddr, di->idi_size);
1929 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1930 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1931 bus_dmamap_sync(di->idi_tag, di->idi_map,
1932 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1936 /*********************************************************************
1938 * Allocate DMA resources for RX buffers as well as memory for the RX
1939 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1940 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1941 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1942 * Since we use use one entry in iflib_sw_rx_desc_array per received
1943 * packet, the maximum number of entries we'll need is equal to the
1944 * number of hardware receive descriptors that we've allocated.
1946 **********************************************************************/
1948 iflib_rxsd_alloc(iflib_rxq_t rxq)
1950 if_ctx_t ctx = rxq->ifr_ctx;
1951 if_shared_ctx_t sctx = ctx->ifc_sctx;
1952 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1953 device_t dev = ctx->ifc_dev;
1958 MPASS(scctx->isc_nrxd[0] > 0);
1959 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1961 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1964 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1965 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1966 /* Set up DMA tag for RX buffers. */
1967 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1968 1, 0, /* alignment, bounds */
1969 lowaddr, /* lowaddr */
1970 BUS_SPACE_MAXADDR, /* highaddr */
1971 NULL, NULL, /* filter, filterarg */
1972 sctx->isc_rx_maxsize, /* maxsize */
1973 sctx->isc_rx_nsegments, /* nsegments */
1974 sctx->isc_rx_maxsegsize, /* maxsegsize */
1976 NULL, /* lockfunc */
1981 "Unable to allocate RX DMA tag: %d\n", err);
1985 /* Allocate memory for the RX mbuf map. */
1986 if (!(fl->ifl_sds.ifsd_m =
1987 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1988 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1990 "Unable to allocate RX mbuf map memory\n");
1995 /* Allocate memory for the direct RX cluster pointer map. */
1996 if (!(fl->ifl_sds.ifsd_cl =
1997 (caddr_t *) malloc(sizeof(caddr_t) *
1998 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2000 "Unable to allocate RX cluster map memory\n");
2005 /* Allocate memory for the RX cluster bus address map. */
2006 if (!(fl->ifl_sds.ifsd_ba =
2007 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
2008 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2010 "Unable to allocate RX bus address map memory\n");
2016 * Create the DMA maps for RX buffers.
2018 if (!(fl->ifl_sds.ifsd_map =
2019 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2021 "Unable to allocate RX buffer DMA map memory\n");
2025 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
2026 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
2027 &fl->ifl_sds.ifsd_map[i]);
2029 device_printf(dev, "Unable to create RX buffer DMA map\n");
2037 iflib_rx_structures_free(ctx);
2042 * Internal service routines
2045 struct rxq_refill_cb_arg {
2047 bus_dma_segment_t seg;
2052 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2054 struct rxq_refill_cb_arg *cb_arg = arg;
2056 cb_arg->error = error;
2057 cb_arg->seg = segs[0];
2058 cb_arg->nseg = nseg;
2062 * iflib_fl_refill - refill an rxq free-buffer list
2063 * @ctx: the iflib context
2064 * @fl: the free list to refill
2065 * @count: the number of new buffers to allocate
2067 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2068 * The caller must assure that @count does not exceed the queue's capacity
2069 * minus one (since we always leave a descriptor unavailable).
2072 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2074 struct if_rxd_update iru;
2075 struct rxq_refill_cb_arg cb_arg;
2079 bus_dmamap_t *sd_map;
2080 bus_addr_t bus_addr, *sd_ba;
2081 int err, frag_idx, i, idx, n, pidx;
2084 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2086 sd_m = fl->ifl_sds.ifsd_m;
2087 sd_map = fl->ifl_sds.ifsd_map;
2088 sd_cl = fl->ifl_sds.ifsd_cl;
2089 sd_ba = fl->ifl_sds.ifsd_ba;
2090 pidx = fl->ifl_pidx;
2092 frag_idx = fl->ifl_fragidx;
2093 credits = fl->ifl_credits;
2098 MPASS(credits + n <= fl->ifl_size);
2100 if (pidx < fl->ifl_cidx)
2101 MPASS(pidx + n <= fl->ifl_cidx);
2102 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2103 MPASS(fl->ifl_gen == 0);
2104 if (pidx > fl->ifl_cidx)
2105 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2107 DBG_COUNTER_INC(fl_refills);
2109 DBG_COUNTER_INC(fl_refills_large);
2110 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2113 * We allocate an uninitialized mbuf + cluster, mbuf is
2114 * initialized after rx.
2116 * If the cluster is still set then we know a minimum sized
2117 * packet was received
2119 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2122 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2123 MPASS(frag_idx >= 0);
2124 if ((cl = sd_cl[frag_idx]) == NULL) {
2125 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2126 if (__predict_false(cl == NULL))
2130 MPASS(sd_map != NULL);
2131 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2132 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2134 if (__predict_false(err != 0 || cb_arg.error)) {
2135 uma_zfree(fl->ifl_zone, cl);
2139 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2140 sd_cl[frag_idx] = cl;
2142 fl->ifl_cl_enqueued++;
2145 bus_addr = sd_ba[frag_idx];
2147 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2148 BUS_DMASYNC_PREREAD);
2150 if (sd_m[frag_idx] == NULL) {
2151 m = m_gethdr_raw(M_NOWAIT, 0);
2152 if (__predict_false(m == NULL))
2156 bit_set(fl->ifl_rx_bitmap, frag_idx);
2158 fl->ifl_m_enqueued++;
2161 DBG_COUNTER_INC(rx_allocs);
2162 fl->ifl_rxd_idxs[i] = frag_idx;
2163 fl->ifl_bus_addrs[i] = bus_addr;
2166 MPASS(credits <= fl->ifl_size);
2167 if (++idx == fl->ifl_size) {
2173 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2174 iru.iru_pidx = pidx;
2176 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2178 fl->ifl_credits = credits;
2184 if (n < count - 1) {
2186 iru.iru_pidx = pidx;
2188 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2190 fl->ifl_credits = credits;
2192 DBG_COUNTER_INC(rxd_flush);
2193 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2194 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2195 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2196 fl->ifl_id, fl->ifl_pidx);
2197 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2198 fl->ifl_fragidx = frag_idx + 1;
2199 if (fl->ifl_fragidx == fl->ifl_size)
2200 fl->ifl_fragidx = 0;
2202 fl->ifl_fragidx = frag_idx;
2206 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2209 static inline uint8_t
2210 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2213 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2214 * This is important as it confuses most NICs. For instance,
2215 * Intel NICs have (per receive ring) RDH and RDT registers, where
2216 * RDH points to the next receive descriptor to be used by the NIC,
2217 * and RDT for the next receive descriptor to be published by the
2218 * driver to the NIC (RDT - 1 is thus the last valid one).
2219 * The condition RDH == RDT means no descriptors are available to
2220 * the NIC, and thus it would be ambiguous if it also meant that
2221 * all the descriptors are available to the NIC.
2223 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2225 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2228 MPASS(fl->ifl_credits <= fl->ifl_size);
2229 MPASS(reclaimable == delta);
2231 if (reclaimable > 0)
2232 return (iflib_fl_refill(ctx, fl, reclaimable));
2237 iflib_in_detach(if_ctx_t ctx)
2242 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2248 iflib_fl_bufs_free(iflib_fl_t fl)
2250 iflib_dma_info_t idi = fl->ifl_ifdi;
2251 bus_dmamap_t sd_map;
2254 for (i = 0; i < fl->ifl_size; i++) {
2255 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2256 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2258 if (*sd_cl != NULL) {
2259 sd_map = fl->ifl_sds.ifsd_map[i];
2260 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2261 BUS_DMASYNC_POSTREAD);
2262 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2263 uma_zfree(fl->ifl_zone, *sd_cl);
2265 if (*sd_m != NULL) {
2266 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2271 MPASS(*sd_m == NULL);
2274 fl->ifl_m_dequeued++;
2275 fl->ifl_cl_dequeued++;
2279 for (i = 0; i < fl->ifl_size; i++) {
2280 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2281 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2285 * Reset free list values
2287 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2288 bzero(idi->idi_vaddr, idi->idi_size);
2291 /*********************************************************************
2293 * Initialize a free list and its buffers.
2295 **********************************************************************/
2297 iflib_fl_setup(iflib_fl_t fl)
2299 iflib_rxq_t rxq = fl->ifl_rxq;
2300 if_ctx_t ctx = rxq->ifr_ctx;
2301 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2304 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2306 ** Free current RX buffer structs and their mbufs
2308 iflib_fl_bufs_free(fl);
2309 /* Now replenish the mbufs */
2310 MPASS(fl->ifl_credits == 0);
2311 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2312 if (scctx->isc_rxd_buf_size[qidx] != 0)
2313 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2315 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2317 * ifl_buf_size may be a driver-supplied value, so pull it up
2318 * to the selected mbuf size.
2320 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2321 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2322 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2323 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2324 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2327 * Avoid pre-allocating zillions of clusters to an idle card
2328 * potentially speeding up attach. In any case make sure
2329 * to leave a descriptor unavailable. See the comment in
2330 * iflib_fl_refill_all().
2332 MPASS(fl->ifl_size > 0);
2333 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2334 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2340 MPASS(fl->ifl_ifdi != NULL);
2341 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2342 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2346 /*********************************************************************
2348 * Free receive ring data structures
2350 **********************************************************************/
2352 iflib_rx_sds_free(iflib_rxq_t rxq)
2357 if (rxq->ifr_fl != NULL) {
2358 for (i = 0; i < rxq->ifr_nfl; i++) {
2359 fl = &rxq->ifr_fl[i];
2360 if (fl->ifl_buf_tag != NULL) {
2361 if (fl->ifl_sds.ifsd_map != NULL) {
2362 for (j = 0; j < fl->ifl_size; j++) {
2365 fl->ifl_sds.ifsd_map[j],
2366 BUS_DMASYNC_POSTREAD);
2369 fl->ifl_sds.ifsd_map[j]);
2372 fl->ifl_sds.ifsd_map[j]);
2375 bus_dma_tag_destroy(fl->ifl_buf_tag);
2376 fl->ifl_buf_tag = NULL;
2378 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2379 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2380 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2381 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2382 free(fl->ifl_rx_bitmap, M_IFLIB);
2383 fl->ifl_sds.ifsd_m = NULL;
2384 fl->ifl_sds.ifsd_cl = NULL;
2385 fl->ifl_sds.ifsd_ba = NULL;
2386 fl->ifl_sds.ifsd_map = NULL;
2387 fl->ifl_rx_bitmap = NULL;
2389 free(rxq->ifr_fl, M_IFLIB);
2391 free(rxq->ifr_ifdi, M_IFLIB);
2392 rxq->ifr_ifdi = NULL;
2393 rxq->ifr_cq_cidx = 0;
2401 iflib_timer(void *arg)
2403 iflib_txq_t txq = arg;
2404 if_ctx_t ctx = txq->ift_ctx;
2405 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2406 uint64_t this_tick = ticks;
2408 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2412 ** Check on the state of the TX queue(s), this
2413 ** can be done without the lock because its RO
2414 ** and the HUNG state will be static if set.
2416 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2417 txq->ift_last_timer_tick = this_tick;
2418 IFDI_TIMER(ctx, txq->ift_id);
2419 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2420 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2421 (sctx->isc_pause_frames == 0)))
2424 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2425 ifmp_ring_is_stalled(txq->ift_br)) {
2426 KASSERT(ctx->ifc_link_state == LINK_STATE_UP,
2427 ("queue can't be marked as hung if interface is down"));
2428 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2430 txq->ift_cleaned_prev = txq->ift_cleaned;
2432 /* handle any laggards */
2433 if (txq->ift_db_pending)
2434 GROUPTASK_ENQUEUE(&txq->ift_task);
2436 sctx->isc_pause_frames = 0;
2437 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2438 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2439 txq, txq->ift_timer.c_cpu);
2443 device_printf(ctx->ifc_dev,
2444 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2445 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2447 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2448 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2449 iflib_admin_intr_deferred(ctx);
2454 iflib_get_mbuf_size_for(unsigned int size)
2457 if (size <= MCLBYTES)
2460 return (MJUMPAGESIZE);
2464 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2466 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2469 * XXX don't set the max_frame_size to larger
2470 * than the hardware can handle
2472 ctx->ifc_rx_mbuf_sz =
2473 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2477 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2480 return (ctx->ifc_rx_mbuf_sz);
2484 iflib_init_locked(if_ctx_t ctx)
2486 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2487 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2488 if_t ifp = ctx->ifc_ifp;
2492 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2494 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2495 IFDI_INTR_DISABLE(ctx);
2498 * See iflib_stop(). Useful in case iflib_init_locked() is
2499 * called without first calling iflib_stop().
2501 netmap_disable_all_rings(ifp);
2503 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2504 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2505 /* Set hardware offload abilities */
2506 if_clearhwassist(ifp);
2507 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2508 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2509 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2510 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2511 if (if_getcapenable(ifp) & IFCAP_TSO4)
2512 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2513 if (if_getcapenable(ifp) & IFCAP_TSO6)
2514 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2516 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2518 callout_stop(&txq->ift_timer);
2520 callout_stop(&txq->ift_netmap_timer);
2521 #endif /* DEV_NETMAP */
2522 CALLOUT_UNLOCK(txq);
2523 (void)iflib_netmap_txq_init(ctx, txq);
2527 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2528 * that drivers can use the value when setting up the hardware receive
2531 iflib_calc_rx_mbuf_sz(ctx);
2534 i = if_getdrvflags(ifp);
2537 MPASS(if_getdrvflags(ifp) == i);
2538 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2539 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2540 /* This rxq is in netmap mode. Skip normal init. */
2543 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2544 if (iflib_fl_setup(fl)) {
2545 device_printf(ctx->ifc_dev,
2546 "setting up free list %d failed - "
2547 "check cluster settings\n", j);
2553 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2554 IFDI_INTR_ENABLE(ctx);
2555 txq = ctx->ifc_txqs;
2556 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2557 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2558 txq->ift_timer.c_cpu);
2560 /* Re-enable txsync/rxsync. */
2561 netmap_enable_all_rings(ifp);
2565 iflib_media_change(if_t ifp)
2567 if_ctx_t ctx = if_getsoftc(ifp);
2571 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2572 iflib_if_init_locked(ctx);
2578 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2580 if_ctx_t ctx = if_getsoftc(ifp);
2583 IFDI_UPDATE_ADMIN_STATUS(ctx);
2584 IFDI_MEDIA_STATUS(ctx, ifmr);
2589 iflib_stop(if_ctx_t ctx)
2591 iflib_txq_t txq = ctx->ifc_txqs;
2592 iflib_rxq_t rxq = ctx->ifc_rxqs;
2593 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2594 if_shared_ctx_t sctx = ctx->ifc_sctx;
2595 iflib_dma_info_t di;
2599 /* Tell the stack that the interface is no longer active */
2600 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2602 IFDI_INTR_DISABLE(ctx);
2608 * Stop any pending txsync/rxsync and prevent new ones
2609 * form starting. Processes blocked in poll() will get
2612 netmap_disable_all_rings(ctx->ifc_ifp);
2614 iflib_debug_reset();
2615 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2616 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2617 /* make sure all transmitters have completed before proceeding XXX */
2620 callout_stop(&txq->ift_timer);
2622 callout_stop(&txq->ift_netmap_timer);
2623 #endif /* DEV_NETMAP */
2624 CALLOUT_UNLOCK(txq);
2626 /* clean any enqueued buffers */
2627 iflib_ifmp_purge(txq);
2628 /* Free any existing tx buffers. */
2629 for (j = 0; j < txq->ift_size; j++) {
2630 iflib_txsd_free(ctx, txq, j);
2632 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2633 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0;
2634 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES)
2635 txq->ift_cidx = txq->ift_pidx;
2637 txq->ift_cidx = txq->ift_pidx = 0;
2639 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2640 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2641 txq->ift_pullups = 0;
2642 ifmp_ring_reset_stats(txq->ift_br);
2643 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2644 bzero((void *)di->idi_vaddr, di->idi_size);
2646 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2647 if (rxq->ifr_task.gt_taskqueue != NULL)
2648 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue,
2649 &rxq->ifr_task.gt_task);
2651 rxq->ifr_cq_cidx = 0;
2652 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2653 bzero((void *)di->idi_vaddr, di->idi_size);
2654 /* also resets the free lists pidx/cidx */
2655 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2656 iflib_fl_bufs_free(fl);
2660 static inline caddr_t
2661 calc_next_rxd(iflib_fl_t fl, int cidx)
2665 caddr_t start, end, cur, next;
2667 nrxd = fl->ifl_size;
2668 size = fl->ifl_rxd_size;
2669 start = fl->ifl_ifdi->idi_vaddr;
2671 if (__predict_false(size == 0))
2673 cur = start + size*cidx;
2674 end = start + size*nrxd;
2675 next = CACHE_PTR_NEXT(cur);
2676 return (next < end ? next : start);
2680 prefetch_pkts(iflib_fl_t fl, int cidx)
2683 int nrxd = fl->ifl_size;
2686 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2687 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2688 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2689 next_rxd = calc_next_rxd(fl, cidx);
2691 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2692 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2693 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2694 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2695 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2696 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2697 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2698 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2701 static struct mbuf *
2702 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2703 int *pf_rv, if_rxd_info_t ri)
2709 int flid, cidx, len, next;
2712 flid = irf->irf_flid;
2713 cidx = irf->irf_idx;
2714 fl = &rxq->ifr_fl[flid];
2716 m = fl->ifl_sds.ifsd_m[cidx];
2717 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2720 fl->ifl_m_dequeued++;
2722 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2723 prefetch_pkts(fl, cidx);
2724 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2725 prefetch(&fl->ifl_sds.ifsd_map[next]);
2726 map = fl->ifl_sds.ifsd_map[cidx];
2728 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2730 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2731 irf->irf_len != 0) {
2732 payload = *sd->ifsd_cl;
2733 payload += ri->iri_pad;
2734 len = ri->iri_len - ri->iri_pad;
2735 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m);
2740 * The filter ate it. Everything is recycled.
2745 case PFIL_REALLOCED:
2747 * The filter copied it. Everything is recycled.
2748 * 'm' points at new mbuf.
2754 * Filter said it was OK, so receive like
2757 fl->ifl_sds.ifsd_m[cidx] = NULL;
2763 fl->ifl_sds.ifsd_m[cidx] = NULL;
2768 if (unload && irf->irf_len != 0)
2769 bus_dmamap_unload(fl->ifl_buf_tag, map);
2770 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2771 if (__predict_false(fl->ifl_cidx == 0))
2773 bit_clear(fl->ifl_rx_bitmap, cidx);
2777 static struct mbuf *
2778 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2780 struct mbuf *m, *mh, *mt;
2782 int *pf_rv_ptr, flags, i, padlen;
2791 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2794 MPASS(*sd->ifsd_cl != NULL);
2797 * Exclude zero-length frags & frags from
2798 * packets the filter has consumed or dropped
2800 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2801 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2803 /* everything saved here */
2808 /* XXX we can save the cluster here, but not the mbuf */
2809 m_init(m, M_NOWAIT, MT_DATA, 0);
2814 flags = M_PKTHDR|M_EXT;
2816 padlen = ri->iri_pad;
2821 /* assuming padding is only on the first fragment */
2825 *sd->ifsd_cl = NULL;
2827 /* Can these two be made one ? */
2828 m_init(m, M_NOWAIT, MT_DATA, flags);
2829 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2831 * These must follow m_init and m_cljset
2833 m->m_data += padlen;
2834 ri->iri_len -= padlen;
2835 m->m_len = ri->iri_frags[i].irf_len;
2836 } while (++i < ri->iri_nfrags);
2842 * Process one software descriptor
2844 static struct mbuf *
2845 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2851 /* should I merge this back in now that the two paths are basically duplicated? */
2852 if (ri->iri_nfrags == 1 &&
2853 ri->iri_frags[0].irf_len != 0 &&
2854 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2855 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2857 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2859 if (pf_rv == PFIL_PASS) {
2860 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2861 #ifndef __NO_STRICT_ALIGNMENT
2862 if (!IP_ALIGNED(m) && ri->iri_pad == 0)
2865 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2866 m->m_len = ri->iri_frags[0].irf_len;
2867 m->m_data += ri->iri_pad;
2868 ri->iri_len -= ri->iri_pad;
2871 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2874 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2877 m->m_pkthdr.len = ri->iri_len;
2878 m->m_pkthdr.rcvif = ri->iri_ifp;
2879 m->m_flags |= ri->iri_flags;
2880 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2881 m->m_pkthdr.flowid = ri->iri_flowid;
2882 M_HASHTYPE_SET(m, ri->iri_rsstype);
2883 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2884 m->m_pkthdr.csum_data = ri->iri_csum_data;
2888 #if defined(INET6) || defined(INET)
2890 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2892 CURVNET_SET(lc->ifp->if_vnet); /* XXX - DRVAPI */
2894 *v6 = V_ip6_forwarding;
2897 *v4 = V_ipforwarding;
2903 * Returns true if it's possible this packet could be LROed.
2904 * if it returns false, it is guaranteed that tcp_lro_rx()
2905 * would not return zero.
2908 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2910 struct ether_header *eh;
2912 eh = mtod(m, struct ether_header *);
2913 switch (eh->ether_type) {
2915 case htons(ETHERTYPE_IPV6):
2916 return (!v6_forwarding);
2919 case htons(ETHERTYPE_IP):
2920 return (!v4_forwarding);
2928 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2934 _task_fn_rx_watchdog(void *context)
2936 iflib_rxq_t rxq = context;
2938 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2942 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2945 if_ctx_t ctx = rxq->ifr_ctx;
2946 if_shared_ctx_t sctx = ctx->ifc_sctx;
2947 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2950 struct if_rxd_info ri;
2951 int err, budget_left, rx_bytes, rx_pkts;
2954 bool v4_forwarding, v6_forwarding, lro_possible;
2958 * XXX early demux data packets so that if_input processing only handles
2959 * acks in interrupt context
2961 struct mbuf *m, *mh, *mt, *mf;
2965 lro_possible = v4_forwarding = v6_forwarding = false;
2969 rx_pkts = rx_bytes = 0;
2970 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2971 cidxp = &rxq->ifr_cq_cidx;
2973 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2974 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2975 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2976 retval |= iflib_fl_refill_all(ctx, fl);
2977 DBG_COUNTER_INC(rx_unavail);
2981 /* pfil needs the vnet to be set */
2982 CURVNET_SET_QUIET(ifp->if_vnet); /* XXX - DRVAPI */
2983 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2984 if (__predict_false(!CTX_ACTIVE(ctx))) {
2985 DBG_COUNTER_INC(rx_ctx_inactive);
2989 * Reset client set fields to their default values
2992 ri.iri_qsidx = rxq->ifr_id;
2993 ri.iri_cidx = *cidxp;
2995 ri.iri_frags = rxq->ifr_frags;
2996 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
3001 rx_bytes += ri.iri_len;
3002 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
3003 *cidxp = ri.iri_cidx;
3004 /* Update our consumer index */
3005 /* XXX NB: shurd - check if this is still safe */
3006 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
3007 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
3008 /* was this only a completion queue message? */
3009 if (__predict_false(ri.iri_nfrags == 0))
3012 MPASS(ri.iri_nfrags != 0);
3013 MPASS(ri.iri_len != 0);
3015 /* will advance the cidx on the corresponding free lists */
3016 m = iflib_rxd_pkt_get(rxq, &ri);
3019 if (avail == 0 && budget_left)
3020 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
3022 if (__predict_false(m == NULL))
3025 /* imm_pkt: -- cxgb */
3034 /* make sure that we can refill faster than drain */
3035 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3036 retval |= iflib_fl_refill_all(ctx, fl);
3038 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
3040 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
3042 while (mh != NULL) {
3045 m->m_nextpkt = NULL;
3046 #ifndef __NO_STRICT_ALIGNMENT
3047 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
3050 #if defined(INET6) || defined(INET)
3052 if (!lro_possible) {
3053 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
3054 if (lro_possible && mf != NULL) {
3056 DBG_COUNTER_INC(rx_if_input);
3060 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
3061 (CSUM_L4_CALC|CSUM_L4_VALID)) {
3062 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
3069 DBG_COUNTER_INC(rx_if_input);
3081 DBG_COUNTER_INC(rx_if_input);
3084 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3085 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3088 * Flush any outstanding LRO work
3090 #if defined(INET6) || defined(INET)
3091 tcp_lro_flush_all(&rxq->ifr_lc);
3093 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3094 retval |= IFLIB_RXEOF_MORE;
3098 ctx->ifc_flags |= IFC_DO_RESET;
3099 iflib_admin_intr_deferred(ctx);
3104 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
3105 static inline qidx_t
3106 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3108 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3109 qidx_t minthresh = txq->ift_size / 8;
3110 if (in_use > 4*minthresh)
3111 return (notify_count);
3112 if (in_use > 2*minthresh)
3113 return (notify_count >> 1);
3114 if (in_use > minthresh)
3115 return (notify_count >> 3);
3119 static inline qidx_t
3120 txq_max_rs_deferred(iflib_txq_t txq)
3122 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3123 qidx_t minthresh = txq->ift_size / 8;
3124 if (txq->ift_in_use > 4*minthresh)
3125 return (notify_count);
3126 if (txq->ift_in_use > 2*minthresh)
3127 return (notify_count >> 1);
3128 if (txq->ift_in_use > minthresh)
3129 return (notify_count >> 2);
3133 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3134 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3136 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3137 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3138 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3140 /* forward compatibility for cxgb */
3141 #define FIRST_QSET(ctx) 0
3142 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3143 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3144 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3145 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3147 /* XXX we should be setting this to something other than zero */
3148 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
3149 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3150 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3153 iflib_txd_db_check(iflib_txq_t txq, int ring)
3155 if_ctx_t ctx = txq->ift_ctx;
3158 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3160 /* force || threshold exceeded || at the edge of the ring */
3161 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) {
3164 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3165 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3166 * producer index explicitly (INTC).
3168 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3169 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3170 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3171 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3174 * Absent bugs there are zero packets pending so reset pending counts to zero.
3176 txq->ift_db_pending = txq->ift_npending = 0;
3184 print_pkt(if_pkt_info_t pi)
3186 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3187 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3188 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3189 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3190 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3191 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3195 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3196 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3197 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3198 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3201 * Parses out ethernet header information in the given mbuf.
3202 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length)
3204 * This will account for the VLAN header if present.
3206 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those
3210 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3212 struct ether_vlan_header *eh;
3216 if (__predict_false(m->m_len < sizeof(*eh))) {
3218 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3221 eh = mtod(m, struct ether_vlan_header *);
3222 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3223 pi->ipi_etype = ntohs(eh->evl_proto);
3224 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3226 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3227 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3235 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi.
3236 * Currently this information includes: IP ToS value, IP header version/presence
3238 * This is missing some checks and doesn't edit the packet content as it goes,
3239 * unlike iflib_parse_header(), in order to keep the amount of code here minimal.
3242 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3249 if (!M_WRITABLE(m)) {
3250 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3254 DBG_COUNTER_INC(tx_frees);
3259 /* Fills out pi->ipi_etype */
3260 err = iflib_parse_ether_header(pi, mp, pullups);
3265 switch (pi->ipi_etype) {
3270 struct ip *ip = NULL;
3273 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip));
3274 if (__predict_false(m->m_len < miniplen)) {
3276 * Check for common case where the first mbuf only contains
3277 * the Ethernet header
3279 if (m->m_len == pi->ipi_ehdrlen) {
3282 /* If next mbuf contains at least the minimal IP header, then stop */
3283 if (n->m_len >= sizeof(*ip)) {
3284 ip = (struct ip *)n->m_data;
3287 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3289 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3293 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3295 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3298 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3301 /* Have the IPv4 header w/ no options here */
3302 pi->ipi_ip_hlen = ip->ip_hl << 2;
3303 pi->ipi_ipproto = ip->ip_p;
3304 pi->ipi_ip_tos = ip->ip_tos;
3305 pi->ipi_flags |= IPI_TX_IPV4;
3311 case ETHERTYPE_IPV6:
3313 struct ip6_hdr *ip6;
3315 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3317 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3320 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3322 /* Have the IPv6 fixed header here */
3323 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3324 pi->ipi_ipproto = ip6->ip6_nxt;
3325 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3326 pi->ipi_flags |= IPI_TX_IPV6;
3332 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3333 pi->ipi_ip_hlen = 0;
3343 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3345 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3350 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3351 M_WRITABLE(m) == 0) {
3352 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3356 DBG_COUNTER_INC(tx_frees);
3361 /* Fills out pi->ipi_etype */
3362 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups);
3363 if (__predict_false(err))
3367 switch (pi->ipi_etype) {
3372 struct ip *ip = NULL;
3373 struct tcphdr *th = NULL;
3376 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3377 if (__predict_false(m->m_len < minthlen)) {
3379 * if this code bloat is causing too much of a hit
3380 * move it to a separate function and mark it noinline
3382 if (m->m_len == pi->ipi_ehdrlen) {
3385 if (n->m_len >= sizeof(*ip)) {
3386 ip = (struct ip *)n->m_data;
3387 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3388 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3391 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3393 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3397 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3399 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3400 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3401 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3404 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3405 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3406 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3408 pi->ipi_ip_hlen = ip->ip_hl << 2;
3409 pi->ipi_ipproto = ip->ip_p;
3410 pi->ipi_ip_tos = ip->ip_tos;
3411 pi->ipi_flags |= IPI_TX_IPV4;
3413 /* TCP checksum offload may require TCP header length */
3414 if (IS_TX_OFFLOAD4(pi)) {
3415 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3416 if (__predict_false(th == NULL)) {
3418 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3420 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3422 pi->ipi_tcp_hflags = th->th_flags;
3423 pi->ipi_tcp_hlen = th->th_off << 2;
3424 pi->ipi_tcp_seq = th->th_seq;
3427 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3430 * TSO always requires hardware checksum offload.
3432 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3433 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3434 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3435 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3436 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3438 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3442 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3449 case ETHERTYPE_IPV6:
3451 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3453 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3455 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3457 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3460 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3462 /* XXX-BZ this will go badly in case of ext hdrs. */
3463 pi->ipi_ipproto = ip6->ip6_nxt;
3464 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3465 pi->ipi_flags |= IPI_TX_IPV6;
3467 /* TCP checksum offload may require TCP header length */
3468 if (IS_TX_OFFLOAD6(pi)) {
3469 if (pi->ipi_ipproto == IPPROTO_TCP) {
3470 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3472 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3475 pi->ipi_tcp_hflags = th->th_flags;
3476 pi->ipi_tcp_hlen = th->th_off << 2;
3477 pi->ipi_tcp_seq = th->th_seq;
3480 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3483 * TSO always requires hardware checksum offload.
3485 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3486 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3487 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3494 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3495 pi->ipi_ip_hlen = 0;
3504 * If dodgy hardware rejects the scatter gather chain we've handed it
3505 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3508 static __noinline struct mbuf *
3509 iflib_remove_mbuf(iflib_txq_t txq)
3512 struct mbuf *m, **ifsd_m;
3514 ifsd_m = txq->ift_sds.ifsd_m;
3515 ntxd = txq->ift_size;
3516 pidx = txq->ift_pidx & (ntxd - 1);
3517 ifsd_m = txq->ift_sds.ifsd_m;
3519 ifsd_m[pidx] = NULL;
3520 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3521 if (txq->ift_sds.ifsd_tso_map != NULL)
3522 bus_dmamap_unload(txq->ift_tso_buf_tag,
3523 txq->ift_sds.ifsd_tso_map[pidx]);
3525 txq->ift_dequeued++;
3530 static inline caddr_t
3531 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3535 caddr_t start, end, cur, next;
3537 ntxd = txq->ift_size;
3538 size = txq->ift_txd_size[qid];
3539 start = txq->ift_ifdi[qid].idi_vaddr;
3541 if (__predict_false(size == 0))
3543 cur = start + size*cidx;
3544 end = start + size*ntxd;
3545 next = CACHE_PTR_NEXT(cur);
3546 return (next < end ? next : start);
3550 * Pad an mbuf to ensure a minimum ethernet frame size.
3551 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3553 static __noinline int
3554 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3557 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3558 * and ARP message is the smallest common payload I can think of
3560 static char pad[18]; /* just zeros */
3562 struct mbuf *new_head;
3564 if (!M_WRITABLE(*m_head)) {
3565 new_head = m_dup(*m_head, M_NOWAIT);
3566 if (new_head == NULL) {
3568 device_printf(dev, "cannot pad short frame, m_dup() failed");
3569 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3570 DBG_COUNTER_INC(tx_frees);
3577 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3578 n > 0; n -= sizeof(pad))
3579 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3584 device_printf(dev, "cannot pad short frame\n");
3585 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3586 DBG_COUNTER_INC(tx_frees);
3594 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3597 if_shared_ctx_t sctx;
3598 if_softc_ctx_t scctx;
3599 bus_dma_tag_t buf_tag;
3600 bus_dma_segment_t *segs;
3601 struct mbuf *m_head, **ifsd_m;
3604 struct if_pkt_info pi;
3606 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3609 sctx = ctx->ifc_sctx;
3610 scctx = &ctx->ifc_softc_ctx;
3611 segs = txq->ift_segs;
3612 ntxd = txq->ift_size;
3617 * If we're doing TSO the next descriptor to clean may be quite far ahead
3619 cidx = txq->ift_cidx;
3620 pidx = txq->ift_pidx;
3621 if (ctx->ifc_flags & IFC_PREFETCH) {
3622 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3623 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3624 next_txd = calc_next_txd(txq, cidx, 0);
3628 /* prefetch the next cache line of mbuf pointers and flags */
3629 prefetch(&txq->ift_sds.ifsd_m[next]);
3630 prefetch(&txq->ift_sds.ifsd_map[next]);
3631 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3633 map = txq->ift_sds.ifsd_map[pidx];
3634 ifsd_m = txq->ift_sds.ifsd_m;
3636 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3637 buf_tag = txq->ift_tso_buf_tag;
3638 max_segs = scctx->isc_tx_tso_segments_max;
3639 map = txq->ift_sds.ifsd_tso_map[pidx];
3640 MPASS(buf_tag != NULL);
3641 MPASS(max_segs > 0);
3643 buf_tag = txq->ift_buf_tag;
3644 max_segs = scctx->isc_tx_nsegments;
3645 map = txq->ift_sds.ifsd_map[pidx];
3647 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3648 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3649 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3651 DBG_COUNTER_INC(encap_txd_encap_fail);
3658 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3660 pi.ipi_qsidx = txq->ift_id;
3661 pi.ipi_len = m_head->m_pkthdr.len;
3662 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3663 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3665 /* deliberate bitwise OR to make one condition */
3666 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3667 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3668 DBG_COUNTER_INC(encap_txd_encap_fail);
3675 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3678 if (__predict_false(err)) {
3681 /* try collapse once and defrag once */
3683 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3684 /* try defrag if collapsing fails */
3689 txq->ift_mbuf_defrag++;
3690 m_head = m_defrag(*m_headp, M_NOWAIT);
3693 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3694 * failed to map an mbuf that was run through m_defrag
3697 if (__predict_false(m_head == NULL || remap > 1))
3704 txq->ift_no_tx_dma_setup++;
3707 txq->ift_no_tx_dma_setup++;
3709 DBG_COUNTER_INC(tx_frees);
3713 txq->ift_map_failed++;
3714 DBG_COUNTER_INC(encap_load_mbuf_fail);
3715 DBG_COUNTER_INC(encap_txd_encap_fail);
3718 ifsd_m[pidx] = m_head;
3720 * XXX assumes a 1 to 1 relationship between segments and
3721 * descriptors - this does not hold true on all drivers, e.g.
3724 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3725 txq->ift_no_desc_avail++;
3726 bus_dmamap_unload(buf_tag, map);
3727 DBG_COUNTER_INC(encap_txq_avail_fail);
3728 DBG_COUNTER_INC(encap_txd_encap_fail);
3729 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3730 GROUPTASK_ENQUEUE(&txq->ift_task);
3734 * On Intel cards we can greatly reduce the number of TX interrupts
3735 * we see by only setting report status on every Nth descriptor.
3736 * However, this also means that the driver will need to keep track
3737 * of the descriptors that RS was set on to check them for the DD bit.
3739 txq->ift_rs_pending += nsegs + 1;
3740 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3741 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3742 pi.ipi_flags |= IPI_TX_INTR;
3743 txq->ift_rs_pending = 0;
3747 pi.ipi_nsegs = nsegs;
3749 MPASS(pidx >= 0 && pidx < txq->ift_size);
3753 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3754 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3755 DBG_COUNTER_INC(tx_encap);
3756 MPASS(pi.ipi_new_pidx < txq->ift_size);
3758 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3759 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3760 ndesc += txq->ift_size;
3764 * drivers can need as many as
3767 MPASS(ndesc <= pi.ipi_nsegs + 2);
3768 MPASS(pi.ipi_new_pidx != pidx);
3770 txq->ift_in_use += ndesc;
3771 txq->ift_db_pending += ndesc;
3774 * We update the last software descriptor again here because there may
3775 * be a sentinel and/or there may be more mbufs than segments
3777 txq->ift_pidx = pi.ipi_new_pidx;
3778 txq->ift_npending += pi.ipi_ndescs;
3780 *m_headp = m_head = iflib_remove_mbuf(txq);
3782 txq->ift_txd_encap_efbig++;
3791 * err can't possibly be non-zero here, so we don't neet to test it
3792 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3797 txq->ift_mbuf_defrag_failed++;
3798 txq->ift_map_failed++;
3800 DBG_COUNTER_INC(tx_frees);
3802 DBG_COUNTER_INC(encap_txd_encap_fail);
3807 iflib_tx_desc_free(iflib_txq_t txq, int n)
3809 uint32_t qsize, cidx, mask, gen;
3810 struct mbuf *m, **ifsd_m;
3813 cidx = txq->ift_cidx;
3815 qsize = txq->ift_size;
3817 ifsd_m = txq->ift_sds.ifsd_m;
3818 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3822 prefetch(ifsd_m[(cidx + 3) & mask]);
3823 prefetch(ifsd_m[(cidx + 4) & mask]);
3825 if ((m = ifsd_m[cidx]) != NULL) {
3826 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3827 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3828 bus_dmamap_sync(txq->ift_tso_buf_tag,
3829 txq->ift_sds.ifsd_tso_map[cidx],
3830 BUS_DMASYNC_POSTWRITE);
3831 bus_dmamap_unload(txq->ift_tso_buf_tag,
3832 txq->ift_sds.ifsd_tso_map[cidx]);
3834 bus_dmamap_sync(txq->ift_buf_tag,
3835 txq->ift_sds.ifsd_map[cidx],
3836 BUS_DMASYNC_POSTWRITE);
3837 bus_dmamap_unload(txq->ift_buf_tag,
3838 txq->ift_sds.ifsd_map[cidx]);
3840 /* XXX we don't support any drivers that batch packets yet */
3841 MPASS(m->m_nextpkt == NULL);
3843 ifsd_m[cidx] = NULL;
3845 txq->ift_dequeued++;
3847 DBG_COUNTER_INC(tx_frees);
3849 if (__predict_false(++cidx == qsize)) {
3854 txq->ift_cidx = cidx;
3859 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3862 if_ctx_t ctx = txq->ift_ctx;
3864 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3865 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3868 * Need a rate-limiting check so that this isn't called every time
3870 iflib_tx_credits_update(ctx, txq);
3871 reclaim = DESC_RECLAIMABLE(txq);
3873 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3875 if (iflib_verbose_debug) {
3876 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3877 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3883 iflib_tx_desc_free(txq, reclaim);
3884 txq->ift_cleaned += reclaim;
3885 txq->ift_in_use -= reclaim;
3890 static struct mbuf **
3891 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3894 struct mbuf **items;
3897 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3898 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3900 prefetch(items[(cidx + offset) & (size-1)]);
3901 if (remaining > 1) {
3902 prefetch2cachelines(&items[next]);
3903 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3904 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3905 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3907 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3911 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3914 ifmp_ring_check_drainage(txq->ift_br, budget);
3918 iflib_txq_can_drain(struct ifmp_ring *r)
3920 iflib_txq_t txq = r->cookie;
3921 if_ctx_t ctx = txq->ift_ctx;
3923 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3925 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3926 BUS_DMASYNC_POSTREAD);
3927 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3932 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3934 iflib_txq_t txq = r->cookie;
3935 if_ctx_t ctx = txq->ift_ctx;
3936 if_t ifp = ctx->ifc_ifp;
3937 struct mbuf *m, **mp;
3938 int avail, bytes_sent, skipped, count, err, i;
3939 int mcast_sent, pkt_sent, reclaimed;
3940 bool do_prefetch, rang, ring;
3942 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3943 !LINK_ACTIVE(ctx))) {
3944 DBG_COUNTER_INC(txq_drain_notready);
3947 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3948 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3949 avail = IDXDIFF(pidx, cidx, r->size);
3951 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3953 * The driver is unloading so we need to free all pending packets.
3955 DBG_COUNTER_INC(txq_drain_flushing);
3956 for (i = 0; i < avail; i++) {
3957 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3958 m_freem(r->items[(cidx + i) & (r->size-1)]);
3959 r->items[(cidx + i) & (r->size-1)] = NULL;
3964 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3965 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3967 callout_stop(&txq->ift_timer);
3968 CALLOUT_UNLOCK(txq);
3969 DBG_COUNTER_INC(txq_drain_oactive);
3974 * If we've reclaimed any packets this queue cannot be hung.
3977 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3978 skipped = mcast_sent = bytes_sent = pkt_sent = 0;
3979 count = MIN(avail, TX_BATCH_SIZE);
3981 if (iflib_verbose_debug)
3982 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3983 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3985 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3987 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) {
3988 int rem = do_prefetch ? count - i : 0;
3990 mp = _ring_peek_one(r, cidx, i, rem);
3991 MPASS(mp != NULL && *mp != NULL);
3994 * Completion interrupts will use the address of the txq
3995 * as a sentinel to enqueue _something_ in order to acquire
3996 * the lock on the mp_ring (there's no direct lock call).
3997 * We obviously whave to check for these sentinel cases
4000 if (__predict_false(*mp == (struct mbuf *)txq)) {
4004 err = iflib_encap(txq, mp);
4005 if (__predict_false(err)) {
4006 /* no room - bail out */
4010 /* we can't send this packet - skip it */
4015 DBG_COUNTER_INC(tx_sent);
4016 bytes_sent += m->m_pkthdr.len;
4017 mcast_sent += !!(m->m_flags & M_MCAST);
4019 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)))
4021 ETHER_BPF_MTAP(ifp, m);
4022 rang = iflib_txd_db_check(txq, false);
4025 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
4026 ring = rang ? false : (iflib_min_tx_latency | err);
4027 iflib_txd_db_check(txq, ring);
4028 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
4029 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
4031 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
4033 if (iflib_verbose_debug)
4034 printf("consumed=%d\n", skipped + pkt_sent);
4036 return (skipped + pkt_sent);
4040 iflib_txq_drain_always(struct ifmp_ring *r)
4046 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
4054 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
4056 callout_stop(&txq->ift_timer);
4057 CALLOUT_UNLOCK(txq);
4059 avail = IDXDIFF(pidx, cidx, r->size);
4060 for (i = 0; i < avail; i++) {
4061 mp = _ring_peek_one(r, cidx, i, avail - i);
4062 if (__predict_false(*mp == (struct mbuf *)txq))
4065 DBG_COUNTER_INC(tx_frees);
4067 MPASS(ifmp_ring_is_stalled(r) == 0);
4072 iflib_ifmp_purge(iflib_txq_t txq)
4074 struct ifmp_ring *r;
4077 r->drain = iflib_txq_drain_free;
4078 r->can_drain = iflib_txq_drain_always;
4080 ifmp_ring_check_drainage(r, r->size);
4082 r->drain = iflib_txq_drain;
4083 r->can_drain = iflib_txq_can_drain;
4087 _task_fn_tx(void *context)
4089 iflib_txq_t txq = context;
4090 if_ctx_t ctx = txq->ift_ctx;
4091 if_t ifp = ctx->ifc_ifp;
4092 int abdicate = ctx->ifc_sysctl_tx_abdicate;
4094 #ifdef IFLIB_DIAGNOSTICS
4095 txq->ift_cpu_exec_count[curcpu]++;
4097 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4100 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
4101 netmap_tx_irq(ifp, txq->ift_id))
4105 if (ALTQ_IS_ENABLED(&ifp->if_snd)) /* XXX - DRVAPI */
4106 iflib_altq_if_start(ifp);
4108 if (txq->ift_db_pending)
4109 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
4111 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4113 * When abdicating, we always need to check drainage, not just when we don't enqueue
4116 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4120 if (ctx->ifc_flags & IFC_LEGACY)
4121 IFDI_INTR_ENABLE(ctx);
4123 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
4127 _task_fn_rx(void *context)
4129 iflib_rxq_t rxq = context;
4130 if_ctx_t ctx = rxq->ifr_ctx;
4138 #ifdef IFLIB_DIAGNOSTICS
4139 rxq->ifr_cpu_exec_count[curcpu]++;
4141 DBG_COUNTER_INC(task_fn_rxs);
4142 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4145 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
4146 if (nmirq != NM_IRQ_PASS) {
4147 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
4151 budget = ctx->ifc_sysctl_rx_budget;
4153 budget = 16; /* XXX */
4154 more = iflib_rxeof(rxq, budget);
4158 if ((more & IFLIB_RXEOF_MORE) == 0) {
4159 if (ctx->ifc_flags & IFC_LEGACY)
4160 IFDI_INTR_ENABLE(ctx);
4162 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
4163 DBG_COUNTER_INC(rx_intr_enables);
4165 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4168 if (more & IFLIB_RXEOF_MORE)
4169 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4170 else if (more & IFLIB_RXEOF_EMPTY)
4171 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4175 _task_fn_admin(void *context)
4177 if_ctx_t ctx = context;
4178 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4181 bool oactive, running, do_reset, do_watchdog, in_detach;
4184 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4185 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4186 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4187 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4188 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4189 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
4192 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4198 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4200 callout_stop(&txq->ift_timer);
4201 CALLOUT_UNLOCK(txq);
4203 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ)
4204 IFDI_ADMIN_COMPLETION_HANDLE(ctx);
4206 ctx->ifc_watchdog_events++;
4207 IFDI_WATCHDOG_RESET(ctx);
4209 IFDI_UPDATE_ADMIN_STATUS(ctx);
4210 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4211 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4212 txq->ift_timer.c_cpu);
4214 IFDI_LINK_INTR_ENABLE(ctx);
4216 iflib_if_init_locked(ctx);
4219 if (LINK_ACTIVE(ctx) == 0)
4221 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4222 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4226 _task_fn_iov(void *context)
4228 if_ctx_t ctx = context;
4230 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4231 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4235 IFDI_VFLR_HANDLE(ctx);
4240 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4243 if_int_delay_info_t info;
4246 info = (if_int_delay_info_t)arg1;
4247 ctx = info->iidi_ctx;
4248 info->iidi_req = req;
4249 info->iidi_oidp = oidp;
4251 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4256 /*********************************************************************
4260 **********************************************************************/
4263 iflib_if_init_locked(if_ctx_t ctx)
4266 iflib_init_locked(ctx);
4270 iflib_if_init(void *arg)
4275 iflib_if_init_locked(ctx);
4280 iflib_if_transmit(if_t ifp, struct mbuf *m)
4282 if_ctx_t ctx = if_getsoftc(ifp);
4287 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4288 DBG_COUNTER_INC(tx_frees);
4293 MPASS(m->m_nextpkt == NULL);
4294 /* ALTQ-enabled interfaces always use queue 0. */
4296 /* Use driver-supplied queue selection method if it exists */
4297 if (ctx->isc_txq_select_v2) {
4298 struct if_pkt_info pi;
4299 uint64_t early_pullups = 0;
4302 err = iflib_parse_header_partial(&pi, &m, &early_pullups);
4303 if (__predict_false(err != 0)) {
4304 /* Assign pullups for bad pkts to default queue */
4305 ctx->ifc_txqs[0].ift_pullups += early_pullups;
4306 DBG_COUNTER_INC(encap_txd_encap_fail);
4309 /* Let driver make queueing decision */
4310 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi);
4311 ctx->ifc_txqs[qidx].ift_pullups += early_pullups;
4313 /* Backwards compatibility w/ simpler queue select */
4314 else if (ctx->isc_txq_select)
4315 qidx = ctx->isc_txq_select(ctx->ifc_softc, m);
4316 /* If not, use iflib's standard method */
4317 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
4318 qidx = QIDX(ctx, m);
4321 txq = &ctx->ifc_txqs[qidx];
4323 #ifdef DRIVER_BACKPRESSURE
4324 if (txq->ift_closed) {
4326 next = m->m_nextpkt;
4327 m->m_nextpkt = NULL;
4329 DBG_COUNTER_INC(tx_frees);
4341 next = next->m_nextpkt;
4342 } while (next != NULL);
4344 if (count > nitems(marr))
4345 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4346 /* XXX check nextpkt */
4348 /* XXX simplify for now */
4349 DBG_COUNTER_INC(tx_frees);
4352 for (next = m, i = 0; next != NULL; i++) {
4354 next = next->m_nextpkt;
4355 mp[i]->m_nextpkt = NULL;
4358 DBG_COUNTER_INC(tx_seen);
4359 abdicate = ctx->ifc_sysctl_tx_abdicate;
4361 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4364 GROUPTASK_ENQUEUE(&txq->ift_task);
4367 GROUPTASK_ENQUEUE(&txq->ift_task);
4368 /* support forthcoming later */
4369 #ifdef DRIVER_BACKPRESSURE
4370 txq->ift_closed = TRUE;
4372 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4374 DBG_COUNTER_INC(tx_frees);
4382 * The overall approach to integrating iflib with ALTQ is to continue to use
4383 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4384 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4385 * is redundant/unnecessary, but doing so minimizes the amount of
4386 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4387 * redundantly queueing to an intermediate mp_ring is swamped by the
4388 * performance limitations inherent in using ALTQ.
4390 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4391 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4392 * given interface. If ALTQ is enabled for an interface, then all
4393 * transmitted packets for that interface will be submitted to the ALTQ
4394 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4395 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4396 * update stats that the iflib machinery handles, and which is sensitve to
4397 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4398 * will be installed as the start routine for use by ALTQ facilities that
4399 * need to trigger queue drains on a scheduled basis.
4403 iflib_altq_if_start(if_t ifp)
4405 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */
4409 IFQ_DEQUEUE_NOLOCK(ifq, m);
4411 iflib_if_transmit(ifp, m);
4412 IFQ_DEQUEUE_NOLOCK(ifq, m);
4418 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4422 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { /* XXX - DRVAPI */
4423 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */
4425 iflib_altq_if_start(ifp);
4427 err = iflib_if_transmit(ifp, m);
4434 iflib_if_qflush(if_t ifp)
4436 if_ctx_t ctx = if_getsoftc(ifp);
4437 iflib_txq_t txq = ctx->ifc_txqs;
4441 ctx->ifc_flags |= IFC_QFLUSH;
4443 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4444 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4445 iflib_txq_check_drain(txq, 0);
4447 ctx->ifc_flags &= ~IFC_QFLUSH;
4451 * When ALTQ is enabled, this will also take care of purging the
4457 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4458 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4459 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4460 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4463 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4465 if_ctx_t ctx = if_getsoftc(ifp);
4466 struct ifreq *ifr = (struct ifreq *)data;
4467 #if defined(INET) || defined(INET6)
4468 struct ifaddr *ifa = (struct ifaddr *)data;
4470 bool avoid_reset = false;
4471 int err = 0, reinit = 0, bits;
4476 if (ifa->ifa_addr->sa_family == AF_INET)
4480 if (ifa->ifa_addr->sa_family == AF_INET6)
4484 ** Calling init results in link renegotiation,
4485 ** so we avoid doing it when possible.
4488 if_setflagbits(ifp, IFF_UP,0);
4489 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4492 if (!(if_getflags(ifp) & IFF_NOARP))
4493 arp_ifinit(ifp, ifa);
4496 err = ether_ioctl(ifp, command, data);
4500 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4504 bits = if_getdrvflags(ifp);
4505 /* stop the driver and free any clusters before proceeding */
4508 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4510 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4511 ctx->ifc_flags |= IFC_MULTISEG;
4513 ctx->ifc_flags &= ~IFC_MULTISEG;
4515 err = if_setmtu(ifp, ifr->ifr_mtu);
4517 iflib_init_locked(ctx);
4519 if_setdrvflags(ifp, bits);
4525 if (if_getflags(ifp) & IFF_UP) {
4526 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4527 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4528 (IFF_PROMISC | IFF_ALLMULTI)) {
4530 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4535 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4538 ctx->ifc_if_flags = if_getflags(ifp);
4543 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4545 IFDI_INTR_DISABLE(ctx);
4546 IFDI_MULTI_SET(ctx);
4547 IFDI_INTR_ENABLE(ctx);
4553 IFDI_MEDIA_SET(ctx);
4558 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4562 struct ifi2creq i2c;
4564 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4567 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4571 if (i2c.len > sizeof(i2c.data)) {
4576 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4577 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4583 int mask, setmask, oldmask;
4585 oldmask = if_getcapenable(ifp);
4586 mask = ifr->ifr_reqcap ^ oldmask;
4587 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4590 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4592 setmask |= (mask & IFCAP_FLAGS);
4593 setmask |= (mask & IFCAP_WOL);
4596 * If any RX csum has changed, change all the ones that
4597 * are supported by the driver.
4599 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4600 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4601 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4605 * want to ensure that traffic has stopped before we change any of the flags
4609 bits = if_getdrvflags(ifp);
4610 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4613 if_togglecapenable(ifp, setmask);
4614 ctx->ifc_softc_ctx.isc_capenable ^= setmask;
4616 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4617 iflib_init_locked(ctx);
4619 if_setdrvflags(ifp, bits);
4626 case SIOCGPRIVATE_0:
4630 err = IFDI_PRIV_IOCTL(ctx, command, data);
4634 err = ether_ioctl(ifp, command, data);
4643 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4645 if_ctx_t ctx = if_getsoftc(ifp);
4647 return (IFDI_GET_COUNTER(ctx, cnt));
4650 /*********************************************************************
4652 * OTHER FUNCTIONS EXPORTED TO THE STACK
4654 **********************************************************************/
4657 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4659 if_ctx_t ctx = if_getsoftc(ifp);
4661 if ((void *)ctx != arg)
4664 if ((vtag == 0) || (vtag > 4095))
4667 if (iflib_in_detach(ctx))
4671 /* Driver may need all untagged packets to be flushed */
4672 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4674 IFDI_VLAN_REGISTER(ctx, vtag);
4675 /* Re-init to load the changes, if required */
4676 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4677 iflib_init_locked(ctx);
4682 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4684 if_ctx_t ctx = if_getsoftc(ifp);
4686 if ((void *)ctx != arg)
4689 if ((vtag == 0) || (vtag > 4095))
4693 /* Driver may need all tagged packets to be flushed */
4694 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4696 IFDI_VLAN_UNREGISTER(ctx, vtag);
4697 /* Re-init to load the changes, if required */
4698 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4699 iflib_init_locked(ctx);
4704 iflib_led_func(void *arg, int onoff)
4709 IFDI_LED_FUNC(ctx, onoff);
4713 /*********************************************************************
4715 * BUS FUNCTION DEFINITIONS
4717 **********************************************************************/
4720 iflib_device_probe(device_t dev)
4722 const pci_vendor_info_t *ent;
4723 if_shared_ctx_t sctx;
4724 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4725 uint16_t pci_vendor_id;
4727 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4730 pci_vendor_id = pci_get_vendor(dev);
4731 pci_device_id = pci_get_device(dev);
4732 pci_subvendor_id = pci_get_subvendor(dev);
4733 pci_subdevice_id = pci_get_subdevice(dev);
4734 pci_rev_id = pci_get_revid(dev);
4735 if (sctx->isc_parse_devinfo != NULL)
4736 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4738 ent = sctx->isc_vendor_info;
4739 while (ent->pvi_vendor_id != 0) {
4740 if (pci_vendor_id != ent->pvi_vendor_id) {
4744 if ((pci_device_id == ent->pvi_device_id) &&
4745 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4746 (ent->pvi_subvendor_id == 0)) &&
4747 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4748 (ent->pvi_subdevice_id == 0)) &&
4749 ((pci_rev_id == ent->pvi_rev_id) ||
4750 (ent->pvi_rev_id == 0))) {
4751 device_set_desc_copy(dev, ent->pvi_name);
4752 /* this needs to be changed to zero if the bus probing code
4753 * ever stops re-probing on best match because the sctx
4754 * may have its values over written by register calls
4755 * in subsequent probes
4757 return (BUS_PROBE_DEFAULT);
4765 iflib_device_probe_vendor(device_t dev)
4769 probe = iflib_device_probe(dev);
4770 if (probe == BUS_PROBE_DEFAULT)
4771 return (BUS_PROBE_VENDOR);
4777 iflib_reset_qvalues(if_ctx_t ctx)
4779 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4780 if_shared_ctx_t sctx = ctx->ifc_sctx;
4781 device_t dev = ctx->ifc_dev;
4784 if (ctx->ifc_sysctl_ntxqs != 0)
4785 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4786 if (ctx->ifc_sysctl_nrxqs != 0)
4787 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4789 for (i = 0; i < sctx->isc_ntxqs; i++) {
4790 if (ctx->ifc_sysctl_ntxds[i] != 0)
4791 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4793 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4796 for (i = 0; i < sctx->isc_nrxqs; i++) {
4797 if (ctx->ifc_sysctl_nrxds[i] != 0)
4798 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4800 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4803 for (i = 0; i < sctx->isc_nrxqs; i++) {
4804 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4805 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4806 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4807 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4809 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4810 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4811 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4812 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4814 if (!powerof2(scctx->isc_nrxd[i])) {
4815 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4816 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4817 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4821 for (i = 0; i < sctx->isc_ntxqs; i++) {
4822 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4823 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4824 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4825 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4827 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4828 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4829 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4830 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4832 if (!powerof2(scctx->isc_ntxd[i])) {
4833 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4834 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4835 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4841 iflib_add_pfil(if_ctx_t ctx)
4843 struct pfil_head *pfil;
4844 struct pfil_head_args pa;
4848 pa.pa_version = PFIL_VERSION;
4849 pa.pa_flags = PFIL_IN;
4850 pa.pa_type = PFIL_TYPE_ETHERNET;
4851 pa.pa_headname = if_name(ctx->ifc_ifp);
4852 pfil = pfil_head_register(&pa);
4854 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4860 iflib_rem_pfil(if_ctx_t ctx)
4862 struct pfil_head *pfil;
4866 rxq = ctx->ifc_rxqs;
4868 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4871 pfil_head_unregister(pfil);
4876 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from
4877 * cpuid and wrapping as necessary.
4880 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n)
4882 unsigned int first_valid;
4883 unsigned int last_valid;
4885 /* cpuid should always be in the valid set */
4886 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus));
4888 /* valid set should never be empty */
4889 MPASS(!CPU_EMPTY(&ctx->ifc_cpus));
4891 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4892 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4893 n = n % CPU_COUNT(&ctx->ifc_cpus);
4897 if (cpuid > last_valid)
4898 cpuid = first_valid;
4899 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus));
4906 #if defined(SMP) && defined(SCHED_ULE)
4907 extern struct cpu_group *cpu_top; /* CPU topology */
4910 find_child_with_core(int cpu, struct cpu_group *grp)
4914 if (grp->cg_children == 0)
4917 MPASS(grp->cg_child);
4918 for (i = 0; i < grp->cg_children; i++) {
4919 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
4928 * Find an L2 neighbor of the given CPU or return -1 if none found. This
4929 * does not distinguish among multiple L2 neighbors if the given CPU has
4930 * more than one (it will always return the same result in that case).
4933 find_l2_neighbor(int cpu)
4935 struct cpu_group *grp;
4943 * Find the smallest CPU group that contains the given core.
4946 while ((i = find_child_with_core(cpu, grp)) != -1) {
4948 * If the smallest group containing the given CPU has less
4949 * than two members, we conclude the given CPU has no
4952 if (grp->cg_child[i].cg_count <= 1)
4954 grp = &grp->cg_child[i];
4957 /* Must share L2. */
4958 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
4962 * Select the first member of the set that isn't the reference
4963 * CPU, which at this point is guaranteed to exist.
4965 for (i = 0; i < CPU_SETSIZE; i++) {
4966 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu)
4970 /* Should never be reached */
4976 find_l2_neighbor(int cpu)
4984 * CPU mapping behaviors
4985 * ---------------------
4986 * 'separate txrx' refers to the separate_txrx sysctl
4987 * 'use logical' refers to the use_logical_cores sysctl
4988 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded
4991 * txrx logical CPUS result
4992 * ---------- --------- ------ ------------------------------------------------
4993 * - - X RX and TX queues mapped to consecutive physical
4994 * cores with RX/TX pairs on same core and excess
4995 * of either following
4996 * - X X RX and TX queues mapped to consecutive cores
4997 * of any type with RX/TX pairs on same core and
4998 * excess of either following
4999 * X - X RX and TX queues mapped to consecutive physical
5000 * cores; all RX then all TX
5001 * X X X RX queues mapped to consecutive physical cores
5002 * first, then TX queues mapped to L2 neighbor of
5003 * the corresponding RX queue if one exists,
5004 * otherwise to consecutive physical cores
5005 * - n/a - RX and TX queues mapped to consecutive cores of
5006 * any type with RX/TX pairs on same core and excess
5007 * of either following
5008 * X n/a - RX and TX queues mapped to consecutive cores of
5009 * any type; all RX then all TX
5012 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid,
5015 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5016 unsigned int core_index;
5018 if (ctx->ifc_sysctl_separate_txrx) {
5020 * When using separate CPUs for TX and RX, the assignment
5021 * will always be of a consecutive CPU out of the set of
5022 * context CPUs, except for the specific case where the
5023 * context CPUs are phsyical cores, the use of logical cores
5024 * has been enabled, the assignment is for TX, the TX qid
5025 * corresponds to an RX qid, and the CPU assigned to the
5026 * corresponding RX queue has an L2 neighbor.
5028 if (ctx->ifc_sysctl_use_logical_cores &&
5029 ctx->ifc_cpus_are_physical_cores &&
5030 is_tx && qid < scctx->isc_nrxqsets) {
5032 unsigned int rx_cpuid;
5034 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid);
5035 l2_neighbor = find_l2_neighbor(rx_cpuid);
5036 if (l2_neighbor != -1) {
5037 return (l2_neighbor);
5040 * ... else fall through to the normal
5041 * consecutive-after-RX assignment scheme.
5043 * Note that we are assuming that all RX queue CPUs
5044 * have an L2 neighbor, or all do not. If a mixed
5045 * scenario is possible, we will have to keep track
5046 * separately of how many queues prior to this one
5047 * were not able to be assigned to an L2 neighbor.
5051 core_index = scctx->isc_nrxqsets + qid;
5058 return (cpuid_advance(ctx, base_cpuid, core_index));
5062 get_ctx_core_offset(if_ctx_t ctx)
5064 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5065 struct cpu_offset *op;
5066 cpuset_t assigned_cpus;
5067 unsigned int cores_consumed;
5068 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset;
5069 unsigned int first_valid;
5070 unsigned int last_valid;
5073 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
5074 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
5076 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) {
5078 * Align the user-chosen base CPU ID to the next valid CPU
5079 * for this device. If the chosen base CPU ID is smaller
5080 * than the first valid CPU or larger than the last valid
5081 * CPU, we assume the user does not know what the valid
5082 * range is for this device and is thinking in terms of a
5083 * zero-based reference frame, and so we shift the given
5084 * value into the valid range (and wrap accordingly) so the
5085 * intent is translated to the proper frame of reference.
5086 * If the base CPU ID is within the valid first/last, but
5087 * does not correspond to a valid CPU, it is advanced to the
5088 * next valid CPU (wrapping if necessary).
5090 if (base_cpuid < first_valid || base_cpuid > last_valid) {
5091 /* shift from zero-based to first_valid-based */
5092 base_cpuid += first_valid;
5093 /* wrap to range [first_valid, last_valid] */
5094 base_cpuid = (base_cpuid - first_valid) %
5095 (last_valid - first_valid + 1);
5097 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) {
5099 * base_cpuid is in [first_valid, last_valid], but
5100 * not a member of the valid set. In this case,
5101 * there will always be a member of the valid set
5102 * with a CPU ID that is greater than base_cpuid,
5103 * and we simply advance to it.
5105 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus))
5108 return (base_cpuid);
5112 * Determine how many cores will be consumed by performing the CPU
5113 * assignments and counting how many of the assigned CPUs correspond
5114 * to CPUs in the set of context CPUs. This is done using the CPU
5115 * ID first_valid as the base CPU ID, as the base CPU must be within
5116 * the set of context CPUs.
5118 * Note not all assigned CPUs will be in the set of context CPUs
5119 * when separate CPUs are being allocated to TX and RX queues,
5120 * assignment to logical cores has been enabled, the set of context
5121 * CPUs contains only physical CPUs, and TX queues are mapped to L2
5122 * neighbors of CPUs that RX queues have been mapped to - in this
5123 * case we do only want to count how many CPUs in the set of context
5124 * CPUs have been consumed, as that determines the next CPU in that
5125 * set to start allocating at for the next device for which
5126 * core_offset is not set.
5128 CPU_ZERO(&assigned_cpus);
5129 for (i = 0; i < scctx->isc_ntxqsets; i++)
5130 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true),
5132 for (i = 0; i < scctx->isc_nrxqsets; i++)
5133 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false),
5135 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus);
5136 cores_consumed = CPU_COUNT(&assigned_cpus);
5138 mtx_lock(&cpu_offset_mtx);
5139 SLIST_FOREACH(op, &cpu_offsets, entries) {
5140 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5141 base_cpuid = op->next_cpuid;
5142 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid,
5144 MPASS(op->refcount < UINT_MAX);
5149 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) {
5150 base_cpuid = first_valid;
5151 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
5154 device_printf(ctx->ifc_dev,
5155 "allocation for cpu offset failed.\n");
5157 op->next_cpuid = cpuid_advance(ctx, base_cpuid,
5160 CPU_COPY(&ctx->ifc_cpus, &op->set);
5161 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
5164 mtx_unlock(&cpu_offset_mtx);
5166 return (base_cpuid);
5170 unref_ctx_core_offset(if_ctx_t ctx)
5172 struct cpu_offset *op, *top;
5174 mtx_lock(&cpu_offset_mtx);
5175 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
5176 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5177 MPASS(op->refcount > 0);
5179 if (op->refcount == 0) {
5180 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
5186 mtx_unlock(&cpu_offset_mtx);
5190 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
5194 if_softc_ctx_t scctx;
5195 kobjop_desc_t kobj_desc;
5196 kobj_method_t *kobj_method;
5198 int num_txd, num_rxd;
5200 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
5203 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5204 device_set_softc(dev, ctx);
5205 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5208 ctx->ifc_sctx = sctx;
5210 ctx->ifc_softc = sc;
5212 if ((err = iflib_register(ctx)) != 0) {
5213 device_printf(dev, "iflib_register failed %d\n", err);
5216 iflib_add_device_sysctl_pre(ctx);
5218 scctx = &ctx->ifc_softc_ctx;
5221 iflib_reset_qvalues(ctx);
5224 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5225 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5228 _iflib_pre_assert(scctx);
5229 ctx->ifc_txrx = *scctx->isc_txrx;
5231 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR));
5233 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
5234 ctx->ifc_mediap = scctx->isc_media;
5237 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5238 MPASS(scctx->isc_tx_csum_flags);
5241 if_setcapabilities(ifp,
5242 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
5243 if_setcapenable(ifp,
5244 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
5246 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5247 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5248 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5249 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5251 num_txd = iflib_num_tx_descs(ctx);
5252 num_rxd = iflib_num_rx_descs(ctx);
5254 /* XXX change for per-queue sizes */
5255 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5258 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5259 scctx->isc_tx_nsegments = max(1, num_txd /
5260 MAX_SINGLE_PACKET_FRACTION);
5261 if (scctx->isc_tx_tso_segments_max > num_txd /
5262 MAX_SINGLE_PACKET_FRACTION)
5263 scctx->isc_tx_tso_segments_max = max(1,
5264 num_txd / MAX_SINGLE_PACKET_FRACTION);
5266 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5267 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5269 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5272 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5275 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5276 * into account. In the worst case, each of these calls will
5277 * add another mbuf and, thus, the requirement for another DMA
5278 * segment. So for best performance, it doesn't make sense to
5279 * advertize a maximum of TSO segments that typically will
5280 * require defragmentation in iflib_encap().
5282 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5283 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5285 if (scctx->isc_rss_table_size == 0)
5286 scctx->isc_rss_table_size = 64;
5287 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5289 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5290 /* XXX format name */
5291 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5292 NULL, NULL, "admin");
5294 /* Set up cpu set. If it fails, use the set of all CPUs. */
5295 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
5296 device_printf(dev, "Unable to fetch CPU list\n");
5297 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
5298 ctx->ifc_cpus_are_physical_cores = false;
5300 ctx->ifc_cpus_are_physical_cores = true;
5301 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
5304 ** Now set up MSI or MSI-X, should return us the number of supported
5305 ** vectors (will be 1 for a legacy interrupt and MSI).
5307 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
5308 msix = scctx->isc_vectors;
5309 } else if (scctx->isc_msix_bar != 0)
5311 * The simple fact that isc_msix_bar is not 0 does not mean we
5312 * we have a good value there that is known to work.
5314 msix = iflib_msix_init(ctx);
5316 scctx->isc_vectors = 1;
5317 scctx->isc_ntxqsets = 1;
5318 scctx->isc_nrxqsets = 1;
5319 scctx->isc_intr = IFLIB_INTR_LEGACY;
5322 /* Get memory for the station queues */
5323 if ((err = iflib_queues_alloc(ctx))) {
5324 device_printf(dev, "Unable to allocate queue memory\n");
5325 goto fail_intr_free;
5328 if ((err = iflib_qset_structures_setup(ctx)))
5332 * Now that we know how many queues there are, get the core offset.
5334 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
5338 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
5339 * aren't the default NULL implementation.
5341 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
5342 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5344 if (kobj_method == &kobj_desc->deflt) {
5346 "MSI-X requires ifdi_rx_queue_intr_enable method");
5350 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
5351 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5353 if (kobj_method == &kobj_desc->deflt) {
5355 "MSI-X requires ifdi_tx_queue_intr_enable method");
5361 * Assign the MSI-X vectors.
5362 * Note that the default NULL ifdi_msix_intr_assign method will
5365 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
5367 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
5371 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
5373 if (scctx->isc_intr == IFLIB_INTR_MSI) {
5377 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
5378 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
5383 "Cannot use iflib with only 1 MSI-X interrupt!\n");
5388 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5390 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5391 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5396 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5397 * This must appear after the call to ether_ifattach() because
5398 * ether_ifattach() sets if_hdrlen to the default value.
5400 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5401 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5403 if ((err = iflib_netmap_attach(ctx))) {
5404 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
5409 DEBUGNET_SET(ctx->ifc_ifp, iflib);
5411 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5412 iflib_add_device_sysctl_post(ctx);
5413 iflib_add_pfil(ctx);
5414 ctx->ifc_flags |= IFC_INIT_DONE;
5421 ether_ifdetach(ctx->ifc_ifp);
5423 iflib_tqg_detach(ctx);
5424 iflib_tx_structures_free(ctx);
5425 iflib_rx_structures_free(ctx);
5427 IFDI_QUEUES_FREE(ctx);
5429 iflib_free_intr_mem(ctx);
5433 iflib_deregister(ctx);
5435 device_set_softc(ctx->ifc_dev, NULL);
5436 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5437 free(ctx->ifc_softc, M_IFLIB);
5443 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
5444 struct iflib_cloneattach_ctx *clctx)
5446 int num_txd, num_rxd;
5450 if_softc_ctx_t scctx;
5454 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
5455 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
5456 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5457 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
5458 ctx->ifc_flags |= IFC_PSEUDO;
5460 ctx->ifc_sctx = sctx;
5461 ctx->ifc_softc = sc;
5464 if ((err = iflib_register(ctx)) != 0) {
5465 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
5468 iflib_add_device_sysctl_pre(ctx);
5470 scctx = &ctx->ifc_softc_ctx;
5473 iflib_reset_qvalues(ctx);
5475 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5476 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5479 if (sctx->isc_flags & IFLIB_GEN_MAC)
5480 ether_gen_addr(ifp, &ctx->ifc_mac);
5481 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
5482 clctx->cc_params)) != 0) {
5483 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
5487 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5488 MPASS(scctx->isc_tx_csum_flags);
5491 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5492 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
5494 if_setflagbits(ifp, IFF_NOGROUP, 0);
5495 if (sctx->isc_flags & IFLIB_PSEUDO) {
5496 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5497 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5498 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
5499 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5501 if_attach(ctx->ifc_ifp);
5502 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
5505 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5506 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5512 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5513 * This must appear after the call to ether_ifattach() because
5514 * ether_ifattach() sets if_hdrlen to the default value.
5516 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5517 if_setifheaderlen(ifp,
5518 sizeof(struct ether_vlan_header));
5520 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5521 iflib_add_device_sysctl_post(ctx);
5522 ctx->ifc_flags |= IFC_INIT_DONE;
5526 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
5527 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
5528 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
5530 _iflib_pre_assert(scctx);
5531 ctx->ifc_txrx = *scctx->isc_txrx;
5533 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5534 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5535 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5536 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5538 num_txd = iflib_num_tx_descs(ctx);
5539 num_rxd = iflib_num_rx_descs(ctx);
5541 /* XXX change for per-queue sizes */
5542 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5545 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5546 scctx->isc_tx_nsegments = max(1, num_txd /
5547 MAX_SINGLE_PACKET_FRACTION);
5548 if (scctx->isc_tx_tso_segments_max > num_txd /
5549 MAX_SINGLE_PACKET_FRACTION)
5550 scctx->isc_tx_tso_segments_max = max(1,
5551 num_txd / MAX_SINGLE_PACKET_FRACTION);
5553 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5554 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5556 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5559 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5562 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5563 * into account. In the worst case, each of these calls will
5564 * add another mbuf and, thus, the requirement for another DMA
5565 * segment. So for best performance, it doesn't make sense to
5566 * advertize a maximum of TSO segments that typically will
5567 * require defragmentation in iflib_encap().
5569 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5570 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5572 if (scctx->isc_rss_table_size == 0)
5573 scctx->isc_rss_table_size = 64;
5574 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
5576 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5577 /* XXX format name */
5578 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
5579 NULL, NULL, "admin");
5581 /* XXX --- can support > 1 -- but keep it simple for now */
5582 scctx->isc_intr = IFLIB_INTR_LEGACY;
5584 /* Get memory for the station queues */
5585 if ((err = iflib_queues_alloc(ctx))) {
5586 device_printf(dev, "Unable to allocate queue memory\n");
5587 goto fail_iflib_detach;
5590 if ((err = iflib_qset_structures_setup(ctx))) {
5591 device_printf(dev, "qset structure setup failed %d\n", err);
5596 * XXX What if anything do we want to do about interrupts?
5598 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5599 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5600 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5605 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5606 * This must appear after the call to ether_ifattach() because
5607 * ether_ifattach() sets if_hdrlen to the default value.
5609 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5610 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5612 /* XXX handle more than one queue */
5613 for (i = 0; i < scctx->isc_nrxqsets; i++)
5614 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5618 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5619 iflib_add_device_sysctl_post(ctx);
5620 ctx->ifc_flags |= IFC_INIT_DONE;
5625 ether_ifdetach(ctx->ifc_ifp);
5627 iflib_tqg_detach(ctx);
5628 iflib_tx_structures_free(ctx);
5629 iflib_rx_structures_free(ctx);
5632 IFDI_QUEUES_FREE(ctx);
5635 iflib_deregister(ctx);
5637 free(ctx->ifc_softc, M_IFLIB);
5643 iflib_pseudo_deregister(if_ctx_t ctx)
5645 if_t ifp = ctx->ifc_ifp;
5646 if_shared_ctx_t sctx = ctx->ifc_sctx;
5648 /* Unregister VLAN event handlers early */
5649 iflib_unregister_vlan_handlers(ctx);
5651 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5652 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5656 ether_ifdetach(ifp);
5659 iflib_tqg_detach(ctx);
5660 iflib_tx_structures_free(ctx);
5661 iflib_rx_structures_free(ctx);
5663 IFDI_QUEUES_FREE(ctx);
5665 iflib_deregister(ctx);
5667 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5668 free(ctx->ifc_softc, M_IFLIB);
5674 iflib_device_attach(device_t dev)
5677 if_shared_ctx_t sctx;
5679 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5682 pci_enable_busmaster(dev);
5684 return (iflib_device_register(dev, NULL, sctx, &ctx));
5688 iflib_device_deregister(if_ctx_t ctx)
5690 if_t ifp = ctx->ifc_ifp;
5691 device_t dev = ctx->ifc_dev;
5693 /* Make sure VLANS are not using driver */
5694 if (if_vlantrunkinuse(ifp)) {
5695 device_printf(dev, "Vlan in use, detach first\n");
5699 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5700 device_printf(dev, "SR-IOV in use; detach first.\n");
5706 ctx->ifc_flags |= IFC_IN_DETACH;
5709 /* Unregister VLAN handlers before calling iflib_stop() */
5710 iflib_unregister_vlan_handlers(ctx);
5712 iflib_netmap_detach(ifp);
5713 ether_ifdetach(ifp);
5719 iflib_rem_pfil(ctx);
5720 if (ctx->ifc_led_dev != NULL)
5721 led_destroy(ctx->ifc_led_dev);
5723 iflib_tqg_detach(ctx);
5724 iflib_tx_structures_free(ctx);
5725 iflib_rx_structures_free(ctx);
5729 IFDI_QUEUES_FREE(ctx);
5732 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5733 iflib_free_intr_mem(ctx);
5735 bus_generic_detach(dev);
5737 iflib_deregister(ctx);
5739 device_set_softc(ctx->ifc_dev, NULL);
5740 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5741 free(ctx->ifc_softc, M_IFLIB);
5742 unref_ctx_core_offset(ctx);
5748 iflib_tqg_detach(if_ctx_t ctx)
5753 struct taskqgroup *tqg;
5755 /* XXX drain any dependent tasks */
5756 tqg = qgroup_if_io_tqg;
5757 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5758 callout_drain(&txq->ift_timer);
5760 callout_drain(&txq->ift_netmap_timer);
5761 #endif /* DEV_NETMAP */
5762 if (txq->ift_task.gt_uniq != NULL)
5763 taskqgroup_detach(tqg, &txq->ift_task);
5765 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5766 if (rxq->ifr_task.gt_uniq != NULL)
5767 taskqgroup_detach(tqg, &rxq->ifr_task);
5769 tqg = qgroup_if_config_tqg;
5770 if (ctx->ifc_admin_task.gt_uniq != NULL)
5771 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5772 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5773 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5777 iflib_free_intr_mem(if_ctx_t ctx)
5780 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5781 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5783 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5784 pci_release_msi(ctx->ifc_dev);
5786 if (ctx->ifc_msix_mem != NULL) {
5787 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5788 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5789 ctx->ifc_msix_mem = NULL;
5794 iflib_device_detach(device_t dev)
5796 if_ctx_t ctx = device_get_softc(dev);
5798 return (iflib_device_deregister(ctx));
5802 iflib_device_suspend(device_t dev)
5804 if_ctx_t ctx = device_get_softc(dev);
5810 return bus_generic_suspend(dev);
5813 iflib_device_shutdown(device_t dev)
5815 if_ctx_t ctx = device_get_softc(dev);
5821 return bus_generic_suspend(dev);
5825 iflib_device_resume(device_t dev)
5827 if_ctx_t ctx = device_get_softc(dev);
5828 iflib_txq_t txq = ctx->ifc_txqs;
5832 iflib_if_init_locked(ctx);
5834 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5835 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5837 return (bus_generic_resume(dev));
5841 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5844 if_ctx_t ctx = device_get_softc(dev);
5847 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5854 iflib_device_iov_uninit(device_t dev)
5856 if_ctx_t ctx = device_get_softc(dev);
5859 IFDI_IOV_UNINIT(ctx);
5864 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5867 if_ctx_t ctx = device_get_softc(dev);
5870 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5876 /*********************************************************************
5878 * MODULE FUNCTION DEFINITIONS
5880 **********************************************************************/
5883 * - Start a fast taskqueue thread for each core
5884 * - Start a taskqueue for control operations
5887 iflib_module_init(void)
5889 iflib_timer_default = hz / 2;
5894 iflib_module_event_handler(module_t mod, int what, void *arg)
5900 if ((err = iflib_module_init()) != 0)
5906 return (EOPNOTSUPP);
5912 /*********************************************************************
5914 * PUBLIC FUNCTION DEFINITIONS
5915 * ordered as in iflib.h
5917 **********************************************************************/
5920 _iflib_assert(if_shared_ctx_t sctx)
5924 MPASS(sctx->isc_tx_maxsize);
5925 MPASS(sctx->isc_tx_maxsegsize);
5927 MPASS(sctx->isc_rx_maxsize);
5928 MPASS(sctx->isc_rx_nsegments);
5929 MPASS(sctx->isc_rx_maxsegsize);
5931 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5932 for (i = 0; i < sctx->isc_nrxqs; i++) {
5933 MPASS(sctx->isc_nrxd_min[i]);
5934 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5935 MPASS(sctx->isc_nrxd_max[i]);
5936 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5937 MPASS(sctx->isc_nrxd_default[i]);
5938 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5941 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5942 for (i = 0; i < sctx->isc_ntxqs; i++) {
5943 MPASS(sctx->isc_ntxd_min[i]);
5944 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5945 MPASS(sctx->isc_ntxd_max[i]);
5946 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5947 MPASS(sctx->isc_ntxd_default[i]);
5948 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5953 _iflib_pre_assert(if_softc_ctx_t scctx)
5956 MPASS(scctx->isc_txrx->ift_txd_encap);
5957 MPASS(scctx->isc_txrx->ift_txd_flush);
5958 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5959 MPASS(scctx->isc_txrx->ift_rxd_available);
5960 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5961 MPASS(scctx->isc_txrx->ift_rxd_refill);
5962 MPASS(scctx->isc_txrx->ift_rxd_flush);
5966 iflib_register(if_ctx_t ctx)
5968 if_shared_ctx_t sctx = ctx->ifc_sctx;
5969 driver_t *driver = sctx->isc_driver;
5970 device_t dev = ctx->ifc_dev;
5975 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5976 _iflib_assert(sctx);
5979 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5980 if (sctx->isc_flags & IFLIB_PSEUDO) {
5981 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5987 ifp = ctx->ifc_ifp = if_alloc(type);
5989 device_printf(dev, "can not allocate ifnet structure\n");
5994 * Initialize our context's device specific methods
5996 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5997 kobj_class_compile((kobj_class_t) driver);
5999 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
6000 if_setsoftc(ifp, ctx);
6001 if_setdev(ifp, dev);
6002 if_setinitfn(ifp, iflib_if_init);
6003 if_setioctlfn(ifp, iflib_if_ioctl);
6005 if_setstartfn(ifp, iflib_altq_if_start);
6006 if_settransmitfn(ifp, iflib_altq_if_transmit);
6007 if_setsendqready(ifp);
6009 if_settransmitfn(ifp, iflib_if_transmit);
6011 if_setqflushfn(ifp, iflib_if_qflush);
6012 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
6014 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
6015 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
6016 iflags |= IFF_POINTOPOINT;
6018 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
6019 if_setflags(ifp, iflags);
6020 ctx->ifc_vlan_attach_event =
6021 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
6022 EVENTHANDLER_PRI_FIRST);
6023 ctx->ifc_vlan_detach_event =
6024 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
6025 EVENTHANDLER_PRI_FIRST);
6027 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
6028 ctx->ifc_mediap = &ctx->ifc_media;
6029 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
6030 iflib_media_change, iflib_media_status);
6036 iflib_unregister_vlan_handlers(if_ctx_t ctx)
6038 /* Unregister VLAN events */
6039 if (ctx->ifc_vlan_attach_event != NULL) {
6040 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
6041 ctx->ifc_vlan_attach_event = NULL;
6043 if (ctx->ifc_vlan_detach_event != NULL) {
6044 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
6045 ctx->ifc_vlan_detach_event = NULL;
6051 iflib_deregister(if_ctx_t ctx)
6053 if_t ifp = ctx->ifc_ifp;
6055 /* Remove all media */
6056 ifmedia_removeall(&ctx->ifc_media);
6058 /* Ensure that VLAN event handlers are unregistered */
6059 iflib_unregister_vlan_handlers(ctx);
6061 /* Release kobject reference */
6062 kobj_delete((kobj_t) ctx, NULL);
6064 /* Free the ifnet structure */
6067 STATE_LOCK_DESTROY(ctx);
6069 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
6070 CTX_LOCK_DESTROY(ctx);
6074 iflib_queues_alloc(if_ctx_t ctx)
6076 if_shared_ctx_t sctx = ctx->ifc_sctx;
6077 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6078 device_t dev = ctx->ifc_dev;
6079 int nrxqsets = scctx->isc_nrxqsets;
6080 int ntxqsets = scctx->isc_ntxqsets;
6083 iflib_fl_t fl = NULL;
6084 int i, j, cpu, err, txconf, rxconf;
6085 iflib_dma_info_t ifdip;
6086 uint32_t *rxqsizes = scctx->isc_rxqsizes;
6087 uint32_t *txqsizes = scctx->isc_txqsizes;
6088 uint8_t nrxqs = sctx->isc_nrxqs;
6089 uint8_t ntxqs = sctx->isc_ntxqs;
6090 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
6091 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
6095 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
6096 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
6097 KASSERT(nrxqs >= fl_offset + nfree_lists,
6098 ("there must be at least a rxq for each free list"));
6100 /* Allocate the TX ring struct memory */
6101 if (!(ctx->ifc_txqs =
6102 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
6103 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
6104 device_printf(dev, "Unable to allocate TX ring memory\n");
6109 /* Now allocate the RX */
6110 if (!(ctx->ifc_rxqs =
6111 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
6112 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
6113 device_printf(dev, "Unable to allocate RX ring memory\n");
6118 txq = ctx->ifc_txqs;
6119 rxq = ctx->ifc_rxqs;
6122 * XXX handle allocation failure
6124 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
6125 /* Set up some basics */
6127 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
6128 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
6130 "Unable to allocate TX DMA info memory\n");
6134 txq->ift_ifdi = ifdip;
6135 for (j = 0; j < ntxqs; j++, ifdip++) {
6136 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
6138 "Unable to allocate TX descriptors\n");
6142 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
6143 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
6147 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
6148 txq->ift_br_offset = 1;
6150 txq->ift_br_offset = 0;
6153 if (iflib_txsd_alloc(txq)) {
6154 device_printf(dev, "Critical Failure setting up TX buffers\n");
6159 /* Initialize the TX lock */
6160 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
6161 device_get_nameunit(dev), txq->ift_id);
6162 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
6163 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
6164 txq->ift_timer.c_cpu = cpu;
6166 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
6167 txq->ift_netmap_timer.c_cpu = cpu;
6168 #endif /* DEV_NETMAP */
6170 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
6171 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
6173 /* XXX free any allocated rings */
6174 device_printf(dev, "Unable to allocate buf_ring\n");
6179 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
6180 /* Set up some basics */
6181 callout_init(&rxq->ifr_watchdog, 1);
6183 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
6184 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
6186 "Unable to allocate RX DMA info memory\n");
6191 rxq->ifr_ifdi = ifdip;
6192 /* XXX this needs to be changed if #rx queues != #tx queues */
6193 rxq->ifr_ntxqirq = 1;
6194 rxq->ifr_txqid[0] = i;
6195 for (j = 0; j < nrxqs; j++, ifdip++) {
6196 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
6198 "Unable to allocate RX descriptors\n");
6202 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
6206 rxq->ifr_fl_offset = fl_offset;
6207 rxq->ifr_nfl = nfree_lists;
6209 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
6210 device_printf(dev, "Unable to allocate free list memory\n");
6215 for (j = 0; j < nfree_lists; j++) {
6216 fl[j].ifl_rxq = rxq;
6218 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
6219 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
6221 /* Allocate receive buffers for the ring */
6222 if (iflib_rxsd_alloc(rxq)) {
6224 "Critical Failure setting up receive buffers\n");
6229 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
6230 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
6235 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
6236 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
6237 for (i = 0; i < ntxqsets; i++) {
6238 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
6240 for (j = 0; j < ntxqs; j++, di++) {
6241 vaddrs[i*ntxqs + j] = di->idi_vaddr;
6242 paddrs[i*ntxqs + j] = di->idi_paddr;
6245 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
6246 device_printf(ctx->ifc_dev,
6247 "Unable to allocate device TX queue\n");
6248 iflib_tx_structures_free(ctx);
6249 free(vaddrs, M_IFLIB);
6250 free(paddrs, M_IFLIB);
6253 free(vaddrs, M_IFLIB);
6254 free(paddrs, M_IFLIB);
6257 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6258 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
6259 for (i = 0; i < nrxqsets; i++) {
6260 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
6262 for (j = 0; j < nrxqs; j++, di++) {
6263 vaddrs[i*nrxqs + j] = di->idi_vaddr;
6264 paddrs[i*nrxqs + j] = di->idi_paddr;
6267 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
6268 device_printf(ctx->ifc_dev,
6269 "Unable to allocate device RX queue\n");
6270 iflib_tx_structures_free(ctx);
6271 free(vaddrs, M_IFLIB);
6272 free(paddrs, M_IFLIB);
6275 free(vaddrs, M_IFLIB);
6276 free(paddrs, M_IFLIB);
6280 /* XXX handle allocation failure changes */
6284 if (ctx->ifc_rxqs != NULL)
6285 free(ctx->ifc_rxqs, M_IFLIB);
6286 ctx->ifc_rxqs = NULL;
6287 if (ctx->ifc_txqs != NULL)
6288 free(ctx->ifc_txqs, M_IFLIB);
6289 ctx->ifc_txqs = NULL;
6295 iflib_tx_structures_setup(if_ctx_t ctx)
6297 iflib_txq_t txq = ctx->ifc_txqs;
6300 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
6301 iflib_txq_setup(txq);
6307 iflib_tx_structures_free(if_ctx_t ctx)
6309 iflib_txq_t txq = ctx->ifc_txqs;
6310 if_shared_ctx_t sctx = ctx->ifc_sctx;
6313 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6314 for (j = 0; j < sctx->isc_ntxqs; j++)
6315 iflib_dma_free(&txq->ift_ifdi[j]);
6316 iflib_txq_destroy(txq);
6318 free(ctx->ifc_txqs, M_IFLIB);
6319 ctx->ifc_txqs = NULL;
6322 /*********************************************************************
6324 * Initialize all receive rings.
6326 **********************************************************************/
6328 iflib_rx_structures_setup(if_ctx_t ctx)
6330 iflib_rxq_t rxq = ctx->ifc_rxqs;
6332 #if defined(INET6) || defined(INET)
6336 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
6337 #if defined(INET6) || defined(INET)
6338 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
6339 TCP_LRO_ENTRIES, min(1024,
6340 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
6342 device_printf(ctx->ifc_dev,
6343 "LRO Initialization failed!\n");
6347 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
6350 #if defined(INET6) || defined(INET)
6353 * Free LRO resources allocated so far, we will only handle
6354 * the rings that completed, the failing case will have
6355 * cleaned up for itself. 'q' failed, so its the terminus.
6357 rxq = ctx->ifc_rxqs;
6358 for (i = 0; i < q; ++i, rxq++) {
6359 tcp_lro_free(&rxq->ifr_lc);
6365 /*********************************************************************
6367 * Free all receive rings.
6369 **********************************************************************/
6371 iflib_rx_structures_free(if_ctx_t ctx)
6373 iflib_rxq_t rxq = ctx->ifc_rxqs;
6374 if_shared_ctx_t sctx = ctx->ifc_sctx;
6377 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
6378 for (j = 0; j < sctx->isc_nrxqs; j++)
6379 iflib_dma_free(&rxq->ifr_ifdi[j]);
6380 iflib_rx_sds_free(rxq);
6381 #if defined(INET6) || defined(INET)
6382 tcp_lro_free(&rxq->ifr_lc);
6385 free(ctx->ifc_rxqs, M_IFLIB);
6386 ctx->ifc_rxqs = NULL;
6390 iflib_qset_structures_setup(if_ctx_t ctx)
6395 * It is expected that the caller takes care of freeing queues if this
6398 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
6399 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
6403 if ((err = iflib_rx_structures_setup(ctx)) != 0)
6404 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
6410 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
6411 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
6414 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
6417 /* Just to avoid copy/paste */
6419 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6420 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6424 unsigned int base_cpuid, cpuid;
6428 base_cpuid = ctx->ifc_sysctl_core_offset;
6429 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX);
6430 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev,
6431 irq ? irq->ii_res : NULL, name);
6433 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6437 if (cpuid > ctx->ifc_cpuid_highest)
6438 ctx->ifc_cpuid_highest = cpuid;
6444 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6445 iflib_intr_type_t type, driver_filter_t *filter,
6446 void *filter_arg, int qid, const char *name)
6449 struct grouptask *gtask;
6450 struct taskqgroup *tqg;
6451 iflib_filter_info_t info;
6454 driver_filter_t *intr_fast;
6457 info = &ctx->ifc_filter_info;
6461 /* XXX merge tx/rx for netmap? */
6463 q = &ctx->ifc_txqs[qid];
6464 info = &ctx->ifc_txqs[qid].ift_filter_info;
6465 gtask = &ctx->ifc_txqs[qid].ift_task;
6466 tqg = qgroup_if_io_tqg;
6468 intr_fast = iflib_fast_intr;
6469 GROUPTASK_INIT(gtask, 0, fn, q);
6470 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6473 q = &ctx->ifc_rxqs[qid];
6474 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6475 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6476 tqg = qgroup_if_io_tqg;
6478 intr_fast = iflib_fast_intr;
6479 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6481 case IFLIB_INTR_RXTX:
6482 q = &ctx->ifc_rxqs[qid];
6483 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6484 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6485 tqg = qgroup_if_io_tqg;
6487 intr_fast = iflib_fast_intr_rxtx;
6488 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6490 case IFLIB_INTR_ADMIN:
6493 info = &ctx->ifc_filter_info;
6494 gtask = &ctx->ifc_admin_task;
6495 tqg = qgroup_if_config_tqg;
6496 fn = _task_fn_admin;
6497 intr_fast = iflib_fast_intr_ctx;
6500 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6505 info->ifi_filter = filter;
6506 info->ifi_filter_arg = filter_arg;
6507 info->ifi_task = gtask;
6511 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6513 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6516 if (type == IFLIB_INTR_ADMIN)
6520 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6525 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6532 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6535 struct grouptask *gtask;
6536 struct taskqgroup *tqg;
6543 q = &ctx->ifc_txqs[qid];
6544 gtask = &ctx->ifc_txqs[qid].ift_task;
6545 tqg = qgroup_if_io_tqg;
6547 GROUPTASK_INIT(gtask, 0, fn, q);
6550 q = &ctx->ifc_rxqs[qid];
6551 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6552 tqg = qgroup_if_io_tqg;
6554 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6556 case IFLIB_INTR_IOV:
6558 gtask = &ctx->ifc_vflr_task;
6559 tqg = qgroup_if_config_tqg;
6561 GROUPTASK_INIT(gtask, 0, fn, q);
6564 panic("unknown net intr type");
6566 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name);
6569 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL,
6575 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6579 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6582 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6583 rman_get_rid(irq->ii_res), irq->ii_res);
6587 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6589 iflib_txq_t txq = ctx->ifc_txqs;
6590 iflib_rxq_t rxq = ctx->ifc_rxqs;
6591 if_irq_t irq = &ctx->ifc_legacy_irq;
6592 iflib_filter_info_t info;
6594 struct grouptask *gtask;
6595 struct resource *res;
6596 struct taskqgroup *tqg;
6601 q = &ctx->ifc_rxqs[0];
6602 info = &rxq[0].ifr_filter_info;
6603 gtask = &rxq[0].ifr_task;
6604 tqg = qgroup_if_io_tqg;
6606 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6608 ctx->ifc_flags |= IFC_LEGACY;
6609 info->ifi_filter = filter;
6610 info->ifi_filter_arg = filter_arg;
6611 info->ifi_task = gtask;
6612 info->ifi_ctx = rx_only ? ctx : q;
6615 /* We allocate a single interrupt resource */
6616 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6617 iflib_fast_intr_rxtx, NULL, info, name);
6620 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6622 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6624 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6625 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6631 iflib_led_create(if_ctx_t ctx)
6634 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6635 device_get_nameunit(ctx->ifc_dev));
6639 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6642 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6646 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6649 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6653 iflib_admin_intr_deferred(if_ctx_t ctx)
6656 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6657 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6661 iflib_iov_intr_deferred(if_ctx_t ctx)
6664 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6668 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6671 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6676 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6680 GROUPTASK_INIT(gtask, 0, fn, ctx);
6681 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6686 iflib_config_gtask_deinit(struct grouptask *gtask)
6689 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6693 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6695 if_t ifp = ctx->ifc_ifp;
6696 iflib_txq_t txq = ctx->ifc_txqs;
6698 if_setbaudrate(ifp, baudrate);
6699 if (baudrate >= IF_Gbps(10)) {
6701 ctx->ifc_flags |= IFC_PREFETCH;
6704 /* If link down, disable watchdog */
6705 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6706 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6707 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6709 ctx->ifc_link_state = link_state;
6710 if_link_state_change(ifp, link_state);
6714 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6718 int credits_pre = txq->ift_cidx_processed;
6721 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6722 BUS_DMASYNC_POSTREAD);
6723 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6726 txq->ift_processed += credits;
6727 txq->ift_cidx_processed += credits;
6729 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6730 if (txq->ift_cidx_processed >= txq->ift_size)
6731 txq->ift_cidx_processed -= txq->ift_size;
6736 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6741 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6742 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6743 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6744 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6749 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6750 const char *description, if_int_delay_info_t info,
6751 int offset, int value)
6753 info->iidi_ctx = ctx;
6754 info->iidi_offset = offset;
6755 info->iidi_value = value;
6756 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6757 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6758 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6759 info, 0, iflib_sysctl_int_delay, "I", description);
6763 iflib_ctx_lock_get(if_ctx_t ctx)
6766 return (&ctx->ifc_ctx_sx);
6770 iflib_msix_init(if_ctx_t ctx)
6772 device_t dev = ctx->ifc_dev;
6773 if_shared_ctx_t sctx = ctx->ifc_sctx;
6774 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6775 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6776 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6778 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6779 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6782 device_printf(dev, "msix_init qsets capped at %d\n",
6783 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6785 /* Override by tuneable */
6786 if (scctx->isc_disable_msix)
6789 /* First try MSI-X */
6790 if ((msgs = pci_msix_count(dev)) == 0) {
6792 device_printf(dev, "MSI-X not supported or disabled\n");
6796 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6798 * bar == -1 => "trust me I know what I'm doing"
6799 * Some drivers are for hardware that is so shoddily
6800 * documented that no one knows which bars are which
6801 * so the developer has to map all bars. This hack
6802 * allows shoddy garbage to use MSI-X in this framework.
6805 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6806 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6807 if (ctx->ifc_msix_mem == NULL) {
6808 device_printf(dev, "Unable to map MSI-X table\n");
6813 admincnt = sctx->isc_admin_intrcnt;
6815 /* use only 1 qset in debug mode */
6816 queuemsgs = min(msgs - admincnt, 1);
6818 queuemsgs = msgs - admincnt;
6821 queues = imin(queuemsgs, rss_getnumbuckets());
6825 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6828 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6829 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6831 /* If we're doing RSS, clamp at the number of RSS buckets */
6832 if (queues > rss_getnumbuckets())
6833 queues = rss_getnumbuckets();
6835 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6836 rx_queues = iflib_num_rx_queues;
6840 if (rx_queues > scctx->isc_nrxqsets)
6841 rx_queues = scctx->isc_nrxqsets;
6844 * We want this to be all logical CPUs by default
6846 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6847 tx_queues = iflib_num_tx_queues;
6849 tx_queues = mp_ncpus;
6851 if (tx_queues > scctx->isc_ntxqsets)
6852 tx_queues = scctx->isc_ntxqsets;
6854 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6856 if (tx_queues != rx_queues)
6858 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6859 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6861 tx_queues = min(rx_queues, tx_queues);
6862 rx_queues = min(rx_queues, tx_queues);
6865 vectors = rx_queues + admincnt;
6866 if (msgs < vectors) {
6868 "insufficient number of MSI-X vectors "
6869 "(supported %d, need %d)\n", msgs, vectors);
6873 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6876 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6877 if (vectors != msgs) {
6879 "Unable to allocate sufficient MSI-X vectors "
6880 "(got %d, need %d)\n", vectors, msgs);
6881 pci_release_msi(dev);
6883 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6885 ctx->ifc_msix_mem = NULL;
6889 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6891 scctx->isc_vectors = vectors;
6892 scctx->isc_nrxqsets = rx_queues;
6893 scctx->isc_ntxqsets = tx_queues;
6894 scctx->isc_intr = IFLIB_INTR_MSIX;
6899 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6902 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6904 ctx->ifc_msix_mem = NULL;
6909 vectors = pci_msi_count(dev);
6910 scctx->isc_nrxqsets = 1;
6911 scctx->isc_ntxqsets = 1;
6912 scctx->isc_vectors = vectors;
6913 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6914 device_printf(dev,"Using an MSI interrupt\n");
6915 scctx->isc_intr = IFLIB_INTR_MSI;
6917 scctx->isc_vectors = 1;
6918 device_printf(dev,"Using a Legacy interrupt\n");
6919 scctx->isc_intr = IFLIB_INTR_LEGACY;
6925 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6928 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6931 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6933 const char *ring_state = "UNKNOWN";
6936 rc = sysctl_wire_old_buffer(req, 0);
6940 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6945 ring_state = ring_states[state[3]];
6947 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6948 state[0], state[1], state[2], ring_state);
6949 rc = sbuf_finish(sb);
6954 enum iflib_ndesc_handler {
6960 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6962 if_ctx_t ctx = (void *)arg1;
6963 enum iflib_ndesc_handler type = arg2;
6964 char buf[256] = {0};
6971 case IFLIB_NTXD_HANDLER:
6972 ndesc = ctx->ifc_sysctl_ntxds;
6974 nqs = ctx->ifc_sctx->isc_ntxqs;
6976 case IFLIB_NRXD_HANDLER:
6977 ndesc = ctx->ifc_sysctl_nrxds;
6979 nqs = ctx->ifc_sctx->isc_nrxqs;
6982 printf("%s: unhandled type\n", __func__);
6988 for (i=0; i<8; i++) {
6993 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6996 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6997 if (rc || req->newptr == NULL)
7000 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
7001 i++, p = strsep(&next, " ,")) {
7002 ndesc[i] = strtoul(p, NULL, 10);
7008 #define NAME_BUFLEN 32
7010 iflib_add_device_sysctl_pre(if_ctx_t ctx)
7012 device_t dev = iflib_get_dev(ctx);
7013 struct sysctl_oid_list *child, *oid_list;
7014 struct sysctl_ctx_list *ctx_list;
7015 struct sysctl_oid *node;
7017 ctx_list = device_get_sysctl_ctx(dev);
7018 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
7019 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
7020 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
7021 oid_list = SYSCTL_CHILDREN(node);
7023 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
7024 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
7027 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
7028 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
7029 "# of txqs to use, 0 => use default #");
7030 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
7031 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
7032 "# of rxqs to use, 0 => use default #");
7033 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
7034 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
7035 "permit #txq != #rxq");
7036 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
7037 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
7038 "disable MSI-X (default 0)");
7039 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
7040 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
7041 "set the RX budget");
7042 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
7043 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
7044 "cause TX to abdicate instead of running to completion");
7045 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
7046 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
7047 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
7048 "offset to start using cores at");
7049 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
7050 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
7051 "use separate cores for TX and RX");
7052 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores",
7053 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0,
7054 "try to make use of logical cores for TX and RX");
7056 /* XXX change for per-queue sizes */
7057 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
7058 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
7059 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
7060 "list of # of TX descriptors to use, 0 = use default #");
7061 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
7062 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
7063 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
7064 "list of # of RX descriptors to use, 0 = use default #");
7068 iflib_add_device_sysctl_post(if_ctx_t ctx)
7070 if_shared_ctx_t sctx = ctx->ifc_sctx;
7071 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
7072 device_t dev = iflib_get_dev(ctx);
7073 struct sysctl_oid_list *child;
7074 struct sysctl_ctx_list *ctx_list;
7079 char namebuf[NAME_BUFLEN];
7081 struct sysctl_oid *queue_node, *fl_node, *node;
7082 struct sysctl_oid_list *queue_list, *fl_list;
7083 ctx_list = device_get_sysctl_ctx(dev);
7085 node = ctx->ifc_sysctl_node;
7086 child = SYSCTL_CHILDREN(node);
7088 if (scctx->isc_ntxqsets > 100)
7090 else if (scctx->isc_ntxqsets > 10)
7094 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
7095 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
7096 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
7097 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
7098 queue_list = SYSCTL_CHILDREN(queue_node);
7099 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
7101 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to");
7103 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
7105 &txq->ift_dequeued, "total mbufs freed");
7106 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
7108 &txq->ift_enqueued, "total mbufs enqueued");
7110 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
7112 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
7113 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
7115 &txq->ift_pullups, "# of times m_pullup was called");
7116 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
7118 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
7119 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
7121 &txq->ift_no_desc_avail, "# of times no descriptors were available");
7122 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
7124 &txq->ift_map_failed, "# of times DMA map failed");
7125 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
7127 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
7128 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
7130 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
7131 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
7133 &txq->ift_pidx, 1, "Producer Index");
7134 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
7136 &txq->ift_cidx, 1, "Consumer Index");
7137 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
7139 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
7140 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
7142 &txq->ift_in_use, 1, "descriptors in use");
7143 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
7145 &txq->ift_processed, "descriptors procesed for clean");
7146 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
7148 &txq->ift_cleaned, "total cleaned");
7149 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
7150 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
7151 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
7152 mp_ring_state_handler, "A", "soft ring state");
7153 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
7154 CTLFLAG_RD, &txq->ift_br->enqueues,
7155 "# of enqueues to the mp_ring for this queue");
7156 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
7157 CTLFLAG_RD, &txq->ift_br->drops,
7158 "# of drops in the mp_ring for this queue");
7159 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
7160 CTLFLAG_RD, &txq->ift_br->starts,
7161 "# of normal consumer starts in the mp_ring for this queue");
7162 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
7163 CTLFLAG_RD, &txq->ift_br->stalls,
7164 "# of consumer stalls in the mp_ring for this queue");
7165 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
7166 CTLFLAG_RD, &txq->ift_br->restarts,
7167 "# of consumer restarts in the mp_ring for this queue");
7168 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
7169 CTLFLAG_RD, &txq->ift_br->abdications,
7170 "# of consumer abdications in the mp_ring for this queue");
7173 if (scctx->isc_nrxqsets > 100)
7175 else if (scctx->isc_nrxqsets > 10)
7179 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
7180 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
7181 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
7182 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
7183 queue_list = SYSCTL_CHILDREN(queue_node);
7184 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
7186 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to");
7187 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
7188 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
7190 &rxq->ifr_cq_cidx, 1, "Consumer Index");
7193 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
7194 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
7195 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
7196 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
7197 fl_list = SYSCTL_CHILDREN(fl_node);
7198 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
7200 &fl->ifl_pidx, 1, "Producer Index");
7201 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
7203 &fl->ifl_cidx, 1, "Consumer Index");
7204 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
7206 &fl->ifl_credits, 1, "credits available");
7207 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
7209 &fl->ifl_buf_size, 1, "buffer size");
7211 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
7213 &fl->ifl_m_enqueued, "mbufs allocated");
7214 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
7216 &fl->ifl_m_dequeued, "mbufs freed");
7217 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
7219 &fl->ifl_cl_enqueued, "clusters allocated");
7220 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
7222 &fl->ifl_cl_dequeued, "clusters freed");
7230 iflib_request_reset(if_ctx_t ctx)
7234 ctx->ifc_flags |= IFC_DO_RESET;
7238 #ifndef __NO_STRICT_ALIGNMENT
7239 static struct mbuf *
7240 iflib_fixup_rx(struct mbuf *m)
7244 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
7245 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
7246 m->m_data += ETHER_HDR_LEN;
7249 MGETHDR(n, M_NOWAIT, MT_DATA);
7254 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
7255 m->m_data += ETHER_HDR_LEN;
7256 m->m_len -= ETHER_HDR_LEN;
7257 n->m_len = ETHER_HDR_LEN;
7258 M_MOVE_PKTHDR(n, m);
7267 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
7271 ctx = if_getsoftc(ifp);
7273 *nrxr = NRXQSETS(ctx);
7274 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
7275 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
7280 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
7283 if_softc_ctx_t scctx;
7288 ctx = if_getsoftc(ifp);
7289 scctx = &ctx->ifc_softc_ctx;
7292 case DEBUGNET_START:
7293 for (i = 0; i < scctx->isc_nrxqsets; i++) {
7294 rxq = &ctx->ifc_rxqs[i];
7295 for (j = 0; j < rxq->ifr_nfl; j++) {
7297 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
7300 iflib_no_tx_batch = 1;
7308 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
7314 ctx = if_getsoftc(ifp);
7315 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7319 txq = &ctx->ifc_txqs[0];
7320 error = iflib_encap(txq, &m);
7322 (void)iflib_txd_db_check(txq, true);
7327 iflib_debugnet_poll(if_t ifp, int count)
7329 struct epoch_tracker et;
7331 if_softc_ctx_t scctx;
7335 ctx = if_getsoftc(ifp);
7336 scctx = &ctx->ifc_softc_ctx;
7338 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7342 txq = &ctx->ifc_txqs[0];
7343 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
7345 NET_EPOCH_ENTER(et);
7346 for (i = 0; i < scctx->isc_nrxqsets; i++)
7347 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7351 #endif /* DEBUGNET */