2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/kernel.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/syslog.h>
55 #include <sys/taskqueue.h>
56 #include <sys/limits.h>
59 #include <net/if_var.h>
60 #include <net/if_types.h>
61 #include <net/if_media.h>
63 #include <net/ethernet.h>
64 #include <net/mp_ring.h>
67 #include <netinet/in.h>
68 #include <netinet/in_pcb.h>
69 #include <netinet/tcp_lro.h>
70 #include <netinet/in_systm.h>
71 #include <netinet/if_ether.h>
72 #include <netinet/ip.h>
73 #include <netinet/ip6.h>
74 #include <netinet/tcp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet/netdump/netdump.h>
77 #include <netinet6/ip6_var.h>
79 #include <machine/bus.h>
80 #include <machine/in_cksum.h>
85 #include <dev/led/led.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pci_private.h>
90 #include <net/iflib.h>
91 #include <net/iflib_private.h>
95 #if defined(__i386__) || defined(__amd64__)
96 #include <sys/memdesc.h>
97 #include <machine/bus.h>
98 #include <machine/md_var.h>
99 #include <machine/specialreg.h>
100 #include <x86/include/busdma_impl.h>
101 #include <x86/iommu/busdma_dmar.h>
105 #include <dev/pci/pci_iov.h>
108 #include <sys/bitstring.h>
110 * enable accounting of every mbuf as it comes in to and goes out of
111 * iflib's software descriptor references
113 #define MEMORY_LOGGING 0
115 * Enable mbuf vectors for compressing long mbuf chains
120 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
121 * we prefetch needs to be determined by the time spent in m_free vis a vis
122 * the cost of a prefetch. This will of course vary based on the workload:
123 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
124 * is quite expensive, thus suggesting very little prefetch.
125 * - small packet forwarding which is just returning a single mbuf to
126 * UMA will typically be very fast vis a vis the cost of a memory
133 * - private structures
134 * - iflib private utility functions
136 * - vlan registry and other exported functions
137 * - iflib public core functions
141 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
144 typedef struct iflib_txq *iflib_txq_t;
146 typedef struct iflib_rxq *iflib_rxq_t;
148 typedef struct iflib_fl *iflib_fl_t;
152 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
153 static void iflib_timer(void *arg);
155 typedef struct iflib_filter_info {
156 driver_filter_t *ifi_filter;
157 void *ifi_filter_arg;
158 struct grouptask *ifi_task;
160 } *iflib_filter_info_t;
165 * Pointer to hardware driver's softc
172 if_shared_ctx_t ifc_sctx;
173 struct if_softc_ctx ifc_softc_ctx;
175 struct sx ifc_ctx_sx;
176 struct mtx ifc_state_mtx;
178 iflib_txq_t ifc_txqs;
179 iflib_rxq_t ifc_rxqs;
180 uint32_t ifc_if_flags;
182 uint32_t ifc_max_fl_buf_size;
186 int ifc_watchdog_events;
187 struct cdev *ifc_led_dev;
188 struct resource *ifc_msix_mem;
190 struct if_irq ifc_legacy_irq;
191 struct grouptask ifc_admin_task;
192 struct grouptask ifc_vflr_task;
193 struct iflib_filter_info ifc_filter_info;
194 struct ifmedia ifc_media;
196 struct sysctl_oid *ifc_sysctl_node;
197 uint16_t ifc_sysctl_ntxqs;
198 uint16_t ifc_sysctl_nrxqs;
199 uint16_t ifc_sysctl_qs_eq_override;
200 uint16_t ifc_sysctl_rx_budget;
201 uint16_t ifc_sysctl_tx_abdicate;
203 qidx_t ifc_sysctl_ntxds[8];
204 qidx_t ifc_sysctl_nrxds[8];
205 struct if_txrx ifc_txrx;
206 #define isc_txd_encap ifc_txrx.ift_txd_encap
207 #define isc_txd_flush ifc_txrx.ift_txd_flush
208 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
209 #define isc_rxd_available ifc_txrx.ift_rxd_available
210 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
212 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
213 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
214 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
215 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
216 eventhandler_tag ifc_vlan_attach_event;
217 eventhandler_tag ifc_vlan_detach_event;
218 uint8_t ifc_mac[ETHER_ADDR_LEN];
219 char ifc_mtx_name[16];
224 iflib_get_softc(if_ctx_t ctx)
227 return (ctx->ifc_softc);
231 iflib_get_dev(if_ctx_t ctx)
234 return (ctx->ifc_dev);
238 iflib_get_ifp(if_ctx_t ctx)
241 return (ctx->ifc_ifp);
245 iflib_get_media(if_ctx_t ctx)
248 return (&ctx->ifc_media);
252 iflib_get_flags(if_ctx_t ctx)
254 return (ctx->ifc_flags);
258 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
261 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN);
265 iflib_get_softc_ctx(if_ctx_t ctx)
268 return (&ctx->ifc_softc_ctx);
272 iflib_get_sctx(if_ctx_t ctx)
275 return (ctx->ifc_sctx);
278 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
279 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
280 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
282 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
283 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
285 #define RX_SW_DESC_MAP_CREATED (1 << 0)
286 #define TX_SW_DESC_MAP_CREATED (1 << 1)
287 #define RX_SW_DESC_INUSE (1 << 3)
288 #define TX_SW_DESC_MAPPED (1 << 4)
290 #define M_TOOBIG M_PROTO1
292 typedef struct iflib_sw_rx_desc_array {
293 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
294 struct mbuf **ifsd_m; /* pkthdr mbufs */
295 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
297 } iflib_rxsd_array_t;
299 typedef struct iflib_sw_tx_desc_array {
300 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
301 struct mbuf **ifsd_m; /* pkthdr mbufs */
306 /* magic number that should be high enough for any hardware */
307 #define IFLIB_MAX_TX_SEGS 128
308 /* bnxt supports 64 with hardware LRO enabled */
309 #define IFLIB_MAX_RX_SEGS 64
310 #define IFLIB_RX_COPY_THRESH 128
311 #define IFLIB_MAX_RX_REFRESH 32
312 /* The minimum descriptors per second before we start coalescing */
313 #define IFLIB_MIN_DESC_SEC 16384
314 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
315 #define IFLIB_QUEUE_IDLE 0
316 #define IFLIB_QUEUE_HUNG 1
317 #define IFLIB_QUEUE_WORKING 2
318 /* maximum number of txqs that can share an rx interrupt */
319 #define IFLIB_MAX_TX_SHARED_INTR 4
321 /* this should really scale with ring size - this is a fairly arbitrary value */
322 #define TX_BATCH_SIZE 32
324 #define IFLIB_RESTART_BUDGET 8
327 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
328 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
329 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
333 qidx_t ift_cidx_processed;
336 uint8_t ift_br_offset;
337 uint16_t ift_npending;
338 uint16_t ift_db_pending;
339 uint16_t ift_rs_pending;
341 uint8_t ift_txd_size[8];
342 uint64_t ift_processed;
343 uint64_t ift_cleaned;
344 uint64_t ift_cleaned_prev;
346 uint64_t ift_enqueued;
347 uint64_t ift_dequeued;
349 uint64_t ift_no_tx_dma_setup;
350 uint64_t ift_no_desc_avail;
351 uint64_t ift_mbuf_defrag_failed;
352 uint64_t ift_mbuf_defrag;
353 uint64_t ift_map_failed;
354 uint64_t ift_txd_encap_efbig;
355 uint64_t ift_pullups;
356 uint64_t ift_last_timer_tick;
359 struct mtx ift_db_mtx;
361 /* constant values */
363 struct ifmp_ring *ift_br;
364 struct grouptask ift_task;
367 struct callout ift_timer;
369 if_txsd_vec_t ift_sds;
372 uint8_t ift_update_freq;
373 struct iflib_filter_info ift_filter_info;
374 bus_dma_tag_t ift_desc_tag;
375 bus_dma_tag_t ift_tso_desc_tag;
376 iflib_dma_info_t ift_ifdi;
377 #define MTX_NAME_LEN 16
378 char ift_mtx_name[MTX_NAME_LEN];
379 char ift_db_mtx_name[MTX_NAME_LEN];
380 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
381 #ifdef IFLIB_DIAGNOSTICS
382 uint64_t ift_cpu_exec_count[256];
384 } __aligned(CACHE_LINE_SIZE);
391 uint8_t ifl_rxd_size;
393 uint64_t ifl_m_enqueued;
394 uint64_t ifl_m_dequeued;
395 uint64_t ifl_cl_enqueued;
396 uint64_t ifl_cl_dequeued;
400 bitstr_t *ifl_rx_bitmap;
404 uint16_t ifl_buf_size;
407 iflib_rxsd_array_t ifl_sds;
410 bus_dma_tag_t ifl_desc_tag;
411 iflib_dma_info_t ifl_ifdi;
412 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
413 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
414 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
415 } __aligned(CACHE_LINE_SIZE);
418 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
424 else if (pidx < cidx)
425 used = size - cidx + pidx;
426 else if (gen == 0 && pidx == cidx)
428 else if (gen == 1 && pidx == cidx)
436 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
438 #define IDXDIFF(head, tail, wrap) \
439 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
442 /* If there is a separate completion queue -
443 * these are the cq cidx and pidx. Otherwise
450 uint8_t ifr_fl_offset;
456 uint8_t ifr_lro_enabled;
459 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
460 struct lro_ctrl ifr_lc;
461 struct grouptask ifr_task;
462 struct iflib_filter_info ifr_filter_info;
463 iflib_dma_info_t ifr_ifdi;
465 /* dynamically allocate if any drivers need a value substantially larger than this */
466 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
467 #ifdef IFLIB_DIAGNOSTICS
468 uint64_t ifr_cpu_exec_count[256];
470 } __aligned(CACHE_LINE_SIZE);
472 typedef struct if_rxsd {
474 struct mbuf **ifsd_m;
479 /* multiple of word size */
481 #define PKT_INFO_SIZE 6
482 #define RXD_INFO_SIZE 5
483 #define PKT_TYPE uint64_t
485 #define PKT_INFO_SIZE 11
486 #define RXD_INFO_SIZE 8
487 #define PKT_TYPE uint32_t
489 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
490 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
492 typedef struct if_pkt_info_pad {
493 PKT_TYPE pkt_val[PKT_INFO_SIZE];
494 } *if_pkt_info_pad_t;
495 typedef struct if_rxd_info_pad {
496 PKT_TYPE rxd_val[RXD_INFO_SIZE];
497 } *if_rxd_info_pad_t;
499 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
500 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
504 pkt_info_zero(if_pkt_info_t pi)
506 if_pkt_info_pad_t pi_pad;
508 pi_pad = (if_pkt_info_pad_t)pi;
509 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
510 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
512 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
513 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
517 static device_method_t iflib_pseudo_methods[] = {
518 DEVMETHOD(device_attach, noop_attach),
519 DEVMETHOD(device_detach, iflib_pseudo_detach),
523 driver_t iflib_pseudodriver = {
524 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
528 rxd_info_zero(if_rxd_info_t ri)
530 if_rxd_info_pad_t ri_pad;
533 ri_pad = (if_rxd_info_pad_t)ri;
534 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
535 ri_pad->rxd_val[i] = 0;
536 ri_pad->rxd_val[i+1] = 0;
537 ri_pad->rxd_val[i+2] = 0;
538 ri_pad->rxd_val[i+3] = 0;
541 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
546 * Only allow a single packet to take up most 1/nth of the tx ring
548 #define MAX_SINGLE_PACKET_FRACTION 12
549 #define IF_BAD_DMA (bus_addr_t)-1
551 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
553 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
554 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
555 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
556 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
559 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
560 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
561 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
562 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
566 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
567 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
570 iflib_set_detach(if_ctx_t ctx)
573 ctx->ifc_flags |= IFC_IN_DETACH;
577 /* Our boot-time initialization hook */
578 static int iflib_module_event_handler(module_t, int, void *);
580 static moduledata_t iflib_moduledata = {
582 iflib_module_event_handler,
586 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
587 MODULE_VERSION(iflib, 1);
589 MODULE_DEPEND(iflib, pci, 1, 1, 1);
590 MODULE_DEPEND(iflib, ether, 1, 1, 1);
592 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
593 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
595 #ifndef IFLIB_DEBUG_COUNTERS
597 #define IFLIB_DEBUG_COUNTERS 1
599 #define IFLIB_DEBUG_COUNTERS 0
600 #endif /* !INVARIANTS */
603 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
604 "iflib driver parameters");
607 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
609 static int iflib_min_tx_latency = 0;
610 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
611 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
612 static int iflib_no_tx_batch = 0;
613 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
614 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
617 #if IFLIB_DEBUG_COUNTERS
619 static int iflib_tx_seen;
620 static int iflib_tx_sent;
621 static int iflib_tx_encap;
622 static int iflib_rx_allocs;
623 static int iflib_fl_refills;
624 static int iflib_fl_refills_large;
625 static int iflib_tx_frees;
627 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
628 &iflib_tx_seen, 0, "# tx mbufs seen");
629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
630 &iflib_tx_sent, 0, "# tx mbufs sent");
631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
632 &iflib_tx_encap, 0, "# tx mbufs encapped");
633 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
634 &iflib_tx_frees, 0, "# tx frees");
635 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
636 &iflib_rx_allocs, 0, "# rx allocations");
637 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
638 &iflib_fl_refills, 0, "# refills");
639 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
640 &iflib_fl_refills_large, 0, "# large refills");
643 static int iflib_txq_drain_flushing;
644 static int iflib_txq_drain_oactive;
645 static int iflib_txq_drain_notready;
647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
648 &iflib_txq_drain_flushing, 0, "# drain flushes");
649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
650 &iflib_txq_drain_oactive, 0, "# drain oactives");
651 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
652 &iflib_txq_drain_notready, 0, "# drain notready");
655 static int iflib_encap_load_mbuf_fail;
656 static int iflib_encap_pad_mbuf_fail;
657 static int iflib_encap_txq_avail_fail;
658 static int iflib_encap_txd_encap_fail;
660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
661 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
663 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
665 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
666 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
667 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
669 static int iflib_task_fn_rxs;
670 static int iflib_rx_intr_enables;
671 static int iflib_fast_intrs;
672 static int iflib_rx_unavail;
673 static int iflib_rx_ctx_inactive;
674 static int iflib_rx_if_input;
675 static int iflib_rx_mbuf_null;
676 static int iflib_rxd_flush;
678 static int iflib_verbose_debug;
680 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
681 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
683 &iflib_rx_intr_enables, 0, "# rx intr enables");
684 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
685 &iflib_fast_intrs, 0, "# fast_intr calls");
686 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
687 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
688 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
689 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
691 &iflib_rx_if_input, 0, "# times rxeof called if_input");
692 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD,
693 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf");
694 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
695 &iflib_rxd_flush, 0, "# times rxd_flush called");
696 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
697 &iflib_verbose_debug, 0, "enable verbose debugging");
699 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
701 iflib_debug_reset(void)
703 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
704 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
705 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
706 iflib_txq_drain_notready =
707 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
708 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
709 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
711 iflib_rx_ctx_inactive = iflib_rx_if_input =
712 iflib_rx_mbuf_null = iflib_rxd_flush = 0;
716 #define DBG_COUNTER_INC(name)
717 static void iflib_debug_reset(void) {}
720 #define IFLIB_DEBUG 0
722 static void iflib_tx_structures_free(if_ctx_t ctx);
723 static void iflib_rx_structures_free(if_ctx_t ctx);
724 static int iflib_queues_alloc(if_ctx_t ctx);
725 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
726 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
727 static int iflib_qset_structures_setup(if_ctx_t ctx);
728 static int iflib_msix_init(if_ctx_t ctx);
729 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
730 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
731 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
733 static void iflib_altq_if_start(if_t ifp);
734 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
736 static int iflib_register(if_ctx_t);
737 static void iflib_init_locked(if_ctx_t ctx);
738 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
739 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
740 static void iflib_ifmp_purge(iflib_txq_t txq);
741 static void _iflib_pre_assert(if_softc_ctx_t scctx);
742 static void iflib_if_init_locked(if_ctx_t ctx);
743 static void iflib_free_intr_mem(if_ctx_t ctx);
744 #ifndef __NO_STRICT_ALIGNMENT
745 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
748 NETDUMP_DEFINE(iflib);
751 #include <sys/selinfo.h>
752 #include <net/netmap.h>
753 #include <dev/netmap/netmap_kern.h>
755 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
757 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
760 * device-specific sysctl variables:
762 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
763 * During regular operations the CRC is stripped, but on some
764 * hardware reception of frames not multiple of 64 is slower,
765 * so using crcstrip=0 helps in benchmarks.
767 * iflib_rx_miss, iflib_rx_miss_bufs:
768 * count packets that might be missed due to lost interrupts.
770 SYSCTL_DECL(_dev_netmap);
772 * The xl driver by default strips CRCs and we do not override it.
775 int iflib_crcstrip = 1;
776 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
777 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames");
779 int iflib_rx_miss, iflib_rx_miss_bufs;
780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
781 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr");
782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
783 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs");
786 * Register/unregister. We are already under netmap lock.
787 * Only called on the first register or the last unregister.
790 iflib_netmap_register(struct netmap_adapter *na, int onoff)
792 struct ifnet *ifp = na->ifp;
793 if_ctx_t ctx = ifp->if_softc;
797 IFDI_INTR_DISABLE(ctx);
799 /* Tell the stack that the interface is no longer active */
800 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
803 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
805 /* enable or disable flags and callbacks in na and ifp */
807 nm_set_native_flags(na);
809 nm_clear_native_flags(na);
812 iflib_init_locked(ctx);
813 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
814 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
816 nm_clear_native_flags(na);
822 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
824 struct netmap_adapter *na = kring->na;
825 u_int const lim = kring->nkr_num_slots - 1;
826 u_int head = kring->rhead;
827 struct netmap_ring *ring = kring->ring;
829 struct if_rxd_update iru;
830 if_ctx_t ctx = rxq->ifr_ctx;
831 iflib_fl_t fl = &rxq->ifr_fl[0];
832 uint32_t refill_pidx, nic_i;
833 #if IFLIB_DEBUG_COUNTERS
837 if (nm_i == head && __predict_true(!init))
839 iru_init(&iru, rxq, 0 /* flid */);
840 map = fl->ifl_sds.ifsd_map;
841 refill_pidx = netmap_idx_k2n(kring, nm_i);
843 * IMPORTANT: we must leave one free slot in the ring,
844 * so move head back by one unit
846 head = nm_prev(head, lim);
848 DBG_COUNTER_INC(fl_refills);
849 while (nm_i != head) {
850 #if IFLIB_DEBUG_COUNTERS
852 DBG_COUNTER_INC(fl_refills_large);
854 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
855 struct netmap_slot *slot = &ring->slot[nm_i];
856 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
857 uint32_t nic_i_dma = refill_pidx;
858 nic_i = netmap_idx_k2n(kring, nm_i);
860 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
862 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
863 return netmap_ring_reinit(kring);
865 fl->ifl_vm_addrs[tmp_pidx] = addr;
866 if (__predict_false(init) && map) {
867 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
868 } else if (map && (slot->flags & NS_BUF_CHANGED)) {
869 /* buffer has changed, reload map */
870 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr);
872 slot->flags &= ~NS_BUF_CHANGED;
874 nm_i = nm_next(nm_i, lim);
875 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
876 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
879 iru.iru_pidx = refill_pidx;
880 iru.iru_count = tmp_pidx+1;
881 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
887 for (int n = 0; n < iru.iru_count; n++) {
888 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma],
889 BUS_DMASYNC_PREREAD);
890 /* XXX - change this to not use the netmap func*/
891 nic_i_dma = nm_next(nic_i_dma, lim);
895 kring->nr_hwcur = head;
898 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
899 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
900 if (__predict_true(nic_i != UINT_MAX)) {
901 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
902 DBG_COUNTER_INC(rxd_flush);
908 * Reconcile kernel and user view of the transmit ring.
910 * All information is in the kring.
911 * Userspace wants to send packets up to the one before kring->rhead,
912 * kernel knows kring->nr_hwcur is the first unsent packet.
914 * Here we push packets out (as many as possible), and possibly
915 * reclaim buffers from previously completed transmission.
917 * The caller (netmap) guarantees that there is only one instance
918 * running at any time. Any interference with other driver
919 * methods should be handled by the individual drivers.
922 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
924 struct netmap_adapter *na = kring->na;
925 struct ifnet *ifp = na->ifp;
926 struct netmap_ring *ring = kring->ring;
927 u_int nm_i; /* index into the netmap kring */
928 u_int nic_i; /* index into the NIC ring */
930 u_int const lim = kring->nkr_num_slots - 1;
931 u_int const head = kring->rhead;
932 struct if_pkt_info pi;
935 * interrupts on every tx packet are expensive so request
936 * them every half ring, or where NS_REPORT is set
938 u_int report_frequency = kring->nkr_num_slots >> 1;
939 /* device-specific */
940 if_ctx_t ctx = ifp->if_softc;
941 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
943 if (txq->ift_sds.ifsd_map)
944 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
945 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
949 * First part: process new packets to send.
950 * nm_i is the current index in the netmap kring,
951 * nic_i is the corresponding index in the NIC ring.
953 * If we have packets to send (nm_i != head)
954 * iterate over the netmap ring, fetch length and update
955 * the corresponding slot in the NIC ring. Some drivers also
956 * need to update the buffer's physical address in the NIC slot
957 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
959 * The netmap_reload_map() calls is especially expensive,
960 * even when (as in this case) the tag is 0, so do only
961 * when the buffer has actually changed.
963 * If possible do not set the report/intr bit on all slots,
964 * but only a few times per ring or when NS_REPORT is set.
966 * Finally, on 10G and faster drivers, it might be useful
967 * to prefetch the next slot and txr entry.
970 nm_i = kring->nr_hwcur;
971 if (nm_i != head) { /* we have new packets to send */
973 pi.ipi_segs = txq->ift_segs;
974 pi.ipi_qsidx = kring->ring_id;
975 nic_i = netmap_idx_k2n(kring, nm_i);
977 __builtin_prefetch(&ring->slot[nm_i]);
978 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
979 if (txq->ift_sds.ifsd_map)
980 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
982 for (n = 0; nm_i != head; n++) {
983 struct netmap_slot *slot = &ring->slot[nm_i];
984 u_int len = slot->len;
986 void *addr = PNMB(na, slot, &paddr);
987 int flags = (slot->flags & NS_REPORT ||
988 nic_i == 0 || nic_i == report_frequency) ?
991 /* device-specific */
993 pi.ipi_segs[0].ds_addr = paddr;
994 pi.ipi_segs[0].ds_len = len;
998 pi.ipi_flags = flags;
1000 /* Fill the slot in the NIC ring. */
1001 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1002 DBG_COUNTER_INC(tx_encap);
1004 /* prefetch for next round */
1005 __builtin_prefetch(&ring->slot[nm_i + 1]);
1006 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1007 if (txq->ift_sds.ifsd_map) {
1008 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1010 NM_CHECK_ADDR_LEN(na, addr, len);
1012 if (slot->flags & NS_BUF_CHANGED) {
1013 /* buffer has changed, reload map */
1014 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr);
1016 /* make sure changes to the buffer are synced */
1017 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i],
1018 BUS_DMASYNC_PREWRITE);
1020 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1021 nm_i = nm_next(nm_i, lim);
1022 nic_i = nm_next(nic_i, lim);
1024 kring->nr_hwcur = nm_i;
1026 /* synchronize the NIC ring */
1027 if (txq->ift_sds.ifsd_map)
1028 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map,
1029 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1031 /* (re)start the tx unit up to slot nic_i (excluded) */
1032 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1036 * Second part: reclaim buffers for completed transmissions.
1038 * If there are unclaimed buffers, attempt to reclaim them.
1039 * If none are reclaimed, and TX IRQs are not in use, do an initial
1040 * minimal delay, then trigger the tx handler which will spin in the
1043 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1044 if (iflib_tx_credits_update(ctx, txq)) {
1045 /* some tx completed, increment avail */
1046 nic_i = txq->ift_cidx_processed;
1047 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1050 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1051 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1052 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1053 iflib_timer, txq, txq->ift_timer.c_cpu);
1059 * Reconcile kernel and user view of the receive ring.
1060 * Same as for the txsync, this routine must be efficient.
1061 * The caller guarantees a single invocations, but races against
1062 * the rest of the driver should be handled here.
1064 * On call, kring->rhead is the first packet that userspace wants
1065 * to keep, and kring->rcur is the wakeup point.
1066 * The kernel has previously reported packets up to kring->rtail.
1068 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1069 * of whether or not we received an interrupt.
1072 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1074 struct netmap_adapter *na = kring->na;
1075 struct netmap_ring *ring = kring->ring;
1076 uint32_t nm_i; /* index into the netmap ring */
1077 uint32_t nic_i; /* index into the NIC ring */
1079 u_int const lim = kring->nkr_num_slots - 1;
1080 u_int const head = kring->rhead;
1081 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1082 struct if_rxd_info ri;
1084 struct ifnet *ifp = na->ifp;
1085 if_ctx_t ctx = ifp->if_softc;
1086 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1087 iflib_fl_t fl = rxq->ifr_fl;
1089 return netmap_ring_reinit(kring);
1091 /* XXX check sync modes */
1092 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1093 if (fl->ifl_sds.ifsd_map == NULL)
1095 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map,
1096 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1099 * First part: import newly received packets.
1101 * nm_i is the index of the next free slot in the netmap ring,
1102 * nic_i is the index of the next received packet in the NIC ring,
1103 * and they may differ in case if_init() has been called while
1104 * in netmap mode. For the receive ring we have
1106 * nic_i = rxr->next_check;
1107 * nm_i = kring->nr_hwtail (previous)
1109 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1111 * rxr->next_check is set to 0 on a ring reinit
1113 if (netmap_no_pendintr || force_update) {
1114 int crclen = iflib_crcstrip ? 0 : 4;
1117 for (i = 0; i < rxq->ifr_nfl; i++) {
1118 fl = &rxq->ifr_fl[i];
1119 nic_i = fl->ifl_cidx;
1120 nm_i = netmap_idx_n2k(kring, nic_i);
1121 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX);
1122 for (n = 0; avail > 0; n++, avail--) {
1124 ri.iri_frags = rxq->ifr_frags;
1125 ri.iri_qsidx = kring->ring_id;
1126 ri.iri_ifp = ctx->ifc_ifp;
1127 ri.iri_cidx = nic_i;
1129 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1130 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1131 ring->slot[nm_i].flags = 0;
1132 if (fl->ifl_sds.ifsd_map)
1133 bus_dmamap_sync(fl->ifl_ifdi->idi_tag,
1134 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1135 nm_i = nm_next(nm_i, lim);
1136 nic_i = nm_next(nic_i, lim);
1138 if (n) { /* update the state variables */
1139 if (netmap_no_pendintr && !force_update) {
1142 iflib_rx_miss_bufs += n;
1144 fl->ifl_cidx = nic_i;
1145 kring->nr_hwtail = nm_i;
1147 kring->nr_kflags &= ~NKR_PENDINTR;
1151 * Second part: skip past packets that userspace has released.
1152 * (kring->nr_hwcur to head excluded),
1153 * and make the buffers available for reception.
1154 * As usual nm_i is the index in the netmap ring,
1155 * nic_i is the index in the NIC ring, and
1156 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1158 /* XXX not sure how this will work with multiple free lists */
1159 nm_i = kring->nr_hwcur;
1161 return (netmap_fl_refill(rxq, kring, nm_i, false));
1165 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1167 struct ifnet *ifp = na->ifp;
1168 if_ctx_t ctx = ifp->if_softc;
1172 IFDI_INTR_ENABLE(ctx);
1174 IFDI_INTR_DISABLE(ctx);
1181 iflib_netmap_attach(if_ctx_t ctx)
1183 struct netmap_adapter na;
1184 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1186 bzero(&na, sizeof(na));
1188 na.ifp = ctx->ifc_ifp;
1189 na.na_flags = NAF_BDG_MAYSLEEP;
1190 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1191 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1193 na.num_tx_desc = scctx->isc_ntxd[0];
1194 na.num_rx_desc = scctx->isc_nrxd[0];
1195 na.nm_txsync = iflib_netmap_txsync;
1196 na.nm_rxsync = iflib_netmap_rxsync;
1197 na.nm_register = iflib_netmap_register;
1198 na.nm_intr = iflib_netmap_intr;
1199 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1200 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1201 return (netmap_attach(&na));
1205 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1207 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1208 struct netmap_slot *slot;
1210 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1213 if (txq->ift_sds.ifsd_map == NULL)
1216 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1219 * In netmap mode, set the map for the packet buffer.
1220 * NOTE: Some drivers (not this one) also need to set
1221 * the physical buffer address in the NIC ring.
1222 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1223 * netmap slot index, si
1225 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1226 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si));
1231 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1233 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1234 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1235 struct netmap_slot *slot;
1238 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1241 nm_i = netmap_idx_n2k(kring, 0);
1242 netmap_fl_refill(rxq, kring, nm_i, true);
1246 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on)
1248 struct netmap_kring *kring;
1250 kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1252 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1253 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1254 netmap_tx_irq(ctx->ifc_ifp, txqid);
1255 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1259 *reset_on = hz / 1000;
1264 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1267 #define iflib_netmap_txq_init(ctx, txq)
1268 #define iflib_netmap_rxq_init(ctx, rxq)
1269 #define iflib_netmap_detach(ifp)
1271 #define iflib_netmap_attach(ctx) (0)
1272 #define netmap_rx_irq(ifp, qid, budget) (0)
1273 #define netmap_tx_irq(ifp, qid) do {} while (0)
1274 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on)
1278 #if defined(__i386__) || defined(__amd64__)
1279 static __inline void
1282 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1284 static __inline void
1285 prefetch2cachelines(void *x)
1287 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1288 #if (CACHE_LINE_SIZE < 128)
1289 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1294 #define prefetch2cachelines(x)
1298 iflib_gen_mac(if_ctx_t ctx)
1302 char uuid[HOSTUUIDLEN+1];
1303 char buf[HOSTUUIDLEN+16];
1305 unsigned char digest[16];
1309 uuid[HOSTUUIDLEN] = 0;
1310 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN);
1311 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev));
1313 * Generate a pseudo-random, deterministic MAC
1314 * address based on the UUID and unit number.
1315 * The FreeBSD Foundation OUI of 58-9C-FC is used.
1318 MD5Update(&mdctx, buf, strlen(buf));
1319 MD5Final(digest, &mdctx);
1330 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1334 fl = &rxq->ifr_fl[flid];
1335 iru->iru_paddrs = fl->ifl_bus_addrs;
1336 iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1337 iru->iru_idxs = fl->ifl_rxd_idxs;
1338 iru->iru_qsidx = rxq->ifr_id;
1339 iru->iru_buf_size = fl->ifl_buf_size;
1340 iru->iru_flidx = fl->ifl_id;
1344 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1348 *(bus_addr_t *) arg = segs[0].ds_addr;
1352 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1355 if_shared_ctx_t sctx = ctx->ifc_sctx;
1356 device_t dev = ctx->ifc_dev;
1358 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1360 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1361 sctx->isc_q_align, 0, /* alignment, bounds */
1362 BUS_SPACE_MAXADDR, /* lowaddr */
1363 BUS_SPACE_MAXADDR, /* highaddr */
1364 NULL, NULL, /* filter, filterarg */
1367 size, /* maxsegsize */
1368 BUS_DMA_ALLOCNOW, /* flags */
1369 NULL, /* lockfunc */
1374 "%s: bus_dma_tag_create failed: %d\n",
1379 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1380 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1383 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1384 __func__, (uintmax_t)size, err);
1388 dma->idi_paddr = IF_BAD_DMA;
1389 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1390 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1391 if (err || dma->idi_paddr == IF_BAD_DMA) {
1393 "%s: bus_dmamap_load failed: %d\n",
1398 dma->idi_size = size;
1402 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1404 bus_dma_tag_destroy(dma->idi_tag);
1406 dma->idi_tag = NULL;
1412 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1415 iflib_dma_info_t *dmaiter;
1418 for (i = 0; i < count; i++, dmaiter++) {
1419 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1423 iflib_dma_free_multi(dmalist, i);
1428 iflib_dma_free(iflib_dma_info_t dma)
1430 if (dma->idi_tag == NULL)
1432 if (dma->idi_paddr != IF_BAD_DMA) {
1433 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1435 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1436 dma->idi_paddr = IF_BAD_DMA;
1438 if (dma->idi_vaddr != NULL) {
1439 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1440 dma->idi_vaddr = NULL;
1442 bus_dma_tag_destroy(dma->idi_tag);
1443 dma->idi_tag = NULL;
1447 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1450 iflib_dma_info_t *dmaiter = dmalist;
1452 for (i = 0; i < count; i++, dmaiter++)
1453 iflib_dma_free(*dmaiter);
1456 #ifdef EARLY_AP_STARTUP
1457 static const int iflib_started = 1;
1460 * We used to abuse the smp_started flag to decide if the queues have been
1461 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1462 * That gave bad races, since the SYSINIT() runs strictly after smp_started
1463 * is set. Run a SYSINIT() strictly after that to just set a usable
1467 static int iflib_started;
1470 iflib_record_started(void *arg)
1475 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1476 iflib_record_started, NULL);
1480 iflib_fast_intr(void *arg)
1482 iflib_filter_info_t info = arg;
1483 struct grouptask *gtask = info->ifi_task;
1485 return (FILTER_HANDLED);
1487 DBG_COUNTER_INC(fast_intrs);
1488 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1489 return (FILTER_HANDLED);
1491 GROUPTASK_ENQUEUE(gtask);
1492 return (FILTER_HANDLED);
1496 iflib_fast_intr_rxtx(void *arg)
1498 iflib_filter_info_t info = arg;
1499 struct grouptask *gtask = info->ifi_task;
1500 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1501 if_ctx_t ctx = NULL;;
1505 return (FILTER_HANDLED);
1507 DBG_COUNTER_INC(fast_intrs);
1508 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1509 return (FILTER_HANDLED);
1511 MPASS(rxq->ifr_ntxqirq);
1512 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1513 qidx_t txqid = rxq->ifr_txqid[i];
1517 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) {
1518 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1521 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
1523 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1524 cidx = rxq->ifr_cq_cidx;
1526 cidx = rxq->ifr_fl[0].ifl_cidx;
1527 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1528 GROUPTASK_ENQUEUE(gtask);
1530 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1531 DBG_COUNTER_INC(rx_intr_enables);
1533 return (FILTER_HANDLED);
1538 iflib_fast_intr_ctx(void *arg)
1540 iflib_filter_info_t info = arg;
1541 struct grouptask *gtask = info->ifi_task;
1544 return (FILTER_HANDLED);
1546 DBG_COUNTER_INC(fast_intrs);
1547 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED)
1548 return (FILTER_HANDLED);
1550 GROUPTASK_ENQUEUE(gtask);
1551 return (FILTER_HANDLED);
1555 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1556 driver_filter_t filter, driver_intr_t handler, void *arg,
1560 struct resource *res;
1562 device_t dev = ctx->ifc_dev;
1565 if (ctx->ifc_flags & IFC_LEGACY)
1566 flags |= RF_SHAREABLE;
1569 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags);
1572 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1576 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1577 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1578 filter, handler, arg, &tag);
1581 "failed to setup interrupt for rid %d, name %s: %d\n",
1582 rid, name ? name : "unknown", rc);
1585 bus_describe_intr(dev, res, tag, "%s", name);
1592 /*********************************************************************
1594 * Allocate memory for tx_buffer structures. The tx_buffer stores all
1595 * the information needed to transmit a packet on the wire. This is
1596 * called only once at attach, setup is done every reset.
1598 **********************************************************************/
1601 iflib_txsd_alloc(iflib_txq_t txq)
1603 if_ctx_t ctx = txq->ift_ctx;
1604 if_shared_ctx_t sctx = ctx->ifc_sctx;
1605 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1606 device_t dev = ctx->ifc_dev;
1607 bus_size_t tsomaxsize;
1608 int err, nsegments, ntsosegments;
1610 nsegments = scctx->isc_tx_nsegments;
1611 ntsosegments = scctx->isc_tx_tso_segments_max;
1612 tsomaxsize = scctx->isc_tx_tso_size_max;
1613 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1614 tsomaxsize += sizeof(struct ether_vlan_header);
1615 MPASS(scctx->isc_ntxd[0] > 0);
1616 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1617 MPASS(nsegments > 0);
1618 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1619 MPASS(ntsosegments > 0);
1620 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1624 * Setup DMA descriptor areas.
1626 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1627 1, 0, /* alignment, bounds */
1628 BUS_SPACE_MAXADDR, /* lowaddr */
1629 BUS_SPACE_MAXADDR, /* highaddr */
1630 NULL, NULL, /* filter, filterarg */
1631 sctx->isc_tx_maxsize, /* maxsize */
1632 nsegments, /* nsegments */
1633 sctx->isc_tx_maxsegsize, /* maxsegsize */
1635 NULL, /* lockfunc */
1636 NULL, /* lockfuncarg */
1637 &txq->ift_desc_tag))) {
1638 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1639 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1640 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1643 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) &
1644 (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1645 1, 0, /* alignment, bounds */
1646 BUS_SPACE_MAXADDR, /* lowaddr */
1647 BUS_SPACE_MAXADDR, /* highaddr */
1648 NULL, NULL, /* filter, filterarg */
1649 tsomaxsize, /* maxsize */
1650 ntsosegments, /* nsegments */
1651 sctx->isc_tso_maxsegsize,/* maxsegsize */
1653 NULL, /* lockfunc */
1654 NULL, /* lockfuncarg */
1655 &txq->ift_tso_desc_tag))) {
1656 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err);
1660 if (!(txq->ift_sds.ifsd_flags =
1661 (uint8_t *) malloc(sizeof(uint8_t) *
1662 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1663 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1667 if (!(txq->ift_sds.ifsd_m =
1668 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1669 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1670 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1675 /* Create the descriptor buffer dma maps */
1676 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1677 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1680 if (!(txq->ift_sds.ifsd_map =
1681 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1682 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1687 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1688 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]);
1690 device_printf(dev, "Unable to create TX DMA map\n");
1697 /* We free all, it handles case where we are in the middle */
1698 iflib_tx_structures_free(ctx);
1703 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1708 if (txq->ift_sds.ifsd_map != NULL)
1709 map = txq->ift_sds.ifsd_map[i];
1711 bus_dmamap_unload(txq->ift_desc_tag, map);
1712 bus_dmamap_destroy(txq->ift_desc_tag, map);
1713 txq->ift_sds.ifsd_map[i] = NULL;
1718 iflib_txq_destroy(iflib_txq_t txq)
1720 if_ctx_t ctx = txq->ift_ctx;
1722 for (int i = 0; i < txq->ift_size; i++)
1723 iflib_txsd_destroy(ctx, txq, i);
1724 if (txq->ift_sds.ifsd_map != NULL) {
1725 free(txq->ift_sds.ifsd_map, M_IFLIB);
1726 txq->ift_sds.ifsd_map = NULL;
1728 if (txq->ift_sds.ifsd_m != NULL) {
1729 free(txq->ift_sds.ifsd_m, M_IFLIB);
1730 txq->ift_sds.ifsd_m = NULL;
1732 if (txq->ift_sds.ifsd_flags != NULL) {
1733 free(txq->ift_sds.ifsd_flags, M_IFLIB);
1734 txq->ift_sds.ifsd_flags = NULL;
1736 if (txq->ift_desc_tag != NULL) {
1737 bus_dma_tag_destroy(txq->ift_desc_tag);
1738 txq->ift_desc_tag = NULL;
1740 if (txq->ift_tso_desc_tag != NULL) {
1741 bus_dma_tag_destroy(txq->ift_tso_desc_tag);
1742 txq->ift_tso_desc_tag = NULL;
1747 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1751 mp = &txq->ift_sds.ifsd_m[i];
1755 if (txq->ift_sds.ifsd_map != NULL) {
1756 bus_dmamap_sync(txq->ift_desc_tag,
1757 txq->ift_sds.ifsd_map[i],
1758 BUS_DMASYNC_POSTWRITE);
1759 bus_dmamap_unload(txq->ift_desc_tag,
1760 txq->ift_sds.ifsd_map[i]);
1763 DBG_COUNTER_INC(tx_frees);
1768 iflib_txq_setup(iflib_txq_t txq)
1770 if_ctx_t ctx = txq->ift_ctx;
1771 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1772 if_shared_ctx_t sctx = ctx->ifc_sctx;
1773 iflib_dma_info_t di;
1776 /* Set number of descriptors available */
1777 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1778 /* XXX make configurable */
1779 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1782 txq->ift_cidx_processed = 0;
1783 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1784 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1786 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1787 bzero((void *)di->idi_vaddr, di->idi_size);
1789 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1790 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1791 bus_dmamap_sync(di->idi_tag, di->idi_map,
1792 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1796 /*********************************************************************
1798 * Allocate memory for rx_buffer structures. Since we use one
1799 * rx_buffer per received packet, the maximum number of rx_buffer's
1800 * that we'll need is equal to the number of receive descriptors
1801 * that we've allocated.
1803 **********************************************************************/
1805 iflib_rxsd_alloc(iflib_rxq_t rxq)
1807 if_ctx_t ctx = rxq->ifr_ctx;
1808 if_shared_ctx_t sctx = ctx->ifc_sctx;
1809 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1810 device_t dev = ctx->ifc_dev;
1814 MPASS(scctx->isc_nrxd[0] > 0);
1815 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1818 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1819 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1820 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1821 1, 0, /* alignment, bounds */
1822 BUS_SPACE_MAXADDR, /* lowaddr */
1823 BUS_SPACE_MAXADDR, /* highaddr */
1824 NULL, NULL, /* filter, filterarg */
1825 sctx->isc_rx_maxsize, /* maxsize */
1826 sctx->isc_rx_nsegments, /* nsegments */
1827 sctx->isc_rx_maxsegsize, /* maxsegsize */
1829 NULL, /* lockfunc */
1833 device_printf(dev, "%s: bus_dma_tag_create failed %d\n",
1837 if (!(fl->ifl_sds.ifsd_flags =
1838 (uint8_t *) malloc(sizeof(uint8_t) *
1839 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1840 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1844 if (!(fl->ifl_sds.ifsd_m =
1845 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1846 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1847 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1851 if (!(fl->ifl_sds.ifsd_cl =
1852 (caddr_t *) malloc(sizeof(caddr_t) *
1853 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1854 device_printf(dev, "Unable to allocate tx_buffer memory\n");
1859 /* Create the descriptor buffer dma maps */
1860 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__)))
1861 if ((ctx->ifc_flags & IFC_DMAR) == 0)
1864 if (!(fl->ifl_sds.ifsd_map =
1865 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1866 device_printf(dev, "Unable to allocate tx_buffer map memory\n");
1871 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1872 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]);
1874 device_printf(dev, "Unable to create RX buffer DMA map\n");
1883 iflib_rx_structures_free(ctx);
1889 * Internal service routines
1892 struct rxq_refill_cb_arg {
1894 bus_dma_segment_t seg;
1899 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1901 struct rxq_refill_cb_arg *cb_arg = arg;
1903 cb_arg->error = error;
1904 cb_arg->seg = segs[0];
1905 cb_arg->nseg = nseg;
1910 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR)
1912 #define IS_DMAR(ctx) (0)
1916 * rxq_refill - refill an rxq free-buffer list
1917 * @ctx: the iflib context
1918 * @rxq: the free-list to refill
1919 * @n: the number of new buffers to allocate
1921 * (Re)populate an rxq free-buffer list with up to @n new packet buffers.
1922 * The caller must assure that @n does not exceed the queue's capacity.
1925 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1928 int idx, frag_idx = fl->ifl_fragidx;
1929 int pidx = fl->ifl_pidx;
1933 struct if_rxd_update iru;
1934 bus_dmamap_t *sd_map;
1940 sd_m = fl->ifl_sds.ifsd_m;
1941 sd_map = fl->ifl_sds.ifsd_map;
1942 sd_cl = fl->ifl_sds.ifsd_cl;
1943 sd_flags = fl->ifl_sds.ifsd_flags;
1945 credits = fl->ifl_credits;
1949 MPASS(credits + n <= fl->ifl_size);
1951 if (pidx < fl->ifl_cidx)
1952 MPASS(pidx + n <= fl->ifl_cidx);
1953 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1954 MPASS(fl->ifl_gen == 0);
1955 if (pidx > fl->ifl_cidx)
1956 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1958 DBG_COUNTER_INC(fl_refills);
1960 DBG_COUNTER_INC(fl_refills_large);
1961 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1964 * We allocate an uninitialized mbuf + cluster, mbuf is
1965 * initialized after rx.
1967 * If the cluster is still set then we know a minimum sized packet was received
1969 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx);
1970 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size))
1971 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1972 if ((cl = sd_cl[frag_idx]) == NULL) {
1973 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1976 fl->ifl_cl_enqueued++;
1979 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
1983 fl->ifl_m_enqueued++;
1986 DBG_COUNTER_INC(rx_allocs);
1987 #if defined(__i386__) || defined(__amd64__)
1988 if (!IS_DMAR(ctx)) {
1989 bus_addr = pmap_kextract((vm_offset_t)cl);
1993 struct rxq_refill_cb_arg cb_arg;
1996 MPASS(sd_map != NULL);
1997 MPASS(sd_map[frag_idx] != NULL);
1998 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx],
1999 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0);
2000 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx],
2001 BUS_DMASYNC_PREREAD);
2003 if (err != 0 || cb_arg.error) {
2007 if (fl->ifl_zone == zone_pack)
2008 uma_zfree(fl->ifl_zone, cl);
2013 bus_addr = cb_arg.seg.ds_addr;
2015 bit_set(fl->ifl_rx_bitmap, frag_idx);
2016 sd_flags[frag_idx] |= RX_SW_DESC_INUSE;
2018 MPASS(sd_m[frag_idx] == NULL);
2019 sd_cl[frag_idx] = cl;
2021 fl->ifl_rxd_idxs[i] = frag_idx;
2022 fl->ifl_bus_addrs[i] = bus_addr;
2023 fl->ifl_vm_addrs[i] = cl;
2026 MPASS(credits <= fl->ifl_size);
2027 if (++idx == fl->ifl_size) {
2031 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2032 iru.iru_pidx = pidx;
2034 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2038 fl->ifl_credits = credits;
2044 iru.iru_pidx = pidx;
2046 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2048 fl->ifl_credits = credits;
2050 DBG_COUNTER_INC(rxd_flush);
2051 if (fl->ifl_pidx == 0)
2052 pidx = fl->ifl_size - 1;
2054 pidx = fl->ifl_pidx - 1;
2057 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2058 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2059 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2060 fl->ifl_fragidx = frag_idx;
2063 static __inline void
2064 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2066 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2067 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2069 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2072 MPASS(fl->ifl_credits <= fl->ifl_size);
2073 MPASS(reclaimable == delta);
2075 if (reclaimable > 0)
2076 _iflib_fl_refill(ctx, fl, min(max, reclaimable));
2080 iflib_in_detach(if_ctx_t ctx)
2084 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2090 iflib_fl_bufs_free(iflib_fl_t fl)
2092 iflib_dma_info_t idi = fl->ifl_ifdi;
2095 for (i = 0; i < fl->ifl_size; i++) {
2096 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2097 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i];
2098 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2100 if (*sd_flags & RX_SW_DESC_INUSE) {
2101 if (fl->ifl_sds.ifsd_map != NULL) {
2102 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i];
2103 bus_dmamap_unload(fl->ifl_desc_tag, sd_map);
2104 // XXX: Should this get moved out?
2105 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2106 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map);
2108 if (*sd_m != NULL) {
2109 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2110 uma_zfree(zone_mbuf, *sd_m);
2113 uma_zfree(fl->ifl_zone, *sd_cl);
2116 MPASS(*sd_cl == NULL);
2117 MPASS(*sd_m == NULL);
2120 fl->ifl_m_dequeued++;
2121 fl->ifl_cl_dequeued++;
2127 for (i = 0; i < fl->ifl_size; i++) {
2128 MPASS(fl->ifl_sds.ifsd_flags[i] == 0);
2129 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2130 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2134 * Reset free list values
2136 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2137 bzero(idi->idi_vaddr, idi->idi_size);
2140 /*********************************************************************
2142 * Initialize a receive ring and its buffers.
2144 **********************************************************************/
2146 iflib_fl_setup(iflib_fl_t fl)
2148 iflib_rxq_t rxq = fl->ifl_rxq;
2149 if_ctx_t ctx = rxq->ifr_ctx;
2150 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2152 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2154 ** Free current RX buffer structs and their mbufs
2156 iflib_fl_bufs_free(fl);
2157 /* Now replenish the mbufs */
2158 MPASS(fl->ifl_credits == 0);
2160 * XXX don't set the max_frame_size to larger
2161 * than the hardware can handle
2163 if (sctx->isc_max_frame_size <= 2048)
2164 fl->ifl_buf_size = MCLBYTES;
2165 #ifndef CONTIGMALLOC_WORKS
2167 fl->ifl_buf_size = MJUMPAGESIZE;
2169 else if (sctx->isc_max_frame_size <= 4096)
2170 fl->ifl_buf_size = MJUMPAGESIZE;
2171 else if (sctx->isc_max_frame_size <= 9216)
2172 fl->ifl_buf_size = MJUM9BYTES;
2174 fl->ifl_buf_size = MJUM16BYTES;
2176 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2177 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2178 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2179 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2182 /* avoid pre-allocating zillions of clusters to an idle card
2183 * potentially speeding up attach
2185 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2186 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2187 if (min(128, fl->ifl_size) != fl->ifl_credits)
2193 MPASS(fl->ifl_ifdi != NULL);
2194 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2199 /*********************************************************************
2201 * Free receive ring data structures
2203 **********************************************************************/
2205 iflib_rx_sds_free(iflib_rxq_t rxq)
2210 if (rxq->ifr_fl != NULL) {
2211 for (i = 0; i < rxq->ifr_nfl; i++) {
2212 fl = &rxq->ifr_fl[i];
2213 if (fl->ifl_desc_tag != NULL) {
2214 bus_dma_tag_destroy(fl->ifl_desc_tag);
2215 fl->ifl_desc_tag = NULL;
2217 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2218 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2219 /* XXX destroy maps first */
2220 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2221 fl->ifl_sds.ifsd_m = NULL;
2222 fl->ifl_sds.ifsd_cl = NULL;
2223 fl->ifl_sds.ifsd_map = NULL;
2225 free(rxq->ifr_fl, M_IFLIB);
2227 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2232 * MI independent logic
2236 iflib_timer(void *arg)
2238 iflib_txq_t txq = arg;
2239 if_ctx_t ctx = txq->ift_ctx;
2240 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2241 uint64_t this_tick = ticks;
2242 uint32_t reset_on = hz / 2;
2244 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2247 ** Check on the state of the TX queue(s), this
2248 ** can be done without the lock because its RO
2249 ** and the HUNG state will be static if set.
2251 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2252 txq->ift_last_timer_tick = this_tick;
2253 IFDI_TIMER(ctx, txq->ift_id);
2254 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2255 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2256 (sctx->isc_pause_frames == 0)))
2259 if (ifmp_ring_is_stalled(txq->ift_br))
2260 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2261 txq->ift_cleaned_prev = txq->ift_cleaned;
2264 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2265 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
2267 /* handle any laggards */
2268 if (txq->ift_db_pending)
2269 GROUPTASK_ENQUEUE(&txq->ift_task);
2271 sctx->isc_pause_frames = 0;
2272 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2273 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2276 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n",
2277 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2280 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2281 iflib_admin_intr_deferred(ctx);
2286 iflib_init_locked(if_ctx_t ctx)
2288 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2289 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2290 if_t ifp = ctx->ifc_ifp;
2294 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2297 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2298 IFDI_INTR_DISABLE(ctx);
2300 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2301 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2302 /* Set hardware offload abilities */
2303 if_clearhwassist(ifp);
2304 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2305 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2306 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2307 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2308 if (if_getcapenable(ifp) & IFCAP_TSO4)
2309 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2310 if (if_getcapenable(ifp) & IFCAP_TSO6)
2311 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2313 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2315 callout_stop(&txq->ift_timer);
2316 CALLOUT_UNLOCK(txq);
2317 iflib_netmap_txq_init(ctx, txq);
2320 i = if_getdrvflags(ifp);
2323 MPASS(if_getdrvflags(ifp) == i);
2324 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2325 /* XXX this should really be done on a per-queue basis */
2326 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2327 MPASS(rxq->ifr_id == i);
2328 iflib_netmap_rxq_init(ctx, rxq);
2331 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2332 if (iflib_fl_setup(fl)) {
2333 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n");
2339 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2340 IFDI_INTR_ENABLE(ctx);
2341 txq = ctx->ifc_txqs;
2342 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2343 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2344 txq->ift_timer.c_cpu);
2348 iflib_media_change(if_t ifp)
2350 if_ctx_t ctx = if_getsoftc(ifp);
2354 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2355 iflib_init_locked(ctx);
2361 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2363 if_ctx_t ctx = if_getsoftc(ifp);
2366 IFDI_UPDATE_ADMIN_STATUS(ctx);
2367 IFDI_MEDIA_STATUS(ctx, ifmr);
2372 iflib_stop(if_ctx_t ctx)
2374 iflib_txq_t txq = ctx->ifc_txqs;
2375 iflib_rxq_t rxq = ctx->ifc_rxqs;
2376 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2377 if_shared_ctx_t sctx = ctx->ifc_sctx;
2378 iflib_dma_info_t di;
2382 /* Tell the stack that the interface is no longer active */
2383 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2385 IFDI_INTR_DISABLE(ctx);
2390 iflib_debug_reset();
2391 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2392 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2393 /* make sure all transmitters have completed before proceeding XXX */
2396 callout_stop(&txq->ift_timer);
2397 CALLOUT_UNLOCK(txq);
2399 /* clean any enqueued buffers */
2400 iflib_ifmp_purge(txq);
2401 /* Free any existing tx buffers. */
2402 for (j = 0; j < txq->ift_size; j++) {
2403 iflib_txsd_free(ctx, txq, j);
2405 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2406 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2407 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2408 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2409 txq->ift_pullups = 0;
2410 ifmp_ring_reset_stats(txq->ift_br);
2411 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2412 bzero((void *)di->idi_vaddr, di->idi_size);
2414 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2415 /* make sure all transmitters have completed before proceeding XXX */
2417 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
2418 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2419 bzero((void *)di->idi_vaddr, di->idi_size);
2420 /* also resets the free lists pidx/cidx */
2421 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2422 iflib_fl_bufs_free(fl);
2426 static inline caddr_t
2427 calc_next_rxd(iflib_fl_t fl, int cidx)
2431 caddr_t start, end, cur, next;
2433 nrxd = fl->ifl_size;
2434 size = fl->ifl_rxd_size;
2435 start = fl->ifl_ifdi->idi_vaddr;
2437 if (__predict_false(size == 0))
2439 cur = start + size*cidx;
2440 end = start + size*nrxd;
2441 next = CACHE_PTR_NEXT(cur);
2442 return (next < end ? next : start);
2446 prefetch_pkts(iflib_fl_t fl, int cidx)
2449 int nrxd = fl->ifl_size;
2453 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2454 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2455 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2456 next_rxd = calc_next_rxd(fl, cidx);
2458 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2459 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2460 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2461 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2462 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2463 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2464 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2465 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2469 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd)
2474 iflib_dma_info_t di;
2478 flid = irf->irf_flid;
2479 cidx = irf->irf_idx;
2480 fl = &rxq->ifr_fl[flid];
2482 sd->ifsd_cidx = cidx;
2483 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx];
2484 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2487 fl->ifl_m_dequeued++;
2489 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2490 prefetch_pkts(fl, cidx);
2491 if (fl->ifl_sds.ifsd_map != NULL) {
2492 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2493 prefetch(&fl->ifl_sds.ifsd_map[next]);
2494 map = fl->ifl_sds.ifsd_map[cidx];
2496 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2497 prefetch(&fl->ifl_sds.ifsd_flags[next]);
2498 bus_dmamap_sync(di->idi_tag, di->idi_map,
2499 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2501 /* not valid assert if bxe really does SGE from non-contiguous elements */
2502 MPASS(fl->ifl_cidx == cidx);
2504 bus_dmamap_unload(fl->ifl_desc_tag, map);
2506 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2507 if (__predict_false(fl->ifl_cidx == 0))
2510 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2512 bit_clear(fl->ifl_rx_bitmap, cidx);
2515 static struct mbuf *
2516 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd)
2518 int i, padlen , flags;
2519 struct mbuf *m, *mh, *mt;
2525 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd);
2527 MPASS(*sd->ifsd_cl != NULL);
2528 MPASS(*sd->ifsd_m != NULL);
2530 /* Don't include zero-length frags */
2531 if (ri->iri_frags[i].irf_len == 0) {
2532 /* XXX we can save the cluster here, but not the mbuf */
2533 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0);
2534 m_free(*sd->ifsd_m);
2541 flags = M_PKTHDR|M_EXT;
2543 padlen = ri->iri_pad;
2548 /* assuming padding is only on the first fragment */
2552 *sd->ifsd_cl = NULL;
2554 /* Can these two be made one ? */
2555 m_init(m, M_NOWAIT, MT_DATA, flags);
2556 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2558 * These must follow m_init and m_cljset
2560 m->m_data += padlen;
2561 ri->iri_len -= padlen;
2562 m->m_len = ri->iri_frags[i].irf_len;
2563 } while (++i < ri->iri_nfrags);
2569 * Process one software descriptor
2571 static struct mbuf *
2572 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2577 /* should I merge this back in now that the two paths are basically duplicated? */
2578 if (ri->iri_nfrags == 1 &&
2579 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2580 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd);
2583 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2584 #ifndef __NO_STRICT_ALIGNMENT
2588 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2589 m->m_len = ri->iri_frags[0].irf_len;
2591 m = assemble_segments(rxq, ri, &sd);
2593 m->m_pkthdr.len = ri->iri_len;
2594 m->m_pkthdr.rcvif = ri->iri_ifp;
2595 m->m_flags |= ri->iri_flags;
2596 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2597 m->m_pkthdr.flowid = ri->iri_flowid;
2598 M_HASHTYPE_SET(m, ri->iri_rsstype);
2599 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2600 m->m_pkthdr.csum_data = ri->iri_csum_data;
2604 #if defined(INET6) || defined(INET)
2606 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2608 CURVNET_SET(lc->ifp->if_vnet);
2610 *v6 = VNET(ip6_forwarding);
2613 *v4 = VNET(ipforwarding);
2619 * Returns true if it's possible this packet could be LROed.
2620 * if it returns false, it is guaranteed that tcp_lro_rx()
2621 * would not return zero.
2624 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2626 struct ether_header *eh;
2629 eh = mtod(m, struct ether_header *);
2630 eh_type = ntohs(eh->ether_type);
2633 case ETHERTYPE_IPV6:
2634 return !v6_forwarding;
2638 return !v4_forwarding;
2646 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2652 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2654 if_ctx_t ctx = rxq->ifr_ctx;
2655 if_shared_ctx_t sctx = ctx->ifc_sctx;
2656 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2659 struct if_rxd_info ri;
2660 int err, budget_left, rx_bytes, rx_pkts;
2664 bool v4_forwarding, v6_forwarding, lro_possible;
2667 * XXX early demux data packets so that if_input processing only handles
2668 * acks in interrupt context
2670 struct mbuf *m, *mh, *mt, *mf;
2672 lro_possible = v4_forwarding = v6_forwarding = false;
2676 rx_pkts = rx_bytes = 0;
2677 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2678 cidxp = &rxq->ifr_cq_cidx;
2680 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2681 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2682 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2683 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2684 DBG_COUNTER_INC(rx_unavail);
2688 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2689 if (__predict_false(!CTX_ACTIVE(ctx))) {
2690 DBG_COUNTER_INC(rx_ctx_inactive);
2694 * Reset client set fields to their default values
2697 ri.iri_qsidx = rxq->ifr_id;
2698 ri.iri_cidx = *cidxp;
2700 ri.iri_frags = rxq->ifr_frags;
2701 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2705 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2706 *cidxp = ri.iri_cidx;
2707 /* Update our consumer index */
2708 /* XXX NB: shurd - check if this is still safe */
2709 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) {
2710 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2711 rxq->ifr_cq_gen = 0;
2713 /* was this only a completion queue message? */
2714 if (__predict_false(ri.iri_nfrags == 0))
2717 MPASS(ri.iri_nfrags != 0);
2718 MPASS(ri.iri_len != 0);
2720 /* will advance the cidx on the corresponding free lists */
2721 m = iflib_rxd_pkt_get(rxq, &ri);
2724 if (avail == 0 && budget_left)
2725 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2727 if (__predict_false(m == NULL)) {
2728 DBG_COUNTER_INC(rx_mbuf_null);
2731 /* imm_pkt: -- cxgb */
2739 /* make sure that we can refill faster than drain */
2740 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2741 __iflib_fl_refill_lt(ctx, fl, budget + 8);
2743 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2745 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2747 while (mh != NULL) {
2750 m->m_nextpkt = NULL;
2751 #ifndef __NO_STRICT_ALIGNMENT
2752 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2755 rx_bytes += m->m_pkthdr.len;
2757 #if defined(INET6) || defined(INET)
2759 if (!lro_possible) {
2760 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2761 if (lro_possible && mf != NULL) {
2762 ifp->if_input(ifp, mf);
2763 DBG_COUNTER_INC(rx_if_input);
2767 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2768 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2769 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2775 ifp->if_input(ifp, m);
2776 DBG_COUNTER_INC(rx_if_input);
2787 ifp->if_input(ifp, mf);
2788 DBG_COUNTER_INC(rx_if_input);
2791 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2792 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2795 * Flush any outstanding LRO work
2797 #if defined(INET6) || defined(INET)
2798 tcp_lro_flush_all(&rxq->ifr_lc);
2802 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2805 ctx->ifc_flags |= IFC_DO_RESET;
2806 iflib_admin_intr_deferred(ctx);
2811 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2812 static inline qidx_t
2813 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2815 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2816 qidx_t minthresh = txq->ift_size / 8;
2817 if (in_use > 4*minthresh)
2818 return (notify_count);
2819 if (in_use > 2*minthresh)
2820 return (notify_count >> 1);
2821 if (in_use > minthresh)
2822 return (notify_count >> 3);
2826 static inline qidx_t
2827 txq_max_rs_deferred(iflib_txq_t txq)
2829 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2830 qidx_t minthresh = txq->ift_size / 8;
2831 if (txq->ift_in_use > 4*minthresh)
2832 return (notify_count);
2833 if (txq->ift_in_use > 2*minthresh)
2834 return (notify_count >> 1);
2835 if (txq->ift_in_use > minthresh)
2836 return (notify_count >> 2);
2840 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2841 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2843 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2844 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2845 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2847 /* forward compatibility for cxgb */
2848 #define FIRST_QSET(ctx) 0
2849 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2850 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2851 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2852 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2854 /* XXX we should be setting this to something other than zero */
2855 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2856 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2857 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2860 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2866 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2867 if (ring || txq->ift_db_pending >= max) {
2868 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2869 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2870 txq->ift_db_pending = txq->ift_npending = 0;
2878 print_pkt(if_pkt_info_t pi)
2880 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2881 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2882 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2883 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2884 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2885 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2889 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2890 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2891 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2892 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2895 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2897 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2898 struct ether_vlan_header *eh;
2902 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2903 M_WRITABLE(m) == 0) {
2904 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2908 DBG_COUNTER_INC(tx_frees);
2914 * Determine where frame payload starts.
2915 * Jump over vlan headers if already present,
2916 * helpful for QinQ too.
2918 if (__predict_false(m->m_len < sizeof(*eh))) {
2920 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
2923 eh = mtod(m, struct ether_vlan_header *);
2924 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2925 pi->ipi_etype = ntohs(eh->evl_proto);
2926 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2928 pi->ipi_etype = ntohs(eh->evl_encap_proto);
2929 pi->ipi_ehdrlen = ETHER_HDR_LEN;
2932 switch (pi->ipi_etype) {
2937 struct ip *ip = NULL;
2938 struct tcphdr *th = NULL;
2941 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
2942 if (__predict_false(m->m_len < minthlen)) {
2944 * if this code bloat is causing too much of a hit
2945 * move it to a separate function and mark it noinline
2947 if (m->m_len == pi->ipi_ehdrlen) {
2950 if (n->m_len >= sizeof(*ip)) {
2951 ip = (struct ip *)n->m_data;
2952 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2953 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2956 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2958 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2962 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
2964 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2965 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2966 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2969 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
2970 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
2971 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
2973 pi->ipi_ip_hlen = ip->ip_hl << 2;
2974 pi->ipi_ipproto = ip->ip_p;
2975 pi->ipi_flags |= IPI_TX_IPV4;
2977 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
2980 /* TCP checksum offload may require TCP header length */
2981 if (IS_TX_OFFLOAD4(pi)) {
2982 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
2983 if (__predict_false(th == NULL)) {
2985 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
2987 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
2989 pi->ipi_tcp_hflags = th->th_flags;
2990 pi->ipi_tcp_hlen = th->th_off << 2;
2991 pi->ipi_tcp_seq = th->th_seq;
2994 if (__predict_false(ip->ip_p != IPPROTO_TCP))
2996 th->th_sum = in_pseudo(ip->ip_src.s_addr,
2997 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
2998 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
2999 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3001 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3009 case ETHERTYPE_IPV6:
3011 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3013 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3015 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3017 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3020 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3022 /* XXX-BZ this will go badly in case of ext hdrs. */
3023 pi->ipi_ipproto = ip6->ip6_nxt;
3024 pi->ipi_flags |= IPI_TX_IPV6;
3026 /* TCP checksum offload may require TCP header length */
3027 if (IS_TX_OFFLOAD6(pi)) {
3028 if (pi->ipi_ipproto == IPPROTO_TCP) {
3029 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3031 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3034 pi->ipi_tcp_hflags = th->th_flags;
3035 pi->ipi_tcp_hlen = th->th_off << 2;
3036 pi->ipi_tcp_seq = th->th_seq;
3039 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3042 * The corresponding flag is set by the stack in the IPv4
3043 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
3044 * So, set it here because the rest of the flow requires it.
3046 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3047 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3048 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3055 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3056 pi->ipi_ip_hlen = 0;
3065 * If dodgy hardware rejects the scatter gather chain we've handed it
3066 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3069 static __noinline struct mbuf *
3070 iflib_remove_mbuf(iflib_txq_t txq)
3073 struct mbuf *m, *mh, **ifsd_m;
3075 pidx = txq->ift_pidx;
3076 ifsd_m = txq->ift_sds.ifsd_m;
3077 ntxd = txq->ift_size;
3078 mh = m = ifsd_m[pidx];
3079 ifsd_m[pidx] = NULL;
3081 txq->ift_dequeued++;
3086 ifsd_m[(pidx + i) & (ntxd -1)] = NULL;
3088 txq->ift_dequeued++;
3097 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map,
3098 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs,
3099 int max_segs, int flags)
3102 if_shared_ctx_t sctx;
3103 if_softc_ctx_t scctx;
3104 int i, next, pidx, err, ntxd, count;
3105 struct mbuf *m, *tmp, **ifsd_m;
3110 * Please don't ever do this
3112 MPASS(__predict_true(m->m_len > 0));
3115 sctx = ctx->ifc_sctx;
3116 scctx = &ctx->ifc_softc_ctx;
3117 ifsd_m = txq->ift_sds.ifsd_m;
3118 ntxd = txq->ift_size;
3119 pidx = txq->ift_pidx;
3121 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags;
3123 err = bus_dmamap_load_mbuf_sg(tag, map,
3124 *m0, segs, nsegs, BUS_DMA_NOWAIT);
3127 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED;
3131 if (__predict_false(m->m_len <= 0)) {
3140 } while (m != NULL);
3141 if (count > *nsegs) {
3143 ifsd_m[pidx]->m_flags |= M_TOOBIG;
3149 next = (pidx + count) & (ntxd-1);
3150 MPASS(ifsd_m[next] == NULL);
3155 } while (m != NULL);
3157 int buflen, sgsize, maxsegsz, max_sgsize;
3163 if (m->m_pkthdr.csum_flags & CSUM_TSO)
3164 maxsegsz = scctx->isc_tx_tso_segsize_max;
3166 maxsegsz = sctx->isc_tx_maxsegsize;
3169 if (__predict_false(m->m_len <= 0)) {
3177 vaddr = (vm_offset_t)m->m_data;
3179 * see if we can't be smarter about physically
3180 * contiguous mappings
3182 next = (pidx + count) & (ntxd-1);
3183 MPASS(ifsd_m[next] == NULL);
3185 txq->ift_enqueued++;
3188 while (buflen > 0) {
3191 max_sgsize = MIN(buflen, maxsegsz);
3192 curaddr = pmap_kextract(vaddr);
3193 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK);
3194 sgsize = MIN(sgsize, max_sgsize);
3195 segs[i].ds_addr = curaddr;
3196 segs[i].ds_len = sgsize;
3204 } while (m != NULL);
3209 *m0 = iflib_remove_mbuf(txq);
3213 static inline caddr_t
3214 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3218 caddr_t start, end, cur, next;
3220 ntxd = txq->ift_size;
3221 size = txq->ift_txd_size[qid];
3222 start = txq->ift_ifdi[qid].idi_vaddr;
3224 if (__predict_false(size == 0))
3226 cur = start + size*cidx;
3227 end = start + size*ntxd;
3228 next = CACHE_PTR_NEXT(cur);
3229 return (next < end ? next : start);
3233 * Pad an mbuf to ensure a minimum ethernet frame size.
3234 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3236 static __noinline int
3237 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3240 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3241 * and ARP message is the smallest common payload I can think of
3243 static char pad[18]; /* just zeros */
3245 struct mbuf *new_head;
3247 if (!M_WRITABLE(*m_head)) {
3248 new_head = m_dup(*m_head, M_NOWAIT);
3249 if (new_head == NULL) {
3251 device_printf(dev, "cannot pad short frame, m_dup() failed");
3252 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3253 DBG_COUNTER_INC(tx_frees);
3260 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3261 n > 0; n -= sizeof(pad))
3262 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3267 device_printf(dev, "cannot pad short frame\n");
3268 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3269 DBG_COUNTER_INC(tx_frees);
3277 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3280 if_shared_ctx_t sctx;
3281 if_softc_ctx_t scctx;
3282 bus_dma_segment_t *segs;
3283 struct mbuf *m_head;
3286 struct if_pkt_info pi;
3288 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3289 bus_dma_tag_t desc_tag;
3292 sctx = ctx->ifc_sctx;
3293 scctx = &ctx->ifc_softc_ctx;
3294 segs = txq->ift_segs;
3295 ntxd = txq->ift_size;
3300 * If we're doing TSO the next descriptor to clean may be quite far ahead
3302 cidx = txq->ift_cidx;
3303 pidx = txq->ift_pidx;
3304 if (ctx->ifc_flags & IFC_PREFETCH) {
3305 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3306 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3307 next_txd = calc_next_txd(txq, cidx, 0);
3311 /* prefetch the next cache line of mbuf pointers and flags */
3312 prefetch(&txq->ift_sds.ifsd_m[next]);
3313 if (txq->ift_sds.ifsd_map != NULL) {
3314 prefetch(&txq->ift_sds.ifsd_map[next]);
3315 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3316 prefetch(&txq->ift_sds.ifsd_flags[next]);
3318 } else if (txq->ift_sds.ifsd_map != NULL)
3319 map = txq->ift_sds.ifsd_map[pidx];
3321 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3322 desc_tag = txq->ift_tso_desc_tag;
3323 max_segs = scctx->isc_tx_tso_segments_max;
3324 MPASS(desc_tag != NULL);
3325 MPASS(max_segs > 0);
3327 desc_tag = txq->ift_desc_tag;
3328 max_segs = scctx->isc_tx_nsegments;
3330 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3331 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3332 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3334 DBG_COUNTER_INC(encap_txd_encap_fail);
3341 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3343 pi.ipi_qsidx = txq->ift_id;
3344 pi.ipi_len = m_head->m_pkthdr.len;
3345 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3346 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0;
3348 /* deliberate bitwise OR to make one condition */
3349 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3350 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3351 DBG_COUNTER_INC(encap_txd_encap_fail);
3358 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT);
3360 if (__predict_false(err)) {
3363 /* try collapse once and defrag once */
3365 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3366 /* try defrag if collapsing fails */
3371 txq->ift_mbuf_defrag++;
3372 m_head = m_defrag(*m_headp, M_NOWAIT);
3375 if (__predict_false(m_head == NULL))
3381 txq->ift_no_tx_dma_setup++;
3384 txq->ift_no_tx_dma_setup++;
3386 DBG_COUNTER_INC(tx_frees);
3390 txq->ift_map_failed++;
3391 DBG_COUNTER_INC(encap_load_mbuf_fail);
3392 DBG_COUNTER_INC(encap_txd_encap_fail);
3397 * XXX assumes a 1 to 1 relationship between segments and
3398 * descriptors - this does not hold true on all drivers, e.g.
3401 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3402 txq->ift_no_desc_avail++;
3404 bus_dmamap_unload(desc_tag, map);
3405 DBG_COUNTER_INC(encap_txq_avail_fail);
3406 DBG_COUNTER_INC(encap_txd_encap_fail);
3407 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3408 GROUPTASK_ENQUEUE(&txq->ift_task);
3412 * On Intel cards we can greatly reduce the number of TX interrupts
3413 * we see by only setting report status on every Nth descriptor.
3414 * However, this also means that the driver will need to keep track
3415 * of the descriptors that RS was set on to check them for the DD bit.
3417 txq->ift_rs_pending += nsegs + 1;
3418 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3419 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3420 pi.ipi_flags |= IPI_TX_INTR;
3421 txq->ift_rs_pending = 0;
3425 pi.ipi_nsegs = nsegs;
3427 MPASS(pidx >= 0 && pidx < txq->ift_size);
3432 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE);
3433 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3435 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3436 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3437 DBG_COUNTER_INC(tx_encap);
3438 MPASS(pi.ipi_new_pidx < txq->ift_size);
3440 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3441 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3442 ndesc += txq->ift_size;
3446 * drivers can need as many as
3449 MPASS(ndesc <= pi.ipi_nsegs + 2);
3450 MPASS(pi.ipi_new_pidx != pidx);
3452 txq->ift_in_use += ndesc;
3455 * We update the last software descriptor again here because there may
3456 * be a sentinel and/or there may be more mbufs than segments
3458 txq->ift_pidx = pi.ipi_new_pidx;
3459 txq->ift_npending += pi.ipi_ndescs;
3461 *m_headp = m_head = iflib_remove_mbuf(txq);
3463 txq->ift_txd_encap_efbig++;
3472 * err can't possibly be non-zero here, so we don't neet to test it
3473 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3478 txq->ift_mbuf_defrag_failed++;
3479 txq->ift_map_failed++;
3481 DBG_COUNTER_INC(tx_frees);
3483 DBG_COUNTER_INC(encap_txd_encap_fail);
3488 iflib_tx_desc_free(iflib_txq_t txq, int n)
3491 uint32_t qsize, cidx, mask, gen;
3492 struct mbuf *m, **ifsd_m;
3493 uint8_t *ifsd_flags;
3494 bus_dmamap_t *ifsd_map;
3497 cidx = txq->ift_cidx;
3499 qsize = txq->ift_size;
3501 hasmap = txq->ift_sds.ifsd_map != NULL;
3502 ifsd_flags = txq->ift_sds.ifsd_flags;
3503 ifsd_m = txq->ift_sds.ifsd_m;
3504 ifsd_map = txq->ift_sds.ifsd_map;
3505 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3509 prefetch(ifsd_m[(cidx + 3) & mask]);
3510 prefetch(ifsd_m[(cidx + 4) & mask]);
3512 if (ifsd_m[cidx] != NULL) {
3513 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3514 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]);
3515 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) {
3517 * does it matter if it's not the TSO tag? If so we'll
3518 * have to add the type to flags
3520 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]);
3521 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED;
3523 if ((m = ifsd_m[cidx]) != NULL) {
3524 /* XXX we don't support any drivers that batch packets yet */
3525 MPASS(m->m_nextpkt == NULL);
3526 /* if the number of clusters exceeds the number of segments
3527 * there won't be space on the ring to save a pointer to each
3528 * cluster so we simply free the list here
3530 if (m->m_flags & M_TOOBIG) {
3535 ifsd_m[cidx] = NULL;
3537 txq->ift_dequeued++;
3539 DBG_COUNTER_INC(tx_frees);
3542 if (__predict_false(++cidx == qsize)) {
3547 txq->ift_cidx = cidx;
3552 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3555 if_ctx_t ctx = txq->ift_ctx;
3557 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3558 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3561 * Need a rate-limiting check so that this isn't called every time
3563 iflib_tx_credits_update(ctx, txq);
3564 reclaim = DESC_RECLAIMABLE(txq);
3566 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3568 if (iflib_verbose_debug) {
3569 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3570 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3577 iflib_tx_desc_free(txq, reclaim);
3578 txq->ift_cleaned += reclaim;
3579 txq->ift_in_use -= reclaim;
3584 static struct mbuf **
3585 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3588 struct mbuf **items;
3591 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3592 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3594 prefetch(items[(cidx + offset) & (size-1)]);
3595 if (remaining > 1) {
3596 prefetch2cachelines(&items[next]);
3597 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3598 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3599 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3601 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3605 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3608 ifmp_ring_check_drainage(txq->ift_br, budget);
3612 iflib_txq_can_drain(struct ifmp_ring *r)
3614 iflib_txq_t txq = r->cookie;
3615 if_ctx_t ctx = txq->ift_ctx;
3617 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) ||
3618 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false));
3622 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3624 iflib_txq_t txq = r->cookie;
3625 if_ctx_t ctx = txq->ift_ctx;
3626 struct ifnet *ifp = ctx->ifc_ifp;
3627 struct mbuf **mp, *m;
3628 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail;
3629 int reclaimed, err, in_use_prev, desc_used;
3630 bool do_prefetch, ring, rang;
3632 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3633 !LINK_ACTIVE(ctx))) {
3634 DBG_COUNTER_INC(txq_drain_notready);
3637 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3638 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3639 avail = IDXDIFF(pidx, cidx, r->size);
3640 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3641 DBG_COUNTER_INC(txq_drain_flushing);
3642 for (i = 0; i < avail; i++) {
3643 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3644 m_free(r->items[(cidx + i) & (r->size-1)]);
3645 r->items[(cidx + i) & (r->size-1)] = NULL;
3650 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3651 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3653 callout_stop(&txq->ift_timer);
3654 CALLOUT_UNLOCK(txq);
3655 DBG_COUNTER_INC(txq_drain_oactive);
3659 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3660 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3661 count = MIN(avail, TX_BATCH_SIZE);
3663 if (iflib_verbose_debug)
3664 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3665 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3667 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3668 avail = TXQ_AVAIL(txq);
3670 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) {
3671 int rem = do_prefetch ? count - i : 0;
3673 mp = _ring_peek_one(r, cidx, i, rem);
3674 MPASS(mp != NULL && *mp != NULL);
3675 if (__predict_false(*mp == (struct mbuf *)txq)) {
3680 in_use_prev = txq->ift_in_use;
3681 err = iflib_encap(txq, mp);
3682 if (__predict_false(err)) {
3683 /* no room - bail out */
3687 /* we can't send this packet - skip it */
3693 DBG_COUNTER_INC(tx_sent);
3694 bytes_sent += m->m_pkthdr.len;
3695 mcast_sent += !!(m->m_flags & M_MCAST);
3696 avail = TXQ_AVAIL(txq);
3698 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3699 desc_used += (txq->ift_in_use - in_use_prev);
3700 ETHER_BPF_MTAP(ifp, m);
3701 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3703 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3706 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3707 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3708 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3709 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3710 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3712 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3714 if (iflib_verbose_debug)
3715 printf("consumed=%d\n", consumed);
3721 iflib_txq_drain_always(struct ifmp_ring *r)
3727 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3735 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3737 callout_stop(&txq->ift_timer);
3738 CALLOUT_UNLOCK(txq);
3740 avail = IDXDIFF(pidx, cidx, r->size);
3741 for (i = 0; i < avail; i++) {
3742 mp = _ring_peek_one(r, cidx, i, avail - i);
3743 if (__predict_false(*mp == (struct mbuf *)txq))
3746 DBG_COUNTER_INC(tx_frees);
3748 MPASS(ifmp_ring_is_stalled(r) == 0);
3753 iflib_ifmp_purge(iflib_txq_t txq)
3755 struct ifmp_ring *r;
3758 r->drain = iflib_txq_drain_free;
3759 r->can_drain = iflib_txq_drain_always;
3761 ifmp_ring_check_drainage(r, r->size);
3763 r->drain = iflib_txq_drain;
3764 r->can_drain = iflib_txq_can_drain;
3768 _task_fn_tx(void *context)
3770 iflib_txq_t txq = context;
3771 if_ctx_t ctx = txq->ift_ctx;
3772 struct ifnet *ifp = ctx->ifc_ifp;
3773 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3775 #ifdef IFLIB_DIAGNOSTICS
3776 txq->ift_cpu_exec_count[curcpu]++;
3778 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3780 if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3781 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3782 netmap_tx_irq(ifp, txq->ift_id);
3783 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3787 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3788 iflib_altq_if_start(ifp);
3790 if (txq->ift_db_pending)
3791 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3793 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3795 * When abdicating, we always need to check drainage, not just when we don't enqueue
3798 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3799 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3800 if (ctx->ifc_flags & IFC_LEGACY)
3801 IFDI_INTR_ENABLE(ctx);
3806 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3807 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3812 _task_fn_rx(void *context)
3814 iflib_rxq_t rxq = context;
3815 if_ctx_t ctx = rxq->ifr_ctx;
3819 #ifdef IFLIB_DIAGNOSTICS
3820 rxq->ifr_cpu_exec_count[curcpu]++;
3822 DBG_COUNTER_INC(task_fn_rxs);
3823 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3827 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3829 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3834 budget = ctx->ifc_sysctl_rx_budget;
3836 budget = 16; /* XXX */
3837 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3838 if (ctx->ifc_flags & IFC_LEGACY)
3839 IFDI_INTR_ENABLE(ctx);
3844 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3845 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver"));
3846 DBG_COUNTER_INC(rx_intr_enables);
3849 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3852 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3856 _task_fn_admin(void *context)
3858 if_ctx_t ctx = context;
3859 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3862 bool oactive, running, do_reset, do_watchdog, in_detach;
3863 uint32_t reset_on = hz / 2;
3866 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3867 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3868 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3869 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3870 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3871 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3874 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3880 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3882 callout_stop(&txq->ift_timer);
3883 CALLOUT_UNLOCK(txq);
3886 ctx->ifc_watchdog_events++;
3887 IFDI_WATCHDOG_RESET(ctx);
3889 IFDI_UPDATE_ADMIN_STATUS(ctx);
3890 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3893 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3894 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on);
3896 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3898 IFDI_LINK_INTR_ENABLE(ctx);
3900 iflib_if_init_locked(ctx);
3903 if (LINK_ACTIVE(ctx) == 0)
3905 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3906 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3911 _task_fn_iov(void *context)
3913 if_ctx_t ctx = context;
3915 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3916 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3920 IFDI_VFLR_HANDLE(ctx);
3925 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3928 if_int_delay_info_t info;
3931 info = (if_int_delay_info_t)arg1;
3932 ctx = info->iidi_ctx;
3933 info->iidi_req = req;
3934 info->iidi_oidp = oidp;
3936 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3941 /*********************************************************************
3945 **********************************************************************/
3948 iflib_if_init_locked(if_ctx_t ctx)
3951 iflib_init_locked(ctx);
3956 iflib_if_init(void *arg)
3961 iflib_if_init_locked(ctx);
3966 iflib_if_transmit(if_t ifp, struct mbuf *m)
3968 if_ctx_t ctx = if_getsoftc(ifp);
3972 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3974 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3975 DBG_COUNTER_INC(tx_frees);
3980 MPASS(m->m_nextpkt == NULL);
3981 /* ALTQ-enabled interfaces always use queue 0. */
3983 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3984 qidx = QIDX(ctx, m);
3986 * XXX calculate buf_ring based on flowid (divvy up bits?)
3988 txq = &ctx->ifc_txqs[qidx];
3990 #ifdef DRIVER_BACKPRESSURE
3991 if (txq->ift_closed) {
3993 next = m->m_nextpkt;
3994 m->m_nextpkt = NULL;
3996 DBG_COUNTER_INC(tx_frees);
4008 next = next->m_nextpkt;
4009 } while (next != NULL);
4011 if (count > nitems(marr))
4012 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4013 /* XXX check nextpkt */
4015 /* XXX simplify for now */
4016 DBG_COUNTER_INC(tx_frees);
4019 for (next = m, i = 0; next != NULL; i++) {
4021 next = next->m_nextpkt;
4022 mp[i]->m_nextpkt = NULL;
4025 DBG_COUNTER_INC(tx_seen);
4026 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4029 GROUPTASK_ENQUEUE(&txq->ift_task);
4032 GROUPTASK_ENQUEUE(&txq->ift_task);
4033 /* support forthcoming later */
4034 #ifdef DRIVER_BACKPRESSURE
4035 txq->ift_closed = TRUE;
4037 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4039 DBG_COUNTER_INC(tx_frees);
4047 * The overall approach to integrating iflib with ALTQ is to continue to use
4048 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4049 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4050 * is redundant/unnecessary, but doing so minimizes the amount of
4051 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4052 * redundantly queueing to an intermediate mp_ring is swamped by the
4053 * performance limitations inherent in using ALTQ.
4055 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4056 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4057 * given interface. If ALTQ is enabled for an interface, then all
4058 * transmitted packets for that interface will be submitted to the ALTQ
4059 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4060 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4061 * update stats that the iflib machinery handles, and which is sensitve to
4062 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4063 * will be installed as the start routine for use by ALTQ facilities that
4064 * need to trigger queue drains on a scheduled basis.
4068 iflib_altq_if_start(if_t ifp)
4070 struct ifaltq *ifq = &ifp->if_snd;
4074 IFQ_DEQUEUE_NOLOCK(ifq, m);
4076 iflib_if_transmit(ifp, m);
4077 IFQ_DEQUEUE_NOLOCK(ifq, m);
4083 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4087 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4088 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4090 iflib_altq_if_start(ifp);
4092 err = iflib_if_transmit(ifp, m);
4099 iflib_if_qflush(if_t ifp)
4101 if_ctx_t ctx = if_getsoftc(ifp);
4102 iflib_txq_t txq = ctx->ifc_txqs;
4106 ctx->ifc_flags |= IFC_QFLUSH;
4108 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4109 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4110 iflib_txq_check_drain(txq, 0);
4112 ctx->ifc_flags &= ~IFC_QFLUSH;
4116 * When ALTQ is enabled, this will also take care of purging the
4123 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4124 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4125 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4126 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4129 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4131 if_ctx_t ctx = if_getsoftc(ifp);
4132 struct ifreq *ifr = (struct ifreq *)data;
4133 #if defined(INET) || defined(INET6)
4134 struct ifaddr *ifa = (struct ifaddr *)data;
4136 bool avoid_reset = FALSE;
4137 int err = 0, reinit = 0, bits;
4142 if (ifa->ifa_addr->sa_family == AF_INET)
4146 if (ifa->ifa_addr->sa_family == AF_INET6)
4150 ** Calling init results in link renegotiation,
4151 ** so we avoid doing it when possible.
4154 if_setflagbits(ifp, IFF_UP,0);
4155 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4158 if (!(if_getflags(ifp) & IFF_NOARP))
4159 arp_ifinit(ifp, ifa);
4162 err = ether_ioctl(ifp, command, data);
4166 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4170 bits = if_getdrvflags(ifp);
4171 /* stop the driver and free any clusters before proceeding */
4174 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4176 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4177 ctx->ifc_flags |= IFC_MULTISEG;
4179 ctx->ifc_flags &= ~IFC_MULTISEG;
4181 err = if_setmtu(ifp, ifr->ifr_mtu);
4183 iflib_init_locked(ctx);
4185 if_setdrvflags(ifp, bits);
4191 if (if_getflags(ifp) & IFF_UP) {
4192 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4193 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4194 (IFF_PROMISC | IFF_ALLMULTI)) {
4195 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4199 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4202 ctx->ifc_if_flags = if_getflags(ifp);
4207 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4209 IFDI_INTR_DISABLE(ctx);
4210 IFDI_MULTI_SET(ctx);
4211 IFDI_INTR_ENABLE(ctx);
4217 IFDI_MEDIA_SET(ctx);
4222 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command);
4226 struct ifi2creq i2c;
4228 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4231 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4235 if (i2c.len > sizeof(i2c.data)) {
4240 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4241 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4247 int mask, setmask, oldmask;
4249 oldmask = if_getcapenable(ifp);
4250 mask = ifr->ifr_reqcap ^ oldmask;
4251 mask &= ctx->ifc_softc_ctx.isc_capabilities;
4254 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4256 setmask |= (mask & IFCAP_FLAGS);
4257 setmask |= (mask & IFCAP_WOL);
4260 * If any RX csum has changed, change all the ones that
4261 * are supported by the driver.
4263 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4264 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4265 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4269 * want to ensure that traffic has stopped before we change any of the flags
4273 bits = if_getdrvflags(ifp);
4274 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4277 if_togglecapenable(ifp, setmask);
4279 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4280 iflib_init_locked(ctx);
4282 if_setdrvflags(ifp, bits);
4289 case SIOCGPRIVATE_0:
4293 err = IFDI_PRIV_IOCTL(ctx, command, data);
4297 err = ether_ioctl(ifp, command, data);
4306 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4308 if_ctx_t ctx = if_getsoftc(ifp);
4310 return (IFDI_GET_COUNTER(ctx, cnt));
4313 /*********************************************************************
4315 * OTHER FUNCTIONS EXPORTED TO THE STACK
4317 **********************************************************************/
4320 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4322 if_ctx_t ctx = if_getsoftc(ifp);
4324 if ((void *)ctx != arg)
4327 if ((vtag == 0) || (vtag > 4095))
4331 IFDI_VLAN_REGISTER(ctx, vtag);
4332 /* Re-init to load the changes */
4333 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4334 iflib_if_init_locked(ctx);
4339 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4341 if_ctx_t ctx = if_getsoftc(ifp);
4343 if ((void *)ctx != arg)
4346 if ((vtag == 0) || (vtag > 4095))
4350 IFDI_VLAN_UNREGISTER(ctx, vtag);
4351 /* Re-init to load the changes */
4352 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4353 iflib_if_init_locked(ctx);
4358 iflib_led_func(void *arg, int onoff)
4363 IFDI_LED_FUNC(ctx, onoff);
4367 /*********************************************************************
4369 * BUS FUNCTION DEFINITIONS
4371 **********************************************************************/
4374 iflib_device_probe(device_t dev)
4376 pci_vendor_info_t *ent;
4378 uint16_t pci_vendor_id, pci_device_id;
4379 uint16_t pci_subvendor_id, pci_subdevice_id;
4380 uint16_t pci_rev_id;
4381 if_shared_ctx_t sctx;
4383 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4386 pci_vendor_id = pci_get_vendor(dev);
4387 pci_device_id = pci_get_device(dev);
4388 pci_subvendor_id = pci_get_subvendor(dev);
4389 pci_subdevice_id = pci_get_subdevice(dev);
4390 pci_rev_id = pci_get_revid(dev);
4391 if (sctx->isc_parse_devinfo != NULL)
4392 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4394 ent = sctx->isc_vendor_info;
4395 while (ent->pvi_vendor_id != 0) {
4396 if (pci_vendor_id != ent->pvi_vendor_id) {
4400 if ((pci_device_id == ent->pvi_device_id) &&
4401 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4402 (ent->pvi_subvendor_id == 0)) &&
4403 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4404 (ent->pvi_subdevice_id == 0)) &&
4405 ((pci_rev_id == ent->pvi_rev_id) ||
4406 (ent->pvi_rev_id == 0))) {
4408 device_set_desc_copy(dev, ent->pvi_name);
4409 /* this needs to be changed to zero if the bus probing code
4410 * ever stops re-probing on best match because the sctx
4411 * may have its values over written by register calls
4412 * in subsequent probes
4414 return (BUS_PROBE_DEFAULT);
4422 iflib_reset_qvalues(if_ctx_t ctx)
4424 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4425 if_shared_ctx_t sctx = ctx->ifc_sctx;
4426 device_t dev = ctx->ifc_dev;
4429 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES;
4430 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH;
4432 * XXX sanity check that ntxd & nrxd are a power of 2
4434 if (ctx->ifc_sysctl_ntxqs != 0)
4435 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4436 if (ctx->ifc_sysctl_nrxqs != 0)
4437 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4439 for (i = 0; i < sctx->isc_ntxqs; i++) {
4440 if (ctx->ifc_sysctl_ntxds[i] != 0)
4441 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4443 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4446 for (i = 0; i < sctx->isc_nrxqs; i++) {
4447 if (ctx->ifc_sysctl_nrxds[i] != 0)
4448 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4450 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4453 for (i = 0; i < sctx->isc_nrxqs; i++) {
4454 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4455 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4456 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4457 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4459 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4460 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4461 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4462 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4466 for (i = 0; i < sctx->isc_ntxqs; i++) {
4467 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4468 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4469 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4470 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4472 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4473 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4474 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4475 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4481 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4486 if_softc_ctx_t scctx;
4492 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4495 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4496 device_set_softc(dev, ctx);
4497 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4500 ctx->ifc_sctx = sctx;
4502 ctx->ifc_softc = sc;
4504 if ((err = iflib_register(ctx)) != 0) {
4505 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4508 device_printf(dev, "iflib_register failed %d\n", err);
4511 iflib_add_device_sysctl_pre(ctx);
4513 scctx = &ctx->ifc_softc_ctx;
4516 iflib_reset_qvalues(ctx);
4518 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4520 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4523 _iflib_pre_assert(scctx);
4524 ctx->ifc_txrx = *scctx->isc_txrx;
4527 MPASS(scctx->isc_capabilities);
4528 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4529 MPASS(scctx->isc_tx_csum_flags);
4532 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4533 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4535 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4536 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4537 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4538 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4541 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL)
4542 ctx->ifc_flags |= IFC_DMAR;
4543 #elif !(defined(__i386__) || defined(__amd64__))
4544 /* set unconditionally for !x86 */
4545 ctx->ifc_flags |= IFC_DMAR;
4548 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4549 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4551 /* XXX change for per-queue sizes */
4552 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4553 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4554 for (i = 0; i < sctx->isc_nrxqs; i++) {
4555 if (!powerof2(scctx->isc_nrxd[i])) {
4556 /* round down instead? */
4557 device_printf(dev, "# rx descriptors must be a power of 2\n");
4562 for (i = 0; i < sctx->isc_ntxqs; i++) {
4563 if (!powerof2(scctx->isc_ntxd[i])) {
4565 "# tx descriptors must be a power of 2");
4571 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4572 MAX_SINGLE_PACKET_FRACTION)
4573 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4574 MAX_SINGLE_PACKET_FRACTION);
4575 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4576 MAX_SINGLE_PACKET_FRACTION)
4577 scctx->isc_tx_tso_segments_max = max(1,
4578 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4580 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4581 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4583 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4586 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4589 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4590 * into account. In the worst case, each of these calls will
4591 * add another mbuf and, thus, the requirement for another DMA
4592 * segment. So for best performance, it doesn't make sense to
4593 * advertize a maximum of TSO segments that typically will
4594 * require defragmentation in iflib_encap().
4596 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4597 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4599 if (scctx->isc_rss_table_size == 0)
4600 scctx->isc_rss_table_size = 64;
4601 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4603 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4604 /* XXX format name */
4605 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4607 /* Set up cpu set. If it fails, use the set of all CPUs. */
4608 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4609 device_printf(dev, "Unable to fetch CPU list\n");
4610 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4612 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4615 ** Now setup MSI or MSI/X, should
4616 ** return us the number of supported
4617 ** vectors. (Will be 1 for MSI)
4619 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4620 msix = scctx->isc_vectors;
4621 } else if (scctx->isc_msix_bar != 0)
4623 * The simple fact that isc_msix_bar is not 0 does not mean we
4624 * we have a good value there that is known to work.
4626 msix = iflib_msix_init(ctx);
4628 scctx->isc_vectors = 1;
4629 scctx->isc_ntxqsets = 1;
4630 scctx->isc_nrxqsets = 1;
4631 scctx->isc_intr = IFLIB_INTR_LEGACY;
4634 /* Get memory for the station queues */
4635 if ((err = iflib_queues_alloc(ctx))) {
4636 device_printf(dev, "Unable to allocate queue memory\n");
4640 if ((err = iflib_qset_structures_setup(ctx)))
4644 * Group taskqueues aren't properly set up until SMP is started,
4645 * so we disable interrupts until we can handle them post
4648 * XXX: disabling interrupts doesn't actually work, at least for
4649 * the non-MSI case. When they occur before SI_SUB_SMP completes,
4650 * we do null handling and depend on this not causing too large an
4653 IFDI_INTR_DISABLE(ctx);
4654 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) {
4655 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err);
4656 goto fail_intr_free;
4660 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4664 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4665 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4666 goto fail_intr_free;
4670 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4672 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4673 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4678 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4679 * This must appear after the call to ether_ifattach() because
4680 * ether_ifattach() sets if_hdrlen to the default value.
4682 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4683 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4685 if ((err = iflib_netmap_attach(ctx))) {
4686 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4691 NETDUMP_SET(ctx->ifc_ifp, iflib);
4693 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4694 iflib_add_device_sysctl_post(ctx);
4695 ctx->ifc_flags |= IFC_INIT_DONE;
4700 ether_ifdetach(ctx->ifc_ifp);
4703 iflib_tx_structures_free(ctx);
4704 iflib_rx_structures_free(ctx);
4706 iflib_free_intr_mem(ctx);
4714 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4715 struct iflib_cloneattach_ctx *clctx)
4720 if_softc_ctx_t scctx;
4726 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4727 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4728 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4729 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4730 ctx->ifc_flags |= IFC_PSEUDO;
4732 ctx->ifc_sctx = sctx;
4733 ctx->ifc_softc = sc;
4736 if ((err = iflib_register(ctx)) != 0) {
4737 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4742 iflib_add_device_sysctl_pre(ctx);
4744 scctx = &ctx->ifc_softc_ctx;
4748 * XXX sanity check that ntxd & nrxd are a power of 2
4750 iflib_reset_qvalues(ctx);
4752 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4753 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4756 if (sctx->isc_flags & IFLIB_GEN_MAC)
4758 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4759 clctx->cc_params)) != 0) {
4760 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4763 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4764 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
4765 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO);
4768 MPASS(scctx->isc_capabilities);
4769 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4770 MPASS(scctx->isc_tx_csum_flags);
4773 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4774 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4776 ifp->if_flags |= IFF_NOGROUP;
4777 if (sctx->isc_flags & IFLIB_PSEUDO) {
4778 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4780 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4781 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4787 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4788 * This must appear after the call to ether_ifattach() because
4789 * ether_ifattach() sets if_hdrlen to the default value.
4791 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4792 if_setifheaderlen(ifp,
4793 sizeof(struct ether_vlan_header));
4795 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4796 iflib_add_device_sysctl_post(ctx);
4797 ctx->ifc_flags |= IFC_INIT_DONE;
4800 _iflib_pre_assert(scctx);
4801 ctx->ifc_txrx = *scctx->isc_txrx;
4803 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4804 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4805 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4806 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4808 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4809 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4811 /* XXX change for per-queue sizes */
4812 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n",
4813 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4814 for (i = 0; i < sctx->isc_nrxqs; i++) {
4815 if (!powerof2(scctx->isc_nrxd[i])) {
4816 /* round down instead? */
4817 device_printf(dev, "# rx descriptors must be a power of 2\n");
4822 for (i = 0; i < sctx->isc_ntxqs; i++) {
4823 if (!powerof2(scctx->isc_ntxd[i])) {
4825 "# tx descriptors must be a power of 2");
4831 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4832 MAX_SINGLE_PACKET_FRACTION)
4833 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4834 MAX_SINGLE_PACKET_FRACTION);
4835 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4836 MAX_SINGLE_PACKET_FRACTION)
4837 scctx->isc_tx_tso_segments_max = max(1,
4838 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4840 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4841 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4843 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4846 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4849 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4850 * into account. In the worst case, each of these calls will
4851 * add another mbuf and, thus, the requirement for another DMA
4852 * segment. So for best performance, it doesn't make sense to
4853 * advertize a maximum of TSO segments that typically will
4854 * require defragmentation in iflib_encap().
4856 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4857 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4859 if (scctx->isc_rss_table_size == 0)
4860 scctx->isc_rss_table_size = 64;
4861 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4863 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4864 /* XXX format name */
4865 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin");
4867 /* XXX --- can support > 1 -- but keep it simple for now */
4868 scctx->isc_intr = IFLIB_INTR_LEGACY;
4870 /* Get memory for the station queues */
4871 if ((err = iflib_queues_alloc(ctx))) {
4872 device_printf(dev, "Unable to allocate queue memory\n");
4876 if ((err = iflib_qset_structures_setup(ctx))) {
4877 device_printf(dev, "qset structure setup failed %d\n", err);
4882 * XXX What if anything do we want to do about interrupts?
4884 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac);
4885 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4886 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4891 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4892 * This must appear after the call to ether_ifattach() because
4893 * ether_ifattach() sets if_hdrlen to the default value.
4895 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4896 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4898 /* XXX handle more than one queue */
4899 for (i = 0; i < scctx->isc_nrxqsets; i++)
4900 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4904 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4905 iflib_add_device_sysctl_post(ctx);
4906 ctx->ifc_flags |= IFC_INIT_DONE;
4909 ether_ifdetach(ctx->ifc_ifp);
4911 iflib_tx_structures_free(ctx);
4912 iflib_rx_structures_free(ctx);
4919 iflib_pseudo_deregister(if_ctx_t ctx)
4921 if_t ifp = ctx->ifc_ifp;
4925 struct taskqgroup *tqg;
4928 /* Unregister VLAN events */
4929 if (ctx->ifc_vlan_attach_event != NULL)
4930 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
4931 if (ctx->ifc_vlan_detach_event != NULL)
4932 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
4934 ether_ifdetach(ifp);
4935 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
4936 CTX_LOCK_DESTROY(ctx);
4937 /* XXX drain any dependent tasks */
4938 tqg = qgroup_if_io_tqg;
4939 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
4940 callout_drain(&txq->ift_timer);
4941 if (txq->ift_task.gt_uniq != NULL)
4942 taskqgroup_detach(tqg, &txq->ift_task);
4944 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4945 if (rxq->ifr_task.gt_uniq != NULL)
4946 taskqgroup_detach(tqg, &rxq->ifr_task);
4948 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
4949 free(fl->ifl_rx_bitmap, M_IFLIB);
4951 tqg = qgroup_if_config_tqg;
4952 if (ctx->ifc_admin_task.gt_uniq != NULL)
4953 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
4954 if (ctx->ifc_vflr_task.gt_uniq != NULL)
4955 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
4959 iflib_tx_structures_free(ctx);
4960 iflib_rx_structures_free(ctx);
4961 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4962 free(ctx->ifc_softc, M_IFLIB);
4968 iflib_device_attach(device_t dev)
4971 if_shared_ctx_t sctx;
4973 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4976 pci_enable_busmaster(dev);
4978 return (iflib_device_register(dev, NULL, sctx, &ctx));
4982 iflib_device_deregister(if_ctx_t ctx)
4984 if_t ifp = ctx->ifc_ifp;
4987 device_t dev = ctx->ifc_dev;
4989 struct taskqgroup *tqg;
4992 /* Make sure VLANS are not using driver */
4993 if (if_vlantrunkinuse(ifp)) {
4994 device_printf(dev, "Vlan in use, detach first\n");
4998 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
4999 device_printf(dev, "SR-IOV in use; detach first.\n");
5005 ctx->ifc_flags |= IFC_IN_DETACH;
5012 /* Unregister VLAN events */
5013 if (ctx->ifc_vlan_attach_event != NULL)
5014 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5015 if (ctx->ifc_vlan_detach_event != NULL)
5016 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5018 iflib_netmap_detach(ifp);
5019 ether_ifdetach(ifp);
5020 if (ctx->ifc_led_dev != NULL)
5021 led_destroy(ctx->ifc_led_dev);
5022 /* XXX drain any dependent tasks */
5023 tqg = qgroup_if_io_tqg;
5024 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5025 callout_drain(&txq->ift_timer);
5026 if (txq->ift_task.gt_uniq != NULL)
5027 taskqgroup_detach(tqg, &txq->ift_task);
5029 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5030 if (rxq->ifr_task.gt_uniq != NULL)
5031 taskqgroup_detach(tqg, &rxq->ifr_task);
5033 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5034 free(fl->ifl_rx_bitmap, M_IFLIB);
5037 tqg = qgroup_if_config_tqg;
5038 if (ctx->ifc_admin_task.gt_uniq != NULL)
5039 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5040 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5041 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5046 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5047 CTX_LOCK_DESTROY(ctx);
5048 device_set_softc(ctx->ifc_dev, NULL);
5049 iflib_free_intr_mem(ctx);
5051 bus_generic_detach(dev);
5054 iflib_tx_structures_free(ctx);
5055 iflib_rx_structures_free(ctx);
5056 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5057 free(ctx->ifc_softc, M_IFLIB);
5058 STATE_LOCK_DESTROY(ctx);
5064 iflib_free_intr_mem(if_ctx_t ctx)
5067 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5068 pci_release_msi(ctx->ifc_dev);
5070 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5071 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5073 if (ctx->ifc_msix_mem != NULL) {
5074 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5075 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem);
5076 ctx->ifc_msix_mem = NULL;
5081 iflib_device_detach(device_t dev)
5083 if_ctx_t ctx = device_get_softc(dev);
5085 return (iflib_device_deregister(ctx));
5089 iflib_device_suspend(device_t dev)
5091 if_ctx_t ctx = device_get_softc(dev);
5097 return bus_generic_suspend(dev);
5100 iflib_device_shutdown(device_t dev)
5102 if_ctx_t ctx = device_get_softc(dev);
5108 return bus_generic_suspend(dev);
5113 iflib_device_resume(device_t dev)
5115 if_ctx_t ctx = device_get_softc(dev);
5116 iflib_txq_t txq = ctx->ifc_txqs;
5120 iflib_init_locked(ctx);
5122 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5123 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5125 return (bus_generic_resume(dev));
5129 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5132 if_ctx_t ctx = device_get_softc(dev);
5135 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5142 iflib_device_iov_uninit(device_t dev)
5144 if_ctx_t ctx = device_get_softc(dev);
5147 IFDI_IOV_UNINIT(ctx);
5152 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5155 if_ctx_t ctx = device_get_softc(dev);
5158 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5164 /*********************************************************************
5166 * MODULE FUNCTION DEFINITIONS
5168 **********************************************************************/
5171 * - Start a fast taskqueue thread for each core
5172 * - Start a taskqueue for control operations
5175 iflib_module_init(void)
5181 iflib_module_event_handler(module_t mod, int what, void *arg)
5187 if ((err = iflib_module_init()) != 0)
5193 return (EOPNOTSUPP);
5199 /*********************************************************************
5201 * PUBLIC FUNCTION DEFINITIONS
5202 * ordered as in iflib.h
5204 **********************************************************************/
5208 _iflib_assert(if_shared_ctx_t sctx)
5210 MPASS(sctx->isc_tx_maxsize);
5211 MPASS(sctx->isc_tx_maxsegsize);
5213 MPASS(sctx->isc_rx_maxsize);
5214 MPASS(sctx->isc_rx_nsegments);
5215 MPASS(sctx->isc_rx_maxsegsize);
5217 MPASS(sctx->isc_nrxd_min[0]);
5218 MPASS(sctx->isc_nrxd_max[0]);
5219 MPASS(sctx->isc_nrxd_default[0]);
5220 MPASS(sctx->isc_ntxd_min[0]);
5221 MPASS(sctx->isc_ntxd_max[0]);
5222 MPASS(sctx->isc_ntxd_default[0]);
5226 _iflib_pre_assert(if_softc_ctx_t scctx)
5229 MPASS(scctx->isc_txrx->ift_txd_encap);
5230 MPASS(scctx->isc_txrx->ift_txd_flush);
5231 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5232 MPASS(scctx->isc_txrx->ift_rxd_available);
5233 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5234 MPASS(scctx->isc_txrx->ift_rxd_refill);
5235 MPASS(scctx->isc_txrx->ift_rxd_flush);
5239 iflib_register(if_ctx_t ctx)
5241 if_shared_ctx_t sctx = ctx->ifc_sctx;
5242 driver_t *driver = sctx->isc_driver;
5243 device_t dev = ctx->ifc_dev;
5246 _iflib_assert(sctx);
5249 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5250 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5252 device_printf(dev, "can not allocate ifnet structure\n");
5257 * Initialize our context's device specific methods
5259 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5260 kobj_class_compile((kobj_class_t) driver);
5263 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5264 if_setsoftc(ifp, ctx);
5265 if_setdev(ifp, dev);
5266 if_setinitfn(ifp, iflib_if_init);
5267 if_setioctlfn(ifp, iflib_if_ioctl);
5269 if_setstartfn(ifp, iflib_altq_if_start);
5270 if_settransmitfn(ifp, iflib_altq_if_transmit);
5271 if_setsendqready(ifp);
5273 if_settransmitfn(ifp, iflib_if_transmit);
5275 if_setqflushfn(ifp, iflib_if_qflush);
5276 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5278 ctx->ifc_vlan_attach_event =
5279 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5280 EVENTHANDLER_PRI_FIRST);
5281 ctx->ifc_vlan_detach_event =
5282 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5283 EVENTHANDLER_PRI_FIRST);
5285 ifmedia_init(&ctx->ifc_media, IFM_IMASK,
5286 iflib_media_change, iflib_media_status);
5293 iflib_queues_alloc(if_ctx_t ctx)
5295 if_shared_ctx_t sctx = ctx->ifc_sctx;
5296 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5297 device_t dev = ctx->ifc_dev;
5298 int nrxqsets = scctx->isc_nrxqsets;
5299 int ntxqsets = scctx->isc_ntxqsets;
5302 iflib_fl_t fl = NULL;
5303 int i, j, cpu, err, txconf, rxconf;
5304 iflib_dma_info_t ifdip;
5305 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5306 uint32_t *txqsizes = scctx->isc_txqsizes;
5307 uint8_t nrxqs = sctx->isc_nrxqs;
5308 uint8_t ntxqs = sctx->isc_ntxqs;
5309 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5313 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5314 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5316 /* Allocate the TX ring struct memory */
5317 if (!(ctx->ifc_txqs =
5318 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5319 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5320 device_printf(dev, "Unable to allocate TX ring memory\n");
5325 /* Now allocate the RX */
5326 if (!(ctx->ifc_rxqs =
5327 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5328 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5329 device_printf(dev, "Unable to allocate RX ring memory\n");
5334 txq = ctx->ifc_txqs;
5335 rxq = ctx->ifc_rxqs;
5338 * XXX handle allocation failure
5340 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5341 /* Set up some basics */
5343 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5344 device_printf(dev, "failed to allocate iflib_dma_info\n");
5348 txq->ift_ifdi = ifdip;
5349 for (j = 0; j < ntxqs; j++, ifdip++) {
5350 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5351 device_printf(dev, "Unable to allocate Descriptor memory\n");
5355 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5356 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5360 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5361 txq->ift_br_offset = 1;
5363 txq->ift_br_offset = 0;
5366 txq->ift_timer.c_cpu = cpu;
5368 if (iflib_txsd_alloc(txq)) {
5369 device_printf(dev, "Critical Failure setting up TX buffers\n");
5374 /* Initialize the TX lock */
5375 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout",
5376 device_get_nameunit(dev), txq->ift_id);
5377 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5378 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5380 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db",
5381 device_get_nameunit(dev), txq->ift_id);
5383 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5384 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5386 /* XXX free any allocated rings */
5387 device_printf(dev, "Unable to allocate buf_ring\n");
5392 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5393 /* Set up some basics */
5395 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) {
5396 device_printf(dev, "failed to allocate iflib_dma_info\n");
5401 rxq->ifr_ifdi = ifdip;
5402 /* XXX this needs to be changed if #rx queues != #tx queues */
5403 rxq->ifr_ntxqirq = 1;
5404 rxq->ifr_txqid[0] = i;
5405 for (j = 0; j < nrxqs; j++, ifdip++) {
5406 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) {
5407 device_printf(dev, "Unable to allocate Descriptor memory\n");
5411 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5415 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5416 rxq->ifr_fl_offset = 1;
5418 rxq->ifr_fl_offset = 0;
5420 rxq->ifr_nfl = nfree_lists;
5422 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5423 device_printf(dev, "Unable to allocate free list memory\n");
5428 for (j = 0; j < nfree_lists; j++) {
5429 fl[j].ifl_rxq = rxq;
5431 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5432 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5434 /* Allocate receive buffers for the ring */
5435 if (iflib_rxsd_alloc(rxq)) {
5437 "Critical Failure setting up receive buffers\n");
5442 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5443 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO);
5447 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5448 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5449 for (i = 0; i < ntxqsets; i++) {
5450 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5452 for (j = 0; j < ntxqs; j++, di++) {
5453 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5454 paddrs[i*ntxqs + j] = di->idi_paddr;
5457 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5458 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5459 iflib_tx_structures_free(ctx);
5460 free(vaddrs, M_IFLIB);
5461 free(paddrs, M_IFLIB);
5464 free(vaddrs, M_IFLIB);
5465 free(paddrs, M_IFLIB);
5468 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5469 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5470 for (i = 0; i < nrxqsets; i++) {
5471 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5473 for (j = 0; j < nrxqs; j++, di++) {
5474 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5475 paddrs[i*nrxqs + j] = di->idi_paddr;
5478 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5479 device_printf(ctx->ifc_dev, "device queue allocation failed\n");
5480 iflib_tx_structures_free(ctx);
5481 free(vaddrs, M_IFLIB);
5482 free(paddrs, M_IFLIB);
5485 free(vaddrs, M_IFLIB);
5486 free(paddrs, M_IFLIB);
5490 /* XXX handle allocation failure changes */
5494 if (ctx->ifc_rxqs != NULL)
5495 free(ctx->ifc_rxqs, M_IFLIB);
5496 ctx->ifc_rxqs = NULL;
5497 if (ctx->ifc_txqs != NULL)
5498 free(ctx->ifc_txqs, M_IFLIB);
5499 ctx->ifc_txqs = NULL;
5505 iflib_tx_structures_setup(if_ctx_t ctx)
5507 iflib_txq_t txq = ctx->ifc_txqs;
5510 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5511 iflib_txq_setup(txq);
5517 iflib_tx_structures_free(if_ctx_t ctx)
5519 iflib_txq_t txq = ctx->ifc_txqs;
5520 if_shared_ctx_t sctx = ctx->ifc_sctx;
5523 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5524 iflib_txq_destroy(txq);
5525 for (j = 0; j < sctx->isc_ntxqs; j++)
5526 iflib_dma_free(&txq->ift_ifdi[j]);
5528 free(ctx->ifc_txqs, M_IFLIB);
5529 ctx->ifc_txqs = NULL;
5530 IFDI_QUEUES_FREE(ctx);
5533 /*********************************************************************
5535 * Initialize all receive rings.
5537 **********************************************************************/
5539 iflib_rx_structures_setup(if_ctx_t ctx)
5541 iflib_rxq_t rxq = ctx->ifc_rxqs;
5543 #if defined(INET6) || defined(INET)
5547 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5548 #if defined(INET6) || defined(INET)
5549 tcp_lro_free(&rxq->ifr_lc);
5550 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5551 TCP_LRO_ENTRIES, min(1024,
5552 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) {
5553 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n");
5556 rxq->ifr_lro_enabled = TRUE;
5558 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5561 #if defined(INET6) || defined(INET)
5564 * Free RX software descriptors allocated so far, we will only handle
5565 * the rings that completed, the failing case will have
5566 * cleaned up for itself. 'q' failed, so its the terminus.
5568 rxq = ctx->ifc_rxqs;
5569 for (i = 0; i < q; ++i, rxq++) {
5570 iflib_rx_sds_free(rxq);
5571 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0;
5577 /*********************************************************************
5579 * Free all receive rings.
5581 **********************************************************************/
5583 iflib_rx_structures_free(if_ctx_t ctx)
5585 iflib_rxq_t rxq = ctx->ifc_rxqs;
5587 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5588 iflib_rx_sds_free(rxq);
5590 free(ctx->ifc_rxqs, M_IFLIB);
5591 ctx->ifc_rxqs = NULL;
5595 iflib_qset_structures_setup(if_ctx_t ctx)
5600 * It is expected that the caller takes care of freeing queues if this
5603 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5604 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5608 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5609 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5615 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5616 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5619 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5624 find_nth(if_ctx_t ctx, int qid)
5627 int i, cpuid, eqid, count;
5629 CPU_COPY(&ctx->ifc_cpus, &cpus);
5630 count = CPU_COUNT(&cpus);
5632 /* clear up to the qid'th bit */
5633 for (i = 0; i < eqid; i++) {
5634 cpuid = CPU_FFS(&cpus);
5636 CPU_CLR(cpuid-1, &cpus);
5638 cpuid = CPU_FFS(&cpus);
5644 extern struct cpu_group *cpu_top; /* CPU topology */
5647 find_child_with_core(int cpu, struct cpu_group *grp)
5651 if (grp->cg_children == 0)
5654 MPASS(grp->cg_child);
5655 for (i = 0; i < grp->cg_children; i++) {
5656 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5664 * Find the nth "close" core to the specified core
5665 * "close" is defined as the deepest level that shares
5666 * at least an L2 cache. With threads, this will be
5667 * threads on the same core. If the sahred cache is L3
5668 * or higher, simply returns the same core.
5671 find_close_core(int cpu, int core_offset)
5673 struct cpu_group *grp;
5682 while ((i = find_child_with_core(cpu, grp)) != -1) {
5683 /* If the child only has one cpu, don't descend */
5684 if (grp->cg_child[i].cg_count <= 1)
5686 grp = &grp->cg_child[i];
5689 /* If they don't share at least an L2 cache, use the same CPU */
5690 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5694 CPU_COPY(&grp->cg_mask, &cs);
5696 /* Add the selected CPU offset to core offset. */
5697 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5698 if (fcpu - 1 == cpu)
5700 CPU_CLR(fcpu - 1, &cs);
5706 CPU_COPY(&grp->cg_mask, &cs);
5707 for (i = core_offset % grp->cg_count; i > 0; i--) {
5708 MPASS(CPU_FFS(&cs));
5709 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5711 MPASS(CPU_FFS(&cs));
5712 return CPU_FFS(&cs) - 1;
5716 find_close_core(int cpu, int core_offset __unused)
5723 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5727 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5728 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5729 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5731 case IFLIB_INTR_RXTX:
5732 /* RX queues get the specified core */
5733 return qid / CPU_COUNT(&ctx->ifc_cpus);
5739 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5740 #define find_close_core(cpuid, tid) CPU_FIRST()
5741 #define find_nth(ctx, gid) CPU_FIRST()
5744 /* Just to avoid copy/paste */
5746 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid,
5747 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name)
5752 cpuid = find_nth(ctx, qid);
5753 tid = get_core_offset(ctx, type, qid);
5755 cpuid = find_close_core(cpuid, tid);
5756 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name);
5758 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err);
5762 if (cpuid > ctx->ifc_cpuid_highest)
5763 ctx->ifc_cpuid_highest = cpuid;
5769 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5770 iflib_intr_type_t type, driver_filter_t *filter,
5771 void *filter_arg, int qid, const char *name)
5773 struct grouptask *gtask;
5774 struct taskqgroup *tqg;
5775 iflib_filter_info_t info;
5778 driver_filter_t *intr_fast;
5781 info = &ctx->ifc_filter_info;
5785 /* XXX merge tx/rx for netmap? */
5787 q = &ctx->ifc_txqs[qid];
5788 info = &ctx->ifc_txqs[qid].ift_filter_info;
5789 gtask = &ctx->ifc_txqs[qid].ift_task;
5790 tqg = qgroup_if_io_tqg;
5792 intr_fast = iflib_fast_intr;
5793 GROUPTASK_INIT(gtask, 0, fn, q);
5794 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5797 q = &ctx->ifc_rxqs[qid];
5798 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5799 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5800 tqg = qgroup_if_io_tqg;
5802 intr_fast = iflib_fast_intr;
5803 GROUPTASK_INIT(gtask, 0, fn, q);
5805 case IFLIB_INTR_RXTX:
5806 q = &ctx->ifc_rxqs[qid];
5807 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5808 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5809 tqg = qgroup_if_io_tqg;
5811 intr_fast = iflib_fast_intr_rxtx;
5812 GROUPTASK_INIT(gtask, 0, fn, q);
5814 case IFLIB_INTR_ADMIN:
5817 info = &ctx->ifc_filter_info;
5818 gtask = &ctx->ifc_admin_task;
5819 tqg = qgroup_if_config_tqg;
5820 fn = _task_fn_admin;
5821 intr_fast = iflib_fast_intr_ctx;
5824 panic("unknown net intr type");
5827 info->ifi_filter = filter;
5828 info->ifi_filter_arg = filter_arg;
5829 info->ifi_task = gtask;
5832 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
5834 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err);
5837 if (type == IFLIB_INTR_ADMIN)
5841 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name);
5845 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5852 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5854 struct grouptask *gtask;
5855 struct taskqgroup *tqg;
5863 q = &ctx->ifc_txqs[qid];
5864 gtask = &ctx->ifc_txqs[qid].ift_task;
5865 tqg = qgroup_if_io_tqg;
5868 irq_num = rman_get_start(irq->ii_res);
5871 q = &ctx->ifc_rxqs[qid];
5872 gtask = &ctx->ifc_rxqs[qid].ifr_task;
5873 tqg = qgroup_if_io_tqg;
5876 irq_num = rman_get_start(irq->ii_res);
5878 case IFLIB_INTR_IOV:
5880 gtask = &ctx->ifc_vflr_task;
5881 tqg = qgroup_if_config_tqg;
5885 panic("unknown net intr type");
5887 GROUPTASK_INIT(gtask, 0, fn, q);
5888 if (irq_num != -1) {
5889 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name);
5891 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5894 taskqgroup_attach(tqg, gtask, q, irq_num, name);
5899 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
5902 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
5905 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res);
5909 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
5911 iflib_txq_t txq = ctx->ifc_txqs;
5912 iflib_rxq_t rxq = ctx->ifc_rxqs;
5913 if_irq_t irq = &ctx->ifc_legacy_irq;
5914 iflib_filter_info_t info;
5915 struct grouptask *gtask;
5916 struct taskqgroup *tqg;
5922 q = &ctx->ifc_rxqs[0];
5923 info = &rxq[0].ifr_filter_info;
5924 gtask = &rxq[0].ifr_task;
5925 tqg = qgroup_if_io_tqg;
5926 tqrid = irq->ii_rid = *rid;
5929 ctx->ifc_flags |= IFC_LEGACY;
5930 info->ifi_filter = filter;
5931 info->ifi_filter_arg = filter_arg;
5932 info->ifi_task = gtask;
5933 info->ifi_ctx = ctx;
5935 /* We allocate a single interrupt resource */
5936 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0)
5938 GROUPTASK_INIT(gtask, 0, fn, q);
5939 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name);
5941 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
5942 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx");
5947 iflib_led_create(if_ctx_t ctx)
5950 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
5951 device_get_nameunit(ctx->ifc_dev));
5955 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
5958 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
5962 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
5965 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
5969 iflib_admin_intr_deferred(if_ctx_t ctx)
5972 struct grouptask *gtask;
5974 gtask = &ctx->ifc_admin_task;
5975 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
5978 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
5982 iflib_iov_intr_deferred(if_ctx_t ctx)
5985 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
5989 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name)
5992 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name);
5996 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6000 GROUPTASK_INIT(gtask, 0, fn, ctx);
6001 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name);
6005 iflib_config_gtask_deinit(struct grouptask *gtask)
6008 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6012 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6014 if_t ifp = ctx->ifc_ifp;
6015 iflib_txq_t txq = ctx->ifc_txqs;
6017 if_setbaudrate(ifp, baudrate);
6018 if (baudrate >= IF_Gbps(10)) {
6020 ctx->ifc_flags |= IFC_PREFETCH;
6023 /* If link down, disable watchdog */
6024 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6025 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6026 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6028 ctx->ifc_link_state = link_state;
6029 if_link_state_change(ifp, link_state);
6033 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6037 int credits_pre = txq->ift_cidx_processed;
6040 if (ctx->isc_txd_credits_update == NULL)
6043 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6046 txq->ift_processed += credits;
6047 txq->ift_cidx_processed += credits;
6049 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6050 if (txq->ift_cidx_processed >= txq->ift_size)
6051 txq->ift_cidx_processed -= txq->ift_size;
6056 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6059 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6064 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6065 const char *description, if_int_delay_info_t info,
6066 int offset, int value)
6068 info->iidi_ctx = ctx;
6069 info->iidi_offset = offset;
6070 info->iidi_value = value;
6071 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6072 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6073 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6074 info, 0, iflib_sysctl_int_delay, "I", description);
6078 iflib_ctx_lock_get(if_ctx_t ctx)
6081 return (&ctx->ifc_ctx_sx);
6085 iflib_msix_init(if_ctx_t ctx)
6087 device_t dev = ctx->ifc_dev;
6088 if_shared_ctx_t sctx = ctx->ifc_sctx;
6089 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6090 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs;
6091 int iflib_num_tx_queues, iflib_num_rx_queues;
6092 int err, admincnt, bar;
6094 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6095 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6097 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6099 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6100 admincnt = sctx->isc_admin_intrcnt;
6101 /* Override by tuneable */
6102 if (scctx->isc_disable_msix)
6106 * bar == -1 => "trust me I know what I'm doing"
6107 * Some drivers are for hardware that is so shoddily
6108 * documented that no one knows which bars are which
6109 * so the developer has to map all bars. This hack
6110 * allows shoddy garbage to use msix in this framework.
6113 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6114 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6115 if (ctx->ifc_msix_mem == NULL) {
6116 /* May not be enabled */
6117 device_printf(dev, "Unable to map MSIX table \n");
6121 /* First try MSI/X */
6122 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */
6123 device_printf(dev, "System has MSIX disabled \n");
6124 bus_release_resource(dev, SYS_RES_MEMORY,
6125 bar, ctx->ifc_msix_mem);
6126 ctx->ifc_msix_mem = NULL;
6130 /* use only 1 qset in debug mode */
6131 queuemsgs = min(msgs - admincnt, 1);
6133 queuemsgs = msgs - admincnt;
6136 queues = imin(queuemsgs, rss_getnumbuckets());
6140 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6141 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n",
6142 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6144 /* If we're doing RSS, clamp at the number of RSS buckets */
6145 if (queues > rss_getnumbuckets())
6146 queues = rss_getnumbuckets();
6148 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6149 rx_queues = iflib_num_rx_queues;
6153 if (rx_queues > scctx->isc_nrxqsets)
6154 rx_queues = scctx->isc_nrxqsets;
6157 * We want this to be all logical CPUs by default
6159 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6160 tx_queues = iflib_num_tx_queues;
6162 tx_queues = mp_ncpus;
6164 if (tx_queues > scctx->isc_ntxqsets)
6165 tx_queues = scctx->isc_ntxqsets;
6167 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6169 if (tx_queues != rx_queues)
6171 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6172 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6174 tx_queues = min(rx_queues, tx_queues);
6175 rx_queues = min(rx_queues, tx_queues);
6178 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues);
6180 vectors = rx_queues + admincnt;
6181 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6182 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors);
6183 scctx->isc_vectors = vectors;
6184 scctx->isc_nrxqsets = rx_queues;
6185 scctx->isc_ntxqsets = tx_queues;
6186 scctx->isc_intr = IFLIB_INTR_MSIX;
6191 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err);
6192 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6194 ctx->ifc_msix_mem = NULL;
6197 vectors = pci_msi_count(dev);
6198 scctx->isc_nrxqsets = 1;
6199 scctx->isc_ntxqsets = 1;
6200 scctx->isc_vectors = vectors;
6201 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6202 device_printf(dev,"Using an MSI interrupt\n");
6203 scctx->isc_intr = IFLIB_INTR_MSI;
6205 scctx->isc_vectors = 1;
6206 device_printf(dev,"Using a Legacy interrupt\n");
6207 scctx->isc_intr = IFLIB_INTR_LEGACY;
6213 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6216 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6219 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6221 const char *ring_state = "UNKNOWN";
6224 rc = sysctl_wire_old_buffer(req, 0);
6228 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6233 ring_state = ring_states[state[3]];
6235 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6236 state[0], state[1], state[2], ring_state);
6237 rc = sbuf_finish(sb);
6242 enum iflib_ndesc_handler {
6248 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6250 if_ctx_t ctx = (void *)arg1;
6251 enum iflib_ndesc_handler type = arg2;
6252 char buf[256] = {0};
6257 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER);
6261 case IFLIB_NTXD_HANDLER:
6262 ndesc = ctx->ifc_sysctl_ntxds;
6264 nqs = ctx->ifc_sctx->isc_ntxqs;
6266 case IFLIB_NRXD_HANDLER:
6267 ndesc = ctx->ifc_sysctl_nrxds;
6269 nqs = ctx->ifc_sctx->isc_nrxqs;
6272 panic("unhandled type");
6277 for (i=0; i<8; i++) {
6282 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6285 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6286 if (rc || req->newptr == NULL)
6289 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6290 i++, p = strsep(&next, " ,")) {
6291 ndesc[i] = strtoul(p, NULL, 10);
6297 #define NAME_BUFLEN 32
6299 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6301 device_t dev = iflib_get_dev(ctx);
6302 struct sysctl_oid_list *child, *oid_list;
6303 struct sysctl_ctx_list *ctx_list;
6304 struct sysctl_oid *node;
6306 ctx_list = device_get_sysctl_ctx(dev);
6307 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6308 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6309 CTLFLAG_RD, NULL, "IFLIB fields");
6310 oid_list = SYSCTL_CHILDREN(node);
6312 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6313 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0,
6316 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6317 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6318 "# of txqs to use, 0 => use default #");
6319 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6320 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6321 "# of rxqs to use, 0 => use default #");
6322 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6323 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6324 "permit #txq != #rxq");
6325 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6326 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6327 "disable MSIX (default 0)");
6328 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6329 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6330 "set the rx budget");
6331 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6332 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6333 "cause tx to abdicate instead of running to completion");
6335 /* XXX change for per-queue sizes */
6336 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6337 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6338 mp_ndesc_handler, "A",
6339 "list of # of tx descriptors to use, 0 = use default #");
6340 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6341 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6342 mp_ndesc_handler, "A",
6343 "list of # of rx descriptors to use, 0 = use default #");
6347 iflib_add_device_sysctl_post(if_ctx_t ctx)
6349 if_shared_ctx_t sctx = ctx->ifc_sctx;
6350 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6351 device_t dev = iflib_get_dev(ctx);
6352 struct sysctl_oid_list *child;
6353 struct sysctl_ctx_list *ctx_list;
6358 char namebuf[NAME_BUFLEN];
6360 struct sysctl_oid *queue_node, *fl_node, *node;
6361 struct sysctl_oid_list *queue_list, *fl_list;
6362 ctx_list = device_get_sysctl_ctx(dev);
6364 node = ctx->ifc_sysctl_node;
6365 child = SYSCTL_CHILDREN(node);
6367 if (scctx->isc_ntxqsets > 100)
6369 else if (scctx->isc_ntxqsets > 10)
6373 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6374 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6375 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6376 CTLFLAG_RD, NULL, "Queue Name");
6377 queue_list = SYSCTL_CHILDREN(queue_node);
6379 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6381 &txq->ift_dequeued, "total mbufs freed");
6382 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6384 &txq->ift_enqueued, "total mbufs enqueued");
6386 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6388 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6389 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6391 &txq->ift_pullups, "# of times m_pullup was called");
6392 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6394 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6395 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6397 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6398 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6400 &txq->ift_map_failed, "# of times dma map failed");
6401 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6403 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6404 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6406 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6407 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6409 &txq->ift_pidx, 1, "Producer Index");
6410 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6412 &txq->ift_cidx, 1, "Consumer Index");
6413 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6415 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6416 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6418 &txq->ift_in_use, 1, "descriptors in use");
6419 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6421 &txq->ift_processed, "descriptors procesed for clean");
6422 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6424 &txq->ift_cleaned, "total cleaned");
6425 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6426 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6427 0, mp_ring_state_handler, "A", "soft ring state");
6428 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6429 CTLFLAG_RD, &txq->ift_br->enqueues,
6430 "# of enqueues to the mp_ring for this queue");
6431 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6432 CTLFLAG_RD, &txq->ift_br->drops,
6433 "# of drops in the mp_ring for this queue");
6434 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6435 CTLFLAG_RD, &txq->ift_br->starts,
6436 "# of normal consumer starts in the mp_ring for this queue");
6437 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6438 CTLFLAG_RD, &txq->ift_br->stalls,
6439 "# of consumer stalls in the mp_ring for this queue");
6440 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6441 CTLFLAG_RD, &txq->ift_br->restarts,
6442 "# of consumer restarts in the mp_ring for this queue");
6443 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6444 CTLFLAG_RD, &txq->ift_br->abdications,
6445 "# of consumer abdications in the mp_ring for this queue");
6448 if (scctx->isc_nrxqsets > 100)
6450 else if (scctx->isc_nrxqsets > 10)
6454 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6455 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6456 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6457 CTLFLAG_RD, NULL, "Queue Name");
6458 queue_list = SYSCTL_CHILDREN(queue_node);
6459 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6460 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx",
6462 &rxq->ifr_cq_pidx, 1, "Producer Index");
6463 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6465 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6468 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6469 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6470 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6471 CTLFLAG_RD, NULL, "freelist Name");
6472 fl_list = SYSCTL_CHILDREN(fl_node);
6473 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6475 &fl->ifl_pidx, 1, "Producer Index");
6476 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6478 &fl->ifl_cidx, 1, "Consumer Index");
6479 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6481 &fl->ifl_credits, 1, "credits available");
6483 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6485 &fl->ifl_m_enqueued, "mbufs allocated");
6486 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6488 &fl->ifl_m_dequeued, "mbufs freed");
6489 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6491 &fl->ifl_cl_enqueued, "clusters allocated");
6492 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6494 &fl->ifl_cl_dequeued, "clusters freed");
6503 iflib_request_reset(if_ctx_t ctx)
6507 ctx->ifc_flags |= IFC_DO_RESET;
6511 #ifndef __NO_STRICT_ALIGNMENT
6512 static struct mbuf *
6513 iflib_fixup_rx(struct mbuf *m)
6517 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6518 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6519 m->m_data += ETHER_HDR_LEN;
6522 MGETHDR(n, M_NOWAIT, MT_DATA);
6527 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6528 m->m_data += ETHER_HDR_LEN;
6529 m->m_len -= ETHER_HDR_LEN;
6530 n->m_len = ETHER_HDR_LEN;
6531 M_MOVE_PKTHDR(n, m);
6540 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
6544 ctx = if_getsoftc(ifp);
6546 *nrxr = NRXQSETS(ctx);
6547 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6548 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6553 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event)
6556 if_softc_ctx_t scctx;
6561 ctx = if_getsoftc(ifp);
6562 scctx = &ctx->ifc_softc_ctx;
6566 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6567 rxq = &ctx->ifc_rxqs[i];
6568 for (j = 0; j < rxq->ifr_nfl; j++) {
6570 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6573 iflib_no_tx_batch = 1;
6581 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
6587 ctx = if_getsoftc(ifp);
6588 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6592 txq = &ctx->ifc_txqs[0];
6593 error = iflib_encap(txq, &m);
6595 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6600 iflib_netdump_poll(struct ifnet *ifp, int count)
6603 if_softc_ctx_t scctx;
6607 ctx = if_getsoftc(ifp);
6608 scctx = &ctx->ifc_softc_ctx;
6610 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6614 txq = &ctx->ifc_txqs[0];
6615 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6617 for (i = 0; i < scctx->isc_nrxqsets; i++)
6618 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6621 #endif /* NETDUMP */