2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/types.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
94 #include <dev/pci/pci_iov.h>
97 #include <sys/bitstring.h>
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
102 #define MEMORY_LOGGING 0
104 * Enable mbuf vectors for compressing long mbuf chains
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
122 * - private structures
123 * - iflib private utility functions
125 * - vlan registry and other exported functions
126 * - iflib public core functions
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
132 #define IFLIB_RXEOF_MORE (1U << 0)
133 #define IFLIB_RXEOF_EMPTY (2U << 0)
136 typedef struct iflib_txq *iflib_txq_t;
138 typedef struct iflib_rxq *iflib_rxq_t;
140 typedef struct iflib_fl *iflib_fl_t;
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
147 typedef struct iflib_filter_info {
148 driver_filter_t *ifi_filter;
149 void *ifi_filter_arg;
150 struct grouptask *ifi_task;
152 } *iflib_filter_info_t;
157 * Pointer to hardware driver's softc
164 if_shared_ctx_t ifc_sctx;
165 struct if_softc_ctx ifc_softc_ctx;
167 struct sx ifc_ctx_sx;
168 struct mtx ifc_state_mtx;
170 iflib_txq_t ifc_txqs;
171 iflib_rxq_t ifc_rxqs;
172 uint32_t ifc_if_flags;
174 uint32_t ifc_max_fl_buf_size;
175 uint32_t ifc_rx_mbuf_sz;
178 int ifc_watchdog_events;
179 struct cdev *ifc_led_dev;
180 struct resource *ifc_msix_mem;
182 struct if_irq ifc_legacy_irq;
183 struct grouptask ifc_admin_task;
184 struct grouptask ifc_vflr_task;
185 struct iflib_filter_info ifc_filter_info;
186 struct ifmedia ifc_media;
187 struct ifmedia *ifc_mediap;
189 struct sysctl_oid *ifc_sysctl_node;
190 uint16_t ifc_sysctl_ntxqs;
191 uint16_t ifc_sysctl_nrxqs;
192 uint16_t ifc_sysctl_qs_eq_override;
193 uint16_t ifc_sysctl_rx_budget;
194 uint16_t ifc_sysctl_tx_abdicate;
195 uint16_t ifc_sysctl_core_offset;
196 #define CORE_OFFSET_UNSPECIFIED 0xffff
197 uint8_t ifc_sysctl_separate_txrx;
199 qidx_t ifc_sysctl_ntxds[8];
200 qidx_t ifc_sysctl_nrxds[8];
201 struct if_txrx ifc_txrx;
202 #define isc_txd_encap ifc_txrx.ift_txd_encap
203 #define isc_txd_flush ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 eventhandler_tag ifc_vlan_attach_event;
211 eventhandler_tag ifc_vlan_detach_event;
212 struct ether_addr ifc_mac;
216 iflib_get_softc(if_ctx_t ctx)
219 return (ctx->ifc_softc);
223 iflib_get_dev(if_ctx_t ctx)
226 return (ctx->ifc_dev);
230 iflib_get_ifp(if_ctx_t ctx)
233 return (ctx->ifc_ifp);
237 iflib_get_media(if_ctx_t ctx)
240 return (ctx->ifc_mediap);
244 iflib_get_flags(if_ctx_t ctx)
246 return (ctx->ifc_flags);
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
257 iflib_get_softc_ctx(if_ctx_t ctx)
260 return (&ctx->ifc_softc_ctx);
264 iflib_get_sctx(if_ctx_t ctx)
267 return (ctx->ifc_sctx);
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
277 typedef struct iflib_sw_rx_desc_array {
278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
279 struct mbuf **ifsd_m; /* pkthdr mbufs */
280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
284 typedef struct iflib_sw_tx_desc_array {
285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
287 struct mbuf **ifsd_m; /* pkthdr mbufs */
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS 128
292 #define IFLIB_RX_COPY_THRESH 128
293 #define IFLIB_MAX_RX_REFRESH 32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC 16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
297 #define IFLIB_QUEUE_IDLE 0
298 #define IFLIB_QUEUE_HUNG 1
299 #define IFLIB_QUEUE_WORKING 2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR 4
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE 32
306 #define IFLIB_RESTART_BUDGET 8
308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
315 qidx_t ift_cidx_processed;
318 uint8_t ift_br_offset;
319 uint16_t ift_npending;
320 uint16_t ift_db_pending;
321 uint16_t ift_rs_pending;
323 uint8_t ift_txd_size[8];
324 uint64_t ift_processed;
325 uint64_t ift_cleaned;
326 uint64_t ift_cleaned_prev;
328 uint64_t ift_enqueued;
329 uint64_t ift_dequeued;
331 uint64_t ift_no_tx_dma_setup;
332 uint64_t ift_no_desc_avail;
333 uint64_t ift_mbuf_defrag_failed;
334 uint64_t ift_mbuf_defrag;
335 uint64_t ift_map_failed;
336 uint64_t ift_txd_encap_efbig;
337 uint64_t ift_pullups;
338 uint64_t ift_last_timer_tick;
341 struct mtx ift_db_mtx;
343 /* constant values */
345 struct ifmp_ring *ift_br;
346 struct grouptask ift_task;
349 struct callout ift_timer;
351 if_txsd_vec_t ift_sds;
354 uint8_t ift_update_freq;
355 struct iflib_filter_info ift_filter_info;
356 bus_dma_tag_t ift_buf_tag;
357 bus_dma_tag_t ift_tso_buf_tag;
358 iflib_dma_info_t ift_ifdi;
359 #define MTX_NAME_LEN 32
360 char ift_mtx_name[MTX_NAME_LEN];
361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 uint64_t ift_cpu_exec_count[256];
365 } __aligned(CACHE_LINE_SIZE);
372 uint8_t ifl_rxd_size;
374 uint64_t ifl_m_enqueued;
375 uint64_t ifl_m_dequeued;
376 uint64_t ifl_cl_enqueued;
377 uint64_t ifl_cl_dequeued;
380 bitstr_t *ifl_rx_bitmap;
384 uint16_t ifl_buf_size;
387 iflib_rxsd_array_t ifl_sds;
390 bus_dma_tag_t ifl_buf_tag;
391 iflib_dma_info_t ifl_ifdi;
392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 } __aligned(CACHE_LINE_SIZE);
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
403 else if (pidx < cidx)
404 used = size - cidx + pidx;
405 else if (gen == 0 && pidx == cidx)
407 else if (gen == 1 && pidx == cidx)
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
417 #define IDXDIFF(head, tail, wrap) \
418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
424 struct pfil_head *pfil;
426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 * the command queue consumer index. Otherwise it's unused.
433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 uint8_t ifr_fl_offset;
435 struct lro_ctrl ifr_lc;
436 struct grouptask ifr_task;
437 struct callout ifr_watchdog;
438 struct iflib_filter_info ifr_filter_info;
439 iflib_dma_info_t ifr_ifdi;
441 /* dynamically allocate if any drivers need a value substantially larger than this */
442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 uint64_t ifr_cpu_exec_count[256];
446 } __aligned(CACHE_LINE_SIZE);
448 typedef struct if_rxsd {
453 /* multiple of word size */
455 #define PKT_INFO_SIZE 6
456 #define RXD_INFO_SIZE 5
457 #define PKT_TYPE uint64_t
459 #define PKT_INFO_SIZE 11
460 #define RXD_INFO_SIZE 8
461 #define PKT_TYPE uint32_t
463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4)
466 typedef struct if_pkt_info_pad {
467 PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 pkt_info_zero(if_pkt_info_t pi)
480 if_pkt_info_pad_t pi_pad;
482 pi_pad = (if_pkt_info_pad_t)pi;
483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 static device_method_t iflib_pseudo_methods[] = {
492 DEVMETHOD(device_attach, noop_attach),
493 DEVMETHOD(device_detach, iflib_pseudo_detach),
497 driver_t iflib_pseudodriver = {
498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 rxd_info_zero(if_rxd_info_t ri)
504 if_rxd_info_pad_t ri_pad;
507 ri_pad = (if_rxd_info_pad_t)ri;
508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 ri_pad->rxd_val[i] = 0;
510 ri_pad->rxd_val[i+1] = 0;
511 ri_pad->rxd_val[i+2] = 0;
512 ri_pad->rxd_val[i+3] = 0;
515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
520 * Only allow a single packet to take up most 1/nth of the tx ring
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
541 iflib_set_detach(if_ctx_t ctx)
544 ctx->ifc_flags |= IFC_IN_DETACH;
548 /* Our boot-time initialization hook */
549 static int iflib_module_event_handler(module_t, int, void *);
551 static moduledata_t iflib_moduledata = {
553 iflib_module_event_handler,
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
566 #ifndef IFLIB_DEBUG_COUNTERS
568 #define IFLIB_DEBUG_COUNTERS 1
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
575 "iflib driver parameters");
578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
588 #if IFLIB_DEBUG_COUNTERS
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 &iflib_fl_refills_large, 0, "# large refills");
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 &iflib_txq_drain_notready, 0, "# drain notready");
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
648 static int iflib_verbose_debug;
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 &iflib_verbose_debug, 0, "enable verbose debugging");
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
669 iflib_debug_reset(void)
671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 iflib_txq_drain_notready =
675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
679 iflib_rx_ctx_inactive = iflib_rx_if_input =
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
688 #define IFLIB_DEBUG 0
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
708 static void iflib_init_locked(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
710 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
711 static void iflib_ifmp_purge(iflib_txq_t txq);
712 static void _iflib_pre_assert(if_softc_ctx_t scctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 static void iflib_free_intr_mem(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
720 SLIST_HEAD_INITIALIZER(cpu_offsets);
722 SLIST_ENTRY(cpu_offset) entries;
724 unsigned int refcount;
727 static struct mtx cpu_offset_mtx;
728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
731 DEBUGNET_DEFINE(iflib);
734 iflib_num_rx_descs(if_ctx_t ctx)
736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
737 if_shared_ctx_t sctx = ctx->ifc_sctx;
738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
740 return scctx->isc_nrxd[first_rxq];
744 iflib_num_tx_descs(if_ctx_t ctx)
746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
747 if_shared_ctx_t sctx = ctx->ifc_sctx;
748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
750 return scctx->isc_ntxd[first_txq];
754 #include <sys/selinfo.h>
755 #include <net/netmap.h>
756 #include <dev/netmap/netmap_kern.h>
758 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
763 * device-specific sysctl variables:
765 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
766 * During regular operations the CRC is stripped, but on some
767 * hardware reception of frames not multiple of 64 is slower,
768 * so using crcstrip=0 helps in benchmarks.
770 * iflib_rx_miss, iflib_rx_miss_bufs:
771 * count packets that might be missed due to lost interrupts.
773 SYSCTL_DECL(_dev_netmap);
775 * The xl driver by default strips CRCs and we do not override it.
778 int iflib_crcstrip = 1;
779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
780 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
782 int iflib_rx_miss, iflib_rx_miss_bufs;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
784 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
786 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
789 * Register/unregister. We are already under netmap lock.
790 * Only called on the first register or the last unregister.
793 iflib_netmap_register(struct netmap_adapter *na, int onoff)
796 if_ctx_t ctx = ifp->if_softc;
800 IFDI_INTR_DISABLE(ctx);
802 /* Tell the stack that the interface is no longer active */
803 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
811 * Enable (or disable) netmap flags, and intercept (or restore)
812 * ifp->if_transmit. This is done once the device has been stopped
813 * to prevent race conditions.
816 nm_set_native_flags(na);
818 nm_clear_native_flags(na);
821 iflib_init_locked(ctx);
822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
825 nm_clear_native_flags(na);
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
833 struct netmap_adapter *na = kring->na;
834 u_int const lim = kring->nkr_num_slots - 1;
835 u_int head = kring->rhead;
836 struct netmap_ring *ring = kring->ring;
838 struct if_rxd_update iru;
839 if_ctx_t ctx = rxq->ifr_ctx;
840 iflib_fl_t fl = &rxq->ifr_fl[0];
841 uint32_t refill_pidx, nic_i;
842 #if IFLIB_DEBUG_COUNTERS
846 if (nm_i == head && __predict_true(!init))
848 iru_init(&iru, rxq, 0 /* flid */);
849 map = fl->ifl_sds.ifsd_map;
850 refill_pidx = netmap_idx_k2n(kring, nm_i);
852 * IMPORTANT: we must leave one free slot in the ring,
853 * so move head back by one unit
855 head = nm_prev(head, lim);
857 DBG_COUNTER_INC(fl_refills);
858 while (nm_i != head) {
859 #if IFLIB_DEBUG_COUNTERS
861 DBG_COUNTER_INC(fl_refills_large);
863 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
864 struct netmap_slot *slot = &ring->slot[nm_i];
865 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
866 uint32_t nic_i_dma = refill_pidx;
867 nic_i = netmap_idx_k2n(kring, nm_i);
869 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
871 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
872 return netmap_ring_reinit(kring);
874 if (__predict_false(init)) {
875 netmap_load_map(na, fl->ifl_buf_tag,
877 } else if (slot->flags & NS_BUF_CHANGED) {
878 /* buffer has changed, reload map */
879 netmap_reload_map(na, fl->ifl_buf_tag,
882 slot->flags &= ~NS_BUF_CHANGED;
884 nm_i = nm_next(nm_i, lim);
885 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
886 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
889 iru.iru_pidx = refill_pidx;
890 iru.iru_count = tmp_pidx+1;
891 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
893 for (int n = 0; n < iru.iru_count; n++) {
894 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
895 BUS_DMASYNC_PREREAD);
896 /* XXX - change this to not use the netmap func*/
897 nic_i_dma = nm_next(nic_i_dma, lim);
901 kring->nr_hwcur = head;
903 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
904 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
905 if (__predict_true(nic_i != UINT_MAX)) {
906 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
907 DBG_COUNTER_INC(rxd_flush);
913 * Reconcile kernel and user view of the transmit ring.
915 * All information is in the kring.
916 * Userspace wants to send packets up to the one before kring->rhead,
917 * kernel knows kring->nr_hwcur is the first unsent packet.
919 * Here we push packets out (as many as possible), and possibly
920 * reclaim buffers from previously completed transmission.
922 * The caller (netmap) guarantees that there is only one instance
923 * running at any time. Any interference with other driver
924 * methods should be handled by the individual drivers.
927 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
929 struct netmap_adapter *na = kring->na;
931 struct netmap_ring *ring = kring->ring;
932 u_int nm_i; /* index into the netmap kring */
933 u_int nic_i; /* index into the NIC ring */
935 u_int const lim = kring->nkr_num_slots - 1;
936 u_int const head = kring->rhead;
937 struct if_pkt_info pi;
940 * interrupts on every tx packet are expensive so request
941 * them every half ring, or where NS_REPORT is set
943 u_int report_frequency = kring->nkr_num_slots >> 1;
944 /* device-specific */
945 if_ctx_t ctx = ifp->if_softc;
946 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
948 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
949 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
952 * First part: process new packets to send.
953 * nm_i is the current index in the netmap kring,
954 * nic_i is the corresponding index in the NIC ring.
956 * If we have packets to send (nm_i != head)
957 * iterate over the netmap ring, fetch length and update
958 * the corresponding slot in the NIC ring. Some drivers also
959 * need to update the buffer's physical address in the NIC slot
960 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
962 * The netmap_reload_map() calls is especially expensive,
963 * even when (as in this case) the tag is 0, so do only
964 * when the buffer has actually changed.
966 * If possible do not set the report/intr bit on all slots,
967 * but only a few times per ring or when NS_REPORT is set.
969 * Finally, on 10G and faster drivers, it might be useful
970 * to prefetch the next slot and txr entry.
973 nm_i = kring->nr_hwcur;
974 if (nm_i != head) { /* we have new packets to send */
976 pi.ipi_segs = txq->ift_segs;
977 pi.ipi_qsidx = kring->ring_id;
978 nic_i = netmap_idx_k2n(kring, nm_i);
980 __builtin_prefetch(&ring->slot[nm_i]);
981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
982 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
984 for (n = 0; nm_i != head; n++) {
985 struct netmap_slot *slot = &ring->slot[nm_i];
986 u_int len = slot->len;
988 void *addr = PNMB(na, slot, &paddr);
989 int flags = (slot->flags & NS_REPORT ||
990 nic_i == 0 || nic_i == report_frequency) ?
993 /* device-specific */
995 pi.ipi_segs[0].ds_addr = paddr;
996 pi.ipi_segs[0].ds_len = len;
1000 pi.ipi_flags = flags;
1002 /* Fill the slot in the NIC ring. */
1003 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1004 DBG_COUNTER_INC(tx_encap);
1006 /* prefetch for next round */
1007 __builtin_prefetch(&ring->slot[nm_i + 1]);
1008 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1009 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1011 NM_CHECK_ADDR_LEN(na, addr, len);
1013 if (slot->flags & NS_BUF_CHANGED) {
1014 /* buffer has changed, reload map */
1015 netmap_reload_map(na, txq->ift_buf_tag,
1016 txq->ift_sds.ifsd_map[nic_i], addr);
1018 /* make sure changes to the buffer are synced */
1019 bus_dmamap_sync(txq->ift_buf_tag,
1020 txq->ift_sds.ifsd_map[nic_i],
1021 BUS_DMASYNC_PREWRITE);
1023 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1024 nm_i = nm_next(nm_i, lim);
1025 nic_i = nm_next(nic_i, lim);
1027 kring->nr_hwcur = nm_i;
1029 /* synchronize the NIC ring */
1030 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1031 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1033 /* (re)start the tx unit up to slot nic_i (excluded) */
1034 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1038 * Second part: reclaim buffers for completed transmissions.
1040 * If there are unclaimed buffers, attempt to reclaim them.
1041 * If none are reclaimed, and TX IRQs are not in use, do an initial
1042 * minimal delay, then trigger the tx handler which will spin in the
1045 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1046 if (iflib_tx_credits_update(ctx, txq)) {
1047 /* some tx completed, increment avail */
1048 nic_i = txq->ift_cidx_processed;
1049 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1052 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1053 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1054 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1055 iflib_timer, txq, txq->ift_timer.c_cpu);
1061 * Reconcile kernel and user view of the receive ring.
1062 * Same as for the txsync, this routine must be efficient.
1063 * The caller guarantees a single invocations, but races against
1064 * the rest of the driver should be handled here.
1066 * On call, kring->rhead is the first packet that userspace wants
1067 * to keep, and kring->rcur is the wakeup point.
1068 * The kernel has previously reported packets up to kring->rtail.
1070 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1071 * of whether or not we received an interrupt.
1074 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1076 struct netmap_adapter *na = kring->na;
1077 struct netmap_ring *ring = kring->ring;
1080 uint32_t nm_i; /* index into the netmap ring */
1081 uint32_t nic_i; /* index into the NIC ring */
1083 u_int const lim = kring->nkr_num_slots - 1;
1084 u_int const head = kring->rhead;
1085 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1086 struct if_rxd_info ri;
1088 if_ctx_t ctx = ifp->if_softc;
1089 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1091 return netmap_ring_reinit(kring);
1094 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1097 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1098 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1099 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1103 * First part: import newly received packets.
1105 * nm_i is the index of the next free slot in the netmap ring,
1106 * nic_i is the index of the next received packet in the NIC ring,
1107 * and they may differ in case if_init() has been called while
1108 * in netmap mode. For the receive ring we have
1110 * nic_i = rxr->next_check;
1111 * nm_i = kring->nr_hwtail (previous)
1113 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1115 * rxr->next_check is set to 0 on a ring reinit
1117 if (netmap_no_pendintr || force_update) {
1118 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1119 int crclen = iflib_crcstrip ? 0 : 4;
1122 for (i = 0; i < rxq->ifr_nfl; i++) {
1123 fl = &rxq->ifr_fl[i];
1124 nic_i = fl->ifl_cidx;
1125 nm_i = netmap_idx_n2k(kring, nic_i);
1126 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1127 rxq->ifr_id, nic_i, USHRT_MAX);
1128 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1130 ri.iri_frags = rxq->ifr_frags;
1131 ri.iri_qsidx = kring->ring_id;
1132 ri.iri_ifp = ctx->ifc_ifp;
1133 ri.iri_cidx = nic_i;
1135 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1136 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1137 ring->slot[nm_i].flags = 0;
1138 bus_dmamap_sync(fl->ifl_buf_tag,
1139 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1140 nm_i = nm_next(nm_i, lim);
1141 nic_i = nm_next(nic_i, lim);
1143 if (n) { /* update the state variables */
1144 if (netmap_no_pendintr && !force_update) {
1147 iflib_rx_miss_bufs += n;
1149 fl->ifl_cidx = nic_i;
1150 kring->nr_hwtail = nm_i;
1152 kring->nr_kflags &= ~NKR_PENDINTR;
1156 * Second part: skip past packets that userspace has released.
1157 * (kring->nr_hwcur to head excluded),
1158 * and make the buffers available for reception.
1159 * As usual nm_i is the index in the netmap ring,
1160 * nic_i is the index in the NIC ring, and
1161 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1163 /* XXX not sure how this will work with multiple free lists */
1164 nm_i = kring->nr_hwcur;
1166 return (netmap_fl_refill(rxq, kring, nm_i, false));
1170 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1172 if_ctx_t ctx = na->ifp->if_softc;
1176 IFDI_INTR_ENABLE(ctx);
1178 IFDI_INTR_DISABLE(ctx);
1185 iflib_netmap_attach(if_ctx_t ctx)
1187 struct netmap_adapter na;
1189 bzero(&na, sizeof(na));
1191 na.ifp = ctx->ifc_ifp;
1192 na.na_flags = NAF_BDG_MAYSLEEP;
1193 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1194 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1196 na.num_tx_desc = iflib_num_tx_descs(ctx);
1197 na.num_rx_desc = iflib_num_rx_descs(ctx);
1198 na.nm_txsync = iflib_netmap_txsync;
1199 na.nm_rxsync = iflib_netmap_rxsync;
1200 na.nm_register = iflib_netmap_register;
1201 na.nm_intr = iflib_netmap_intr;
1202 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1203 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1204 return (netmap_attach(&na));
1208 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1210 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1211 struct netmap_slot *slot;
1213 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1216 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1219 * In netmap mode, set the map for the packet buffer.
1220 * NOTE: Some drivers (not this one) also need to set
1221 * the physical buffer address in the NIC ring.
1222 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1223 * netmap slot index, si
1225 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1226 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1227 NMB(na, slot + si));
1233 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1235 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1236 struct netmap_kring *kring;
1237 struct netmap_slot *slot;
1240 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1243 kring = na->rx_rings[rxq->ifr_id];
1244 nm_i = netmap_idx_n2k(kring, 0);
1245 netmap_fl_refill(rxq, kring, nm_i, true);
1250 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1252 struct netmap_kring *kring;
1255 txqid = txq->ift_id;
1256 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX);
1260 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1261 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1262 BUS_DMASYNC_POSTREAD);
1263 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1264 netmap_tx_irq(ctx->ifc_ifp, txqid);
1265 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1269 *reset_on = hz / 1000;
1274 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1277 #define iflib_netmap_txq_init(ctx, txq) (0)
1278 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1279 #define iflib_netmap_detach(ifp)
1281 #define iflib_netmap_attach(ctx) (0)
1282 #define netmap_rx_irq(ifp, qid, budget) (0)
1283 #define netmap_tx_irq(ifp, qid) do {} while (0)
1284 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1287 #if defined(__i386__) || defined(__amd64__)
1288 static __inline void
1291 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1293 static __inline void
1294 prefetch2cachelines(void *x)
1296 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1297 #if (CACHE_LINE_SIZE < 128)
1298 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1303 #define prefetch2cachelines(x)
1307 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1311 fl = &rxq->ifr_fl[flid];
1312 iru->iru_paddrs = fl->ifl_bus_addrs;
1313 iru->iru_idxs = fl->ifl_rxd_idxs;
1314 iru->iru_qsidx = rxq->ifr_id;
1315 iru->iru_buf_size = fl->ifl_buf_size;
1316 iru->iru_flidx = fl->ifl_id;
1320 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1324 *(bus_addr_t *) arg = segs[0].ds_addr;
1328 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1331 device_t dev = ctx->ifc_dev;
1333 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1334 align, 0, /* alignment, bounds */
1335 BUS_SPACE_MAXADDR, /* lowaddr */
1336 BUS_SPACE_MAXADDR, /* highaddr */
1337 NULL, NULL, /* filter, filterarg */
1340 size, /* maxsegsize */
1341 BUS_DMA_ALLOCNOW, /* flags */
1342 NULL, /* lockfunc */
1347 "%s: bus_dma_tag_create failed: %d\n",
1352 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1353 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1356 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1357 __func__, (uintmax_t)size, err);
1361 dma->idi_paddr = IF_BAD_DMA;
1362 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1363 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1364 if (err || dma->idi_paddr == IF_BAD_DMA) {
1366 "%s: bus_dmamap_load failed: %d\n",
1371 dma->idi_size = size;
1375 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1377 bus_dma_tag_destroy(dma->idi_tag);
1379 dma->idi_tag = NULL;
1385 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1387 if_shared_ctx_t sctx = ctx->ifc_sctx;
1389 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1391 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1395 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1398 iflib_dma_info_t *dmaiter;
1401 for (i = 0; i < count; i++, dmaiter++) {
1402 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1406 iflib_dma_free_multi(dmalist, i);
1411 iflib_dma_free(iflib_dma_info_t dma)
1413 if (dma->idi_tag == NULL)
1415 if (dma->idi_paddr != IF_BAD_DMA) {
1416 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1417 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1418 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1419 dma->idi_paddr = IF_BAD_DMA;
1421 if (dma->idi_vaddr != NULL) {
1422 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1423 dma->idi_vaddr = NULL;
1425 bus_dma_tag_destroy(dma->idi_tag);
1426 dma->idi_tag = NULL;
1430 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1433 iflib_dma_info_t *dmaiter = dmalist;
1435 for (i = 0; i < count; i++, dmaiter++)
1436 iflib_dma_free(*dmaiter);
1440 iflib_fast_intr(void *arg)
1442 iflib_filter_info_t info = arg;
1443 struct grouptask *gtask = info->ifi_task;
1446 DBG_COUNTER_INC(fast_intrs);
1447 if (info->ifi_filter != NULL) {
1448 result = info->ifi_filter(info->ifi_filter_arg);
1449 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1453 GROUPTASK_ENQUEUE(gtask);
1454 return (FILTER_HANDLED);
1458 iflib_fast_intr_rxtx(void *arg)
1460 iflib_filter_info_t info = arg;
1461 struct grouptask *gtask = info->ifi_task;
1463 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1466 int i, cidx, result;
1468 bool intr_enable, intr_legacy;
1470 DBG_COUNTER_INC(fast_intrs);
1471 if (info->ifi_filter != NULL) {
1472 result = info->ifi_filter(info->ifi_filter_arg);
1473 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1478 sc = ctx->ifc_softc;
1479 intr_enable = false;
1480 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1481 MPASS(rxq->ifr_ntxqirq);
1482 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1483 txqid = rxq->ifr_txqid[i];
1484 txq = &ctx->ifc_txqs[txqid];
1485 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1486 BUS_DMASYNC_POSTREAD);
1487 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1491 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1494 GROUPTASK_ENQUEUE(&txq->ift_task);
1496 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1497 cidx = rxq->ifr_cq_cidx;
1499 cidx = rxq->ifr_fl[0].ifl_cidx;
1500 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1501 GROUPTASK_ENQUEUE(gtask);
1506 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1507 DBG_COUNTER_INC(rx_intr_enables);
1510 IFDI_INTR_ENABLE(ctx);
1511 return (FILTER_HANDLED);
1516 iflib_fast_intr_ctx(void *arg)
1518 iflib_filter_info_t info = arg;
1519 struct grouptask *gtask = info->ifi_task;
1522 DBG_COUNTER_INC(fast_intrs);
1523 if (info->ifi_filter != NULL) {
1524 result = info->ifi_filter(info->ifi_filter_arg);
1525 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1529 GROUPTASK_ENQUEUE(gtask);
1530 return (FILTER_HANDLED);
1534 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1535 driver_filter_t filter, driver_intr_t handler, void *arg,
1538 struct resource *res;
1540 device_t dev = ctx->ifc_dev;
1544 if (ctx->ifc_flags & IFC_LEGACY)
1545 flags |= RF_SHAREABLE;
1548 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1551 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1555 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1556 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1557 filter, handler, arg, &tag);
1560 "failed to setup interrupt for rid %d, name %s: %d\n",
1561 rid, name ? name : "unknown", rc);
1564 bus_describe_intr(dev, res, tag, "%s", name);
1570 /*********************************************************************
1572 * Allocate DMA resources for TX buffers as well as memory for the TX
1573 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1574 * iflib_sw_tx_desc_array structure, storing all the information that
1575 * is needed to transmit a packet on the wire. This is called only
1576 * once at attach, setup is done every reset.
1578 **********************************************************************/
1580 iflib_txsd_alloc(iflib_txq_t txq)
1582 if_ctx_t ctx = txq->ift_ctx;
1583 if_shared_ctx_t sctx = ctx->ifc_sctx;
1584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1585 device_t dev = ctx->ifc_dev;
1586 bus_size_t tsomaxsize;
1587 int err, nsegments, ntsosegments;
1590 nsegments = scctx->isc_tx_nsegments;
1591 ntsosegments = scctx->isc_tx_tso_segments_max;
1592 tsomaxsize = scctx->isc_tx_tso_size_max;
1593 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1594 tsomaxsize += sizeof(struct ether_vlan_header);
1595 MPASS(scctx->isc_ntxd[0] > 0);
1596 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1597 MPASS(nsegments > 0);
1598 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1599 MPASS(ntsosegments > 0);
1600 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1604 * Set up DMA tags for TX buffers.
1606 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1607 1, 0, /* alignment, bounds */
1608 BUS_SPACE_MAXADDR, /* lowaddr */
1609 BUS_SPACE_MAXADDR, /* highaddr */
1610 NULL, NULL, /* filter, filterarg */
1611 sctx->isc_tx_maxsize, /* maxsize */
1612 nsegments, /* nsegments */
1613 sctx->isc_tx_maxsegsize, /* maxsegsize */
1615 NULL, /* lockfunc */
1616 NULL, /* lockfuncarg */
1617 &txq->ift_buf_tag))) {
1618 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1619 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1620 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1623 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1624 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1625 1, 0, /* alignment, bounds */
1626 BUS_SPACE_MAXADDR, /* lowaddr */
1627 BUS_SPACE_MAXADDR, /* highaddr */
1628 NULL, NULL, /* filter, filterarg */
1629 tsomaxsize, /* maxsize */
1630 ntsosegments, /* nsegments */
1631 sctx->isc_tso_maxsegsize,/* maxsegsize */
1633 NULL, /* lockfunc */
1634 NULL, /* lockfuncarg */
1635 &txq->ift_tso_buf_tag))) {
1636 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1641 /* Allocate memory for the TX mbuf map. */
1642 if (!(txq->ift_sds.ifsd_m =
1643 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1644 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1645 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1651 * Create the DMA maps for TX buffers.
1653 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1654 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1655 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1657 "Unable to allocate TX buffer DMA map memory\n");
1661 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1662 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1663 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1665 "Unable to allocate TSO TX buffer map memory\n");
1669 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1670 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1671 &txq->ift_sds.ifsd_map[i]);
1673 device_printf(dev, "Unable to create TX DMA map\n");
1678 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1679 &txq->ift_sds.ifsd_tso_map[i]);
1681 device_printf(dev, "Unable to create TSO TX DMA map\n");
1687 /* We free all, it handles case where we are in the middle */
1688 iflib_tx_structures_free(ctx);
1693 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1697 if (txq->ift_sds.ifsd_map != NULL) {
1698 map = txq->ift_sds.ifsd_map[i];
1699 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1700 bus_dmamap_unload(txq->ift_buf_tag, map);
1701 bus_dmamap_destroy(txq->ift_buf_tag, map);
1702 txq->ift_sds.ifsd_map[i] = NULL;
1705 if (txq->ift_sds.ifsd_tso_map != NULL) {
1706 map = txq->ift_sds.ifsd_tso_map[i];
1707 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1708 BUS_DMASYNC_POSTWRITE);
1709 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1710 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1711 txq->ift_sds.ifsd_tso_map[i] = NULL;
1716 iflib_txq_destroy(iflib_txq_t txq)
1718 if_ctx_t ctx = txq->ift_ctx;
1720 for (int i = 0; i < txq->ift_size; i++)
1721 iflib_txsd_destroy(ctx, txq, i);
1723 if (txq->ift_br != NULL) {
1724 ifmp_ring_free(txq->ift_br);
1728 mtx_destroy(&txq->ift_mtx);
1730 if (txq->ift_sds.ifsd_map != NULL) {
1731 free(txq->ift_sds.ifsd_map, M_IFLIB);
1732 txq->ift_sds.ifsd_map = NULL;
1734 if (txq->ift_sds.ifsd_tso_map != NULL) {
1735 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1736 txq->ift_sds.ifsd_tso_map = NULL;
1738 if (txq->ift_sds.ifsd_m != NULL) {
1739 free(txq->ift_sds.ifsd_m, M_IFLIB);
1740 txq->ift_sds.ifsd_m = NULL;
1742 if (txq->ift_buf_tag != NULL) {
1743 bus_dma_tag_destroy(txq->ift_buf_tag);
1744 txq->ift_buf_tag = NULL;
1746 if (txq->ift_tso_buf_tag != NULL) {
1747 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1748 txq->ift_tso_buf_tag = NULL;
1750 if (txq->ift_ifdi != NULL) {
1751 free(txq->ift_ifdi, M_IFLIB);
1756 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1760 mp = &txq->ift_sds.ifsd_m[i];
1764 if (txq->ift_sds.ifsd_map != NULL) {
1765 bus_dmamap_sync(txq->ift_buf_tag,
1766 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1767 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1769 if (txq->ift_sds.ifsd_tso_map != NULL) {
1770 bus_dmamap_sync(txq->ift_tso_buf_tag,
1771 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1772 bus_dmamap_unload(txq->ift_tso_buf_tag,
1773 txq->ift_sds.ifsd_tso_map[i]);
1776 DBG_COUNTER_INC(tx_frees);
1781 iflib_txq_setup(iflib_txq_t txq)
1783 if_ctx_t ctx = txq->ift_ctx;
1784 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1785 if_shared_ctx_t sctx = ctx->ifc_sctx;
1786 iflib_dma_info_t di;
1789 /* Set number of descriptors available */
1790 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1791 /* XXX make configurable */
1792 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1795 txq->ift_cidx_processed = 0;
1796 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1797 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1799 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1800 bzero((void *)di->idi_vaddr, di->idi_size);
1802 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1803 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1804 bus_dmamap_sync(di->idi_tag, di->idi_map,
1805 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1809 /*********************************************************************
1811 * Allocate DMA resources for RX buffers as well as memory for the RX
1812 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1813 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1814 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1815 * Since we use use one entry in iflib_sw_rx_desc_array per received
1816 * packet, the maximum number of entries we'll need is equal to the
1817 * number of hardware receive descriptors that we've allocated.
1819 **********************************************************************/
1821 iflib_rxsd_alloc(iflib_rxq_t rxq)
1823 if_ctx_t ctx = rxq->ifr_ctx;
1824 if_shared_ctx_t sctx = ctx->ifc_sctx;
1825 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1826 device_t dev = ctx->ifc_dev;
1830 MPASS(scctx->isc_nrxd[0] > 0);
1831 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1834 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1835 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1836 /* Set up DMA tag for RX buffers. */
1837 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1838 1, 0, /* alignment, bounds */
1839 BUS_SPACE_MAXADDR, /* lowaddr */
1840 BUS_SPACE_MAXADDR, /* highaddr */
1841 NULL, NULL, /* filter, filterarg */
1842 sctx->isc_rx_maxsize, /* maxsize */
1843 sctx->isc_rx_nsegments, /* nsegments */
1844 sctx->isc_rx_maxsegsize, /* maxsegsize */
1846 NULL, /* lockfunc */
1851 "Unable to allocate RX DMA tag: %d\n", err);
1855 /* Allocate memory for the RX mbuf map. */
1856 if (!(fl->ifl_sds.ifsd_m =
1857 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1858 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1860 "Unable to allocate RX mbuf map memory\n");
1865 /* Allocate memory for the direct RX cluster pointer map. */
1866 if (!(fl->ifl_sds.ifsd_cl =
1867 (caddr_t *) malloc(sizeof(caddr_t) *
1868 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1870 "Unable to allocate RX cluster map memory\n");
1875 /* Allocate memory for the RX cluster bus address map. */
1876 if (!(fl->ifl_sds.ifsd_ba =
1877 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1878 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1880 "Unable to allocate RX bus address map memory\n");
1886 * Create the DMA maps for RX buffers.
1888 if (!(fl->ifl_sds.ifsd_map =
1889 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1891 "Unable to allocate RX buffer DMA map memory\n");
1895 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1896 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1897 &fl->ifl_sds.ifsd_map[i]);
1899 device_printf(dev, "Unable to create RX buffer DMA map\n");
1907 iflib_rx_structures_free(ctx);
1913 * Internal service routines
1916 struct rxq_refill_cb_arg {
1918 bus_dma_segment_t seg;
1923 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1925 struct rxq_refill_cb_arg *cb_arg = arg;
1927 cb_arg->error = error;
1928 cb_arg->seg = segs[0];
1929 cb_arg->nseg = nseg;
1933 * iflib_fl_refill - refill an rxq free-buffer list
1934 * @ctx: the iflib context
1935 * @fl: the free list to refill
1936 * @count: the number of new buffers to allocate
1938 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1939 * The caller must assure that @count does not exceed the queue's capacity.
1942 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1944 struct if_rxd_update iru;
1945 struct rxq_refill_cb_arg cb_arg;
1949 bus_dmamap_t *sd_map;
1950 bus_addr_t bus_addr, *sd_ba;
1951 int err, frag_idx, i, idx, n, pidx;
1954 sd_m = fl->ifl_sds.ifsd_m;
1955 sd_map = fl->ifl_sds.ifsd_map;
1956 sd_cl = fl->ifl_sds.ifsd_cl;
1957 sd_ba = fl->ifl_sds.ifsd_ba;
1958 pidx = fl->ifl_pidx;
1960 frag_idx = fl->ifl_fragidx;
1961 credits = fl->ifl_credits;
1966 MPASS(credits + n <= fl->ifl_size);
1968 if (pidx < fl->ifl_cidx)
1969 MPASS(pidx + n <= fl->ifl_cidx);
1970 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1971 MPASS(fl->ifl_gen == 0);
1972 if (pidx > fl->ifl_cidx)
1973 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1975 DBG_COUNTER_INC(fl_refills);
1977 DBG_COUNTER_INC(fl_refills_large);
1978 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1981 * We allocate an uninitialized mbuf + cluster, mbuf is
1982 * initialized after rx.
1984 * If the cluster is still set then we know a minimum sized
1985 * packet was received
1987 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1990 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1991 MPASS(frag_idx >= 0);
1992 if ((cl = sd_cl[frag_idx]) == NULL) {
1993 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
1994 if (__predict_false(cl == NULL))
1998 MPASS(sd_map != NULL);
1999 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2000 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2002 if (__predict_false(err != 0 || cb_arg.error)) {
2003 uma_zfree(fl->ifl_zone, cl);
2007 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2008 sd_cl[frag_idx] = cl;
2010 fl->ifl_cl_enqueued++;
2013 bus_addr = sd_ba[frag_idx];
2015 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2016 BUS_DMASYNC_PREREAD);
2018 if (sd_m[frag_idx] == NULL) {
2019 m = m_gethdr(M_NOWAIT, MT_NOINIT);
2020 if (__predict_false(m == NULL))
2024 bit_set(fl->ifl_rx_bitmap, frag_idx);
2026 fl->ifl_m_enqueued++;
2029 DBG_COUNTER_INC(rx_allocs);
2030 fl->ifl_rxd_idxs[i] = frag_idx;
2031 fl->ifl_bus_addrs[i] = bus_addr;
2034 MPASS(credits <= fl->ifl_size);
2035 if (++idx == fl->ifl_size) {
2041 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2042 iru.iru_pidx = pidx;
2044 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2046 fl->ifl_credits = credits;
2052 if (n < count - 1) {
2054 iru.iru_pidx = pidx;
2056 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2058 fl->ifl_credits = credits;
2060 DBG_COUNTER_INC(rxd_flush);
2061 if (fl->ifl_pidx == 0)
2062 pidx = fl->ifl_size - 1;
2064 pidx = fl->ifl_pidx - 1;
2066 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2068 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2070 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2071 fl->ifl_fragidx = frag_idx + 1;
2072 if (fl->ifl_fragidx == fl->ifl_size)
2073 fl->ifl_fragidx = 0;
2075 fl->ifl_fragidx = frag_idx;
2079 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2082 static inline uint8_t
2083 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2085 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2086 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2088 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2091 MPASS(fl->ifl_credits <= fl->ifl_size);
2092 MPASS(reclaimable == delta);
2094 if (reclaimable > 0)
2095 return (iflib_fl_refill(ctx, fl, reclaimable));
2100 iflib_in_detach(if_ctx_t ctx)
2105 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2111 iflib_fl_bufs_free(iflib_fl_t fl)
2113 iflib_dma_info_t idi = fl->ifl_ifdi;
2114 bus_dmamap_t sd_map;
2117 for (i = 0; i < fl->ifl_size; i++) {
2118 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2119 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2121 if (*sd_cl != NULL) {
2122 sd_map = fl->ifl_sds.ifsd_map[i];
2123 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2124 BUS_DMASYNC_POSTREAD);
2125 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2126 uma_zfree(fl->ifl_zone, *sd_cl);
2128 if (*sd_m != NULL) {
2129 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2130 uma_zfree(zone_mbuf, *sd_m);
2134 MPASS(*sd_m == NULL);
2137 fl->ifl_m_dequeued++;
2138 fl->ifl_cl_dequeued++;
2142 for (i = 0; i < fl->ifl_size; i++) {
2143 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2144 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2148 * Reset free list values
2150 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2151 bzero(idi->idi_vaddr, idi->idi_size);
2154 /*********************************************************************
2156 * Initialize a free list and its buffers.
2158 **********************************************************************/
2160 iflib_fl_setup(iflib_fl_t fl)
2162 iflib_rxq_t rxq = fl->ifl_rxq;
2163 if_ctx_t ctx = rxq->ifr_ctx;
2164 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2167 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2169 ** Free current RX buffer structs and their mbufs
2171 iflib_fl_bufs_free(fl);
2172 /* Now replenish the mbufs */
2173 MPASS(fl->ifl_credits == 0);
2174 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2175 if (scctx->isc_rxd_buf_size[qidx] != 0)
2176 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2178 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2180 * ifl_buf_size may be a driver-supplied value, so pull it up
2181 * to the selected mbuf size.
2183 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2184 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2185 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2186 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2187 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2190 /* avoid pre-allocating zillions of clusters to an idle card
2191 * potentially speeding up attach
2193 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2194 MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2195 if (min(128, fl->ifl_size) != fl->ifl_credits)
2201 MPASS(fl->ifl_ifdi != NULL);
2202 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2203 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2207 /*********************************************************************
2209 * Free receive ring data structures
2211 **********************************************************************/
2213 iflib_rx_sds_free(iflib_rxq_t rxq)
2218 if (rxq->ifr_fl != NULL) {
2219 for (i = 0; i < rxq->ifr_nfl; i++) {
2220 fl = &rxq->ifr_fl[i];
2221 if (fl->ifl_buf_tag != NULL) {
2222 if (fl->ifl_sds.ifsd_map != NULL) {
2223 for (j = 0; j < fl->ifl_size; j++) {
2226 fl->ifl_sds.ifsd_map[j],
2227 BUS_DMASYNC_POSTREAD);
2230 fl->ifl_sds.ifsd_map[j]);
2233 fl->ifl_sds.ifsd_map[j]);
2236 bus_dma_tag_destroy(fl->ifl_buf_tag);
2237 fl->ifl_buf_tag = NULL;
2239 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2240 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2241 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2242 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2243 fl->ifl_sds.ifsd_m = NULL;
2244 fl->ifl_sds.ifsd_cl = NULL;
2245 fl->ifl_sds.ifsd_ba = NULL;
2246 fl->ifl_sds.ifsd_map = NULL;
2248 free(rxq->ifr_fl, M_IFLIB);
2250 free(rxq->ifr_ifdi, M_IFLIB);
2251 rxq->ifr_ifdi = NULL;
2252 rxq->ifr_cq_cidx = 0;
2260 iflib_timer(void *arg)
2262 iflib_txq_t txq = arg;
2263 if_ctx_t ctx = txq->ift_ctx;
2264 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2265 uint64_t this_tick = ticks;
2266 uint32_t reset_on = hz / 2;
2268 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2272 ** Check on the state of the TX queue(s), this
2273 ** can be done without the lock because its RO
2274 ** and the HUNG state will be static if set.
2276 if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2277 txq->ift_last_timer_tick = this_tick;
2278 IFDI_TIMER(ctx, txq->ift_id);
2279 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2280 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2281 (sctx->isc_pause_frames == 0)))
2284 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2285 ifmp_ring_is_stalled(txq->ift_br)) {
2286 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2287 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2289 txq->ift_cleaned_prev = txq->ift_cleaned;
2292 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2293 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2295 /* handle any laggards */
2296 if (txq->ift_db_pending)
2297 GROUPTASK_ENQUEUE(&txq->ift_task);
2299 sctx->isc_pause_frames = 0;
2300 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2301 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2305 device_printf(ctx->ifc_dev,
2306 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2307 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2309 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2310 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2311 iflib_admin_intr_deferred(ctx);
2316 iflib_get_mbuf_size_for(unsigned int size)
2319 if (size <= MCLBYTES)
2322 return (MJUMPAGESIZE);
2326 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2328 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2331 * XXX don't set the max_frame_size to larger
2332 * than the hardware can handle
2334 ctx->ifc_rx_mbuf_sz =
2335 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2339 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2342 return (ctx->ifc_rx_mbuf_sz);
2346 iflib_init_locked(if_ctx_t ctx)
2348 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2349 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2350 if_t ifp = ctx->ifc_ifp;
2354 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2356 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2357 IFDI_INTR_DISABLE(ctx);
2359 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2360 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2361 /* Set hardware offload abilities */
2362 if_clearhwassist(ifp);
2363 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2364 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2365 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2366 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2367 if (if_getcapenable(ifp) & IFCAP_TSO4)
2368 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2369 if (if_getcapenable(ifp) & IFCAP_TSO6)
2370 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2372 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2374 callout_stop(&txq->ift_timer);
2375 CALLOUT_UNLOCK(txq);
2376 iflib_netmap_txq_init(ctx, txq);
2380 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2381 * that drivers can use the value when setting up the hardware receive
2384 iflib_calc_rx_mbuf_sz(ctx);
2387 i = if_getdrvflags(ifp);
2390 MPASS(if_getdrvflags(ifp) == i);
2391 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2392 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2393 /* This rxq is in netmap mode. Skip normal init. */
2396 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2397 if (iflib_fl_setup(fl)) {
2398 device_printf(ctx->ifc_dev,
2399 "setting up free list %d failed - "
2400 "check cluster settings\n", j);
2406 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2407 IFDI_INTR_ENABLE(ctx);
2408 txq = ctx->ifc_txqs;
2409 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2410 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2411 txq->ift_timer.c_cpu);
2415 iflib_media_change(if_t ifp)
2417 if_ctx_t ctx = if_getsoftc(ifp);
2421 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2422 iflib_init_locked(ctx);
2428 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2430 if_ctx_t ctx = if_getsoftc(ifp);
2433 IFDI_UPDATE_ADMIN_STATUS(ctx);
2434 IFDI_MEDIA_STATUS(ctx, ifmr);
2439 iflib_stop(if_ctx_t ctx)
2441 iflib_txq_t txq = ctx->ifc_txqs;
2442 iflib_rxq_t rxq = ctx->ifc_rxqs;
2443 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2444 if_shared_ctx_t sctx = ctx->ifc_sctx;
2445 iflib_dma_info_t di;
2449 /* Tell the stack that the interface is no longer active */
2450 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2452 IFDI_INTR_DISABLE(ctx);
2457 iflib_debug_reset();
2458 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2459 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2460 /* make sure all transmitters have completed before proceeding XXX */
2463 callout_stop(&txq->ift_timer);
2464 CALLOUT_UNLOCK(txq);
2466 /* clean any enqueued buffers */
2467 iflib_ifmp_purge(txq);
2468 /* Free any existing tx buffers. */
2469 for (j = 0; j < txq->ift_size; j++) {
2470 iflib_txsd_free(ctx, txq, j);
2472 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2473 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2474 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2475 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2476 txq->ift_pullups = 0;
2477 ifmp_ring_reset_stats(txq->ift_br);
2478 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2479 bzero((void *)di->idi_vaddr, di->idi_size);
2481 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2482 /* make sure all transmitters have completed before proceeding XXX */
2484 rxq->ifr_cq_cidx = 0;
2485 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2486 bzero((void *)di->idi_vaddr, di->idi_size);
2487 /* also resets the free lists pidx/cidx */
2488 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2489 iflib_fl_bufs_free(fl);
2493 static inline caddr_t
2494 calc_next_rxd(iflib_fl_t fl, int cidx)
2498 caddr_t start, end, cur, next;
2500 nrxd = fl->ifl_size;
2501 size = fl->ifl_rxd_size;
2502 start = fl->ifl_ifdi->idi_vaddr;
2504 if (__predict_false(size == 0))
2506 cur = start + size*cidx;
2507 end = start + size*nrxd;
2508 next = CACHE_PTR_NEXT(cur);
2509 return (next < end ? next : start);
2513 prefetch_pkts(iflib_fl_t fl, int cidx)
2516 int nrxd = fl->ifl_size;
2520 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2521 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2522 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2523 next_rxd = calc_next_rxd(fl, cidx);
2525 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2526 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2527 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2528 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2529 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2530 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2531 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2532 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2535 static struct mbuf *
2536 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2537 int *pf_rv, if_rxd_info_t ri)
2543 int flid, cidx, len, next;
2546 flid = irf->irf_flid;
2547 cidx = irf->irf_idx;
2548 fl = &rxq->ifr_fl[flid];
2550 m = fl->ifl_sds.ifsd_m[cidx];
2551 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2554 fl->ifl_m_dequeued++;
2556 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2557 prefetch_pkts(fl, cidx);
2558 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2559 prefetch(&fl->ifl_sds.ifsd_map[next]);
2560 map = fl->ifl_sds.ifsd_map[cidx];
2562 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2564 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2565 irf->irf_len != 0) {
2566 payload = *sd->ifsd_cl;
2567 payload += ri->iri_pad;
2568 len = ri->iri_len - ri->iri_pad;
2569 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2570 len | PFIL_MEMPTR | PFIL_IN, NULL);
2575 * The filter ate it. Everything is recycled.
2580 case PFIL_REALLOCED:
2582 * The filter copied it. Everything is recycled.
2584 m = pfil_mem2mbuf(payload);
2589 * Filter said it was OK, so receive like
2592 fl->ifl_sds.ifsd_m[cidx] = NULL;
2598 fl->ifl_sds.ifsd_m[cidx] = NULL;
2602 if (unload && irf->irf_len != 0)
2603 bus_dmamap_unload(fl->ifl_buf_tag, map);
2604 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2605 if (__predict_false(fl->ifl_cidx == 0))
2607 bit_clear(fl->ifl_rx_bitmap, cidx);
2611 static struct mbuf *
2612 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2614 struct mbuf *m, *mh, *mt;
2616 int *pf_rv_ptr, flags, i, padlen;
2625 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2628 MPASS(*sd->ifsd_cl != NULL);
2631 * Exclude zero-length frags & frags from
2632 * packets the filter has consumed or dropped
2634 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2635 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2637 /* everything saved here */
2642 /* XXX we can save the cluster here, but not the mbuf */
2643 m_init(m, M_NOWAIT, MT_DATA, 0);
2648 flags = M_PKTHDR|M_EXT;
2650 padlen = ri->iri_pad;
2655 /* assuming padding is only on the first fragment */
2659 *sd->ifsd_cl = NULL;
2661 /* Can these two be made one ? */
2662 m_init(m, M_NOWAIT, MT_DATA, flags);
2663 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2665 * These must follow m_init and m_cljset
2667 m->m_data += padlen;
2668 ri->iri_len -= padlen;
2669 m->m_len = ri->iri_frags[i].irf_len;
2670 } while (++i < ri->iri_nfrags);
2676 * Process one software descriptor
2678 static struct mbuf *
2679 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2685 /* should I merge this back in now that the two paths are basically duplicated? */
2686 if (ri->iri_nfrags == 1 &&
2687 ri->iri_frags[0].irf_len != 0 &&
2688 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2689 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2691 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2693 if (pf_rv == PFIL_PASS) {
2694 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2695 #ifndef __NO_STRICT_ALIGNMENT
2699 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2700 m->m_len = ri->iri_frags[0].irf_len;
2703 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2706 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2709 m->m_pkthdr.len = ri->iri_len;
2710 m->m_pkthdr.rcvif = ri->iri_ifp;
2711 m->m_flags |= ri->iri_flags;
2712 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2713 m->m_pkthdr.flowid = ri->iri_flowid;
2714 M_HASHTYPE_SET(m, ri->iri_rsstype);
2715 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2716 m->m_pkthdr.csum_data = ri->iri_csum_data;
2720 #if defined(INET6) || defined(INET)
2722 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2724 CURVNET_SET(lc->ifp->if_vnet);
2726 *v6 = V_ip6_forwarding;
2729 *v4 = V_ipforwarding;
2735 * Returns true if it's possible this packet could be LROed.
2736 * if it returns false, it is guaranteed that tcp_lro_rx()
2737 * would not return zero.
2740 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2742 struct ether_header *eh;
2744 eh = mtod(m, struct ether_header *);
2745 switch (eh->ether_type) {
2747 case htons(ETHERTYPE_IPV6):
2748 return (!v6_forwarding);
2751 case htons(ETHERTYPE_IP):
2752 return (!v4_forwarding);
2760 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2766 _task_fn_rx_watchdog(void *context)
2768 iflib_rxq_t rxq = context;
2770 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2774 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2777 if_ctx_t ctx = rxq->ifr_ctx;
2778 if_shared_ctx_t sctx = ctx->ifc_sctx;
2779 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2782 struct if_rxd_info ri;
2783 int err, budget_left, rx_bytes, rx_pkts;
2786 bool v4_forwarding, v6_forwarding, lro_possible;
2790 * XXX early demux data packets so that if_input processing only handles
2791 * acks in interrupt context
2793 struct mbuf *m, *mh, *mt, *mf;
2797 lro_possible = v4_forwarding = v6_forwarding = false;
2801 rx_pkts = rx_bytes = 0;
2802 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2803 cidxp = &rxq->ifr_cq_cidx;
2805 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2806 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2807 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2808 retval |= iflib_fl_refill_all(ctx, fl);
2809 DBG_COUNTER_INC(rx_unavail);
2813 /* pfil needs the vnet to be set */
2814 CURVNET_SET_QUIET(ifp->if_vnet);
2815 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2816 if (__predict_false(!CTX_ACTIVE(ctx))) {
2817 DBG_COUNTER_INC(rx_ctx_inactive);
2821 * Reset client set fields to their default values
2824 ri.iri_qsidx = rxq->ifr_id;
2825 ri.iri_cidx = *cidxp;
2827 ri.iri_frags = rxq->ifr_frags;
2828 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2833 rx_bytes += ri.iri_len;
2834 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2835 *cidxp = ri.iri_cidx;
2836 /* Update our consumer index */
2837 /* XXX NB: shurd - check if this is still safe */
2838 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2839 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2840 /* was this only a completion queue message? */
2841 if (__predict_false(ri.iri_nfrags == 0))
2844 MPASS(ri.iri_nfrags != 0);
2845 MPASS(ri.iri_len != 0);
2847 /* will advance the cidx on the corresponding free lists */
2848 m = iflib_rxd_pkt_get(rxq, &ri);
2851 if (avail == 0 && budget_left)
2852 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2854 if (__predict_false(m == NULL))
2857 /* imm_pkt: -- cxgb */
2866 /* make sure that we can refill faster than drain */
2867 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2868 retval |= iflib_fl_refill_all(ctx, fl);
2870 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2872 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2874 while (mh != NULL) {
2877 m->m_nextpkt = NULL;
2878 #ifndef __NO_STRICT_ALIGNMENT
2879 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2882 rx_bytes += m->m_pkthdr.len;
2884 #if defined(INET6) || defined(INET)
2886 if (!lro_possible) {
2887 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2888 if (lro_possible && mf != NULL) {
2889 ifp->if_input(ifp, mf);
2890 DBG_COUNTER_INC(rx_if_input);
2894 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2895 (CSUM_L4_CALC|CSUM_L4_VALID)) {
2896 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2902 ifp->if_input(ifp, m);
2903 DBG_COUNTER_INC(rx_if_input);
2914 ifp->if_input(ifp, mf);
2915 DBG_COUNTER_INC(rx_if_input);
2918 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2919 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2922 * Flush any outstanding LRO work
2924 #if defined(INET6) || defined(INET)
2925 tcp_lro_flush_all(&rxq->ifr_lc);
2927 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2928 retval |= IFLIB_RXEOF_MORE;
2932 ctx->ifc_flags |= IFC_DO_RESET;
2933 iflib_admin_intr_deferred(ctx);
2938 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2939 static inline qidx_t
2940 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2942 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2943 qidx_t minthresh = txq->ift_size / 8;
2944 if (in_use > 4*minthresh)
2945 return (notify_count);
2946 if (in_use > 2*minthresh)
2947 return (notify_count >> 1);
2948 if (in_use > minthresh)
2949 return (notify_count >> 3);
2953 static inline qidx_t
2954 txq_max_rs_deferred(iflib_txq_t txq)
2956 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2957 qidx_t minthresh = txq->ift_size / 8;
2958 if (txq->ift_in_use > 4*minthresh)
2959 return (notify_count);
2960 if (txq->ift_in_use > 2*minthresh)
2961 return (notify_count >> 1);
2962 if (txq->ift_in_use > minthresh)
2963 return (notify_count >> 2);
2967 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2968 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2970 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2971 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2972 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2974 /* forward compatibility for cxgb */
2975 #define FIRST_QSET(ctx) 0
2976 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2977 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2978 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2979 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2981 /* XXX we should be setting this to something other than zero */
2982 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2983 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2984 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2987 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2993 max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2994 if (ring || txq->ift_db_pending >= max) {
2995 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2996 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2998 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2999 txq->ift_db_pending = txq->ift_npending = 0;
3007 print_pkt(if_pkt_info_t pi)
3009 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3010 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3011 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3012 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3013 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3014 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3018 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3019 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3020 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3021 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3024 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3026 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3027 struct ether_vlan_header *eh;
3031 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3032 M_WRITABLE(m) == 0) {
3033 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3037 DBG_COUNTER_INC(tx_frees);
3043 * Determine where frame payload starts.
3044 * Jump over vlan headers if already present,
3045 * helpful for QinQ too.
3047 if (__predict_false(m->m_len < sizeof(*eh))) {
3049 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3052 eh = mtod(m, struct ether_vlan_header *);
3053 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3054 pi->ipi_etype = ntohs(eh->evl_proto);
3055 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3057 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3058 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3061 switch (pi->ipi_etype) {
3066 struct ip *ip = NULL;
3067 struct tcphdr *th = NULL;
3070 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3071 if (__predict_false(m->m_len < minthlen)) {
3073 * if this code bloat is causing too much of a hit
3074 * move it to a separate function and mark it noinline
3076 if (m->m_len == pi->ipi_ehdrlen) {
3079 if (n->m_len >= sizeof(*ip)) {
3080 ip = (struct ip *)n->m_data;
3081 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3082 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3085 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3087 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3091 if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3093 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3094 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3095 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3098 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3099 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3100 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3102 pi->ipi_ip_hlen = ip->ip_hl << 2;
3103 pi->ipi_ipproto = ip->ip_p;
3104 pi->ipi_flags |= IPI_TX_IPV4;
3106 /* TCP checksum offload may require TCP header length */
3107 if (IS_TX_OFFLOAD4(pi)) {
3108 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3109 if (__predict_false(th == NULL)) {
3111 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3113 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3115 pi->ipi_tcp_hflags = th->th_flags;
3116 pi->ipi_tcp_hlen = th->th_off << 2;
3117 pi->ipi_tcp_seq = th->th_seq;
3120 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3123 * TSO always requires hardware checksum offload.
3125 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3126 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3127 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3128 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3129 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3131 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3135 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3142 case ETHERTYPE_IPV6:
3144 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3146 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3148 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3150 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3153 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3155 /* XXX-BZ this will go badly in case of ext hdrs. */
3156 pi->ipi_ipproto = ip6->ip6_nxt;
3157 pi->ipi_flags |= IPI_TX_IPV6;
3159 /* TCP checksum offload may require TCP header length */
3160 if (IS_TX_OFFLOAD6(pi)) {
3161 if (pi->ipi_ipproto == IPPROTO_TCP) {
3162 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3164 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3167 pi->ipi_tcp_hflags = th->th_flags;
3168 pi->ipi_tcp_hlen = th->th_off << 2;
3169 pi->ipi_tcp_seq = th->th_seq;
3172 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3175 * TSO always requires hardware checksum offload.
3177 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3178 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3179 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3186 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3187 pi->ipi_ip_hlen = 0;
3196 * If dodgy hardware rejects the scatter gather chain we've handed it
3197 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3200 static __noinline struct mbuf *
3201 iflib_remove_mbuf(iflib_txq_t txq)
3204 struct mbuf *m, **ifsd_m;
3206 ifsd_m = txq->ift_sds.ifsd_m;
3207 ntxd = txq->ift_size;
3208 pidx = txq->ift_pidx & (ntxd - 1);
3209 ifsd_m = txq->ift_sds.ifsd_m;
3211 ifsd_m[pidx] = NULL;
3212 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3213 if (txq->ift_sds.ifsd_tso_map != NULL)
3214 bus_dmamap_unload(txq->ift_tso_buf_tag,
3215 txq->ift_sds.ifsd_tso_map[pidx]);
3217 txq->ift_dequeued++;
3222 static inline caddr_t
3223 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3227 caddr_t start, end, cur, next;
3229 ntxd = txq->ift_size;
3230 size = txq->ift_txd_size[qid];
3231 start = txq->ift_ifdi[qid].idi_vaddr;
3233 if (__predict_false(size == 0))
3235 cur = start + size*cidx;
3236 end = start + size*ntxd;
3237 next = CACHE_PTR_NEXT(cur);
3238 return (next < end ? next : start);
3242 * Pad an mbuf to ensure a minimum ethernet frame size.
3243 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3245 static __noinline int
3246 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3249 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3250 * and ARP message is the smallest common payload I can think of
3252 static char pad[18]; /* just zeros */
3254 struct mbuf *new_head;
3256 if (!M_WRITABLE(*m_head)) {
3257 new_head = m_dup(*m_head, M_NOWAIT);
3258 if (new_head == NULL) {
3260 device_printf(dev, "cannot pad short frame, m_dup() failed");
3261 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3262 DBG_COUNTER_INC(tx_frees);
3269 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3270 n > 0; n -= sizeof(pad))
3271 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3276 device_printf(dev, "cannot pad short frame\n");
3277 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3278 DBG_COUNTER_INC(tx_frees);
3286 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3289 if_shared_ctx_t sctx;
3290 if_softc_ctx_t scctx;
3291 bus_dma_tag_t buf_tag;
3292 bus_dma_segment_t *segs;
3293 struct mbuf *m_head, **ifsd_m;
3296 struct if_pkt_info pi;
3298 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3301 sctx = ctx->ifc_sctx;
3302 scctx = &ctx->ifc_softc_ctx;
3303 segs = txq->ift_segs;
3304 ntxd = txq->ift_size;
3309 * If we're doing TSO the next descriptor to clean may be quite far ahead
3311 cidx = txq->ift_cidx;
3312 pidx = txq->ift_pidx;
3313 if (ctx->ifc_flags & IFC_PREFETCH) {
3314 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3315 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3316 next_txd = calc_next_txd(txq, cidx, 0);
3320 /* prefetch the next cache line of mbuf pointers and flags */
3321 prefetch(&txq->ift_sds.ifsd_m[next]);
3322 prefetch(&txq->ift_sds.ifsd_map[next]);
3323 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3325 map = txq->ift_sds.ifsd_map[pidx];
3326 ifsd_m = txq->ift_sds.ifsd_m;
3328 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3329 buf_tag = txq->ift_tso_buf_tag;
3330 max_segs = scctx->isc_tx_tso_segments_max;
3331 map = txq->ift_sds.ifsd_tso_map[pidx];
3332 MPASS(buf_tag != NULL);
3333 MPASS(max_segs > 0);
3335 buf_tag = txq->ift_buf_tag;
3336 max_segs = scctx->isc_tx_nsegments;
3337 map = txq->ift_sds.ifsd_map[pidx];
3339 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3340 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3341 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3343 DBG_COUNTER_INC(encap_txd_encap_fail);
3350 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3352 pi.ipi_qsidx = txq->ift_id;
3353 pi.ipi_len = m_head->m_pkthdr.len;
3354 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3355 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3357 /* deliberate bitwise OR to make one condition */
3358 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3359 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3360 DBG_COUNTER_INC(encap_txd_encap_fail);
3367 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3370 if (__predict_false(err)) {
3373 /* try collapse once and defrag once */
3375 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3376 /* try defrag if collapsing fails */
3381 txq->ift_mbuf_defrag++;
3382 m_head = m_defrag(*m_headp, M_NOWAIT);
3385 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3386 * failed to map an mbuf that was run through m_defrag
3389 if (__predict_false(m_head == NULL || remap > 1))
3396 txq->ift_no_tx_dma_setup++;
3399 txq->ift_no_tx_dma_setup++;
3401 DBG_COUNTER_INC(tx_frees);
3405 txq->ift_map_failed++;
3406 DBG_COUNTER_INC(encap_load_mbuf_fail);
3407 DBG_COUNTER_INC(encap_txd_encap_fail);
3410 ifsd_m[pidx] = m_head;
3412 * XXX assumes a 1 to 1 relationship between segments and
3413 * descriptors - this does not hold true on all drivers, e.g.
3416 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3417 txq->ift_no_desc_avail++;
3418 bus_dmamap_unload(buf_tag, map);
3419 DBG_COUNTER_INC(encap_txq_avail_fail);
3420 DBG_COUNTER_INC(encap_txd_encap_fail);
3421 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3422 GROUPTASK_ENQUEUE(&txq->ift_task);
3426 * On Intel cards we can greatly reduce the number of TX interrupts
3427 * we see by only setting report status on every Nth descriptor.
3428 * However, this also means that the driver will need to keep track
3429 * of the descriptors that RS was set on to check them for the DD bit.
3431 txq->ift_rs_pending += nsegs + 1;
3432 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3433 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3434 pi.ipi_flags |= IPI_TX_INTR;
3435 txq->ift_rs_pending = 0;
3439 pi.ipi_nsegs = nsegs;
3441 MPASS(pidx >= 0 && pidx < txq->ift_size);
3445 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3446 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3447 DBG_COUNTER_INC(tx_encap);
3448 MPASS(pi.ipi_new_pidx < txq->ift_size);
3450 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3451 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3452 ndesc += txq->ift_size;
3456 * drivers can need as many as
3459 MPASS(ndesc <= pi.ipi_nsegs + 2);
3460 MPASS(pi.ipi_new_pidx != pidx);
3462 txq->ift_in_use += ndesc;
3465 * We update the last software descriptor again here because there may
3466 * be a sentinel and/or there may be more mbufs than segments
3468 txq->ift_pidx = pi.ipi_new_pidx;
3469 txq->ift_npending += pi.ipi_ndescs;
3471 *m_headp = m_head = iflib_remove_mbuf(txq);
3473 txq->ift_txd_encap_efbig++;
3482 * err can't possibly be non-zero here, so we don't neet to test it
3483 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3488 txq->ift_mbuf_defrag_failed++;
3489 txq->ift_map_failed++;
3491 DBG_COUNTER_INC(tx_frees);
3493 DBG_COUNTER_INC(encap_txd_encap_fail);
3498 iflib_tx_desc_free(iflib_txq_t txq, int n)
3500 uint32_t qsize, cidx, mask, gen;
3501 struct mbuf *m, **ifsd_m;
3504 cidx = txq->ift_cidx;
3506 qsize = txq->ift_size;
3508 ifsd_m = txq->ift_sds.ifsd_m;
3509 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3513 prefetch(ifsd_m[(cidx + 3) & mask]);
3514 prefetch(ifsd_m[(cidx + 4) & mask]);
3516 if ((m = ifsd_m[cidx]) != NULL) {
3517 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3518 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3519 bus_dmamap_sync(txq->ift_tso_buf_tag,
3520 txq->ift_sds.ifsd_tso_map[cidx],
3521 BUS_DMASYNC_POSTWRITE);
3522 bus_dmamap_unload(txq->ift_tso_buf_tag,
3523 txq->ift_sds.ifsd_tso_map[cidx]);
3525 bus_dmamap_sync(txq->ift_buf_tag,
3526 txq->ift_sds.ifsd_map[cidx],
3527 BUS_DMASYNC_POSTWRITE);
3528 bus_dmamap_unload(txq->ift_buf_tag,
3529 txq->ift_sds.ifsd_map[cidx]);
3531 /* XXX we don't support any drivers that batch packets yet */
3532 MPASS(m->m_nextpkt == NULL);
3534 ifsd_m[cidx] = NULL;
3536 txq->ift_dequeued++;
3538 DBG_COUNTER_INC(tx_frees);
3540 if (__predict_false(++cidx == qsize)) {
3545 txq->ift_cidx = cidx;
3550 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3553 if_ctx_t ctx = txq->ift_ctx;
3555 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3556 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3559 * Need a rate-limiting check so that this isn't called every time
3561 iflib_tx_credits_update(ctx, txq);
3562 reclaim = DESC_RECLAIMABLE(txq);
3564 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3566 if (iflib_verbose_debug) {
3567 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3568 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3575 iflib_tx_desc_free(txq, reclaim);
3576 txq->ift_cleaned += reclaim;
3577 txq->ift_in_use -= reclaim;
3582 static struct mbuf **
3583 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3586 struct mbuf **items;
3589 next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3590 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3592 prefetch(items[(cidx + offset) & (size-1)]);
3593 if (remaining > 1) {
3594 prefetch2cachelines(&items[next]);
3595 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3596 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3597 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3599 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3603 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3606 ifmp_ring_check_drainage(txq->ift_br, budget);
3610 iflib_txq_can_drain(struct ifmp_ring *r)
3612 iflib_txq_t txq = r->cookie;
3613 if_ctx_t ctx = txq->ift_ctx;
3615 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3617 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3618 BUS_DMASYNC_POSTREAD);
3619 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3624 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3626 iflib_txq_t txq = r->cookie;
3627 if_ctx_t ctx = txq->ift_ctx;
3628 if_t ifp = ctx->ifc_ifp;
3629 struct mbuf *m, **mp;
3630 int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3631 int mcast_sent, pkt_sent, reclaimed, txq_avail;
3632 bool do_prefetch, rang, ring;
3634 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3635 !LINK_ACTIVE(ctx))) {
3636 DBG_COUNTER_INC(txq_drain_notready);
3639 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3640 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3641 avail = IDXDIFF(pidx, cidx, r->size);
3642 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3643 DBG_COUNTER_INC(txq_drain_flushing);
3644 for (i = 0; i < avail; i++) {
3645 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3646 m_free(r->items[(cidx + i) & (r->size-1)]);
3647 r->items[(cidx + i) & (r->size-1)] = NULL;
3652 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3653 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3655 callout_stop(&txq->ift_timer);
3656 CALLOUT_UNLOCK(txq);
3657 DBG_COUNTER_INC(txq_drain_oactive);
3661 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3662 consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3663 count = MIN(avail, TX_BATCH_SIZE);
3665 if (iflib_verbose_debug)
3666 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3667 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3669 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3670 txq_avail = TXQ_AVAIL(txq);
3672 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3673 int rem = do_prefetch ? count - i : 0;
3675 mp = _ring_peek_one(r, cidx, i, rem);
3676 MPASS(mp != NULL && *mp != NULL);
3677 if (__predict_false(*mp == (struct mbuf *)txq)) {
3681 in_use_prev = txq->ift_in_use;
3682 err = iflib_encap(txq, mp);
3683 if (__predict_false(err)) {
3684 /* no room - bail out */
3688 /* we can't send this packet - skip it */
3694 DBG_COUNTER_INC(tx_sent);
3695 bytes_sent += m->m_pkthdr.len;
3696 mcast_sent += !!(m->m_flags & M_MCAST);
3697 txq_avail = TXQ_AVAIL(txq);
3699 txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3700 ETHER_BPF_MTAP(ifp, m);
3701 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3703 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3706 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3707 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3708 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3709 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3710 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3712 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3714 if (iflib_verbose_debug)
3715 printf("consumed=%d\n", consumed);
3721 iflib_txq_drain_always(struct ifmp_ring *r)
3727 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3735 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3737 callout_stop(&txq->ift_timer);
3738 CALLOUT_UNLOCK(txq);
3740 avail = IDXDIFF(pidx, cidx, r->size);
3741 for (i = 0; i < avail; i++) {
3742 mp = _ring_peek_one(r, cidx, i, avail - i);
3743 if (__predict_false(*mp == (struct mbuf *)txq))
3746 DBG_COUNTER_INC(tx_frees);
3748 MPASS(ifmp_ring_is_stalled(r) == 0);
3753 iflib_ifmp_purge(iflib_txq_t txq)
3755 struct ifmp_ring *r;
3758 r->drain = iflib_txq_drain_free;
3759 r->can_drain = iflib_txq_drain_always;
3761 ifmp_ring_check_drainage(r, r->size);
3763 r->drain = iflib_txq_drain;
3764 r->can_drain = iflib_txq_can_drain;
3768 _task_fn_tx(void *context)
3770 iflib_txq_t txq = context;
3771 if_ctx_t ctx = txq->ift_ctx;
3772 if_t ifp = ctx->ifc_ifp;
3773 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3775 #ifdef IFLIB_DIAGNOSTICS
3776 txq->ift_cpu_exec_count[curcpu]++;
3778 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3781 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3782 netmap_tx_irq(ifp, txq->ift_id))
3786 if (ALTQ_IS_ENABLED(&ifp->if_snd))
3787 iflib_altq_if_start(ifp);
3789 if (txq->ift_db_pending)
3790 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3792 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3794 * When abdicating, we always need to check drainage, not just when we don't enqueue
3797 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3801 if (ctx->ifc_flags & IFC_LEGACY)
3802 IFDI_INTR_ENABLE(ctx);
3804 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3808 _task_fn_rx(void *context)
3810 iflib_rxq_t rxq = context;
3811 if_ctx_t ctx = rxq->ifr_ctx;
3819 #ifdef IFLIB_DIAGNOSTICS
3820 rxq->ifr_cpu_exec_count[curcpu]++;
3822 DBG_COUNTER_INC(task_fn_rxs);
3823 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3826 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3827 if (nmirq != NM_IRQ_PASS) {
3828 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3832 budget = ctx->ifc_sysctl_rx_budget;
3834 budget = 16; /* XXX */
3835 more = iflib_rxeof(rxq, budget);
3839 if ((more & IFLIB_RXEOF_MORE) == 0) {
3840 if (ctx->ifc_flags & IFC_LEGACY)
3841 IFDI_INTR_ENABLE(ctx);
3843 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3844 DBG_COUNTER_INC(rx_intr_enables);
3846 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3849 if (more & IFLIB_RXEOF_MORE)
3850 GROUPTASK_ENQUEUE(&rxq->ifr_task);
3851 else if (more & IFLIB_RXEOF_EMPTY)
3852 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3856 _task_fn_admin(void *context)
3858 if_ctx_t ctx = context;
3859 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3862 bool oactive, running, do_reset, do_watchdog, in_detach;
3863 uint32_t reset_on = hz / 2;
3866 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3867 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3868 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3869 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3870 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3871 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3874 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3880 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3882 callout_stop(&txq->ift_timer);
3883 CALLOUT_UNLOCK(txq);
3886 ctx->ifc_watchdog_events++;
3887 IFDI_WATCHDOG_RESET(ctx);
3889 IFDI_UPDATE_ADMIN_STATUS(ctx);
3890 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3893 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3894 iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3896 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3898 IFDI_LINK_INTR_ENABLE(ctx);
3900 iflib_if_init_locked(ctx);
3903 if (LINK_ACTIVE(ctx) == 0)
3905 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3906 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3911 _task_fn_iov(void *context)
3913 if_ctx_t ctx = context;
3915 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3916 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3920 IFDI_VFLR_HANDLE(ctx);
3925 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3928 if_int_delay_info_t info;
3931 info = (if_int_delay_info_t)arg1;
3932 ctx = info->iidi_ctx;
3933 info->iidi_req = req;
3934 info->iidi_oidp = oidp;
3936 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3941 /*********************************************************************
3945 **********************************************************************/
3948 iflib_if_init_locked(if_ctx_t ctx)
3951 iflib_init_locked(ctx);
3956 iflib_if_init(void *arg)
3961 iflib_if_init_locked(ctx);
3966 iflib_if_transmit(if_t ifp, struct mbuf *m)
3968 if_ctx_t ctx = if_getsoftc(ifp);
3972 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3974 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3975 DBG_COUNTER_INC(tx_frees);
3980 MPASS(m->m_nextpkt == NULL);
3981 /* ALTQ-enabled interfaces always use queue 0. */
3983 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3984 qidx = QIDX(ctx, m);
3986 * XXX calculate buf_ring based on flowid (divvy up bits?)
3988 txq = &ctx->ifc_txqs[qidx];
3990 #ifdef DRIVER_BACKPRESSURE
3991 if (txq->ift_closed) {
3993 next = m->m_nextpkt;
3994 m->m_nextpkt = NULL;
3996 DBG_COUNTER_INC(tx_frees);
4008 next = next->m_nextpkt;
4009 } while (next != NULL);
4011 if (count > nitems(marr))
4012 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4013 /* XXX check nextpkt */
4015 /* XXX simplify for now */
4016 DBG_COUNTER_INC(tx_frees);
4019 for (next = m, i = 0; next != NULL; i++) {
4021 next = next->m_nextpkt;
4022 mp[i]->m_nextpkt = NULL;
4025 DBG_COUNTER_INC(tx_seen);
4026 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4029 GROUPTASK_ENQUEUE(&txq->ift_task);
4032 GROUPTASK_ENQUEUE(&txq->ift_task);
4033 /* support forthcoming later */
4034 #ifdef DRIVER_BACKPRESSURE
4035 txq->ift_closed = TRUE;
4037 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4039 DBG_COUNTER_INC(tx_frees);
4047 * The overall approach to integrating iflib with ALTQ is to continue to use
4048 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4049 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4050 * is redundant/unnecessary, but doing so minimizes the amount of
4051 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4052 * redundantly queueing to an intermediate mp_ring is swamped by the
4053 * performance limitations inherent in using ALTQ.
4055 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4056 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4057 * given interface. If ALTQ is enabled for an interface, then all
4058 * transmitted packets for that interface will be submitted to the ALTQ
4059 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4060 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4061 * update stats that the iflib machinery handles, and which is sensitve to
4062 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4063 * will be installed as the start routine for use by ALTQ facilities that
4064 * need to trigger queue drains on a scheduled basis.
4068 iflib_altq_if_start(if_t ifp)
4070 struct ifaltq *ifq = &ifp->if_snd;
4074 IFQ_DEQUEUE_NOLOCK(ifq, m);
4076 iflib_if_transmit(ifp, m);
4077 IFQ_DEQUEUE_NOLOCK(ifq, m);
4083 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4087 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4088 IFQ_ENQUEUE(&ifp->if_snd, m, err);
4090 iflib_altq_if_start(ifp);
4092 err = iflib_if_transmit(ifp, m);
4099 iflib_if_qflush(if_t ifp)
4101 if_ctx_t ctx = if_getsoftc(ifp);
4102 iflib_txq_t txq = ctx->ifc_txqs;
4106 ctx->ifc_flags |= IFC_QFLUSH;
4108 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4109 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4110 iflib_txq_check_drain(txq, 0);
4112 ctx->ifc_flags &= ~IFC_QFLUSH;
4116 * When ALTQ is enabled, this will also take care of purging the
4123 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4124 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4125 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4126 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4129 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4131 if_ctx_t ctx = if_getsoftc(ifp);
4132 struct ifreq *ifr = (struct ifreq *)data;
4133 #if defined(INET) || defined(INET6)
4134 struct ifaddr *ifa = (struct ifaddr *)data;
4136 bool avoid_reset = false;
4137 int err = 0, reinit = 0, bits;
4142 if (ifa->ifa_addr->sa_family == AF_INET)
4146 if (ifa->ifa_addr->sa_family == AF_INET6)
4150 ** Calling init results in link renegotiation,
4151 ** so we avoid doing it when possible.
4154 if_setflagbits(ifp, IFF_UP,0);
4155 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4158 if (!(if_getflags(ifp) & IFF_NOARP))
4159 arp_ifinit(ifp, ifa);
4162 err = ether_ioctl(ifp, command, data);
4166 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4170 bits = if_getdrvflags(ifp);
4171 /* stop the driver and free any clusters before proceeding */
4174 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4176 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4177 ctx->ifc_flags |= IFC_MULTISEG;
4179 ctx->ifc_flags &= ~IFC_MULTISEG;
4181 err = if_setmtu(ifp, ifr->ifr_mtu);
4183 iflib_init_locked(ctx);
4185 if_setdrvflags(ifp, bits);
4191 if (if_getflags(ifp) & IFF_UP) {
4192 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4193 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4194 (IFF_PROMISC | IFF_ALLMULTI)) {
4196 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4201 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4204 ctx->ifc_if_flags = if_getflags(ifp);
4209 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4211 IFDI_INTR_DISABLE(ctx);
4212 IFDI_MULTI_SET(ctx);
4213 IFDI_INTR_ENABLE(ctx);
4219 IFDI_MEDIA_SET(ctx);
4224 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4228 struct ifi2creq i2c;
4230 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4233 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4237 if (i2c.len > sizeof(i2c.data)) {
4242 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4243 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4249 int mask, setmask, oldmask;
4251 oldmask = if_getcapenable(ifp);
4252 mask = ifr->ifr_reqcap ^ oldmask;
4253 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4256 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4258 setmask |= (mask & IFCAP_FLAGS);
4259 setmask |= (mask & IFCAP_WOL);
4262 * If any RX csum has changed, change all the ones that
4263 * are supported by the driver.
4265 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4266 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4267 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4271 * want to ensure that traffic has stopped before we change any of the flags
4275 bits = if_getdrvflags(ifp);
4276 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4279 if_togglecapenable(ifp, setmask);
4281 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4282 iflib_init_locked(ctx);
4284 if_setdrvflags(ifp, bits);
4291 case SIOCGPRIVATE_0:
4295 err = IFDI_PRIV_IOCTL(ctx, command, data);
4299 err = ether_ioctl(ifp, command, data);
4308 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4310 if_ctx_t ctx = if_getsoftc(ifp);
4312 return (IFDI_GET_COUNTER(ctx, cnt));
4315 /*********************************************************************
4317 * OTHER FUNCTIONS EXPORTED TO THE STACK
4319 **********************************************************************/
4322 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4324 if_ctx_t ctx = if_getsoftc(ifp);
4326 if ((void *)ctx != arg)
4329 if ((vtag == 0) || (vtag > 4095))
4332 if (iflib_in_detach(ctx))
4336 /* Driver may need all untagged packets to be flushed */
4337 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4339 IFDI_VLAN_REGISTER(ctx, vtag);
4340 /* Re-init to load the changes, if required */
4341 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4342 iflib_init_locked(ctx);
4347 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4349 if_ctx_t ctx = if_getsoftc(ifp);
4351 if ((void *)ctx != arg)
4354 if ((vtag == 0) || (vtag > 4095))
4358 /* Driver may need all tagged packets to be flushed */
4359 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4361 IFDI_VLAN_UNREGISTER(ctx, vtag);
4362 /* Re-init to load the changes, if required */
4363 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4364 iflib_init_locked(ctx);
4369 iflib_led_func(void *arg, int onoff)
4374 IFDI_LED_FUNC(ctx, onoff);
4378 /*********************************************************************
4380 * BUS FUNCTION DEFINITIONS
4382 **********************************************************************/
4385 iflib_device_probe(device_t dev)
4387 const pci_vendor_info_t *ent;
4388 if_shared_ctx_t sctx;
4389 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4390 uint16_t pci_vendor_id;
4392 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4395 pci_vendor_id = pci_get_vendor(dev);
4396 pci_device_id = pci_get_device(dev);
4397 pci_subvendor_id = pci_get_subvendor(dev);
4398 pci_subdevice_id = pci_get_subdevice(dev);
4399 pci_rev_id = pci_get_revid(dev);
4400 if (sctx->isc_parse_devinfo != NULL)
4401 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4403 ent = sctx->isc_vendor_info;
4404 while (ent->pvi_vendor_id != 0) {
4405 if (pci_vendor_id != ent->pvi_vendor_id) {
4409 if ((pci_device_id == ent->pvi_device_id) &&
4410 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4411 (ent->pvi_subvendor_id == 0)) &&
4412 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4413 (ent->pvi_subdevice_id == 0)) &&
4414 ((pci_rev_id == ent->pvi_rev_id) ||
4415 (ent->pvi_rev_id == 0))) {
4417 device_set_desc_copy(dev, ent->pvi_name);
4418 /* this needs to be changed to zero if the bus probing code
4419 * ever stops re-probing on best match because the sctx
4420 * may have its values over written by register calls
4421 * in subsequent probes
4423 return (BUS_PROBE_DEFAULT);
4431 iflib_device_probe_vendor(device_t dev)
4435 probe = iflib_device_probe(dev);
4436 if (probe == BUS_PROBE_DEFAULT)
4437 return (BUS_PROBE_VENDOR);
4443 iflib_reset_qvalues(if_ctx_t ctx)
4445 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4446 if_shared_ctx_t sctx = ctx->ifc_sctx;
4447 device_t dev = ctx->ifc_dev;
4450 if (ctx->ifc_sysctl_ntxqs != 0)
4451 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4452 if (ctx->ifc_sysctl_nrxqs != 0)
4453 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4455 for (i = 0; i < sctx->isc_ntxqs; i++) {
4456 if (ctx->ifc_sysctl_ntxds[i] != 0)
4457 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4459 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4462 for (i = 0; i < sctx->isc_nrxqs; i++) {
4463 if (ctx->ifc_sysctl_nrxds[i] != 0)
4464 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4466 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4469 for (i = 0; i < sctx->isc_nrxqs; i++) {
4470 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4471 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4472 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4473 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4475 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4476 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4477 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4478 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4480 if (!powerof2(scctx->isc_nrxd[i])) {
4481 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4482 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4483 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4487 for (i = 0; i < sctx->isc_ntxqs; i++) {
4488 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4489 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4490 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4491 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4493 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4494 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4495 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4496 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4498 if (!powerof2(scctx->isc_ntxd[i])) {
4499 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4500 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4501 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4507 iflib_add_pfil(if_ctx_t ctx)
4509 struct pfil_head *pfil;
4510 struct pfil_head_args pa;
4514 pa.pa_version = PFIL_VERSION;
4515 pa.pa_flags = PFIL_IN;
4516 pa.pa_type = PFIL_TYPE_ETHERNET;
4517 pa.pa_headname = ctx->ifc_ifp->if_xname;
4518 pfil = pfil_head_register(&pa);
4520 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4526 iflib_rem_pfil(if_ctx_t ctx)
4528 struct pfil_head *pfil;
4532 rxq = ctx->ifc_rxqs;
4534 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4537 pfil_head_unregister(pfil);
4541 get_ctx_core_offset(if_ctx_t ctx)
4543 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4544 struct cpu_offset *op;
4546 uint16_t ret = ctx->ifc_sysctl_core_offset;
4548 if (ret != CORE_OFFSET_UNSPECIFIED)
4551 if (ctx->ifc_sysctl_separate_txrx)
4552 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4554 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4556 mtx_lock(&cpu_offset_mtx);
4557 SLIST_FOREACH(op, &cpu_offsets, entries) {
4558 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4561 MPASS(op->refcount < UINT_MAX);
4566 if (ret == CORE_OFFSET_UNSPECIFIED) {
4568 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4571 device_printf(ctx->ifc_dev,
4572 "allocation for cpu offset failed.\n");
4576 CPU_COPY(&ctx->ifc_cpus, &op->set);
4577 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4580 mtx_unlock(&cpu_offset_mtx);
4586 unref_ctx_core_offset(if_ctx_t ctx)
4588 struct cpu_offset *op, *top;
4590 mtx_lock(&cpu_offset_mtx);
4591 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4592 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4593 MPASS(op->refcount > 0);
4595 if (op->refcount == 0) {
4596 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4602 mtx_unlock(&cpu_offset_mtx);
4606 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4610 if_softc_ctx_t scctx;
4611 kobjop_desc_t kobj_desc;
4612 kobj_method_t *kobj_method;
4614 int num_txd, num_rxd;
4616 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4619 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4620 device_set_softc(dev, ctx);
4621 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4624 ctx->ifc_sctx = sctx;
4626 ctx->ifc_softc = sc;
4628 if ((err = iflib_register(ctx)) != 0) {
4629 device_printf(dev, "iflib_register failed %d\n", err);
4632 iflib_add_device_sysctl_pre(ctx);
4634 scctx = &ctx->ifc_softc_ctx;
4637 iflib_reset_qvalues(ctx);
4639 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4640 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4643 _iflib_pre_assert(scctx);
4644 ctx->ifc_txrx = *scctx->isc_txrx;
4646 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4647 ctx->ifc_mediap = scctx->isc_media;
4650 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4651 MPASS(scctx->isc_tx_csum_flags);
4654 if_setcapabilities(ifp,
4655 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4656 if_setcapenable(ifp,
4657 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4659 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4660 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4661 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4662 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4664 num_txd = iflib_num_tx_descs(ctx);
4665 num_rxd = iflib_num_rx_descs(ctx);
4667 /* XXX change for per-queue sizes */
4668 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4671 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4672 scctx->isc_tx_nsegments = max(1, num_txd /
4673 MAX_SINGLE_PACKET_FRACTION);
4674 if (scctx->isc_tx_tso_segments_max > num_txd /
4675 MAX_SINGLE_PACKET_FRACTION)
4676 scctx->isc_tx_tso_segments_max = max(1,
4677 num_txd / MAX_SINGLE_PACKET_FRACTION);
4679 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4680 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4682 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4685 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4688 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4689 * into account. In the worst case, each of these calls will
4690 * add another mbuf and, thus, the requirement for another DMA
4691 * segment. So for best performance, it doesn't make sense to
4692 * advertize a maximum of TSO segments that typically will
4693 * require defragmentation in iflib_encap().
4695 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4696 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4698 if (scctx->isc_rss_table_size == 0)
4699 scctx->isc_rss_table_size = 64;
4700 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4702 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4703 /* XXX format name */
4704 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4705 NULL, NULL, "admin");
4707 /* Set up cpu set. If it fails, use the set of all CPUs. */
4708 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4709 device_printf(dev, "Unable to fetch CPU list\n");
4710 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4712 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4715 ** Now set up MSI or MSI-X, should return us the number of supported
4716 ** vectors (will be 1 for a legacy interrupt and MSI).
4718 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4719 msix = scctx->isc_vectors;
4720 } else if (scctx->isc_msix_bar != 0)
4722 * The simple fact that isc_msix_bar is not 0 does not mean we
4723 * we have a good value there that is known to work.
4725 msix = iflib_msix_init(ctx);
4727 scctx->isc_vectors = 1;
4728 scctx->isc_ntxqsets = 1;
4729 scctx->isc_nrxqsets = 1;
4730 scctx->isc_intr = IFLIB_INTR_LEGACY;
4733 /* Get memory for the station queues */
4734 if ((err = iflib_queues_alloc(ctx))) {
4735 device_printf(dev, "Unable to allocate queue memory\n");
4736 goto fail_intr_free;
4739 if ((err = iflib_qset_structures_setup(ctx)))
4743 * Now that we know how many queues there are, get the core offset.
4745 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4749 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4750 * aren't the default NULL implementation.
4752 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4753 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4755 if (kobj_method == &kobj_desc->deflt) {
4757 "MSI-X requires ifdi_rx_queue_intr_enable method");
4761 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4762 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4764 if (kobj_method == &kobj_desc->deflt) {
4766 "MSI-X requires ifdi_tx_queue_intr_enable method");
4772 * Assign the MSI-X vectors.
4773 * Note that the default NULL ifdi_msix_intr_assign method will
4776 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4778 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4782 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4784 if (scctx->isc_intr == IFLIB_INTR_MSI) {
4788 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4789 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4794 "Cannot use iflib with only 1 MSI-X interrupt!\n");
4796 goto fail_intr_free;
4799 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4801 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4802 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4807 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4808 * This must appear after the call to ether_ifattach() because
4809 * ether_ifattach() sets if_hdrlen to the default value.
4811 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4812 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4814 if ((err = iflib_netmap_attach(ctx))) {
4815 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4820 DEBUGNET_SET(ctx->ifc_ifp, iflib);
4822 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4823 iflib_add_device_sysctl_post(ctx);
4824 iflib_add_pfil(ctx);
4825 ctx->ifc_flags |= IFC_INIT_DONE;
4831 ether_ifdetach(ctx->ifc_ifp);
4833 iflib_free_intr_mem(ctx);
4835 iflib_tx_structures_free(ctx);
4836 iflib_rx_structures_free(ctx);
4837 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4841 iflib_deregister(ctx);
4843 device_set_softc(ctx->ifc_dev, NULL);
4844 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4845 free(ctx->ifc_softc, M_IFLIB);
4851 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4852 struct iflib_cloneattach_ctx *clctx)
4854 int num_txd, num_rxd;
4858 if_softc_ctx_t scctx;
4862 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4863 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4864 ctx->ifc_flags |= IFC_SC_ALLOCATED;
4865 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4866 ctx->ifc_flags |= IFC_PSEUDO;
4868 ctx->ifc_sctx = sctx;
4869 ctx->ifc_softc = sc;
4872 if ((err = iflib_register(ctx)) != 0) {
4873 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4876 iflib_add_device_sysctl_pre(ctx);
4878 scctx = &ctx->ifc_softc_ctx;
4881 iflib_reset_qvalues(ctx);
4883 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4884 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4887 if (sctx->isc_flags & IFLIB_GEN_MAC)
4888 ether_gen_addr(ifp, &ctx->ifc_mac);
4889 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4890 clctx->cc_params)) != 0) {
4891 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4895 if (scctx->isc_capabilities & IFCAP_TXCSUM)
4896 MPASS(scctx->isc_tx_csum_flags);
4899 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4900 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4902 ifp->if_flags |= IFF_NOGROUP;
4903 if (sctx->isc_flags & IFLIB_PSEUDO) {
4904 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4905 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4906 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4907 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4909 if_attach(ctx->ifc_ifp);
4910 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4913 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4914 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4920 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4921 * This must appear after the call to ether_ifattach() because
4922 * ether_ifattach() sets if_hdrlen to the default value.
4924 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4925 if_setifheaderlen(ifp,
4926 sizeof(struct ether_vlan_header));
4928 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4929 iflib_add_device_sysctl_post(ctx);
4930 ctx->ifc_flags |= IFC_INIT_DONE;
4934 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4935 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4936 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4938 _iflib_pre_assert(scctx);
4939 ctx->ifc_txrx = *scctx->isc_txrx;
4941 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4942 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4943 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4944 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4946 num_txd = iflib_num_tx_descs(ctx);
4947 num_rxd = iflib_num_rx_descs(ctx);
4949 /* XXX change for per-queue sizes */
4950 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4953 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4954 scctx->isc_tx_nsegments = max(1, num_txd /
4955 MAX_SINGLE_PACKET_FRACTION);
4956 if (scctx->isc_tx_tso_segments_max > num_txd /
4957 MAX_SINGLE_PACKET_FRACTION)
4958 scctx->isc_tx_tso_segments_max = max(1,
4959 num_txd / MAX_SINGLE_PACKET_FRACTION);
4961 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4962 if (if_getcapabilities(ifp) & IFCAP_TSO) {
4964 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4967 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4970 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4971 * into account. In the worst case, each of these calls will
4972 * add another mbuf and, thus, the requirement for another DMA
4973 * segment. So for best performance, it doesn't make sense to
4974 * advertize a maximum of TSO segments that typically will
4975 * require defragmentation in iflib_encap().
4977 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4978 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4980 if (scctx->isc_rss_table_size == 0)
4981 scctx->isc_rss_table_size = 64;
4982 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4984 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4985 /* XXX format name */
4986 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4987 NULL, NULL, "admin");
4989 /* XXX --- can support > 1 -- but keep it simple for now */
4990 scctx->isc_intr = IFLIB_INTR_LEGACY;
4992 /* Get memory for the station queues */
4993 if ((err = iflib_queues_alloc(ctx))) {
4994 device_printf(dev, "Unable to allocate queue memory\n");
4995 goto fail_iflib_detach;
4998 if ((err = iflib_qset_structures_setup(ctx))) {
4999 device_printf(dev, "qset structure setup failed %d\n", err);
5004 * XXX What if anything do we want to do about interrupts?
5006 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5007 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5008 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5013 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5014 * This must appear after the call to ether_ifattach() because
5015 * ether_ifattach() sets if_hdrlen to the default value.
5017 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5018 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5020 /* XXX handle more than one queue */
5021 for (i = 0; i < scctx->isc_nrxqsets; i++)
5022 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5026 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5027 iflib_add_device_sysctl_post(ctx);
5028 ctx->ifc_flags |= IFC_INIT_DONE;
5033 ether_ifdetach(ctx->ifc_ifp);
5035 iflib_tx_structures_free(ctx);
5036 iflib_rx_structures_free(ctx);
5041 iflib_deregister(ctx);
5043 free(ctx->ifc_softc, M_IFLIB);
5049 iflib_pseudo_deregister(if_ctx_t ctx)
5051 if_t ifp = ctx->ifc_ifp;
5052 if_shared_ctx_t sctx = ctx->ifc_sctx;
5056 struct taskqgroup *tqg;
5059 /* Unregister VLAN event handlers early */
5060 iflib_unregister_vlan_handlers(ctx);
5062 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5063 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5067 ether_ifdetach(ifp);
5069 /* XXX drain any dependent tasks */
5070 tqg = qgroup_if_io_tqg;
5071 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5072 callout_drain(&txq->ift_timer);
5073 if (txq->ift_task.gt_uniq != NULL)
5074 taskqgroup_detach(tqg, &txq->ift_task);
5076 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5077 callout_drain(&rxq->ifr_watchdog);
5078 if (rxq->ifr_task.gt_uniq != NULL)
5079 taskqgroup_detach(tqg, &rxq->ifr_task);
5081 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5082 free(fl->ifl_rx_bitmap, M_IFLIB);
5084 tqg = qgroup_if_config_tqg;
5085 if (ctx->ifc_admin_task.gt_uniq != NULL)
5086 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5087 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5088 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5090 iflib_tx_structures_free(ctx);
5091 iflib_rx_structures_free(ctx);
5093 iflib_deregister(ctx);
5095 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5096 free(ctx->ifc_softc, M_IFLIB);
5102 iflib_device_attach(device_t dev)
5105 if_shared_ctx_t sctx;
5107 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5110 pci_enable_busmaster(dev);
5112 return (iflib_device_register(dev, NULL, sctx, &ctx));
5116 iflib_device_deregister(if_ctx_t ctx)
5118 if_t ifp = ctx->ifc_ifp;
5121 device_t dev = ctx->ifc_dev;
5123 struct taskqgroup *tqg;
5126 /* Make sure VLANS are not using driver */
5127 if (if_vlantrunkinuse(ifp)) {
5128 device_printf(dev, "Vlan in use, detach first\n");
5132 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5133 device_printf(dev, "SR-IOV in use; detach first.\n");
5139 ctx->ifc_flags |= IFC_IN_DETACH;
5142 /* Unregister VLAN handlers before calling iflib_stop() */
5143 iflib_unregister_vlan_handlers(ctx);
5145 iflib_netmap_detach(ifp);
5146 ether_ifdetach(ifp);
5152 iflib_rem_pfil(ctx);
5153 if (ctx->ifc_led_dev != NULL)
5154 led_destroy(ctx->ifc_led_dev);
5155 /* XXX drain any dependent tasks */
5156 tqg = qgroup_if_io_tqg;
5157 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5158 callout_drain(&txq->ift_timer);
5159 if (txq->ift_task.gt_uniq != NULL)
5160 taskqgroup_detach(tqg, &txq->ift_task);
5162 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5163 if (rxq->ifr_task.gt_uniq != NULL)
5164 taskqgroup_detach(tqg, &rxq->ifr_task);
5166 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5167 free(fl->ifl_rx_bitmap, M_IFLIB);
5169 tqg = qgroup_if_config_tqg;
5170 if (ctx->ifc_admin_task.gt_uniq != NULL)
5171 taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5172 if (ctx->ifc_vflr_task.gt_uniq != NULL)
5173 taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5178 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5179 iflib_free_intr_mem(ctx);
5181 bus_generic_detach(dev);
5183 iflib_tx_structures_free(ctx);
5184 iflib_rx_structures_free(ctx);
5186 iflib_deregister(ctx);
5188 device_set_softc(ctx->ifc_dev, NULL);
5189 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5190 free(ctx->ifc_softc, M_IFLIB);
5191 unref_ctx_core_offset(ctx);
5197 iflib_free_intr_mem(if_ctx_t ctx)
5200 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5201 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5203 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5204 pci_release_msi(ctx->ifc_dev);
5206 if (ctx->ifc_msix_mem != NULL) {
5207 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5208 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5209 ctx->ifc_msix_mem = NULL;
5214 iflib_device_detach(device_t dev)
5216 if_ctx_t ctx = device_get_softc(dev);
5218 return (iflib_device_deregister(ctx));
5222 iflib_device_suspend(device_t dev)
5224 if_ctx_t ctx = device_get_softc(dev);
5230 return bus_generic_suspend(dev);
5233 iflib_device_shutdown(device_t dev)
5235 if_ctx_t ctx = device_get_softc(dev);
5241 return bus_generic_suspend(dev);
5246 iflib_device_resume(device_t dev)
5248 if_ctx_t ctx = device_get_softc(dev);
5249 iflib_txq_t txq = ctx->ifc_txqs;
5253 iflib_if_init_locked(ctx);
5255 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5256 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5258 return (bus_generic_resume(dev));
5262 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5265 if_ctx_t ctx = device_get_softc(dev);
5268 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5275 iflib_device_iov_uninit(device_t dev)
5277 if_ctx_t ctx = device_get_softc(dev);
5280 IFDI_IOV_UNINIT(ctx);
5285 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5288 if_ctx_t ctx = device_get_softc(dev);
5291 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5297 /*********************************************************************
5299 * MODULE FUNCTION DEFINITIONS
5301 **********************************************************************/
5304 * - Start a fast taskqueue thread for each core
5305 * - Start a taskqueue for control operations
5308 iflib_module_init(void)
5314 iflib_module_event_handler(module_t mod, int what, void *arg)
5320 if ((err = iflib_module_init()) != 0)
5326 return (EOPNOTSUPP);
5332 /*********************************************************************
5334 * PUBLIC FUNCTION DEFINITIONS
5335 * ordered as in iflib.h
5337 **********************************************************************/
5341 _iflib_assert(if_shared_ctx_t sctx)
5345 MPASS(sctx->isc_tx_maxsize);
5346 MPASS(sctx->isc_tx_maxsegsize);
5348 MPASS(sctx->isc_rx_maxsize);
5349 MPASS(sctx->isc_rx_nsegments);
5350 MPASS(sctx->isc_rx_maxsegsize);
5352 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5353 for (i = 0; i < sctx->isc_nrxqs; i++) {
5354 MPASS(sctx->isc_nrxd_min[i]);
5355 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5356 MPASS(sctx->isc_nrxd_max[i]);
5357 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5358 MPASS(sctx->isc_nrxd_default[i]);
5359 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5362 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5363 for (i = 0; i < sctx->isc_ntxqs; i++) {
5364 MPASS(sctx->isc_ntxd_min[i]);
5365 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5366 MPASS(sctx->isc_ntxd_max[i]);
5367 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5368 MPASS(sctx->isc_ntxd_default[i]);
5369 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5374 _iflib_pre_assert(if_softc_ctx_t scctx)
5377 MPASS(scctx->isc_txrx->ift_txd_encap);
5378 MPASS(scctx->isc_txrx->ift_txd_flush);
5379 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5380 MPASS(scctx->isc_txrx->ift_rxd_available);
5381 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5382 MPASS(scctx->isc_txrx->ift_rxd_refill);
5383 MPASS(scctx->isc_txrx->ift_rxd_flush);
5387 iflib_register(if_ctx_t ctx)
5389 if_shared_ctx_t sctx = ctx->ifc_sctx;
5390 driver_t *driver = sctx->isc_driver;
5391 device_t dev = ctx->ifc_dev;
5396 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5397 _iflib_assert(sctx);
5400 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5401 if (sctx->isc_flags & IFLIB_PSEUDO) {
5402 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5408 ifp = ctx->ifc_ifp = if_alloc(type);
5410 device_printf(dev, "can not allocate ifnet structure\n");
5415 * Initialize our context's device specific methods
5417 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5418 kobj_class_compile((kobj_class_t) driver);
5420 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5421 if_setsoftc(ifp, ctx);
5422 if_setdev(ifp, dev);
5423 if_setinitfn(ifp, iflib_if_init);
5424 if_setioctlfn(ifp, iflib_if_ioctl);
5426 if_setstartfn(ifp, iflib_altq_if_start);
5427 if_settransmitfn(ifp, iflib_altq_if_transmit);
5428 if_setsendqready(ifp);
5430 if_settransmitfn(ifp, iflib_if_transmit);
5432 if_setqflushfn(ifp, iflib_if_qflush);
5433 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5435 if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5436 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5437 iflags |= IFF_POINTOPOINT;
5439 iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5440 if_setflags(ifp, iflags);
5441 ctx->ifc_vlan_attach_event =
5442 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5443 EVENTHANDLER_PRI_FIRST);
5444 ctx->ifc_vlan_detach_event =
5445 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5446 EVENTHANDLER_PRI_FIRST);
5448 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5449 ctx->ifc_mediap = &ctx->ifc_media;
5450 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5451 iflib_media_change, iflib_media_status);
5457 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5459 /* Unregister VLAN events */
5460 if (ctx->ifc_vlan_attach_event != NULL) {
5461 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5462 ctx->ifc_vlan_attach_event = NULL;
5464 if (ctx->ifc_vlan_detach_event != NULL) {
5465 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5466 ctx->ifc_vlan_detach_event = NULL;
5472 iflib_deregister(if_ctx_t ctx)
5474 if_t ifp = ctx->ifc_ifp;
5476 /* Remove all media */
5477 ifmedia_removeall(&ctx->ifc_media);
5479 /* Ensure that VLAN event handlers are unregistered */
5480 iflib_unregister_vlan_handlers(ctx);
5482 /* Release kobject reference */
5483 kobj_delete((kobj_t) ctx, NULL);
5485 /* Free the ifnet structure */
5488 STATE_LOCK_DESTROY(ctx);
5490 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5491 CTX_LOCK_DESTROY(ctx);
5495 iflib_queues_alloc(if_ctx_t ctx)
5497 if_shared_ctx_t sctx = ctx->ifc_sctx;
5498 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5499 device_t dev = ctx->ifc_dev;
5500 int nrxqsets = scctx->isc_nrxqsets;
5501 int ntxqsets = scctx->isc_ntxqsets;
5504 iflib_fl_t fl = NULL;
5505 int i, j, cpu, err, txconf, rxconf;
5506 iflib_dma_info_t ifdip;
5507 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5508 uint32_t *txqsizes = scctx->isc_txqsizes;
5509 uint8_t nrxqs = sctx->isc_nrxqs;
5510 uint8_t ntxqs = sctx->isc_ntxqs;
5511 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5515 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5516 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5518 /* Allocate the TX ring struct memory */
5519 if (!(ctx->ifc_txqs =
5520 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5521 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5522 device_printf(dev, "Unable to allocate TX ring memory\n");
5527 /* Now allocate the RX */
5528 if (!(ctx->ifc_rxqs =
5529 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5530 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5531 device_printf(dev, "Unable to allocate RX ring memory\n");
5536 txq = ctx->ifc_txqs;
5537 rxq = ctx->ifc_rxqs;
5540 * XXX handle allocation failure
5542 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5543 /* Set up some basics */
5545 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5546 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5548 "Unable to allocate TX DMA info memory\n");
5552 txq->ift_ifdi = ifdip;
5553 for (j = 0; j < ntxqs; j++, ifdip++) {
5554 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5556 "Unable to allocate TX descriptors\n");
5560 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5561 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5565 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5566 txq->ift_br_offset = 1;
5568 txq->ift_br_offset = 0;
5571 txq->ift_timer.c_cpu = cpu;
5573 if (iflib_txsd_alloc(txq)) {
5574 device_printf(dev, "Critical Failure setting up TX buffers\n");
5579 /* Initialize the TX lock */
5580 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5581 device_get_nameunit(dev), txq->ift_id);
5582 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5583 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5585 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5586 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5588 /* XXX free any allocated rings */
5589 device_printf(dev, "Unable to allocate buf_ring\n");
5594 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5595 /* Set up some basics */
5596 callout_init(&rxq->ifr_watchdog, 1);
5598 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5599 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5601 "Unable to allocate RX DMA info memory\n");
5606 rxq->ifr_ifdi = ifdip;
5607 /* XXX this needs to be changed if #rx queues != #tx queues */
5608 rxq->ifr_ntxqirq = 1;
5609 rxq->ifr_txqid[0] = i;
5610 for (j = 0; j < nrxqs; j++, ifdip++) {
5611 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5613 "Unable to allocate RX descriptors\n");
5617 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5621 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5622 rxq->ifr_fl_offset = 1;
5624 rxq->ifr_fl_offset = 0;
5626 rxq->ifr_nfl = nfree_lists;
5628 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5629 device_printf(dev, "Unable to allocate free list memory\n");
5634 for (j = 0; j < nfree_lists; j++) {
5635 fl[j].ifl_rxq = rxq;
5637 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5638 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5640 /* Allocate receive buffers for the ring */
5641 if (iflib_rxsd_alloc(rxq)) {
5643 "Critical Failure setting up receive buffers\n");
5648 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5649 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5654 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5655 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5656 for (i = 0; i < ntxqsets; i++) {
5657 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5659 for (j = 0; j < ntxqs; j++, di++) {
5660 vaddrs[i*ntxqs + j] = di->idi_vaddr;
5661 paddrs[i*ntxqs + j] = di->idi_paddr;
5664 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5665 device_printf(ctx->ifc_dev,
5666 "Unable to allocate device TX queue\n");
5667 iflib_tx_structures_free(ctx);
5668 free(vaddrs, M_IFLIB);
5669 free(paddrs, M_IFLIB);
5672 free(vaddrs, M_IFLIB);
5673 free(paddrs, M_IFLIB);
5676 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5677 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5678 for (i = 0; i < nrxqsets; i++) {
5679 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5681 for (j = 0; j < nrxqs; j++, di++) {
5682 vaddrs[i*nrxqs + j] = di->idi_vaddr;
5683 paddrs[i*nrxqs + j] = di->idi_paddr;
5686 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5687 device_printf(ctx->ifc_dev,
5688 "Unable to allocate device RX queue\n");
5689 iflib_tx_structures_free(ctx);
5690 free(vaddrs, M_IFLIB);
5691 free(paddrs, M_IFLIB);
5694 free(vaddrs, M_IFLIB);
5695 free(paddrs, M_IFLIB);
5699 /* XXX handle allocation failure changes */
5703 if (ctx->ifc_rxqs != NULL)
5704 free(ctx->ifc_rxqs, M_IFLIB);
5705 ctx->ifc_rxqs = NULL;
5706 if (ctx->ifc_txqs != NULL)
5707 free(ctx->ifc_txqs, M_IFLIB);
5708 ctx->ifc_txqs = NULL;
5714 iflib_tx_structures_setup(if_ctx_t ctx)
5716 iflib_txq_t txq = ctx->ifc_txqs;
5719 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5720 iflib_txq_setup(txq);
5726 iflib_tx_structures_free(if_ctx_t ctx)
5728 iflib_txq_t txq = ctx->ifc_txqs;
5729 if_shared_ctx_t sctx = ctx->ifc_sctx;
5732 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5733 for (j = 0; j < sctx->isc_ntxqs; j++)
5734 iflib_dma_free(&txq->ift_ifdi[j]);
5735 iflib_txq_destroy(txq);
5737 free(ctx->ifc_txqs, M_IFLIB);
5738 ctx->ifc_txqs = NULL;
5739 IFDI_QUEUES_FREE(ctx);
5742 /*********************************************************************
5744 * Initialize all receive rings.
5746 **********************************************************************/
5748 iflib_rx_structures_setup(if_ctx_t ctx)
5750 iflib_rxq_t rxq = ctx->ifc_rxqs;
5752 #if defined(INET6) || defined(INET)
5756 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5757 #if defined(INET6) || defined(INET)
5758 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5759 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5760 TCP_LRO_ENTRIES, min(1024,
5761 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5763 device_printf(ctx->ifc_dev,
5764 "LRO Initialization failed!\n");
5769 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5772 #if defined(INET6) || defined(INET)
5775 * Free LRO resources allocated so far, we will only handle
5776 * the rings that completed, the failing case will have
5777 * cleaned up for itself. 'q' failed, so its the terminus.
5779 rxq = ctx->ifc_rxqs;
5780 for (i = 0; i < q; ++i, rxq++) {
5781 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5782 tcp_lro_free(&rxq->ifr_lc);
5788 /*********************************************************************
5790 * Free all receive rings.
5792 **********************************************************************/
5794 iflib_rx_structures_free(if_ctx_t ctx)
5796 iflib_rxq_t rxq = ctx->ifc_rxqs;
5797 if_shared_ctx_t sctx = ctx->ifc_sctx;
5800 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5801 for (j = 0; j < sctx->isc_nrxqs; j++)
5802 iflib_dma_free(&rxq->ifr_ifdi[j]);
5803 iflib_rx_sds_free(rxq);
5804 #if defined(INET6) || defined(INET)
5805 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5806 tcp_lro_free(&rxq->ifr_lc);
5809 free(ctx->ifc_rxqs, M_IFLIB);
5810 ctx->ifc_rxqs = NULL;
5814 iflib_qset_structures_setup(if_ctx_t ctx)
5819 * It is expected that the caller takes care of freeing queues if this
5822 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5823 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5827 if ((err = iflib_rx_structures_setup(ctx)) != 0)
5828 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5834 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5835 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5838 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5843 find_nth(if_ctx_t ctx, int qid)
5846 int i, cpuid, eqid, count;
5848 CPU_COPY(&ctx->ifc_cpus, &cpus);
5849 count = CPU_COUNT(&cpus);
5851 /* clear up to the qid'th bit */
5852 for (i = 0; i < eqid; i++) {
5853 cpuid = CPU_FFS(&cpus);
5855 CPU_CLR(cpuid-1, &cpus);
5857 cpuid = CPU_FFS(&cpus);
5863 extern struct cpu_group *cpu_top; /* CPU topology */
5866 find_child_with_core(int cpu, struct cpu_group *grp)
5870 if (grp->cg_children == 0)
5873 MPASS(grp->cg_child);
5874 for (i = 0; i < grp->cg_children; i++) {
5875 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5883 * Find the nth "close" core to the specified core
5884 * "close" is defined as the deepest level that shares
5885 * at least an L2 cache. With threads, this will be
5886 * threads on the same core. If the shared cache is L3
5887 * or higher, simply returns the same core.
5890 find_close_core(int cpu, int core_offset)
5892 struct cpu_group *grp;
5901 while ((i = find_child_with_core(cpu, grp)) != -1) {
5902 /* If the child only has one cpu, don't descend */
5903 if (grp->cg_child[i].cg_count <= 1)
5905 grp = &grp->cg_child[i];
5908 /* If they don't share at least an L2 cache, use the same CPU */
5909 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5913 CPU_COPY(&grp->cg_mask, &cs);
5915 /* Add the selected CPU offset to core offset. */
5916 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5917 if (fcpu - 1 == cpu)
5919 CPU_CLR(fcpu - 1, &cs);
5925 CPU_COPY(&grp->cg_mask, &cs);
5926 for (i = core_offset % grp->cg_count; i > 0; i--) {
5927 MPASS(CPU_FFS(&cs));
5928 CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5930 MPASS(CPU_FFS(&cs));
5931 return CPU_FFS(&cs) - 1;
5935 find_close_core(int cpu, int core_offset __unused)
5942 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5946 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5947 /* XXX handle multiple RX threads per core and more than two core per L2 group */
5948 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5950 case IFLIB_INTR_RXTX:
5951 /* RX queues get the specified core */
5952 return qid / CPU_COUNT(&ctx->ifc_cpus);
5958 #define get_core_offset(ctx, type, qid) CPU_FIRST()
5959 #define find_close_core(cpuid, tid) CPU_FIRST()
5960 #define find_nth(ctx, gid) CPU_FIRST()
5963 /* Just to avoid copy/paste */
5965 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5966 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5970 int co, cpuid, err, tid;
5973 co = ctx->ifc_sysctl_core_offset;
5974 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5975 co += ctx->ifc_softc_ctx.isc_nrxqsets;
5976 cpuid = find_nth(ctx, qid + co);
5977 tid = get_core_offset(ctx, type, qid);
5979 device_printf(dev, "get_core_offset failed\n");
5980 return (EOPNOTSUPP);
5982 cpuid = find_close_core(cpuid, tid);
5983 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5986 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5990 if (cpuid > ctx->ifc_cpuid_highest)
5991 ctx->ifc_cpuid_highest = cpuid;
5997 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5998 iflib_intr_type_t type, driver_filter_t *filter,
5999 void *filter_arg, int qid, const char *name)
6002 struct grouptask *gtask;
6003 struct taskqgroup *tqg;
6004 iflib_filter_info_t info;
6007 driver_filter_t *intr_fast;
6010 info = &ctx->ifc_filter_info;
6014 /* XXX merge tx/rx for netmap? */
6016 q = &ctx->ifc_txqs[qid];
6017 info = &ctx->ifc_txqs[qid].ift_filter_info;
6018 gtask = &ctx->ifc_txqs[qid].ift_task;
6019 tqg = qgroup_if_io_tqg;
6021 intr_fast = iflib_fast_intr;
6022 GROUPTASK_INIT(gtask, 0, fn, q);
6023 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6026 q = &ctx->ifc_rxqs[qid];
6027 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6028 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6029 tqg = qgroup_if_io_tqg;
6031 intr_fast = iflib_fast_intr;
6032 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6034 case IFLIB_INTR_RXTX:
6035 q = &ctx->ifc_rxqs[qid];
6036 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6037 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6038 tqg = qgroup_if_io_tqg;
6040 intr_fast = iflib_fast_intr_rxtx;
6041 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6043 case IFLIB_INTR_ADMIN:
6046 info = &ctx->ifc_filter_info;
6047 gtask = &ctx->ifc_admin_task;
6048 tqg = qgroup_if_config_tqg;
6049 fn = _task_fn_admin;
6050 intr_fast = iflib_fast_intr_ctx;
6053 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6058 info->ifi_filter = filter;
6059 info->ifi_filter_arg = filter_arg;
6060 info->ifi_task = gtask;
6064 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6066 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6069 if (type == IFLIB_INTR_ADMIN)
6073 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6078 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6085 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6087 struct grouptask *gtask;
6088 struct taskqgroup *tqg;
6095 q = &ctx->ifc_txqs[qid];
6096 gtask = &ctx->ifc_txqs[qid].ift_task;
6097 tqg = qgroup_if_io_tqg;
6099 GROUPTASK_INIT(gtask, 0, fn, q);
6102 q = &ctx->ifc_rxqs[qid];
6103 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6104 tqg = qgroup_if_io_tqg;
6106 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6108 case IFLIB_INTR_IOV:
6110 gtask = &ctx->ifc_vflr_task;
6111 tqg = qgroup_if_config_tqg;
6113 GROUPTASK_INIT(gtask, 0, fn, q);
6116 panic("unknown net intr type");
6119 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6122 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6125 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6130 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6134 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6137 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6138 rman_get_rid(irq->ii_res), irq->ii_res);
6142 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6144 iflib_txq_t txq = ctx->ifc_txqs;
6145 iflib_rxq_t rxq = ctx->ifc_rxqs;
6146 if_irq_t irq = &ctx->ifc_legacy_irq;
6147 iflib_filter_info_t info;
6149 struct grouptask *gtask;
6150 struct resource *res;
6151 struct taskqgroup *tqg;
6156 q = &ctx->ifc_rxqs[0];
6157 info = &rxq[0].ifr_filter_info;
6158 gtask = &rxq[0].ifr_task;
6159 tqg = qgroup_if_io_tqg;
6161 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6163 ctx->ifc_flags |= IFC_LEGACY;
6164 info->ifi_filter = filter;
6165 info->ifi_filter_arg = filter_arg;
6166 info->ifi_task = gtask;
6167 info->ifi_ctx = rx_only ? ctx : q;
6170 /* We allocate a single interrupt resource */
6171 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6172 iflib_fast_intr_rxtx, NULL, info, name);
6175 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6177 taskqgroup_attach(tqg, gtask, q, dev, res, name);
6179 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6180 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6186 iflib_led_create(if_ctx_t ctx)
6189 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6190 device_get_nameunit(ctx->ifc_dev));
6194 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6197 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6201 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6204 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6208 iflib_admin_intr_deferred(if_ctx_t ctx)
6211 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6212 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6216 iflib_iov_intr_deferred(if_ctx_t ctx)
6219 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6223 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6226 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6231 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6235 GROUPTASK_INIT(gtask, 0, fn, ctx);
6236 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6241 iflib_config_gtask_deinit(struct grouptask *gtask)
6244 taskqgroup_detach(qgroup_if_config_tqg, gtask);
6248 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6250 if_t ifp = ctx->ifc_ifp;
6251 iflib_txq_t txq = ctx->ifc_txqs;
6253 if_setbaudrate(ifp, baudrate);
6254 if (baudrate >= IF_Gbps(10)) {
6256 ctx->ifc_flags |= IFC_PREFETCH;
6259 /* If link down, disable watchdog */
6260 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6261 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6262 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6264 ctx->ifc_link_state = link_state;
6265 if_link_state_change(ifp, link_state);
6269 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6273 int credits_pre = txq->ift_cidx_processed;
6276 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6277 BUS_DMASYNC_POSTREAD);
6278 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6281 txq->ift_processed += credits;
6282 txq->ift_cidx_processed += credits;
6284 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6285 if (txq->ift_cidx_processed >= txq->ift_size)
6286 txq->ift_cidx_processed -= txq->ift_size;
6291 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6296 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6297 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6298 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6299 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6304 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6305 const char *description, if_int_delay_info_t info,
6306 int offset, int value)
6308 info->iidi_ctx = ctx;
6309 info->iidi_offset = offset;
6310 info->iidi_value = value;
6311 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6312 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6313 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6314 info, 0, iflib_sysctl_int_delay, "I", description);
6318 iflib_ctx_lock_get(if_ctx_t ctx)
6321 return (&ctx->ifc_ctx_sx);
6325 iflib_msix_init(if_ctx_t ctx)
6327 device_t dev = ctx->ifc_dev;
6328 if_shared_ctx_t sctx = ctx->ifc_sctx;
6329 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6330 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6331 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6333 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6334 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6337 device_printf(dev, "msix_init qsets capped at %d\n",
6338 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6340 /* Override by tuneable */
6341 if (scctx->isc_disable_msix)
6344 /* First try MSI-X */
6345 if ((msgs = pci_msix_count(dev)) == 0) {
6347 device_printf(dev, "MSI-X not supported or disabled\n");
6351 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6353 * bar == -1 => "trust me I know what I'm doing"
6354 * Some drivers are for hardware that is so shoddily
6355 * documented that no one knows which bars are which
6356 * so the developer has to map all bars. This hack
6357 * allows shoddy garbage to use MSI-X in this framework.
6360 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6361 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6362 if (ctx->ifc_msix_mem == NULL) {
6363 device_printf(dev, "Unable to map MSI-X table\n");
6368 admincnt = sctx->isc_admin_intrcnt;
6370 /* use only 1 qset in debug mode */
6371 queuemsgs = min(msgs - admincnt, 1);
6373 queuemsgs = msgs - admincnt;
6376 queues = imin(queuemsgs, rss_getnumbuckets());
6380 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6383 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6384 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6386 /* If we're doing RSS, clamp at the number of RSS buckets */
6387 if (queues > rss_getnumbuckets())
6388 queues = rss_getnumbuckets();
6390 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6391 rx_queues = iflib_num_rx_queues;
6395 if (rx_queues > scctx->isc_nrxqsets)
6396 rx_queues = scctx->isc_nrxqsets;
6399 * We want this to be all logical CPUs by default
6401 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6402 tx_queues = iflib_num_tx_queues;
6404 tx_queues = mp_ncpus;
6406 if (tx_queues > scctx->isc_ntxqsets)
6407 tx_queues = scctx->isc_ntxqsets;
6409 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6411 if (tx_queues != rx_queues)
6413 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6414 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6416 tx_queues = min(rx_queues, tx_queues);
6417 rx_queues = min(rx_queues, tx_queues);
6420 vectors = rx_queues + admincnt;
6421 if (msgs < vectors) {
6423 "insufficient number of MSI-X vectors "
6424 "(supported %d, need %d)\n", msgs, vectors);
6428 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6431 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6432 if (vectors != msgs) {
6434 "Unable to allocate sufficient MSI-X vectors "
6435 "(got %d, need %d)\n", vectors, msgs);
6436 pci_release_msi(dev);
6438 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6440 ctx->ifc_msix_mem = NULL;
6444 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6446 scctx->isc_vectors = vectors;
6447 scctx->isc_nrxqsets = rx_queues;
6448 scctx->isc_ntxqsets = tx_queues;
6449 scctx->isc_intr = IFLIB_INTR_MSIX;
6454 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6457 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6459 ctx->ifc_msix_mem = NULL;
6464 vectors = pci_msi_count(dev);
6465 scctx->isc_nrxqsets = 1;
6466 scctx->isc_ntxqsets = 1;
6467 scctx->isc_vectors = vectors;
6468 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6469 device_printf(dev,"Using an MSI interrupt\n");
6470 scctx->isc_intr = IFLIB_INTR_MSI;
6472 scctx->isc_vectors = 1;
6473 device_printf(dev,"Using a Legacy interrupt\n");
6474 scctx->isc_intr = IFLIB_INTR_LEGACY;
6480 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6483 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6486 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6488 const char *ring_state = "UNKNOWN";
6491 rc = sysctl_wire_old_buffer(req, 0);
6495 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6500 ring_state = ring_states[state[3]];
6502 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6503 state[0], state[1], state[2], ring_state);
6504 rc = sbuf_finish(sb);
6509 enum iflib_ndesc_handler {
6515 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6517 if_ctx_t ctx = (void *)arg1;
6518 enum iflib_ndesc_handler type = arg2;
6519 char buf[256] = {0};
6526 case IFLIB_NTXD_HANDLER:
6527 ndesc = ctx->ifc_sysctl_ntxds;
6529 nqs = ctx->ifc_sctx->isc_ntxqs;
6531 case IFLIB_NRXD_HANDLER:
6532 ndesc = ctx->ifc_sysctl_nrxds;
6534 nqs = ctx->ifc_sctx->isc_nrxqs;
6537 printf("%s: unhandled type\n", __func__);
6543 for (i=0; i<8; i++) {
6548 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6551 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6552 if (rc || req->newptr == NULL)
6555 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6556 i++, p = strsep(&next, " ,")) {
6557 ndesc[i] = strtoul(p, NULL, 10);
6563 #define NAME_BUFLEN 32
6565 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6567 device_t dev = iflib_get_dev(ctx);
6568 struct sysctl_oid_list *child, *oid_list;
6569 struct sysctl_ctx_list *ctx_list;
6570 struct sysctl_oid *node;
6572 ctx_list = device_get_sysctl_ctx(dev);
6573 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6574 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6575 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6576 oid_list = SYSCTL_CHILDREN(node);
6578 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6579 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6582 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6583 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6584 "# of txqs to use, 0 => use default #");
6585 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6586 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6587 "# of rxqs to use, 0 => use default #");
6588 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6589 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6590 "permit #txq != #rxq");
6591 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6592 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6593 "disable MSI-X (default 0)");
6594 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6595 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6596 "set the RX budget");
6597 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6598 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6599 "cause TX to abdicate instead of running to completion");
6600 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6601 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6602 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6603 "offset to start using cores at");
6604 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6605 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6606 "use separate cores for TX and RX");
6608 /* XXX change for per-queue sizes */
6609 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6610 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6611 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6612 "list of # of TX descriptors to use, 0 = use default #");
6613 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6614 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6615 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6616 "list of # of RX descriptors to use, 0 = use default #");
6620 iflib_add_device_sysctl_post(if_ctx_t ctx)
6622 if_shared_ctx_t sctx = ctx->ifc_sctx;
6623 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6624 device_t dev = iflib_get_dev(ctx);
6625 struct sysctl_oid_list *child;
6626 struct sysctl_ctx_list *ctx_list;
6631 char namebuf[NAME_BUFLEN];
6633 struct sysctl_oid *queue_node, *fl_node, *node;
6634 struct sysctl_oid_list *queue_list, *fl_list;
6635 ctx_list = device_get_sysctl_ctx(dev);
6637 node = ctx->ifc_sysctl_node;
6638 child = SYSCTL_CHILDREN(node);
6640 if (scctx->isc_ntxqsets > 100)
6642 else if (scctx->isc_ntxqsets > 10)
6646 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6647 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6648 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6649 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6650 queue_list = SYSCTL_CHILDREN(queue_node);
6652 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6654 &txq->ift_dequeued, "total mbufs freed");
6655 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6657 &txq->ift_enqueued, "total mbufs enqueued");
6659 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6661 &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6662 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6664 &txq->ift_pullups, "# of times m_pullup was called");
6665 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6667 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6668 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6670 &txq->ift_no_desc_avail, "# of times no descriptors were available");
6671 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6673 &txq->ift_map_failed, "# of times DMA map failed");
6674 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6676 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6677 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6679 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6680 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6682 &txq->ift_pidx, 1, "Producer Index");
6683 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6685 &txq->ift_cidx, 1, "Consumer Index");
6686 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6688 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6689 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6691 &txq->ift_in_use, 1, "descriptors in use");
6692 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6694 &txq->ift_processed, "descriptors procesed for clean");
6695 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6697 &txq->ift_cleaned, "total cleaned");
6698 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6699 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6700 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6701 mp_ring_state_handler, "A", "soft ring state");
6702 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6703 CTLFLAG_RD, &txq->ift_br->enqueues,
6704 "# of enqueues to the mp_ring for this queue");
6705 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6706 CTLFLAG_RD, &txq->ift_br->drops,
6707 "# of drops in the mp_ring for this queue");
6708 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6709 CTLFLAG_RD, &txq->ift_br->starts,
6710 "# of normal consumer starts in the mp_ring for this queue");
6711 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6712 CTLFLAG_RD, &txq->ift_br->stalls,
6713 "# of consumer stalls in the mp_ring for this queue");
6714 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6715 CTLFLAG_RD, &txq->ift_br->restarts,
6716 "# of consumer restarts in the mp_ring for this queue");
6717 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6718 CTLFLAG_RD, &txq->ift_br->abdications,
6719 "# of consumer abdications in the mp_ring for this queue");
6722 if (scctx->isc_nrxqsets > 100)
6724 else if (scctx->isc_nrxqsets > 10)
6728 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6729 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6730 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6731 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6732 queue_list = SYSCTL_CHILDREN(queue_node);
6733 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6734 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6736 &rxq->ifr_cq_cidx, 1, "Consumer Index");
6739 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6740 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6741 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6742 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6743 fl_list = SYSCTL_CHILDREN(fl_node);
6744 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6746 &fl->ifl_pidx, 1, "Producer Index");
6747 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6749 &fl->ifl_cidx, 1, "Consumer Index");
6750 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6752 &fl->ifl_credits, 1, "credits available");
6753 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6755 &fl->ifl_buf_size, 1, "buffer size");
6757 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6759 &fl->ifl_m_enqueued, "mbufs allocated");
6760 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6762 &fl->ifl_m_dequeued, "mbufs freed");
6763 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6765 &fl->ifl_cl_enqueued, "clusters allocated");
6766 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6768 &fl->ifl_cl_dequeued, "clusters freed");
6777 iflib_request_reset(if_ctx_t ctx)
6781 ctx->ifc_flags |= IFC_DO_RESET;
6785 #ifndef __NO_STRICT_ALIGNMENT
6786 static struct mbuf *
6787 iflib_fixup_rx(struct mbuf *m)
6791 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6792 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6793 m->m_data += ETHER_HDR_LEN;
6796 MGETHDR(n, M_NOWAIT, MT_DATA);
6801 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6802 m->m_data += ETHER_HDR_LEN;
6803 m->m_len -= ETHER_HDR_LEN;
6804 n->m_len = ETHER_HDR_LEN;
6805 M_MOVE_PKTHDR(n, m);
6814 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6818 ctx = if_getsoftc(ifp);
6820 *nrxr = NRXQSETS(ctx);
6821 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6822 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6827 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6830 if_softc_ctx_t scctx;
6835 ctx = if_getsoftc(ifp);
6836 scctx = &ctx->ifc_softc_ctx;
6839 case DEBUGNET_START:
6840 for (i = 0; i < scctx->isc_nrxqsets; i++) {
6841 rxq = &ctx->ifc_rxqs[i];
6842 for (j = 0; j < rxq->ifr_nfl; j++) {
6844 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6847 iflib_no_tx_batch = 1;
6855 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6861 ctx = if_getsoftc(ifp);
6862 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6866 txq = &ctx->ifc_txqs[0];
6867 error = iflib_encap(txq, &m);
6869 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6874 iflib_debugnet_poll(if_t ifp, int count)
6876 struct epoch_tracker et;
6878 if_softc_ctx_t scctx;
6882 ctx = if_getsoftc(ifp);
6883 scctx = &ctx->ifc_softc_ctx;
6885 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6889 txq = &ctx->ifc_txqs[0];
6890 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6892 NET_EPOCH_ENTER(et);
6893 for (i = 0; i < scctx->isc_nrxqsets; i++)
6894 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6898 #endif /* DEBUGNET */