2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/mlx4/cq.h>
38 #include <linux/mlx4/qp.h>
40 #include <net/ethernet.h>
41 #include <net/if_vlan_var.h>
48 static int mlx4_en_alloc_buf(struct mlx4_en_priv *priv,
49 struct mlx4_en_rx_desc *rx_desc,
50 struct mbuf **mb_list,
53 struct mlx4_en_dev *mdev = priv->mdev;
54 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
59 mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, frag_info->frag_size);
61 mb = m_getjcl(M_NOWAIT, MT_DATA, 0, frag_info->frag_size);
63 priv->port_stats.rx_alloc_failed++;
66 dma = pci_map_single(mdev->pdev, mb->m_data, frag_info->frag_size,
68 rx_desc->data[i].addr = cpu_to_be64(dma);
73 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
74 struct mlx4_en_rx_ring *ring, int index)
76 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
80 /* Set size and memtype fields */
81 for (i = 0; i < priv->num_frags; i++) {
82 rx_desc->data[i].byte_count =
83 cpu_to_be32(priv->frag_info[i].frag_size);
84 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
87 /* If the number of used fragments does not fill up the ring stride,
88 * remaining (unused) fragments must be padded with null address/size
89 * and a special memory key */
90 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
91 for (i = priv->num_frags; i < possible_frags; i++) {
92 rx_desc->data[i].byte_count = 0;
93 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
94 rx_desc->data[i].addr = 0;
98 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
99 struct mlx4_en_rx_ring *ring, int index)
101 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
102 struct mbuf **mb_list = ring->rx_info + (index << priv->log_rx_info);
105 for (i = 0; i < priv->num_frags; i++)
106 if (mlx4_en_alloc_buf(priv, rx_desc, mb_list, i))
117 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
119 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
122 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
123 struct mlx4_en_rx_ring *ring,
126 struct mlx4_en_frag_info *frag_info;
127 struct mlx4_en_dev *mdev = priv->mdev;
128 struct mbuf **mb_list;
129 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
133 mb_list = ring->rx_info + (index << priv->log_rx_info);
134 for (nr = 0; nr < priv->num_frags; nr++) {
135 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
136 frag_info = &priv->frag_info[nr];
137 dma = be64_to_cpu(rx_desc->data[nr].addr);
139 en_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
140 pci_unmap_single(mdev->pdev, dma, frag_info->frag_size,
146 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
148 struct mlx4_en_rx_ring *ring;
154 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
155 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
156 ring = &priv->rx_ring[ring_ind];
158 err = mlx4_en_prepare_rx_desc(priv, ring,
161 if (ring->actual_size == 0) {
162 en_err(priv, "Failed to allocate "
163 "enough rx buffers\n");
166 new_size = rounddown_pow_of_two(ring->actual_size);
167 en_warn(priv, "Only %d buffers allocated "
168 "reducing ring size to %d\n",
169 ring->actual_size, new_size);
180 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
181 ring = &priv->rx_ring[ring_ind];
182 while (ring->actual_size > new_size) {
185 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
192 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
193 struct mlx4_en_rx_ring *ring)
197 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
198 ring->cons, ring->prod);
200 /* Unmap and free Rx buffers */
201 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
202 while (ring->cons != ring->prod) {
203 index = ring->cons & ring->size_mask;
204 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
205 mlx4_en_free_rx_desc(priv, ring, index);
211 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
212 struct mlx4_en_rx_ring *ring, u32 size)
214 struct mlx4_en_dev *mdev = priv->mdev;
222 ring->size_mask = size - 1;
223 ring->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
224 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
225 ring->log_stride = ffs(ring->stride) - 1;
226 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
228 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
229 sizeof(struct mbuf *));
231 ring->rx_info = kmalloc(tmp, GFP_KERNEL);
232 if (!ring->rx_info) {
233 en_err(priv, "Failed allocating rx_info ring\n");
236 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d stride:%d (%d)\n",
237 ring->rx_info, tmp, ring->stride, ring->log_stride);
239 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
240 ring->buf_size, 2 * PAGE_SIZE);
244 err = mlx4_en_map_buffer(&ring->wqres.buf);
246 en_err(priv, "Failed to map RX buffer\n");
249 ring->buf = ring->wqres.buf.direct.buf;
253 mlx4_en_unmap_buffer(&ring->wqres.buf);
255 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
257 kfree(ring->rx_info);
258 ring->rx_info = NULL;
262 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
264 struct mlx4_en_rx_ring *ring;
268 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
269 DS_SIZE * priv->num_frags);
270 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
271 ring = &priv->rx_ring[ring_ind];
275 ring->actual_size = 0;
276 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
277 ring->stride = stride;
278 if (ring->stride <= TXBB_SIZE)
279 ring->buf += TXBB_SIZE;
281 ring->log_stride = ffs(ring->stride) - 1;
282 ring->buf_size = ring->size * ring->stride;
284 memset(ring->buf, 0, ring->buf_size);
285 mlx4_en_update_rx_prod_db(ring);
287 /* Initailize all descriptors */
288 for (i = 0; i < ring->size; i++)
289 mlx4_en_init_rx_desc(priv, ring, i);
291 /* Configure lro mngr */
292 if (priv->dev->if_capenable & IFCAP_LRO) {
293 if (tcp_lro_init(&ring->lro))
294 priv->dev->if_capenable &= ~IFCAP_LRO;
296 ring->lro.ifp = priv->dev;
300 err = mlx4_en_fill_rx_buffers(priv);
304 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
305 ring = &priv->rx_ring[ring_ind];
307 ring->size_mask = ring->actual_size - 1;
308 mlx4_en_update_rx_prod_db(ring);
315 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
316 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
321 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
322 struct mlx4_en_rx_ring *ring)
324 struct mlx4_en_dev *mdev = priv->mdev;
326 mlx4_en_unmap_buffer(&ring->wqres.buf);
327 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE);
328 kfree(ring->rx_info);
329 ring->rx_info = NULL;
332 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
333 struct mlx4_en_rx_ring *ring)
336 tcp_lro_free(&ring->lro);
338 mlx4_en_free_rx_buf(priv, ring);
339 if (ring->stride <= TXBB_SIZE)
340 ring->buf -= TXBB_SIZE;
344 /* Unmap a completed descriptor and free unused pages */
345 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
346 struct mlx4_en_rx_desc *rx_desc,
347 struct mbuf **mb_list,
350 struct mlx4_en_dev *mdev = priv->mdev;
351 struct mlx4_en_frag_info *frag_info;
357 mb->m_pkthdr.len = length;
358 /* Collect used fragments while replacing them in the HW descirptors */
359 for (nr = 0; nr < priv->num_frags; nr++) {
360 frag_info = &priv->frag_info[nr];
361 if (length <= frag_info->frag_prefix_size)
364 mb->m_next = mb_list[nr];
366 mb->m_len = frag_info[nr].frag_size;
367 dma = be64_to_cpu(rx_desc->data[nr].addr);
369 /* Allocate a replacement page */
370 if (mlx4_en_alloc_buf(priv, rx_desc, mb_list, nr))
374 pci_unmap_single(mdev->pdev, dma, frag_info[nr].frag_size,
377 /* Adjust size of last fragment to match actual length */
378 mb->m_len = length - priv->frag_info[nr - 1].frag_prefix_size;
383 /* Drop all accumulated fragments (which have already been replaced in
384 * the descriptor) of this packet; remaining fragments are reused... */
393 static inline int invalid_cqe(struct mlx4_en_priv *priv,
394 struct mlx4_cqe *cqe)
396 /* Drop packet on bad receive or bad checksum */
397 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
398 MLX4_CQE_OPCODE_ERROR)) {
399 en_err(priv, "CQE completed in error - vendor "
400 "syndrom:%d syndrom:%d\n",
401 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
402 ((struct mlx4_err_cqe *) cqe)->syndrome);
405 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
406 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
413 static void validate_loopback(struct mlx4_en_priv *priv, struct mbuf *mb)
416 int offset = ETHER_HDR_LEN;
418 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
419 if (*(mb->m_data + offset) != (unsigned char) (i & 0xff))
423 priv->loopback_ok = 1;
429 static struct mbuf *mlx4_en_rx_mb(struct mlx4_en_priv *priv,
430 struct mlx4_en_rx_desc *rx_desc,
431 struct mbuf **mb_list,
437 /* Move relevant fragments to mb */
438 if (unlikely(mlx4_en_complete_rx_desc(priv, rx_desc, mb_list, length)))
445 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
447 struct mlx4_en_priv *priv = netdev_priv(dev);
448 struct mlx4_cqe *cqe;
449 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
450 struct mbuf **mb_list;
451 struct mlx4_en_rx_desc *rx_desc;
454 struct lro_entry *queued;
463 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
464 * descriptor offset can be deduced from the CQE index instead of
465 * reading 'cqe->index' */
466 index = cq->mcq.cons_index & ring->size_mask;
467 cqe = &cq->buf[index];
469 /* Process all completed CQEs */
470 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
471 cq->mcq.cons_index & cq->size)) {
473 mb_list = ring->rx_info + (index << priv->log_rx_info);
474 rx_desc = ring->buf + (index << ring->log_stride);
477 * make sure we read the CQE after we read the ownership bit
481 if (invalid_cqe(priv, cqe))
485 * Packet is OK - process it.
487 length = be32_to_cpu(cqe->byte_cnt);
488 mb = mlx4_en_rx_mb(priv, rx_desc, mb_list, length);
494 ring->bytes += length;
497 if (unlikely(priv->validate_loopback)) {
498 validate_loopback(priv, mb);
502 mb->m_pkthdr.flowid = cq->ring;
503 mb->m_flags |= M_FLOWID;
504 mb->m_pkthdr.rcvif = dev;
505 if (be32_to_cpu(cqe->vlan_my_qpn) &
506 MLX4_CQE_VLAN_PRESENT_MASK) {
507 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->sl_vid);
508 mb->m_flags |= M_VLANTAG;
510 if (likely(priv->rx_csum) &&
511 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
512 (cqe->checksum == cpu_to_be16(0xffff))) {
513 priv->port_stats.rx_chksum_good++;
514 mb->m_pkthdr.csum_flags =
515 CSUM_IP_CHECKED | CSUM_IP_VALID |
516 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
517 mb->m_pkthdr.csum_data = htons(0xffff);
518 /* This packet is eligible for LRO if it is:
519 * - DIX Ethernet (type interpretation)
521 * - without IP options
522 * - not an IP fragment
525 if (mlx4_en_can_lro(cqe->status) &&
526 (dev->if_capenable & IFCAP_LRO)) {
527 if (ring->lro.lro_cnt != 0 &&
528 tcp_lro_rx(&ring->lro, mb, 0) == 0)
533 /* LRO not possible, complete processing here */
534 INC_PERF_COUNTER(priv->pstats.lro_misses);
536 mb->m_pkthdr.csum_flags = 0;
537 priv->port_stats.rx_chksum_none++;
539 if (priv->ip_reasm &&
540 cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4) &&
541 !mlx4_en_rx_frags(priv, ring, mb, cqe))
546 /* Push it up the stack */
547 dev->if_input(dev, mb);
550 ++cq->mcq.cons_index;
551 index = (cq->mcq.cons_index) & ring->size_mask;
552 cqe = &cq->buf[index];
553 if (++polled == budget)
556 /* Flush all pending IP reassembly sessions */
559 mlx4_en_flush_frags(priv, ring);
560 while ((queued = SLIST_FIRST(&ring->lro.lro_active)) != NULL) {
561 SLIST_REMOVE_HEAD(&ring->lro.lro_active, next);
562 tcp_lro_flush(&ring->lro, queued);
565 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
566 mlx4_cq_set_ci(&cq->mcq);
567 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
568 ring->cons = cq->mcq.cons_index;
569 ring->prod += polled; /* Polled descriptors were realocated in place */
570 mlx4_en_update_rx_prod_db(ring);
575 /* Rx CQ polling - called by NAPI */
576 static int mlx4_en_poll_rx_cq(struct mlx4_en_cq *cq, int budget)
578 struct net_device *dev = cq->dev;
581 done = mlx4_en_process_rx_cq(dev, cq, budget);
587 void mlx4_en_rx_que(void *context, int pending)
589 struct mlx4_en_cq *cq;
592 while (mlx4_en_poll_rx_cq(cq, MLX4_EN_MAX_RX_POLL)
593 == MLX4_EN_MAX_RX_POLL);
594 mlx4_en_arm_cq(cq->dev->if_softc, cq);
597 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
599 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
600 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
603 done = mlx4_en_poll_rx_cq(cq, MLX4_EN_MAX_RX_POLL);
604 if (done == MLX4_EN_MAX_RX_POLL)
605 taskqueue_enqueue(cq->tq, &cq->cq_task);
607 mlx4_en_arm_cq(priv, cq);
611 #if MLX4_EN_MAX_RX_FRAGS == 3
612 static int frag_sizes[] = {
617 #elif MLX4_EN_MAX_RX_FRAGS == 2
618 static int frag_sizes[] = {
623 #error "Unknown MAX_RX_FRAGS"
626 void mlx4_en_calc_rx_buf(struct net_device *dev)
628 struct mlx4_en_priv *priv = netdev_priv(dev);
629 int eff_mtu = dev->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETH_LLC_SNAP_SIZE;
633 for (i = 0, frag = 0; buf_size < eff_mtu; frag++, i++) {
635 * Allocate small to large but only as much as is needed for
638 while (i > 0 && eff_mtu - buf_size <= frag_sizes[i - 1])
640 priv->frag_info[frag].frag_size = frag_sizes[i];
641 priv->frag_info[frag].frag_prefix_size = buf_size;
642 buf_size += priv->frag_info[frag].frag_size;
645 priv->num_frags = frag;
646 priv->rx_mb_size = eff_mtu;
648 ROUNDUP_LOG2(priv->num_frags * sizeof(struct mbuf *));
650 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
651 "num_frags:%d):\n", eff_mtu, priv->num_frags);
652 for (i = 0; i < priv->num_frags; i++) {
653 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d\n", i,
654 priv->frag_info[i].frag_size,
655 priv->frag_info[i].frag_prefix_size)
659 /* RSS related functions */
661 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
662 struct mlx4_en_rx_ring *ring,
663 enum mlx4_qp_state *state,
666 struct mlx4_en_dev *mdev = priv->mdev;
667 struct mlx4_qp_context *context;
670 context = kmalloc(sizeof *context , GFP_KERNEL);
672 en_err(priv, "Failed to allocate qp context\n");
675 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
677 en_err(priv, "Failed to allocate qp #%x\n", qpn);
680 qp->event = mlx4_en_sqp_event;
682 memset(context, 0, sizeof *context);
683 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
684 qpn, ring->cqn, context);
685 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
687 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
689 mlx4_qp_remove(mdev->dev, qp);
690 mlx4_qp_free(mdev->dev, qp);
692 mlx4_en_update_rx_prod_db(ring);
698 /* Allocate rx qp's and configure them according to rss map */
699 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
701 struct mlx4_en_dev *mdev = priv->mdev;
702 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
703 struct mlx4_qp_context context;
704 struct mlx4_en_rss_context *rss_context;
711 if (mdev->profile.udp_rss)
715 en_dbg(DRV, priv, "Configuring rss steering\n");
716 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
717 roundup_pow_of_two(priv->rx_ring_num),
718 &rss_map->base_qpn, 0);
720 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
724 for (i = 0; i < priv->rx_ring_num; i++) {
725 qpn = rss_map->base_qpn + i;
726 err = mlx4_en_config_rss_qp(priv, qpn,
736 /* Configure RSS indirection qp */
737 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn, 0);
739 en_err(priv, "Failed to reserve range for RSS "
743 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
745 en_err(priv, "Failed to allocate RSS indirection QP\n");
748 rss_map->indir_qp.event = mlx4_en_sqp_event;
749 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
750 priv->rx_ring[0].cqn, &context);
752 ptr = ((void *) &context) + 0x3c;
753 rss_context = (struct mlx4_en_rss_context *) ptr;
754 rss_context->base_qpn = cpu_to_be32(ilog2(priv->rx_ring_num) << 24 |
755 (rss_map->base_qpn));
756 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
757 rss_context->flags = rss_mask;
758 rss_context->base_qpn_udp = rss_context->default_qpn;
760 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
761 &rss_map->indir_qp, &rss_map->indir_state);
768 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
769 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
770 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
771 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
773 mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
775 for (i = 0; i < good_qps; i++) {
776 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
777 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
778 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
779 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
781 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
785 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
787 struct mlx4_en_dev *mdev = priv->mdev;
788 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
791 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
792 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
793 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
794 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
795 mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
797 for (i = 0; i < priv->rx_ring_num; i++) {
798 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
799 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
800 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
801 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
803 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);