2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/moduleparam.h>
40 int mlx4_set_4k_mtu = -1;
41 module_param_named(set_4k_mtu, mlx4_set_4k_mtu, int, 0444);
42 MODULE_PARM_DESC(set_4k_mtu,
43 "(Obsolete) attempt to set 4K MTU to all ConnectX ports");
46 #define MLX4_MAC_VALID (1ull << 63)
48 #define MLX4_VLAN_VALID (1u << 31)
49 #define MLX4_VLAN_MASK 0xfff
51 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
52 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
53 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
54 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
55 #define MLX4_STATS_IF_RX_ERRORS_COUNTERS_MASK 0x8010ULL
57 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
61 mutex_init(&table->mutex);
62 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
63 table->entries[i] = 0;
66 table->max = 1 << dev->caps.log_num_macs;
70 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
74 mutex_init(&table->mutex);
75 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
76 table->entries[i] = 0;
79 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
83 static int validate_index(struct mlx4_dev *dev,
84 struct mlx4_mac_table *table, int index)
88 if (index < 0 || index >= table->max || !table->entries[index]) {
89 mlx4_warn(dev, "No valid Mac entry for the given index\n");
95 static int find_index(struct mlx4_dev *dev,
96 struct mlx4_mac_table *table, u64 mac)
100 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
101 if ((mac & MLX4_MAC_MASK) ==
102 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
109 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
112 struct mlx4_cmd_mailbox *mailbox;
116 mailbox = mlx4_alloc_cmd_mailbox(dev);
118 return PTR_ERR(mailbox);
120 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
122 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
124 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
125 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
127 mlx4_free_cmd_mailbox(dev, mailbox);
131 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
133 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
134 struct mlx4_mac_table *table = &info->mac_table;
138 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
139 (unsigned long long) mac, port);
141 mutex_lock(&table->mutex);
142 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
143 if (free < 0 && !table->entries[i]) {
148 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
149 /* MAC already registered, Must not have duplicates */
156 mlx4_dbg(dev, "Free MAC index is %d\n", free);
158 if (table->total == table->max) {
159 /* No free mac entries */
164 /* Register new MAC */
165 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
167 err = mlx4_set_port_mac_table(dev, port, table->entries);
169 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
170 (unsigned long long) mac);
171 table->entries[free] = 0;
174 table->refs[free] = 1;
179 mutex_unlock(&table->mutex);
182 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
184 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
189 if (mlx4_is_mfunc(dev)) {
190 err = mlx4_cmd_imm(dev, mac, &out_param,
191 ((u32) port) << 8 | (u32) RES_MAC,
192 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
193 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
197 return get_param_l(&out_param);
199 return __mlx4_register_mac(dev, port, mac);
201 EXPORT_SYMBOL_GPL(mlx4_register_mac);
203 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port)
205 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
206 (port - 1) * (1 << dev->caps.log_num_macs);
208 EXPORT_SYMBOL_GPL(mlx4_get_base_qpn);
210 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
212 struct mlx4_port_info *info;
213 struct mlx4_mac_table *table;
216 if (port < 1 || port > dev->caps.num_ports) {
217 mlx4_warn(dev, "invalid port number (%d), aborting...\n", port);
220 info = &mlx4_priv(dev)->port[port];
221 table = &info->mac_table;
222 mutex_lock(&table->mutex);
224 index = find_index(dev, table, mac);
226 if (validate_index(dev, table, index))
229 if (--table->refs[index]) {
230 mlx4_dbg(dev, "Have more references for index %d,"
231 "no need to modify mac table\n", index);
235 table->entries[index] = 0;
236 mlx4_set_port_mac_table(dev, port, table->entries);
239 mutex_unlock(&table->mutex);
241 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
243 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
247 if (mlx4_is_mfunc(dev)) {
248 (void) mlx4_cmd_imm(dev, mac, &out_param,
249 ((u32) port) << 8 | (u32) RES_MAC,
250 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
251 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
254 __mlx4_unregister_mac(dev, port, mac);
257 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
259 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
261 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
262 struct mlx4_mac_table *table = &info->mac_table;
263 int index = qpn - info->base_qpn;
266 /* CX1 doesn't support multi-functions */
267 mutex_lock(&table->mutex);
269 err = validate_index(dev, table, index);
273 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
275 err = mlx4_set_port_mac_table(dev, port, table->entries);
277 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
278 (unsigned long long) new_mac);
279 table->entries[index] = 0;
282 mutex_unlock(&table->mutex);
285 EXPORT_SYMBOL_GPL(__mlx4_replace_mac);
287 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
290 struct mlx4_cmd_mailbox *mailbox;
294 mailbox = mlx4_alloc_cmd_mailbox(dev);
296 return PTR_ERR(mailbox);
298 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
299 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
300 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
301 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
303 mlx4_free_cmd_mailbox(dev, mailbox);
308 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
310 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
313 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
314 if (table->refs[i] &&
315 (vid == (MLX4_VLAN_MASK &
316 be32_to_cpu(table->entries[i])))) {
317 /* VLAN already registered, increase reference count */
325 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
327 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
330 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
334 mutex_lock(&table->mutex);
336 if (table->total == table->max) {
337 /* No free vlan entries */
342 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
343 if (free < 0 && (table->refs[i] == 0)) {
348 if (table->refs[i] &&
349 (vlan == (MLX4_VLAN_MASK &
350 be32_to_cpu(table->entries[i])))) {
351 /* Vlan already registered, increase references count */
363 /* Register new VLAN */
364 table->refs[free] = 1;
365 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
367 err = mlx4_set_port_vlan_table(dev, port, table->entries);
369 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
370 table->refs[free] = 0;
371 table->entries[free] = 0;
378 mutex_unlock(&table->mutex);
382 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
390 if (mlx4_is_mfunc(dev)) {
391 err = mlx4_cmd_imm(dev, vlan, &out_param,
392 ((u32) port) << 8 | (u32) RES_VLAN,
393 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
394 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
396 *index = get_param_l(&out_param);
400 return __mlx4_register_vlan(dev, port, vlan, index);
402 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
404 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
406 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
409 mutex_lock(&table->mutex);
410 if (mlx4_find_cached_vlan(dev, port, vlan, &index)) {
411 mlx4_warn(dev, "vlan 0x%x is not in the vlan table\n", vlan);
415 if (index < MLX4_VLAN_REGULAR) {
416 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
420 if (--table->refs[index]) {
421 mlx4_dbg(dev, "Have %d more references for index %d, "
422 "no need to modify vlan table\n", table->refs[index],
426 table->entries[index] = 0;
427 mlx4_set_port_vlan_table(dev, port, table->entries);
430 mutex_unlock(&table->mutex);
433 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan)
437 if (mlx4_is_mfunc(dev)) {
438 (void) mlx4_cmd_imm(dev, vlan, &out_param,
439 ((u32) port) << 8 | (u32) RES_VLAN,
440 RES_OP_RESERVE_AND_MAP,
441 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
445 __mlx4_unregister_vlan(dev, port, vlan);
447 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
449 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
451 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
455 inmailbox = mlx4_alloc_cmd_mailbox(dev);
456 if (IS_ERR(inmailbox))
457 return PTR_ERR(inmailbox);
459 outmailbox = mlx4_alloc_cmd_mailbox(dev);
460 if (IS_ERR(outmailbox)) {
461 mlx4_free_cmd_mailbox(dev, inmailbox);
462 return PTR_ERR(outmailbox);
465 inbuf = inmailbox->buf;
466 outbuf = outmailbox->buf;
467 memset(inbuf, 0, 256);
468 memset(outbuf, 0, 256);
473 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
474 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
476 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
477 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
480 *caps = *(__be32 *) (outbuf + 84);
481 mlx4_free_cmd_mailbox(dev, inmailbox);
482 mlx4_free_cmd_mailbox(dev, outmailbox);
485 static struct mlx4_roce_gid_entry zgid_entry;
487 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave)
490 return MLX4_ROCE_PF_GIDS;
491 if (slave <= ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) % dev->num_vfs))
492 return ((MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / dev->num_vfs) + 1;
493 return (MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS) / dev->num_vfs;
496 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave)
501 gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
506 if (slave <= gids % vfs)
507 return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave - 1);
509 return MLX4_ROCE_PF_GIDS + (gids % vfs) + ((gids / vfs) * (slave - 1));
512 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
513 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
515 struct mlx4_priv *priv = mlx4_priv(dev);
516 struct mlx4_port_info *port_info;
517 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
518 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
519 struct mlx4_set_port_rqp_calc_context *qpn_context;
520 struct mlx4_set_port_general_context *gen_context;
521 struct mlx4_roce_gid_entry *gid_entry_tbl, *gid_entry_mbox, *gid_entry_mb1;
522 int reset_qkey_viols;
534 __be32 slave_cap_mask;
537 port = in_mod & 0xff;
538 in_modifier = in_mod >> 8;
540 port_info = &priv->port[port];
542 /* Slaves cannot perform SET_PORT operations except changing MTU */
544 if (slave != dev->caps.function &&
545 in_modifier != MLX4_SET_PORT_GENERAL &&
546 in_modifier != MLX4_SET_PORT_GID_TABLE) {
547 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
551 switch (in_modifier) {
552 case MLX4_SET_PORT_RQP_CALC:
553 qpn_context = inbox->buf;
554 qpn_context->base_qpn =
555 cpu_to_be32(port_info->base_qpn);
556 qpn_context->n_mac = 0x7;
557 promisc = be32_to_cpu(qpn_context->promisc) >>
558 SET_PORT_PROMISC_SHIFT;
559 qpn_context->promisc = cpu_to_be32(
560 promisc << SET_PORT_PROMISC_SHIFT |
561 port_info->base_qpn);
562 promisc = be32_to_cpu(qpn_context->mcast) >>
563 SET_PORT_MC_PROMISC_SHIFT;
564 qpn_context->mcast = cpu_to_be32(
565 promisc << SET_PORT_MC_PROMISC_SHIFT |
566 port_info->base_qpn);
568 case MLX4_SET_PORT_GENERAL:
569 gen_context = inbox->buf;
570 /* Mtu is configured as the max MTU among all the
571 * the functions on the port. */
572 mtu = be16_to_cpu(gen_context->mtu);
573 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port]);
574 prev_mtu = slave_st->mtu[port];
575 slave_st->mtu[port] = mtu;
576 if (mtu > master->max_mtu[port])
577 master->max_mtu[port] = mtu;
578 if (mtu < prev_mtu && prev_mtu ==
579 master->max_mtu[port]) {
580 slave_st->mtu[port] = mtu;
581 master->max_mtu[port] = mtu;
582 for (i = 0; i < dev->num_slaves; i++) {
583 master->max_mtu[port] =
584 max(master->max_mtu[port],
585 master->slave_state[i].mtu[port]);
589 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
591 case MLX4_SET_PORT_GID_TABLE:
592 /* change to MULTIPLE entries: number of guest's gids
593 * need a FOR-loop here over number of gids the guest has.
594 * 1. Check no duplicates in gids passed by slave
596 num_gids = mlx4_get_slave_num_gids(dev, slave);
597 base = mlx4_get_base_gid_ix(dev, slave);
598 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
599 for (i = 0; i < num_gids; gid_entry_mbox++, i++) {
600 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
603 gid_entry_mb1 = gid_entry_mbox + 1;
604 for (j = i + 1; j < num_gids; gid_entry_mb1++, j++) {
605 if (!memcmp(gid_entry_mb1->raw,
606 zgid_entry.raw, sizeof(zgid_entry)))
608 if (!memcmp(gid_entry_mb1->raw, gid_entry_mbox->raw,
609 sizeof(gid_entry_mbox->raw))) {
610 /* found duplicate */
616 /* 2. Check that do not have duplicates in OTHER
617 * entries in the port GID table
619 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
620 if (i >= base && i < base + num_gids)
621 continue; /* don't compare to slave's current gids */
622 gid_entry_tbl = &priv->roce_gids[port - 1][i];
623 if (!memcmp(gid_entry_tbl->raw, zgid_entry.raw, sizeof(zgid_entry)))
625 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
626 for (j = 0; j < num_gids; gid_entry_mbox++, j++) {
627 if (!memcmp(gid_entry_mbox->raw, zgid_entry.raw,
630 if (!memcmp(gid_entry_mbox->raw, gid_entry_tbl->raw,
631 sizeof(gid_entry_tbl->raw))) {
632 /* found duplicate */
633 mlx4_warn(dev, "requested gid entry for slave:%d "
634 "is a duplicate of gid at index %d\n",
641 /* insert slave GIDs with memcpy, starting at slave's base index */
642 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
643 for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++)
644 memcpy(priv->roce_gids[port - 1][offset].raw, gid_entry_mbox->raw, 16);
646 /* Now, copy roce port gids table to current mailbox for passing to FW */
647 gid_entry_mbox = (struct mlx4_roce_gid_entry *) (inbox->buf);
648 for (i = 0; i < MLX4_ROCE_MAX_GIDS; gid_entry_mbox++, i++)
649 memcpy(gid_entry_mbox->raw, priv->roce_gids[port - 1][i].raw, 16);
653 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
654 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
658 /* For IB, we only consider:
659 * - The capability mask, which is set to the aggregate of all
660 * slave function capabilities
661 * - The QKey violatin counter - reset according to each request.
664 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
665 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
666 new_cap_mask = ((__be32 *) inbox->buf)[2];
668 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
669 new_cap_mask = ((__be32 *) inbox->buf)[1];
672 /* slave may not set the IS_SM capability for the port */
673 if (slave != mlx4_master_func_num(dev) &&
674 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_IS_SM))
677 /* No DEV_MGMT in multifunc mode */
678 if (mlx4_is_mfunc(dev) &&
679 (be32_to_cpu(new_cap_mask) & MLX4_PORT_CAP_DEV_MGMT_SUP))
684 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
685 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
686 for (i = 0; i < dev->num_slaves; i++)
688 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
690 /* only clear mailbox for guests. Master may be setting
691 * MTU or PKEY table size
693 if (slave != dev->caps.function)
694 memset(inbox->buf, 0, 256);
695 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
696 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
697 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
699 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
700 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
703 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
704 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
706 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
711 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
712 struct mlx4_vhcr *vhcr,
713 struct mlx4_cmd_mailbox *inbox,
714 struct mlx4_cmd_mailbox *outbox,
715 struct mlx4_cmd_info *cmd)
717 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
718 vhcr->op_modifier, inbox);
721 /* bit locations for set port command with zero op modifier */
723 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
724 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
725 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
726 MLX4_CHANGE_PORT_VL_CAP = 21,
727 MLX4_CHANGE_PORT_MTU_CAP = 22,
730 #define CX3_PPF_DEV_ID 0x1003
731 static int vl_cap_start(struct mlx4_dev *dev)
733 /* for non CX3 devices, start with 4 VLs to avoid errors in syslog */
734 if (dev->pdev->device != CX3_PPF_DEV_ID)
739 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
741 struct mlx4_cmd_mailbox *mailbox;
742 int err, vl_cap, pkey_tbl_flag = 0;
745 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_NONE)
748 mailbox = mlx4_alloc_cmd_mailbox(dev);
750 return PTR_ERR(mailbox);
752 memset(mailbox->buf, 0, 256);
754 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
755 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
756 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1,
757 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
760 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
762 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
764 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
767 /* IB VL CAP enum isn't used by the firmware, just numerical values */
768 for (vl_cap = vl_cap_start(dev); vl_cap >= 1; vl_cap >>= 1) {
769 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
770 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
771 (1 << MLX4_CHANGE_PORT_VL_CAP) |
772 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
773 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
774 (vl_cap << MLX4_SET_PORT_VL_CAP));
775 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
776 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
782 mlx4_free_cmd_mailbox(dev, mailbox);
786 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
787 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
789 struct mlx4_cmd_mailbox *mailbox;
790 struct mlx4_set_port_general_context *context;
794 mailbox = mlx4_alloc_cmd_mailbox(dev);
796 return PTR_ERR(mailbox);
797 context = mailbox->buf;
798 memset(context, 0, sizeof *context);
800 context->flags = SET_PORT_GEN_ALL_VALID;
801 context->mtu = cpu_to_be16(mtu);
802 context->pptx = (pptx * (!pfctx)) << 7;
803 context->pfctx = pfctx;
804 context->pprx = (pprx * (!pfcrx)) << 7;
805 context->pfcrx = pfcrx;
807 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
808 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
809 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
811 mlx4_free_cmd_mailbox(dev, mailbox);
814 EXPORT_SYMBOL(mlx4_SET_PORT_general);
816 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
819 struct mlx4_cmd_mailbox *mailbox;
820 struct mlx4_set_port_rqp_calc_context *context;
823 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
824 MCAST_DIRECT : MCAST_DEFAULT;
826 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
830 mailbox = mlx4_alloc_cmd_mailbox(dev);
832 return PTR_ERR(mailbox);
833 context = mailbox->buf;
834 memset(context, 0, sizeof *context);
836 context->base_qpn = cpu_to_be32(base_qpn);
838 * This assignment breaks vlan support - I don't know why. Probablya an A0 issue - shahar Klein
839 * context->n_mac = dev->caps.log_num_macs;
841 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
843 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
845 context->intra_no_vlan = 0;
846 context->no_vlan = MLX4_NO_VLAN_IDX;
847 context->intra_vlan_miss = 0;
848 context->vlan_miss = MLX4_VLAN_MISS_IDX;
850 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
851 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
852 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
854 mlx4_free_cmd_mailbox(dev, mailbox);
857 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
859 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
861 struct mlx4_cmd_mailbox *mailbox;
862 struct mlx4_set_port_prio2tc_context *context;
867 mailbox = mlx4_alloc_cmd_mailbox(dev);
869 return PTR_ERR(mailbox);
870 context = mailbox->buf;
871 memset(context, 0, sizeof *context);
873 for (i = 0; i < MLX4_NUM_UP; i += 2)
874 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
876 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
877 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
878 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
880 mlx4_free_cmd_mailbox(dev, mailbox);
883 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
885 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
886 u8 *pg, u16 *ratelimit)
888 struct mlx4_cmd_mailbox *mailbox;
889 struct mlx4_set_port_scheduler_context *context;
894 mailbox = mlx4_alloc_cmd_mailbox(dev);
896 return PTR_ERR(mailbox);
897 context = mailbox->buf;
898 memset(context, 0, sizeof *context);
900 for (i = 0; i < MLX4_NUM_TC; i++) {
901 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
903 if (ratelimit && ratelimit[i]) {
904 if (ratelimit[i] <= MLX4_MAX_100M_UNITS_VAL) {
907 htons(MLX4_RATELIMIT_100M_UNITS);
911 htons(MLX4_RATELIMIT_1G_UNITS);
913 tc->max_bw_value = htons(r);
915 tc->max_bw_value = htons(MLX4_RATELIMIT_DEFAULT);
916 tc->max_bw_units = htons(MLX4_RATELIMIT_1G_UNITS);
919 tc->pg = htons(pg[i]);
920 tc->bw_precentage = htons(tc_tx_bw[i]);
923 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
924 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
925 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
927 mlx4_free_cmd_mailbox(dev, mailbox);
930 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
932 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd)
943 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
944 u64 mac, u64 clear, u8 mode)
946 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
947 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
950 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
952 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd)
963 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
964 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
966 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
967 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
971 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
972 struct mlx4_vhcr *vhcr,
973 struct mlx4_cmd_mailbox *inbox,
974 struct mlx4_cmd_mailbox *outbox,
975 struct mlx4_cmd_info *cmd)
977 if (slave != dev->caps.function)
979 return mlx4_common_dump_eth_stats(dev, slave,
980 vhcr->in_modifier, outbox);
983 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
985 if (!mlx4_is_mfunc(dev)) {
990 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
991 MLX4_STATS_TRAFFIC_DROPS_MASK |
992 MLX4_STATS_PORT_COUNTERS_MASK |
993 MLX4_STATS_IF_RX_ERRORS_COUNTERS_MASK);
995 if (mlx4_is_master(dev))
996 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
998 EXPORT_SYMBOL(mlx4_set_stats_bitmap);
1000 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id)
1002 struct mlx4_priv *priv = mlx4_priv(dev);
1003 int i, found_ix = -1;
1004 int vf_gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1006 if (!mlx4_is_mfunc(dev))
1009 for (i = 0; i < MLX4_ROCE_MAX_GIDS; i++) {
1010 if (!memcmp(priv->roce_gids[port - 1][i].raw, gid, 16)) {
1016 if (found_ix >= 0) {
1017 if (found_ix < MLX4_ROCE_PF_GIDS)
1019 else if (found_ix < MLX4_ROCE_PF_GIDS + (vf_gids % dev->num_vfs) *
1020 (vf_gids / dev->num_vfs + 1))
1021 *slave_id = ((found_ix - MLX4_ROCE_PF_GIDS) /
1022 (vf_gids / dev->num_vfs + 1)) + 1;
1025 ((found_ix - MLX4_ROCE_PF_GIDS -
1026 ((vf_gids % dev->num_vfs) * ((vf_gids / dev->num_vfs + 1)))) /
1027 (vf_gids / dev->num_vfs)) + vf_gids % dev->num_vfs + 1;
1030 return (found_ix >= 0) ? 0 : -EINVAL;
1032 EXPORT_SYMBOL(mlx4_get_slave_from_roce_gid);
1034 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid)
1036 struct mlx4_priv *priv = mlx4_priv(dev);
1038 if (!mlx4_is_master(dev))
1041 memcpy(gid, priv->roce_gids[port - 1][slave_id].raw, 16);
1044 EXPORT_SYMBOL(mlx4_get_roce_gid_from_slave);