sys/pc98/cbus/pcrtc.c

   1 /*-
   2  * Copyright (c) 1990 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * This code is derived from software contributed to Berkeley by
   6  * William Jolitz and Don Ahn.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by the University of
  19  *      California, Berkeley and its contributors.
  20  * 4. Neither the name of the University nor the names of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  *      from: @(#)clock.c       7.2 (Berkeley) 5/12/91
  37  * $FreeBSD$
  38  */
  39
  40 /*
  41  * Routines to handle clock hardware.
  42  */
  43
  44 /*
  45  * inittodr, settodr and support routines written
  46  * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
  47  *
  48  * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
  49  */
  50
  51 /*
  52  * modified for PC98 by Kakefuda
  53  */
  54
  55 #include "opt_clock.h"
  56 #include "apm.h"
  57
  58 #include <sys/param.h>
  59 #include <sys/systm.h>
  60 #include <sys/time.h>
  61 #include <sys/kernel.h>
  62 #ifndef SMP
  63 #include <sys/lock.h>
  64 #endif
  65 #include <sys/sysctl.h>
  66 #include <sys/cons.h>
  67
  68 #include <machine/clock.h>
  69 #ifdef CLK_CALIBRATION_LOOP
  70 #endif
  71 #include <machine/cputypes.h>
  72 #include <machine/frame.h>
  73 #include <machine/ipl.h>
  74 #include <machine/limits.h>
  75 #include <machine/md_var.h>
  76 #include <machine/psl.h>
  77 #ifdef APIC_IO
  78 #include <machine/segments.h>
  79 #endif
  80 #if defined(SMP) || defined(APIC_IO)
  81 #include <machine/smp.h>
  82 #endif /* SMP || APIC_IO */
  83 #include <machine/specialreg.h>
  84
  85 #include <i386/isa/icu.h>
  86 #ifdef PC98
  87 #include <pc98/pc98/pc98.h>
  88 #include <pc98/pc98/pc98_machdep.h>
  89 #include <i386/isa/isa_device.h>
  90 #else
  91 #include <i386/isa/isa.h>
  92 #include <isa/rtc.h>
  93 #endif
  94 #include <i386/isa/timerreg.h>
  95
  96 #include <i386/isa/intr_machdep.h>
  97
  98 #include "mca.h"
  99 #if NMCA > 0
 100 #include <i386/isa/mca_machdep.h>
 101 #endif
 102
 103 #ifdef SMP
 104 #define disable_intr()  CLOCK_DISABLE_INTR()
 105 #define enable_intr()   CLOCK_ENABLE_INTR()
 106
 107 #ifdef APIC_IO
 108 #include <i386/isa/intr_machdep.h>
 109 /* The interrupt triggered by the 8254 (timer) chip */
 110 int apic_8254_intr;
 111 static u_long read_intr_count __P((int vec));
 112 static void setup_8254_mixed_mode __P((void));
 113 #endif
 114 #endif /* SMP */
 115
 116 /*
 117  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
 118  * can use a simple formula for leap years.
 119  */
 120 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
 121 #define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
 122
 123 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
 124
 125 /*
 126  * Time in timer cycles that it takes for microtime() to disable interrupts
 127  * and latch the count.  microtime() currently uses "cli; outb ..." so it
 128  * normally takes less than 2 timer cycles.  Add a few for cache misses.
 129  * Add a few more to allow for latency in bogus calls to microtime() with
 130  * interrupts already disabled.
 131  */
 132 #define TIMER0_LATCH_COUNT      20
 133
 134 /*
 135  * Maximum frequency that we are willing to allow for timer0.  Must be
 136  * low enough to guarantee that the timer interrupt handler returns
 137  * before the next timer interrupt.
 138  */
 139 #define TIMER0_MAX_FREQ         20000
 140
 141 int     adjkerntz;              /* local offset from GMT in seconds */
 142 int     clkintr_pending;
 143 int     disable_rtc_set;        /* disable resettodr() if != 0 */
 144 volatile u_int  idelayed;
 145 int     statclock_disable;
 146 u_int   stat_imask = SWI_CLOCK_MASK;
 147 #ifndef TIMER_FREQ
 148 #ifdef PC98
 149 #define TIMER_FREQ      2457600;
 150 #else /* IBM-PC */
 151 #define TIMER_FREQ      1193182;
 152 #endif /* PC98 */
 153 #endif
 154 u_int   timer_freq = TIMER_FREQ;
 155 int     timer0_max_count;
 156 u_int   tsc_freq;
 157 int     tsc_is_broken;
 158 int     wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
 159
 160 static  int     beeping = 0;
 161 static  u_int   clk_imask = HWI_MASK | SWI_MASK;
 162 static  const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
 163 static  u_int   hardclock_max_count;
 164 static  u_int32_t i8254_lastcount;
 165 static  u_int32_t i8254_offset;
 166 static  int     i8254_ticked;
 167 /*
 168  * XXX new_function and timer_func should not handle clockframes, but
 169  * timer_func currently needs to hold hardclock to handle the
 170  * timer0_state == 0 case.  We should use inthand_add()/inthand_remove()
 171  * to switch between clkintr() and a slightly different timerintr().
 172  */
 173 static  void    (*new_function) __P((struct clockframe *frame));
 174 static  u_int   new_rate;
 175 #ifndef PC98
 176 static  u_char  rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
 177 static  u_char  rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
 178 #endif
 179 static  u_int   timer0_prescaler_count;
 180
 181 /* Values for timerX_state: */
 182 #define RELEASED        0
 183 #define RELEASE_PENDING 1
 184 #define ACQUIRED        2
 185 #define ACQUIRE_PENDING 3
 186
 187 static  u_char  timer0_state;
 188 #ifdef  PC98
 189 static  u_char  timer1_state;
 190 #endif
 191 static  u_char  timer2_state;
 192 static  void    (*timer_func) __P((struct clockframe *frame)) = hardclock;
 193 #ifdef PC98
 194 static void rtc_serialcombit __P((int));
 195 static void rtc_serialcom __P((int));
 196 static int rtc_inb __P((void));
 197 static void rtc_outb __P((int));
 198 #endif
 199 static  u_int   tsc_present;
 200
 201 static  unsigned i8254_get_timecount __P((struct timecounter *tc));
 202 static  unsigned tsc_get_timecount __P((struct timecounter *tc));
 203 static  void    set_timer_freq(u_int freq, int intr_freq);
 204
 205 static struct timecounter tsc_timecounter = {
 206         tsc_get_timecount,      /* get_timecount */
 207         0,                      /* no poll_pps */
 208         ~0u,                    /* counter_mask */
 209         0,                      /* frequency */
 210          "TSC"                  /* name */
 211 };
 212
 213 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
 214         &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
 215
 216 static struct timecounter i8254_timecounter = {
 217         i8254_get_timecount,    /* get_timecount */
 218         0,                      /* no poll_pps */
 219         ~0u,                    /* counter_mask */
 220         0,                      /* frequency */
 221         "i8254"                 /* name */
 222 };
 223
 224 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
 225         &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
 226
 227 static void
 228 clkintr(struct clockframe frame)
 229 {
 230         if (timecounter->tc_get_timecount == i8254_get_timecount) {
 231                 disable_intr();
 232                 if (i8254_ticked)
 233                         i8254_ticked = 0;
 234                 else {
 235                         i8254_offset += timer0_max_count;
 236                         i8254_lastcount = 0;
 237                 }
 238                 clkintr_pending = 0;
 239                 enable_intr();
 240         }
 241         timer_func(&frame);
 242         switch (timer0_state) {
 243
 244         case RELEASED:
 245                 setdelayed();
 246                 break;
 247
 248         case ACQUIRED:
 249                 if ((timer0_prescaler_count += timer0_max_count)
 250                     >= hardclock_max_count) {
 251                         timer0_prescaler_count -= hardclock_max_count;
 252                         hardclock(&frame);
 253                         setdelayed();
 254                 }
 255                 break;
 256
 257         case ACQUIRE_PENDING:
 258                 disable_intr();
 259                 i8254_offset = i8254_get_timecount(NULL);
 260                 i8254_lastcount = 0;
 261                 timer0_max_count = TIMER_DIV(new_rate);
 262                 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 263                 outb(TIMER_CNTR0, timer0_max_count & 0xff);
 264                 outb(TIMER_CNTR0, timer0_max_count >> 8);
 265                 enable_intr();
 266                 timer_func = new_function;
 267                 timer0_state = ACQUIRED;
 268                 setdelayed();
 269                 break;
 270
 271         case RELEASE_PENDING:
 272                 if ((timer0_prescaler_count += timer0_max_count)
 273                     >= hardclock_max_count) {
 274                         disable_intr();
 275                         i8254_offset = i8254_get_timecount(NULL);
 276                         i8254_lastcount = 0;
 277                         timer0_max_count = hardclock_max_count;
 278                         outb(TIMER_MODE,
 279                              TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 280                         outb(TIMER_CNTR0, timer0_max_count & 0xff);
 281                         outb(TIMER_CNTR0, timer0_max_count >> 8);
 282                         enable_intr();
 283                         timer0_prescaler_count = 0;
 284                         timer_func = hardclock;
 285                         timer0_state = RELEASED;
 286                         hardclock(&frame);
 287                         setdelayed();
 288                 }
 289                 break;
 290         }
 291 #if NMCA > 0
 292         /* Reset clock interrupt by asserting bit 7 of port 0x61 */
 293         if (MCA_system)
 294                 outb(0x61, inb(0x61) | 0x80);
 295 #endif
 296 }
 297
 298 /*
 299  * The acquire and release functions must be called at ipl >= splclock().
 300  */
 301 int
 302 acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
 303 {
 304         static int old_rate;
 305
 306         if (rate <= 0 || rate > TIMER0_MAX_FREQ)
 307                 return (-1);
 308         switch (timer0_state) {
 309
 310         case RELEASED:
 311                 timer0_state = ACQUIRE_PENDING;
 312                 break;
 313
 314         case RELEASE_PENDING:
 315                 if (rate != old_rate)
 316                         return (-1);
 317                 /*
 318                  * The timer has been released recently, but is being
 319                  * re-acquired before the release completed.  In this
 320                  * case, we simply reclaim it as if it had not been
 321                  * released at all.
 322                  */
 323                 timer0_state = ACQUIRED;
 324                 break;
 325
 326         default:
 327                 return (-1);    /* busy */
 328         }
 329         new_function = function;
 330         old_rate = new_rate = rate;
 331         return (0);
 332 }
 333
 334 #ifdef PC98
 335 int
 336 acquire_timer1(int mode)
 337 {
 338
 339         if (timer1_state != RELEASED)
 340                 return (-1);
 341         timer1_state = ACQUIRED;
 342
 343         /*
 344          * This access to the timer registers is as atomic as possible
 345          * because it is a single instruction.  We could do better if we
 346          * knew the rate.  Use of splclock() limits glitches to 10-100us,
 347          * and this is probably good enough for timer2, so we aren't as
 348          * careful with it as with timer0.
 349          */
 350         outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f));
 351
 352         return (0);
 353 }
 354 #endif
 355
 356 int
 357 acquire_timer2(int mode)
 358 {
 359
 360         if (timer2_state != RELEASED)
 361                 return (-1);
 362         timer2_state = ACQUIRED;
 363
 364         /*
 365          * This access to the timer registers is as atomic as possible
 366          * because it is a single instruction.  We could do better if we
 367          * knew the rate.  Use of splclock() limits glitches to 10-100us,
 368          * and this is probably good enough for timer2, so we aren't as
 369          * careful with it as with timer0.
 370          */
 371         outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
 372
 373         return (0);
 374 }
 375
 376 int
 377 release_timer0()
 378 {
 379         switch (timer0_state) {
 380
 381         case ACQUIRED:
 382                 timer0_state = RELEASE_PENDING;
 383                 break;
 384
 385         case ACQUIRE_PENDING:
 386                 /* Nothing happened yet, release quickly. */
 387                 timer0_state = RELEASED;
 388                 break;
 389
 390         default:
 391                 return (-1);
 392         }
 393         return (0);
 394 }
 395
 396 #ifdef PC98
 397 int
 398 release_timer1()
 399 {
 400
 401         if (timer1_state != ACQUIRED)
 402                 return (-1);
 403         timer1_state = RELEASED;
 404         outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT);
 405         return (0);
 406 }
 407 #endif
 408
 409 int
 410 release_timer2()
 411 {
 412
 413         if (timer2_state != ACQUIRED)
 414                 return (-1);
 415         timer2_state = RELEASED;
 416         outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
 417         return (0);
 418 }
 419
 420 #ifndef PC98
 421 /*
 422  * This routine receives statistical clock interrupts from the RTC.
 423  * As explained above, these occur at 128 interrupts per second.
 424  * When profiling, we receive interrupts at a rate of 1024 Hz.
 425  *
 426  * This does not actually add as much overhead as it sounds, because
 427  * when the statistical clock is active, the hardclock driver no longer
 428  * needs to keep (inaccurate) statistics on its own.  This decouples
 429  * statistics gathering from scheduling interrupts.
 430  *
 431  * The RTC chip requires that we read status register C (RTC_INTR)
 432  * to acknowledge an interrupt, before it will generate the next one.
 433  * Under high interrupt load, rtcintr() can be indefinitely delayed and
 434  * the clock can tick immediately after the read from RTC_INTR.  In this
 435  * case, the mc146818A interrupt signal will not drop for long enough
 436  * to register with the 8259 PIC.  If an interrupt is missed, the stat
 437  * clock will halt, considerably degrading system performance.  This is
 438  * why we use 'while' rather than a more straightforward 'if' below.
 439  * Stat clock ticks can still be lost, causing minor loss of accuracy
 440  * in the statistics, but the stat clock will no longer stop.
 441  */
 442 static void
 443 rtcintr(struct clockframe frame)
 444 {
 445         while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 446                 statclock(&frame);
 447 }
 448
 449 #include "opt_ddb.h"
 450 #ifdef DDB
 451 #include <ddb/ddb.h>
 452
 453 DB_SHOW_COMMAND(rtc, rtc)
 454 {
 455         printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
 456                rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
 457                rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
 458                rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
 459 }
 460 #endif /* DDB */
 461 #endif /* for PC98 */
 462
 463 static int
 464 getit(void)
 465 {
 466         u_long ef;
 467         int high, low;
 468
 469         ef = read_eflags();
 470         disable_intr();
 471
 472         /* Select timer0 and latch counter value. */
 473         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
 474
 475         low = inb(TIMER_CNTR0);
 476         high = inb(TIMER_CNTR0);
 477
 478         CLOCK_UNLOCK();
 479         write_eflags(ef);
 480         return ((high << 8) | low);
 481 }
 482
 483 /*
 484  * Wait "n" microseconds.
 485  * Relies on timer 1 counting down from (timer_freq / hz)
 486  * Note: timer had better have been programmed before this is first used!
 487  */
 488 void
 489 DELAY(int n)
 490 {
 491         int delta, prev_tick, tick, ticks_left;
 492
 493 #ifdef DELAYDEBUG
 494         int getit_calls = 1;
 495         int n1;
 496         static int state = 0;
 497
 498         if (state == 0) {
 499                 state = 1;
 500                 for (n1 = 1; n1 <= 10000000; n1 *= 10)
 501                         DELAY(n1);
 502                 state = 2;
 503         }
 504         if (state == 1)
 505                 printf("DELAY(%d)...", n);
 506 #endif
 507         /*
 508          * Guard against the timer being uninitialized if we are called
 509          * early for console i/o.
 510          */
 511         if (timer0_max_count == 0)
 512                 set_timer_freq(timer_freq, hz);
 513
 514         /*
 515          * Read the counter first, so that the rest of the setup overhead is
 516          * counted.  Guess the initial overhead is 20 usec (on most systems it
 517          * takes about 1.5 usec for each of the i/o's in getit().  The loop
 518          * takes about 6 usec on a 486/33 and 13 usec on a 386/20.  The
 519          * multiplications and divisions to scale the count take a while).
 520          */
 521         prev_tick = getit();
 522         n -= 0;                 /* XXX actually guess no initial overhead */
 523         /*
 524          * Calculate (n * (timer_freq / 1e6)) without using floating point
 525          * and without any avoidable overflows.
 526          */
 527         if (n <= 0)
 528                 ticks_left = 0;
 529         else if (n < 256)
 530                 /*
 531                  * Use fixed point to avoid a slow division by 1000000.
 532                  * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
 533                  * 2^15 is the first power of 2 that gives exact results
 534                  * for n between 0 and 256.
 535                  */
 536                 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
 537         else
 538                 /*
 539                  * Don't bother using fixed point, although gcc-2.7.2
 540                  * generates particularly poor code for the long long
 541                  * division, since even the slow way will complete long
 542                  * before the delay is up (unless we're interrupted).
 543                  */
 544                 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
 545                              / 1000000;
 546
 547         while (ticks_left > 0) {
 548                 tick = getit();
 549 #ifdef DELAYDEBUG
 550                 ++getit_calls;
 551 #endif
 552                 delta = prev_tick - tick;
 553                 prev_tick = tick;
 554                 if (delta < 0) {
 555                         delta += timer0_max_count;
 556                         /*
 557                          * Guard against timer0_max_count being wrong.
 558                          * This shouldn't happen in normal operation,
 559                          * but it may happen if set_timer_freq() is
 560                          * traced.
 561                          */
 562                         if (delta < 0)
 563                                 delta = 0;
 564                 }
 565                 ticks_left -= delta;
 566         }
 567 #ifdef DELAYDEBUG
 568         if (state == 1)
 569                 printf(" %d calls to getit() at %d usec each\n",
 570                        getit_calls, (n + 5) / getit_calls);
 571 #endif
 572 }
 573
 574 static void
 575 sysbeepstop(void *chan)
 576 {
 577 #ifdef PC98     /* PC98 */
 578         outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */
 579         release_timer1();
 580 #else
 581         outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
 582         release_timer2();
 583 #endif
 584         beeping = 0;
 585 }
 586
 587 int
 588 sysbeep(int pitch, int period)
 589 {
 590         int x = splclock();
 591
 592 #ifdef PC98
 593         if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT))
 594                 if (!beeping) {
 595                         /* Something else owns it. */
 596                         splx(x);
 597                         return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
 598                 }
 599         disable_intr();
 600         outb(0x3fdb, pitch);
 601         outb(0x3fdb, (pitch>>8));
 602         enable_intr();
 603         if (!beeping) {
 604                 /* enable counter1 output to speaker */
 605                 outb(IO_PPI, (inb(IO_PPI) & 0xf7));
 606                 beeping = period;
 607                 timeout(sysbeepstop, (void *)NULL, period);
 608         }
 609 #else
 610         if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
 611                 if (!beeping) {
 612                         /* Something else owns it. */
 613                         splx(x);
 614                         return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
 615                 }
 616         disable_intr();
 617         outb(TIMER_CNTR2, pitch);
 618         outb(TIMER_CNTR2, (pitch>>8));
 619         enable_intr();
 620         if (!beeping) {
 621                 /* enable counter2 output to speaker */
 622                 outb(IO_PPI, inb(IO_PPI) | 3);
 623                 beeping = period;
 624                 timeout(sysbeepstop, (void *)NULL, period);
 625         }
 626 #endif
 627         splx(x);
 628         return (0);
 629 }
 630
 631 #ifndef PC98
 632 /*
 633  * RTC support routines
 634  */
 635
 636 int
 637 rtcin(reg)
 638         int reg;
 639 {
 640         int s;
 641         u_char val;
 642
 643         s = splhigh();
 644         outb(IO_RTC, reg);
 645         inb(0x84);
 646         val = inb(IO_RTC + 1);
 647         inb(0x84);
 648         splx(s);
 649         return (val);
 650 }
 651
 652 static __inline void
 653 writertc(u_char reg, u_char val)
 654 {
 655         int s;
 656
 657         s = splhigh();
 658         inb(0x84);
 659         outb(IO_RTC, reg);
 660         inb(0x84);
 661         outb(IO_RTC + 1, val);
 662         inb(0x84);              /* XXX work around wrong order in rtcin() */
 663         splx(s);
 664 }
 665
 666 static __inline int
 667 readrtc(int port)
 668 {
 669         return(bcd2bin(rtcin(port)));
 670 }
 671 #endif
 672
 673 #ifdef PC98
 674 unsigned int delaycount;
 675 #define FIRST_GUESS     0x2000
 676 static void findcpuspeed(void)
 677 {
 678         int i;
 679         int remainder;
 680
 681         /* Put counter in count down mode */
 682         outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN);
 683         outb(TIMER_CNTR0, 0xff);
 684         outb(TIMER_CNTR0, 0xff);
 685         for (i = FIRST_GUESS; i; i--)
 686                 ;
 687         remainder = getit();
 688         delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder);
 689 }
 690 #endif
 691
 692 #ifdef PC98
 693 static u_int
 694 calibrate_clocks(void)
 695 {
 696         int     timeout;
 697         u_int   count, prev_count, tot_count;
 698         u_short sec, start_sec;
 699
 700         if (bootverbose)
 701                 printf("Calibrating clock(s) ... ");
 702         /* Check ARTIC. */
 703         if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) &&
 704             !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04))
 705                 goto fail;
 706         timeout = 100000000;
 707
 708         /* Read the ARTIC. */
 709         sec = inw(0x5e);
 710
 711         /* Wait for the ARTIC to changes. */
 712         start_sec = sec;
 713         for (;;) {
 714                 sec = inw(0x5e);
 715                 if (sec != start_sec)
 716                         break;
 717                 if (--timeout == 0)
 718                         goto fail;
 719         }
 720         prev_count = getit();
 721         if (prev_count == 0 || prev_count > timer0_max_count)
 722                 goto fail;
 723         tot_count = 0;
 724
 725         if (tsc_present)
 726                 wrmsr(0x10, 0LL);       /* XXX 0x10 is the MSR for the TSC */
 727         start_sec = sec;
 728         for (;;) {
 729                 sec = inw(0x5e);
 730                 count = getit();
 731                 if (count == 0 || count > timer0_max_count)
 732                         goto fail;
 733                 if (count > prev_count)
 734                         tot_count += prev_count - (count - timer0_max_count);
 735                 else
 736                         tot_count += prev_count - count;
 737                 prev_count = count;
 738                 if ((sec == start_sec + 1200) ||
 739                     (sec < start_sec &&
 740                         (u_int)sec + 0x10000 == (u_int)start_sec + 1200))
 741                         break;
 742                 if (--timeout == 0)
 743                         goto fail;
 744         }
 745         /*
 746          * Read the cpu cycle counter.  The timing considerations are
 747          * similar to those for the i8254 clock.
 748          */
 749         if (tsc_present)
 750                 tsc_freq = rdtsc();
 751
 752         if (bootverbose) {
 753                 if (tsc_present)
 754                         printf("TSC clock: %u Hz, ", tsc_freq);
 755                 printf("i8254 clock: %u Hz\n", tot_count);
 756         }
 757         return (tot_count);
 758
 759 fail:
 760         if (bootverbose)
 761                 printf("failed, using default i8254 clock of %u Hz\n",
 762                        timer_freq);
 763         return (timer_freq);
 764 }
 765 #else
 766 static u_int
 767 calibrate_clocks(void)
 768 {
 769         u_int64_t old_tsc;
 770         u_int count, prev_count, tot_count;
 771         int sec, start_sec, timeout;
 772
 773         if (bootverbose)
 774                 printf("Calibrating clock(s) ... ");
 775         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 776                 goto fail;
 777         timeout = 100000000;
 778
 779         /* Read the mc146818A seconds counter. */
 780         for (;;) {
 781                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 782                         sec = rtcin(RTC_SEC);
 783                         break;
 784                 }
 785                 if (--timeout == 0)
 786                         goto fail;
 787         }
 788
 789         /* Wait for the mC146818A seconds counter to change. */
 790         start_sec = sec;
 791         for (;;) {
 792                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 793                         sec = rtcin(RTC_SEC);
 794                         if (sec != start_sec)
 795                                 break;
 796                 }
 797                 if (--timeout == 0)
 798                         goto fail;
 799         }
 800
 801         /* Start keeping track of the i8254 counter. */
 802         prev_count = getit();
 803         if (prev_count == 0 || prev_count > timer0_max_count)
 804                 goto fail;
 805         tot_count = 0;
 806
 807         if (tsc_present)
 808                 old_tsc = rdtsc();
 809         else
 810                 old_tsc = 0;            /* shut up gcc */
 811
 812         /*
 813          * Wait for the mc146818A seconds counter to change.  Read the i8254
 814          * counter for each iteration since this is convenient and only
 815          * costs a few usec of inaccuracy. The timing of the final reads
 816          * of the counters almost matches the timing of the initial reads,
 817          * so the main cause of inaccuracy is the varying latency from
 818          * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
 819          * rtcin(RTC_SEC) that returns a changed seconds count.  The
 820          * maximum inaccuracy from this cause is < 10 usec on 486's.
 821          */
 822         start_sec = sec;
 823         for (;;) {
 824                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
 825                         sec = rtcin(RTC_SEC);
 826                 count = getit();
 827                 if (count == 0 || count > timer0_max_count)
 828                         goto fail;
 829                 if (count > prev_count)
 830                         tot_count += prev_count - (count - timer0_max_count);
 831                 else
 832                         tot_count += prev_count - count;
 833                 prev_count = count;
 834                 if (sec != start_sec)
 835                         break;
 836                 if (--timeout == 0)
 837                         goto fail;
 838         }
 839
 840         /*
 841          * Read the cpu cycle counter.  The timing considerations are
 842          * similar to those for the i8254 clock.
 843          */
 844         if (tsc_present)
 845                 tsc_freq = rdtsc() - old_tsc;
 846
 847         if (bootverbose) {
 848                 if (tsc_present)
 849                         printf("TSC clock: %u Hz, ", tsc_freq);
 850                 printf("i8254 clock: %u Hz\n", tot_count);
 851         }
 852         return (tot_count);
 853
 854 fail:
 855         if (bootverbose)
 856                 printf("failed, using default i8254 clock of %u Hz\n",
 857                        timer_freq);
 858         return (timer_freq);
 859 }
 860 #endif  /* !PC98 */
 861
 862 static void
 863 set_timer_freq(u_int freq, int intr_freq)
 864 {
 865         u_long ef;
 866         int new_timer0_max_count;
 867
 868         ef = read_eflags();
 869         disable_intr();
 870         timer_freq = freq;
 871         new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
 872         if (new_timer0_max_count != timer0_max_count) {
 873                 timer0_max_count = new_timer0_max_count;
 874                 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 875                 outb(TIMER_CNTR0, timer0_max_count & 0xff);
 876                 outb(TIMER_CNTR0, timer0_max_count >> 8);
 877         }
 878         CLOCK_UNLOCK();
 879         write_eflags(ef);
 880 }
 881
 882 /*
 883  * i8254_restore is called from apm_default_resume() to reload
 884  * the countdown register.
 885  * this should not be necessary but there are broken laptops that
 886  * do not restore the countdown register on resume.
 887  * when it happnes, it messes up the hardclock interval and system clock,
 888  * which leads to the infamous "calcru: negative time" problem.
 889  */
 890 void
 891 i8254_restore(void)
 892 {
 893         u_long ef;
 894
 895         ef = read_eflags();
 896         disable_intr();
 897         outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 898         outb(TIMER_CNTR0, timer0_max_count & 0xff);
 899         outb(TIMER_CNTR0, timer0_max_count >> 8);
 900         CLOCK_UNLOCK();
 901         write_eflags(ef);
 902 }
 903
 904 /*
 905  * Initialize 8254 timer 0 early so that it can be used in DELAY().
 906  * XXX initialization of other timers is unintentionally left blank.
 907  */
 908 void
 909 startrtclock()
 910 {
 911         u_int delta, freq;
 912
 913 #ifdef PC98
 914         findcpuspeed();
 915         if (pc98_machine_type & M_8M)
 916                 timer_freq = 1996800L; /* 1.9968 MHz */
 917         else
 918                 timer_freq = 2457600L; /* 2.4576 MHz */
 919 #endif /* PC98 */
 920
 921         if (cpu_feature & CPUID_TSC)
 922                 tsc_present = 1;
 923         else
 924                 tsc_present = 0;
 925
 926 #ifndef PC98
 927         writertc(RTC_STATUSA, rtc_statusa);
 928         writertc(RTC_STATUSB, RTCSB_24HR);
 929 #endif
 930
 931         set_timer_freq(timer_freq, hz);
 932         freq = calibrate_clocks();
 933 #ifdef CLK_CALIBRATION_LOOP
 934         if (bootverbose) {
 935                 printf(
 936                 "Press a key on the console to abort clock calibration\n");
 937                 while (cncheckc() == -1)
 938                         calibrate_clocks();
 939         }
 940 #endif
 941
 942         /*
 943          * Use the calibrated i8254 frequency if it seems reasonable.
 944          * Otherwise use the default, and don't use the calibrated i586
 945          * frequency.
 946          */
 947         delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
 948         if (delta < timer_freq / 100) {
 949 #ifndef CLK_USE_I8254_CALIBRATION
 950                 if (bootverbose)
 951                         printf(
 952 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
 953                 freq = timer_freq;
 954 #endif
 955                 timer_freq = freq;
 956         } else {
 957                 if (bootverbose)
 958                         printf(
 959                     "%d Hz differs from default of %d Hz by more than 1%%\n",
 960                                freq, timer_freq);
 961                 tsc_freq = 0;
 962         }
 963
 964         set_timer_freq(timer_freq, hz);
 965         i8254_timecounter.tc_frequency = timer_freq;
 966         init_timecounter(&i8254_timecounter);
 967
 968 #ifndef CLK_USE_TSC_CALIBRATION
 969         if (tsc_freq != 0) {
 970                 if (bootverbose)
 971                         printf(
 972 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
 973                 tsc_freq = 0;
 974         }
 975 #endif
 976         if (tsc_present && tsc_freq == 0) {
 977                 /*
 978                  * Calibration of the i586 clock relative to the mc146818A
 979                  * clock failed.  Do a less accurate calibration relative
 980                  * to the i8254 clock.
 981                  */
 982                 u_int64_t old_tsc = rdtsc();
 983
 984                 DELAY(1000000);
 985                 tsc_freq = rdtsc() - old_tsc;
 986 #ifdef CLK_USE_TSC_CALIBRATION
 987                 if (bootverbose)
 988                         printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
 989 #endif
 990         }
 991
 992 #if !defined(SMP)
 993         /*
 994          * We can not use the TSC in SMP mode, until we figure out a
 995          * cheap (impossible), reliable and precise (yeah right!)  way
 996          * to synchronize the TSCs of all the CPUs.
 997          * Curse Intel for leaving the counter out of the I/O APIC.
 998          */
 999
1000 #if NAPM > 0
1001         /*
1002          * We can not use the TSC if we support APM. Precise timekeeping
1003          * on an APM'ed machine is at best a fools pursuit, since
1004          * any and all of the time spent in various SMM code can't
1005          * be reliably accounted for.  Reading the RTC is your only
1006          * source of reliable time info.  The i8254 looses too of course
1007          * but we need to have some kind of time...
1008          * We don't know at this point whether APM is going to be used
1009          * or not, nor when it might be activated.  Play it safe.
1010          */
1011         return;
1012 #endif /* NAPM > 0 */
1013
1014         if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
1015                 tsc_timecounter.tc_frequency = tsc_freq;
1016                 init_timecounter(&tsc_timecounter);
1017         }
1018
1019 #endif /* !defined(SMP) */
1020 }
1021
1022 #ifdef PC98
1023 static void
1024 rtc_serialcombit(int i)
1025 {
1026         outb(IO_RTC, ((i&0x01)<<5)|0x07);
1027         DELAY(1);
1028         outb(IO_RTC, ((i&0x01)<<5)|0x17);
1029         DELAY(1);
1030         outb(IO_RTC, ((i&0x01)<<5)|0x07);
1031         DELAY(1);
1032 }
1033
1034 static void
1035 rtc_serialcom(int i)
1036 {
1037         rtc_serialcombit(i&0x01);
1038         rtc_serialcombit((i&0x02)>>1);
1039         rtc_serialcombit((i&0x04)>>2);
1040         rtc_serialcombit((i&0x08)>>3);
1041         outb(IO_RTC, 0x07);
1042         DELAY(1);
1043         outb(IO_RTC, 0x0f);
1044         DELAY(1);
1045         outb(IO_RTC, 0x07);
1046         DELAY(1);
1047 }
1048
1049 static void
1050 rtc_outb(int val)
1051 {
1052         int s;
1053         int sa = 0;
1054
1055         for (s=0;s<8;s++) {
1056             sa = ((val >> s) & 0x01) ? 0x27 : 0x07;
1057             outb(IO_RTC, sa);           /* set DI & CLK 0 */
1058             DELAY(1);
1059             outb(IO_RTC, sa | 0x10);    /* CLK 1 */
1060             DELAY(1);
1061         }
1062         outb(IO_RTC, sa & 0xef);        /* CLK 0 */
1063 }
1064
1065 static int
1066 rtc_inb(void)
1067 {
1068         int s;
1069         int sa = 0;
1070
1071         for (s=0;s<8;s++) {
1072             sa |= ((inb(0x33) & 0x01) << s);
1073             outb(IO_RTC, 0x17); /* CLK 1 */
1074             DELAY(1);
1075             outb(IO_RTC, 0x07); /* CLK 0 */
1076             DELAY(2);
1077         }
1078         return sa;
1079 }
1080 #endif /* PC-98 */
1081
1082 /*
1083  * Initialize the time of day register, based on the time base which is, e.g.
1084  * from a filesystem.
1085  */
1086 void
1087 inittodr(time_t base)
1088 {
1089         unsigned long   sec, days;
1090 #ifndef PC98
1091         int             yd;
1092 #endif
1093         int             year, month;
1094         int             y, m, s;
1095         struct timespec ts;
1096 #ifdef PC98
1097         int             second, min, hour;
1098 #endif
1099
1100         if (base) {
1101                 s = splclock();
1102                 ts.tv_sec = base;
1103                 ts.tv_nsec = 0;
1104                 set_timecounter(&ts);
1105                 splx(s);
1106         }
1107
1108 #ifdef PC98
1109         rtc_serialcom(0x03);    /* Time Read */
1110         rtc_serialcom(0x01);    /* Register shift command. */
1111         DELAY(20);
1112
1113         second = bcd2bin(rtc_inb() & 0xff);     /* sec */
1114         min = bcd2bin(rtc_inb() & 0xff);        /* min */
1115         hour = bcd2bin(rtc_inb() & 0xff);       /* hour */
1116         days = bcd2bin(rtc_inb() & 0xff) - 1;   /* date */
1117
1118         month = (rtc_inb() >> 4) & 0x0f;        /* month */
1119         for (m = 1; m < month; m++)
1120                 days += daysinmonth[m-1];
1121         year = bcd2bin(rtc_inb() & 0xff) + 1900;        /* year */
1122         /* 2000 year problem */
1123         if (year < 1995)
1124                 year += 100;
1125         if (year < 1970)
1126                 goto wrong_time;
1127         for (y = 1970; y < year; y++)
1128                 days += DAYSPERYEAR + LEAPYEAR(y);
1129         if ((month > 2) && LEAPYEAR(year))
1130                 days ++;
1131         sec = ((( days * 24 +
1132                   hour) * 60 +
1133                   min) * 60 +
1134                   second);
1135         /* sec now contains the number of seconds, since Jan 1 1970,
1136            in the local time zone */
1137 #else   /* IBM-PC */
1138         /* Look if we have a RTC present and the time is valid */
1139         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
1140                 goto wrong_time;
1141
1142         /* wait for time update to complete */
1143         /* If RTCSA_TUP is zero, we have at least 244us before next update */
1144         s = splhigh();
1145         while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
1146                 splx(s);
1147                 s = splhigh();
1148         }
1149
1150         days = 0;
1151 #ifdef USE_RTC_CENTURY
1152         year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
1153 #else
1154         year = readrtc(RTC_YEAR) + 1900;
1155         if (year < 1970)
1156                 year += 100;
1157 #endif
1158         if (year < 1970) {
1159                 splx(s);
1160                 goto wrong_time;
1161         }
1162         month = readrtc(RTC_MONTH);
1163         for (m = 1; m < month; m++)
1164                 days += daysinmonth[m-1];
1165         if ((month > 2) && LEAPYEAR(year))
1166                 days ++;
1167         days += readrtc(RTC_DAY) - 1;
1168         yd = days;
1169         for (y = 1970; y < year; y++)
1170                 days += DAYSPERYEAR + LEAPYEAR(y);
1171         sec = ((( days * 24 +
1172                   readrtc(RTC_HRS)) * 60 +
1173                   readrtc(RTC_MIN)) * 60 +
1174                   readrtc(RTC_SEC));
1175         /* sec now contains the number of seconds, since Jan 1 1970,
1176            in the local time zone */
1177 #endif
1178
1179         sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
1180
1181         y = time_second - sec;
1182         if (y <= -2 || y >= 2) {
1183                 /* badly off, adjust it */
1184                 ts.tv_sec = sec;
1185                 ts.tv_nsec = 0;
1186                 set_timecounter(&ts);
1187         }
1188         splx(s);
1189         return;
1190
1191 wrong_time:
1192         printf("Invalid time in real time clock.\n");
1193         printf("Check and reset the date immediately!\n");
1194 }
1195
1196 /*
1197  * Write system time back to RTC
1198  */
1199 void
1200 resettodr()
1201 {
1202         unsigned long   tm;
1203         int             y, m, s;
1204 #ifdef PC98
1205         int             wd;
1206 #endif
1207
1208         if (disable_rtc_set)
1209                 return;
1210
1211         s = splclock();
1212         tm = time_second;
1213         splx(s);
1214
1215 #ifdef PC98
1216         rtc_serialcom(0x01);    /* Register shift command. */
1217
1218         /* Calculate local time to put in RTC */
1219
1220         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
1221
1222         rtc_outb(bin2bcd(tm%60)); tm /= 60;     /* Write back Seconds */
1223         rtc_outb(bin2bcd(tm%60)); tm /= 60;     /* Write back Minutes */
1224         rtc_outb(bin2bcd(tm%24)); tm /= 24;     /* Write back Hours   */
1225
1226         /* We have now the days since 01-01-1970 in tm */
1227         wd = (tm+4)%7;
1228         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
1229              tm >= m;
1230              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
1231              tm -= m;
1232
1233         /* Now we have the years in y and the day-of-the-year in tm */
1234         for (m = 0; ; m++) {
1235                 int ml;
1236
1237                 ml = daysinmonth[m];
1238                 if (m == 1 && LEAPYEAR(y))
1239                         ml++;
1240                 if (tm < ml)
1241                         break;
1242                 tm -= ml;
1243         }
1244
1245         m++;
1246         rtc_outb(bin2bcd(tm+1));                /* Write back Day     */
1247         rtc_outb((m << 4) | wd);                /* Write back Month & Weekday  */
1248         rtc_outb(bin2bcd(y%100));               /* Write back Year    */
1249
1250         rtc_serialcom(0x02);    /* Time set & Counter hold command. */
1251         rtc_serialcom(0x00);    /* Register hold command. */
1252 #else
1253         /* Disable RTC updates and interrupts. */
1254         writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
1255
1256         /* Calculate local time to put in RTC */
1257
1258         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
1259
1260         writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60;    /* Write back Seconds */
1261         writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60;    /* Write back Minutes */
1262         writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24;    /* Write back Hours   */
1263
1264         /* We have now the days since 01-01-1970 in tm */
1265         writertc(RTC_WDAY, (tm+4)%7);                   /* Write back Weekday */
1266         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
1267              tm >= m;
1268              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
1269              tm -= m;
1270
1271         /* Now we have the years in y and the day-of-the-year in tm */
1272         writertc(RTC_YEAR, bin2bcd(y%100));             /* Write back Year    */
1273 #ifdef USE_RTC_CENTURY
1274         writertc(RTC_CENTURY, bin2bcd(y/100));          /* ... and Century    */
1275 #endif
1276         for (m = 0; ; m++) {
1277                 int ml;
1278
1279                 ml = daysinmonth[m];
1280                 if (m == 1 && LEAPYEAR(y))
1281                         ml++;
1282                 if (tm < ml)
1283                         break;
1284                 tm -= ml;
1285         }
1286
1287         writertc(RTC_MONTH, bin2bcd(m + 1));            /* Write back Month   */
1288         writertc(RTC_DAY, bin2bcd(tm + 1));             /* Write back Month Day */
1289
1290         /* Reenable RTC updates and interrupts. */
1291         writertc(RTC_STATUSB, rtc_statusb);
1292 #endif
1293 }
1294
1295
1296 /*
1297  * Start both clocks running.
1298  */
1299 void
1300 cpu_initclocks()
1301 {
1302 #ifdef APIC_IO
1303         int apic_8254_trial;
1304         struct intrec *clkdesc;
1305 #endif /* APIC_IO */
1306 #ifndef PC98
1307         int diag;
1308
1309         if (statclock_disable) {
1310                 /*
1311                  * The stat interrupt mask is different without the
1312                  * statistics clock.  Also, don't set the interrupt
1313                  * flag which would normally cause the RTC to generate
1314                  * interrupts.
1315                  */
1316                 stat_imask = HWI_MASK | SWI_MASK;
1317                 rtc_statusb = RTCSB_24HR;
1318         } else {
1319                 /* Setting stathz to nonzero early helps avoid races. */
1320                 stathz = RTC_NOPROFRATE;
1321                 profhz = RTC_PROFRATE;
1322         }
1323 #endif
1324
1325         /* Finish initializing 8253 timer 0. */
1326 #ifdef APIC_IO
1327
1328         apic_8254_intr = isa_apic_irq(0);
1329         apic_8254_trial = 0;
1330         if (apic_8254_intr >= 0 ) {
1331                 if (apic_int_type(0, 0) == 3)
1332                         apic_8254_trial = 1;
1333         } else {
1334                 /* look for ExtInt on pin 0 */
1335                 if (apic_int_type(0, 0) == 3) {
1336                         apic_8254_intr = apic_irq(0, 0);
1337                         setup_8254_mixed_mode();
1338                 } else
1339                         panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1340         }
1341
1342         clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
1343                               NULL, &clk_imask, INTR_EXCL);
1344         INTREN(1 << apic_8254_intr);
1345
1346 #else /* APIC_IO */
1347
1348         inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
1349                     INTR_EXCL);
1350         INTREN(IRQ0);
1351
1352 #endif /* APIC_IO */
1353
1354 #ifndef PC98
1355         /* Initialize RTC. */
1356         writertc(RTC_STATUSA, rtc_statusa);
1357         writertc(RTC_STATUSB, RTCSB_24HR);
1358
1359         /* Don't bother enabling the statistics clock. */
1360         if (statclock_disable)
1361                 return;
1362         diag = rtcin(RTC_DIAG);
1363         if (diag != 0)
1364                 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1365
1366 #ifdef APIC_IO
1367         if (isa_apic_irq(8) != 8)
1368                 panic("APIC RTC != 8");
1369 #endif /* APIC_IO */
1370
1371         inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
1372                     INTR_EXCL);
1373
1374 #ifdef APIC_IO
1375         INTREN(APIC_IRQ8);
1376 #else
1377         INTREN(IRQ8);
1378 #endif /* APIC_IO */
1379
1380         writertc(RTC_STATUSB, rtc_statusb);
1381 #endif /* !PC98 */
1382
1383 #ifdef APIC_IO
1384         if (apic_8254_trial) {
1385
1386                 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1387                 while (read_intr_count(8) < 6)
1388                         ;       /* nothing */
1389                 if (read_intr_count(apic_8254_intr) < 3) {
1390                         /*
1391                          * The MP table is broken.
1392                          * The 8254 was not connected to the specified pin
1393                          * on the IO APIC.
1394                          * Workaround: Limited variant of mixed mode.
1395                          */
1396                         INTRDIS(1 << apic_8254_intr);
1397                         inthand_remove(clkdesc);
1398                         printf("APIC_IO: Broken MP table detected: "
1399                                "8254 is not connected to "
1400                                "IOAPIC #%d intpin %d\n",
1401                                int_to_apicintpin[apic_8254_intr].ioapic,
1402                                int_to_apicintpin[apic_8254_intr].int_pin);
1403                         /*
1404                          * Revoke current ISA IRQ 0 assignment and
1405                          * configure a fallback interrupt routing from
1406                          * the 8254 Timer via the 8259 PIC to the
1407                          * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1408                          * We reuse the low level interrupt handler number.
1409                          */
1410                         if (apic_irq(0, 0) < 0) {
1411                                 revoke_apic_irq(apic_8254_intr);
1412                                 assign_apic_irq(0, 0, apic_8254_intr);
1413                         }
1414                         apic_8254_intr = apic_irq(0, 0);
1415                         setup_8254_mixed_mode();
1416                         inthand_add("clk", apic_8254_intr,
1417                                     (inthand2_t *)clkintr,
1418                                     NULL, &clk_imask, INTR_EXCL);
1419                         INTREN(1 << apic_8254_intr);
1420                 }
1421
1422         }
1423         if (apic_int_type(0, 0) != 3 ||
1424             int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1425             int_to_apicintpin[apic_8254_intr].int_pin != 0)
1426                 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1427                        int_to_apicintpin[apic_8254_intr].ioapic,
1428                        int_to_apicintpin[apic_8254_intr].int_pin);
1429         else
1430                 printf("APIC_IO: "
1431                        "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1432 #endif
1433
1434 }
1435
1436 #ifdef APIC_IO
1437 static u_long
1438 read_intr_count(int vec)
1439 {
1440         u_long *up;
1441         up = intr_countp[vec];
1442         if (up)
1443                 return *up;
1444         return 0UL;
1445 }
1446
1447 static void
1448 setup_8254_mixed_mode()
1449 {
1450         /*
1451          * Allow 8254 timer to INTerrupt 8259:
1452          *  re-initialize master 8259:
1453          *   reset; prog 4 bytes, single ICU, edge triggered
1454          */
1455         outb(IO_ICU1, 0x13);
1456 #ifdef PC98
1457         outb(IO_ICU1 + 2, NRSVIDT);     /* start vector (unused) */
1458         outb(IO_ICU1 + 2, 0x00);        /* ignore slave */
1459         outb(IO_ICU1 + 2, 0x03);        /* auto EOI, 8086 */
1460         outb(IO_ICU1 + 2, 0xfe);        /* unmask INT0 */
1461 #else
1462         outb(IO_ICU1 + 1, NRSVIDT);     /* start vector (unused) */
1463         outb(IO_ICU1 + 1, 0x00);        /* ignore slave */
1464         outb(IO_ICU1 + 1, 0x03);        /* auto EOI, 8086 */
1465         outb(IO_ICU1 + 1, 0xfe);        /* unmask INT0 */
1466 #endif
1467         /* program IO APIC for type 3 INT on INT0 */
1468         if (ext_int_setup(0, 0) < 0)
1469                 panic("8254 redirect via APIC pin0 impossible!");
1470 }
1471 #endif
1472
1473 void
1474 setstatclockrate(int newhz)
1475 {
1476 #ifndef PC98
1477         if (newhz == RTC_PROFRATE)
1478                 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1479         else
1480                 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1481         writertc(RTC_STATUSA, rtc_statusa);
1482 #endif
1483 }
1484
1485 static int
1486 sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS
1487 {
1488         int error;
1489         u_int freq;
1490
1491         /*
1492          * Use `i8254' instead of `timer' in external names because `timer'
1493          * is is too generic.  Should use it everywhere.
1494          */
1495         freq = timer_freq;
1496         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1497         if (error == 0 && req->newptr != NULL) {
1498                 if (timer0_state != RELEASED)
1499                         return (EBUSY); /* too much trouble to handle */
1500                 set_timer_freq(freq, hz);
1501                 i8254_timecounter.tc_frequency = freq;
1502                 update_timecounter(&i8254_timecounter);
1503         }
1504         return (error);
1505 }
1506
1507 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1508     0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
1509
1510 static int
1511 sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS
1512 {
1513         int error;
1514         u_int freq;
1515
1516         if (tsc_timecounter.tc_frequency == 0)
1517                 return (EOPNOTSUPP);
1518         freq = tsc_freq;
1519         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1520         if (error == 0 && req->newptr != NULL) {
1521                 tsc_freq = freq;
1522                 tsc_timecounter.tc_frequency = tsc_freq;
1523                 update_timecounter(&tsc_timecounter);
1524         }
1525         return (error);
1526 }
1527
1528 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1529     0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", "");
1530
1531 static unsigned
1532 i8254_get_timecount(struct timecounter *tc)
1533 {
1534         u_int count;
1535         u_long ef;
1536         u_int high, low;
1537
1538         ef = read_eflags();
1539         disable_intr();
1540
1541         /* Select timer0 and latch counter value. */
1542         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1543
1544         low = inb(TIMER_CNTR0);
1545         high = inb(TIMER_CNTR0);
1546         count = timer0_max_count - ((high << 8) | low);
1547         if (count < i8254_lastcount ||
1548             (!i8254_ticked && (clkintr_pending ||
1549             ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
1550 #ifdef APIC_IO
1551 #define lapic_irr1      ((volatile u_int *)&lapic)[0x210 / 4]   /* XXX XXX */
1552             /* XXX this assumes that apic_8254_intr is < 24. */
1553             (lapic_irr1 & (1 << apic_8254_intr))))
1554 #else
1555             (inb(IO_ICU1) & 1)))
1556 #endif
1557             )) {
1558                 i8254_ticked = 1;
1559                 i8254_offset += timer0_max_count;
1560         }
1561         i8254_lastcount = count;
1562         count += i8254_offset;
1563         CLOCK_UNLOCK();
1564         write_eflags(ef);
1565         return (count);
1566 }
1567
1568 static unsigned
1569 tsc_get_timecount(struct timecounter *tc)
1570 {
1571         return (rdtsc());
1572 }