2 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
43 #include <machine/clock.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/vmparam.h>
50 #include <pc98/pc98/pc98.h>
52 #include <isa/isareg.h>
54 #include <isa/isavar.h>
56 #include <dev/ppbus/ppbconf.h>
57 #include <dev/ppbus/ppb_msq.h>
60 #include <pc98/pc98/ppcreg.h>
62 #include <i386/isa/ppcreg.h>
67 #define LOG_PPC(function, ppc, string) \
68 if (bootverbose) printf("%s: %s\n", function, string)
71 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
73 devclass_t ppc_devclass;
75 static int ppc_probe(device_t dev);
76 static int ppc_attach(device_t dev);
77 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
79 static void ppc_reset_epp(device_t);
80 static void ppc_ecp_sync(device_t);
81 static void ppcintr(void *arg);
83 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
84 static int ppc_setmode(device_t, int);
86 static int ppc_read(device_t, char *, int, int);
87 static int ppc_write(device_t, char *, int, int);
89 static u_char ppc_io(device_t, int, u_char *, int, u_char);
91 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
92 void (*)(void *), void *, void **);
93 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
95 static device_method_t ppc_methods[] = {
96 /* device interface */
97 DEVMETHOD(device_probe, ppc_probe),
98 DEVMETHOD(device_attach, ppc_attach),
101 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
102 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
103 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
104 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
106 /* ppbus interface */
107 DEVMETHOD(ppbus_io, ppc_io),
108 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
109 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
110 DEVMETHOD(ppbus_setmode, ppc_setmode),
111 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
112 DEVMETHOD(ppbus_read, ppc_read),
113 DEVMETHOD(ppbus_write, ppc_write),
118 static driver_t ppc_driver = {
121 sizeof(struct ppc_data),
124 static char *ppc_models[] = {
125 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
126 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0
129 /* list of available modes */
130 static char *ppc_avms[] = {
131 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
132 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
133 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
134 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
137 /* list of current executing modes
138 * Note that few modes do not actually exist.
140 static char *ppc_modes[] = {
141 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
142 "EPP", "EPP", "EPP", "ECP",
143 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
144 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
147 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
150 * BIOS printer list - used by BIOS probe.
152 #define BIOS_PPC_PORTS 0x408
153 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
154 #define BIOS_MAX_PPC 4
160 ppc_ecp_sync(device_t dev) {
163 struct ppc_data *ppc = DEVTOSOFTC(dev);
165 if (!(ppc->ppc_avm & PPB_ECP))
169 if ((r & 0xe0) != PPC_ECR_EPP)
172 for (i = 0; i < 100; i++) {
179 printf("ppc%d: ECP sync failed as data still " \
180 "present in FIFO.\n", ppc->ppc_unit);
188 * Detect parallel port FIFO
191 ppc_detect_fifo(struct ppc_data *ppc)
194 char ctr_sav, ctr, cc;
198 ecr_sav = r_ecr(ppc);
199 ctr_sav = r_ctr(ppc);
201 /* enter ECP configuration mode, no interrupt, no DMA */
204 /* read PWord size - transfers in FIFO mode must be PWord aligned */
205 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
207 /* XXX 16 and 32 bits implementations not supported */
208 if (ppc->ppc_pword != PPC_PWORD_8) {
209 LOG_PPC(__FUNCTION__, ppc, "PWord not supported");
213 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
215 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
217 /* enter ECP test mode, no interrupt, no DMA */
221 for (i=0; i<1024; i++) {
222 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
228 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO");
232 /* enable interrupts, no DMA */
235 /* determine readIntrThreshold
236 * fill the FIFO until serviceIntr is set
238 for (i=0; i<1024; i++) {
239 w_fifo(ppc, (char)i);
240 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
241 /* readThreshold reached */
244 if (r_ecr(ppc) & PPC_FIFO_FULL) {
251 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO");
255 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
256 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
257 w_ecr(ppc, 0xd0); /* enable interrupts */
259 /* determine writeIntrThreshold
260 * empty the FIFO until serviceIntr is set
262 for (i=ppc->ppc_fifo; i>0; i--) {
263 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
264 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO");
267 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
268 /* writeIntrThreshold reached */
269 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
271 /* if FIFO empty before the last byte, error */
272 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
273 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO");
278 /* FIFO must be empty after the last byte */
279 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
280 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO");
297 ppc_detect_port(struct ppc_data *ppc)
300 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
302 if (r_dtr(ppc) != 0xaa)
309 * EPP timeout, according to the PC87332 manual
310 * Semantics of clearing EPP timeout bit.
311 * PC87332 - reading SPP_STR does it...
312 * SMC - write 1 to EPP timeout bit XXX
313 * Others - (?) write 0 to EPP timeout bit
316 ppc_reset_epp_timeout(struct ppc_data *ppc)
322 w_str(ppc, r & 0xfe);
328 ppc_check_epp_timeout(struct ppc_data *ppc)
330 ppc_reset_epp_timeout(ppc);
332 return (!(r_str(ppc) & TIMEOUT));
336 * Configure current operating mode
339 ppc_generic_setmode(struct ppc_data *ppc, int mode)
343 /* check if mode is available */
344 if (mode && !(ppc->ppc_avm & mode))
347 /* if ECP mode, configure ecr register */
348 if (ppc->ppc_avm & PPB_ECP) {
349 /* return to byte mode (keeping direction bit),
350 * no interrupt, no DMA to be able to change to
353 w_ecr(ppc, PPC_ECR_RESET);
354 ecr = PPC_DISABLE_INTR;
358 else if (mode & PPB_ECP)
359 /* select ECP mode */
361 else if (mode & PPB_PS2)
362 /* select PS2 mode with ECP */
365 /* select COMPATIBLE/NIBBLE mode */
371 ppc->ppc_mode = mode;
377 * The ppc driver is free to choose options like FIFO or DMA
378 * if ECP mode is available.
380 * The 'RAW' option allows the upper drivers to force the ppc mode
381 * even with FIFO, DMA available.
384 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
388 /* check if mode is available */
389 if (mode && !(ppc->ppc_avm & mode))
392 /* if ECP mode, configure ecr register */
393 if (ppc->ppc_avm & PPB_ECP) {
394 /* return to byte mode (keeping direction bit),
395 * no interrupt, no DMA to be able to change to
398 w_ecr(ppc, PPC_ECR_RESET);
399 ecr = PPC_DISABLE_INTR;
402 /* select EPP mode */
404 else if (mode & PPB_ECP)
405 /* select ECP mode */
407 else if (mode & PPB_PS2)
408 /* select PS2 mode with ECP */
411 /* select COMPATIBLE/NIBBLE mode */
417 ppc->ppc_mode = mode;
422 #ifdef PPC_PROBE_CHIPSET
426 * Probe for a Natsemi PC873xx-family part.
428 * References in this function are to the National Semiconductor
429 * PC87332 datasheet TL/C/11930, May 1995 revision.
431 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
432 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
433 static int pc873xx_irqtab[] = {5, 7, 5, 0};
435 static int pc873xx_regstab[] = {
436 PC873_FER, PC873_FAR, PC873_PTR,
437 PC873_FCR, PC873_PCR, PC873_PMC,
438 PC873_TUP, PC873_SID, PC873_PNP0,
439 PC873_PNP1, PC873_LPTBA, -1
442 static char *pc873xx_rnametab[] = {
443 "FER", "FAR", "PTR", "FCR", "PCR",
444 "PMC", "TUP", "SID", "PNP0", "PNP1",
449 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
451 static int index = 0;
453 int ptr, pcr, val, i;
455 while ((idport = pc873xx_basetab[index++])) {
457 /* XXX should check first to see if this location is already claimed */
460 * Pull the 873xx through the power-on ID cycle (2.2,1.).
461 * We can't use this to locate the chip as it may already have
462 * been used by the BIOS.
464 (void)inb(idport); (void)inb(idport);
465 (void)inb(idport); (void)inb(idport);
468 * Read the SID byte. Possible values are :
474 outb(idport, PC873_SID);
475 val = inb(idport + 1);
476 if ((val & 0xf0) == 0x10) {
477 ppc->ppc_model = NS_PC87332;
478 } else if ((val & 0xf8) == 0x70) {
479 ppc->ppc_model = NS_PC87306;
480 } else if ((val & 0xf8) == 0x50) {
481 ppc->ppc_model = NS_PC87334;
483 if (bootverbose && (val != 0xff))
484 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
485 continue ; /* not recognised */
488 /* print registers */
491 for (i=0; pc873xx_regstab[i] != -1; i++) {
492 outb(idport, pc873xx_regstab[i]);
493 printf(" %s=0x%x", pc873xx_rnametab[i],
494 inb(idport + 1) & 0xff);
500 * We think we have one. Is it enabled and where we want it to be?
502 outb(idport, PC873_FER);
503 val = inb(idport + 1);
504 if (!(val & PC873_PPENABLE)) {
506 printf("PC873xx parallel port disabled\n");
509 outb(idport, PC873_FAR);
510 val = inb(idport + 1) & 0x3;
511 /* XXX we should create a driver instance for every port found */
512 if (pc873xx_porttab[val] != ppc->ppc_base) {
514 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
515 pc873xx_porttab[val], ppc->ppc_base);
519 outb(idport, PC873_PTR);
520 ptr = inb(idport + 1);
522 /* get irq settings */
523 if (ppc->ppc_base == 0x378)
524 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
526 irq = pc873xx_irqtab[val];
529 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
532 * Check if irq settings are correct
534 if (irq != ppc->ppc_irq) {
536 * If the chipset is not locked and base address is 0x378,
537 * we have another chance
539 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
540 if (ppc->ppc_irq == 7) {
541 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
542 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
544 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
545 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
548 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
551 printf("PC873xx sorry, can't change irq setting\n");
555 printf("PC873xx irq settings are correct\n");
558 outb(idport, PC873_PCR);
559 pcr = inb(idport + 1);
561 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
563 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
565 ppc->ppc_avm |= PPB_NIBBLE;
569 if (pcr & PC873_EPPEN) {
570 ppc->ppc_avm |= PPB_EPP;
575 if (pcr & PC873_EPP19)
576 ppc->ppc_epp = EPP_1_9;
578 ppc->ppc_epp = EPP_1_7;
580 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
581 outb(idport, PC873_PTR);
582 ptr = inb(idport + 1);
583 if (ptr & PC873_EPPRDIR)
584 printf(", Regular mode");
586 printf(", Automatic mode");
588 } else if (pcr & PC873_ECPEN) {
589 ppc->ppc_avm |= PPB_ECP;
593 if (pcr & PC873_ECPCLK) { /* XXX */
594 ppc->ppc_avm |= PPB_PS2;
599 outb(idport, PC873_PTR);
600 ptr = inb(idport + 1);
601 if (ptr & PC873_EXTENDED) {
602 ppc->ppc_avm |= PPB_SPP;
609 printf("PC873xx unlocked");
611 if (chipset_mode & PPB_ECP) {
612 if ((chipset_mode & PPB_EPP) && bootverbose)
613 printf(", ECP+EPP not supported");
616 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
617 outb(idport + 1, pcr);
618 outb(idport + 1, pcr);
623 } else if (chipset_mode & PPB_EPP) {
624 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
625 pcr |= (PC873_EPPEN | PC873_EPP19);
626 outb(idport + 1, pcr);
627 outb(idport + 1, pcr);
629 ppc->ppc_epp = EPP_1_9; /* XXX */
634 /* enable automatic direction turnover */
635 if (ppc->ppc_model == NS_PC87332) {
636 outb(idport, PC873_PTR);
637 ptr = inb(idport + 1);
638 ptr &= ~PC873_EPPRDIR;
639 outb(idport + 1, ptr);
640 outb(idport + 1, ptr);
643 printf(", Automatic mode");
646 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
647 outb(idport + 1, pcr);
648 outb(idport + 1, pcr);
650 /* configure extended bit in PTR */
651 outb(idport, PC873_PTR);
652 ptr = inb(idport + 1);
654 if (chipset_mode & PPB_PS2) {
655 ptr |= PC873_EXTENDED;
661 /* default to NIBBLE mode */
662 ptr &= ~PC873_EXTENDED;
667 outb(idport + 1, ptr);
668 outb(idport + 1, ptr);
671 ppc->ppc_avm = chipset_mode;
677 ppc->ppc_type = PPC_TYPE_GENERIC;
678 ppc_generic_setmode(ppc, chipset_mode);
680 return(chipset_mode);
686 * ppc_smc37c66xgt_detect
688 * SMC FDC37C66xGT configuration.
691 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
696 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
698 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
701 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
704 * Detection: enter configuration mode and read CRD register.
708 outb(csr, SMC665_iCODE);
709 outb(csr, SMC665_iCODE);
713 if (inb(cio) == 0x65) {
718 for (i = 0; i < 2; i++) {
720 outb(csr, SMC666_iCODE);
721 outb(csr, SMC666_iCODE);
725 if (inb(cio) == 0x66) {
730 /* Another chance, CSR may be hard-configured to be at 0x370 */
736 * If chipset not found, do not continue.
744 /* read the port's address: bits 0 and 1 of CR1 */
745 r = inb(cio) & SMC_CR1_ADDR;
746 if (port_address[(int)r] != ppc->ppc_base)
749 ppc->ppc_model = type;
752 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
753 * If SPP mode is detected, try to set ECP+EPP mode
758 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
762 printf(" CR4=0x%x", inb(cio) & 0xff);
769 /* autodetect mode */
771 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
772 if (type == SMC_37C666GT) {
773 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
775 printf(" configuration hardwired, supposing " \
779 if ((inb(cio) & SMC_CR1_MODE) == 0) {
780 /* already in extended parallel port mode, read CR4 */
782 r = (inb(cio) & SMC_CR4_EMODE);
786 ppc->ppc_avm |= PPB_SPP;
792 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
798 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
804 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
806 printf(" ECP+EPP SPP");
810 /* not an extended port mode */
811 ppc->ppc_avm |= PPB_SPP;
818 ppc->ppc_avm = chipset_mode;
820 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
821 if (type == SMC_37C666GT)
825 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
826 /* do not use ECP when the mode is not forced to */
827 outb(cio, r | SMC_CR1_MODE);
831 /* an extended mode is selected */
832 outb(cio, r & ~SMC_CR1_MODE);
834 /* read CR4 register and reset mode field */
836 r = inb(cio) & ~SMC_CR4_EMODE;
838 if (chipset_mode & PPB_ECP) {
839 if (chipset_mode & PPB_EPP) {
840 outb(cio, r | SMC_ECPEPP);
844 outb(cio, r | SMC_ECP);
850 outb(cio, r | SMC_EPPSPP);
855 ppc->ppc_avm = chipset_mode;
858 /* set FIFO threshold to 16 */
859 if (ppc->ppc_avm & PPB_ECP) {
870 if (ppc->ppc_avm & PPB_EPP) {
876 * Set the EPP protocol...
877 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
879 if (ppc->ppc_epp == EPP_1_9)
880 outb(cio, (r & ~SMC_CR4_EPPTYPE));
882 outb(cio, (r | SMC_CR4_EPPTYPE));
885 /* end config mode */
888 ppc->ppc_type = PPC_TYPE_SMCLIKE;
889 ppc_smclike_setmode(ppc, chipset_mode);
891 return (chipset_mode);
895 * Winbond W83877F stuff
897 * EFER: extended function enable register
898 * EFIR: extended function index register
899 * EFDR: extended function data register
901 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
902 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
904 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
905 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
906 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
907 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
910 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
913 unsigned char r, hefere, hefras;
915 for (i = 0; i < 4; i ++) {
916 /* first try to enable configuration registers */
917 efer = w83877f_efers[i];
919 /* write the key to the EFER */
920 for (j = 0; j < w83877f_keyiter[i]; j ++)
921 outb (efer, w83877f_keys[i]);
923 /* then check HEFERE and HEFRAS bits */
925 hefere = inb(efdr) & WINB_HEFERE;
928 hefras = inb(efdr) & WINB_HEFRAS;
932 * 0 1 write 89h to 250h (power-on default)
933 * 1 0 write 86h twice to 3f0h
934 * 1 1 write 87h twice to 3f0h
935 * 0 0 write 88h to 250h
937 if ((hefere | hefras) == w83877f_hefs[i])
941 return (-1); /* failed */
944 /* check base port address - read from CR23 */
946 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
949 /* read CHIP ID from CR9/bits0-3 */
952 switch (inb(efdr) & WINB_CHIPID) {
953 case WINB_W83877F_ID:
954 ppc->ppc_model = WINB_W83877F;
957 case WINB_W83877AF_ID:
958 ppc->ppc_model = WINB_W83877AF;
962 ppc->ppc_model = WINB_UNKNOWN;
966 /* dump of registers */
967 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
968 for (i = 0; i <= 0xd; i ++) {
970 printf("0x%x ", inb(efdr));
972 for (i = 0x10; i <= 0x17; i ++) {
974 printf("0x%x ", inb(efdr));
977 printf("0x%x ", inb(efdr));
978 for (i = 0x20; i <= 0x29; i ++) {
980 printf("0x%x ", inb(efdr));
983 printf("ppc%d:", ppc->ppc_unit);
986 ppc->ppc_type = PPC_TYPE_GENERIC;
989 /* autodetect mode */
993 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
997 r |= (inb(efdr) & WINB_PRTMODS2);
1002 printf("ppc%d: W83757 compatible mode\n",
1004 return (-1); /* generic or SMC-like */
1011 printf(" not in parallel port mode\n");
1014 case (WINB_PARALLEL | WINB_EPP_SPP):
1015 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1020 case (WINB_PARALLEL | WINB_ECP):
1021 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1026 case (WINB_PARALLEL | WINB_ECP_EPP):
1027 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1028 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1031 printf(" ECP+EPP SPP");
1034 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r);
1040 /* select CR9 and set PRTMODS2 bit */
1042 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1044 /* select CR0 and reset PRTMODSx bits */
1046 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1048 if (chipset_mode & PPB_ECP) {
1049 if (chipset_mode & PPB_EPP) {
1050 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1054 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1057 outb(efdr, inb(efdr) | WINB_ECP);
1062 /* select EPP_SPP otherwise */
1063 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1067 ppc->ppc_avm = chipset_mode;
1073 /* exit configuration mode */
1076 switch (ppc->ppc_type) {
1077 case PPC_TYPE_SMCLIKE:
1078 ppc_smclike_setmode(ppc, chipset_mode);
1081 ppc_generic_setmode(ppc, chipset_mode);
1085 return (chipset_mode);
1090 * ppc_generic_detect
1093 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1095 /* default to generic */
1096 ppc->ppc_type = PPC_TYPE_GENERIC;
1099 printf("ppc%d:", ppc->ppc_unit);
1101 if (!chipset_mode) {
1102 /* first, check for ECP */
1103 w_ecr(ppc, PPC_ECR_PS2);
1104 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1105 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1109 /* search for SMC style ECP+EPP mode */
1110 w_ecr(ppc, PPC_ECR_EPP);
1113 /* try to reset EPP timeout bit */
1114 if (ppc_check_epp_timeout(ppc)) {
1115 ppc->ppc_avm |= PPB_EPP;
1117 if (ppc->ppc_avm & PPB_ECP) {
1118 /* SMC like chipset found */
1119 ppc->ppc_model = SMC_LIKE;
1120 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1129 /* restore to standard mode */
1130 w_ecr(ppc, PPC_ECR_STD);
1133 /* XXX try to detect NIBBLE and PS2 modes */
1134 ppc->ppc_avm |= PPB_NIBBLE;
1140 ppc->ppc_avm = chipset_mode;
1146 switch (ppc->ppc_type) {
1147 case PPC_TYPE_SMCLIKE:
1148 ppc_smclike_setmode(ppc, chipset_mode);
1151 ppc_generic_setmode(ppc, chipset_mode);
1155 return (chipset_mode);
1161 * mode is the mode suggested at boot
1164 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1166 #ifdef PPC_PROBE_CHIPSET
1169 /* list of supported chipsets */
1170 int (*chipset_detect[])(struct ppc_data *, int) = {
1172 ppc_smc37c66xgt_detect,
1179 /* if can't find the port and mode not forced return error */
1180 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1181 return (EIO); /* failed, port not present */
1183 /* assume centronics compatible mode is supported */
1184 ppc->ppc_avm = PPB_COMPATIBLE;
1186 #ifdef PPC_PROBE_CHIPSET
1187 /* we have to differenciate available chipset modes,
1188 * chipset running modes and IEEE-1284 operating modes
1190 * after detection, the port must support running in compatible mode
1192 if (ppc->ppc_flags & 0x40) {
1194 printf("ppc: chipset forced to generic\n");
1197 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1199 #ifdef PPC_PROBE_CHIPSET
1201 for (i=0; chipset_detect[i] != NULL; i++) {
1202 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1203 ppc->ppc_mode = mode;
1210 /* configure/detect ECP FIFO */
1211 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1212 ppc_detect_fifo(ppc);
1218 * ppc_exec_microseq()
1220 * Execute a microsequence.
1221 * Microsequence mechanism is supposed to handle fast I/O operations.
1224 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1226 struct ppc_data *ppc = DEVTOSOFTC(dev);
1227 struct ppb_microseq *mi;
1234 register int accum = 0;
1235 register char *ptr = 0;
1237 struct ppb_microseq *stack = 0;
1239 /* microsequence registers are equivalent to PC-like port registers */
1240 #define r_reg(register,ppc) (inb((ppc)->ppc_base + register))
1241 #define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte)
1243 #define INCR_PC (mi ++) /* increment program counter */
1247 switch (mi->opcode) {
1249 cc = r_reg(mi->arg[0].i, ppc);
1250 cc &= (char)mi->arg[2].i; /* clear mask */
1251 cc |= (char)mi->arg[1].i; /* assert mask */
1252 w_reg(mi->arg[0].i, ppc, cc);
1256 case MS_OP_RASSERT_P:
1260 if ((len = mi->arg[0].i) == MS_ACCUM) {
1261 accum = ppc->ppc_accum;
1262 for (; accum; accum--)
1263 w_reg(reg, ppc, *ptr++);
1264 ppc->ppc_accum = accum;
1266 for (i=0; i<len; i++)
1267 w_reg(reg, ppc, *ptr++);
1273 case MS_OP_RFETCH_P:
1275 mask = (char)mi->arg[2].i;
1278 if ((len = mi->arg[0].i) == MS_ACCUM) {
1279 accum = ppc->ppc_accum;
1280 for (; accum; accum--)
1281 *ptr++ = r_reg(reg, ppc) & mask;
1282 ppc->ppc_accum = accum;
1284 for (i=0; i<len; i++)
1285 *ptr++ = r_reg(reg, ppc) & mask;
1292 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1300 /* let's suppose the next instr. is the same */
1302 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1303 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1305 if (mi->opcode == MS_OP_DELAY) {
1306 DELAY(mi->arg[0].i);
1314 tsleep(NULL, PPBPRI, "ppbdelay",
1315 mi->arg[0].i * (hz/1000));
1321 iter = mi->arg[1].i;
1322 p = (char *)mi->arg[2].p;
1324 /* XXX delay limited to 255 us */
1325 for (i=0; i<iter; i++) {
1326 w_reg(reg, ppc, *p++);
1327 DELAY((unsigned char)*p++);
1333 ppc->ppc_accum = mi->arg[0].i;
1338 if (--ppc->ppc_accum > 0)
1345 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1352 if ((cc & (char)mi->arg[0].i) == 0)
1359 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1367 * If the C call returns !0 then end the microseq.
1368 * The current state of ptr is passed to the C function
1370 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1377 ppc->ppc_ptr = (char *)mi->arg[0].p;
1383 panic("%s: too much calls", __FUNCTION__);
1386 /* store the state of the actual
1391 /* jump to the new microsequence */
1392 mi = (struct ppb_microseq *)mi->arg[0].p;
1399 /* retrieve microseq and pc state before the call */
1402 /* reset the stack */
1405 /* XXX return code */
1413 /* can't return to ppb level during the execution
1414 * of a submicrosequence */
1416 panic("%s: can't return to ppb level",
1419 /* update pc for ppb level of execution */
1422 /* return to ppb level of execution */
1426 panic("%s: unknown microsequence opcode 0x%x",
1427 __FUNCTION__, mi->opcode);
1437 device_t dev = (device_t)arg;
1438 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1439 u_char ctr, ecr, str;
1446 printf("![%x/%x/%x]", ctr, ecr, str);
1449 /* don't use ecp mode with IRQENABLE set */
1450 if (ctr & IRQENABLE) {
1454 /* interrupts are generated by nFault signal
1455 * only in ECP mode */
1456 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1457 /* check if ppc driver has programmed the
1458 * nFault interrupt */
1459 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1461 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1462 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1464 /* shall be handled by underlying layers XXX */
1469 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1470 /* disable interrupts (should be done by hardware though) */
1471 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1472 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1475 /* check if DMA completed */
1476 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1481 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1484 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1494 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1496 /* wakeup the waiting process */
1497 wakeup((caddr_t)ppc);
1500 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1502 /* classic interrupt I/O */
1503 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1510 ppc_read(device_t dev, char *buf, int len, int mode)
1516 * Call this function if you want to send data in any advanced mode
1517 * of your parallel port: FIFO, DMA
1519 * If what you want is not possible (no ECP, no DMA...),
1520 * EINVAL is returned
1523 ppc_write(device_t dev, char *buf, int len, int how)
1525 struct ppc_data *ppc = DEVTOSOFTC(dev);
1526 char ecr, ecr_sav, ctr, ctr_sav;
1534 ecr_sav = r_ecr(ppc);
1535 ctr_sav = r_ctr(ppc);
1538 * Send buffer with DMA, FIFO and interrupts
1540 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1542 if (ppc->ppc_dmachan >= 0) {
1544 /* byte mode, no intr, no DMA, dir=0, flush fifo
1546 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1549 /* disable nAck interrupts */
1554 ppc->ppc_dmaflags = 0;
1555 ppc->ppc_dmaddr = (caddr_t)buf;
1556 ppc->ppc_dmacnt = (u_int)len;
1558 switch (ppc->ppc_mode) {
1559 case PPB_COMPATIBLE:
1560 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1561 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1564 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1574 /* enter splhigh() not to be preempted
1575 * by the dma interrupt, we may miss
1576 * the wakeup otherwise
1580 ppc->ppc_dmastat = PPC_DMA_INIT;
1582 /* enable interrupts */
1583 ecr &= ~PPC_SERVICE_INTR;
1584 ppc->ppc_irqstat = PPC_IRQ_DMA;
1593 printf("s%d", ppc->ppc_dmacnt);
1595 ppc->ppc_dmastat = PPC_DMA_STARTED;
1597 /* Wait for the DMA completed interrupt. We hope we won't
1598 * miss it, otherwise a signal will be necessary to unlock the
1603 error = tsleep((caddr_t)ppc,
1604 PPBPRI | PCATCH, "ppcdma", 0);
1606 } while (error == EWOULDBLOCK);
1616 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1617 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1619 /* no dma, no interrupt, flush the fifo */
1620 w_ecr(ppc, PPC_ECR_RESET);
1622 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1626 /* wait for an empty fifo */
1627 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1629 for (spin=100; spin; spin--)
1630 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1635 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1636 if (error != EWOULDBLOCK) {
1640 /* no dma, no interrupt, flush the fifo */
1641 w_ecr(ppc, PPC_ECR_RESET);
1643 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1650 /* no dma, no interrupt, flush the fifo */
1651 w_ecr(ppc, PPC_ECR_RESET);
1654 error = EINVAL; /* XXX we should FIFO and
1661 /* PDRQ must be kept unasserted until nPDACK is
1662 * deasserted for a minimum of 350ns (SMC datasheet)
1664 * Consequence may be a FIFO that never empty
1668 w_ecr(ppc, ecr_sav);
1669 w_ctr(ppc, ctr_sav);
1675 ppc_reset_epp(device_t dev)
1677 struct ppc_data *ppc = DEVTOSOFTC(dev);
1679 ppc_reset_epp_timeout(ppc);
1685 ppc_setmode(device_t dev, int mode)
1687 struct ppc_data *ppc = DEVTOSOFTC(dev);
1689 switch (ppc->ppc_type) {
1690 case PPC_TYPE_SMCLIKE:
1691 return (ppc_smclike_setmode(ppc, mode));
1694 case PPC_TYPE_GENERIC:
1696 return (ppc_generic_setmode(ppc, mode));
1705 ppc_probe(device_t dev)
1707 static short next_bios_ppc = 0;
1708 struct ppc_data *ppc;
1712 #define PC98_IEEE_1284_DISABLE 0x100
1713 #define PC98_IEEE_1284_PORT 0x140
1715 unsigned int pc98_ieee_mode = 0x00;
1719 /* If we are a PNP device, abort. Otherwise we attach to *everthing* */
1720 if (isa_get_logicalid(dev))
1723 parent = device_get_parent(dev);
1725 /* XXX shall be set after detection */
1726 device_set_desc(dev, "Parallel port");
1729 * Allocate the ppc_data structure.
1731 ppc = DEVTOSOFTC(dev);
1732 bzero(ppc, sizeof(struct ppc_data));
1734 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1735 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1737 /* retrieve ISA parameters */
1738 BUS_READ_IVAR(parent, dev, ISA_IVAR_PORT, &port);
1741 * If port not specified, use bios list.
1745 if((next_bios_ppc < BIOS_MAX_PPC) &&
1746 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1747 port = *(BIOS_PORTS+next_bios_ppc++);
1749 device_printf(dev, "parallel port found at 0x%x\n",
1752 device_printf(dev, "parallel port not found.\n");
1756 if (next_bios_ppc == 0) {
1757 /* Use default IEEE-1284 port of NEC PC-98x1 */
1758 port = PC98_IEEE_1284_PORT;
1761 device_printf(dev, "parallel port found at 0x%x\n",
1766 ppc->ppc_base = port;
1768 /* IO port is mandatory */
1769 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1770 &ppc->rid_ioport, port, port,
1771 IO_LPTSIZE, RF_ACTIVE);
1772 if (ppc->res_ioport == 0) {
1773 device_printf(dev, "cannot reserve I/O port range\n");
1777 ppc->ppc_flags = device_get_flags(dev);
1779 if (!(ppc->ppc_flags & 0x20)) {
1780 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1781 0ul, ~0ul, 1, RF_SHAREABLE);
1782 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1783 0ul, ~0ul, 1, RF_ACTIVE);
1787 BUS_READ_IVAR(parent, dev, ISA_IVAR_IRQ, &ppc->ppc_irq);
1789 BUS_READ_IVAR(parent, dev, ISA_IVAR_DRQ, &ppc->ppc_dmachan);
1791 ppc->ppc_unit = device_get_unit(dev);
1792 ppc->ppc_model = GENERIC;
1794 ppc->ppc_mode = PPB_COMPATIBLE;
1795 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1797 ppc->ppc_type = PPC_TYPE_GENERIC;
1801 * IEEE STD 1284 Function Check and Enable
1802 * for default IEEE-1284 port of NEC PC-98x1
1804 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1805 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1806 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1807 pc98_ieee_mode = tmp;
1808 if ((tmp & 0x10) == 0x10) {
1809 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1810 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1811 if ((tmp & 0x10) == 0x10)
1814 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1815 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1816 if ((tmp & 0x10) != 0x10)
1819 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1824 * Try to detect the chipset and its mode.
1826 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1833 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1834 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1835 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1838 if (ppc->res_irq != 0) {
1839 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1842 if (ppc->res_ioport != 0) {
1843 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1845 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1848 if (ppc->res_drq != 0) {
1849 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1851 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1858 ppc_attach(device_t dev)
1860 struct ppc_data *ppc = DEVTOSOFTC(dev);
1863 device_t parent = device_get_parent(dev);
1865 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1866 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1867 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1868 ppc_epp_protocol[ppc->ppc_epp] : "");
1871 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1872 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1874 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1875 /* acquire the DMA channel forever */ /* XXX */
1876 isa_dma_acquire(ppc->ppc_dmachan);
1877 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1880 /* add ppbus as a child of this isa to parallel bridge */
1881 ppbus = device_add_child(dev, "ppbus", -1);
1884 * Probe the ppbus and attach devices found.
1886 device_probe_and_attach(ppbus);
1888 /* register the ppc interrupt handler as default */
1890 /* default to the tty mask for registration */ /* XXX */
1891 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY,
1892 ppcintr, dev, &ppc->intr_cookie) == 0) {
1894 /* remember the ppcintr is registered */
1895 ppc->ppc_registered = 1;
1903 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1905 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1908 outsb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1911 outsw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1914 outsl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1917 insb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1920 insw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1923 insl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1926 return (r_dtr(ppc));
1929 return (r_str(ppc));
1932 return (r_ctr(ppc));
1935 return (r_epp_A(ppc));
1938 return (r_epp_D(ppc));
1941 return (r_ecr(ppc));
1944 return (r_fifo(ppc));
1968 panic("%s: unknown I/O operation", __FUNCTION__);
1972 return (0); /* not significative */
1976 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1978 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1981 case PPC_IVAR_EPP_PROTO:
1982 *val = (u_long)ppc->ppc_epp;
1985 BUS_READ_IVAR(device_get_parent(bus), bus, ISA_IVAR_IRQ, val);
1995 * Resource is useless here since ppbus devices' interrupt handlers are
1996 * multiplexed to the same resource initially allocated by ppc
1999 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2000 void (*ihand)(void *), void *arg, void **cookiep)
2003 struct ppc_data *ppc = DEVTOSOFTC(bus);
2005 if (ppc->ppc_registered) {
2006 /* XXX refuse registration if DMA is in progress */
2008 /* first, unregister the default interrupt handler */
2009 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2010 bus, ppc->res_irq, ppc->intr_cookie)))
2013 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2014 /* ppc->res_irq); */
2016 /* DMA/FIFO operation won't be possible anymore */
2017 ppc->ppc_registered = 0;
2020 /* pass registration to the upper layer, ignore the incoming resource */
2021 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2022 r, flags, ihand, arg, cookiep));
2026 * When no underlying device has a registered interrupt, register the ppc
2030 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2033 struct ppc_data *ppc = DEVTOSOFTC(bus);
2034 device_t parent = device_get_parent(bus);
2036 /* pass unregistration to the upper layer */
2037 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2040 /* default to the tty mask for registration */ /* XXX */
2042 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2043 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) {
2045 /* remember the ppcintr is registered */
2046 ppc->ppc_registered = 1;
2052 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);