2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/vmparam.h>
47 #include <pc98/cbus/cbus.h>
49 #include <isa/isareg.h>
51 #include <isa/isavar.h>
53 #include <dev/ppbus/ppbconf.h>
54 #include <dev/ppbus/ppb_msq.h>
56 #include <dev/ppc/ppcvar.h>
58 #include <pc98/cbus/ppcreg.h>
60 #include <dev/ppc/ppcreg.h>
65 static int ppc_cbus_probe(device_t dev);
67 static void ppcintr(void *arg);
69 #define LOG_PPC(function, ppc, string) \
70 if (bootverbose) printf("%s: %s\n", function, string)
73 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
75 devclass_t ppc_devclass;
77 static device_method_t ppc_methods[] = {
78 /* device interface */
79 DEVMETHOD(device_probe, ppc_cbus_probe),
80 DEVMETHOD(device_attach, ppc_attach),
83 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
84 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
85 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
86 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
89 DEVMETHOD(ppbus_io, ppc_io),
90 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
91 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
92 DEVMETHOD(ppbus_setmode, ppc_setmode),
93 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
94 DEVMETHOD(ppbus_read, ppc_read),
95 DEVMETHOD(ppbus_write, ppc_write),
100 static driver_t ppc_driver = {
103 sizeof(struct ppc_data),
106 static char *ppc_models[] = {
107 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
108 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
109 "SMC FDC37C935", "PC87303", 0
112 /* list of available modes */
113 static char *ppc_avms[] = {
114 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
115 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
116 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
117 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
120 /* list of current executing modes
121 * Note that few modes do not actually exist.
123 static char *ppc_modes[] = {
124 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
125 "EPP", "EPP", "EPP", "ECP",
126 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
127 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
130 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
134 * BIOS printer list - used by BIOS probe.
136 #define BIOS_PPC_PORTS 0x408
137 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
138 #define BIOS_MAX_PPC 4
145 ppc_ecp_sync(device_t dev) {
148 struct ppc_data *ppc = DEVTOSOFTC(dev);
150 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
154 if ((r & 0xe0) != PPC_ECR_EPP)
157 for (i = 0; i < 100; i++) {
164 printf("ppc%d: ECP sync failed as data still " \
165 "present in FIFO.\n", ppc->ppc_unit);
173 * Detect parallel port FIFO
176 ppc_detect_fifo(struct ppc_data *ppc)
179 char ctr_sav, ctr, cc;
183 ecr_sav = r_ecr(ppc);
184 ctr_sav = r_ctr(ppc);
186 /* enter ECP configuration mode, no interrupt, no DMA */
189 /* read PWord size - transfers in FIFO mode must be PWord aligned */
190 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
192 /* XXX 16 and 32 bits implementations not supported */
193 if (ppc->ppc_pword != PPC_PWORD_8) {
194 LOG_PPC(__func__, ppc, "PWord not supported");
198 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
200 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
202 /* enter ECP test mode, no interrupt, no DMA */
206 for (i=0; i<1024; i++) {
207 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
213 LOG_PPC(__func__, ppc, "can't flush FIFO");
217 /* enable interrupts, no DMA */
220 /* determine readIntrThreshold
221 * fill the FIFO until serviceIntr is set
223 for (i=0; i<1024; i++) {
224 w_fifo(ppc, (char)i);
225 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
226 /* readThreshold reached */
229 if (r_ecr(ppc) & PPC_FIFO_FULL) {
236 LOG_PPC(__func__, ppc, "can't fill FIFO");
240 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
241 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
242 w_ecr(ppc, 0xd0); /* enable interrupts */
244 /* determine writeIntrThreshold
245 * empty the FIFO until serviceIntr is set
247 for (i=ppc->ppc_fifo; i>0; i--) {
248 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
249 LOG_PPC(__func__, ppc, "invalid data in FIFO");
252 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
253 /* writeIntrThreshold reached */
254 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
256 /* if FIFO empty before the last byte, error */
257 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
258 LOG_PPC(__func__, ppc, "data lost in FIFO");
263 /* FIFO must be empty after the last byte */
264 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
265 LOG_PPC(__func__, ppc, "can't empty the FIFO");
282 ppc_detect_port(struct ppc_data *ppc)
285 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
287 if (r_dtr(ppc) != 0xaa)
294 * EPP timeout, according to the PC87332 manual
295 * Semantics of clearing EPP timeout bit.
296 * PC87332 - reading SPP_STR does it...
297 * SMC - write 1 to EPP timeout bit XXX
298 * Others - (?) write 0 to EPP timeout bit
301 ppc_reset_epp_timeout(struct ppc_data *ppc)
307 w_str(ppc, r & 0xfe);
313 ppc_check_epp_timeout(struct ppc_data *ppc)
315 ppc_reset_epp_timeout(ppc);
317 return (!(r_str(ppc) & TIMEOUT));
321 * Configure current operating mode
324 ppc_generic_setmode(struct ppc_data *ppc, int mode)
328 /* check if mode is available */
329 if (mode && !(ppc->ppc_avm & mode))
332 /* if ECP mode, configure ecr register */
333 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
334 /* return to byte mode (keeping direction bit),
335 * no interrupt, no DMA to be able to change to
338 w_ecr(ppc, PPC_ECR_RESET);
339 ecr = PPC_DISABLE_INTR;
343 else if (mode & PPB_ECP)
344 /* select ECP mode */
346 else if (mode & PPB_PS2)
347 /* select PS2 mode with ECP */
350 /* select COMPATIBLE/NIBBLE mode */
356 ppc->ppc_mode = mode;
362 * The ppc driver is free to choose options like FIFO or DMA
363 * if ECP mode is available.
365 * The 'RAW' option allows the upper drivers to force the ppc mode
366 * even with FIFO, DMA available.
369 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
373 /* check if mode is available */
374 if (mode && !(ppc->ppc_avm & mode))
377 /* if ECP mode, configure ecr register */
378 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
379 /* return to byte mode (keeping direction bit),
380 * no interrupt, no DMA to be able to change to
383 w_ecr(ppc, PPC_ECR_RESET);
384 ecr = PPC_DISABLE_INTR;
387 /* select EPP mode */
389 else if (mode & PPB_ECP)
390 /* select ECP mode */
392 else if (mode & PPB_PS2)
393 /* select PS2 mode with ECP */
396 /* select COMPATIBLE/NIBBLE mode */
402 ppc->ppc_mode = mode;
407 #ifdef PPC_PROBE_CHIPSET
411 * Probe for a Natsemi PC873xx-family part.
413 * References in this function are to the National Semiconductor
414 * PC87332 datasheet TL/C/11930, May 1995 revision.
416 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
417 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
418 static int pc873xx_irqtab[] = {5, 7, 5, 0};
420 static int pc873xx_regstab[] = {
421 PC873_FER, PC873_FAR, PC873_PTR,
422 PC873_FCR, PC873_PCR, PC873_PMC,
423 PC873_TUP, PC873_SID, PC873_PNP0,
424 PC873_PNP1, PC873_LPTBA, -1
427 static char *pc873xx_rnametab[] = {
428 "FER", "FAR", "PTR", "FCR", "PCR",
429 "PMC", "TUP", "SID", "PNP0", "PNP1",
434 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
436 static int index = 0;
438 int ptr, pcr, val, i;
440 while ((idport = pc873xx_basetab[index++])) {
442 /* XXX should check first to see if this location is already claimed */
445 * Pull the 873xx through the power-on ID cycle (2.2,1.).
446 * We can't use this to locate the chip as it may already have
447 * been used by the BIOS.
449 (void)inb(idport); (void)inb(idport);
450 (void)inb(idport); (void)inb(idport);
453 * Read the SID byte. Possible values are :
460 outb(idport, PC873_SID);
461 val = inb(idport + 1);
462 if ((val & 0xf0) == 0x10) {
463 ppc->ppc_model = NS_PC87332;
464 } else if ((val & 0xf8) == 0x70) {
465 ppc->ppc_model = NS_PC87306;
466 } else if ((val & 0xf8) == 0x50) {
467 ppc->ppc_model = NS_PC87334;
468 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
469 documentation, but probing
471 ppc->ppc_model = NS_PC87303;
473 if (bootverbose && (val != 0xff))
474 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
475 continue ; /* not recognised */
478 /* print registers */
481 for (i=0; pc873xx_regstab[i] != -1; i++) {
482 outb(idport, pc873xx_regstab[i]);
483 printf(" %s=0x%x", pc873xx_rnametab[i],
484 inb(idport + 1) & 0xff);
490 * We think we have one. Is it enabled and where we want it to be?
492 outb(idport, PC873_FER);
493 val = inb(idport + 1);
494 if (!(val & PC873_PPENABLE)) {
496 printf("PC873xx parallel port disabled\n");
499 outb(idport, PC873_FAR);
500 val = inb(idport + 1);
501 /* XXX we should create a driver instance for every port found */
502 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
504 /* First try to change the port address to that requested... */
506 switch(ppc->ppc_base) {
524 outb(idport, PC873_FAR);
525 outb(idport + 1, val);
526 outb(idport + 1, val);
528 /* Check for success by reading back the value we supposedly
529 wrote and comparing...*/
531 outb(idport, PC873_FAR);
532 val = inb(idport + 1) & 0x3;
534 /* If we fail, report the failure... */
536 if (pc873xx_porttab[val] != ppc->ppc_base) {
538 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
539 pc873xx_porttab[val], ppc->ppc_base);
544 outb(idport, PC873_PTR);
545 ptr = inb(idport + 1);
547 /* get irq settings */
548 if (ppc->ppc_base == 0x378)
549 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
551 irq = pc873xx_irqtab[val];
554 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
557 * Check if irq settings are correct
559 if (irq != ppc->ppc_irq) {
561 * If the chipset is not locked and base address is 0x378,
562 * we have another chance
564 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
565 if (ppc->ppc_irq == 7) {
566 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
567 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
569 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
570 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
573 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
576 printf("PC873xx sorry, can't change irq setting\n");
580 printf("PC873xx irq settings are correct\n");
583 outb(idport, PC873_PCR);
584 pcr = inb(idport + 1);
586 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
588 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
590 ppc->ppc_avm |= PPB_NIBBLE;
594 if (pcr & PC873_EPPEN) {
595 ppc->ppc_avm |= PPB_EPP;
600 if (pcr & PC873_EPP19)
601 ppc->ppc_epp = EPP_1_9;
603 ppc->ppc_epp = EPP_1_7;
605 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
606 outb(idport, PC873_PTR);
607 ptr = inb(idport + 1);
608 if (ptr & PC873_EPPRDIR)
609 printf(", Regular mode");
611 printf(", Automatic mode");
613 } else if (pcr & PC873_ECPEN) {
614 ppc->ppc_avm |= PPB_ECP;
618 if (pcr & PC873_ECPCLK) { /* XXX */
619 ppc->ppc_avm |= PPB_PS2;
624 outb(idport, PC873_PTR);
625 ptr = inb(idport + 1);
626 if (ptr & PC873_EXTENDED) {
627 ppc->ppc_avm |= PPB_SPP;
634 printf("PC873xx unlocked");
636 if (chipset_mode & PPB_ECP) {
637 if ((chipset_mode & PPB_EPP) && bootverbose)
638 printf(", ECP+EPP not supported");
641 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
642 outb(idport + 1, pcr);
643 outb(idport + 1, pcr);
648 } else if (chipset_mode & PPB_EPP) {
649 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
650 pcr |= (PC873_EPPEN | PC873_EPP19);
651 outb(idport + 1, pcr);
652 outb(idport + 1, pcr);
654 ppc->ppc_epp = EPP_1_9; /* XXX */
659 /* enable automatic direction turnover */
660 if (ppc->ppc_model == NS_PC87332) {
661 outb(idport, PC873_PTR);
662 ptr = inb(idport + 1);
663 ptr &= ~PC873_EPPRDIR;
664 outb(idport + 1, ptr);
665 outb(idport + 1, ptr);
668 printf(", Automatic mode");
671 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
672 outb(idport + 1, pcr);
673 outb(idport + 1, pcr);
675 /* configure extended bit in PTR */
676 outb(idport, PC873_PTR);
677 ptr = inb(idport + 1);
679 if (chipset_mode & PPB_PS2) {
680 ptr |= PC873_EXTENDED;
686 /* default to NIBBLE mode */
687 ptr &= ~PC873_EXTENDED;
692 outb(idport + 1, ptr);
693 outb(idport + 1, ptr);
696 ppc->ppc_avm = chipset_mode;
702 ppc->ppc_type = PPC_TYPE_GENERIC;
703 ppc_generic_setmode(ppc, chipset_mode);
705 return(chipset_mode);
711 * ppc_smc37c66xgt_detect
713 * SMC FDC37C66xGT configuration.
716 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
721 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
723 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
726 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
729 * Detection: enter configuration mode and read CRD register.
733 outb(csr, SMC665_iCODE);
734 outb(csr, SMC665_iCODE);
738 if (inb(cio) == 0x65) {
743 for (i = 0; i < 2; i++) {
745 outb(csr, SMC666_iCODE);
746 outb(csr, SMC666_iCODE);
750 if (inb(cio) == 0x66) {
755 /* Another chance, CSR may be hard-configured to be at 0x370 */
761 * If chipset not found, do not continue.
769 /* read the port's address: bits 0 and 1 of CR1 */
770 r = inb(cio) & SMC_CR1_ADDR;
771 if (port_address[(int)r] != ppc->ppc_base)
774 ppc->ppc_model = type;
777 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
778 * If SPP mode is detected, try to set ECP+EPP mode
783 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
787 printf(" CR4=0x%x", inb(cio) & 0xff);
794 /* autodetect mode */
796 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
797 if (type == SMC_37C666GT) {
798 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
800 printf(" configuration hardwired, supposing " \
804 if ((inb(cio) & SMC_CR1_MODE) == 0) {
805 /* already in extended parallel port mode, read CR4 */
807 r = (inb(cio) & SMC_CR4_EMODE);
811 ppc->ppc_avm |= PPB_SPP;
817 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
823 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
829 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
831 printf(" ECP+EPP SPP");
835 /* not an extended port mode */
836 ppc->ppc_avm |= PPB_SPP;
843 ppc->ppc_avm = chipset_mode;
845 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
846 if (type == SMC_37C666GT)
850 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
851 /* do not use ECP when the mode is not forced to */
852 outb(cio, r | SMC_CR1_MODE);
856 /* an extended mode is selected */
857 outb(cio, r & ~SMC_CR1_MODE);
859 /* read CR4 register and reset mode field */
861 r = inb(cio) & ~SMC_CR4_EMODE;
863 if (chipset_mode & PPB_ECP) {
864 if (chipset_mode & PPB_EPP) {
865 outb(cio, r | SMC_ECPEPP);
869 outb(cio, r | SMC_ECP);
875 outb(cio, r | SMC_EPPSPP);
880 ppc->ppc_avm = chipset_mode;
883 /* set FIFO threshold to 16 */
884 if (ppc->ppc_avm & PPB_ECP) {
895 if (ppc->ppc_avm & PPB_EPP) {
901 * Set the EPP protocol...
902 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
904 if (ppc->ppc_epp == EPP_1_9)
905 outb(cio, (r & ~SMC_CR4_EPPTYPE));
907 outb(cio, (r | SMC_CR4_EPPTYPE));
910 /* end config mode */
913 ppc->ppc_type = PPC_TYPE_SMCLIKE;
914 ppc_smclike_setmode(ppc, chipset_mode);
916 return (chipset_mode);
920 * SMC FDC37C935 configuration
921 * Found on many Alpha machines
924 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
930 outb(SMC935_CFG, 0x55); /* enter config mode */
931 outb(SMC935_CFG, 0x55);
934 outb(SMC935_IND, SMC935_ID); /* check device id */
935 if (inb(SMC935_DAT) == 0x2)
939 outb(SMC935_CFG, 0xaa); /* exit config mode */
943 ppc->ppc_model = type;
945 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
946 outb(SMC935_DAT, 3); /* which is logical device 3 */
948 /* set io port base */
949 outb(SMC935_IND, SMC935_PORTHI);
950 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
951 outb(SMC935_IND, SMC935_PORTLO);
952 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
955 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
957 ppc->ppc_avm = chipset_mode;
958 outb(SMC935_IND, SMC935_PPMODE);
959 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
961 /* SPP + EPP or just plain SPP */
962 if (chipset_mode & (PPB_SPP)) {
963 if (chipset_mode & PPB_EPP) {
964 if (ppc->ppc_epp == EPP_1_9) {
965 outb(SMC935_IND, SMC935_PPMODE);
966 outb(SMC935_DAT, SMC935_EPP19SPP);
968 if (ppc->ppc_epp == EPP_1_7) {
969 outb(SMC935_IND, SMC935_PPMODE);
970 outb(SMC935_DAT, SMC935_EPP17SPP);
973 outb(SMC935_IND, SMC935_PPMODE);
974 outb(SMC935_DAT, SMC935_SPP);
978 /* ECP + EPP or just plain ECP */
979 if (chipset_mode & PPB_ECP) {
980 if (chipset_mode & PPB_EPP) {
981 if (ppc->ppc_epp == EPP_1_9) {
982 outb(SMC935_IND, SMC935_PPMODE);
983 outb(SMC935_DAT, SMC935_ECPEPP19);
985 if (ppc->ppc_epp == EPP_1_7) {
986 outb(SMC935_IND, SMC935_PPMODE);
987 outb(SMC935_DAT, SMC935_ECPEPP17);
990 outb(SMC935_IND, SMC935_PPMODE);
991 outb(SMC935_DAT, SMC935_ECP);
996 outb(SMC935_CFG, 0xaa); /* exit config mode */
998 ppc->ppc_type = PPC_TYPE_SMCLIKE;
999 ppc_smclike_setmode(ppc, chipset_mode);
1001 return (chipset_mode);
1005 * Winbond W83877F stuff
1007 * EFER: extended function enable register
1008 * EFIR: extended function index register
1009 * EFDR: extended function data register
1011 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1012 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1014 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1015 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1016 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1017 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1020 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1023 unsigned char r, hefere, hefras;
1025 for (i = 0; i < 4; i ++) {
1026 /* first try to enable configuration registers */
1027 efer = w83877f_efers[i];
1029 /* write the key to the EFER */
1030 for (j = 0; j < w83877f_keyiter[i]; j ++)
1031 outb (efer, w83877f_keys[i]);
1033 /* then check HEFERE and HEFRAS bits */
1035 hefere = inb(efdr) & WINB_HEFERE;
1038 hefras = inb(efdr) & WINB_HEFRAS;
1042 * 0 1 write 89h to 250h (power-on default)
1043 * 1 0 write 86h twice to 3f0h
1044 * 1 1 write 87h twice to 3f0h
1045 * 0 0 write 88h to 250h
1047 if ((hefere | hefras) == w83877f_hefs[i])
1051 return (-1); /* failed */
1054 /* check base port address - read from CR23 */
1056 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1059 /* read CHIP ID from CR9/bits0-3 */
1062 switch (inb(efdr) & WINB_CHIPID) {
1063 case WINB_W83877F_ID:
1064 ppc->ppc_model = WINB_W83877F;
1067 case WINB_W83877AF_ID:
1068 ppc->ppc_model = WINB_W83877AF;
1072 ppc->ppc_model = WINB_UNKNOWN;
1076 /* dump of registers */
1077 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1078 for (i = 0; i <= 0xd; i ++) {
1080 printf("0x%x ", inb(efdr));
1082 for (i = 0x10; i <= 0x17; i ++) {
1084 printf("0x%x ", inb(efdr));
1087 printf("0x%x ", inb(efdr));
1088 for (i = 0x20; i <= 0x29; i ++) {
1090 printf("0x%x ", inb(efdr));
1093 printf("ppc%d:", ppc->ppc_unit);
1096 ppc->ppc_type = PPC_TYPE_GENERIC;
1098 if (!chipset_mode) {
1099 /* autodetect mode */
1103 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1107 r |= (inb(efdr) & WINB_PRTMODS2);
1112 printf("ppc%d: W83757 compatible mode\n",
1114 return (-1); /* generic or SMC-like */
1121 printf(" not in parallel port mode\n");
1124 case (WINB_PARALLEL | WINB_EPP_SPP):
1125 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1130 case (WINB_PARALLEL | WINB_ECP):
1131 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1136 case (WINB_PARALLEL | WINB_ECP_EPP):
1137 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1138 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1141 printf(" ECP+EPP SPP");
1144 printf("%s: unknown case (0x%x)!\n", __func__, r);
1150 /* select CR9 and set PRTMODS2 bit */
1152 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1154 /* select CR0 and reset PRTMODSx bits */
1156 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1158 if (chipset_mode & PPB_ECP) {
1159 if (chipset_mode & PPB_EPP) {
1160 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1164 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1167 outb(efdr, inb(efdr) | WINB_ECP);
1172 /* select EPP_SPP otherwise */
1173 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1177 ppc->ppc_avm = chipset_mode;
1183 /* exit configuration mode */
1186 switch (ppc->ppc_type) {
1187 case PPC_TYPE_SMCLIKE:
1188 ppc_smclike_setmode(ppc, chipset_mode);
1191 ppc_generic_setmode(ppc, chipset_mode);
1195 return (chipset_mode);
1200 * ppc_generic_detect
1203 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1205 /* default to generic */
1206 ppc->ppc_type = PPC_TYPE_GENERIC;
1209 printf("ppc%d:", ppc->ppc_unit);
1211 /* first, check for ECP */
1212 w_ecr(ppc, PPC_ECR_PS2);
1213 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1214 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1218 /* search for SMC style ECP+EPP mode */
1219 w_ecr(ppc, PPC_ECR_EPP);
1222 /* try to reset EPP timeout bit */
1223 if (ppc_check_epp_timeout(ppc)) {
1224 ppc->ppc_dtm |= PPB_EPP;
1226 if (ppc->ppc_dtm & PPB_ECP) {
1227 /* SMC like chipset found */
1228 ppc->ppc_model = SMC_LIKE;
1229 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1238 /* restore to standard mode */
1239 w_ecr(ppc, PPC_ECR_STD);
1242 /* XXX try to detect NIBBLE and PS2 modes */
1243 ppc->ppc_dtm |= PPB_NIBBLE;
1249 ppc->ppc_avm = chipset_mode;
1251 ppc->ppc_avm = ppc->ppc_dtm;
1256 switch (ppc->ppc_type) {
1257 case PPC_TYPE_SMCLIKE:
1258 ppc_smclike_setmode(ppc, chipset_mode);
1261 ppc_generic_setmode(ppc, chipset_mode);
1265 return (chipset_mode);
1271 * mode is the mode suggested at boot
1274 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1276 #ifdef PPC_PROBE_CHIPSET
1279 /* list of supported chipsets */
1280 int (*chipset_detect[])(struct ppc_data *, int) = {
1282 ppc_smc37c66xgt_detect,
1284 ppc_smc37c935_detect,
1290 /* if can't find the port and mode not forced return error */
1291 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1292 return (EIO); /* failed, port not present */
1294 /* assume centronics compatible mode is supported */
1295 ppc->ppc_avm = PPB_COMPATIBLE;
1297 #ifdef PPC_PROBE_CHIPSET
1298 /* we have to differenciate available chipset modes,
1299 * chipset running modes and IEEE-1284 operating modes
1301 * after detection, the port must support running in compatible mode
1303 if (ppc->ppc_flags & 0x40) {
1305 printf("ppc: chipset forced to generic\n");
1308 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1310 #ifdef PPC_PROBE_CHIPSET
1312 for (i=0; chipset_detect[i] != NULL; i++) {
1313 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1314 ppc->ppc_mode = mode;
1321 /* configure/detect ECP FIFO */
1322 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1323 ppc_detect_fifo(ppc);
1329 * ppc_exec_microseq()
1331 * Execute a microsequence.
1332 * Microsequence mechanism is supposed to handle fast I/O operations.
1335 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1337 struct ppc_data *ppc = DEVTOSOFTC(dev);
1338 struct ppb_microseq *mi;
1345 register int accum = 0;
1346 register char *ptr = 0;
1348 struct ppb_microseq *stack = 0;
1350 /* microsequence registers are equivalent to PC-like port registers */
1352 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1353 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1355 #define INCR_PC (mi ++) /* increment program counter */
1359 switch (mi->opcode) {
1361 cc = r_reg(mi->arg[0].i, ppc);
1362 cc &= (char)mi->arg[2].i; /* clear mask */
1363 cc |= (char)mi->arg[1].i; /* assert mask */
1364 w_reg(mi->arg[0].i, ppc, cc);
1368 case MS_OP_RASSERT_P:
1372 if ((len = mi->arg[0].i) == MS_ACCUM) {
1373 accum = ppc->ppc_accum;
1374 for (; accum; accum--)
1375 w_reg(reg, ppc, *ptr++);
1376 ppc->ppc_accum = accum;
1378 for (i=0; i<len; i++)
1379 w_reg(reg, ppc, *ptr++);
1385 case MS_OP_RFETCH_P:
1387 mask = (char)mi->arg[2].i;
1390 if ((len = mi->arg[0].i) == MS_ACCUM) {
1391 accum = ppc->ppc_accum;
1392 for (; accum; accum--)
1393 *ptr++ = r_reg(reg, ppc) & mask;
1394 ppc->ppc_accum = accum;
1396 for (i=0; i<len; i++)
1397 *ptr++ = r_reg(reg, ppc) & mask;
1404 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1412 /* let's suppose the next instr. is the same */
1414 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1415 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1417 if (mi->opcode == MS_OP_DELAY) {
1418 DELAY(mi->arg[0].i);
1426 tsleep(NULL, PPBPRI, "ppbdelay",
1427 mi->arg[0].i * (hz/1000));
1433 iter = mi->arg[1].i;
1434 p = (char *)mi->arg[2].p;
1436 /* XXX delay limited to 255 us */
1437 for (i=0; i<iter; i++) {
1438 w_reg(reg, ppc, *p++);
1439 DELAY((unsigned char)*p++);
1445 ppc->ppc_accum = mi->arg[0].i;
1450 if (--ppc->ppc_accum > 0)
1457 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1464 if ((cc & (char)mi->arg[0].i) == 0)
1471 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1479 * If the C call returns !0 then end the microseq.
1480 * The current state of ptr is passed to the C function
1482 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1489 ppc->ppc_ptr = (char *)mi->arg[0].p;
1495 panic("%s: too much calls", __func__);
1498 /* store the state of the actual
1503 /* jump to the new microsequence */
1504 mi = (struct ppb_microseq *)mi->arg[0].p;
1511 /* retrieve microseq and pc state before the call */
1514 /* reset the stack */
1517 /* XXX return code */
1525 /* can't return to ppb level during the execution
1526 * of a submicrosequence */
1528 panic("%s: can't return to ppb level",
1531 /* update pc for ppb level of execution */
1534 /* return to ppb level of execution */
1538 panic("%s: unknown microsequence opcode 0x%x",
1539 __func__, mi->opcode);
1549 device_t dev = (device_t)arg;
1550 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1551 u_char ctr, ecr, str;
1558 printf("![%x/%x/%x]", ctr, ecr, str);
1561 /* don't use ecp mode with IRQENABLE set */
1562 if (ctr & IRQENABLE) {
1566 /* interrupts are generated by nFault signal
1567 * only in ECP mode */
1568 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1569 /* check if ppc driver has programmed the
1570 * nFault interrupt */
1571 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1573 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1574 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1576 /* shall be handled by underlying layers XXX */
1581 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1582 /* disable interrupts (should be done by hardware though) */
1583 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1584 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1587 /* check if DMA completed */
1588 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1593 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1596 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1606 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1608 /* wakeup the waiting process */
1612 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1614 /* classic interrupt I/O */
1615 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1622 ppc_read(device_t dev, char *buf, int len, int mode)
1628 * Call this function if you want to send data in any advanced mode
1629 * of your parallel port: FIFO, DMA
1631 * If what you want is not possible (no ECP, no DMA...),
1632 * EINVAL is returned
1635 ppc_write(device_t dev, char *buf, int len, int how)
1637 struct ppc_data *ppc = DEVTOSOFTC(dev);
1638 char ecr, ecr_sav, ctr, ctr_sav;
1646 ecr_sav = r_ecr(ppc);
1647 ctr_sav = r_ctr(ppc);
1650 * Send buffer with DMA, FIFO and interrupts
1652 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1654 if (ppc->ppc_dmachan > 0) {
1656 /* byte mode, no intr, no DMA, dir=0, flush fifo
1658 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1661 /* disable nAck interrupts */
1666 ppc->ppc_dmaflags = 0;
1667 ppc->ppc_dmaddr = (caddr_t)buf;
1668 ppc->ppc_dmacnt = (u_int)len;
1670 switch (ppc->ppc_mode) {
1671 case PPB_COMPATIBLE:
1672 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1673 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1676 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1686 /* enter splhigh() not to be preempted
1687 * by the dma interrupt, we may miss
1688 * the wakeup otherwise
1692 ppc->ppc_dmastat = PPC_DMA_INIT;
1694 /* enable interrupts */
1695 ecr &= ~PPC_SERVICE_INTR;
1696 ppc->ppc_irqstat = PPC_IRQ_DMA;
1705 printf("s%d", ppc->ppc_dmacnt);
1707 ppc->ppc_dmastat = PPC_DMA_STARTED;
1709 /* Wait for the DMA completed interrupt. We hope we won't
1710 * miss it, otherwise a signal will be necessary to unlock the
1716 PPBPRI | PCATCH, "ppcdma", 0);
1718 } while (error == EWOULDBLOCK);
1728 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1729 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1731 /* no dma, no interrupt, flush the fifo */
1732 w_ecr(ppc, PPC_ECR_RESET);
1734 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1738 /* wait for an empty fifo */
1739 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1741 for (spin=100; spin; spin--)
1742 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1747 error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1748 if (error != EWOULDBLOCK) {
1752 /* no dma, no interrupt, flush the fifo */
1753 w_ecr(ppc, PPC_ECR_RESET);
1755 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1762 /* no dma, no interrupt, flush the fifo */
1763 w_ecr(ppc, PPC_ECR_RESET);
1766 error = EINVAL; /* XXX we should FIFO and
1773 /* PDRQ must be kept unasserted until nPDACK is
1774 * deasserted for a minimum of 350ns (SMC datasheet)
1776 * Consequence may be a FIFO that never empty
1780 w_ecr(ppc, ecr_sav);
1781 w_ctr(ppc, ctr_sav);
1787 ppc_reset_epp(device_t dev)
1789 struct ppc_data *ppc = DEVTOSOFTC(dev);
1791 ppc_reset_epp_timeout(ppc);
1797 ppc_setmode(device_t dev, int mode)
1799 struct ppc_data *ppc = DEVTOSOFTC(dev);
1801 switch (ppc->ppc_type) {
1802 case PPC_TYPE_SMCLIKE:
1803 return (ppc_smclike_setmode(ppc, mode));
1806 case PPC_TYPE_GENERIC:
1808 return (ppc_generic_setmode(ppc, mode));
1816 static struct isa_pnp_id lpc_ids[] = {
1817 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1818 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1823 ppc_cbus_probe(device_t dev)
1828 parent = device_get_parent(dev);
1830 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1833 else if (error != 0) /* XXX shall be set after detection */
1834 device_set_desc(dev, "Parallel port");
1836 return(ppc_probe(dev));
1840 ppc_probe(device_t dev)
1843 static short next_bios_ppc = 0;
1845 struct ppc_data *ppc;
1849 #define PC98_IEEE_1284_DISABLE 0x100
1850 #define PC98_IEEE_1284_PORT 0x140
1852 unsigned int pc98_ieee_mode = 0x00;
1857 * Allocate the ppc_data structure.
1859 ppc = DEVTOSOFTC(dev);
1860 bzero(ppc, sizeof(struct ppc_data));
1862 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1863 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1865 /* retrieve ISA parameters */
1866 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1870 * If port not specified, use bios list.
1874 if((next_bios_ppc < BIOS_MAX_PPC) &&
1875 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1876 port = *(BIOS_PORTS+next_bios_ppc++);
1878 device_printf(dev, "parallel port found at 0x%x\n",
1881 device_printf(dev, "parallel port not found.\n");
1885 if (next_bios_ppc == 0) {
1886 /* Use default IEEE-1284 port of NEC PC-98x1 */
1887 port = PC98_IEEE_1284_PORT;
1891 "parallel port found at 0x%x\n",
1895 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1896 IO_LPTSIZE_EXTENDED);
1901 * There isn't a bios list on alpha. Put it in the usual place.
1904 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc,
1909 /* IO port is mandatory */
1911 /* Try "extended" IO port range...*/
1912 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1913 &ppc->rid_ioport, 0, ~0,
1914 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1916 if (ppc->res_ioport != 0) {
1918 device_printf(dev, "using extended I/O port range\n");
1920 /* Failed? If so, then try the "normal" IO port range... */
1921 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1922 &ppc->rid_ioport, 0, ~0,
1925 if (ppc->res_ioport != 0) {
1927 device_printf(dev, "using normal I/O port range\n");
1929 device_printf(dev, "cannot reserve I/O port range\n");
1934 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1936 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1937 ppc->bst = rman_get_bustag(ppc->res_ioport);
1939 ppc->ppc_flags = device_get_flags(dev);
1941 if (!(ppc->ppc_flags & 0x20)) {
1942 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1945 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1951 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1953 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1955 ppc->ppc_unit = device_get_unit(dev);
1956 ppc->ppc_model = GENERIC;
1958 ppc->ppc_mode = PPB_COMPATIBLE;
1959 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1961 ppc->ppc_type = PPC_TYPE_GENERIC;
1965 * IEEE STD 1284 Function Check and Enable
1966 * for default IEEE-1284 port of NEC PC-98x1
1968 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1969 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1970 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1971 pc98_ieee_mode = tmp;
1972 if ((tmp & 0x10) == 0x10) {
1973 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1974 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1975 if ((tmp & 0x10) == 0x10)
1978 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1979 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1980 if ((tmp & 0x10) != 0x10)
1983 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1988 * Try to detect the chipset and its mode.
1990 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1997 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1998 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1999 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
2002 if (ppc->res_irq != 0) {
2003 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
2006 if (ppc->res_ioport != 0) {
2007 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
2010 if (ppc->res_drq != 0) {
2011 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
2018 ppc_attach(device_t dev)
2020 struct ppc_data *ppc = DEVTOSOFTC(dev);
2023 device_t parent = device_get_parent(dev);
2025 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
2026 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
2027 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
2028 ppc_epp_protocol[ppc->ppc_epp] : "");
2031 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
2032 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
2034 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
2035 /* acquire the DMA channel forever */ /* XXX */
2036 isa_dma_acquire(ppc->ppc_dmachan);
2037 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
2040 /* add ppbus as a child of this isa to parallel bridge */
2041 ppbus = device_add_child(dev, "ppbus", -1);
2044 * Probe the ppbus and attach devices found.
2046 device_probe_and_attach(ppbus);
2048 /* register the ppc interrupt handler as default */
2050 /* default to the tty mask for registration */ /* XXX */
2051 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY,
2052 ppcintr, dev, &ppc->intr_cookie) == 0) {
2054 /* remember the ppcintr is registered */
2055 ppc->ppc_registered = 1;
2063 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2065 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2068 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2071 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2074 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2077 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2080 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2083 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2086 return (r_dtr(ppc));
2088 return (r_str(ppc));
2090 return (r_ctr(ppc));
2092 return (r_epp_A(ppc));
2094 return (r_epp_D(ppc));
2096 return (r_ecr(ppc));
2098 return (r_fifo(ppc));
2121 panic("%s: unknown I/O operation", __func__);
2125 return (0); /* not significative */
2129 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2131 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2134 case PPC_IVAR_EPP_PROTO:
2135 *val = (u_long)ppc->ppc_epp;
2138 *val = (u_long)ppc->ppc_irq;
2148 * Resource is useless here since ppbus devices' interrupt handlers are
2149 * multiplexed to the same resource initially allocated by ppc
2152 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2153 void (*ihand)(void *), void *arg, void **cookiep)
2156 struct ppc_data *ppc = DEVTOSOFTC(bus);
2158 if (ppc->ppc_registered) {
2159 /* XXX refuse registration if DMA is in progress */
2161 /* first, unregister the default interrupt handler */
2162 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2163 bus, ppc->res_irq, ppc->intr_cookie)))
2166 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2167 /* ppc->res_irq); */
2169 /* DMA/FIFO operation won't be possible anymore */
2170 ppc->ppc_registered = 0;
2173 /* pass registration to the upper layer, ignore the incoming resource */
2174 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2175 r, flags, ihand, arg, cookiep));
2179 * When no underlying device has a registered interrupt, register the ppc
2183 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2186 struct ppc_data *ppc = DEVTOSOFTC(bus);
2187 device_t parent = device_get_parent(bus);
2189 /* pass unregistration to the upper layer */
2190 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2193 /* default to the tty mask for registration */ /* XXX */
2195 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2196 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) {
2198 /* remember the ppcintr is registered */
2199 ppc->ppc_registered = 1;
2205 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);
2207 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0);