2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
38 #include "opt_comconsole.h"
39 #include "opt_compat.h"
45 * Serial driver, based on 386BSD-0.1 com driver.
46 * Mostly rewritten to use pseudo-DMA.
47 * Works for National Semiconductor NS8250-NS16550AF UARTs.
48 * COM driver, based on HP dca driver.
50 * Changes for PC-Card integration:
51 * - Added PC-Card driver table and handlers
53 /*===============================================================
54 * 386BSD(98),FreeBSD-1.1x(98) com driver.
56 * modified for PC9801 by M.Ishii
57 * Kyoto University Microcomputer Club (KMC)
58 * Chou "TEFUTEFU" Hirotomi
59 * Kyoto Univ. the faculty of medicine
60 *===============================================================
61 * FreeBSD-2.0.1(98) sio driver.
63 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
64 * T.Koike(hfc01340@niftyserve.or.jp)
65 * implement kernel device configuration
66 * aizu@orient.center.nitech.ac.jp
70 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
72 * This driver is under debugging,has bugs.
75 * options COM_MULTIPORT #if using MC16550II
76 * device sio0 at nec? port 0x30 tty irq 4 #internal
77 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
78 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
79 * # ~~~~~iobase ~~multi port flag
80 * # ~ master device is sio1
82 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
84 * 57600bps is too fast for sio0(internal8251)
86 * #set default speed 9600
89 * stty </dev/ttyid$i crtscts 9600
90 * : # ~~~~ default speed(can change after init.)
94 * 5) PC9861K,PIO9032B,B98_01
98 * modified for AIWA B98-01
99 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
101 * How to configure...
102 * # options COM_MULTIPORT # support for MICROCORE MC16550II
103 * ... comment-out this line, which will conflict with B98_01.
104 * options "B98_01" # support for AIWA B98-01
105 * device sio1 at nec? port 0x00d1 tty irq ?
106 * device sio2 at nec? port 0x00d5 tty irq ?
107 * ... you can leave these lines `irq ?', irq will be autodetected.
110 * Modified by Y.Takahashi of Kogakuin University.
114 #define COM_IF_INTERNAL 0x00
115 #define COM_IF_PC9861K_1 0x01
116 #define COM_IF_PC9861K_2 0x02
117 #define COM_IF_IND_SS_1 0x03
118 #define COM_IF_IND_SS_2 0x04
119 #define COM_IF_PIO9032B_1 0x05
120 #define COM_IF_PIO9032B_2 0x06
121 #define COM_IF_B98_01_1 0x07
122 #define COM_IF_B98_01_2 0x08
123 #define COM_IF_END1 COM_IF_B98_01_2
124 #define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
125 #define COM_IF_NS16550 0x11
126 #define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
127 #define COM_IF_MC16550II 0x13
128 #define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
129 #define COM_IF_RSB3000 0x15
130 #define COM_IF_RSB384 0x16
131 #define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
132 #define COM_IF_RSA98III 0x18
133 #define COM_IF_ESP98 0x19
134 #define COM_IF_END2 COM_IF_ESP98
137 #include <sys/param.h>
138 #include <sys/systm.h>
139 #include <sys/reboot.h>
140 #include <sys/malloc.h>
142 #include <sys/proc.h>
143 #include <sys/module.h>
144 #include <sys/conf.h>
145 #include <sys/dkstat.h>
146 #include <sys/fcntl.h>
147 #include <sys/interrupt.h>
148 #include <sys/kernel.h>
149 #include <sys/syslog.h>
150 #include <sys/sysctl.h>
152 #include <machine/bus.h>
153 #include <sys/rman.h>
154 #include <sys/timepps.h>
157 #include <pc98/pc98/pc98.h>
158 #include <pc98/pc98/pc98_machdep.h>
159 #include <i386/isa/ic/i8251.h>
161 #include <isa/isareg.h>
163 #include <isa/isavar.h>
164 #include <machine/lock.h>
166 #include <machine/clock.h>
167 #include <machine/ipl.h>
169 #include <machine/lock.h>
171 #include <machine/resource.h>
173 #include <isa/sioreg.h>
176 #include <i386/isa/ic/esp.h>
178 #include <i386/isa/ic/ns16550.h>
180 #include <i386/isa/ic/rsa.h>
186 #include <sys/module.h>
187 #include <pccard/cardinfo.h>
188 #include <pccard/slot.h>
195 #define disable_intr()
196 #define enable_intr()
200 #define disable_intr() COM_DISABLE_INTR()
201 #define enable_intr() COM_ENABLE_INTR()
205 #define EXTRA_SIO 4 /* XXX shouldn't need NSIO */
208 #define NSIOTOT (NSIO + EXTRA_SIO)
210 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
212 #define CALLOUT_MASK 0x80
213 #define CONTROL_MASK 0x60
214 #define CONTROL_INIT_STATE 0x20
215 #define CONTROL_LOCK_STATE 0x40
216 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
217 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
218 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
221 /* checks in flags for multiport and which is multiport "master chip"
224 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
225 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
226 #define COM_NOTAST4(flags) ((flags) & 0x04)
227 #endif /* COM_MULTIPORT */
229 #define COM_CONSOLE(flags) ((flags) & 0x10)
230 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
231 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
232 #define COM_DEBUGGER(flags) ((flags) & 0x80)
233 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
234 #define COM_NOFIFO(flags) ((flags) & 0x02)
235 #define COM_ST16650A(flags) ((flags) & 0x20000)
236 #define COM_C_NOPROBE (0x40000)
237 #define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
238 #define COM_C_IIR_TXRDYBUG (0x80000)
239 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
240 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
243 #define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
245 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
250 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
251 * than the other bits so that they can be tested as a group without masking
254 * The following com and tty flags correspond closely:
255 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
257 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
258 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
259 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
260 * TS_FLUSH is not used.
261 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
262 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
264 #define CS_BUSY 0x80 /* output in progress */
265 #define CS_TTGO 0x40 /* output not stopped by XOFF */
266 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
267 #define CS_CHECKMSR 1 /* check of MSR scheduled */
268 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
269 #define CS_DTR_OFF 0x10 /* DTR held off */
270 #define CS_ODONE 4 /* output completed */
271 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
272 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
274 static char const * const error_desc[] = {
277 #define CE_INTERRUPT_BUF_OVERFLOW 1
278 "interrupt-level buffer overflow",
279 #define CE_TTY_BUF_OVERFLOW 2
280 "tty-level buffer overflow",
284 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
286 /* types. XXX - should be elsewhere */
287 typedef u_int Port_t; /* hardware port */
288 typedef u_char bool_t; /* boolean */
290 /* queue of linear buffers */
292 u_char *l_head; /* next char to process */
293 u_char *l_tail; /* one past the last char to process */
294 struct lbq *l_next; /* next in queue */
295 bool_t l_queued; /* nonzero if queued */
298 /* com device structure */
300 u_int flags; /* Copy isa device flags */
301 u_char state; /* miscellaneous flag bits */
302 bool_t active_out; /* nonzero if the callout device is open */
303 u_char cfcr_image; /* copy of value written to CFCR */
305 bool_t esp; /* is this unit a hayes esp board? */
307 u_char extra_state; /* more flag bits, separate for order trick */
308 u_char fifo_image; /* copy of value written to FIFO */
309 bool_t hasfifo; /* nonzero for 16550 UARTs */
310 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
311 bool_t loses_outints; /* nonzero if device loses output interrupts */
312 u_char mcr_image; /* copy of value written to MCR */
314 bool_t multiport; /* is this unit part of a multiport device? */
315 #endif /* COM_MULTIPORT */
316 bool_t no_irq; /* nonzero if irq is not attached */
317 bool_t gone; /* hardware disappeared */
318 bool_t poll; /* nonzero if polling is required */
319 bool_t poll_output; /* nonzero if polling for output is required */
320 int unit; /* unit number */
321 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
323 u_int wopeners; /* # processes waiting for DCD in open() */
326 * The high level of the driver never reads status registers directly
327 * because there would be too many side effects to handle conveniently.
328 * Instead, it reads copies of the registers stored here by the
331 u_char last_modem_status; /* last MSR read by intr handler */
332 u_char prev_modem_status; /* last MSR handled by high level */
334 u_char hotchar; /* ldisc-specific char to be handled ASAP */
335 u_char *ibuf; /* start of input buffer */
336 u_char *ibufend; /* end of input buffer */
337 u_char *ibufold; /* old input buffer, to be freed */
338 u_char *ihighwater; /* threshold in input buffer */
339 u_char *iptr; /* next free spot in input buffer */
340 int ibufsize; /* size of ibuf (not include error bytes) */
341 int ierroff; /* offset of error bytes in ibuf */
343 struct lbq obufq; /* head of queue of output buffers */
344 struct lbq obufs[2]; /* output buffers */
349 Port_t in_modem_port;
350 Port_t intr_ctrl_port;
352 int pc98_prev_modem_status;
353 int pc98_modem_delta;
354 int modem_car_chg_timer;
355 int pc98_prev_siocmd;
356 int pc98_prev_siomod;
360 Port_t data_port; /* i/o ports */
367 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
369 Port_t modem_ctl_port;
370 Port_t line_status_port;
371 Port_t modem_status_port;
372 Port_t intr_ctl_port; /* Ports of IIR register */
374 struct tty *tp; /* cross reference */
377 struct termios it_in; /* should be in struct tty */
378 struct termios it_out;
381 struct termios lt_in; /* should be in struct tty */
382 struct termios lt_out;
385 bool_t do_dcd_timestamp;
386 struct timeval timestamp;
387 struct timeval dcd_timestamp;
388 struct pps_state pps;
390 u_long bytes_in; /* statistics */
392 u_int delta_error_counts[CE_NTYPES];
393 u_long error_counts[CE_NTYPES];
395 struct resource *irqres;
396 struct resource *ioportres;
399 * Data area for output buffers. Someday we should build the output
400 * buffer queue without copying data.
413 static int espattach __P((struct com_s *com, Port_t esp_port));
415 static int sioattach __P((device_t dev));
417 static timeout_t siobusycheck;
418 static timeout_t siodtrwakeup;
419 static void comhardclose __P((struct com_s *com));
420 static void sioinput __P((struct com_s *com));
421 static void siointr1 __P((struct com_s *com));
422 static void siointr __P((void *arg));
423 static int commctl __P((struct com_s *com, int bits, int how));
424 static int comparam __P((struct tty *tp, struct termios *t));
425 static swihand_t siopoll;
426 static int sioprobe __P((device_t dev));
427 static void siosettimeout __P((void));
428 static int siosetwater __P((struct com_s *com, speed_t speed));
429 static void comstart __P((struct tty *tp));
430 static timeout_t comwakeup;
431 static void disc_optim __P((struct tty *tp, struct termios *t,
435 static char driver_name[] = "sio";
437 /* table and macro for fast conversion from a unit number to its com struct */
438 static devclass_t sio_devclass;
439 #define com_addr(unit) ((struct com_s *) \
440 devclass_get_softc(sio_devclass, unit))
442 static device_method_t sio_methods[] = {
443 /* Device interface */
444 DEVMETHOD(device_probe, sioprobe),
445 DEVMETHOD(device_attach, sioattach),
450 static driver_t sio_driver = {
453 sizeof(struct com_s),
456 static d_open_t sioopen;
457 static d_close_t sioclose;
458 static d_read_t sioread;
459 static d_write_t siowrite;
460 static d_ioctl_t sioioctl;
461 static d_stop_t siostop;
462 static d_devtotty_t siodevtotty;
464 #define CDEV_MAJOR 28
465 static struct cdevsw sio_cdevsw = {
467 /* close */ sioclose,
469 /* write */ siowrite,
470 /* ioctl */ sioioctl,
473 /* devtotty */ siodevtotty,
476 /* strategy */ nostrategy,
477 /* name */ driver_name,
479 /* maj */ CDEV_MAJOR,
488 static volatile speed_t comdefaultrate = CONSPEED;
490 static volatile speed_t gdbdefaultrate = CONSPEED;
492 static u_int com_events; /* input chars + weighted output completions */
493 static Port_t siocniobase;
494 static int siocnunit;
495 static Port_t siogdbiobase;
496 static int siogdbunit = -1;
497 static bool_t sio_registered;
498 static int sio_timeout;
499 static int sio_timeouts_until_log;
500 static struct callout_handle sio_timeout_handle
501 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
507 Port_t cmd, sts, ctrl, mod;
511 #define COM_INT_DISABLE {int previpri; previpri=spltty();
512 #define COM_INT_ENABLE splx(previpri);}
513 #define IEN_TxFLAG IEN_Tx
515 #define COM_CARRIER_DETECT_EMULATE 0
516 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
517 #define DCD_OFF_TOLERANCE 2
518 #define DCD_ON_RECOGNITION 2
519 #define IS_8251(if_type) (!(if_type & 0x10))
520 #define COM1_EXT_CLOCK 0x40000
522 static void commint __P((dev_t dev));
523 static void com_tiocm_set __P((struct com_s *com, int msr));
524 static void com_tiocm_bis __P((struct com_s *com, int msr));
525 static void com_tiocm_bic __P((struct com_s *com, int msr));
526 static int com_tiocm_get __P((struct com_s *com));
527 static int com_tiocm_get_delta __P((struct com_s *com));
528 static void pc98_msrint_start __P((dev_t dev));
529 static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
530 static int pc98_ttspeedtab __P((struct com_s *com, int speed));
531 static int pc98_get_modem_status __P((struct com_s *com));
532 static timeout_t pc98_check_msr;
533 static void pc98_set_baud_rate __P((struct com_s *com, int count));
534 static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
535 static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
536 static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
537 static int pc98_check_i8251_interrupt __P((struct com_s *com));
538 static int pc98_i8251_get_cmd __P((struct com_s *com));
539 static int pc98_i8251_get_mod __P((struct com_s *com));
540 static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
541 static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
542 static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
543 static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
544 static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
545 static void pc98_check_sysclock __P((void));
546 static int pc98_set_ioport __P((struct com_s *com, int id_flags));
548 #define com_int_Tx_disable(com) \
549 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
550 #define com_int_Tx_enable(com) \
551 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
552 #define com_int_Rx_disable(com) \
553 pc98_disable_i8251_interrupt(com,IEN_Rx)
554 #define com_int_Rx_enable(com) \
555 pc98_enable_i8251_interrupt(com,IEN_Rx)
556 #define com_int_TxRx_disable(com) \
557 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
558 #define com_int_TxRx_enable(com) \
559 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
560 #define com_send_break_on(com) \
561 pc98_i8251_or_cmd(com,CMD8251_SBRK)
562 #define com_send_break_off(com) \
563 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
565 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
587 static struct speedtab pc98fast_speedtab[] = {
588 { 9600, 0x80 | COMBRD(9600), },
589 { 19200, 0x80 | COMBRD(19200), },
590 { 38400, 0x80 | COMBRD(38400), },
591 { 57600, 0x80 | COMBRD(57600), },
592 { 115200, 0x80 | COMBRD(115200), },
595 static struct speedtab comspeedtab_pio9032b[] = {
606 static struct speedtab comspeedtab_b98_01[] = {
621 static struct speedtab comspeedtab_mc16550[] = {
637 static struct speedtab comspeedtab_rsb384[] = {
658 static struct speedtab comspeedtab_rsa[] = {
660 { 50, COMBRD_RSA(50) },
661 { 75, COMBRD_RSA(75) },
662 { 110, COMBRD_RSA(110) },
663 { 134, COMBRD_RSA(134) },
664 { 150, COMBRD_RSA(150) },
665 { 200, COMBRD_RSA(200) },
666 { 300, COMBRD_RSA(300) },
667 { 600, COMBRD_RSA(600) },
668 { 1200, COMBRD_RSA(1200) },
669 { 1800, COMBRD_RSA(1800) },
670 { 2400, COMBRD_RSA(2400) },
671 { 4800, COMBRD_RSA(4800) },
672 { 9600, COMBRD_RSA(9600) },
673 { 19200, COMBRD_RSA(19200) },
674 { 38400, COMBRD_RSA(38400) },
675 { 57600, COMBRD_RSA(57600) },
676 { 115200, COMBRD_RSA(115200) },
677 { 230400, COMBRD_RSA(230400) },
678 { 460800, COMBRD_RSA(460800) },
679 { 921600, COMBRD_RSA(921600) },
684 static struct speedtab comspeedtab[] = {
688 { 110, COMBRD(110) },
689 { 134, COMBRD(134) },
690 { 150, COMBRD(150) },
691 { 200, COMBRD(200) },
692 { 300, COMBRD(300) },
693 { 600, COMBRD(600) },
694 { 1200, COMBRD(1200) },
695 { 1800, COMBRD(1800) },
696 { 2400, COMBRD(2400) },
697 { 4800, COMBRD(4800) },
698 { 9600, COMBRD(9600) },
699 { 19200, COMBRD(19200) },
700 { 38400, COMBRD(38400) },
701 { 57600, COMBRD(57600) },
702 { 115200, COMBRD(115200) },
711 struct speedtab *speedtab;
714 /* COM_IF_INTERNAL */
715 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
716 -1, pc98speedtab, 1 },
717 /* COM_IF_PC9861K_1 */
718 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
720 /* COM_IF_PC9861K_2 */
721 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
723 /* COM_IF_IND_SS_1 */
724 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
725 3, comspeedtab_mc16550, 1 },
726 /* COM_IF_IND_SS_2 */
727 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
728 3, comspeedtab_mc16550, 1 },
729 /* COM_IF_PIO9032B_1 */
730 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
731 7, comspeedtab_pio9032b, 1 },
732 /* COM_IF_PIO9032B_2 */
733 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
734 7, comspeedtab_pio9032b, 1 },
735 /* COM_IF_B98_01_1 */
736 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
737 7, comspeedtab_b98_01, 0 },
738 /* COM_IF_B98_01_2 */
739 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
740 7, comspeedtab_b98_01, 0 },
742 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
743 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
744 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
745 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
746 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
747 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
748 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
756 struct speedtab *speedtab;
757 } if_16550a_type[] = {
759 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
761 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
762 /* COM_IF_SECOND_CCU */
763 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
764 /* COM_IF_MC16550II */
765 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
767 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
769 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
771 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
772 /* COM_IF_MODEM_CARD */
773 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
774 /* COM_IF_RSA98III */
775 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
777 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
784 /* XXX configure this properly. */
785 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
786 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
788 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
789 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
790 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
791 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
795 /* XXX configure this properly. */
796 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
797 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
803 * handle sysctl read/write requests for console speed
805 * In addition to setting comdefaultrate for I/O through /dev/console,
806 * also set the initial and lock values for the /dev/ttyXX device
807 * if there is one associated with the console. Finally, if the /dev/tty
808 * device has already been open, change the speed on the open running port
813 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
820 newspeed = comdefaultrate;
822 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
823 if (error || !req->newptr)
826 comdefaultrate = newspeed;
828 if (comconsole < 0) /* serial console not selected? */
831 com = com_addr(comconsole);
836 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
837 * (note, the lock rates really are boolean -- if non-zero, disallow
840 com->it_in.c_ispeed = com->it_in.c_ospeed =
841 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
842 com->it_out.c_ispeed = com->it_out.c_ospeed =
843 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
846 * if we're open, change the running rate too
849 if (tp && (tp->t_state & TS_ISOPEN)) {
850 tp->t_termios.c_ispeed =
851 tp->t_termios.c_ospeed = comdefaultrate;
853 error = comparam(tp, &tp->t_termios);
859 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
860 0, 0, sysctl_machdep_comdefaultrate, "I", "");
864 * PC-Card (PCMCIA) specific code.
866 static int sioinit __P((struct pccard_devinfo *));
867 static void siounload __P((struct pccard_devinfo *));
868 static int card_intr __P((struct pccard_devinfo *));
870 PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
873 * Initialize the device - called from Slot manager.
876 sioinit(struct pccard_devinfo *devi)
879 /* validate unit number. */
880 if (devi->isahd.id_unit >= (NSIOTOT))
882 /* Make sure it isn't already probed. */
883 if (com_addr(devi->isahd.id_unit))
886 /* It's already probed as serial by Upper */
887 devi->isahd.id_flags |= COM_C_NOPROBE;
892 if (sioattach(devi->isahd.id_device) == 0)
899 * siounload - unload the driver and clear the table.
901 * This is usually called when the card is ejected, but
902 * can be caused by a modunload of a controller driver.
903 * The idea is to reset the driver's view of the device
904 * and ensure that any driver entry points such as
905 * read and write do not hang.
908 siounload(struct pccard_devinfo *devi)
913 printf("NULL devi in siounload\n");
916 com = com_addr(devi->isahd.id_unit);
918 printf("NULL com in siounload\n");
922 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
925 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
927 printf("sio%d: unload\n", devi->isahd.id_unit);
933 if (com->ibuf != NULL)
934 free(com->ibuf, M_DEVBUF);
936 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
941 * card_intr - Shared interrupt called from
942 * front end of PC-Card handler.
945 card_intr(struct pccard_devinfo *devi)
950 com = com_addr(devi->isahd.id_unit);
951 if (com && !com->gone)
952 siointr1(com_addr(devi->isahd.id_unit));
956 #endif /* NCARD > 0 */
958 #define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
959 #define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
961 static struct isa_pnp_id sio_ids[] = {
962 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
963 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
964 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
965 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
966 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
967 {0x31307256, "USR3031"}, /* USR3031 */
975 static bool_t already_init;
980 intrmask_t irqmap[4];
985 u_int flags = device_get_flags(dev);
987 struct resource *port;
993 Port_t rsabase = NULL;
996 /* Check isapnp ids */
997 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
1002 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1003 0, ~0, 1, RF_ACTIVE); /* XXX */
1005 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1006 0, ~0, IO_COMSIZE, RF_ACTIVE);
1011 if (!already_init) {
1013 * Turn off MCR_IENABLE for all likely serial ports. An unused
1014 * port with its MCR_IENABLE gate open will inhibit interrupts
1015 * from any used port that shares the interrupt vector.
1016 * XXX the gate enable is elsewhere for some multiports.
1021 devclass_get_devices(sio_devclass, &devs, &count);
1023 for (i = 0; i < count; i++) {
1025 if (device_is_enabled(xdev)) {
1026 tmp = (flags >> 24) & 0xff;
1028 outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
1030 if (tmp == COM_IF_RSA98III) {
1031 rsabase = isa_get_port(xdev) & 0xfff0;
1032 outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1034 outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1038 for (i = 0; i < count; i++) {
1040 if (device_is_enabled(xdev))
1041 outb(isa_get_port(xdev) + com_mcr, 0);
1045 already_init = TRUE;
1048 if (COM_LLCONSOLE(flags)) {
1049 printf("sio%d: reserved for low-level i/o\n",
1050 device_get_unit(dev));
1058 * If the port is i8251 UART (internal, B98_01)
1060 if (pc98_check_if_type(dev, &iod) == -1)
1063 isa_set_irq(dev, iod.irq);
1064 if (IS_8251(iod.if_type)) {
1071 outb(iod.cmd, CMD8251_RESET);
1072 DELAY(1000); /* for a while...*/
1073 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1075 outb(iod.cmd, 0x01); /* CMD (dummy) */
1076 DELAY(1000); /* for a while...*/
1077 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1080 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1082 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1083 outb( iod.ctrl, tmp|IEN_TxEMP );
1085 result = isa_irq_pending() ? 0 : ENXIO;
1086 outb( iod.ctrl, tmp );
1090 * B98_01 doesn't activate TxEMP interrupt line
1091 * when being reset, so we can't check irq pending.
1095 if (epson_machine_id==0x20) { /* XXX */
1098 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1103 * If the device is on a multiport card and has an AST/4
1104 * compatible interrupt control register, initialize this
1105 * register and prepare to leave MCR_IENABLE clear in the mcr.
1106 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1107 * Point idev to the device struct giving the correct id_irq.
1108 * This is the struct for the master device if there is one.
1111 mcr_image = MCR_IENABLE;
1113 if (iod.if_type == COM_IF_RSA98III) {
1115 rsabase = isa_get_port(idev) & 0xfff0;
1116 if (rsabase != isa_get_port(idev))
1118 outb(rsabase + rsa_msr, 0x04);
1119 outb(rsabase + rsa_frr, 0x00);
1120 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1122 outb(rsabase + rsa_ier, 0x00);
1123 outb(rsabase + rsa_frr, 0x00);
1124 outb(rsabase + rsa_tivsr, 0x00);
1125 outb(rsabase + rsa_tcr, 0x00);
1128 #ifdef COM_MULTIPORT
1129 if (COM_ISMULTIPORT(flags)) {
1130 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1132 printf("sio%d: master device %d not configured\n",
1133 device_get_unit(dev), COM_MPMASTER(flags));
1137 if (!COM_NOTAST4(flags)) {
1138 outb(isa_get_port(idev) + com_scr,
1139 isa_get_irq(idev) >= 0 ? 0x80 : 0);
1144 #endif /* COM_MULTIPORT */
1145 if (isa_get_irq(idev) < 0)
1149 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1152 switch (isa_get_irq(idev)) {
1153 case 3: irqout = 4; break;
1154 case 5: irqout = 5; break;
1155 case 6: irqout = 6; break;
1156 case 12: irqout = 7; break;
1158 printf("sio%d: irq configuration error\n",
1159 device_get_unit(dev));
1162 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
1164 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1166 bzero(failures, sizeof failures);
1167 iobase = rman_get_start(port);
1169 if (iod.if_type == COM_IF_RSA98III)
1174 * We don't want to get actual interrupts, just masked ones.
1175 * Interrupts from this line should already be masked in the ICU,
1176 * but mask them in the processor as well in case there are some
1177 * (misconfigured) shared interrupts.
1183 * Initialize the speed and the word size and wait long enough to
1184 * drain the maximum of 16 bytes of junk in device output queues.
1185 * The speed is undefined after a master reset and must be set
1186 * before relying on anything related to output. There may be
1187 * junk after a (very fast) soft reboot and (apparently) after
1189 * XXX what about the UART bug avoided by waiting in comparam()?
1190 * We don't want to to wait long enough to drain at 2 bps.
1192 if (iobase == siocniobase)
1193 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1196 tmp = ttspeedtab(SIO_TEST_SPEED,
1197 if_16550a_type[iod.if_type & 0x0f].speedtab);
1198 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1199 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1200 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1201 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1203 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1204 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1205 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1206 outb(iobase + com_cfcr, CFCR_8BITS);
1208 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1212 * Enable the interrupt gate and disable device interupts. This
1213 * should leave the device driving the interrupt line low and
1214 * guarantee an edge trigger if an interrupt can be generated.
1218 outb(iobase + (com_mcr << port_shift), mcr_image);
1219 outb(iobase + (com_ier << port_shift), 0);
1221 outb(iobase + com_mcr, mcr_image);
1222 outb(iobase + com_ier, 0);
1224 DELAY(1000); /* XXX */
1225 irqmap[0] = isa_irq_pending();
1228 * Attempt to set loopback mode so that we can send a null byte
1229 * without annoying any external device.
1233 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1235 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1239 * Attempt to generate an output interrupt. On 8250's, setting
1240 * IER_ETXRDY generates an interrupt independent of the current
1241 * setting and independent of whether the THR is empty. On 16450's,
1242 * setting IER_ETXRDY generates an interrupt independent of the
1243 * current setting. On 16550A's, setting IER_ETXRDY only
1244 * generates an interrupt when IER_ETXRDY is not already set.
1247 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1248 if (iod.if_type == COM_IF_RSA98III)
1249 outb(rsabase + rsa_ier, 0x04);
1251 outb(iobase + com_ier, IER_ETXRDY);
1255 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1256 * an interrupt. They'd better generate one for actually doing
1257 * output. Loopback may be broken on the same incompatibles but
1258 * it's unlikely to do more than allow the null byte out.
1261 outb(iobase + (com_data << port_shift), 0);
1263 outb(iobase + com_data, 0);
1265 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1268 * Turn off loopback mode so that the interrupt gate works again
1269 * (MCR_IENABLE was hidden). This should leave the device driving
1270 * an interrupt line high. It doesn't matter if the interrupt
1271 * line oscillates while we are not looking at it, since interrupts
1276 outb(iobase + (com_mcr << port_shift), mcr_image);
1278 outb(iobase + com_mcr, mcr_image);
1282 * It's a definitly Serial PCMCIA(16550A), but still be required
1283 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1285 if ( COM_NOPROBE(flags) ) {
1286 /* Reading IIR register twice */
1287 for ( fn = 0; fn < 2; fn ++ ) {
1290 failures[6] = inb(iobase + (com_iir << port_shift));
1292 failures[6] = inb(iobase + com_iir);
1295 /* Check IIR_TXRDY clear ? */
1297 if ( failures[6] & IIR_TXRDY ) {
1298 /* Nop, Double check with clearing IER */
1300 outb(iobase + (com_ier << port_shift), 0);
1302 (com_iir << port_shift)) & IIR_NOPEND) {
1304 outb(iobase + com_ier, 0);
1305 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1307 /* Ok. we're familia this gang */
1308 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
1310 /* Unknown, Just omit this chip.. XXX */
1314 /* OK. this is well-known guys */
1315 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
1318 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1320 outb(iobase + com_cfcr, CFCR_8BITS);
1323 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1324 return (iobase == siocniobase ? 0 : result);
1329 * o the CFCR, IER and MCR in UART hold the values written to them
1330 * (the values happen to be all distinct - this is good for
1331 * avoiding false positive tests from bus echoes).
1332 * o an output interrupt is generated and its vector is correct.
1333 * o the interrupt goes away when the IIR in the UART is read.
1337 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1338 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1339 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1341 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1342 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1343 failures[2] = inb(iobase + com_mcr) - mcr_image;
1345 DELAY(10000); /* Some internal modems need this time */
1346 irqmap[1] = isa_irq_pending();
1348 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1350 if (iod.if_type == COM_IF_RSA98III)
1351 inb(rsabase + rsa_srr);
1353 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1355 DELAY(1000); /* XXX */
1356 irqmap[2] = isa_irq_pending();
1358 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1360 if (iod.if_type == COM_IF_RSA98III)
1361 inb(rsabase + rsa_srr);
1363 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1367 * Turn off all device interrupts and check that they go off properly.
1368 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1369 * the OUT2 output of the UART to
1370 * the ICU input. Closing the gate would give a floating ICU input
1371 * (unless there is another device driving it) and spurious interrupts.
1372 * (On the system that this was first tested on, the input floats high
1373 * and gives a (masked) interrupt as soon as the gate is closed.)
1376 outb(iobase + (com_ier << port_shift), 0);
1377 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1378 failures[7] = inb(iobase + (com_ier << port_shift));
1379 if (iod.if_type == COM_IF_RSA98III)
1380 outb(rsabase + rsa_ier, 0x00);
1382 outb(iobase + com_ier, 0);
1383 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1384 failures[7] = inb(iobase + com_ier);
1386 DELAY(1000); /* XXX */
1387 irqmap[3] = isa_irq_pending();
1389 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1391 if (iod.if_type == COM_IF_RSA98III) {
1392 inb(rsabase + rsa_srr);
1393 outb(rsabase + rsa_frr, 0x00);
1396 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1401 irqs = irqmap[1] & ~irqmap[0];
1402 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
1404 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1405 device_get_unit(dev), isa_get_irq(idev), irqs);
1407 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1408 device_get_unit(dev),
1409 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1412 for (fn = 0; fn < sizeof failures; ++fn)
1415 outb(iobase + (com_mcr << port_shift), 0);
1417 outb(iobase + com_mcr, 0);
1421 printf("sio%d: probe failed test(s):",
1422 device_get_unit(dev));
1423 for (fn = 0; fn < sizeof failures; ++fn)
1430 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1431 return (iobase == siocniobase ? 0 : result);
1436 espattach(com, esp_port)
1444 * Check the ESP-specific I/O port to see if we're an ESP
1445 * card. If not, return failure immediately.
1447 if ((inb(esp_port) & 0xf3) == 0) {
1448 printf(" port 0x%x is not an ESP board?\n", esp_port);
1453 * We've got something that claims to be a Hayes ESP card.
1457 /* Get the dip-switch configuration */
1459 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1460 dips = inb(esp_port + ESP98_STATUS1);
1462 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1463 dips = inb(esp_port + ESP_STATUS1);
1467 * Bits 0,1 of dips say which COM port we are.
1470 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1472 if (com->iobase == likely_com_ports[dips & 0x03])
1476 printf(" esp_port has com %d\n", dips & 0x03);
1481 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1484 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1485 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1486 val = inb(esp_port + ESP98_STATUS2);
1488 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1489 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1490 val = inb(esp_port + ESP_STATUS2);
1492 if ((val & 0x70) < 0x20) {
1493 printf("-old (%o)", val & 0x70);
1498 * Check for ability to emulate 16550: bit 7 == 1
1500 if ((dips & 0x80) == 0) {
1506 * Okay, we seem to be a Hayes ESP card. Whee.
1509 com->esp_port = esp_port;
1512 #endif /* COM_ESP */
1525 u_int flags = device_get_flags(dev);
1527 struct resource *port;
1536 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1537 0, ~0, 1, RF_ACTIVE); /* XXX */
1539 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1540 0, ~0, IO_COMSIZE, RF_ACTIVE);
1545 iobase = rman_get_start(port);
1547 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1550 unit = device_get_unit(dev);
1551 com = device_get_softc(dev);
1554 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1556 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL)
1558 bzero(obuf, obufsize * 2);
1562 * sioprobe() has initialized the device registers as follows:
1563 * o cfcr = CFCR_8BITS.
1564 * It is most important that CFCR_DLAB is off, so that the
1565 * data port is not hidden when we enable interrupts.
1567 * Interrupts are only enabled when the line is open.
1568 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1569 * interrupt control register or the config specifies no irq.
1570 * Keeping MCR_DTR and MCR_RTS off might stop the external
1571 * device from sending before we are ready.
1573 bzero(com, sizeof *com);
1575 com->obufsize = obufsize;
1577 com->obuf2 = obuf + obufsize;
1580 com->ioportres = port;
1581 com->cfcr_image = CFCR_8BITS;
1582 com->dtr_wait = 3 * hz;
1583 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1584 com->no_irq = isa_get_irq(dev) < 0;
1585 com->tx_fifo_size = 1;
1586 com->obufs[0].l_head = com->obuf1;
1587 com->obufs[1].l_head = com->obuf2;
1589 com->iobase = iobase;
1591 if (pc98_set_ioport(com, device_get_flags(dev)) == -1) {
1592 com->pc98_if_type = (device_get_flags(dev) >> 24) & 0xff;
1593 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1594 com->data_port = iobase + (com_data << port_shift);
1595 com->int_id_port = iobase + (com_iir << port_shift);
1596 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1597 com->mcr_image = inb(com->modem_ctl_port);
1598 com->line_status_port = iobase + (com_lsr << port_shift);
1599 com->modem_status_port = iobase + (com_msr << port_shift);
1600 com->intr_ctl_port = iobase + (com_ier << port_shift);
1602 #else /* not PC98 */
1603 com->data_port = iobase + com_data;
1604 com->int_id_port = iobase + com_iir;
1605 com->modem_ctl_port = iobase + com_mcr;
1606 com->mcr_image = inb(com->modem_ctl_port);
1607 com->line_status_port = iobase + com_lsr;
1608 com->modem_status_port = iobase + com_msr;
1609 com->intr_ctl_port = iobase + com_ier;
1613 * We don't use all the flags from <sys/ttydefaults.h> since they
1614 * are only relevant for logins. It's important to have echo off
1615 * initially so that the line doesn't start blathering before the
1616 * echo flag can be turned off.
1618 com->it_in.c_iflag = 0;
1619 com->it_in.c_oflag = 0;
1620 com->it_in.c_cflag = TTYDEF_CFLAG;
1621 com->it_in.c_lflag = 0;
1622 if (unit == comconsole) {
1624 if (IS_8251(com->pc98_if_type))
1627 com->it_in.c_iflag = TTYDEF_IFLAG;
1628 com->it_in.c_oflag = TTYDEF_OFLAG;
1629 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1630 com->it_in.c_lflag = TTYDEF_LFLAG;
1631 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1632 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1633 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1634 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1636 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1637 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1639 free(com, M_DEVBUF);
1643 termioschars(&com->it_in);
1644 com->it_out = com->it_in;
1646 /* attempt to determine UART type */
1647 printf("sio%d: type", unit);
1651 #ifdef COM_MULTIPORT
1652 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1654 if (!COM_IIR_TXRDYBUG(flags))
1661 scr = inb(iobase + com_scr);
1662 outb(iobase + com_scr, 0xa5);
1663 scr1 = inb(iobase + com_scr);
1664 outb(iobase + com_scr, 0x5a);
1665 scr2 = inb(iobase + com_scr);
1666 outb(iobase + com_scr, scr);
1667 if (scr1 != 0xa5 || scr2 != 0x5a) {
1669 goto determined_type;
1674 if (IS_8251(com->pc98_if_type)) {
1675 com_int_TxRx_disable( com );
1676 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1677 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1678 com_send_break_off( com );
1679 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1681 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1683 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1687 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1698 if (COM_NOFIFO(flags)) {
1699 printf(" 16550A fifo disabled");
1701 com->hasfifo = TRUE;
1703 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1706 if (COM_ST16650A(flags)) {
1708 com->tx_fifo_size = 32;
1709 printf(" ST16650A");
1711 com->tx_fifo_size = COM_FIFOSIZE(flags);
1717 if (com->pc98_if_type == COM_IF_RSA98III) {
1718 com->tx_fifo_size = 2048;
1719 com->rsabase = isa_get_port(dev);
1720 outb(com->rsabase + rsa_ier, 0x00);
1721 outb(com->rsabase + rsa_frr, 0x00);
1727 if (com->pc98_if_type == COM_IF_ESP98)
1729 for (espp = likely_esp_ports; *espp != 0; espp++)
1730 if (espattach(com, *espp)) {
1731 com->tx_fifo_size = 1024;
1735 if (!com->st16650a) {
1736 if (!com->tx_fifo_size)
1737 com->tx_fifo_size = 16;
1739 printf(" lookalike with %d bytes FIFO",
1747 if (com->pc98_if_type == COM_IF_RSB3000) {
1748 /* Set RSB-2000/3000 Extended Buffer mode. */
1750 lcr = inb(iobase + (com_cfcr << port_shift));
1751 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1752 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1753 outb(iobase + (com_cfcr << port_shift), lcr);
1760 * Set 16550 compatibility mode.
1761 * We don't use the ESP_MODE_SCALE bit to increase the
1762 * fifo trigger levels because we can't handle large
1764 * XXX flow control should be set in comparam(), not here.
1767 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1768 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1770 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1771 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1774 /* Set RTS/CTS flow control. */
1776 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1777 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1778 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1780 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1781 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1782 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1785 /* Set flow-control levels. */
1787 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1788 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1789 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1790 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1791 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1793 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1794 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1795 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1796 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1797 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1801 /* Set UART clock prescaler. */
1802 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1803 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1806 #endif /* COM_ESP */
1808 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1809 outb(iobase + (com_fifo << port_shift), 0);
1811 outb(iobase + com_fifo, 0);
1815 #ifdef COM_MULTIPORT
1816 if (COM_ISMULTIPORT(flags)) {
1817 com->multiport = TRUE;
1818 printf(" (multiport");
1819 if (unit == COM_MPMASTER(flags))
1823 isa_get_irq(devclass_get_device
1824 (sio_devclass, COM_MPMASTER(flags))) < 0;
1826 #endif /* COM_MULTIPORT */
1830 if (unit == comconsole)
1831 printf(", console");
1832 if ( COM_IIR_TXRDYBUG(flags) )
1833 printf(" with a bogus IIR_TXRDY register");
1836 if (!sio_registered) {
1837 register_swi(SWI_TTY, siopoll);
1838 sio_registered = TRUE;
1840 make_dev(&sio_cdevsw, unit,
1841 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1842 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
1843 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1844 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
1845 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1846 make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
1847 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1848 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE,
1849 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1850 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
1851 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1853 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1854 pps_init(&com->pps);
1857 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
1858 RF_SHAREABLE | RF_ACTIVE);
1859 BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
1860 INTR_TYPE_TTY | INTR_TYPE_FAST,
1867 sioopen(dev, flag, mode, p)
1885 unit = MINOR_TO_UNIT(mynor);
1886 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1890 if (mynor & CONTROL_MASK)
1892 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
1896 if (!IS_8251(com->pc98_if_type))
1897 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1900 * We jump to this label after all non-interrupted sleeps to pick
1901 * up any changes of the device state.
1904 while (com->state & CS_DTR_OFF) {
1905 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1906 if (com_addr(unit) == NULL)
1908 if (error != 0 || com->gone)
1911 if (tp->t_state & TS_ISOPEN) {
1913 * The device is open, so everything has been initialized.
1916 if (mynor & CALLOUT_MASK) {
1917 if (!com->active_out) {
1922 if (com->active_out) {
1923 if (flag & O_NONBLOCK) {
1927 error = tsleep(&com->active_out,
1928 TTIPRI | PCATCH, "siobi", 0);
1929 if (com_addr(unit) == NULL)
1931 if (error != 0 || com->gone)
1936 if (tp->t_state & TS_XCLUDE &&
1943 * The device isn't open, so there are no conflicts.
1944 * Initialize it. Initialization is done twice in many
1945 * cases: to preempt sleeping callin opens if we are
1946 * callout, and to complete a callin open after DCD rises.
1948 tp->t_oproc = comstart;
1949 tp->t_param = comparam;
1951 tp->t_termios = mynor & CALLOUT_MASK
1952 ? com->it_out : com->it_in;
1954 if (!IS_8251(com->pc98_if_type))
1956 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1957 com->poll = com->no_irq;
1958 com->poll_output = com->loses_outints;
1960 error = comparam(tp, &tp->t_termios);
1965 if (IS_8251(com->pc98_if_type)) {
1966 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1967 pc98_msrint_start(dev);
1971 * XXX we should goto open_top if comparam() slept.
1973 iobase = com->iobase;
1976 * (Re)enable and drain fifos.
1978 * Certain SMC chips cause problems if the fifos
1979 * are enabled while input is ready. Turn off the
1980 * fifo if necessary to clear the input. We test
1981 * the input ready bit after enabling the fifos
1982 * since we've already enabled them in comparam()
1983 * and to handle races between enabling and fresh
1988 outb(iobase + (com_fifo << port_shift),
1989 FIFO_RCV_RST | FIFO_XMT_RST
1991 if (com->pc98_if_type == COM_IF_RSA98III)
1992 outb(com->rsabase + rsa_frr , 0x00);
1994 outb(iobase + com_fifo,
1995 FIFO_RCV_RST | FIFO_XMT_RST
1999 * XXX the delays are for superstitious
2000 * historical reasons. It must be less than
2001 * the character time at the maximum
2002 * supported speed (87 usec at 115200 bps
2003 * 8N1). Otherwise we might loop endlessly
2004 * if data is streaming in. We used to use
2005 * delays of 100. That usually worked
2006 * because DELAY(100) used to usually delay
2007 * for about 85 usec instead of 100.
2011 if (!(inb(com->line_status_port) & LSR_RXRDY))
2013 if (com->pc98_if_type == COM_IF_RSA98III
2014 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2015 : !(inb(com->line_status_port) & LSR_RXRDY))
2019 outb(iobase + (com_fifo << port_shift), 0);
2021 outb(iobase + com_fifo, 0);
2024 (void) inb(com->data_port);
2030 if (IS_8251(com->pc98_if_type)) {
2031 com_tiocm_bis(com, TIOCM_LE);
2032 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2033 com_int_Rx_enable(com);
2036 (void) inb(com->line_status_port);
2037 (void) inb(com->data_port);
2038 com->prev_modem_status = com->last_modem_status
2039 = inb(com->modem_status_port);
2040 if (COM_IIR_TXRDYBUG(com->flags)) {
2041 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2044 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2045 | IER_ERLS | IER_EMSC);
2048 if (com->pc98_if_type == COM_IF_RSA98III) {
2049 outb(com->rsabase + rsa_ier, 0x1d);
2050 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2058 * Handle initial DCD. Callout devices get a fake initial
2059 * DCD (trapdoor DCD). If we are callout, then any sleeping
2060 * callin opens get woken up and resume sleeping on "siobi"
2061 * instead of "siodcd".
2064 * XXX `mynor & CALLOUT_MASK' should be
2065 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2066 * TRAPDOOR_CARRIER is the default initial state for callout
2067 * devices and SOFT_CARRIER is like CLOCAL except it hides
2071 if ((IS_8251(com->pc98_if_type) &&
2072 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2073 (!IS_8251(com->pc98_if_type) &&
2074 (com->prev_modem_status & MSR_DCD)) ||
2075 mynor & CALLOUT_MASK)
2077 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2079 (*linesw[tp->t_line].l_modem)(tp, 1);
2082 * Wait for DCD if necessary.
2084 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2085 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2087 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2088 if (com_addr(unit) == NULL)
2091 if (error != 0 || com->gone)
2095 error = (*linesw[tp->t_line].l_open)(dev, tp);
2096 disc_optim(tp, &tp->t_termios, com);
2097 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2098 com->active_out = TRUE;
2102 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2108 sioclose(dev, flag, mode, p)
2120 if (mynor & CONTROL_MASK)
2122 com = com_addr(MINOR_TO_UNIT(mynor));
2125 (*linesw[tp->t_line].l_close)(tp, flag);
2127 com->modem_checking = 0;
2129 disc_optim(tp, &tp->t_termios, com);
2130 siostop(tp, FREAD | FWRITE);
2136 printf("sio%d: gone\n", com->unit);
2138 if (com->ibuf != NULL)
2139 free(com->ibuf, M_DEVBUF);
2140 bzero(tp, sizeof *tp);
2141 free(com, M_DEVBUF);
2160 iobase = com->iobase;
2163 com->poll_output = FALSE;
2164 com->do_timestamp = FALSE;
2165 com->do_dcd_timestamp = FALSE;
2166 com->pps.ppsparam.mode = 0;
2168 if (IS_8251(com->pc98_if_type))
2169 com_send_break_off(com);
2171 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2172 outb(iobase + (com_cfcr << port_shift),
2173 com->cfcr_image &= ~CFCR_SBREAK);
2176 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2181 if (IS_8251(com->pc98_if_type))
2182 com_int_TxRx_disable(com);
2184 outb(iobase + (com_ier << port_shift), 0);
2185 if (com->pc98_if_type == COM_IF_RSA98III) {
2186 outb(com->rsabase + rsa_ier, 0x00);
2189 outb(iobase + com_ier, 0);
2193 if (IS_8251(com->pc98_if_type))
2194 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2196 tmp = com->prev_modem_status & MSR_DCD;
2198 if (tp->t_cflag & HUPCL
2200 * XXX we will miss any carrier drop between here and the
2201 * next open. Perhaps we should watch DCD even when the
2202 * port is closed; it is not sufficient to check it at
2203 * the next open because it might go up and down while
2204 * we're not watching.
2206 || (!com->active_out
2210 && !(com->prev_modem_status & MSR_DCD)
2212 && !(com->it_in.c_cflag & CLOCAL))
2213 || !(tp->t_state & TS_ISOPEN)) {
2215 if (IS_8251(com->pc98_if_type))
2216 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2219 (void)commctl(com, TIOCM_DTR, DMBIC);
2220 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2221 timeout(siodtrwakeup, com, com->dtr_wait);
2222 com->state |= CS_DTR_OFF;
2227 if (IS_8251(com->pc98_if_type))
2228 com_tiocm_bic(com, TIOCM_LE );
2234 * Disable fifos so that they are off after controlled
2235 * reboots. Some BIOSes fail to detect 16550s when the
2236 * fifos are enabled.
2239 outb(iobase + (com_fifo << port_shift), 0);
2241 outb(iobase + com_fifo, 0);
2244 com->active_out = FALSE;
2245 wakeup(&com->active_out);
2246 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2251 sioread(dev, uio, flag)
2260 if (mynor & CONTROL_MASK)
2262 com = com_addr(MINOR_TO_UNIT(mynor));
2265 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
2269 siowrite(dev, uio, flag)
2279 if (mynor & CONTROL_MASK)
2282 unit = MINOR_TO_UNIT(mynor);
2283 com = com_addr(unit);
2287 * (XXX) We disallow virtual consoles if the physical console is
2288 * a serial port. This is in case there is a display attached that
2289 * is not the console. In that situation we don't need/want the X
2290 * server taking over the console.
2292 if (constty != NULL && unit == comconsole)
2294 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
2304 com = (struct com_s *)chan;
2307 * Clear TS_BUSY if low-level output is complete.
2308 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2309 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2310 * called again. Reading the line status port outside of siointr1()
2311 * is safe because CS_BUSY is clear so there are no output interrupts
2315 if (com->state & CS_BUSY)
2316 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2318 else if ((IS_8251(com->pc98_if_type) &&
2319 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2320 == (STS8251_TxRDY | STS8251_TxEMP)) ||
2321 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2322 == (LSR_TSRE | LSR_TXRDY)) {
2324 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2325 == (LSR_TSRE | LSR_TXRDY)) {
2327 com->tp->t_state &= ~TS_BUSY;
2329 com->extra_state &= ~CSE_BUSYCHECK;
2331 timeout(siobusycheck, com, hz / 100);
2341 com = (struct com_s *)chan;
2342 com->state &= ~CS_DTR_OFF;
2343 wakeup(&com->dtr_wait);
2361 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2362 com_events -= (com->iptr - com->ibuf);
2363 com->iptr = com->ibuf;
2366 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2368 * Avoid the grotesquely inefficient lineswitch routine
2369 * (ttyinput) in "raw" mode. It usually takes about 450
2370 * instructions (that's without canonical processing or echo!).
2371 * slinput is reasonably fast (usually 40 instructions plus
2376 incc = com->iptr - buf;
2377 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2378 && (com->state & CS_RTS_IFLOW
2379 || tp->t_iflag & IXOFF)
2380 && !(tp->t_state & TS_TBLOCK))
2382 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2383 += b_to_q((char *)buf, incc, &tp->t_rawq);
2387 tp->t_rawcc += incc;
2389 if (tp->t_state & TS_TTSTOP
2390 && (tp->t_iflag & IXANY
2391 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2392 tp->t_state &= ~TS_TTSTOP;
2393 tp->t_lflag &= ~FLUSHO;
2397 } while (buf < com->iptr);
2401 line_status = buf[com->ierroff];
2404 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2405 if (line_status & LSR_BI)
2406 recv_data |= TTY_BI;
2407 if (line_status & LSR_FE)
2408 recv_data |= TTY_FE;
2409 if (line_status & LSR_OE)
2410 recv_data |= TTY_OE;
2411 if (line_status & LSR_PE)
2412 recv_data |= TTY_PE;
2414 (*linesw[tp->t_line].l_rint)(recv_data, tp);
2416 } while (buf < com->iptr);
2418 com_events -= (com->iptr - com->ibuf);
2419 com->iptr = com->ibuf;
2422 * There is now room for another low-level buffer full of input,
2423 * so enable RTS if it is now disabled and there is room in the
2424 * high-level buffer.
2427 if (IS_8251(com->pc98_if_type))
2428 tmp = com_tiocm_get(com) & TIOCM_RTS;
2430 tmp = com->mcr_image & MCR_RTS;
2431 if ((com->state & CS_RTS_IFLOW) && !(tmp) &&
2432 !(tp->t_state & TS_TBLOCK))
2433 if (IS_8251(com->pc98_if_type))
2434 com_tiocm_bis(com, TIOCM_RTS);
2436 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2438 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2439 !(tp->t_state & TS_TBLOCK))
2440 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2448 #ifndef COM_MULTIPORT
2450 siointr1((struct com_s *) arg);
2452 #else /* COM_MULTIPORT */
2453 bool_t possibly_more_intrs;
2457 u_char rsa_buf_status;
2461 * Loop until there is no activity on any port. This is necessary
2462 * to get an interrupt edge more than to avoid another interrupt.
2463 * If the IRQ signal is just an OR of the IRQ signals from several
2464 * devices, then the edge from one may be lost because another is
2469 possibly_more_intrs = FALSE;
2470 for (unit = 0; unit < NSIOTOT; ++unit) {
2471 com = com_addr(unit);
2474 * would it work here, or be counter-productive?
2479 && IS_8251(com->pc98_if_type)){
2486 && com->pc98_if_type == COM_IF_RSA98III) {
2487 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2488 if ((rsa_buf_status & 0xc8)
2489 || !(rsa_buf_status & 0x01)) {
2492 != (inb(com->rsabase + rsa_srr) & 0xc9))
2493 possibly_more_intrs = TRUE;
2499 && (inb(com->int_id_port) & IIR_IMASK)
2502 possibly_more_intrs = TRUE;
2504 /* XXX COM_UNLOCK(); */
2506 } while (possibly_more_intrs);
2508 #endif /* COM_MULTIPORT */
2516 u_char modem_status;
2521 struct timecounter *tc;
2526 u_char rsa_buf_status = 0;
2527 int rsa_tx_fifo_size=0;
2531 int_ctl = inb(com->intr_ctl_port);
2532 int_ctl_new = int_ctl;
2534 while (!com->gone) {
2537 if (IS_8251(com->pc98_if_type)) {
2538 tmp = inb(com->sts_port);
2541 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2542 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2543 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2544 if (tmp & STS8251_PE) line_status |= LSR_PE;
2545 if (tmp & STS8251_OE) line_status |= LSR_OE;
2546 if (tmp & STS8251_FE) line_status |= LSR_FE;
2547 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2550 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2551 modem_status = inb(com->modem_status_port);
2552 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2554 count = tc->tc_get_timecount(tc);
2555 pps_event(&com->pps, tc, count,
2556 (modem_status & MSR_DCD) ?
2557 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2560 line_status = inb(com->line_status_port);
2563 if (com->pc98_if_type == COM_IF_RSA98III)
2564 rsa_buf_status = inb(com->rsabase + rsa_srr);
2567 /* input event? (check first to help avoid overruns) */
2569 while (line_status & LSR_RCV_MASK) {
2571 while ((line_status & LSR_RCV_MASK)
2572 || (com->pc98_if_type == COM_IF_RSA98III
2573 && (rsa_buf_status & 0x08))) {
2575 /* break/unnattached error bits or real input? */
2577 if (IS_8251(com->pc98_if_type)) {
2578 recv_data = inb(com->data_port);
2580 pc98_i8251_or_cmd(com,CMD8251_ER);
2586 if (com->pc98_if_type == COM_IF_RSA98III) {
2587 if (!(rsa_buf_status & 0x08))
2590 recv_data = inb(com->data_port);
2594 if (!(line_status & LSR_RXRDY))
2597 recv_data = inb(com->data_port);
2601 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2603 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2604 * Otherwise, push the work to a higher level
2605 * (to handle PARMRK) if we're bypassing.
2606 * Otherwise, convert BI/FE and PE+INPCK to 0.
2608 * This makes bypassing work right in the
2609 * usual "raw" case (IGNBRK set, and IGNPAR
2612 * Note: BI together with FE/PE means just BI.
2614 if (line_status & LSR_BI) {
2615 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2616 if (com->unit == comconsole) {
2622 || com->tp->t_iflag & IGNBRK)
2626 || com->tp->t_iflag & IGNPAR)
2629 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2630 && (line_status & (LSR_BI | LSR_FE)
2631 || com->tp->t_iflag & INPCK))
2635 if (com->hotchar != 0 && recv_data == com->hotchar)
2638 if (ioptr >= com->ibufend)
2639 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2641 if (com->do_timestamp)
2642 microtime(&com->timestamp);
2645 #if 0 /* for testing input latency vs efficiency */
2646 if (com->iptr - com->ibuf == 8)
2649 ioptr[0] = recv_data;
2650 ioptr[com->ierroff] = line_status;
2651 com->iptr = ++ioptr;
2652 if (ioptr == com->ihighwater
2653 && com->state & CS_RTS_IFLOW)
2655 if (IS_8251(com->pc98_if_type))
2656 com_tiocm_bic(com, TIOCM_RTS);
2659 outb(com->modem_ctl_port,
2660 com->mcr_image &= ~MCR_RTS);
2661 if (line_status & LSR_OE)
2662 CE_RECORD(com, CE_OVERRUN);
2666 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2667 * jump from the top of the loop to here
2670 if (IS_8251(com->pc98_if_type))
2674 line_status = inb(com->line_status_port) & 0x7F;
2676 if (com->pc98_if_type == COM_IF_RSA98III)
2677 rsa_buf_status = inb(com->rsabase + rsa_srr);
2681 /* modem status change? (always check before doing output) */
2683 if (!IS_8251(com->pc98_if_type)) {
2685 modem_status = inb(com->modem_status_port);
2686 if (modem_status != com->last_modem_status) {
2687 if (com->do_dcd_timestamp
2688 && !(com->last_modem_status & MSR_DCD)
2689 && modem_status & MSR_DCD)
2690 microtime(&com->dcd_timestamp);
2693 * Schedule high level to handle DCD changes. Note
2694 * that we don't use the delta bits anywhere. Some
2695 * UARTs mess them up, and it's easy to remember the
2696 * previous bits and calculate the delta.
2698 com->last_modem_status = modem_status;
2699 if (!(com->state & CS_CHECKMSR)) {
2700 com_events += LOTS_OF_EVENTS;
2701 com->state |= CS_CHECKMSR;
2705 /* handle CTS change immediately for crisp flow ctl */
2706 if (com->state & CS_CTS_OFLOW) {
2707 if (modem_status & MSR_CTS)
2708 com->state |= CS_ODEVREADY;
2710 com->state &= ~CS_ODEVREADY;
2717 /* output queued and everything ready? */
2719 if (line_status & LSR_TXRDY
2720 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2722 if (((com->pc98_if_type == COM_IF_RSA98III)
2723 ? (rsa_buf_status & 0x02)
2724 : (line_status & LSR_TXRDY))
2725 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2727 ioptr = com->obufq.l_head;
2728 if (com->tx_fifo_size > 1) {
2731 ocount = com->obufq.l_tail - ioptr;
2733 if (com->pc98_if_type == COM_IF_RSA98III) {
2734 rsa_buf_status = inb(com->rsabase + rsa_srr);
2735 rsa_tx_fifo_size = 1024;
2736 if (!(rsa_buf_status & 0x01))
2737 rsa_tx_fifo_size = 2048;
2738 if (ocount > rsa_tx_fifo_size)
2739 ocount = rsa_tx_fifo_size;
2742 if (ocount > com->tx_fifo_size)
2743 ocount = com->tx_fifo_size;
2744 com->bytes_out += ocount;
2746 outb(com->data_port, *ioptr++);
2747 while (--ocount != 0);
2749 outb(com->data_port, *ioptr++);
2753 if (IS_8251(com->pc98_if_type))
2754 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2755 com_int_Tx_enable(com);
2757 com->obufq.l_head = ioptr;
2758 if (COM_IIR_TXRDYBUG(com->flags)) {
2759 int_ctl_new = int_ctl | IER_ETXRDY;
2761 if (ioptr >= com->obufq.l_tail) {
2764 qp = com->obufq.l_next;
2765 qp->l_queued = FALSE;
2768 com->obufq.l_head = qp->l_head;
2769 com->obufq.l_tail = qp->l_tail;
2770 com->obufq.l_next = qp;
2772 /* output just completed */
2773 if ( COM_IIR_TXRDYBUG(com->flags) ) {
2774 int_ctl_new = int_ctl & ~IER_ETXRDY;
2776 com->state &= ~CS_BUSY;
2778 if (IS_8251(com->pc98_if_type))
2779 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2780 com_int_Tx_disable(com);
2783 if (!(com->state & CS_ODONE)) {
2784 com_events += LOTS_OF_EVENTS;
2785 com->state |= CS_ODONE;
2786 setsofttty(); /* handle at high level ASAP */
2789 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2791 if (com->pc98_if_type == COM_IF_RSA98III) {
2792 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2793 outb(com->intr_ctl_port, int_ctl_new);
2794 outb(com->rsabase + rsa_ier, 0x1d);
2797 outb(com->intr_ctl_port, int_ctl_new);
2801 else if (line_status & LSR_TXRDY) {
2802 if (IS_8251(com->pc98_if_type))
2803 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2804 com_int_Tx_disable(com);
2806 if (IS_8251(com->pc98_if_type))
2807 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2812 #ifndef COM_MULTIPORT
2814 if (IS_8251(com->pc98_if_type))
2817 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2818 #endif /* COM_MULTIPORT */
2824 sioioctl(dev, cmd, data, flag, p)
2837 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2839 struct termios term;
2843 com = com_addr(MINOR_TO_UNIT(mynor));
2846 iobase = com->iobase;
2847 if (mynor & CONTROL_MASK) {
2850 switch (mynor & CONTROL_MASK) {
2851 case CONTROL_INIT_STATE:
2852 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2854 case CONTROL_LOCK_STATE:
2855 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2858 return (ENODEV); /* /dev/nodev */
2865 *ct = *(struct termios *)data;
2868 *(struct termios *)data = *ct;
2871 *(int *)data = TTYDISC;
2874 bzero(data, sizeof(struct winsize));
2881 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2882 term = tp->t_termios;
2884 error = ttsetcompat(tp, &cmd, data, &term);
2888 data = (caddr_t)&term;
2890 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2892 struct termios *dt = (struct termios *)data;
2893 struct termios *lt = mynor & CALLOUT_MASK
2894 ? &com->lt_out : &com->lt_in;
2896 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2897 | (dt->c_iflag & ~lt->c_iflag);
2898 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2899 | (dt->c_oflag & ~lt->c_oflag);
2900 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2901 | (dt->c_cflag & ~lt->c_cflag);
2902 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2903 | (dt->c_lflag & ~lt->c_lflag);
2904 for (cc = 0; cc < NCCS; ++cc)
2905 if (lt->c_cc[cc] != 0)
2906 dt->c_cc[cc] = tp->t_cc[cc];
2907 if (lt->c_ispeed != 0)
2908 dt->c_ispeed = tp->t_ispeed;
2909 if (lt->c_ospeed != 0)
2910 dt->c_ospeed = tp->t_ospeed;
2912 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2913 if (error != ENOIOCTL)
2916 error = ttioctl(tp, cmd, data, flag);
2917 disc_optim(tp, &tp->t_termios, com);
2918 if (error != ENOIOCTL) {
2923 if (IS_8251(com->pc98_if_type)) {
2926 com_send_break_on( com );
2929 com_send_break_off( com );
2932 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
2935 com_tiocm_bic(com, TIOCM_DTR);
2938 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2939 * changes get undone on the next call to comparam().
2942 com_tiocm_set( com, *(int *)data );
2945 com_tiocm_bis( com, *(int *)data );
2948 com_tiocm_bic( com, *(int *)data );
2951 *(int *)data = com_tiocm_get(com);
2954 /* must be root since the wait applies to following logins */
2960 com->dtr_wait = *(int *)data * hz / 100;
2963 *(int *)data = com->dtr_wait * 100 / hz;
2966 com->do_timestamp = TRUE;
2967 *(struct timeval *)data = com->timestamp;
2969 case TIOCDCDTIMESTAMP:
2970 com->do_dcd_timestamp = TRUE;
2971 *(struct timeval *)data = com->dcd_timestamp;
2979 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2984 outb(iobase + (com_cfcr << port_shift),
2985 com->cfcr_image |= CFCR_SBREAK);
2987 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2992 outb(iobase + (com_cfcr << port_shift),
2993 com->cfcr_image &= ~CFCR_SBREAK);
2995 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2999 (void)commctl(com, TIOCM_DTR, DMBIS);
3002 (void)commctl(com, TIOCM_DTR, DMBIC);
3005 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3006 * changes get undone on the next call to comparam().
3009 (void)commctl(com, *(int *)data, DMSET);
3012 (void)commctl(com, *(int *)data, DMBIS);
3015 (void)commctl(com, *(int *)data, DMBIC);
3018 *(int *)data = commctl(com, 0, DMGET);
3021 /* must be root since the wait applies to following logins */
3027 com->dtr_wait = *(int *)data * hz / 100;
3030 *(int *)data = com->dtr_wait * 100 / hz;
3033 com->do_timestamp = TRUE;
3034 *(struct timeval *)data = com->timestamp;
3036 case TIOCDCDTIMESTAMP:
3037 com->do_dcd_timestamp = TRUE;
3038 *(struct timeval *)data = com->dcd_timestamp;
3042 error = pps_ioctl(cmd, data, &com->pps);
3043 if (error == ENODEV)
3059 if (com_events == 0)
3062 for (unit = 0; unit < NSIOTOT; ++unit) {
3067 com = com_addr(unit);
3071 if (tp == NULL || com->gone) {
3073 * Discard any events related to never-opened or
3074 * going-away devices.
3077 incc = com->iptr - com->ibuf;
3078 com->iptr = com->ibuf;
3079 if (com->state & CS_CHECKMSR) {
3080 incc += LOTS_OF_EVENTS;
3081 com->state &= ~CS_CHECKMSR;
3087 if (com->iptr != com->ibuf) {
3092 if (com->state & CS_CHECKMSR) {
3093 u_char delta_modem_status;
3096 if (!IS_8251(com->pc98_if_type)) {
3099 delta_modem_status = com->last_modem_status
3100 ^ com->prev_modem_status;
3101 com->prev_modem_status = com->last_modem_status;
3102 com_events -= LOTS_OF_EVENTS;
3103 com->state &= ~CS_CHECKMSR;
3105 if (delta_modem_status & MSR_DCD)
3106 (*linesw[tp->t_line].l_modem)
3107 (tp, com->prev_modem_status & MSR_DCD);
3112 if (com->state & CS_ODONE) {
3114 com_events -= LOTS_OF_EVENTS;
3115 com->state &= ~CS_ODONE;
3117 if (!(com->state & CS_BUSY)
3118 && !(com->extra_state & CSE_BUSYCHECK)) {
3119 timeout(siobusycheck, com, hz / 100);
3120 com->extra_state |= CSE_BUSYCHECK;
3122 (*linesw[tp->t_line].l_start)(tp);
3124 if (com_events == 0)
3127 if (com_events >= LOTS_OF_EVENTS)
3152 unit = DEV_TO_UNIT(tp->t_dev);
3153 com = com_addr(unit);
3154 iobase = com->iobase;
3155 if (IS_8251(com->pc98_if_type)) {
3156 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3158 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3160 /* do historical conversions */
3161 if (t->c_ispeed == 0)
3162 t->c_ispeed = t->c_ospeed;
3164 /* check requested parameters */
3165 divisor = ttspeedtab(t->c_ospeed,
3166 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3169 /* do historical conversions */
3170 if (t->c_ispeed == 0)
3171 t->c_ispeed = t->c_ospeed;
3173 /* check requested parameters */
3174 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3176 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
3179 /* parameters are OK, convert them to the com struct and the device */
3181 unit = DEV_TO_UNIT(tp->t_dev);
3182 com = com_addr(unit);
3183 iobase = com->iobase;
3187 if (IS_8251(com->pc98_if_type)) {
3189 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3191 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3195 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3197 (void)commctl(com, TIOCM_DTR, DMBIS);
3203 if (!IS_8251(com->pc98_if_type)) {
3205 switch (cflag & CSIZE) {
3219 if (cflag & PARENB) {
3221 if (!(cflag & PARODD))
3227 if (com->hasfifo && divisor != 0) {
3229 * Use a fifo trigger level low enough so that the input
3230 * latency from the fifo is less than about 16 msec and
3231 * the total latency is less than about 30 msec. These
3232 * latencies are reasonable for humans. Serial comms
3233 * protocols shouldn't expect anything better since modem
3234 * latencies are larger.
3236 com->fifo_image = t->c_ospeed <= 4800
3237 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3240 * The Hayes ESP card needs the fifo DMA mode bit set
3241 * in compatibility mode. If not, it will interrupt
3242 * for each character received.
3245 com->fifo_image |= FIFO_DMA_MODE;
3248 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3250 outb(iobase + com_fifo, com->fifo_image);
3258 * This returns with interrupts disabled so that we can complete
3259 * the speed change atomically. Keeping interrupts disabled is
3260 * especially important while com_data is hidden.
3262 (void) siosetwater(com, t->c_ispeed);
3265 if (IS_8251(com->pc98_if_type))
3266 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3271 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3273 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3276 * Only set the divisor registers if they would change,
3277 * since on some 16550 incompatibles (UMC8669F), setting
3278 * them while input is arriving them loses sync until
3279 * data stops arriving.
3281 dlbl = divisor & 0xFF;
3283 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3284 outb(iobase + (com_dlbl << port_shift), dlbl);
3285 dlbh = (u_int) divisor >> 8;
3286 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3287 outb(iobase + (com_dlbh << port_shift), dlbh);
3289 if (inb(iobase + com_dlbl) != dlbl)
3290 outb(iobase + com_dlbl, dlbl);
3291 dlbh = (u_int) divisor >> 8;
3292 if (inb(iobase + com_dlbh) != dlbh)
3293 outb(iobase + com_dlbh, dlbh);
3300 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3302 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3305 if (!(tp->t_state & TS_TTSTOP))
3306 com->state |= CS_TTGO;
3308 if (cflag & CRTS_IFLOW) {
3309 if (com->st16650a) {
3310 outb(iobase + com_cfcr, 0xbf);
3311 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3313 com->state |= CS_RTS_IFLOW;
3315 * If CS_RTS_IFLOW just changed from off to on, the change
3316 * needs to be propagated to MCR_RTS. This isn't urgent,
3317 * so do it later by calling comstart() instead of repeating
3318 * a lot of code from comstart() here.
3320 } else if (com->state & CS_RTS_IFLOW) {
3321 com->state &= ~CS_RTS_IFLOW;
3323 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3324 * on here, since comstart() won't do it later.
3327 if (IS_8251(com->pc98_if_type))
3328 com_tiocm_bis(com, TIOCM_RTS);
3331 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3332 if (com->st16650a) {
3333 outb(iobase + com_cfcr, 0xbf);
3334 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3340 * Set up state to handle output flow control.
3341 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3342 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3344 com->state |= CS_ODEVREADY;
3345 com->state &= ~CS_CTS_OFLOW;
3347 if (com->pc98_if_type == COM_IF_RSA98III) {
3348 param = inb(com->rsabase + rsa_msr);
3349 outb(com->rsabase + rsa_msr, param & 0x14);
3352 if (cflag & CCTS_OFLOW) {
3353 com->state |= CS_CTS_OFLOW;
3355 if (IS_8251(com->pc98_if_type)) {
3356 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3357 com->state &= ~CS_ODEVREADY;
3361 if (com->pc98_if_type == COM_IF_RSA98III) {
3362 /* Set automatic flow control mode */
3363 outb(com->rsabase + rsa_msr, param | 0x08);
3366 if (!(com->last_modem_status & MSR_CTS))
3367 com->state &= ~CS_ODEVREADY;
3368 if (com->st16650a) {
3369 outb(iobase + com_cfcr, 0xbf);
3370 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3376 if (com->st16650a) {
3377 outb(iobase + com_cfcr, 0xbf);
3378 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3384 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3386 outb(iobase + com_cfcr, com->cfcr_image);
3390 /* XXX shouldn't call functions while intrs are disabled. */
3391 disc_optim(tp, t, com);
3393 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3394 * unconditionally, but that defeated the careful discarding of
3395 * stale input in sioopen().
3397 if (com->state >= (CS_BUSY | CS_TTGO))
3403 if (com->ibufold != NULL) {
3404 free(com->ibufold, M_DEVBUF);
3405 com->ibufold = NULL;
3411 siosetwater(com, speed)
3421 * Make the buffer size large enough to handle a softtty interrupt
3422 * latency of about 2 ticks without loss of throughput or data
3423 * (about 3 ticks if input flow control is not used or not honoured,
3424 * but a bit less for CS5-CS7 modes).
3426 cp4ticks = speed / 10 / hz * 4;
3427 for (ibufsize = 128; ibufsize < cp4ticks;)
3430 if (com->pc98_if_type == COM_IF_RSA98III)
3433 if (ibufsize == com->ibufsize) {
3439 * Allocate input buffer. The extra factor of 2 in the size is
3440 * to allow for an error byte for each input byte.
3442 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3448 /* Initialize non-critical variables. */
3449 com->ibufold = com->ibuf;
3450 com->ibufsize = ibufsize;
3453 tp->t_ififosize = 2 * ibufsize;
3454 tp->t_ispeedwat = (speed_t)-1;
3455 tp->t_ospeedwat = (speed_t)-1;
3459 * Read current input buffer, if any. Continue with interrupts
3463 if (com->iptr != com->ibuf)
3467 * Initialize critical variables, including input buffer watermarks.
3468 * The external device is asked to stop sending when the buffer
3469 * exactly reaches high water, or when the high level requests it.
3470 * The high level is notified immediately (rather than at a later
3471 * clock tick) when this watermark is reached.
3472 * The buffer size is chosen so the watermark should almost never
3474 * The low watermark is invisibly 0 since the buffer is always
3475 * emptied all at once.
3477 com->iptr = com->ibuf = ibuf;
3478 com->ibufend = ibuf + ibufsize;
3479 com->ierroff = ibufsize;
3480 com->ihighwater = ibuf + 3 * ibufsize / 4;
3495 unit = DEV_TO_UNIT(tp->t_dev);
3496 com = com_addr(unit);
3499 if (tp->t_state & TS_TTSTOP)
3500 com->state &= ~CS_TTGO;
3502 com->state |= CS_TTGO;
3503 if (tp->t_state & TS_TBLOCK) {
3505 if (IS_8251(com->pc98_if_type))
3506 tmp = com_tiocm_get(com) & TIOCM_RTS;
3508 tmp = com->mcr_image & MCR_RTS;
3509 if (tmp && (com->state & CS_RTS_IFLOW))
3511 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3514 if (IS_8251(com->pc98_if_type))
3515 com_tiocm_bic(com, TIOCM_RTS);
3518 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3521 if (IS_8251(com->pc98_if_type))
3522 tmp = com_tiocm_get(com) & TIOCM_RTS;
3524 tmp = com->mcr_image & MCR_RTS;
3525 if (!(tmp) && com->iptr < com->ihighwater
3526 && com->state & CS_RTS_IFLOW)
3528 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3529 && com->state & CS_RTS_IFLOW)
3532 if (IS_8251(com->pc98_if_type))
3533 com_tiocm_bis(com, TIOCM_RTS);
3536 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3539 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3542 /* if(IS_8251(com->pc98_if_type))
3543 com_int_Tx_enable(com); */
3548 if (tp->t_outq.c_cc != 0) {
3552 if (!com->obufs[0].l_queued) {
3553 com->obufs[0].l_tail
3554 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3560 com->obufs[0].l_next = NULL;
3561 com->obufs[0].l_queued = TRUE;
3563 if (com->state & CS_BUSY) {
3564 qp = com->obufq.l_next;
3565 while ((next = qp->l_next) != NULL)
3567 qp->l_next = &com->obufs[0];
3569 com->obufq.l_head = com->obufs[0].l_head;
3570 com->obufq.l_tail = com->obufs[0].l_tail;
3571 com->obufq.l_next = &com->obufs[0];
3572 com->state |= CS_BUSY;
3576 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3577 com->obufs[1].l_tail
3578 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3584 com->obufs[1].l_next = NULL;
3585 com->obufs[1].l_queued = TRUE;
3587 if (com->state & CS_BUSY) {
3588 qp = com->obufq.l_next;
3589 while ((next = qp->l_next) != NULL)
3591 qp->l_next = &com->obufs[1];
3593 com->obufq.l_head = com->obufs[1].l_head;
3594 com->obufq.l_tail = com->obufs[1].l_tail;
3595 com->obufq.l_next = &com->obufs[1];
3596 com->state |= CS_BUSY;
3600 tp->t_state |= TS_BUSY;
3603 if (com->state >= (CS_BUSY | CS_TTGO))
3604 siointr1(com); /* fake interrupt to start output */
3607 /* if(IS_8251(com->pc98_if_type))
3608 com_int_Tx_enable(com); */
3625 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3629 if (!IS_8251(com->pc98_if_type))
3630 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3636 /* XXX avoid h/w bug. */
3640 outb(com->iobase + (com_fifo << port_shift),
3641 FIFO_XMT_RST | com->fifo_image);
3642 if (com->pc98_if_type == COM_IF_RSA98III)
3643 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3644 outb(com->iobase + (com_fifo << port_shift),
3645 FIFO_XMT_RST | com->fifo_image);
3647 outb(com->iobase + com_fifo,
3648 FIFO_XMT_RST | com->fifo_image);
3650 com->obufs[0].l_queued = FALSE;
3651 com->obufs[1].l_queued = FALSE;
3652 if (com->state & CS_ODONE)
3653 com_events -= LOTS_OF_EVENTS;
3654 com->state &= ~(CS_ODONE | CS_BUSY);
3655 com->tp->t_state &= ~TS_BUSY;
3660 /* XXX avoid h/w bug. */
3664 if (com->pc98_if_type == COM_IF_RSA98III) {
3665 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3666 inb(com->data_port);
3668 outb(com->iobase + (com_fifo << port_shift),
3669 FIFO_RCV_RST | com->fifo_image);
3671 outb(com->iobase + com_fifo,
3672 FIFO_RCV_RST | com->fifo_image);
3674 com_events -= (com->iptr - com->ibuf);
3675 com->iptr = com->ibuf;
3689 if (mynor & CONTROL_MASK)
3691 unit = MINOR_TO_UNIT(mynor);
3692 if ((u_int) unit >= NSIOTOT)
3694 return (dev->si_tty);
3698 commctl(com, bits, how)
3707 bits = TIOCM_LE; /* XXX - always enabled while open */
3708 mcr = com->mcr_image;
3713 msr = com->prev_modem_status;
3721 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3722 * more volatile by reading the modem status a lot. Perhaps
3723 * we should latch both bits until the status is read here.
3725 if (msr & (MSR_RI | MSR_TERI))
3730 if (bits & TIOCM_DTR)
3732 if (bits & TIOCM_RTS)
3739 outb(com->modem_ctl_port,
3740 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3743 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3746 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3761 * Set our timeout period to 1 second if no polled devices are open.
3762 * Otherwise set it to max(1/200, 1/hz).
3763 * Enable timeouts iff some device is open.
3765 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3768 for (unit = 0; unit < NSIOTOT; ++unit) {
3769 com = com_addr(unit);
3770 if (com != NULL && com->tp != NULL
3771 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3773 if (com->poll || com->poll_output) {
3774 sio_timeout = hz > 200 ? hz / 200 : 1;
3780 sio_timeouts_until_log = hz / sio_timeout;
3781 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3784 /* Flush error messages, if any. */
3785 sio_timeouts_until_log = 1;
3786 comwakeup((void *)NULL);
3787 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3798 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3801 * Recover from lost output interrupts.
3802 * Poll any lines that don't use interrupts.
3804 for (unit = 0; unit < NSIOTOT; ++unit) {
3805 com = com_addr(unit);
3806 if (com != NULL && !com->gone
3807 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3815 * Check for and log errors, but not too often.
3817 if (--sio_timeouts_until_log > 0)
3819 sio_timeouts_until_log = hz / sio_timeout;
3820 for (unit = 0; unit < NSIOTOT; ++unit) {
3823 com = com_addr(unit);
3828 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3833 delta = com->delta_error_counts[errnum];
3834 com->delta_error_counts[errnum] = 0;
3838 total = com->error_counts[errnum] += delta;
3839 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3840 unit, delta, error_desc[errnum],
3841 delta == 1 ? "" : "s", total);
3847 /* commint is called when modem control line changes */
3851 register struct tty *tp;
3857 unit = MINOR_TO_UNIT(mynor);
3858 com = com_addr(unit);
3861 stat = com_tiocm_get(com);
3862 delta = com_tiocm_get_delta(com);
3864 if (com->state & CS_CTS_OFLOW) {
3865 if (stat & TIOCM_CTS)
3866 com->state |= CS_ODEVREADY;
3868 com->state &= ~CS_ODEVREADY;
3870 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3871 if (stat & TIOCM_CAR )
3872 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
3873 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
3874 /* negate DTR, RTS */
3875 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3876 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3877 /* disable IENABLE */
3878 com_int_TxRx_disable( com );
3885 disc_optim(tp, t, com)
3890 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
3891 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
3892 && (!(t->c_iflag & PARMRK)
3893 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
3894 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
3895 && linesw[tp->t_line].l_rint == ttyinput)
3896 tp->t_state |= TS_CAN_BYPASS_L_RINT;
3898 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
3899 com->hotchar = linesw[tp->t_line].l_hotchar;
3903 * Following are all routines needed for SIO to act as console
3905 #include <sys/cons.h>
3915 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3916 static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
3917 static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
3918 static void siocntxwait __P((Port_t iobase));
3920 static cn_probe_t siocnprobe;
3921 static cn_init_t siocninit;
3922 static cn_checkc_t siocncheckc;
3923 static cn_getc_t siocngetc;
3924 static cn_putc_t siocnputc;
3927 CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc);
3931 /* To get the GDB related variables */
3933 #include <ddb/ddb.h>
3943 * Wait for any pending transmission to finish. Required to avoid
3944 * the UART lockup bug when the speed is changed, and for normal
3948 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3949 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3954 * Read the serial port specified and try to figure out what speed
3955 * it's currently running at. We're assuming the serial port has
3956 * been initialized and is basicly idle. This routine is only intended
3957 * to be run at system startup.
3959 * If the value read from the serial port doesn't make sense, return 0.
3963 siocngetspeed(iobase, table)
3965 struct speedtab *table;
3972 cfcr = inb(iobase + com_cfcr);
3973 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3975 dlbl = inb(iobase + com_dlbl);
3976 dlbh = inb(iobase + com_dlbh);
3978 outb(iobase + com_cfcr, cfcr);
3980 code = dlbh << 8 | dlbl;
3982 for ( ; table->sp_speed != -1; table++)
3983 if (table->sp_code == code)
3984 return (table->sp_speed);
3986 return 0; /* didn't match anything sane */
3990 siocnopen(sp, iobase, speed)
3991 struct siocnstate *sp;
4000 * Save all the device control registers except the fifo register
4001 * and set our default ones (cs8 -parenb speed=comdefaultrate).
4002 * We can't save the fifo register since it is read-only.
4004 sp->ier = inb(iobase + com_ier);
4005 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
4006 siocntxwait(iobase);
4007 sp->cfcr = inb(iobase + com_cfcr);
4008 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4009 sp->dlbl = inb(iobase + com_dlbl);
4010 sp->dlbh = inb(iobase + com_dlbh);
4012 * Only set the divisor registers if they would change, since on
4013 * some 16550 incompatibles (Startech), setting them clears the
4014 * data input register. This also reduces the effects of the
4017 divisor = ttspeedtab(speed, comspeedtab);
4018 dlbl = divisor & 0xFF;
4019 if (sp->dlbl != dlbl)
4020 outb(iobase + com_dlbl, dlbl);
4021 dlbh = (u_int) divisor >> 8;
4022 if (sp->dlbh != dlbh)
4023 outb(iobase + com_dlbh, dlbh);
4024 outb(iobase + com_cfcr, CFCR_8BITS);
4025 sp->mcr = inb(iobase + com_mcr);
4027 * We don't want interrupts, but must be careful not to "disable"
4028 * them by clearing the MCR_IENABLE bit, since that might cause
4029 * an interrupt by floating the IRQ line.
4031 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4035 siocnclose(sp, iobase)
4036 struct siocnstate *sp;
4040 * Restore the device control registers.
4042 siocntxwait(iobase);
4043 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4044 if (sp->dlbl != inb(iobase + com_dlbl))
4045 outb(iobase + com_dlbl, sp->dlbl);
4046 if (sp->dlbh != inb(iobase + com_dlbh))
4047 outb(iobase + com_dlbh, sp->dlbh);
4048 outb(iobase + com_cfcr, sp->cfcr);
4050 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4052 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4053 outb(iobase + com_ier, sp->ier);
4063 struct siocnstate sp;
4066 * Find our first enabled console, if any. If it is a high-level
4067 * console device, then initialize it and return successfully.
4068 * If it is a low-level console device, then initialize it and
4069 * return unsuccessfully. It must be initialized in both cases
4070 * for early use by console drivers and debuggers. Initializing
4071 * the hardware is not necessary in all cases, since the i/o
4072 * routines initialize it on the fly, but it is necessary if
4073 * input might arrive while the hardware is switched back to an
4074 * uninitialized state. We can't handle multiple console devices
4075 * yet because our low-level routines don't take a device arg.
4076 * We trust the user to set the console flags properly so that we
4077 * don't need to probe.
4079 cp->cn_pri = CN_DEAD;
4081 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4084 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
4088 if (resource_int_value("sio", unit, "flags", &flags))
4090 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4094 if (resource_int_value("sio", unit, "port", &port))
4098 if (boothowto & RB_SERIAL) {
4099 boot_speed = siocngetspeed(iobase, comspeedtab);
4101 comdefaultrate = boot_speed;
4105 * Initialize the divisor latch. We can't rely on
4106 * siocnopen() to do this the first time, since it
4107 * avoids writing to the latch if the latch appears
4108 * to have the correct value. Also, if we didn't
4109 * just read the speed from the hardware, then we
4110 * need to set the speed in hardware so that
4111 * switching it later is null.
4113 cfcr = inb(iobase + com_cfcr);
4114 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4115 outb(iobase + com_dlbl,
4116 COMBRD(comdefaultrate) & 0xff);
4117 outb(iobase + com_dlbh,
4118 (u_int) COMBRD(comdefaultrate) >> 8);
4119 outb(iobase + com_cfcr, cfcr);
4121 siocnopen(&sp, iobase, comdefaultrate);
4124 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4125 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4126 cp->cn_pri = COM_FORCECONSOLE(flags)
4127 || boothowto & RB_SERIAL
4128 ? CN_REMOTE : CN_NORMAL;
4129 siocniobase = iobase;
4132 if (COM_DEBUGGER(flags)) {
4133 printf("sio%d: gdb debugging port\n", unit);
4134 siogdbiobase = iobase;
4137 gdbdev = makedev(CDEV_MAJOR, unit);
4138 gdb_getc = siocngetc;
4139 gdb_putc = siocnputc;
4147 * XXX Ugly Compatability.
4148 * If no gdb port has been specified, set it to be the console
4149 * as some configuration files don't specify the gdb port.
4151 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
4152 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
4154 printf("Set flag 0x80 on desired GDB port in your\n");
4155 printf("configuration file (currently sio only).\n");
4156 siogdbiobase = siocniobase;
4157 siogdbunit = siocnunit;
4158 gdbdev = makedev(CDEV_MAJOR, siocnunit);
4159 gdb_getc = siocngetc;
4160 gdb_putc = siocnputc;
4168 CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc);
4171 siocnattach(port, speed)
4177 struct siocnstate sp;
4180 comdefaultrate = speed;
4181 sio_consdev.cn_pri = CN_NORMAL;
4182 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
4187 * Initialize the divisor latch. We can't rely on
4188 * siocnopen() to do this the first time, since it
4189 * avoids writing to the latch if the latch appears
4190 * to have the correct value. Also, if we didn't
4191 * just read the speed from the hardware, then we
4192 * need to set the speed in hardware so that
4193 * switching it later is null.
4195 cfcr = inb(siocniobase + com_cfcr);
4196 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4197 outb(siocniobase + com_dlbl,
4198 COMBRD(comdefaultrate) & 0xff);
4199 outb(siocniobase + com_dlbh,
4200 (u_int) COMBRD(comdefaultrate) >> 8);
4201 outb(siocniobase + com_cfcr, cfcr);
4203 siocnopen(&sp, siocniobase, comdefaultrate);
4206 cn_tab = &sio_consdev;
4211 siogdbattach(port, speed)
4217 struct siocnstate sp;
4219 siogdbiobase = port;
4220 gdbdefaultrate = speed;
4225 * Initialize the divisor latch. We can't rely on
4226 * siocnopen() to do this the first time, since it
4227 * avoids writing to the latch if the latch appears
4228 * to have the correct value. Also, if we didn't
4229 * just read the speed from the hardware, then we
4230 * need to set the speed in hardware so that
4231 * switching it later is null.
4233 cfcr = inb(siogdbiobase + com_cfcr);
4234 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4235 outb(siogdbiobase + com_dlbl,
4236 COMBRD(gdbdefaultrate) & 0xff);
4237 outb(siogdbiobase + com_dlbh,
4238 (u_int) COMBRD(gdbdefaultrate) >> 8);
4239 outb(siogdbiobase + com_cfcr, cfcr);
4241 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4253 comconsole = DEV_TO_UNIT(cp->cn_dev);
4263 struct siocnstate sp;
4265 if (minor(dev) == siogdbunit)
4266 iobase = siogdbiobase;
4268 iobase = siocniobase;
4270 siocnopen(&sp, iobase, comdefaultrate);
4271 if (inb(iobase + com_lsr) & LSR_RXRDY)
4272 c = inb(iobase + com_data);
4275 siocnclose(&sp, iobase);
4288 struct siocnstate sp;
4290 if (minor(dev) == siogdbunit)
4291 iobase = siogdbiobase;
4293 iobase = siocniobase;
4295 siocnopen(&sp, iobase, comdefaultrate);
4296 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4298 c = inb(iobase + com_data);
4299 siocnclose(&sp, iobase);
4310 struct siocnstate sp;
4313 if (minor(dev) == siogdbunit)
4314 iobase = siogdbiobase;
4316 iobase = siocniobase;
4318 siocnopen(&sp, iobase, comdefaultrate);
4319 siocntxwait(iobase);
4320 outb(iobase + com_data, c);
4321 siocnclose(&sp, iobase);
4332 struct siocnstate sp;
4334 iobase = siogdbiobase;
4336 siocnopen(&sp, iobase, gdbdefaultrate);
4337 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4339 c = inb(iobase + com_data);
4340 siocnclose(&sp, iobase);
4350 struct siocnstate sp;
4353 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4354 siocntxwait(siogdbiobase);
4355 outb(siogdbiobase + com_data, c);
4356 siocnclose(&sp, siogdbiobase);
4361 DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass, sio_cdevsw, 0, 0);
4365 * pc98 local function
4369 com_tiocm_set(struct com_s *com, int msr)
4373 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4376 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4377 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4378 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4379 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4380 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4381 pc98_i8251_clear_or_cmd( com, mask, tmp );
4386 com_tiocm_bis(struct com_s *com, int msr)
4392 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4393 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4394 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4395 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4397 pc98_i8251_or_cmd( com, tmp );
4402 com_tiocm_bic(struct com_s *com, int msr)
4408 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4409 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4410 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4412 pc98_i8251_clear_cmd( com, tmp );
4417 com_tiocm_get(struct com_s *com)
4419 return( com->pc98_prev_modem_status );
4423 com_tiocm_get_delta(struct com_s *com)
4427 tmp = com->pc98_modem_delta;
4428 com->pc98_modem_delta = 0;
4432 /* convert to TIOCM_?? ( ioctl.h ) */
4434 pc98_get_modem_status(struct com_s *com)
4439 stat = inb(com->sts_port);
4440 stat2 = inb(com->in_modem_port);
4441 msr = com->pc98_prev_modem_status
4442 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4443 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4444 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4445 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4446 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4447 #if COM_CARRIER_DETECT_EMULATE
4448 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4456 pc98_check_msr(void* chan)
4460 register struct tty *tp;
4468 unit = MINOR_TO_UNIT(mynor);
4469 com = com_addr(unit);
4473 msr = pc98_get_modem_status(com);
4474 /* make change flag */
4475 delta = msr ^ com->pc98_prev_modem_status;
4476 if ( delta & TIOCM_CAR ) {
4477 if ( com->modem_car_chg_timer ) {
4478 if ( -- com->modem_car_chg_timer )
4481 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4482 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4486 com->modem_car_chg_timer = 0;
4487 delta = ( msr ^ com->pc98_prev_modem_status ) &
4488 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4489 com->pc98_prev_modem_status = msr;
4490 delta = ( com->pc98_modem_delta |= delta );
4492 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4496 timeout(pc98_check_msr, (caddr_t)dev,
4497 PC98_CHECK_MODEM_INTERVAL);
4499 com->modem_checking = 0;
4504 pc98_msrint_start(dev_t dev)
4512 unit = MINOR_TO_UNIT(mynor);
4513 com = com_addr(unit);
4514 /* modem control line check routine envoke interval is 1/10 sec */
4515 if ( com->modem_checking == 0 ) {
4516 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4517 com->pc98_modem_delta = 0;
4518 timeout(pc98_check_msr, (caddr_t)dev,
4519 PC98_CHECK_MODEM_INTERVAL);
4520 com->modem_checking = 1;
4526 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4528 /* disable interrupt */
4531 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4533 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4534 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4539 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4544 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4545 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4550 pc98_check_i8251_interrupt(struct com_s *com)
4552 return ( com->intr_enable & 0x07 );
4556 pc98_i8251_clear_cmd(struct com_s *com, int x)
4561 tmp = com->pc98_prev_siocmd & ~(x);
4562 outb(com->cmd_port, tmp);
4563 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4568 pc98_i8251_or_cmd(struct com_s *com, int x)
4573 tmp = com->pc98_prev_siocmd | (x);
4574 outb(com->cmd_port, tmp);
4575 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4580 pc98_i8251_set_cmd(struct com_s *com, int x)
4586 outb(com->cmd_port, tmp);
4587 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4592 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4596 tmp = com->pc98_prev_siocmd & ~(clr);
4598 outb(com->cmd_port, tmp);
4599 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4604 pc98_i8251_get_cmd(struct com_s *com)
4606 return com->pc98_prev_siocmd;
4610 pc98_i8251_get_mod(struct com_s *com)
4612 return com->pc98_prev_siomod;
4616 pc98_i8251_reset(struct com_s *com, int mode, int command)
4618 outb(com->cmd_port, 0); /* dummy */
4620 outb(com->cmd_port, 0); /* dummy */
4622 outb(com->cmd_port, 0); /* dummy */
4624 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4626 outb(com->cmd_port, mode ); /* mode register */
4627 com->pc98_prev_siomod = mode;
4629 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4633 pc98_check_sysclock(void)
4635 /* get system clock from port */
4636 if ( pc98_machine_type & M_8M ) {
4637 /* 8 MHz system & H98 */
4646 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4651 count = pc98_ttspeedtab( com, speed );
4652 if ( count < 0 ) return;
4654 previnterrupt = pc98_check_i8251_interrupt(com);
4655 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4657 switch ( cflag&CSIZE ) {
4659 cfcr = MOD8251_5BITS; break;
4661 cfcr = MOD8251_6BITS; break;
4663 cfcr = MOD8251_7BITS; break;
4665 cfcr = MOD8251_8BITS; break;
4667 if ( cflag&PARENB ) {
4669 cfcr |= MOD8251_PODD;
4671 cfcr |= MOD8251_PEVEN;
4673 cfcr |= MOD8251_PDISAB;
4676 cfcr |= MOD8251_STOP2;
4678 cfcr |= MOD8251_STOP1;
4680 if ( count & 0x10000 )
4681 cfcr |= MOD8251_CLKX1;
4683 cfcr |= MOD8251_CLKX16;
4685 if (epson_machine_id != 0x20) { /* XXX */
4687 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4690 /* set baud rate from ospeed */
4691 pc98_set_baud_rate( com, count );
4693 if ( cfcr != pc98_i8251_get_mod(com) )
4694 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4696 pc98_enable_i8251_interrupt( com, previnterrupt );
4700 pc98_ttspeedtab(struct com_s *com, int speed)
4702 int if_type, effect_sp, count = -1, mod;
4704 if_type = com->pc98_if_type & 0x0f;
4706 switch (com->pc98_if_type) {
4707 case COM_IF_INTERNAL:
4708 if (PC98SIO_baud_rate_port(if_type) != -1) {
4709 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4711 count |= COM1_EXT_CLOCK;
4716 /* for *1CLK asynchronous! mode, TEFUTEFU */
4717 mod = (sysclock == 5) ? 2457600 : 1996800;
4718 effect_sp = ttspeedtab( speed, pc98speedtab );
4719 if ( effect_sp < 0 ) /* XXX */
4720 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4721 if ( effect_sp <= 0 )
4723 if ( effect_sp == speed )
4725 if ( mod % effect_sp )
4727 count = mod / effect_sp;
4728 if ( count > 65535 )
4730 if ( effect_sp != speed )
4733 case COM_IF_PC9861K_1:
4734 case COM_IF_PC9861K_2:
4737 case COM_IF_IND_SS_1:
4738 case COM_IF_IND_SS_2:
4739 case COM_IF_PIO9032B_1:
4740 case COM_IF_PIO9032B_2:
4741 if ( speed == 0 ) return 0;
4742 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4744 case COM_IF_B98_01_1:
4745 case COM_IF_B98_01_2:
4746 if ( speed == 0 ) return 0;
4747 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4749 if (count == 0 || count == 1) {
4751 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4761 pc98_set_baud_rate( struct com_s *com, int count )
4765 if_type = com->pc98_if_type & 0x0f;
4766 io = com->iobase & 0xff00;
4768 switch (com->pc98_if_type) {
4769 case COM_IF_INTERNAL:
4770 if (PC98SIO_baud_rate_port(if_type) != -1) {
4771 if (count & COM1_EXT_CLOCK) {
4772 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4775 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4780 printf( "[ Illegal count : %d ]", count );
4782 } else if ( count == 0 )
4791 outb( 0x75, count & 0xff );
4793 outb( 0x75, (count >> 8) & 0xff );
4796 case COM_IF_IND_SS_1:
4797 case COM_IF_IND_SS_2:
4798 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4799 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4800 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4801 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4802 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4804 case COM_IF_PIO9032B_1:
4805 case COM_IF_PIO9032B_2:
4806 outb(io | PC98SIO_baud_rate_port(if_type), count);
4808 case COM_IF_B98_01_1:
4809 case COM_IF_B98_01_2:
4810 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4813 * Some old B98_01 board should be controlled
4814 * in different way, but this hasn't been tested yet.
4816 outb(io | PC98SIO_func_port(if_type),
4817 (count & 0x20000) ? 0xf0 : 0xf2);
4823 pc98_check_if_type(device_t dev, struct siodev *iod)
4825 int irr, io, if_type, tmp;
4826 static short irq_tab[2][8] = {
4827 { 3, 5, 6, 9, 10, 12, 13, -1},
4828 { 3, 10, 12, 13, 5, 6, 9, -1}
4831 iod->if_type = if_type = (device_get_flags(dev) >> 24) & 0xff;
4832 if ((if_type < 0 || if_type > COM_IF_END1) &&
4833 (if_type < 0x10 || if_type > COM_IF_END2))
4837 io = isa_get_port(dev) & 0xff00;
4839 if (IS_8251(iod->if_type)) {
4840 if (PC98SIO_func_port(if_type) != -1) {
4841 outb(io | PC98SIO_func_port(if_type), 0xf2);
4842 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4843 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4844 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4847 iod->cmd = io | PC98SIO_cmd_port(if_type);
4848 iod->sts = io | PC98SIO_sts_port(if_type);
4849 iod->mod = io | PC98SIO_in_modem_port(if_type);
4850 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4852 if (iod->if_type == COM_IF_INTERNAL) {
4855 /* XXX check new internal port. */
4858 for (tmp = 0; tmp < 100; tmp++) {
4859 if ((inb(0x13a) & 0x80) == 0) {
4860 PC98SIO_baud_rate_port(if_type) = 0x13a;
4861 if_8251_type[if_type].name = " (internal fast)";
4862 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4868 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4869 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4870 iod->irq = irq_tab[0][tmp];
4872 iod->irq = irq_tab[1][tmp];
4875 irr = if_16550a_type[if_type].irr_read;
4876 #ifdef COM_MULTIPORT
4877 if (!COM_ISMULTIPORT(device_get_flags(dev)) ||
4878 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev)))
4881 tmp = inb(io | irr);
4882 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4883 iod->irq = irq_tab[1][tmp >> 3];
4885 iod->irq = irq_tab[0][tmp & 0x07];
4888 if ( iod->irq == -1 ) return -1;
4893 pc98_set_ioport( struct com_s *com, int id_flags )
4897 if_type = (id_flags >> 24) & 0xff;
4898 if (IS_8251(if_type)) {
4899 pc98_check_sysclock();
4900 io = com->iobase & 0xff00;
4901 com->pc98_if_type = if_type;
4903 com->data_port = io | PC98SIO_data_port(if_type);
4904 com->cmd_port = io | PC98SIO_cmd_port(if_type);
4905 com->sts_port = io | PC98SIO_sts_port(if_type);
4906 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
4907 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
4913 #endif /* PC98 defined */