2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $Id: sio.c,v 1.101 1999/08/09 13:03:35 nyan Exp $
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
38 #include "opt_comconsole.h"
39 #include "opt_compat.h"
41 #include "opt_devfs.h"
44 /* #include "pnp.h" */
48 * Serial driver, based on 386BSD-0.1 com driver.
49 * Mostly rewritten to use pseudo-DMA.
50 * Works for National Semiconductor NS8250-NS16550AF UARTs.
51 * COM driver, based on HP dca driver.
53 * Changes for PC-Card integration:
54 * - Added PC-Card driver table and handlers
56 /*===============================================================
57 * 386BSD(98),FreeBSD-1.1x(98) com driver.
59 * modified for PC9801 by M.Ishii
60 * Kyoto University Microcomputer Club (KMC)
61 * Chou "TEFUTEFU" Hirotomi
62 * Kyoto Univ. the faculty of medicine
63 *===============================================================
64 * FreeBSD-2.0.1(98) sio driver.
66 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
67 * T.Koike(hfc01340@niftyserve.or.jp)
68 * implement kernel device configuration
69 * aizu@orient.center.nitech.ac.jp
73 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
75 * This driver is under debugging,has bugs.
78 * options COM_MULTIPORT #if using MC16550II
79 * device sio0 at nec? port 0x30 tty irq 4 #internal
80 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
81 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
82 * # ~~~~~iobase ~~multi port flag
83 * # ~ master device is sio1
85 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
87 * 57600bps is too fast for sio0(internal8251)
89 * #set default speed 9600
92 * stty </dev/ttyid$i crtscts 9600
93 * : # ~~~~ default speed(can change after init.)
97 * 5) PC9861K,PIO9032B,B98_01
101 * modified for AIWA B98-01
102 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
104 * How to configure...
105 * # options COM_MULTIPORT # support for MICROCORE MC16550II
106 * ... comment-out this line, which will conflict with B98_01.
107 * options "B98_01" # support for AIWA B98-01
108 * device sio1 at nec? port 0x00d1 tty irq ?
109 * device sio2 at nec? port 0x00d5 tty irq ?
110 * ... you can leave these lines `irq ?', irq will be autodetected.
113 * Modified by Y.Takahashi of Kogakuin University.
117 #define COM_IF_INTERNAL 0x00
118 #define COM_IF_PC9861K_1 0x01
119 #define COM_IF_PC9861K_2 0x02
120 #define COM_IF_IND_SS_1 0x03
121 #define COM_IF_IND_SS_2 0x04
122 #define COM_IF_PIO9032B_1 0x05
123 #define COM_IF_PIO9032B_2 0x06
124 #define COM_IF_B98_01_1 0x07
125 #define COM_IF_B98_01_2 0x08
126 #define COM_IF_END1 COM_IF_B98_01_2
127 #define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
128 #define COM_IF_NS16550 0x11
129 #define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
130 #define COM_IF_MC16550II 0x13
131 #define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
132 #define COM_IF_RSB3000 0x15
133 #define COM_IF_RSB384 0x16
134 #define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
135 #define COM_IF_RSA98III 0x18
136 #define COM_IF_ESP98 0x19
137 #define COM_IF_END2 COM_IF_ESP98
140 #include <sys/param.h>
141 #include <sys/systm.h>
142 #include <sys/reboot.h>
143 #include <sys/malloc.h>
145 #include <sys/proc.h>
146 #include <sys/module.h>
147 #include <sys/conf.h>
148 #include <sys/dkstat.h>
149 #include <sys/fcntl.h>
150 #include <sys/interrupt.h>
151 #include <sys/kernel.h>
152 #include <sys/syslog.h>
153 #include <sys/sysctl.h>
155 #include <machine/bus.h>
156 #include <sys/rman.h>
158 #include <sys/devfsext.h>
160 #include <sys/timepps.h>
163 #include <pc98/pc98/pc98.h>
164 #include <pc98/pc98/pc98_machdep.h>
165 #include <i386/isa/ic/i8251.h>
167 #include <isa/isareg.h>
169 #include <isa/isavar.h>
170 #include <machine/lock.h>
172 #include <machine/clock.h>
173 #include <machine/ipl.h>
175 #include <machine/lock.h>
177 #include <machine/resource.h>
179 #include <isa/sioreg.h>
182 #include <i386/isa/ic/esp.h>
184 #include <i386/isa/ic/ns16550.h>
186 #include <i386/isa/ic/rsa.h>
193 #include <sys/module.h>
194 #include <pccard/cardinfo.h>
195 #include <pccard/slot.h>
199 #include <i386/isa/pnp.h>
205 #define disable_intr() 0
206 #define enable_intr() 0
210 #define disable_intr() COM_DISABLE_INTR()
211 #define enable_intr() COM_ENABLE_INTR()
216 #define EXTRA_SIO MAX_PNP_CARDS
222 #define NSIOTOT (NSIO + EXTRA_SIO)
224 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
226 #define CALLOUT_MASK 0x80
227 #define CONTROL_MASK 0x60
228 #define CONTROL_INIT_STATE 0x20
229 #define CONTROL_LOCK_STATE 0x40
230 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
231 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
232 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
235 /* checks in flags for multiport and which is multiport "master chip"
238 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
239 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
240 #define COM_NOTAST4(flags) ((flags) & 0x04)
241 #endif /* COM_MULTIPORT */
243 #define COM_CONSOLE(flags) ((flags) & 0x10)
244 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
245 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
246 #define COM_DEBUGGER(flags) ((flags) & 0x80)
247 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
248 #define COM_NOFIFO(flags) ((flags) & 0x02)
249 #define COM_ST16650A(flags) ((flags) & 0x20000)
250 #define COM_C_NOPROBE (0x40000)
251 #define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
252 #define COM_C_IIR_TXRDYBUG (0x80000)
253 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
254 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
257 #define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
259 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
264 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
265 * than the other bits so that they can be tested as a group without masking
268 * The following com and tty flags correspond closely:
269 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
271 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
272 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
273 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
274 * TS_FLUSH is not used.
275 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
276 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
278 #define CS_BUSY 0x80 /* output in progress */
279 #define CS_TTGO 0x40 /* output not stopped by XOFF */
280 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
281 #define CS_CHECKMSR 1 /* check of MSR scheduled */
282 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
283 #define CS_DTR_OFF 0x10 /* DTR held off */
284 #define CS_ODONE 4 /* output completed */
285 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
286 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
288 static char const * const error_desc[] = {
291 #define CE_INTERRUPT_BUF_OVERFLOW 1
292 "interrupt-level buffer overflow",
293 #define CE_TTY_BUF_OVERFLOW 2
294 "tty-level buffer overflow",
298 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
300 /* types. XXX - should be elsewhere */
301 typedef u_int Port_t; /* hardware port */
302 typedef u_char bool_t; /* boolean */
304 /* queue of linear buffers */
306 u_char *l_head; /* next char to process */
307 u_char *l_tail; /* one past the last char to process */
308 struct lbq *l_next; /* next in queue */
309 bool_t l_queued; /* nonzero if queued */
312 /* com device structure */
314 u_int flags; /* Copy isa device flags */
315 u_char state; /* miscellaneous flag bits */
316 bool_t active_out; /* nonzero if the callout device is open */
317 u_char cfcr_image; /* copy of value written to CFCR */
319 bool_t esp; /* is this unit a hayes esp board? */
321 u_char extra_state; /* more flag bits, separate for order trick */
322 u_char fifo_image; /* copy of value written to FIFO */
323 bool_t hasfifo; /* nonzero for 16550 UARTs */
324 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
325 bool_t loses_outints; /* nonzero if device loses output interrupts */
326 u_char mcr_image; /* copy of value written to MCR */
328 bool_t multiport; /* is this unit part of a multiport device? */
329 #endif /* COM_MULTIPORT */
330 bool_t no_irq; /* nonzero if irq is not attached */
331 bool_t gone; /* hardware disappeared */
332 bool_t poll; /* nonzero if polling is required */
333 bool_t poll_output; /* nonzero if polling for output is required */
334 int unit; /* unit number */
335 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
337 u_int wopeners; /* # processes waiting for DCD in open() */
340 * The high level of the driver never reads status registers directly
341 * because there would be too many side effects to handle conveniently.
342 * Instead, it reads copies of the registers stored here by the
345 u_char last_modem_status; /* last MSR read by intr handler */
346 u_char prev_modem_status; /* last MSR handled by high level */
348 u_char hotchar; /* ldisc-specific char to be handled ASAP */
349 u_char *ibuf; /* start of input buffer */
350 u_char *ibufend; /* end of input buffer */
351 u_char *ibufold; /* old input buffer, to be freed */
352 u_char *ihighwater; /* threshold in input buffer */
353 u_char *iptr; /* next free spot in input buffer */
354 int ibufsize; /* size of ibuf (not include error bytes) */
355 int ierroff; /* offset of error bytes in ibuf */
357 struct lbq obufq; /* head of queue of output buffers */
358 struct lbq obufs[2]; /* output buffers */
363 Port_t in_modem_port;
364 Port_t intr_ctrl_port;
366 int pc98_prev_modem_status;
367 int pc98_modem_delta;
368 int modem_car_chg_timer;
369 int pc98_prev_siocmd;
370 int pc98_prev_siomod;
374 Port_t data_port; /* i/o ports */
381 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
383 Port_t modem_ctl_port;
384 Port_t line_status_port;
385 Port_t modem_status_port;
386 Port_t intr_ctl_port; /* Ports of IIR register */
388 struct tty *tp; /* cross reference */
391 struct termios it_in; /* should be in struct tty */
392 struct termios it_out;
395 struct termios lt_in; /* should be in struct tty */
396 struct termios lt_out;
399 bool_t do_dcd_timestamp;
400 struct timeval timestamp;
401 struct timeval dcd_timestamp;
402 struct pps_state pps;
404 u_long bytes_in; /* statistics */
406 u_int delta_error_counts[CE_NTYPES];
407 u_long error_counts[CE_NTYPES];
410 * Data area for output buffers. Someday we should build the output
411 * buffer queue without copying data.
422 void *devfs_token_ttyd;
423 void *devfs_token_ttyl;
424 void *devfs_token_ttyi;
425 void *devfs_token_cuaa;
426 void *devfs_token_cual;
427 void *devfs_token_cuai;
432 static int espattach __P((struct com_s *com, Port_t esp_port));
434 static int sioattach __P((device_t dev));
436 static timeout_t siobusycheck;
437 static timeout_t siodtrwakeup;
438 static void comhardclose __P((struct com_s *com));
439 static void sioinput __P((struct com_s *com));
440 static void siointr1 __P((struct com_s *com));
441 static void siointr __P((void *arg));
442 static int commctl __P((struct com_s *com, int bits, int how));
443 static int comparam __P((struct tty *tp, struct termios *t));
444 static swihand_t siopoll;
445 static int sioprobe __P((device_t dev));
446 static void siosettimeout __P((void));
447 static int siosetwater __P((struct com_s *com, speed_t speed));
448 static void comstart __P((struct tty *tp));
449 static timeout_t comwakeup;
450 static void disc_optim __P((struct tty *tp, struct termios *t,
454 static char driver_name[] = "sio";
456 /* table and macro for fast conversion from a unit number to its com struct */
457 static devclass_t sio_devclass;
458 #define com_addr(unit) ((struct com_s *) \
459 devclass_get_softc(sio_devclass, unit))
461 static device_method_t sio_methods[] = {
462 /* Device interface */
463 DEVMETHOD(device_probe, sioprobe),
464 DEVMETHOD(device_attach, sioattach),
469 static driver_t sio_driver = {
472 sizeof(struct com_s),
475 static d_open_t sioopen;
476 static d_close_t sioclose;
477 static d_read_t sioread;
478 static d_write_t siowrite;
479 static d_ioctl_t sioioctl;
480 static d_stop_t siostop;
481 static d_devtotty_t siodevtotty;
483 #define CDEV_MAJOR 28
484 static struct cdevsw sio_cdevsw = {
486 /* close */ sioclose,
488 /* write */ siowrite,
489 /* ioctl */ sioioctl,
492 /* devtotty */ siodevtotty,
495 /* strategy */ nostrategy,
496 /* name */ driver_name,
498 /* maj */ CDEV_MAJOR,
507 static volatile speed_t comdefaultrate = CONSPEED;
509 static volatile speed_t gdbdefaultrate = CONSPEED;
511 static u_int com_events; /* input chars + weighted output completions */
512 static Port_t siocniobase;
513 static int siocnunit;
514 static Port_t siogdbiobase;
515 static int siogdbunit = -1;
516 static bool_t sio_registered;
517 static int sio_timeout;
518 static int sio_timeouts_until_log;
519 static struct callout_handle sio_timeout_handle
520 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
522 static struct tty *sio_tty[NSIOTOT];
524 static struct tty sio_tty[NSIOTOT];
526 static const int nsio_tty = NSIOTOT;
532 Port_t cmd, sts, ctrl, mod;
536 #define COM_INT_DISABLE {int previpri; previpri=spltty();
537 #define COM_INT_ENABLE splx(previpri);}
538 #define IEN_TxFLAG IEN_Tx
540 #define COM_CARRIER_DETECT_EMULATE 0
541 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
542 #define DCD_OFF_TOLERANCE 2
543 #define DCD_ON_RECOGNITION 2
544 #define IS_8251(if_type) (!(if_type & 0x10))
545 #define COM1_EXT_CLOCK 0x40000
547 static void commint __P((dev_t dev));
548 static void com_tiocm_set __P((struct com_s *com, int msr));
549 static void com_tiocm_bis __P((struct com_s *com, int msr));
550 static void com_tiocm_bic __P((struct com_s *com, int msr));
551 static int com_tiocm_get __P((struct com_s *com));
552 static int com_tiocm_get_delta __P((struct com_s *com));
553 static void pc98_msrint_start __P((dev_t dev));
554 static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
555 static int pc98_ttspeedtab __P((struct com_s *com, int speed));
556 static int pc98_get_modem_status __P((struct com_s *com));
557 static timeout_t pc98_check_msr;
558 static void pc98_set_baud_rate __P((struct com_s *com, int count));
559 static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
560 static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
561 static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
562 static int pc98_check_i8251_interrupt __P((struct com_s *com));
563 static int pc98_i8251_get_cmd __P((struct com_s *com));
564 static int pc98_i8251_get_mod __P((struct com_s *com));
565 static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
566 static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
567 static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
568 static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
569 static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
570 static void pc98_check_sysclock __P((void));
571 static int pc98_set_ioport __P((struct com_s *com, int id_flags));
573 #define com_int_Tx_disable(com) \
574 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
575 #define com_int_Tx_enable(com) \
576 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
577 #define com_int_Rx_disable(com) \
578 pc98_disable_i8251_interrupt(com,IEN_Rx)
579 #define com_int_Rx_enable(com) \
580 pc98_enable_i8251_interrupt(com,IEN_Rx)
581 #define com_int_TxRx_disable(com) \
582 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
583 #define com_int_TxRx_enable(com) \
584 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
585 #define com_send_break_on(com) \
586 pc98_i8251_or_cmd(com,CMD8251_SBRK)
587 #define com_send_break_off(com) \
588 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
590 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
612 static struct speedtab pc98fast_speedtab[] = {
613 { 9600, 0x80 | COMBRD(9600), },
614 { 19200, 0x80 | COMBRD(19200), },
615 { 38400, 0x80 | COMBRD(38400), },
616 { 57600, 0x80 | COMBRD(57600), },
617 { 115200, 0x80 | COMBRD(115200), },
620 static struct speedtab comspeedtab_pio9032b[] = {
631 static struct speedtab comspeedtab_b98_01[] = {
646 static struct speedtab comspeedtab_mc16550[] = {
662 static struct speedtab comspeedtab_rsb384[] = {
683 static struct speedtab comspeedtab_rsa[] = {
685 { 50, COMBRD_RSA(50) },
686 { 75, COMBRD_RSA(75) },
687 { 110, COMBRD_RSA(110) },
688 { 134, COMBRD_RSA(134) },
689 { 150, COMBRD_RSA(150) },
690 { 200, COMBRD_RSA(200) },
691 { 300, COMBRD_RSA(300) },
692 { 600, COMBRD_RSA(600) },
693 { 1200, COMBRD_RSA(1200) },
694 { 1800, COMBRD_RSA(1800) },
695 { 2400, COMBRD_RSA(2400) },
696 { 4800, COMBRD_RSA(4800) },
697 { 9600, COMBRD_RSA(9600) },
698 { 19200, COMBRD_RSA(19200) },
699 { 38400, COMBRD_RSA(38400) },
700 { 57600, COMBRD_RSA(57600) },
701 { 115200, COMBRD_RSA(115200) },
702 { 230400, COMBRD_RSA(230400) },
703 { 460800, COMBRD_RSA(460800) },
704 { 921600, COMBRD_RSA(921600) },
709 static struct speedtab comspeedtab[] = {
713 { 110, COMBRD(110) },
714 { 134, COMBRD(134) },
715 { 150, COMBRD(150) },
716 { 200, COMBRD(200) },
717 { 300, COMBRD(300) },
718 { 600, COMBRD(600) },
719 { 1200, COMBRD(1200) },
720 { 1800, COMBRD(1800) },
721 { 2400, COMBRD(2400) },
722 { 4800, COMBRD(4800) },
723 { 9600, COMBRD(9600) },
724 { 19200, COMBRD(19200) },
725 { 38400, COMBRD(38400) },
726 { 57600, COMBRD(57600) },
727 { 115200, COMBRD(115200) },
736 struct speedtab *speedtab;
739 /* COM_IF_INTERNAL */
740 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
741 -1, pc98speedtab, 1 },
742 /* COM_IF_PC9861K_1 */
743 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
745 /* COM_IF_PC9861K_2 */
746 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
748 /* COM_IF_IND_SS_1 */
749 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
750 3, comspeedtab_mc16550, 1 },
751 /* COM_IF_IND_SS_2 */
752 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
753 3, comspeedtab_mc16550, 1 },
754 /* COM_IF_PIO9032B_1 */
755 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
756 7, comspeedtab_pio9032b, 1 },
757 /* COM_IF_PIO9032B_2 */
758 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
759 7, comspeedtab_pio9032b, 1 },
760 /* COM_IF_B98_01_1 */
761 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
762 7, comspeedtab_b98_01, 0 },
763 /* COM_IF_B98_01_2 */
764 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
765 7, comspeedtab_b98_01, 0 },
767 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
768 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
769 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
770 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
771 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
772 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
773 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
781 struct speedtab *speedtab;
782 } if_16550a_type[] = {
784 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
786 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
787 /* COM_IF_SECOND_CCU */
788 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
789 /* COM_IF_MC16550II */
790 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
792 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
794 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
796 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
797 /* COM_IF_MODEM_CARD */
798 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
799 /* COM_IF_RSA98III */
800 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
802 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
809 /* XXX configure this properly. */
810 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
811 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
813 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
814 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
815 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
816 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
820 /* XXX configure this properly. */
821 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
822 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
828 * handle sysctl read/write requests for console speed
830 * In addition to setting comdefaultrate for I/O through /dev/console,
831 * also set the initial and lock values for the /dev/ttyXX device
832 * if there is one associated with the console. Finally, if the /dev/tty
833 * device has already been open, change the speed on the open running port
838 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
845 newspeed = comdefaultrate;
847 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
848 if (error || !req->newptr)
851 comdefaultrate = newspeed;
853 if (comconsole < 0) /* serial console not selected? */
856 com = com_addr(comconsole);
861 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
862 * (note, the lock rates really are boolean -- if non-zero, disallow
865 com->it_in.c_ispeed = com->it_in.c_ospeed =
866 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
867 com->it_out.c_ispeed = com->it_out.c_ospeed =
868 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
871 * if we're open, change the running rate too
874 if (tp && (tp->t_state & TS_ISOPEN)) {
875 tp->t_termios.c_ispeed =
876 tp->t_termios.c_ospeed = comdefaultrate;
878 error = comparam(tp, &tp->t_termios);
884 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
885 0, 0, sysctl_machdep_comdefaultrate, "I", "");
889 * PC-Card (PCMCIA) specific code.
891 static int sioinit __P((struct pccard_devinfo *));
892 static void siounload __P((struct pccard_devinfo *));
893 static int card_intr __P((struct pccard_devinfo *));
895 PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
898 * Initialize the device - called from Slot manager.
901 sioinit(struct pccard_devinfo *devi)
904 /* validate unit number. */
905 if (devi->isahd.id_unit >= (NSIOTOT))
907 /* Make sure it isn't already probed. */
908 if (com_addr(devi->isahd.id_unit))
911 /* It's already probed as serial by Upper */
912 devi->isahd.id_flags |= COM_C_NOPROBE;
915 * Probe the device. If a value is returned, the
916 * device was found at the location.
918 if (sioprobe(&devi->isahd) == 0)
920 if (sioattach(&devi->isahd) == 0)
927 * siounload - unload the driver and clear the table.
929 * This is usually called when the card is ejected, but
930 * can be caused by a modunload of a controller driver.
931 * The idea is to reset the driver's view of the device
932 * and ensure that any driver entry points such as
933 * read and write do not hang.
936 siounload(struct pccard_devinfo *devi)
941 printf("NULL devi in siounload\n");
944 com = com_addr(devi->isahd.id_unit);
946 printf("NULL com in siounload\n");
950 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
953 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
955 printf("sio%d: unload\n", devi->isahd.id_unit);
961 if (com->ibuf != NULL)
962 free(com->ibuf, M_DEVBUF);
964 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
969 * card_intr - Shared interrupt called from
970 * front end of PC-Card handler.
973 card_intr(struct pccard_devinfo *devi)
978 com = com_addr(devi->isahd.id_unit);
979 if (com && !com->gone)
980 siointr1(com_addr(devi->isahd.id_unit));
984 #endif /* NCARD > 0 */
986 #define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit))
987 #define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit))
993 static bool_t already_init;
998 intrmask_t irqmap[4];
1003 u_int flags = isa_get_flags(dev);
1009 Port_t rsabase = NULL;
1012 if (!already_init) {
1014 * Turn off MCR_IENABLE for all likely serial ports. An unused
1015 * port with its MCR_IENABLE gate open will inhibit interrupts
1016 * from any used port that shares the interrupt vector.
1017 * XXX the gate enable is elsewhere for some multiports.
1022 devclass_get_devices(sio_devclass, &devs, &count);
1024 for (i = 0; i < count; i++) {
1026 tmp = (flags >> 24) & 0xff;
1028 outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
1030 if (tmp == COM_IF_RSA98III) {
1031 rsabase = isa_get_port(xdev) & 0xfff0;
1032 outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1034 outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1037 for (i = 0; i < count; i++) {
1039 outb(isa_get_port(xdev) + com_mcr, 0);
1043 already_init = TRUE;
1046 if (COM_LLCONSOLE(flags)) {
1047 printf("sio%d: reserved for low-level i/o\n",
1048 device_get_unit(dev));
1056 * If the port is i8251 UART (internal, B98_01)
1058 if (pc98_check_if_type(dev, &iod) == -1)
1061 isa_set_irq(dev, iod.irq);
1062 if (IS_8251(iod.if_type)) {
1069 outb(iod.cmd, CMD8251_RESET);
1070 DELAY(1000); /* for a while...*/
1071 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1073 outb(iod.cmd, 0x01); /* CMD (dummy) */
1074 DELAY(1000); /* for a while...*/
1075 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1078 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1080 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1081 outb( iod.ctrl, tmp|IEN_TxEMP );
1083 result = isa_irq_pending() ? 0 : ENXIO;
1084 outb( iod.ctrl, tmp );
1088 * B98_01 doesn't activate TxEMP interrupt line
1089 * when being reset, so we can't check irq pending.
1093 if (epson_machine_id==0x20) { /* XXX */
1096 isa_set_portsize(dev, 4);
1101 * If the device is on a multiport card and has an AST/4
1102 * compatible interrupt control register, initialize this
1103 * register and prepare to leave MCR_IENABLE clear in the mcr.
1104 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1105 * Point idev to the device struct giving the correct id_irq.
1106 * This is the struct for the master device if there is one.
1109 mcr_image = MCR_IENABLE;
1111 if (iod.if_type == COM_IF_RSA98III) {
1113 rsabase = isa_get_port(idev) & 0xfff0;
1114 if (rsabase != isa_get_port(idev))
1116 outb(rsabase + rsa_msr, 0x04);
1117 outb(rsabase + rsa_frr, 0x00);
1118 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1120 outb(rsabase + rsa_ier, 0x00);
1121 outb(rsabase + rsa_frr, 0x00);
1122 outb(rsabase + rsa_tivsr, 0x00);
1123 outb(rsabase + rsa_tcr, 0x00);
1126 #ifdef COM_MULTIPORT
1127 if (COM_ISMULTIPORT(flags)) {
1128 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1130 printf("sio%d: master device %d not configured\n",
1131 device_get_unit(dev), COM_MPMASTER(flags));
1132 isa_set_irq(dev, 0);
1136 if (!COM_NOTAST4(flags)) {
1137 outb(isa_get_port(idev) + com_scr,
1138 isa_get_irq(idev) >= 0 ? 0x80 : 0);
1143 #endif /* COM_MULTIPORT */
1144 if (isa_get_irq(idev) < 0)
1148 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1151 switch (isa_get_irq(idev)) {
1152 case 3: irqout = 4; break;
1153 case 5: irqout = 5; break;
1154 case 6: irqout = 6; break;
1155 case 12: irqout = 7; break;
1157 printf("sio%d: irq configuration error\n",
1158 device_get_unit(dev));
1161 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
1163 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1165 bzero(failures, sizeof failures);
1166 iobase = isa_get_port(dev);
1168 if (iod.if_type == COM_IF_RSA98III)
1173 * We don't want to get actual interrupts, just masked ones.
1174 * Interrupts from this line should already be masked in the ICU,
1175 * but mask them in the processor as well in case there are some
1176 * (misconfigured) shared interrupts.
1182 * Initialize the speed and the word size and wait long enough to
1183 * drain the maximum of 16 bytes of junk in device output queues.
1184 * The speed is undefined after a master reset and must be set
1185 * before relying on anything related to output. There may be
1186 * junk after a (very fast) soft reboot and (apparently) after
1188 * XXX what about the UART bug avoided by waiting in comparam()?
1189 * We don't want to to wait long enough to drain at 2 bps.
1191 if (iobase == siocniobase)
1192 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1195 tmp = ttspeedtab(SIO_TEST_SPEED,
1196 if_16550a_type[iod.if_type & 0x0f].speedtab);
1197 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1198 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1199 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1200 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1202 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1203 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1204 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1205 outb(iobase + com_cfcr, CFCR_8BITS);
1207 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1211 * Enable the interrupt gate and disable device interupts. This
1212 * should leave the device driving the interrupt line low and
1213 * guarantee an edge trigger if an interrupt can be generated.
1217 outb(iobase + (com_mcr << port_shift), mcr_image);
1218 outb(iobase + (com_ier << port_shift), 0);
1220 outb(iobase + com_mcr, mcr_image);
1221 outb(iobase + com_ier, 0);
1223 DELAY(1000); /* XXX */
1224 irqmap[0] = isa_irq_pending();
1227 * Attempt to set loopback mode so that we can send a null byte
1228 * without annoying any external device.
1232 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1234 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1238 * Attempt to generate an output interrupt. On 8250's, setting
1239 * IER_ETXRDY generates an interrupt independent of the current
1240 * setting and independent of whether the THR is empty. On 16450's,
1241 * setting IER_ETXRDY generates an interrupt independent of the
1242 * current setting. On 16550A's, setting IER_ETXRDY only
1243 * generates an interrupt when IER_ETXRDY is not already set.
1246 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1247 if (iod.if_type == COM_IF_RSA98III)
1248 outb(rsabase + rsa_ier, 0x04);
1250 outb(iobase + com_ier, IER_ETXRDY);
1254 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1255 * an interrupt. They'd better generate one for actually doing
1256 * output. Loopback may be broken on the same incompatibles but
1257 * it's unlikely to do more than allow the null byte out.
1260 outb(iobase + (com_data << port_shift), 0);
1262 outb(iobase + com_data, 0);
1264 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1267 * Turn off loopback mode so that the interrupt gate works again
1268 * (MCR_IENABLE was hidden). This should leave the device driving
1269 * an interrupt line high. It doesn't matter if the interrupt
1270 * line oscillates while we are not looking at it, since interrupts
1275 outb(iobase + (com_mcr << port_shift), mcr_image);
1277 outb(iobase + com_mcr, mcr_image);
1281 * It's a definitly Serial PCMCIA(16550A), but still be required
1282 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1284 if ( COM_NOPROBE(flags) ) {
1285 /* Reading IIR register twice */
1286 for ( fn = 0; fn < 2; fn ++ ) {
1289 failures[6] = inb(iobase + (com_iir << port_shift));
1291 failures[6] = inb(iobase + com_iir);
1294 /* Check IIR_TXRDY clear ? */
1296 isa_set_portsize(dev,
1297 if_16550a_type[iod.if_type & 0x0f].io_size);
1299 isa_set_portsize(dev, IO_COMSIZE);
1302 if ( failures[6] & IIR_TXRDY ) {
1303 /* Nop, Double check with clearing IER */
1305 outb(iobase + (com_ier << port_shift), 0);
1307 (com_iir << port_shift)) & IIR_NOPEND) {
1309 outb(iobase + com_ier, 0);
1310 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1312 /* Ok. we're familia this gang */
1313 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
1315 /* Unknow, Just omit this chip.. XXX*/
1319 /* OK. this is well-known guys */
1320 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
1323 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1325 outb(iobase + com_cfcr, CFCR_8BITS);
1328 return (iobase == siocniobase ? 0 : result);
1333 * o the CFCR, IER and MCR in UART hold the values written to them
1334 * (the values happen to be all distinct - this is good for
1335 * avoiding false positive tests from bus echoes).
1336 * o an output interrupt is generated and its vector is correct.
1337 * o the interrupt goes away when the IIR in the UART is read.
1341 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1342 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1343 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1345 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1346 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1347 failures[2] = inb(iobase + com_mcr) - mcr_image;
1349 DELAY(10000); /* Some internal modems need this time */
1350 irqmap[1] = isa_irq_pending();
1352 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1354 if (iod.if_type == COM_IF_RSA98III)
1355 inb(rsabase + rsa_srr);
1357 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1359 DELAY(1000); /* XXX */
1360 irqmap[2] = isa_irq_pending();
1362 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1364 if (iod.if_type == COM_IF_RSA98III)
1365 inb(rsabase + rsa_srr);
1367 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1371 * Turn off all device interrupts and check that they go off properly.
1372 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1373 * the OUT2 output of the UART to
1374 * the ICU input. Closing the gate would give a floating ICU input
1375 * (unless there is another device driving it) and spurious interrupts.
1376 * (On the system that this was first tested on, the input floats high
1377 * and gives a (masked) interrupt as soon as the gate is closed.)
1380 outb(iobase + (com_ier << port_shift), 0);
1381 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1382 failures[7] = inb(iobase + (com_ier << port_shift));
1383 if (iod.if_type == COM_IF_RSA98III)
1384 outb(rsabase + rsa_ier, 0x00);
1386 outb(iobase + com_ier, 0);
1387 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1388 failures[7] = inb(iobase + com_ier);
1390 DELAY(1000); /* XXX */
1391 irqmap[3] = isa_irq_pending();
1393 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1395 if (iod.if_type == COM_IF_RSA98III) {
1396 inb(rsabase + rsa_srr);
1397 outb(rsabase + rsa_frr, 0x00);
1400 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1405 irqs = irqmap[1] & ~irqmap[0];
1406 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
1408 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1409 device_get_unit(dev), isa_get_irq(idev), irqs);
1411 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1412 device_get_unit(dev),
1413 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1416 isa_set_portsize(dev, if_16550a_type[iod.if_type & 0x0f].io_size);
1418 isa_set_portsize(dev, IO_COMSIZE);
1421 for (fn = 0; fn < sizeof failures; ++fn)
1424 outb(iobase + (com_mcr << port_shift), 0);
1426 outb(iobase + com_mcr, 0);
1430 printf("sio%d: probe failed test(s):",
1431 device_get_unit(dev));
1432 for (fn = 0; fn < sizeof failures; ++fn)
1439 return (iobase == siocniobase ? 0 : result);
1444 espattach(com, esp_port)
1452 * Check the ESP-specific I/O port to see if we're an ESP
1453 * card. If not, return failure immediately.
1455 if ((inb(esp_port) & 0xf3) == 0) {
1456 printf(" port 0x%x is not an ESP board?\n", esp_port);
1461 * We've got something that claims to be a Hayes ESP card.
1465 /* Get the dip-switch configuration */
1467 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1468 dips = inb(esp_port + ESP98_STATUS1);
1470 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1471 dips = inb(esp_port + ESP_STATUS1);
1475 * Bits 0,1 of dips say which COM port we are.
1478 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1480 if (com->iobase == likely_com_ports[dips & 0x03])
1484 printf(" esp_port has com %d\n", dips & 0x03);
1489 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1492 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1493 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1494 val = inb(esp_port + ESP98_STATUS2);
1496 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1497 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1498 val = inb(esp_port + ESP_STATUS2);
1500 if ((val & 0x70) < 0x20) {
1501 printf("-old (%o)", val & 0x70);
1506 * Check for ability to emulate 16550: bit 7 == 1
1508 if ((dips & 0x80) == 0) {
1514 * Okay, we seem to be a Hayes ESP card. Whee.
1517 com->esp_port = esp_port;
1520 #endif /* COM_ESP */
1533 struct resource *res;
1535 u_int flags = isa_get_flags(dev);
1542 iobase = isa_get_port(dev);
1544 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1547 unit = device_get_unit(dev);
1548 com = device_get_softc(dev);
1551 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1553 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL)
1555 bzero(obuf, obufsize * 2);
1559 * sioprobe() has initialized the device registers as follows:
1560 * o cfcr = CFCR_8BITS.
1561 * It is most important that CFCR_DLAB is off, so that the
1562 * data port is not hidden when we enable interrupts.
1564 * Interrupts are only enabled when the line is open.
1565 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1566 * interrupt control register or the config specifies no irq.
1567 * Keeping MCR_DTR and MCR_RTS off might stop the external
1568 * device from sending before we are ready.
1570 bzero(com, sizeof *com);
1572 com->obufsize = obufsize;
1574 com->obuf2 = obuf + obufsize;
1577 com->cfcr_image = CFCR_8BITS;
1578 com->dtr_wait = 3 * hz;
1579 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1580 com->no_irq = isa_get_irq(dev) < 0;
1581 com->tx_fifo_size = 1;
1582 com->obufs[0].l_head = com->obuf1;
1583 com->obufs[1].l_head = com->obuf2;
1585 com->iobase = iobase;
1587 if (pc98_set_ioport(com, isa_get_flags(dev)) == -1) {
1588 com->pc98_if_type = (isa_get_flags(dev) >> 24) & 0xff;
1589 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1590 com->data_port = iobase + (com_data << port_shift);
1591 com->int_id_port = iobase + (com_iir << port_shift);
1592 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1593 com->mcr_image = inb(com->modem_ctl_port);
1594 com->line_status_port = iobase + (com_lsr << port_shift);
1595 com->modem_status_port = iobase + (com_msr << port_shift);
1596 com->intr_ctl_port = iobase + (com_ier << port_shift);
1598 #else /* not PC98 */
1599 com->data_port = iobase + com_data;
1600 com->int_id_port = iobase + com_iir;
1601 com->modem_ctl_port = iobase + com_mcr;
1602 com->mcr_image = inb(com->modem_ctl_port);
1603 com->line_status_port = iobase + com_lsr;
1604 com->modem_status_port = iobase + com_msr;
1605 com->intr_ctl_port = iobase + com_ier;
1609 * We don't use all the flags from <sys/ttydefaults.h> since they
1610 * are only relevant for logins. It's important to have echo off
1611 * initially so that the line doesn't start blathering before the
1612 * echo flag can be turned off.
1614 com->it_in.c_iflag = 0;
1615 com->it_in.c_oflag = 0;
1616 com->it_in.c_cflag = TTYDEF_CFLAG;
1617 com->it_in.c_lflag = 0;
1618 if (unit == comconsole) {
1620 if (IS_8251(com->pc98_if_type))
1623 com->it_in.c_iflag = TTYDEF_IFLAG;
1624 com->it_in.c_oflag = TTYDEF_OFLAG;
1625 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1626 com->it_in.c_lflag = TTYDEF_LFLAG;
1627 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1628 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1629 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1630 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1632 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1633 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1635 free(com, M_DEVBUF);
1639 termioschars(&com->it_in);
1640 com->it_out = com->it_in;
1642 /* attempt to determine UART type */
1643 printf("sio%d: type", unit);
1647 #ifdef COM_MULTIPORT
1648 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1650 if (!COM_IIR_TXRDYBUG(flags))
1657 scr = inb(iobase + com_scr);
1658 outb(iobase + com_scr, 0xa5);
1659 scr1 = inb(iobase + com_scr);
1660 outb(iobase + com_scr, 0x5a);
1661 scr2 = inb(iobase + com_scr);
1662 outb(iobase + com_scr, scr);
1663 if (scr1 != 0xa5 || scr2 != 0x5a) {
1665 goto determined_type;
1670 if (IS_8251(com->pc98_if_type)) {
1671 com_int_TxRx_disable( com );
1672 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1673 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1674 com_send_break_off( com );
1675 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1677 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1679 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1683 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1694 if (COM_NOFIFO(flags)) {
1695 printf(" 16550A fifo disabled");
1697 com->hasfifo = TRUE;
1699 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1702 if (COM_ST16650A(flags)) {
1704 com->tx_fifo_size = 32;
1705 printf(" ST16650A");
1707 com->tx_fifo_size = COM_FIFOSIZE(flags);
1713 if (com->pc98_if_type == COM_IF_RSA98III) {
1714 com->tx_fifo_size = 2048;
1715 com->rsabase = isa_get_port(dev);
1716 outb(com->rsabase + rsa_ier, 0x00);
1717 outb(com->rsabase + rsa_frr, 0x00);
1723 if (com->pc98_if_type == COM_IF_ESP98)
1725 for (espp = likely_esp_ports; *espp != 0; espp++)
1726 if (espattach(com, *espp)) {
1727 com->tx_fifo_size = 1024;
1731 if (!com->st16650a) {
1732 if (!com->tx_fifo_size)
1733 com->tx_fifo_size = 16;
1735 printf(" lookalike with %d bytes FIFO",
1743 if (com->pc98_if_type == COM_IF_RSB3000) {
1744 /* Set RSB-2000/3000 Extended Buffer mode. */
1746 lcr = inb(iobase + (com_cfcr << port_shift));
1747 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1748 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1749 outb(iobase + (com_cfcr << port_shift), lcr);
1756 * Set 16550 compatibility mode.
1757 * We don't use the ESP_MODE_SCALE bit to increase the
1758 * fifo trigger levels because we can't handle large
1760 * XXX flow control should be set in comparam(), not here.
1763 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1764 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1766 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1767 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1770 /* Set RTS/CTS flow control. */
1772 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1773 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1774 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1776 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1777 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1778 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1781 /* Set flow-control levels. */
1783 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1784 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1785 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1786 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1787 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1789 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1790 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1791 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1792 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1793 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1797 /* Set UART clock prescaler. */
1798 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1799 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1802 #endif /* COM_ESP */
1804 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1805 outb(iobase + (com_fifo << port_shift), 0);
1807 outb(iobase + com_fifo, 0);
1811 #ifdef COM_MULTIPORT
1812 if (COM_ISMULTIPORT(flags)) {
1813 com->multiport = TRUE;
1814 printf(" (multiport");
1815 if (unit == COM_MPMASTER(flags))
1819 isa_get_irq(devclass_get_device
1820 (sio_devclass, COM_MPMASTER(flags))) < 0;
1822 #endif /* COM_MULTIPORT */
1826 if (unit == comconsole)
1827 printf(", console");
1828 if ( COM_IIR_TXRDYBUG(flags) )
1829 printf(" with a bogus IIR_TXRDY register");
1832 if (!sio_registered) {
1833 register_swi(SWI_TTY, siopoll);
1834 sio_registered = TRUE;
1837 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
1839 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1840 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,
1841 unit | CONTROL_INIT_STATE, DV_CHR,
1842 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1843 com->devfs_token_ttyl = devfs_add_devswf(&sio_cdevsw,
1844 unit | CONTROL_LOCK_STATE, DV_CHR,
1845 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1846 com->devfs_token_cuaa = devfs_add_devswf(&sio_cdevsw,
1847 unit | CALLOUT_MASK, DV_CHR,
1848 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1849 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
1850 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
1851 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1852 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
1853 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
1854 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1856 com->flags = isa_get_flags(dev); /* Heritate id_flags for later */
1857 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1858 pps_init(&com->pps);
1860 res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1,
1861 RF_SHAREABLE | RF_ACTIVE);
1862 BUS_SETUP_INTR(device_get_parent(dev), dev, res,
1863 INTR_TYPE_TTY | INTR_TYPE_FAST,
1870 sioopen(dev, flag, mode, p)
1888 unit = MINOR_TO_UNIT(mynor);
1889 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1893 if (mynor & CONTROL_MASK)
1896 tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]);
1898 tp = com->tp = &sio_tty[unit];
1903 if (!IS_8251(com->pc98_if_type))
1904 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1907 * We jump to this label after all non-interrupted sleeps to pick
1908 * up any changes of the device state.
1911 while (com->state & CS_DTR_OFF) {
1912 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1913 if (com_addr(unit) == NULL)
1915 if (error != 0 || com->gone)
1918 if (tp->t_state & TS_ISOPEN) {
1920 * The device is open, so everything has been initialized.
1923 if (mynor & CALLOUT_MASK) {
1924 if (!com->active_out) {
1929 if (com->active_out) {
1930 if (flag & O_NONBLOCK) {
1934 error = tsleep(&com->active_out,
1935 TTIPRI | PCATCH, "siobi", 0);
1936 if (com_addr(unit) == NULL)
1938 if (error != 0 || com->gone)
1943 if (tp->t_state & TS_XCLUDE &&
1950 * The device isn't open, so there are no conflicts.
1951 * Initialize it. Initialization is done twice in many
1952 * cases: to preempt sleeping callin opens if we are
1953 * callout, and to complete a callin open after DCD rises.
1955 tp->t_oproc = comstart;
1956 tp->t_param = comparam;
1958 tp->t_termios = mynor & CALLOUT_MASK
1959 ? com->it_out : com->it_in;
1961 if (!IS_8251(com->pc98_if_type))
1963 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1964 com->poll = com->no_irq;
1965 com->poll_output = com->loses_outints;
1967 error = comparam(tp, &tp->t_termios);
1972 if (IS_8251(com->pc98_if_type)) {
1973 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1974 pc98_msrint_start(dev);
1978 * XXX we should goto open_top if comparam() slept.
1980 iobase = com->iobase;
1983 * (Re)enable and drain fifos.
1985 * Certain SMC chips cause problems if the fifos
1986 * are enabled while input is ready. Turn off the
1987 * fifo if necessary to clear the input. We test
1988 * the input ready bit after enabling the fifos
1989 * since we've already enabled them in comparam()
1990 * and to handle races between enabling and fresh
1995 outb(iobase + (com_fifo << port_shift),
1996 FIFO_RCV_RST | FIFO_XMT_RST
1998 if (com->pc98_if_type == COM_IF_RSA98III)
1999 outb(com->rsabase + rsa_frr , 0x00);
2001 outb(iobase + com_fifo,
2002 FIFO_RCV_RST | FIFO_XMT_RST
2006 * XXX the delays are for superstitious
2007 * historical reasons. It must be less than
2008 * the character time at the maximum
2009 * supported speed (87 usec at 115200 bps
2010 * 8N1). Otherwise we might loop endlessly
2011 * if data is streaming in. We used to use
2012 * delays of 100. That usually worked
2013 * because DELAY(100) used to usually delay
2014 * for about 85 usec instead of 100.
2018 if (!(inb(com->line_status_port) & LSR_RXRDY))
2020 if (com->pc98_if_type == COM_IF_RSA98III
2021 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2022 : !(inb(com->line_status_port) & LSR_RXRDY))
2026 outb(iobase + (com_fifo << port_shift), 0);
2028 outb(iobase + com_fifo, 0);
2031 (void) inb(com->data_port);
2037 if (IS_8251(com->pc98_if_type)) {
2038 com_tiocm_bis(com, TIOCM_LE);
2039 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2040 com_int_Rx_enable(com);
2043 (void) inb(com->line_status_port);
2044 (void) inb(com->data_port);
2045 com->prev_modem_status = com->last_modem_status
2046 = inb(com->modem_status_port);
2047 if (COM_IIR_TXRDYBUG(com->flags)) {
2048 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2051 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2052 | IER_ERLS | IER_EMSC);
2055 if (com->pc98_if_type == COM_IF_RSA98III) {
2056 outb(com->rsabase + rsa_ier, 0x1d);
2057 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2065 * Handle initial DCD. Callout devices get a fake initial
2066 * DCD (trapdoor DCD). If we are callout, then any sleeping
2067 * callin opens get woken up and resume sleeping on "siobi"
2068 * instead of "siodcd".
2071 * XXX `mynor & CALLOUT_MASK' should be
2072 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2073 * TRAPDOOR_CARRIER is the default initial state for callout
2074 * devices and SOFT_CARRIER is like CLOCAL except it hides
2078 if ((IS_8251(com->pc98_if_type) &&
2079 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2080 (!IS_8251(com->pc98_if_type) &&
2081 (com->prev_modem_status & MSR_DCD)) ||
2082 mynor & CALLOUT_MASK)
2084 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2086 (*linesw[tp->t_line].l_modem)(tp, 1);
2089 * Wait for DCD if necessary.
2091 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2092 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2094 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2095 if (com_addr(unit) == NULL)
2098 if (error != 0 || com->gone)
2102 error = (*linesw[tp->t_line].l_open)(dev, tp);
2103 disc_optim(tp, &tp->t_termios, com);
2104 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2105 com->active_out = TRUE;
2109 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2115 sioclose(dev, flag, mode, p)
2127 if (mynor & CONTROL_MASK)
2129 com = com_addr(MINOR_TO_UNIT(mynor));
2132 (*linesw[tp->t_line].l_close)(tp, flag);
2134 com->modem_checking = 0;
2136 disc_optim(tp, &tp->t_termios, com);
2137 siostop(tp, FREAD | FWRITE);
2143 printf("sio%d: gone\n", com->unit);
2145 if (com->ibuf != NULL)
2146 free(com->ibuf, M_DEVBUF);
2147 bzero(tp, sizeof *tp);
2148 free(com, M_DEVBUF);
2167 iobase = com->iobase;
2170 com->poll_output = FALSE;
2171 com->do_timestamp = FALSE;
2172 com->do_dcd_timestamp = FALSE;
2173 com->pps.ppsparam.mode = 0;
2175 if (IS_8251(com->pc98_if_type))
2176 com_send_break_off(com);
2178 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2179 outb(iobase + (com_cfcr << port_shift),
2180 com->cfcr_image &= ~CFCR_SBREAK);
2183 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2188 if (IS_8251(com->pc98_if_type))
2189 com_int_TxRx_disable(com);
2191 outb(iobase + (com_ier << port_shift), 0);
2192 if (com->pc98_if_type == COM_IF_RSA98III) {
2193 outb(com->rsabase + rsa_ier, 0x00);
2196 outb(iobase + com_ier, 0);
2200 if (IS_8251(com->pc98_if_type))
2201 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2203 tmp = com->prev_modem_status & MSR_DCD;
2205 if (tp->t_cflag & HUPCL
2207 * XXX we will miss any carrier drop between here and the
2208 * next open. Perhaps we should watch DCD even when the
2209 * port is closed; it is not sufficient to check it at
2210 * the next open because it might go up and down while
2211 * we're not watching.
2213 || (!com->active_out
2217 && !(com->prev_modem_status & MSR_DCD)
2219 && !(com->it_in.c_cflag & CLOCAL))
2220 || !(tp->t_state & TS_ISOPEN)) {
2222 if (IS_8251(com->pc98_if_type))
2223 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2226 (void)commctl(com, TIOCM_DTR, DMBIC);
2227 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2228 timeout(siodtrwakeup, com, com->dtr_wait);
2229 com->state |= CS_DTR_OFF;
2234 if (IS_8251(com->pc98_if_type))
2235 com_tiocm_bic(com, TIOCM_LE );
2241 * Disable fifos so that they are off after controlled
2242 * reboots. Some BIOSes fail to detect 16550s when the
2243 * fifos are enabled.
2246 outb(iobase + (com_fifo << port_shift), 0);
2248 outb(iobase + com_fifo, 0);
2251 com->active_out = FALSE;
2252 wakeup(&com->active_out);
2253 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2258 sioread(dev, uio, flag)
2267 if (mynor & CONTROL_MASK)
2269 com = com_addr(MINOR_TO_UNIT(mynor));
2272 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
2276 siowrite(dev, uio, flag)
2286 if (mynor & CONTROL_MASK)
2289 unit = MINOR_TO_UNIT(mynor);
2290 com = com_addr(unit);
2294 * (XXX) We disallow virtual consoles if the physical console is
2295 * a serial port. This is in case there is a display attached that
2296 * is not the console. In that situation we don't need/want the X
2297 * server taking over the console.
2299 if (constty != NULL && unit == comconsole)
2301 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
2311 com = (struct com_s *)chan;
2314 * Clear TS_BUSY if low-level output is complete.
2315 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2316 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2317 * called again. Reading the line status port outside of siointr1()
2318 * is safe because CS_BUSY is clear so there are no output interrupts
2322 if (com->state & CS_BUSY)
2323 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2325 else if ((IS_8251(com->pc98_if_type) &&
2326 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2327 == (STS8251_TxRDY | STS8251_TxEMP)) ||
2328 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2329 == (LSR_TSRE | LSR_TXRDY)) {
2331 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2332 == (LSR_TSRE | LSR_TXRDY)) {
2334 com->tp->t_state &= ~TS_BUSY;
2336 com->extra_state &= ~CSE_BUSYCHECK;
2338 timeout(siobusycheck, com, hz / 100);
2348 com = (struct com_s *)chan;
2349 com->state &= ~CS_DTR_OFF;
2350 wakeup(&com->dtr_wait);
2368 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2369 com_events -= (com->iptr - com->ibuf);
2370 com->iptr = com->ibuf;
2373 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2375 * Avoid the grotesquely inefficient lineswitch routine
2376 * (ttyinput) in "raw" mode. It usually takes about 450
2377 * instructions (that's without canonical processing or echo!).
2378 * slinput is reasonably fast (usually 40 instructions plus
2383 incc = com->iptr - buf;
2384 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2385 && (com->state & CS_RTS_IFLOW
2386 || tp->t_iflag & IXOFF)
2387 && !(tp->t_state & TS_TBLOCK))
2389 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2390 += b_to_q((char *)buf, incc, &tp->t_rawq);
2394 tp->t_rawcc += incc;
2396 if (tp->t_state & TS_TTSTOP
2397 && (tp->t_iflag & IXANY
2398 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2399 tp->t_state &= ~TS_TTSTOP;
2400 tp->t_lflag &= ~FLUSHO;
2404 } while (buf < com->iptr);
2408 line_status = buf[com->ierroff];
2411 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2412 if (line_status & LSR_BI)
2413 recv_data |= TTY_BI;
2414 if (line_status & LSR_FE)
2415 recv_data |= TTY_FE;
2416 if (line_status & LSR_OE)
2417 recv_data |= TTY_OE;
2418 if (line_status & LSR_PE)
2419 recv_data |= TTY_PE;
2421 (*linesw[tp->t_line].l_rint)(recv_data, tp);
2423 } while (buf < com->iptr);
2425 com_events -= (com->iptr - com->ibuf);
2426 com->iptr = com->ibuf;
2429 * There is now room for another low-level buffer full of input,
2430 * so enable RTS if it is now disabled and there is room in the
2431 * high-level buffer.
2434 if (IS_8251(com->pc98_if_type))
2435 tmp = com_tiocm_get(com) & TIOCM_RTS;
2437 tmp = com->mcr_image & MCR_RTS;
2438 if ((com->state & CS_RTS_IFLOW) && !(tmp) &&
2439 !(tp->t_state & TS_TBLOCK))
2440 if (IS_8251(com->pc98_if_type))
2441 com_tiocm_bis(com, TIOCM_RTS);
2443 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2445 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2446 !(tp->t_state & TS_TBLOCK))
2447 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2455 #ifndef COM_MULTIPORT
2457 siointr1((struct com_s *) arg);
2459 #else /* COM_MULTIPORT */
2460 bool_t possibly_more_intrs;
2464 u_char rsa_buf_status;
2468 * Loop until there is no activity on any port. This is necessary
2469 * to get an interrupt edge more than to avoid another interrupt.
2470 * If the IRQ signal is just an OR of the IRQ signals from several
2471 * devices, then the edge from one may be lost because another is
2476 possibly_more_intrs = FALSE;
2477 for (unit = 0; unit < NSIOTOT; ++unit) {
2478 com = com_addr(unit);
2481 * would it work here, or be counter-productive?
2486 && IS_8251(com->pc98_if_type)){
2493 && com->pc98_if_type == COM_IF_RSA98III) {
2494 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2495 if ((rsa_buf_status & 0xc8)
2496 || !(rsa_buf_status & 0x01)) {
2499 != (inb(com->rsabase + rsa_srr) & 0xc9))
2500 possibly_more_intrs = TRUE;
2506 && (inb(com->int_id_port) & IIR_IMASK)
2509 possibly_more_intrs = TRUE;
2511 /* XXX COM_UNLOCK(); */
2513 } while (possibly_more_intrs);
2515 #endif /* COM_MULTIPORT */
2523 u_char modem_status;
2528 struct timecounter *tc;
2533 u_char rsa_buf_status = 0;
2534 int rsa_tx_fifo_size=0;
2538 int_ctl = inb(com->intr_ctl_port);
2539 int_ctl_new = int_ctl;
2541 while (!com->gone) {
2544 if (IS_8251(com->pc98_if_type)) {
2545 tmp = inb(com->sts_port);
2548 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2549 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2550 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2551 if (tmp & STS8251_PE) line_status |= LSR_PE;
2552 if (tmp & STS8251_OE) line_status |= LSR_OE;
2553 if (tmp & STS8251_FE) line_status |= LSR_FE;
2554 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2557 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2558 modem_status = inb(com->modem_status_port);
2559 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2561 count = tc->tc_get_timecount(tc);
2562 pps_event(&com->pps, tc, count,
2563 (modem_status & MSR_DCD) ?
2564 PPS_CAPTURECLEAR : PPS_CAPTUREASSERT);
2567 line_status = inb(com->line_status_port);
2570 if (com->pc98_if_type == COM_IF_RSA98III)
2571 rsa_buf_status = inb(com->rsabase + rsa_srr);
2574 /* input event? (check first to help avoid overruns) */
2576 while (line_status & LSR_RCV_MASK) {
2578 while ((line_status & LSR_RCV_MASK)
2579 || (com->pc98_if_type == COM_IF_RSA98III
2580 && (rsa_buf_status & 0x08))) {
2582 /* break/unnattached error bits or real input? */
2584 if (IS_8251(com->pc98_if_type)) {
2585 recv_data = inb(com->data_port);
2587 pc98_i8251_or_cmd(com,CMD8251_ER);
2593 if (com->pc98_if_type == COM_IF_RSA98III) {
2594 if (!(rsa_buf_status & 0x08))
2597 recv_data = inb(com->data_port);
2601 if (!(line_status & LSR_RXRDY))
2604 recv_data = inb(com->data_port);
2608 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2610 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2611 * Otherwise, push the work to a higher level
2612 * (to handle PARMRK) if we're bypassing.
2613 * Otherwise, convert BI/FE and PE+INPCK to 0.
2615 * This makes bypassing work right in the
2616 * usual "raw" case (IGNBRK set, and IGNPAR
2619 * Note: BI together with FE/PE means just BI.
2621 if (line_status & LSR_BI) {
2622 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2623 if (com->unit == comconsole) {
2629 || com->tp->t_iflag & IGNBRK)
2633 || com->tp->t_iflag & IGNPAR)
2636 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2637 && (line_status & (LSR_BI | LSR_FE)
2638 || com->tp->t_iflag & INPCK))
2642 if (com->hotchar != 0 && recv_data == com->hotchar)
2645 if (ioptr >= com->ibufend)
2646 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2648 if (com->do_timestamp)
2649 microtime(&com->timestamp);
2652 #if 0 /* for testing input latency vs efficiency */
2653 if (com->iptr - com->ibuf == 8)
2656 ioptr[0] = recv_data;
2657 ioptr[com->ierroff] = line_status;
2658 com->iptr = ++ioptr;
2659 if (ioptr == com->ihighwater
2660 && com->state & CS_RTS_IFLOW)
2662 if (IS_8251(com->pc98_if_type))
2663 com_tiocm_bic(com, TIOCM_RTS);
2666 outb(com->modem_ctl_port,
2667 com->mcr_image &= ~MCR_RTS);
2668 if (line_status & LSR_OE)
2669 CE_RECORD(com, CE_OVERRUN);
2673 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2674 * jump from the top of the loop to here
2677 if (IS_8251(com->pc98_if_type))
2681 line_status = inb(com->line_status_port) & 0x7F;
2683 if (com->pc98_if_type == COM_IF_RSA98III)
2684 rsa_buf_status = inb(com->rsabase + rsa_srr);
2688 /* modem status change? (always check before doing output) */
2690 if (!IS_8251(com->pc98_if_type)) {
2692 modem_status = inb(com->modem_status_port);
2693 if (modem_status != com->last_modem_status) {
2694 if (com->do_dcd_timestamp
2695 && !(com->last_modem_status & MSR_DCD)
2696 && modem_status & MSR_DCD)
2697 microtime(&com->dcd_timestamp);
2700 * Schedule high level to handle DCD changes. Note
2701 * that we don't use the delta bits anywhere. Some
2702 * UARTs mess them up, and it's easy to remember the
2703 * previous bits and calculate the delta.
2705 com->last_modem_status = modem_status;
2706 if (!(com->state & CS_CHECKMSR)) {
2707 com_events += LOTS_OF_EVENTS;
2708 com->state |= CS_CHECKMSR;
2712 /* handle CTS change immediately for crisp flow ctl */
2713 if (com->state & CS_CTS_OFLOW) {
2714 if (modem_status & MSR_CTS)
2715 com->state |= CS_ODEVREADY;
2717 com->state &= ~CS_ODEVREADY;
2724 /* output queued and everything ready? */
2726 if (line_status & LSR_TXRDY
2727 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2729 if (((com->pc98_if_type == COM_IF_RSA98III)
2730 ? (rsa_buf_status & 0x02)
2731 : (line_status & LSR_TXRDY))
2732 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2734 ioptr = com->obufq.l_head;
2735 if (com->tx_fifo_size > 1) {
2738 ocount = com->obufq.l_tail - ioptr;
2740 if (com->pc98_if_type == COM_IF_RSA98III) {
2741 rsa_buf_status = inb(com->rsabase + rsa_srr);
2742 rsa_tx_fifo_size = 1024;
2743 if (!(rsa_buf_status & 0x01))
2744 rsa_tx_fifo_size = 2048;
2745 if (ocount > rsa_tx_fifo_size)
2746 ocount = rsa_tx_fifo_size;
2749 if (ocount > com->tx_fifo_size)
2750 ocount = com->tx_fifo_size;
2751 com->bytes_out += ocount;
2753 outb(com->data_port, *ioptr++);
2754 while (--ocount != 0);
2756 outb(com->data_port, *ioptr++);
2760 if (IS_8251(com->pc98_if_type))
2761 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2762 com_int_Tx_enable(com);
2764 com->obufq.l_head = ioptr;
2765 if (COM_IIR_TXRDYBUG(com->flags)) {
2766 int_ctl_new = int_ctl | IER_ETXRDY;
2768 if (ioptr >= com->obufq.l_tail) {
2771 qp = com->obufq.l_next;
2772 qp->l_queued = FALSE;
2775 com->obufq.l_head = qp->l_head;
2776 com->obufq.l_tail = qp->l_tail;
2777 com->obufq.l_next = qp;
2779 /* output just completed */
2780 if ( COM_IIR_TXRDYBUG(com->flags) ) {
2781 int_ctl_new = int_ctl & ~IER_ETXRDY;
2783 com->state &= ~CS_BUSY;
2785 if (IS_8251(com->pc98_if_type))
2786 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2787 com_int_Tx_disable(com);
2790 if (!(com->state & CS_ODONE)) {
2791 com_events += LOTS_OF_EVENTS;
2792 com->state |= CS_ODONE;
2793 setsofttty(); /* handle at high level ASAP */
2796 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2798 if (com->pc98_if_type == COM_IF_RSA98III) {
2799 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2800 outb(com->intr_ctl_port, int_ctl_new);
2801 outb(com->rsabase + rsa_ier, 0x1d);
2804 outb(com->intr_ctl_port, int_ctl_new);
2808 else if (line_status & LSR_TXRDY) {
2809 if (IS_8251(com->pc98_if_type))
2810 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2811 com_int_Tx_disable(com);
2813 if (IS_8251(com->pc98_if_type))
2814 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2819 #ifndef COM_MULTIPORT
2821 if (IS_8251(com->pc98_if_type))
2824 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2825 #endif /* COM_MULTIPORT */
2831 sioioctl(dev, cmd, data, flag, p)
2844 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2846 struct termios term;
2850 com = com_addr(MINOR_TO_UNIT(mynor));
2853 iobase = com->iobase;
2854 if (mynor & CONTROL_MASK) {
2857 switch (mynor & CONTROL_MASK) {
2858 case CONTROL_INIT_STATE:
2859 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2861 case CONTROL_LOCK_STATE:
2862 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2865 return (ENODEV); /* /dev/nodev */
2872 *ct = *(struct termios *)data;
2875 *(struct termios *)data = *ct;
2878 *(int *)data = TTYDISC;
2881 bzero(data, sizeof(struct winsize));
2888 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2889 term = tp->t_termios;
2891 error = ttsetcompat(tp, &cmd, data, &term);
2895 data = (caddr_t)&term;
2897 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2899 struct termios *dt = (struct termios *)data;
2900 struct termios *lt = mynor & CALLOUT_MASK
2901 ? &com->lt_out : &com->lt_in;
2903 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2904 | (dt->c_iflag & ~lt->c_iflag);
2905 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2906 | (dt->c_oflag & ~lt->c_oflag);
2907 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2908 | (dt->c_cflag & ~lt->c_cflag);
2909 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2910 | (dt->c_lflag & ~lt->c_lflag);
2911 for (cc = 0; cc < NCCS; ++cc)
2912 if (lt->c_cc[cc] != 0)
2913 dt->c_cc[cc] = tp->t_cc[cc];
2914 if (lt->c_ispeed != 0)
2915 dt->c_ispeed = tp->t_ispeed;
2916 if (lt->c_ospeed != 0)
2917 dt->c_ospeed = tp->t_ospeed;
2919 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2920 if (error != ENOIOCTL)
2923 error = ttioctl(tp, cmd, data, flag);
2924 disc_optim(tp, &tp->t_termios, com);
2925 if (error != ENOIOCTL) {
2930 if (IS_8251(com->pc98_if_type)) {
2933 com_send_break_on( com );
2936 com_send_break_off( com );
2939 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
2942 com_tiocm_bic(com, TIOCM_DTR);
2945 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2946 * changes get undone on the next call to comparam().
2949 com_tiocm_set( com, *(int *)data );
2952 com_tiocm_bis( com, *(int *)data );
2955 com_tiocm_bic( com, *(int *)data );
2958 *(int *)data = com_tiocm_get(com);
2961 /* must be root since the wait applies to following logins */
2967 com->dtr_wait = *(int *)data * hz / 100;
2970 *(int *)data = com->dtr_wait * 100 / hz;
2973 com->do_timestamp = TRUE;
2974 *(struct timeval *)data = com->timestamp;
2976 case TIOCDCDTIMESTAMP:
2977 com->do_dcd_timestamp = TRUE;
2978 *(struct timeval *)data = com->dcd_timestamp;
2986 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2991 outb(iobase + (com_cfcr << port_shift),
2992 com->cfcr_image |= CFCR_SBREAK);
2994 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2999 outb(iobase + (com_cfcr << port_shift),
3000 com->cfcr_image &= ~CFCR_SBREAK);
3002 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
3006 (void)commctl(com, TIOCM_DTR, DMBIS);
3009 (void)commctl(com, TIOCM_DTR, DMBIC);
3012 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3013 * changes get undone on the next call to comparam().
3016 (void)commctl(com, *(int *)data, DMSET);
3019 (void)commctl(com, *(int *)data, DMBIS);
3022 (void)commctl(com, *(int *)data, DMBIC);
3025 *(int *)data = commctl(com, 0, DMGET);
3028 /* must be root since the wait applies to following logins */
3034 com->dtr_wait = *(int *)data * hz / 100;
3037 *(int *)data = com->dtr_wait * 100 / hz;
3040 com->do_timestamp = TRUE;
3041 *(struct timeval *)data = com->timestamp;
3043 case TIOCDCDTIMESTAMP:
3044 com->do_dcd_timestamp = TRUE;
3045 *(struct timeval *)data = com->dcd_timestamp;
3049 error = pps_ioctl(cmd, data, &com->pps);
3050 if (error == ENODEV)
3066 if (com_events == 0)
3069 for (unit = 0; unit < NSIOTOT; ++unit) {
3074 com = com_addr(unit);
3078 if (tp == NULL || com->gone) {
3080 * Discard any events related to never-opened or
3081 * going-away devices.
3084 incc = com->iptr - com->ibuf;
3085 com->iptr = com->ibuf;
3086 if (com->state & CS_CHECKMSR) {
3087 incc += LOTS_OF_EVENTS;
3088 com->state &= ~CS_CHECKMSR;
3094 if (com->iptr != com->ibuf) {
3099 if (com->state & CS_CHECKMSR) {
3100 u_char delta_modem_status;
3103 if (!IS_8251(com->pc98_if_type)) {
3106 delta_modem_status = com->last_modem_status
3107 ^ com->prev_modem_status;
3108 com->prev_modem_status = com->last_modem_status;
3109 com_events -= LOTS_OF_EVENTS;
3110 com->state &= ~CS_CHECKMSR;
3112 if (delta_modem_status & MSR_DCD)
3113 (*linesw[tp->t_line].l_modem)
3114 (tp, com->prev_modem_status & MSR_DCD);
3119 if (com->state & CS_ODONE) {
3121 com_events -= LOTS_OF_EVENTS;
3122 com->state &= ~CS_ODONE;
3124 if (!(com->state & CS_BUSY)
3125 && !(com->extra_state & CSE_BUSYCHECK)) {
3126 timeout(siobusycheck, com, hz / 100);
3127 com->extra_state |= CSE_BUSYCHECK;
3129 (*linesw[tp->t_line].l_start)(tp);
3131 if (com_events == 0)
3134 if (com_events >= LOTS_OF_EVENTS)
3159 unit = DEV_TO_UNIT(tp->t_dev);
3160 com = com_addr(unit);
3161 iobase = com->iobase;
3162 if (IS_8251(com->pc98_if_type)) {
3163 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3165 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3167 /* do historical conversions */
3168 if (t->c_ispeed == 0)
3169 t->c_ispeed = t->c_ospeed;
3171 /* check requested parameters */
3172 divisor = ttspeedtab(t->c_ospeed,
3173 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3176 /* do historical conversions */
3177 if (t->c_ispeed == 0)
3178 t->c_ispeed = t->c_ospeed;
3180 /* check requested parameters */
3181 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3183 if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed)
3186 /* parameters are OK, convert them to the com struct and the device */
3188 unit = DEV_TO_UNIT(tp->t_dev);
3189 com = com_addr(unit);
3190 iobase = com->iobase;
3194 if (IS_8251(com->pc98_if_type)) {
3196 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3198 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3202 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3204 (void)commctl(com, TIOCM_DTR, DMBIS);
3210 if (!IS_8251(com->pc98_if_type)) {
3212 switch (cflag & CSIZE) {
3226 if (cflag & PARENB) {
3228 if (!(cflag & PARODD))
3234 if (com->hasfifo && divisor != 0) {
3236 * Use a fifo trigger level low enough so that the input
3237 * latency from the fifo is less than about 16 msec and
3238 * the total latency is less than about 30 msec. These
3239 * latencies are reasonable for humans. Serial comms
3240 * protocols shouldn't expect anything better since modem
3241 * latencies are larger.
3243 com->fifo_image = t->c_ospeed <= 4800
3244 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3247 * The Hayes ESP card needs the fifo DMA mode bit set
3248 * in compatibility mode. If not, it will interrupt
3249 * for each character received.
3252 com->fifo_image |= FIFO_DMA_MODE;
3255 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3257 outb(iobase + com_fifo, com->fifo_image);
3265 * This returns with interrupts disabled so that we can complete
3266 * the speed change atomically. Keeping interrupts disabled is
3267 * especially important while com_data is hidden.
3269 (void) siosetwater(com, t->c_ispeed);
3272 if (IS_8251(com->pc98_if_type))
3273 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3278 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3280 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3283 * Only set the divisor registers if they would change,
3284 * since on some 16550 incompatibles (UMC8669F), setting
3285 * them while input is arriving them loses sync until
3286 * data stops arriving.
3288 dlbl = divisor & 0xFF;
3290 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3291 outb(iobase + (com_dlbl << port_shift), dlbl);
3292 dlbh = (u_int) divisor >> 8;
3293 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3294 outb(iobase + (com_dlbh << port_shift), dlbh);
3296 if (inb(iobase + com_dlbl) != dlbl)
3297 outb(iobase + com_dlbl, dlbl);
3298 dlbh = (u_int) divisor >> 8;
3299 if (inb(iobase + com_dlbh) != dlbh)
3300 outb(iobase + com_dlbh, dlbh);
3307 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3309 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3312 if (!(tp->t_state & TS_TTSTOP))
3313 com->state |= CS_TTGO;
3315 if (cflag & CRTS_IFLOW) {
3316 if (com->st16650a) {
3317 outb(iobase + com_cfcr, 0xbf);
3318 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3320 com->state |= CS_RTS_IFLOW;
3322 * If CS_RTS_IFLOW just changed from off to on, the change
3323 * needs to be propagated to MCR_RTS. This isn't urgent,
3324 * so do it later by calling comstart() instead of repeating
3325 * a lot of code from comstart() here.
3327 } else if (com->state & CS_RTS_IFLOW) {
3328 com->state &= ~CS_RTS_IFLOW;
3330 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3331 * on here, since comstart() won't do it later.
3334 if (IS_8251(com->pc98_if_type))
3335 com_tiocm_bis(com, TIOCM_RTS);
3338 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3339 if (com->st16650a) {
3340 outb(iobase + com_cfcr, 0xbf);
3341 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3347 * Set up state to handle output flow control.
3348 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3349 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3351 com->state |= CS_ODEVREADY;
3352 com->state &= ~CS_CTS_OFLOW;
3354 if (com->pc98_if_type == COM_IF_RSA98III) {
3355 param = inb(com->rsabase + rsa_msr);
3356 outb(com->rsabase + rsa_msr, param & 0x14);
3359 if (cflag & CCTS_OFLOW) {
3360 com->state |= CS_CTS_OFLOW;
3362 if (IS_8251(com->pc98_if_type)) {
3363 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3364 com->state &= ~CS_ODEVREADY;
3368 if (com->pc98_if_type == COM_IF_RSA98III) {
3369 /* Set automatic flow control mode */
3370 outb(com->rsabase + rsa_msr, param | 0x08);
3373 if (!(com->last_modem_status & MSR_CTS))
3374 com->state &= ~CS_ODEVREADY;
3375 if (com->st16650a) {
3376 outb(iobase + com_cfcr, 0xbf);
3377 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3383 if (com->st16650a) {
3384 outb(iobase + com_cfcr, 0xbf);
3385 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3391 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3393 outb(iobase + com_cfcr, com->cfcr_image);
3397 /* XXX shouldn't call functions while intrs are disabled. */
3398 disc_optim(tp, t, com);
3400 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3401 * unconditionally, but that defeated the careful discarding of
3402 * stale input in sioopen().
3404 if (com->state >= (CS_BUSY | CS_TTGO))
3410 if (com->ibufold != NULL) {
3411 free(com->ibufold, M_DEVBUF);
3412 com->ibufold = NULL;
3418 siosetwater(com, speed)
3428 * Make the buffer size large enough to handle a softtty interrupt
3429 * latency of about 2 ticks without loss of throughput or data
3430 * (about 3 ticks if input flow control is not used or not honoured,
3431 * but a bit less for CS5-CS7 modes).
3433 cp4ticks = speed / 10 / hz * 4;
3434 for (ibufsize = 128; ibufsize < cp4ticks;)
3437 if (com->pc98_if_type == COM_IF_RSA98III)
3440 if (ibufsize == com->ibufsize) {
3446 * Allocate input buffer. The extra factor of 2 in the size is
3447 * to allow for an error byte for each input byte.
3449 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3455 /* Initialize non-critical variables. */
3456 com->ibufold = com->ibuf;
3457 com->ibufsize = ibufsize;
3460 tp->t_ififosize = 2 * ibufsize;
3461 tp->t_ispeedwat = (speed_t)-1;
3462 tp->t_ospeedwat = (speed_t)-1;
3466 * Read current input buffer, if any. Continue with interrupts
3470 if (com->iptr != com->ibuf)
3474 * Initialize critical variables, including input buffer watermarks.
3475 * The external device is asked to stop sending when the buffer
3476 * exactly reaches high water, or when the high level requests it.
3477 * The high level is notified immediately (rather than at a later
3478 * clock tick) when this watermark is reached.
3479 * The buffer size is chosen so the watermark should almost never
3481 * The low watermark is invisibly 0 since the buffer is always
3482 * emptied all at once.
3484 com->iptr = com->ibuf = ibuf;
3485 com->ibufend = ibuf + ibufsize;
3486 com->ierroff = ibufsize;
3487 com->ihighwater = ibuf + 3 * ibufsize / 4;
3502 unit = DEV_TO_UNIT(tp->t_dev);
3503 com = com_addr(unit);
3506 if (tp->t_state & TS_TTSTOP)
3507 com->state &= ~CS_TTGO;
3509 com->state |= CS_TTGO;
3510 if (tp->t_state & TS_TBLOCK) {
3512 if (IS_8251(com->pc98_if_type))
3513 tmp = com_tiocm_get(com) & TIOCM_RTS;
3515 tmp = com->mcr_image & MCR_RTS;
3516 if (tmp && (com->state & CS_RTS_IFLOW))
3518 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3521 if (IS_8251(com->pc98_if_type))
3522 com_tiocm_bic(com, TIOCM_RTS);
3525 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3528 if (IS_8251(com->pc98_if_type))
3529 tmp = com_tiocm_get(com) & TIOCM_RTS;
3531 tmp = com->mcr_image & MCR_RTS;
3532 if (!(tmp) && com->iptr < com->ihighwater
3533 && com->state & CS_RTS_IFLOW)
3535 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3536 && com->state & CS_RTS_IFLOW)
3539 if (IS_8251(com->pc98_if_type))
3540 com_tiocm_bis(com, TIOCM_RTS);
3543 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3546 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3549 /* if(IS_8251(com->pc98_if_type))
3550 com_int_Tx_enable(com); */
3555 if (tp->t_outq.c_cc != 0) {
3559 if (!com->obufs[0].l_queued) {
3560 com->obufs[0].l_tail
3561 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3567 com->obufs[0].l_next = NULL;
3568 com->obufs[0].l_queued = TRUE;
3570 if (com->state & CS_BUSY) {
3571 qp = com->obufq.l_next;
3572 while ((next = qp->l_next) != NULL)
3574 qp->l_next = &com->obufs[0];
3576 com->obufq.l_head = com->obufs[0].l_head;
3577 com->obufq.l_tail = com->obufs[0].l_tail;
3578 com->obufq.l_next = &com->obufs[0];
3579 com->state |= CS_BUSY;
3583 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3584 com->obufs[1].l_tail
3585 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3591 com->obufs[1].l_next = NULL;
3592 com->obufs[1].l_queued = TRUE;
3594 if (com->state & CS_BUSY) {
3595 qp = com->obufq.l_next;
3596 while ((next = qp->l_next) != NULL)
3598 qp->l_next = &com->obufs[1];
3600 com->obufq.l_head = com->obufs[1].l_head;
3601 com->obufq.l_tail = com->obufs[1].l_tail;
3602 com->obufq.l_next = &com->obufs[1];
3603 com->state |= CS_BUSY;
3607 tp->t_state |= TS_BUSY;
3610 if (com->state >= (CS_BUSY | CS_TTGO))
3611 siointr1(com); /* fake interrupt to start output */
3614 /* if(IS_8251(com->pc98_if_type))
3615 com_int_Tx_enable(com); */
3632 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3636 if (!IS_8251(com->pc98_if_type))
3637 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3643 /* XXX avoid h/w bug. */
3647 outb(com->iobase + (com_fifo << port_shift),
3648 FIFO_XMT_RST | com->fifo_image);
3649 if (com->pc98_if_type == COM_IF_RSA98III)
3650 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3651 outb(com->iobase + (com_fifo << port_shift),
3652 FIFO_XMT_RST | com->fifo_image);
3654 outb(com->iobase + com_fifo,
3655 FIFO_XMT_RST | com->fifo_image);
3657 com->obufs[0].l_queued = FALSE;
3658 com->obufs[1].l_queued = FALSE;
3659 if (com->state & CS_ODONE)
3660 com_events -= LOTS_OF_EVENTS;
3661 com->state &= ~(CS_ODONE | CS_BUSY);
3662 com->tp->t_state &= ~TS_BUSY;
3667 /* XXX avoid h/w bug. */
3671 if (com->pc98_if_type == COM_IF_RSA98III) {
3672 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3673 inb(com->data_port);
3675 outb(com->iobase + (com_fifo << port_shift),
3676 FIFO_RCV_RST | com->fifo_image);
3678 outb(com->iobase + com_fifo,
3679 FIFO_RCV_RST | com->fifo_image);
3681 com_events -= (com->iptr - com->ibuf);
3682 com->iptr = com->ibuf;
3696 if (mynor & CONTROL_MASK)
3698 unit = MINOR_TO_UNIT(mynor);
3699 if ((u_int) unit >= NSIOTOT)
3701 return (&sio_tty[unit]);
3705 commctl(com, bits, how)
3714 bits = TIOCM_LE; /* XXX - always enabled while open */
3715 mcr = com->mcr_image;
3720 msr = com->prev_modem_status;
3728 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3729 * more volatile by reading the modem status a lot. Perhaps
3730 * we should latch both bits until the status is read here.
3732 if (msr & (MSR_RI | MSR_TERI))
3737 if (bits & TIOCM_DTR)
3739 if (bits & TIOCM_RTS)
3746 outb(com->modem_ctl_port,
3747 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3750 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3753 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3768 * Set our timeout period to 1 second if no polled devices are open.
3769 * Otherwise set it to max(1/200, 1/hz).
3770 * Enable timeouts iff some device is open.
3772 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3775 for (unit = 0; unit < NSIOTOT; ++unit) {
3776 com = com_addr(unit);
3777 if (com != NULL && com->tp != NULL
3778 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3780 if (com->poll || com->poll_output) {
3781 sio_timeout = hz > 200 ? hz / 200 : 1;
3787 sio_timeouts_until_log = hz / sio_timeout;
3788 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3791 /* Flush error messages, if any. */
3792 sio_timeouts_until_log = 1;
3793 comwakeup((void *)NULL);
3794 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3805 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3808 * Recover from lost output interrupts.
3809 * Poll any lines that don't use interrupts.
3811 for (unit = 0; unit < NSIOTOT; ++unit) {
3812 com = com_addr(unit);
3813 if (com != NULL && !com->gone
3814 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3822 * Check for and log errors, but not too often.
3824 if (--sio_timeouts_until_log > 0)
3826 sio_timeouts_until_log = hz / sio_timeout;
3827 for (unit = 0; unit < NSIOTOT; ++unit) {
3830 com = com_addr(unit);
3835 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3840 delta = com->delta_error_counts[errnum];
3841 com->delta_error_counts[errnum] = 0;
3845 total = com->error_counts[errnum] += delta;
3846 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3847 unit, delta, error_desc[errnum],
3848 delta == 1 ? "" : "s", total);
3854 /* commint is called when modem control line changes */
3858 register struct tty *tp;
3864 unit = MINOR_TO_UNIT(mynor);
3865 com = com_addr(unit);
3868 stat = com_tiocm_get(com);
3869 delta = com_tiocm_get_delta(com);
3871 if (com->state & CS_CTS_OFLOW) {
3872 if (stat & TIOCM_CTS)
3873 com->state |= CS_ODEVREADY;
3875 com->state &= ~CS_ODEVREADY;
3877 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3878 if (stat & TIOCM_CAR )
3879 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
3880 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
3881 /* negate DTR, RTS */
3882 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3883 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3884 /* disable IENABLE */
3885 com_int_TxRx_disable( com );
3892 disc_optim(tp, t, com)
3897 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
3898 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
3899 && (!(t->c_iflag & PARMRK)
3900 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
3901 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
3902 && linesw[tp->t_line].l_rint == ttyinput)
3903 tp->t_state |= TS_CAN_BYPASS_L_RINT;
3905 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
3906 com->hotchar = linesw[tp->t_line].l_hotchar;
3910 * Following are all routines needed for SIO to act as console
3912 #include <sys/cons.h>
3922 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3923 static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
3924 static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
3925 static void siocntxwait __P((Port_t iobase));
3928 static cn_probe_t siocnprobe;
3929 static cn_init_t siocninit;
3930 static cn_checkc_t siocncheckc;
3931 static cn_getc_t siocngetc;
3932 static cn_putc_t siocnputc;
3934 CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc);
3936 /* To get the GDB related variables */
3938 #include <ddb/ddb.h>
3949 * Wait for any pending transmission to finish. Required to avoid
3950 * the UART lockup bug when the speed is changed, and for normal
3954 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3955 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3960 * Read the serial port specified and try to figure out what speed
3961 * it's currently running at. We're assuming the serial port has
3962 * been initialized and is basicly idle. This routine is only intended
3963 * to be run at system startup.
3965 * If the value read from the serial port doesn't make sense, return 0.
3969 siocngetspeed(iobase, table)
3971 struct speedtab *table;
3978 cfcr = inb(iobase + com_cfcr);
3979 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3981 dlbl = inb(iobase + com_dlbl);
3982 dlbh = inb(iobase + com_dlbh);
3984 outb(iobase + com_cfcr, cfcr);
3986 code = dlbh << 8 | dlbl;
3988 for ( ; table->sp_speed != -1; table++)
3989 if (table->sp_code == code)
3990 return (table->sp_speed);
3992 return 0; /* didn't match anything sane */
3996 siocnopen(sp, iobase, speed)
3997 struct siocnstate *sp;
4006 * Save all the device control registers except the fifo register
4007 * and set our default ones (cs8 -parenb speed=comdefaultrate).
4008 * We can't save the fifo register since it is read-only.
4010 sp->ier = inb(iobase + com_ier);
4011 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
4012 siocntxwait(iobase);
4013 sp->cfcr = inb(iobase + com_cfcr);
4014 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4015 sp->dlbl = inb(iobase + com_dlbl);
4016 sp->dlbh = inb(iobase + com_dlbh);
4018 * Only set the divisor registers if they would change, since on
4019 * some 16550 incompatibles (Startech), setting them clears the
4020 * data input register. This also reduces the effects of the
4023 divisor = ttspeedtab(speed, comspeedtab);
4024 dlbl = divisor & 0xFF;
4025 if (sp->dlbl != dlbl)
4026 outb(iobase + com_dlbl, dlbl);
4027 dlbh = (u_int) divisor >> 8;
4028 if (sp->dlbh != dlbh)
4029 outb(iobase + com_dlbh, dlbh);
4030 outb(iobase + com_cfcr, CFCR_8BITS);
4031 sp->mcr = inb(iobase + com_mcr);
4033 * We don't want interrupts, but must be careful not to "disable"
4034 * them by clearing the MCR_IENABLE bit, since that might cause
4035 * an interrupt by floating the IRQ line.
4037 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4041 siocnclose(sp, iobase)
4042 struct siocnstate *sp;
4046 * Restore the device control registers.
4048 siocntxwait(iobase);
4049 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4050 if (sp->dlbl != inb(iobase + com_dlbl))
4051 outb(iobase + com_dlbl, sp->dlbl);
4052 if (sp->dlbh != inb(iobase + com_dlbh))
4053 outb(iobase + com_dlbh, sp->dlbh);
4054 outb(iobase + com_cfcr, sp->cfcr);
4056 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4058 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4059 outb(iobase + com_ier, sp->ier);
4072 struct siocnstate sp;
4075 * Find our first enabled console, if any. If it is a high-level
4076 * console device, then initialize it and return successfully.
4077 * If it is a low-level console device, then initialize it and
4078 * return unsuccessfully. It must be initialized in both cases
4079 * for early use by console drivers and debuggers. Initializing
4080 * the hardware is not necessary in all cases, since the i/o
4081 * routines initialize it on the fly, but it is necessary if
4082 * input might arrive while the hardware is switched back to an
4083 * uninitialized state. We can't handle multiple console devices
4084 * yet because our low-level routines don't take a device arg.
4085 * We trust the user to set the console flags properly so that we
4086 * don't need to probe.
4088 cp->cn_pri = CN_DEAD;
4090 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4092 if (resource_int_value("sio", unit, "flags", &flags))
4094 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4098 if (resource_int_value("sio", unit, "port", &port))
4102 if (boothowto & RB_SERIAL) {
4103 boot_speed = siocngetspeed(iobase, comspeedtab);
4105 comdefaultrate = boot_speed;
4109 * Initialize the divisor latch. We can't rely on
4110 * siocnopen() to do this the first time, since it
4111 * avoids writing to the latch if the latch appears
4112 * to have the correct value. Also, if we didn't
4113 * just read the speed from the hardware, then we
4114 * need to set the speed in hardware so that
4115 * switching it later is null.
4117 cfcr = inb(iobase + com_cfcr);
4118 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4119 outb(iobase + com_dlbl,
4120 COMBRD(comdefaultrate) & 0xff);
4121 outb(iobase + com_dlbh,
4122 (u_int) COMBRD(comdefaultrate) >> 8);
4123 outb(iobase + com_cfcr, cfcr);
4125 siocnopen(&sp, iobase, comdefaultrate);
4128 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4129 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4130 cp->cn_pri = COM_FORCECONSOLE(flags)
4131 || boothowto & RB_SERIAL
4132 ? CN_REMOTE : CN_NORMAL;
4133 printf("sio%d: system console\n", unit);
4134 siocniobase = iobase;
4137 if (COM_DEBUGGER(flags) && !COM_LLCONSOLE(flags)) {
4138 printf("sio%d: gdb debugging port\n", unit);
4139 siogdbiobase = iobase;
4143 gdbdev = makedev(CDEV_MAJOR, unit);
4144 gdb_getc = siocngetc;
4145 gdb_putc = siocnputc;
4154 * XXX Ugly Compatability.
4155 * If no gdb port has been specified, set it to be the console
4156 * as some configuration files don't specify the gdb port.
4158 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
4159 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
4161 printf("Set flag 0x80 on desired GDB port in your\n");
4162 printf("configuration file (currently sio only).\n");
4163 siogdbiobase = siocniobase;
4164 siogdbunit = siocnunit;
4165 gdbdev = makedev(CDEV_MAJOR, siocnunit);
4166 gdb_getc = siocngetc;
4167 gdb_putc = siocnputc;
4175 struct consdev siocons = {
4176 NULL, NULL, siocngetc, siocncheckc, siocnputc,
4180 extern struct consdev *cn_tab;
4183 siocnattach(port, speed)
4189 struct siocnstate sp;
4192 comdefaultrate = speed;
4197 * Initialize the divisor latch. We can't rely on
4198 * siocnopen() to do this the first time, since it
4199 * avoids writing to the latch if the latch appears
4200 * to have the correct value. Also, if we didn't
4201 * just read the speed from the hardware, then we
4202 * need to set the speed in hardware so that
4203 * switching it later is null.
4205 cfcr = inb(siocniobase + com_cfcr);
4206 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4207 outb(siocniobase + com_dlbl,
4208 COMBRD(comdefaultrate) & 0xff);
4209 outb(siocniobase + com_dlbh,
4210 (u_int) COMBRD(comdefaultrate) >> 8);
4211 outb(siocniobase + com_cfcr, cfcr);
4213 siocnopen(&sp, siocniobase, comdefaultrate);
4216 siocons.cn_dev = makedev(CDEV_MAJOR, 0);
4222 siogdbattach(port, speed)
4228 struct siocnstate sp;
4230 siogdbiobase = port;
4231 gdbdefaultrate = speed;
4236 * Initialize the divisor latch. We can't rely on
4237 * siocnopen() to do this the first time, since it
4238 * avoids writing to the latch if the latch appears
4239 * to have the correct value. Also, if we didn't
4240 * just read the speed from the hardware, then we
4241 * need to set the speed in hardware so that
4242 * switching it later is null.
4244 cfcr = inb(siogdbiobase + com_cfcr);
4245 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4246 outb(siogdbiobase + com_dlbl,
4247 COMBRD(gdbdefaultrate) & 0xff);
4248 outb(siogdbiobase + com_dlbh,
4249 (u_int) COMBRD(gdbdefaultrate) >> 8);
4250 outb(siogdbiobase + com_cfcr, cfcr);
4252 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4267 comconsole = DEV_TO_UNIT(cp->cn_dev);
4280 struct siocnstate sp;
4282 if (minor(dev) == siogdbunit)
4283 iobase = siogdbiobase;
4285 iobase = siocniobase;
4287 siocnopen(&sp, iobase, comdefaultrate);
4288 if (inb(iobase + com_lsr) & LSR_RXRDY)
4289 c = inb(iobase + com_data);
4292 siocnclose(&sp, iobase);
4305 struct siocnstate sp;
4307 if (minor(dev) == siogdbunit)
4308 iobase = siogdbiobase;
4310 iobase = siocniobase;
4312 siocnopen(&sp, iobase, comdefaultrate);
4313 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4315 c = inb(iobase + com_data);
4316 siocnclose(&sp, iobase);
4327 struct siocnstate sp;
4330 if (minor(dev) == siogdbunit)
4331 iobase = siogdbiobase;
4333 iobase = siocniobase;
4335 siocnopen(&sp, iobase, comdefaultrate);
4336 siocntxwait(iobase);
4337 outb(iobase + com_data, c);
4338 siocnclose(&sp, iobase);
4349 struct siocnstate sp;
4351 iobase = siogdbiobase;
4353 siocnopen(&sp, iobase, gdbdefaultrate);
4354 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4356 c = inb(iobase + com_data);
4357 siocnclose(&sp, iobase);
4367 struct siocnstate sp;
4370 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4371 siocntxwait(siogdbiobase);
4372 outb(siogdbiobase + com_data, c);
4373 siocnclose(&sp, siogdbiobase);
4380 * support PnP cards if we are using 'em
4385 static pnpid_t siopnp_ids[] = {
4386 { 0x5015f435, "MOT1550"},
4387 { 0x8113b04e, "Supra1381"},
4388 { 0x9012b04e, "Supra1290"},
4389 { 0x7121b04e, "SupraExpress 56i Sp"},
4390 { 0x11007256, "USR0011"},
4391 { 0x30207256, "USR2030"},
4392 { 0x31307256, "USR3031"},
4393 { 0x90307256, "USR3090"},
4394 { 0x0100440e, "Cardinal MVP288IV"},
4398 static char *siopnp_probe(u_long csn, u_long vend_id);
4399 static void siopnp_attach(u_long csn, u_long vend_id, char *name,
4400 struct isa_device *dev);
4401 static u_long nsiopnp = NSIO;
4403 static struct pnp_device siopnp = {
4410 DATA_SET (pnpdevice_set, siopnp);
4413 siopnp_probe(u_long csn, u_long vend_id)
4418 for(id = siopnp_ids; id->vend_id != 0; id++) {
4419 if (vend_id == id->vend_id) {
4427 read_pnp_parms(&d, 0);
4428 if (d.enable == 0 || d.flags & 1) {
4429 printf("CSN %lu is disabled.\n", csn);
4439 siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4443 if (dev->id_unit >= NSIOTOT)
4446 if (read_pnp_parms(&d, 0) == 0) {
4447 printf("failed to read pnp parms\n");
4451 write_pnp_parms(&d, 0);
4455 dev->id_iobase = d.port[0];
4456 dev->id_irq = (1 << d.irq[0]);
4457 dev->id_ointr = siointr;
4458 dev->id_ri_flags = RI_FAST;
4461 if (dev->id_driver == NULL) {
4462 dev->id_driver = &siodriver;
4463 dev->id_id = isa_compat_nextid();
4466 if ((dev->id_alive = sioprobe(dev)) != 0)
4469 printf("sio%d: probe failed\n", dev->id_unit);
4473 DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass, sio_cdevsw, 0, 0);
4477 * pc98 local function
4481 com_tiocm_set(struct com_s *com, int msr)
4485 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4488 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4489 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4490 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4491 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4492 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4493 pc98_i8251_clear_or_cmd( com, mask, tmp );
4498 com_tiocm_bis(struct com_s *com, int msr)
4504 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4505 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4506 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4507 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4509 pc98_i8251_or_cmd( com, tmp );
4514 com_tiocm_bic(struct com_s *com, int msr)
4520 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4521 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4522 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4524 pc98_i8251_clear_cmd( com, tmp );
4529 com_tiocm_get(struct com_s *com)
4531 return( com->pc98_prev_modem_status );
4535 com_tiocm_get_delta(struct com_s *com)
4539 tmp = com->pc98_modem_delta;
4540 com->pc98_modem_delta = 0;
4544 /* convert to TIOCM_?? ( ioctl.h ) */
4546 pc98_get_modem_status(struct com_s *com)
4551 stat = inb(com->sts_port);
4552 stat2 = inb(com->in_modem_port);
4553 msr = com->pc98_prev_modem_status
4554 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4555 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4556 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4557 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4558 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4559 #if COM_CARRIER_DETECT_EMULATE
4560 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4568 pc98_check_msr(void* chan)
4572 register struct tty *tp;
4580 unit = MINOR_TO_UNIT(mynor);
4581 com = com_addr(unit);
4585 msr = pc98_get_modem_status(com);
4586 /* make change flag */
4587 delta = msr ^ com->pc98_prev_modem_status;
4588 if ( delta & TIOCM_CAR ) {
4589 if ( com->modem_car_chg_timer ) {
4590 if ( -- com->modem_car_chg_timer )
4593 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4594 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4598 com->modem_car_chg_timer = 0;
4599 delta = ( msr ^ com->pc98_prev_modem_status ) &
4600 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4601 com->pc98_prev_modem_status = msr;
4602 delta = ( com->pc98_modem_delta |= delta );
4604 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4608 timeout(pc98_check_msr, (caddr_t)dev,
4609 PC98_CHECK_MODEM_INTERVAL);
4611 com->modem_checking = 0;
4616 pc98_msrint_start(dev_t dev)
4624 unit = MINOR_TO_UNIT(mynor);
4625 com = com_addr(unit);
4626 /* modem control line check routine envoke interval is 1/10 sec */
4627 if ( com->modem_checking == 0 ) {
4628 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4629 com->pc98_modem_delta = 0;
4630 timeout(pc98_check_msr, (caddr_t)dev,
4631 PC98_CHECK_MODEM_INTERVAL);
4632 com->modem_checking = 1;
4638 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4640 /* disable interrupt */
4643 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4645 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4646 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4651 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4656 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4657 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4662 pc98_check_i8251_interrupt(struct com_s *com)
4664 return ( com->intr_enable & 0x07 );
4668 pc98_i8251_clear_cmd(struct com_s *com, int x)
4673 tmp = com->pc98_prev_siocmd & ~(x);
4674 outb(com->cmd_port, tmp);
4675 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4680 pc98_i8251_or_cmd(struct com_s *com, int x)
4685 tmp = com->pc98_prev_siocmd | (x);
4686 outb(com->cmd_port, tmp);
4687 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4692 pc98_i8251_set_cmd(struct com_s *com, int x)
4698 outb(com->cmd_port, tmp);
4699 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4704 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4708 tmp = com->pc98_prev_siocmd & ~(clr);
4710 outb(com->cmd_port, tmp);
4711 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4716 pc98_i8251_get_cmd(struct com_s *com)
4718 return com->pc98_prev_siocmd;
4722 pc98_i8251_get_mod(struct com_s *com)
4724 return com->pc98_prev_siomod;
4728 pc98_i8251_reset(struct com_s *com, int mode, int command)
4730 outb(com->cmd_port, 0); /* dummy */
4732 outb(com->cmd_port, 0); /* dummy */
4734 outb(com->cmd_port, 0); /* dummy */
4736 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4738 outb(com->cmd_port, mode ); /* mode register */
4739 com->pc98_prev_siomod = mode;
4741 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4745 pc98_check_sysclock(void)
4747 /* get system clock from port */
4748 if ( pc98_machine_type & M_8M ) {
4749 /* 8 MHz system & H98 */
4758 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4763 count = pc98_ttspeedtab( com, speed );
4764 if ( count < 0 ) return;
4766 previnterrupt = pc98_check_i8251_interrupt(com);
4767 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4769 switch ( cflag&CSIZE ) {
4771 cfcr = MOD8251_5BITS; break;
4773 cfcr = MOD8251_6BITS; break;
4775 cfcr = MOD8251_7BITS; break;
4777 cfcr = MOD8251_8BITS; break;
4779 if ( cflag&PARENB ) {
4781 cfcr |= MOD8251_PODD;
4783 cfcr |= MOD8251_PEVEN;
4785 cfcr |= MOD8251_PDISAB;
4788 cfcr |= MOD8251_STOP2;
4790 cfcr |= MOD8251_STOP1;
4792 if ( count & 0x10000 )
4793 cfcr |= MOD8251_CLKX1;
4795 cfcr |= MOD8251_CLKX16;
4797 if (epson_machine_id != 0x20) { /* XXX */
4799 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4802 /* set baud rate from ospeed */
4803 pc98_set_baud_rate( com, count );
4805 if ( cfcr != pc98_i8251_get_mod(com) )
4806 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4808 pc98_enable_i8251_interrupt( com, previnterrupt );
4812 pc98_ttspeedtab(struct com_s *com, int speed)
4814 int if_type, effect_sp, count = -1, mod;
4816 if_type = com->pc98_if_type & 0x0f;
4818 switch (com->pc98_if_type) {
4819 case COM_IF_INTERNAL:
4820 if (PC98SIO_baud_rate_port(if_type) != -1) {
4821 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4823 count |= COM1_EXT_CLOCK;
4828 /* for *1CLK asynchronous! mode, TEFUTEFU */
4829 mod = (sysclock == 5) ? 2457600 : 1996800;
4830 effect_sp = ttspeedtab( speed, pc98speedtab );
4831 if ( effect_sp < 0 ) /* XXX */
4832 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4833 if ( effect_sp <= 0 )
4835 if ( effect_sp == speed )
4837 if ( mod % effect_sp )
4839 count = mod / effect_sp;
4840 if ( count > 65535 )
4842 if ( effect_sp != speed )
4845 case COM_IF_PC9861K_1:
4846 case COM_IF_PC9861K_2:
4849 case COM_IF_IND_SS_1:
4850 case COM_IF_IND_SS_2:
4851 case COM_IF_PIO9032B_1:
4852 case COM_IF_PIO9032B_2:
4853 if ( speed == 0 ) return 0;
4854 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4856 case COM_IF_B98_01_1:
4857 case COM_IF_B98_01_2:
4858 if ( speed == 0 ) return 0;
4859 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4861 if (count == 0 || count == 1) {
4863 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4873 pc98_set_baud_rate( struct com_s *com, int count )
4877 if_type = com->pc98_if_type & 0x0f;
4878 io = com->iobase & 0xff00;
4880 switch (com->pc98_if_type) {
4881 case COM_IF_INTERNAL:
4882 if (PC98SIO_baud_rate_port(if_type) != -1) {
4883 if (count & COM1_EXT_CLOCK) {
4884 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4887 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4892 printf( "[ Illegal count : %d ]", count );
4894 } else if ( count == 0 )
4903 outb( 0x75, count & 0xff );
4905 outb( 0x75, (count >> 8) & 0xff );
4908 case COM_IF_IND_SS_1:
4909 case COM_IF_IND_SS_2:
4910 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4911 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4912 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4913 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4914 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4916 case COM_IF_PIO9032B_1:
4917 case COM_IF_PIO9032B_2:
4918 outb(io | PC98SIO_baud_rate_port(if_type), count);
4920 case COM_IF_B98_01_1:
4921 case COM_IF_B98_01_2:
4922 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4925 * Some old B98_01 board should be controlled
4926 * in different way, but this hasn't been tested yet.
4928 outb(io | PC98SIO_func_port(if_type),
4929 (count & 0x20000) ? 0xf0 : 0xf2);
4935 pc98_check_if_type(device_t dev, struct siodev *iod)
4937 int irr, io, if_type, tmp;
4938 static short irq_tab[2][8] = {
4939 { 3, 5, 6, 9, 10, 12, 13, -1},
4940 { 3, 10, 12, 13, 5, 6, 9, -1}
4943 iod->if_type = if_type = (isa_get_flags(dev) >> 24) & 0xff;
4944 if ((if_type < 0 || if_type > COM_IF_END1) &&
4945 (if_type < 0x10 || if_type > COM_IF_END2))
4949 io = isa_get_port(dev) & 0xff00;
4951 if (IS_8251(iod->if_type)) {
4952 if (PC98SIO_func_port(if_type) != -1) {
4953 outb(io | PC98SIO_func_port(if_type), 0xf2);
4954 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4955 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4956 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4959 iod->cmd = io | PC98SIO_cmd_port(if_type);
4960 iod->sts = io | PC98SIO_sts_port(if_type);
4961 iod->mod = io | PC98SIO_in_modem_port(if_type);
4962 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4964 if (iod->if_type == COM_IF_INTERNAL) {
4967 /* XXX check new internal port. */
4970 for (tmp = 0; tmp < 100; tmp++) {
4971 if ((inb(0x13a) & 0x80) == 0) {
4972 PC98SIO_baud_rate_port(if_type) = 0x13a;
4973 if_8251_type[if_type].name = " (internal fast)";
4974 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4980 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4981 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4982 iod->irq = irq_tab[0][tmp];
4984 iod->irq = irq_tab[1][tmp];
4987 irr = if_16550a_type[if_type].irr_read;
4988 #ifdef COM_MULTIPORT
4989 if (!COM_ISMULTIPORT(isa_get_flags(dev)) ||
4990 device_get_unit(dev) == COM_MPMASTER(isa_get_flags(dev)))
4993 tmp = inb(io | irr);
4994 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4995 iod->irq = irq_tab[1][tmp >> 3];
4997 iod->irq = irq_tab[0][tmp & 0x07];
5000 if ( iod->irq == -1 ) return -1;
5005 pc98_set_ioport( struct com_s *com, int id_flags )
5009 if_type = (id_flags >> 24) & 0xff;
5010 if (IS_8251(if_type)) {
5011 pc98_check_sysclock();
5012 io = com->iobase & 0xff00;
5013 com->pc98_if_type = if_type;
5015 com->data_port = io | PC98SIO_data_port(if_type);
5016 com->cmd_port = io | PC98SIO_cmd_port(if_type);
5017 com->sts_port = io | PC98SIO_sts_port(if_type);
5018 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
5019 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5025 #endif /* PC98 defined */