2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
38 #include "opt_comconsole.h"
39 #include "opt_compat.h"
43 /* #include "pnp.h" */
47 * Serial driver, based on 386BSD-0.1 com driver.
48 * Mostly rewritten to use pseudo-DMA.
49 * Works for National Semiconductor NS8250-NS16550AF UARTs.
50 * COM driver, based on HP dca driver.
52 * Changes for PC-Card integration:
53 * - Added PC-Card driver table and handlers
55 /*===============================================================
56 * 386BSD(98),FreeBSD-1.1x(98) com driver.
58 * modified for PC9801 by M.Ishii
59 * Kyoto University Microcomputer Club (KMC)
60 * Chou "TEFUTEFU" Hirotomi
61 * Kyoto Univ. the faculty of medicine
62 *===============================================================
63 * FreeBSD-2.0.1(98) sio driver.
65 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
66 * T.Koike(hfc01340@niftyserve.or.jp)
67 * implement kernel device configuration
68 * aizu@orient.center.nitech.ac.jp
72 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
74 * This driver is under debugging,has bugs.
77 * options COM_MULTIPORT #if using MC16550II
78 * device sio0 at nec? port 0x30 tty irq 4 #internal
79 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
80 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
81 * # ~~~~~iobase ~~multi port flag
82 * # ~ master device is sio1
84 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
86 * 57600bps is too fast for sio0(internal8251)
88 * #set default speed 9600
91 * stty </dev/ttyid$i crtscts 9600
92 * : # ~~~~ default speed(can change after init.)
96 * 5) PC9861K,PIO9032B,B98_01
100 * modified for AIWA B98-01
101 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
103 * How to configure...
104 * # options COM_MULTIPORT # support for MICROCORE MC16550II
105 * ... comment-out this line, which will conflict with B98_01.
106 * options "B98_01" # support for AIWA B98-01
107 * device sio1 at nec? port 0x00d1 tty irq ?
108 * device sio2 at nec? port 0x00d5 tty irq ?
109 * ... you can leave these lines `irq ?', irq will be autodetected.
112 * Modified by Y.Takahashi of Kogakuin University.
116 #define COM_IF_INTERNAL 0x00
117 #define COM_IF_PC9861K_1 0x01
118 #define COM_IF_PC9861K_2 0x02
119 #define COM_IF_IND_SS_1 0x03
120 #define COM_IF_IND_SS_2 0x04
121 #define COM_IF_PIO9032B_1 0x05
122 #define COM_IF_PIO9032B_2 0x06
123 #define COM_IF_B98_01_1 0x07
124 #define COM_IF_B98_01_2 0x08
125 #define COM_IF_END1 COM_IF_B98_01_2
126 #define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
127 #define COM_IF_NS16550 0x11
128 #define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
129 #define COM_IF_MC16550II 0x13
130 #define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
131 #define COM_IF_RSB3000 0x15
132 #define COM_IF_RSB384 0x16
133 #define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
134 #define COM_IF_RSA98III 0x18
135 #define COM_IF_ESP98 0x19
136 #define COM_IF_END2 COM_IF_ESP98
139 #include <sys/param.h>
140 #include <sys/systm.h>
141 #include <sys/reboot.h>
142 #include <sys/malloc.h>
144 #include <sys/proc.h>
145 #include <sys/module.h>
146 #include <sys/conf.h>
147 #include <sys/dkstat.h>
148 #include <sys/fcntl.h>
149 #include <sys/interrupt.h>
150 #include <sys/kernel.h>
151 #include <sys/syslog.h>
152 #include <sys/sysctl.h>
154 #include <machine/bus.h>
155 #include <sys/rman.h>
156 #include <sys/timepps.h>
159 #include <pc98/pc98/pc98.h>
160 #include <pc98/pc98/pc98_machdep.h>
161 #include <i386/isa/ic/i8251.h>
163 #include <isa/isareg.h>
165 #include <isa/isavar.h>
166 #include <machine/lock.h>
168 #include <machine/clock.h>
169 #include <machine/ipl.h>
171 #include <machine/lock.h>
173 #include <machine/resource.h>
175 #include <isa/sioreg.h>
178 #include <i386/isa/ic/esp.h>
180 #include <i386/isa/ic/ns16550.h>
182 #include <i386/isa/ic/rsa.h>
189 #include <sys/module.h>
190 #include <pccard/cardinfo.h>
191 #include <pccard/slot.h>
195 #include <i386/isa/pnp.h>
201 #define disable_intr() 0
202 #define enable_intr() 0
206 #define disable_intr() COM_DISABLE_INTR()
207 #define enable_intr() COM_ENABLE_INTR()
212 #define EXTRA_SIO MAX_PNP_CARDS
218 #define NSIOTOT (NSIO + EXTRA_SIO)
220 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
222 #define CALLOUT_MASK 0x80
223 #define CONTROL_MASK 0x60
224 #define CONTROL_INIT_STATE 0x20
225 #define CONTROL_LOCK_STATE 0x40
226 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
227 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
228 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
231 /* checks in flags for multiport and which is multiport "master chip"
234 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
235 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
236 #define COM_NOTAST4(flags) ((flags) & 0x04)
237 #endif /* COM_MULTIPORT */
239 #define COM_CONSOLE(flags) ((flags) & 0x10)
240 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
241 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
242 #define COM_DEBUGGER(flags) ((flags) & 0x80)
243 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
244 #define COM_NOFIFO(flags) ((flags) & 0x02)
245 #define COM_ST16650A(flags) ((flags) & 0x20000)
246 #define COM_C_NOPROBE (0x40000)
247 #define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
248 #define COM_C_IIR_TXRDYBUG (0x80000)
249 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
250 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
253 #define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
255 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
260 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
261 * than the other bits so that they can be tested as a group without masking
264 * The following com and tty flags correspond closely:
265 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
267 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
268 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
269 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
270 * TS_FLUSH is not used.
271 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
272 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
274 #define CS_BUSY 0x80 /* output in progress */
275 #define CS_TTGO 0x40 /* output not stopped by XOFF */
276 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
277 #define CS_CHECKMSR 1 /* check of MSR scheduled */
278 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
279 #define CS_DTR_OFF 0x10 /* DTR held off */
280 #define CS_ODONE 4 /* output completed */
281 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
282 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
284 static char const * const error_desc[] = {
287 #define CE_INTERRUPT_BUF_OVERFLOW 1
288 "interrupt-level buffer overflow",
289 #define CE_TTY_BUF_OVERFLOW 2
290 "tty-level buffer overflow",
294 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
296 /* types. XXX - should be elsewhere */
297 typedef u_int Port_t; /* hardware port */
298 typedef u_char bool_t; /* boolean */
300 /* queue of linear buffers */
302 u_char *l_head; /* next char to process */
303 u_char *l_tail; /* one past the last char to process */
304 struct lbq *l_next; /* next in queue */
305 bool_t l_queued; /* nonzero if queued */
308 /* com device structure */
310 u_int flags; /* Copy isa device flags */
311 u_char state; /* miscellaneous flag bits */
312 bool_t active_out; /* nonzero if the callout device is open */
313 u_char cfcr_image; /* copy of value written to CFCR */
315 bool_t esp; /* is this unit a hayes esp board? */
317 u_char extra_state; /* more flag bits, separate for order trick */
318 u_char fifo_image; /* copy of value written to FIFO */
319 bool_t hasfifo; /* nonzero for 16550 UARTs */
320 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
321 bool_t loses_outints; /* nonzero if device loses output interrupts */
322 u_char mcr_image; /* copy of value written to MCR */
324 bool_t multiport; /* is this unit part of a multiport device? */
325 #endif /* COM_MULTIPORT */
326 bool_t no_irq; /* nonzero if irq is not attached */
327 bool_t gone; /* hardware disappeared */
328 bool_t poll; /* nonzero if polling is required */
329 bool_t poll_output; /* nonzero if polling for output is required */
330 int unit; /* unit number */
331 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
333 u_int wopeners; /* # processes waiting for DCD in open() */
336 * The high level of the driver never reads status registers directly
337 * because there would be too many side effects to handle conveniently.
338 * Instead, it reads copies of the registers stored here by the
341 u_char last_modem_status; /* last MSR read by intr handler */
342 u_char prev_modem_status; /* last MSR handled by high level */
344 u_char hotchar; /* ldisc-specific char to be handled ASAP */
345 u_char *ibuf; /* start of input buffer */
346 u_char *ibufend; /* end of input buffer */
347 u_char *ibufold; /* old input buffer, to be freed */
348 u_char *ihighwater; /* threshold in input buffer */
349 u_char *iptr; /* next free spot in input buffer */
350 int ibufsize; /* size of ibuf (not include error bytes) */
351 int ierroff; /* offset of error bytes in ibuf */
353 struct lbq obufq; /* head of queue of output buffers */
354 struct lbq obufs[2]; /* output buffers */
359 Port_t in_modem_port;
360 Port_t intr_ctrl_port;
362 int pc98_prev_modem_status;
363 int pc98_modem_delta;
364 int modem_car_chg_timer;
365 int pc98_prev_siocmd;
366 int pc98_prev_siomod;
370 Port_t data_port; /* i/o ports */
377 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
379 Port_t modem_ctl_port;
380 Port_t line_status_port;
381 Port_t modem_status_port;
382 Port_t intr_ctl_port; /* Ports of IIR register */
384 struct tty *tp; /* cross reference */
387 struct termios it_in; /* should be in struct tty */
388 struct termios it_out;
391 struct termios lt_in; /* should be in struct tty */
392 struct termios lt_out;
395 bool_t do_dcd_timestamp;
396 struct timeval timestamp;
397 struct timeval dcd_timestamp;
398 struct pps_state pps;
400 u_long bytes_in; /* statistics */
402 u_int delta_error_counts[CE_NTYPES];
403 u_long error_counts[CE_NTYPES];
406 * Data area for output buffers. Someday we should build the output
407 * buffer queue without copying data.
420 static int espattach __P((struct com_s *com, Port_t esp_port));
422 static int sioattach __P((device_t dev));
424 static timeout_t siobusycheck;
425 static timeout_t siodtrwakeup;
426 static void comhardclose __P((struct com_s *com));
427 static void sioinput __P((struct com_s *com));
428 static void siointr1 __P((struct com_s *com));
429 static void siointr __P((void *arg));
430 static int commctl __P((struct com_s *com, int bits, int how));
431 static int comparam __P((struct tty *tp, struct termios *t));
432 static swihand_t siopoll;
433 static int sioprobe __P((device_t dev));
434 static void siosettimeout __P((void));
435 static int siosetwater __P((struct com_s *com, speed_t speed));
436 static void comstart __P((struct tty *tp));
437 static timeout_t comwakeup;
438 static void disc_optim __P((struct tty *tp, struct termios *t,
442 static char driver_name[] = "sio";
444 /* table and macro for fast conversion from a unit number to its com struct */
445 static devclass_t sio_devclass;
446 #define com_addr(unit) ((struct com_s *) \
447 devclass_get_softc(sio_devclass, unit))
449 static device_method_t sio_methods[] = {
450 /* Device interface */
451 DEVMETHOD(device_probe, sioprobe),
452 DEVMETHOD(device_attach, sioattach),
457 static driver_t sio_driver = {
460 sizeof(struct com_s),
463 static d_open_t sioopen;
464 static d_close_t sioclose;
465 static d_read_t sioread;
466 static d_write_t siowrite;
467 static d_ioctl_t sioioctl;
468 static d_stop_t siostop;
469 static d_devtotty_t siodevtotty;
471 #define CDEV_MAJOR 28
472 static struct cdevsw sio_cdevsw = {
474 /* close */ sioclose,
476 /* write */ siowrite,
477 /* ioctl */ sioioctl,
480 /* devtotty */ siodevtotty,
483 /* strategy */ nostrategy,
484 /* name */ driver_name,
486 /* maj */ CDEV_MAJOR,
495 static volatile speed_t comdefaultrate = CONSPEED;
497 static volatile speed_t gdbdefaultrate = CONSPEED;
499 static u_int com_events; /* input chars + weighted output completions */
500 static Port_t siocniobase;
501 static int siocnunit;
502 static Port_t siogdbiobase;
503 static int siogdbunit = -1;
504 static bool_t sio_registered;
505 static int sio_timeout;
506 static int sio_timeouts_until_log;
507 static struct callout_handle sio_timeout_handle
508 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
510 static struct tty *sio_tty[NSIOTOT];
512 static struct tty sio_tty[NSIOTOT];
514 static const int nsio_tty = NSIOTOT;
520 Port_t cmd, sts, ctrl, mod;
524 #define COM_INT_DISABLE {int previpri; previpri=spltty();
525 #define COM_INT_ENABLE splx(previpri);}
526 #define IEN_TxFLAG IEN_Tx
528 #define COM_CARRIER_DETECT_EMULATE 0
529 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
530 #define DCD_OFF_TOLERANCE 2
531 #define DCD_ON_RECOGNITION 2
532 #define IS_8251(if_type) (!(if_type & 0x10))
533 #define COM1_EXT_CLOCK 0x40000
535 static void commint __P((dev_t dev));
536 static void com_tiocm_set __P((struct com_s *com, int msr));
537 static void com_tiocm_bis __P((struct com_s *com, int msr));
538 static void com_tiocm_bic __P((struct com_s *com, int msr));
539 static int com_tiocm_get __P((struct com_s *com));
540 static int com_tiocm_get_delta __P((struct com_s *com));
541 static void pc98_msrint_start __P((dev_t dev));
542 static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
543 static int pc98_ttspeedtab __P((struct com_s *com, int speed));
544 static int pc98_get_modem_status __P((struct com_s *com));
545 static timeout_t pc98_check_msr;
546 static void pc98_set_baud_rate __P((struct com_s *com, int count));
547 static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
548 static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
549 static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
550 static int pc98_check_i8251_interrupt __P((struct com_s *com));
551 static int pc98_i8251_get_cmd __P((struct com_s *com));
552 static int pc98_i8251_get_mod __P((struct com_s *com));
553 static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
554 static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
555 static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
556 static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
557 static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
558 static void pc98_check_sysclock __P((void));
559 static int pc98_set_ioport __P((struct com_s *com, int id_flags));
561 #define com_int_Tx_disable(com) \
562 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
563 #define com_int_Tx_enable(com) \
564 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
565 #define com_int_Rx_disable(com) \
566 pc98_disable_i8251_interrupt(com,IEN_Rx)
567 #define com_int_Rx_enable(com) \
568 pc98_enable_i8251_interrupt(com,IEN_Rx)
569 #define com_int_TxRx_disable(com) \
570 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
571 #define com_int_TxRx_enable(com) \
572 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
573 #define com_send_break_on(com) \
574 pc98_i8251_or_cmd(com,CMD8251_SBRK)
575 #define com_send_break_off(com) \
576 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
578 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
600 static struct speedtab pc98fast_speedtab[] = {
601 { 9600, 0x80 | COMBRD(9600), },
602 { 19200, 0x80 | COMBRD(19200), },
603 { 38400, 0x80 | COMBRD(38400), },
604 { 57600, 0x80 | COMBRD(57600), },
605 { 115200, 0x80 | COMBRD(115200), },
608 static struct speedtab comspeedtab_pio9032b[] = {
619 static struct speedtab comspeedtab_b98_01[] = {
634 static struct speedtab comspeedtab_mc16550[] = {
650 static struct speedtab comspeedtab_rsb384[] = {
671 static struct speedtab comspeedtab_rsa[] = {
673 { 50, COMBRD_RSA(50) },
674 { 75, COMBRD_RSA(75) },
675 { 110, COMBRD_RSA(110) },
676 { 134, COMBRD_RSA(134) },
677 { 150, COMBRD_RSA(150) },
678 { 200, COMBRD_RSA(200) },
679 { 300, COMBRD_RSA(300) },
680 { 600, COMBRD_RSA(600) },
681 { 1200, COMBRD_RSA(1200) },
682 { 1800, COMBRD_RSA(1800) },
683 { 2400, COMBRD_RSA(2400) },
684 { 4800, COMBRD_RSA(4800) },
685 { 9600, COMBRD_RSA(9600) },
686 { 19200, COMBRD_RSA(19200) },
687 { 38400, COMBRD_RSA(38400) },
688 { 57600, COMBRD_RSA(57600) },
689 { 115200, COMBRD_RSA(115200) },
690 { 230400, COMBRD_RSA(230400) },
691 { 460800, COMBRD_RSA(460800) },
692 { 921600, COMBRD_RSA(921600) },
697 static struct speedtab comspeedtab[] = {
701 { 110, COMBRD(110) },
702 { 134, COMBRD(134) },
703 { 150, COMBRD(150) },
704 { 200, COMBRD(200) },
705 { 300, COMBRD(300) },
706 { 600, COMBRD(600) },
707 { 1200, COMBRD(1200) },
708 { 1800, COMBRD(1800) },
709 { 2400, COMBRD(2400) },
710 { 4800, COMBRD(4800) },
711 { 9600, COMBRD(9600) },
712 { 19200, COMBRD(19200) },
713 { 38400, COMBRD(38400) },
714 { 57600, COMBRD(57600) },
715 { 115200, COMBRD(115200) },
724 struct speedtab *speedtab;
727 /* COM_IF_INTERNAL */
728 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
729 -1, pc98speedtab, 1 },
730 /* COM_IF_PC9861K_1 */
731 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
733 /* COM_IF_PC9861K_2 */
734 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
736 /* COM_IF_IND_SS_1 */
737 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
738 3, comspeedtab_mc16550, 1 },
739 /* COM_IF_IND_SS_2 */
740 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
741 3, comspeedtab_mc16550, 1 },
742 /* COM_IF_PIO9032B_1 */
743 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
744 7, comspeedtab_pio9032b, 1 },
745 /* COM_IF_PIO9032B_2 */
746 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
747 7, comspeedtab_pio9032b, 1 },
748 /* COM_IF_B98_01_1 */
749 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
750 7, comspeedtab_b98_01, 0 },
751 /* COM_IF_B98_01_2 */
752 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
753 7, comspeedtab_b98_01, 0 },
755 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
756 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
757 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
758 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
759 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
760 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
761 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
769 struct speedtab *speedtab;
770 } if_16550a_type[] = {
772 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
774 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
775 /* COM_IF_SECOND_CCU */
776 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
777 /* COM_IF_MC16550II */
778 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
780 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
782 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
784 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
785 /* COM_IF_MODEM_CARD */
786 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
787 /* COM_IF_RSA98III */
788 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
790 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
797 /* XXX configure this properly. */
798 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
799 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
801 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
802 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
803 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
804 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
808 /* XXX configure this properly. */
809 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
810 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
816 * handle sysctl read/write requests for console speed
818 * In addition to setting comdefaultrate for I/O through /dev/console,
819 * also set the initial and lock values for the /dev/ttyXX device
820 * if there is one associated with the console. Finally, if the /dev/tty
821 * device has already been open, change the speed on the open running port
826 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
833 newspeed = comdefaultrate;
835 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
836 if (error || !req->newptr)
839 comdefaultrate = newspeed;
841 if (comconsole < 0) /* serial console not selected? */
844 com = com_addr(comconsole);
849 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
850 * (note, the lock rates really are boolean -- if non-zero, disallow
853 com->it_in.c_ispeed = com->it_in.c_ospeed =
854 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
855 com->it_out.c_ispeed = com->it_out.c_ospeed =
856 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
859 * if we're open, change the running rate too
862 if (tp && (tp->t_state & TS_ISOPEN)) {
863 tp->t_termios.c_ispeed =
864 tp->t_termios.c_ospeed = comdefaultrate;
866 error = comparam(tp, &tp->t_termios);
872 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
873 0, 0, sysctl_machdep_comdefaultrate, "I", "");
877 * PC-Card (PCMCIA) specific code.
879 static int sioinit __P((struct pccard_devinfo *));
880 static void siounload __P((struct pccard_devinfo *));
881 static int card_intr __P((struct pccard_devinfo *));
883 PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
886 * Initialize the device - called from Slot manager.
889 sioinit(struct pccard_devinfo *devi)
892 /* validate unit number. */
893 if (devi->isahd.id_unit >= (NSIOTOT))
895 /* Make sure it isn't already probed. */
896 if (com_addr(devi->isahd.id_unit))
899 /* It's already probed as serial by Upper */
900 devi->isahd.id_flags |= COM_C_NOPROBE;
903 * Probe the device. If a value is returned, the
904 * device was found at the location.
906 if (sioprobe(&devi->isahd) == 0)
908 if (sioattach(&devi->isahd) == 0)
915 * siounload - unload the driver and clear the table.
917 * This is usually called when the card is ejected, but
918 * can be caused by a modunload of a controller driver.
919 * The idea is to reset the driver's view of the device
920 * and ensure that any driver entry points such as
921 * read and write do not hang.
924 siounload(struct pccard_devinfo *devi)
929 printf("NULL devi in siounload\n");
932 com = com_addr(devi->isahd.id_unit);
934 printf("NULL com in siounload\n");
938 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
941 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
943 printf("sio%d: unload\n", devi->isahd.id_unit);
949 if (com->ibuf != NULL)
950 free(com->ibuf, M_DEVBUF);
952 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
957 * card_intr - Shared interrupt called from
958 * front end of PC-Card handler.
961 card_intr(struct pccard_devinfo *devi)
966 com = com_addr(devi->isahd.id_unit);
967 if (com && !com->gone)
968 siointr1(com_addr(devi->isahd.id_unit));
972 #endif /* NCARD > 0 */
974 #define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit))
975 #define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit))
981 static bool_t already_init;
986 intrmask_t irqmap[4];
991 u_int flags = isa_get_flags(dev);
997 Port_t rsabase = NULL;
1000 if (!already_init) {
1002 * Turn off MCR_IENABLE for all likely serial ports. An unused
1003 * port with its MCR_IENABLE gate open will inhibit interrupts
1004 * from any used port that shares the interrupt vector.
1005 * XXX the gate enable is elsewhere for some multiports.
1010 devclass_get_devices(sio_devclass, &devs, &count);
1012 for (i = 0; i < count; i++) {
1014 tmp = (flags >> 24) & 0xff;
1016 outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
1018 if (tmp == COM_IF_RSA98III) {
1019 rsabase = isa_get_port(xdev) & 0xfff0;
1020 outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1022 outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1025 for (i = 0; i < count; i++) {
1027 outb(isa_get_port(xdev) + com_mcr, 0);
1031 already_init = TRUE;
1034 if (COM_LLCONSOLE(flags)) {
1035 printf("sio%d: reserved for low-level i/o\n",
1036 device_get_unit(dev));
1044 * If the port is i8251 UART (internal, B98_01)
1046 if (pc98_check_if_type(dev, &iod) == -1)
1049 isa_set_irq(dev, iod.irq);
1050 if (IS_8251(iod.if_type)) {
1057 outb(iod.cmd, CMD8251_RESET);
1058 DELAY(1000); /* for a while...*/
1059 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1061 outb(iod.cmd, 0x01); /* CMD (dummy) */
1062 DELAY(1000); /* for a while...*/
1063 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1066 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1068 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1069 outb( iod.ctrl, tmp|IEN_TxEMP );
1071 result = isa_irq_pending() ? 0 : ENXIO;
1072 outb( iod.ctrl, tmp );
1076 * B98_01 doesn't activate TxEMP interrupt line
1077 * when being reset, so we can't check irq pending.
1081 if (epson_machine_id==0x20) { /* XXX */
1084 isa_set_portsize(dev, 4);
1089 * If the device is on a multiport card and has an AST/4
1090 * compatible interrupt control register, initialize this
1091 * register and prepare to leave MCR_IENABLE clear in the mcr.
1092 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1093 * Point idev to the device struct giving the correct id_irq.
1094 * This is the struct for the master device if there is one.
1097 mcr_image = MCR_IENABLE;
1099 if (iod.if_type == COM_IF_RSA98III) {
1101 rsabase = isa_get_port(idev) & 0xfff0;
1102 if (rsabase != isa_get_port(idev))
1104 outb(rsabase + rsa_msr, 0x04);
1105 outb(rsabase + rsa_frr, 0x00);
1106 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1108 outb(rsabase + rsa_ier, 0x00);
1109 outb(rsabase + rsa_frr, 0x00);
1110 outb(rsabase + rsa_tivsr, 0x00);
1111 outb(rsabase + rsa_tcr, 0x00);
1114 #ifdef COM_MULTIPORT
1115 if (COM_ISMULTIPORT(flags)) {
1116 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1118 printf("sio%d: master device %d not configured\n",
1119 device_get_unit(dev), COM_MPMASTER(flags));
1120 isa_set_irq(dev, 0);
1124 if (!COM_NOTAST4(flags)) {
1125 outb(isa_get_port(idev) + com_scr,
1126 isa_get_irq(idev) >= 0 ? 0x80 : 0);
1131 #endif /* COM_MULTIPORT */
1132 if (isa_get_irq(idev) < 0)
1136 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1139 switch (isa_get_irq(idev)) {
1140 case 3: irqout = 4; break;
1141 case 5: irqout = 5; break;
1142 case 6: irqout = 6; break;
1143 case 12: irqout = 7; break;
1145 printf("sio%d: irq configuration error\n",
1146 device_get_unit(dev));
1149 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
1151 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1153 bzero(failures, sizeof failures);
1154 iobase = isa_get_port(dev);
1156 if (iod.if_type == COM_IF_RSA98III)
1161 * We don't want to get actual interrupts, just masked ones.
1162 * Interrupts from this line should already be masked in the ICU,
1163 * but mask them in the processor as well in case there are some
1164 * (misconfigured) shared interrupts.
1170 * Initialize the speed and the word size and wait long enough to
1171 * drain the maximum of 16 bytes of junk in device output queues.
1172 * The speed is undefined after a master reset and must be set
1173 * before relying on anything related to output. There may be
1174 * junk after a (very fast) soft reboot and (apparently) after
1176 * XXX what about the UART bug avoided by waiting in comparam()?
1177 * We don't want to to wait long enough to drain at 2 bps.
1179 if (iobase == siocniobase)
1180 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1183 tmp = ttspeedtab(SIO_TEST_SPEED,
1184 if_16550a_type[iod.if_type & 0x0f].speedtab);
1185 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1186 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1187 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1188 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1190 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1191 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1192 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1193 outb(iobase + com_cfcr, CFCR_8BITS);
1195 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1199 * Enable the interrupt gate and disable device interupts. This
1200 * should leave the device driving the interrupt line low and
1201 * guarantee an edge trigger if an interrupt can be generated.
1205 outb(iobase + (com_mcr << port_shift), mcr_image);
1206 outb(iobase + (com_ier << port_shift), 0);
1208 outb(iobase + com_mcr, mcr_image);
1209 outb(iobase + com_ier, 0);
1211 DELAY(1000); /* XXX */
1212 irqmap[0] = isa_irq_pending();
1215 * Attempt to set loopback mode so that we can send a null byte
1216 * without annoying any external device.
1220 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1222 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1226 * Attempt to generate an output interrupt. On 8250's, setting
1227 * IER_ETXRDY generates an interrupt independent of the current
1228 * setting and independent of whether the THR is empty. On 16450's,
1229 * setting IER_ETXRDY generates an interrupt independent of the
1230 * current setting. On 16550A's, setting IER_ETXRDY only
1231 * generates an interrupt when IER_ETXRDY is not already set.
1234 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1235 if (iod.if_type == COM_IF_RSA98III)
1236 outb(rsabase + rsa_ier, 0x04);
1238 outb(iobase + com_ier, IER_ETXRDY);
1242 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1243 * an interrupt. They'd better generate one for actually doing
1244 * output. Loopback may be broken on the same incompatibles but
1245 * it's unlikely to do more than allow the null byte out.
1248 outb(iobase + (com_data << port_shift), 0);
1250 outb(iobase + com_data, 0);
1252 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1255 * Turn off loopback mode so that the interrupt gate works again
1256 * (MCR_IENABLE was hidden). This should leave the device driving
1257 * an interrupt line high. It doesn't matter if the interrupt
1258 * line oscillates while we are not looking at it, since interrupts
1263 outb(iobase + (com_mcr << port_shift), mcr_image);
1265 outb(iobase + com_mcr, mcr_image);
1269 * It's a definitly Serial PCMCIA(16550A), but still be required
1270 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1272 if ( COM_NOPROBE(flags) ) {
1273 /* Reading IIR register twice */
1274 for ( fn = 0; fn < 2; fn ++ ) {
1277 failures[6] = inb(iobase + (com_iir << port_shift));
1279 failures[6] = inb(iobase + com_iir);
1282 /* Check IIR_TXRDY clear ? */
1284 isa_set_portsize(dev,
1285 if_16550a_type[iod.if_type & 0x0f].io_size);
1287 isa_set_portsize(dev, IO_COMSIZE);
1290 if ( failures[6] & IIR_TXRDY ) {
1291 /* Nop, Double check with clearing IER */
1293 outb(iobase + (com_ier << port_shift), 0);
1295 (com_iir << port_shift)) & IIR_NOPEND) {
1297 outb(iobase + com_ier, 0);
1298 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1300 /* Ok. we're familia this gang */
1301 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
1303 /* Unknow, Just omit this chip.. XXX*/
1307 /* OK. this is well-known guys */
1308 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
1311 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1313 outb(iobase + com_cfcr, CFCR_8BITS);
1316 return (iobase == siocniobase ? 0 : result);
1321 * o the CFCR, IER and MCR in UART hold the values written to them
1322 * (the values happen to be all distinct - this is good for
1323 * avoiding false positive tests from bus echoes).
1324 * o an output interrupt is generated and its vector is correct.
1325 * o the interrupt goes away when the IIR in the UART is read.
1329 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1330 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1331 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1333 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1334 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1335 failures[2] = inb(iobase + com_mcr) - mcr_image;
1337 DELAY(10000); /* Some internal modems need this time */
1338 irqmap[1] = isa_irq_pending();
1340 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1342 if (iod.if_type == COM_IF_RSA98III)
1343 inb(rsabase + rsa_srr);
1345 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1347 DELAY(1000); /* XXX */
1348 irqmap[2] = isa_irq_pending();
1350 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1352 if (iod.if_type == COM_IF_RSA98III)
1353 inb(rsabase + rsa_srr);
1355 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1359 * Turn off all device interrupts and check that they go off properly.
1360 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1361 * the OUT2 output of the UART to
1362 * the ICU input. Closing the gate would give a floating ICU input
1363 * (unless there is another device driving it) and spurious interrupts.
1364 * (On the system that this was first tested on, the input floats high
1365 * and gives a (masked) interrupt as soon as the gate is closed.)
1368 outb(iobase + (com_ier << port_shift), 0);
1369 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1370 failures[7] = inb(iobase + (com_ier << port_shift));
1371 if (iod.if_type == COM_IF_RSA98III)
1372 outb(rsabase + rsa_ier, 0x00);
1374 outb(iobase + com_ier, 0);
1375 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1376 failures[7] = inb(iobase + com_ier);
1378 DELAY(1000); /* XXX */
1379 irqmap[3] = isa_irq_pending();
1381 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1383 if (iod.if_type == COM_IF_RSA98III) {
1384 inb(rsabase + rsa_srr);
1385 outb(rsabase + rsa_frr, 0x00);
1388 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1393 irqs = irqmap[1] & ~irqmap[0];
1394 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
1396 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1397 device_get_unit(dev), isa_get_irq(idev), irqs);
1399 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1400 device_get_unit(dev),
1401 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1404 isa_set_portsize(dev, if_16550a_type[iod.if_type & 0x0f].io_size);
1406 isa_set_portsize(dev, IO_COMSIZE);
1409 for (fn = 0; fn < sizeof failures; ++fn)
1412 outb(iobase + (com_mcr << port_shift), 0);
1414 outb(iobase + com_mcr, 0);
1418 printf("sio%d: probe failed test(s):",
1419 device_get_unit(dev));
1420 for (fn = 0; fn < sizeof failures; ++fn)
1427 return (iobase == siocniobase ? 0 : result);
1432 espattach(com, esp_port)
1440 * Check the ESP-specific I/O port to see if we're an ESP
1441 * card. If not, return failure immediately.
1443 if ((inb(esp_port) & 0xf3) == 0) {
1444 printf(" port 0x%x is not an ESP board?\n", esp_port);
1449 * We've got something that claims to be a Hayes ESP card.
1453 /* Get the dip-switch configuration */
1455 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1456 dips = inb(esp_port + ESP98_STATUS1);
1458 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1459 dips = inb(esp_port + ESP_STATUS1);
1463 * Bits 0,1 of dips say which COM port we are.
1466 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1468 if (com->iobase == likely_com_ports[dips & 0x03])
1472 printf(" esp_port has com %d\n", dips & 0x03);
1477 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1480 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1481 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1482 val = inb(esp_port + ESP98_STATUS2);
1484 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1485 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1486 val = inb(esp_port + ESP_STATUS2);
1488 if ((val & 0x70) < 0x20) {
1489 printf("-old (%o)", val & 0x70);
1494 * Check for ability to emulate 16550: bit 7 == 1
1496 if ((dips & 0x80) == 0) {
1502 * Okay, we seem to be a Hayes ESP card. Whee.
1505 com->esp_port = esp_port;
1508 #endif /* COM_ESP */
1521 struct resource *res;
1523 u_int flags = isa_get_flags(dev);
1530 iobase = isa_get_port(dev);
1532 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1535 unit = device_get_unit(dev);
1536 com = device_get_softc(dev);
1539 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1541 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL)
1543 bzero(obuf, obufsize * 2);
1547 * sioprobe() has initialized the device registers as follows:
1548 * o cfcr = CFCR_8BITS.
1549 * It is most important that CFCR_DLAB is off, so that the
1550 * data port is not hidden when we enable interrupts.
1552 * Interrupts are only enabled when the line is open.
1553 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1554 * interrupt control register or the config specifies no irq.
1555 * Keeping MCR_DTR and MCR_RTS off might stop the external
1556 * device from sending before we are ready.
1558 bzero(com, sizeof *com);
1560 com->obufsize = obufsize;
1562 com->obuf2 = obuf + obufsize;
1565 com->cfcr_image = CFCR_8BITS;
1566 com->dtr_wait = 3 * hz;
1567 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1568 com->no_irq = isa_get_irq(dev) < 0;
1569 com->tx_fifo_size = 1;
1570 com->obufs[0].l_head = com->obuf1;
1571 com->obufs[1].l_head = com->obuf2;
1573 com->iobase = iobase;
1575 if (pc98_set_ioport(com, isa_get_flags(dev)) == -1) {
1576 com->pc98_if_type = (isa_get_flags(dev) >> 24) & 0xff;
1577 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1578 com->data_port = iobase + (com_data << port_shift);
1579 com->int_id_port = iobase + (com_iir << port_shift);
1580 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1581 com->mcr_image = inb(com->modem_ctl_port);
1582 com->line_status_port = iobase + (com_lsr << port_shift);
1583 com->modem_status_port = iobase + (com_msr << port_shift);
1584 com->intr_ctl_port = iobase + (com_ier << port_shift);
1586 #else /* not PC98 */
1587 com->data_port = iobase + com_data;
1588 com->int_id_port = iobase + com_iir;
1589 com->modem_ctl_port = iobase + com_mcr;
1590 com->mcr_image = inb(com->modem_ctl_port);
1591 com->line_status_port = iobase + com_lsr;
1592 com->modem_status_port = iobase + com_msr;
1593 com->intr_ctl_port = iobase + com_ier;
1597 * We don't use all the flags from <sys/ttydefaults.h> since they
1598 * are only relevant for logins. It's important to have echo off
1599 * initially so that the line doesn't start blathering before the
1600 * echo flag can be turned off.
1602 com->it_in.c_iflag = 0;
1603 com->it_in.c_oflag = 0;
1604 com->it_in.c_cflag = TTYDEF_CFLAG;
1605 com->it_in.c_lflag = 0;
1606 if (unit == comconsole) {
1608 if (IS_8251(com->pc98_if_type))
1611 com->it_in.c_iflag = TTYDEF_IFLAG;
1612 com->it_in.c_oflag = TTYDEF_OFLAG;
1613 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1614 com->it_in.c_lflag = TTYDEF_LFLAG;
1615 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1616 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1617 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1618 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1620 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1621 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1623 free(com, M_DEVBUF);
1627 termioschars(&com->it_in);
1628 com->it_out = com->it_in;
1630 /* attempt to determine UART type */
1631 printf("sio%d: type", unit);
1635 #ifdef COM_MULTIPORT
1636 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1638 if (!COM_IIR_TXRDYBUG(flags))
1645 scr = inb(iobase + com_scr);
1646 outb(iobase + com_scr, 0xa5);
1647 scr1 = inb(iobase + com_scr);
1648 outb(iobase + com_scr, 0x5a);
1649 scr2 = inb(iobase + com_scr);
1650 outb(iobase + com_scr, scr);
1651 if (scr1 != 0xa5 || scr2 != 0x5a) {
1653 goto determined_type;
1658 if (IS_8251(com->pc98_if_type)) {
1659 com_int_TxRx_disable( com );
1660 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1661 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1662 com_send_break_off( com );
1663 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1665 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1667 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1671 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1682 if (COM_NOFIFO(flags)) {
1683 printf(" 16550A fifo disabled");
1685 com->hasfifo = TRUE;
1687 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1690 if (COM_ST16650A(flags)) {
1692 com->tx_fifo_size = 32;
1693 printf(" ST16650A");
1695 com->tx_fifo_size = COM_FIFOSIZE(flags);
1701 if (com->pc98_if_type == COM_IF_RSA98III) {
1702 com->tx_fifo_size = 2048;
1703 com->rsabase = isa_get_port(dev);
1704 outb(com->rsabase + rsa_ier, 0x00);
1705 outb(com->rsabase + rsa_frr, 0x00);
1711 if (com->pc98_if_type == COM_IF_ESP98)
1713 for (espp = likely_esp_ports; *espp != 0; espp++)
1714 if (espattach(com, *espp)) {
1715 com->tx_fifo_size = 1024;
1719 if (!com->st16650a) {
1720 if (!com->tx_fifo_size)
1721 com->tx_fifo_size = 16;
1723 printf(" lookalike with %d bytes FIFO",
1731 if (com->pc98_if_type == COM_IF_RSB3000) {
1732 /* Set RSB-2000/3000 Extended Buffer mode. */
1734 lcr = inb(iobase + (com_cfcr << port_shift));
1735 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1736 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1737 outb(iobase + (com_cfcr << port_shift), lcr);
1744 * Set 16550 compatibility mode.
1745 * We don't use the ESP_MODE_SCALE bit to increase the
1746 * fifo trigger levels because we can't handle large
1748 * XXX flow control should be set in comparam(), not here.
1751 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1752 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1754 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1755 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1758 /* Set RTS/CTS flow control. */
1760 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1761 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1762 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1764 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1765 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1766 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1769 /* Set flow-control levels. */
1771 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1772 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1773 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1774 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1775 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1777 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1778 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1779 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1780 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1781 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1785 /* Set UART clock prescaler. */
1786 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1787 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1790 #endif /* COM_ESP */
1792 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1793 outb(iobase + (com_fifo << port_shift), 0);
1795 outb(iobase + com_fifo, 0);
1799 #ifdef COM_MULTIPORT
1800 if (COM_ISMULTIPORT(flags)) {
1801 com->multiport = TRUE;
1802 printf(" (multiport");
1803 if (unit == COM_MPMASTER(flags))
1807 isa_get_irq(devclass_get_device
1808 (sio_devclass, COM_MPMASTER(flags))) < 0;
1810 #endif /* COM_MULTIPORT */
1814 if (unit == comconsole)
1815 printf(", console");
1816 if ( COM_IIR_TXRDYBUG(flags) )
1817 printf(" with a bogus IIR_TXRDY register");
1820 if (!sio_registered) {
1821 register_swi(SWI_TTY, siopoll);
1822 sio_registered = TRUE;
1824 make_dev(&sio_cdevsw, unit,
1825 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1826 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
1827 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1828 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
1829 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1830 make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
1831 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1832 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE,
1833 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1834 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
1835 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1836 com->flags = isa_get_flags(dev); /* Heritate id_flags for later */
1837 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1838 pps_init(&com->pps);
1840 res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1,
1841 RF_SHAREABLE | RF_ACTIVE);
1842 BUS_SETUP_INTR(device_get_parent(dev), dev, res,
1843 INTR_TYPE_TTY | INTR_TYPE_FAST,
1850 sioopen(dev, flag, mode, p)
1868 unit = MINOR_TO_UNIT(mynor);
1869 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1873 if (mynor & CONTROL_MASK)
1876 tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]);
1878 tp = com->tp = &sio_tty[unit];
1883 if (!IS_8251(com->pc98_if_type))
1884 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1887 * We jump to this label after all non-interrupted sleeps to pick
1888 * up any changes of the device state.
1891 while (com->state & CS_DTR_OFF) {
1892 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1893 if (com_addr(unit) == NULL)
1895 if (error != 0 || com->gone)
1898 if (tp->t_state & TS_ISOPEN) {
1900 * The device is open, so everything has been initialized.
1903 if (mynor & CALLOUT_MASK) {
1904 if (!com->active_out) {
1909 if (com->active_out) {
1910 if (flag & O_NONBLOCK) {
1914 error = tsleep(&com->active_out,
1915 TTIPRI | PCATCH, "siobi", 0);
1916 if (com_addr(unit) == NULL)
1918 if (error != 0 || com->gone)
1923 if (tp->t_state & TS_XCLUDE &&
1930 * The device isn't open, so there are no conflicts.
1931 * Initialize it. Initialization is done twice in many
1932 * cases: to preempt sleeping callin opens if we are
1933 * callout, and to complete a callin open after DCD rises.
1935 tp->t_oproc = comstart;
1936 tp->t_param = comparam;
1938 tp->t_termios = mynor & CALLOUT_MASK
1939 ? com->it_out : com->it_in;
1941 if (!IS_8251(com->pc98_if_type))
1943 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1944 com->poll = com->no_irq;
1945 com->poll_output = com->loses_outints;
1947 error = comparam(tp, &tp->t_termios);
1952 if (IS_8251(com->pc98_if_type)) {
1953 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1954 pc98_msrint_start(dev);
1958 * XXX we should goto open_top if comparam() slept.
1960 iobase = com->iobase;
1963 * (Re)enable and drain fifos.
1965 * Certain SMC chips cause problems if the fifos
1966 * are enabled while input is ready. Turn off the
1967 * fifo if necessary to clear the input. We test
1968 * the input ready bit after enabling the fifos
1969 * since we've already enabled them in comparam()
1970 * and to handle races between enabling and fresh
1975 outb(iobase + (com_fifo << port_shift),
1976 FIFO_RCV_RST | FIFO_XMT_RST
1978 if (com->pc98_if_type == COM_IF_RSA98III)
1979 outb(com->rsabase + rsa_frr , 0x00);
1981 outb(iobase + com_fifo,
1982 FIFO_RCV_RST | FIFO_XMT_RST
1986 * XXX the delays are for superstitious
1987 * historical reasons. It must be less than
1988 * the character time at the maximum
1989 * supported speed (87 usec at 115200 bps
1990 * 8N1). Otherwise we might loop endlessly
1991 * if data is streaming in. We used to use
1992 * delays of 100. That usually worked
1993 * because DELAY(100) used to usually delay
1994 * for about 85 usec instead of 100.
1998 if (!(inb(com->line_status_port) & LSR_RXRDY))
2000 if (com->pc98_if_type == COM_IF_RSA98III
2001 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2002 : !(inb(com->line_status_port) & LSR_RXRDY))
2006 outb(iobase + (com_fifo << port_shift), 0);
2008 outb(iobase + com_fifo, 0);
2011 (void) inb(com->data_port);
2017 if (IS_8251(com->pc98_if_type)) {
2018 com_tiocm_bis(com, TIOCM_LE);
2019 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2020 com_int_Rx_enable(com);
2023 (void) inb(com->line_status_port);
2024 (void) inb(com->data_port);
2025 com->prev_modem_status = com->last_modem_status
2026 = inb(com->modem_status_port);
2027 if (COM_IIR_TXRDYBUG(com->flags)) {
2028 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2031 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2032 | IER_ERLS | IER_EMSC);
2035 if (com->pc98_if_type == COM_IF_RSA98III) {
2036 outb(com->rsabase + rsa_ier, 0x1d);
2037 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2045 * Handle initial DCD. Callout devices get a fake initial
2046 * DCD (trapdoor DCD). If we are callout, then any sleeping
2047 * callin opens get woken up and resume sleeping on "siobi"
2048 * instead of "siodcd".
2051 * XXX `mynor & CALLOUT_MASK' should be
2052 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2053 * TRAPDOOR_CARRIER is the default initial state for callout
2054 * devices and SOFT_CARRIER is like CLOCAL except it hides
2058 if ((IS_8251(com->pc98_if_type) &&
2059 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2060 (!IS_8251(com->pc98_if_type) &&
2061 (com->prev_modem_status & MSR_DCD)) ||
2062 mynor & CALLOUT_MASK)
2064 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2066 (*linesw[tp->t_line].l_modem)(tp, 1);
2069 * Wait for DCD if necessary.
2071 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2072 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2074 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2075 if (com_addr(unit) == NULL)
2078 if (error != 0 || com->gone)
2082 error = (*linesw[tp->t_line].l_open)(dev, tp);
2083 disc_optim(tp, &tp->t_termios, com);
2084 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2085 com->active_out = TRUE;
2089 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2095 sioclose(dev, flag, mode, p)
2107 if (mynor & CONTROL_MASK)
2109 com = com_addr(MINOR_TO_UNIT(mynor));
2112 (*linesw[tp->t_line].l_close)(tp, flag);
2114 com->modem_checking = 0;
2116 disc_optim(tp, &tp->t_termios, com);
2117 siostop(tp, FREAD | FWRITE);
2123 printf("sio%d: gone\n", com->unit);
2125 if (com->ibuf != NULL)
2126 free(com->ibuf, M_DEVBUF);
2127 bzero(tp, sizeof *tp);
2128 free(com, M_DEVBUF);
2147 iobase = com->iobase;
2150 com->poll_output = FALSE;
2151 com->do_timestamp = FALSE;
2152 com->do_dcd_timestamp = FALSE;
2153 com->pps.ppsparam.mode = 0;
2155 if (IS_8251(com->pc98_if_type))
2156 com_send_break_off(com);
2158 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2159 outb(iobase + (com_cfcr << port_shift),
2160 com->cfcr_image &= ~CFCR_SBREAK);
2163 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2168 if (IS_8251(com->pc98_if_type))
2169 com_int_TxRx_disable(com);
2171 outb(iobase + (com_ier << port_shift), 0);
2172 if (com->pc98_if_type == COM_IF_RSA98III) {
2173 outb(com->rsabase + rsa_ier, 0x00);
2176 outb(iobase + com_ier, 0);
2180 if (IS_8251(com->pc98_if_type))
2181 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2183 tmp = com->prev_modem_status & MSR_DCD;
2185 if (tp->t_cflag & HUPCL
2187 * XXX we will miss any carrier drop between here and the
2188 * next open. Perhaps we should watch DCD even when the
2189 * port is closed; it is not sufficient to check it at
2190 * the next open because it might go up and down while
2191 * we're not watching.
2193 || (!com->active_out
2197 && !(com->prev_modem_status & MSR_DCD)
2199 && !(com->it_in.c_cflag & CLOCAL))
2200 || !(tp->t_state & TS_ISOPEN)) {
2202 if (IS_8251(com->pc98_if_type))
2203 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2206 (void)commctl(com, TIOCM_DTR, DMBIC);
2207 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2208 timeout(siodtrwakeup, com, com->dtr_wait);
2209 com->state |= CS_DTR_OFF;
2214 if (IS_8251(com->pc98_if_type))
2215 com_tiocm_bic(com, TIOCM_LE );
2221 * Disable fifos so that they are off after controlled
2222 * reboots. Some BIOSes fail to detect 16550s when the
2223 * fifos are enabled.
2226 outb(iobase + (com_fifo << port_shift), 0);
2228 outb(iobase + com_fifo, 0);
2231 com->active_out = FALSE;
2232 wakeup(&com->active_out);
2233 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2238 sioread(dev, uio, flag)
2247 if (mynor & CONTROL_MASK)
2249 com = com_addr(MINOR_TO_UNIT(mynor));
2252 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
2256 siowrite(dev, uio, flag)
2266 if (mynor & CONTROL_MASK)
2269 unit = MINOR_TO_UNIT(mynor);
2270 com = com_addr(unit);
2274 * (XXX) We disallow virtual consoles if the physical console is
2275 * a serial port. This is in case there is a display attached that
2276 * is not the console. In that situation we don't need/want the X
2277 * server taking over the console.
2279 if (constty != NULL && unit == comconsole)
2281 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
2291 com = (struct com_s *)chan;
2294 * Clear TS_BUSY if low-level output is complete.
2295 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2296 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2297 * called again. Reading the line status port outside of siointr1()
2298 * is safe because CS_BUSY is clear so there are no output interrupts
2302 if (com->state & CS_BUSY)
2303 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2305 else if ((IS_8251(com->pc98_if_type) &&
2306 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2307 == (STS8251_TxRDY | STS8251_TxEMP)) ||
2308 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2309 == (LSR_TSRE | LSR_TXRDY)) {
2311 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2312 == (LSR_TSRE | LSR_TXRDY)) {
2314 com->tp->t_state &= ~TS_BUSY;
2316 com->extra_state &= ~CSE_BUSYCHECK;
2318 timeout(siobusycheck, com, hz / 100);
2328 com = (struct com_s *)chan;
2329 com->state &= ~CS_DTR_OFF;
2330 wakeup(&com->dtr_wait);
2348 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2349 com_events -= (com->iptr - com->ibuf);
2350 com->iptr = com->ibuf;
2353 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2355 * Avoid the grotesquely inefficient lineswitch routine
2356 * (ttyinput) in "raw" mode. It usually takes about 450
2357 * instructions (that's without canonical processing or echo!).
2358 * slinput is reasonably fast (usually 40 instructions plus
2363 incc = com->iptr - buf;
2364 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2365 && (com->state & CS_RTS_IFLOW
2366 || tp->t_iflag & IXOFF)
2367 && !(tp->t_state & TS_TBLOCK))
2369 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2370 += b_to_q((char *)buf, incc, &tp->t_rawq);
2374 tp->t_rawcc += incc;
2376 if (tp->t_state & TS_TTSTOP
2377 && (tp->t_iflag & IXANY
2378 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2379 tp->t_state &= ~TS_TTSTOP;
2380 tp->t_lflag &= ~FLUSHO;
2384 } while (buf < com->iptr);
2388 line_status = buf[com->ierroff];
2391 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2392 if (line_status & LSR_BI)
2393 recv_data |= TTY_BI;
2394 if (line_status & LSR_FE)
2395 recv_data |= TTY_FE;
2396 if (line_status & LSR_OE)
2397 recv_data |= TTY_OE;
2398 if (line_status & LSR_PE)
2399 recv_data |= TTY_PE;
2401 (*linesw[tp->t_line].l_rint)(recv_data, tp);
2403 } while (buf < com->iptr);
2405 com_events -= (com->iptr - com->ibuf);
2406 com->iptr = com->ibuf;
2409 * There is now room for another low-level buffer full of input,
2410 * so enable RTS if it is now disabled and there is room in the
2411 * high-level buffer.
2414 if (IS_8251(com->pc98_if_type))
2415 tmp = com_tiocm_get(com) & TIOCM_RTS;
2417 tmp = com->mcr_image & MCR_RTS;
2418 if ((com->state & CS_RTS_IFLOW) && !(tmp) &&
2419 !(tp->t_state & TS_TBLOCK))
2420 if (IS_8251(com->pc98_if_type))
2421 com_tiocm_bis(com, TIOCM_RTS);
2423 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2425 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2426 !(tp->t_state & TS_TBLOCK))
2427 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2435 #ifndef COM_MULTIPORT
2437 siointr1((struct com_s *) arg);
2439 #else /* COM_MULTIPORT */
2440 bool_t possibly_more_intrs;
2444 u_char rsa_buf_status;
2448 * Loop until there is no activity on any port. This is necessary
2449 * to get an interrupt edge more than to avoid another interrupt.
2450 * If the IRQ signal is just an OR of the IRQ signals from several
2451 * devices, then the edge from one may be lost because another is
2456 possibly_more_intrs = FALSE;
2457 for (unit = 0; unit < NSIOTOT; ++unit) {
2458 com = com_addr(unit);
2461 * would it work here, or be counter-productive?
2466 && IS_8251(com->pc98_if_type)){
2473 && com->pc98_if_type == COM_IF_RSA98III) {
2474 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2475 if ((rsa_buf_status & 0xc8)
2476 || !(rsa_buf_status & 0x01)) {
2479 != (inb(com->rsabase + rsa_srr) & 0xc9))
2480 possibly_more_intrs = TRUE;
2486 && (inb(com->int_id_port) & IIR_IMASK)
2489 possibly_more_intrs = TRUE;
2491 /* XXX COM_UNLOCK(); */
2493 } while (possibly_more_intrs);
2495 #endif /* COM_MULTIPORT */
2503 u_char modem_status;
2508 struct timecounter *tc;
2513 u_char rsa_buf_status = 0;
2514 int rsa_tx_fifo_size=0;
2518 int_ctl = inb(com->intr_ctl_port);
2519 int_ctl_new = int_ctl;
2521 while (!com->gone) {
2524 if (IS_8251(com->pc98_if_type)) {
2525 tmp = inb(com->sts_port);
2528 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2529 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2530 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2531 if (tmp & STS8251_PE) line_status |= LSR_PE;
2532 if (tmp & STS8251_OE) line_status |= LSR_OE;
2533 if (tmp & STS8251_FE) line_status |= LSR_FE;
2534 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2537 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2538 modem_status = inb(com->modem_status_port);
2539 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2541 count = tc->tc_get_timecount(tc);
2542 pps_event(&com->pps, tc, count,
2543 (modem_status & MSR_DCD) ?
2544 PPS_CAPTURECLEAR : PPS_CAPTUREASSERT);
2547 line_status = inb(com->line_status_port);
2550 if (com->pc98_if_type == COM_IF_RSA98III)
2551 rsa_buf_status = inb(com->rsabase + rsa_srr);
2554 /* input event? (check first to help avoid overruns) */
2556 while (line_status & LSR_RCV_MASK) {
2558 while ((line_status & LSR_RCV_MASK)
2559 || (com->pc98_if_type == COM_IF_RSA98III
2560 && (rsa_buf_status & 0x08))) {
2562 /* break/unnattached error bits or real input? */
2564 if (IS_8251(com->pc98_if_type)) {
2565 recv_data = inb(com->data_port);
2567 pc98_i8251_or_cmd(com,CMD8251_ER);
2573 if (com->pc98_if_type == COM_IF_RSA98III) {
2574 if (!(rsa_buf_status & 0x08))
2577 recv_data = inb(com->data_port);
2581 if (!(line_status & LSR_RXRDY))
2584 recv_data = inb(com->data_port);
2588 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2590 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2591 * Otherwise, push the work to a higher level
2592 * (to handle PARMRK) if we're bypassing.
2593 * Otherwise, convert BI/FE and PE+INPCK to 0.
2595 * This makes bypassing work right in the
2596 * usual "raw" case (IGNBRK set, and IGNPAR
2599 * Note: BI together with FE/PE means just BI.
2601 if (line_status & LSR_BI) {
2602 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2603 if (com->unit == comconsole) {
2609 || com->tp->t_iflag & IGNBRK)
2613 || com->tp->t_iflag & IGNPAR)
2616 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2617 && (line_status & (LSR_BI | LSR_FE)
2618 || com->tp->t_iflag & INPCK))
2622 if (com->hotchar != 0 && recv_data == com->hotchar)
2625 if (ioptr >= com->ibufend)
2626 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2628 if (com->do_timestamp)
2629 microtime(&com->timestamp);
2632 #if 0 /* for testing input latency vs efficiency */
2633 if (com->iptr - com->ibuf == 8)
2636 ioptr[0] = recv_data;
2637 ioptr[com->ierroff] = line_status;
2638 com->iptr = ++ioptr;
2639 if (ioptr == com->ihighwater
2640 && com->state & CS_RTS_IFLOW)
2642 if (IS_8251(com->pc98_if_type))
2643 com_tiocm_bic(com, TIOCM_RTS);
2646 outb(com->modem_ctl_port,
2647 com->mcr_image &= ~MCR_RTS);
2648 if (line_status & LSR_OE)
2649 CE_RECORD(com, CE_OVERRUN);
2653 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2654 * jump from the top of the loop to here
2657 if (IS_8251(com->pc98_if_type))
2661 line_status = inb(com->line_status_port) & 0x7F;
2663 if (com->pc98_if_type == COM_IF_RSA98III)
2664 rsa_buf_status = inb(com->rsabase + rsa_srr);
2668 /* modem status change? (always check before doing output) */
2670 if (!IS_8251(com->pc98_if_type)) {
2672 modem_status = inb(com->modem_status_port);
2673 if (modem_status != com->last_modem_status) {
2674 if (com->do_dcd_timestamp
2675 && !(com->last_modem_status & MSR_DCD)
2676 && modem_status & MSR_DCD)
2677 microtime(&com->dcd_timestamp);
2680 * Schedule high level to handle DCD changes. Note
2681 * that we don't use the delta bits anywhere. Some
2682 * UARTs mess them up, and it's easy to remember the
2683 * previous bits and calculate the delta.
2685 com->last_modem_status = modem_status;
2686 if (!(com->state & CS_CHECKMSR)) {
2687 com_events += LOTS_OF_EVENTS;
2688 com->state |= CS_CHECKMSR;
2692 /* handle CTS change immediately for crisp flow ctl */
2693 if (com->state & CS_CTS_OFLOW) {
2694 if (modem_status & MSR_CTS)
2695 com->state |= CS_ODEVREADY;
2697 com->state &= ~CS_ODEVREADY;
2704 /* output queued and everything ready? */
2706 if (line_status & LSR_TXRDY
2707 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2709 if (((com->pc98_if_type == COM_IF_RSA98III)
2710 ? (rsa_buf_status & 0x02)
2711 : (line_status & LSR_TXRDY))
2712 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2714 ioptr = com->obufq.l_head;
2715 if (com->tx_fifo_size > 1) {
2718 ocount = com->obufq.l_tail - ioptr;
2720 if (com->pc98_if_type == COM_IF_RSA98III) {
2721 rsa_buf_status = inb(com->rsabase + rsa_srr);
2722 rsa_tx_fifo_size = 1024;
2723 if (!(rsa_buf_status & 0x01))
2724 rsa_tx_fifo_size = 2048;
2725 if (ocount > rsa_tx_fifo_size)
2726 ocount = rsa_tx_fifo_size;
2729 if (ocount > com->tx_fifo_size)
2730 ocount = com->tx_fifo_size;
2731 com->bytes_out += ocount;
2733 outb(com->data_port, *ioptr++);
2734 while (--ocount != 0);
2736 outb(com->data_port, *ioptr++);
2740 if (IS_8251(com->pc98_if_type))
2741 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2742 com_int_Tx_enable(com);
2744 com->obufq.l_head = ioptr;
2745 if (COM_IIR_TXRDYBUG(com->flags)) {
2746 int_ctl_new = int_ctl | IER_ETXRDY;
2748 if (ioptr >= com->obufq.l_tail) {
2751 qp = com->obufq.l_next;
2752 qp->l_queued = FALSE;
2755 com->obufq.l_head = qp->l_head;
2756 com->obufq.l_tail = qp->l_tail;
2757 com->obufq.l_next = qp;
2759 /* output just completed */
2760 if ( COM_IIR_TXRDYBUG(com->flags) ) {
2761 int_ctl_new = int_ctl & ~IER_ETXRDY;
2763 com->state &= ~CS_BUSY;
2765 if (IS_8251(com->pc98_if_type))
2766 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2767 com_int_Tx_disable(com);
2770 if (!(com->state & CS_ODONE)) {
2771 com_events += LOTS_OF_EVENTS;
2772 com->state |= CS_ODONE;
2773 setsofttty(); /* handle at high level ASAP */
2776 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2778 if (com->pc98_if_type == COM_IF_RSA98III) {
2779 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2780 outb(com->intr_ctl_port, int_ctl_new);
2781 outb(com->rsabase + rsa_ier, 0x1d);
2784 outb(com->intr_ctl_port, int_ctl_new);
2788 else if (line_status & LSR_TXRDY) {
2789 if (IS_8251(com->pc98_if_type))
2790 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2791 com_int_Tx_disable(com);
2793 if (IS_8251(com->pc98_if_type))
2794 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2799 #ifndef COM_MULTIPORT
2801 if (IS_8251(com->pc98_if_type))
2804 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2805 #endif /* COM_MULTIPORT */
2811 sioioctl(dev, cmd, data, flag, p)
2824 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2826 struct termios term;
2830 com = com_addr(MINOR_TO_UNIT(mynor));
2833 iobase = com->iobase;
2834 if (mynor & CONTROL_MASK) {
2837 switch (mynor & CONTROL_MASK) {
2838 case CONTROL_INIT_STATE:
2839 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2841 case CONTROL_LOCK_STATE:
2842 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2845 return (ENODEV); /* /dev/nodev */
2852 *ct = *(struct termios *)data;
2855 *(struct termios *)data = *ct;
2858 *(int *)data = TTYDISC;
2861 bzero(data, sizeof(struct winsize));
2868 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2869 term = tp->t_termios;
2871 error = ttsetcompat(tp, &cmd, data, &term);
2875 data = (caddr_t)&term;
2877 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2879 struct termios *dt = (struct termios *)data;
2880 struct termios *lt = mynor & CALLOUT_MASK
2881 ? &com->lt_out : &com->lt_in;
2883 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2884 | (dt->c_iflag & ~lt->c_iflag);
2885 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2886 | (dt->c_oflag & ~lt->c_oflag);
2887 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2888 | (dt->c_cflag & ~lt->c_cflag);
2889 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2890 | (dt->c_lflag & ~lt->c_lflag);
2891 for (cc = 0; cc < NCCS; ++cc)
2892 if (lt->c_cc[cc] != 0)
2893 dt->c_cc[cc] = tp->t_cc[cc];
2894 if (lt->c_ispeed != 0)
2895 dt->c_ispeed = tp->t_ispeed;
2896 if (lt->c_ospeed != 0)
2897 dt->c_ospeed = tp->t_ospeed;
2899 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2900 if (error != ENOIOCTL)
2903 error = ttioctl(tp, cmd, data, flag);
2904 disc_optim(tp, &tp->t_termios, com);
2905 if (error != ENOIOCTL) {
2910 if (IS_8251(com->pc98_if_type)) {
2913 com_send_break_on( com );
2916 com_send_break_off( com );
2919 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
2922 com_tiocm_bic(com, TIOCM_DTR);
2925 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2926 * changes get undone on the next call to comparam().
2929 com_tiocm_set( com, *(int *)data );
2932 com_tiocm_bis( com, *(int *)data );
2935 com_tiocm_bic( com, *(int *)data );
2938 *(int *)data = com_tiocm_get(com);
2941 /* must be root since the wait applies to following logins */
2947 com->dtr_wait = *(int *)data * hz / 100;
2950 *(int *)data = com->dtr_wait * 100 / hz;
2953 com->do_timestamp = TRUE;
2954 *(struct timeval *)data = com->timestamp;
2956 case TIOCDCDTIMESTAMP:
2957 com->do_dcd_timestamp = TRUE;
2958 *(struct timeval *)data = com->dcd_timestamp;
2966 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2971 outb(iobase + (com_cfcr << port_shift),
2972 com->cfcr_image |= CFCR_SBREAK);
2974 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2979 outb(iobase + (com_cfcr << port_shift),
2980 com->cfcr_image &= ~CFCR_SBREAK);
2982 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2986 (void)commctl(com, TIOCM_DTR, DMBIS);
2989 (void)commctl(com, TIOCM_DTR, DMBIC);
2992 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2993 * changes get undone on the next call to comparam().
2996 (void)commctl(com, *(int *)data, DMSET);
2999 (void)commctl(com, *(int *)data, DMBIS);
3002 (void)commctl(com, *(int *)data, DMBIC);
3005 *(int *)data = commctl(com, 0, DMGET);
3008 /* must be root since the wait applies to following logins */
3014 com->dtr_wait = *(int *)data * hz / 100;
3017 *(int *)data = com->dtr_wait * 100 / hz;
3020 com->do_timestamp = TRUE;
3021 *(struct timeval *)data = com->timestamp;
3023 case TIOCDCDTIMESTAMP:
3024 com->do_dcd_timestamp = TRUE;
3025 *(struct timeval *)data = com->dcd_timestamp;
3029 error = pps_ioctl(cmd, data, &com->pps);
3030 if (error == ENODEV)
3046 if (com_events == 0)
3049 for (unit = 0; unit < NSIOTOT; ++unit) {
3054 com = com_addr(unit);
3058 if (tp == NULL || com->gone) {
3060 * Discard any events related to never-opened or
3061 * going-away devices.
3064 incc = com->iptr - com->ibuf;
3065 com->iptr = com->ibuf;
3066 if (com->state & CS_CHECKMSR) {
3067 incc += LOTS_OF_EVENTS;
3068 com->state &= ~CS_CHECKMSR;
3074 if (com->iptr != com->ibuf) {
3079 if (com->state & CS_CHECKMSR) {
3080 u_char delta_modem_status;
3083 if (!IS_8251(com->pc98_if_type)) {
3086 delta_modem_status = com->last_modem_status
3087 ^ com->prev_modem_status;
3088 com->prev_modem_status = com->last_modem_status;
3089 com_events -= LOTS_OF_EVENTS;
3090 com->state &= ~CS_CHECKMSR;
3092 if (delta_modem_status & MSR_DCD)
3093 (*linesw[tp->t_line].l_modem)
3094 (tp, com->prev_modem_status & MSR_DCD);
3099 if (com->state & CS_ODONE) {
3101 com_events -= LOTS_OF_EVENTS;
3102 com->state &= ~CS_ODONE;
3104 if (!(com->state & CS_BUSY)
3105 && !(com->extra_state & CSE_BUSYCHECK)) {
3106 timeout(siobusycheck, com, hz / 100);
3107 com->extra_state |= CSE_BUSYCHECK;
3109 (*linesw[tp->t_line].l_start)(tp);
3111 if (com_events == 0)
3114 if (com_events >= LOTS_OF_EVENTS)
3139 unit = DEV_TO_UNIT(tp->t_dev);
3140 com = com_addr(unit);
3141 iobase = com->iobase;
3142 if (IS_8251(com->pc98_if_type)) {
3143 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3145 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3147 /* do historical conversions */
3148 if (t->c_ispeed == 0)
3149 t->c_ispeed = t->c_ospeed;
3151 /* check requested parameters */
3152 divisor = ttspeedtab(t->c_ospeed,
3153 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3156 /* do historical conversions */
3157 if (t->c_ispeed == 0)
3158 t->c_ispeed = t->c_ospeed;
3160 /* check requested parameters */
3161 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3163 if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed)
3166 /* parameters are OK, convert them to the com struct and the device */
3168 unit = DEV_TO_UNIT(tp->t_dev);
3169 com = com_addr(unit);
3170 iobase = com->iobase;
3174 if (IS_8251(com->pc98_if_type)) {
3176 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3178 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3182 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3184 (void)commctl(com, TIOCM_DTR, DMBIS);
3190 if (!IS_8251(com->pc98_if_type)) {
3192 switch (cflag & CSIZE) {
3206 if (cflag & PARENB) {
3208 if (!(cflag & PARODD))
3214 if (com->hasfifo && divisor != 0) {
3216 * Use a fifo trigger level low enough so that the input
3217 * latency from the fifo is less than about 16 msec and
3218 * the total latency is less than about 30 msec. These
3219 * latencies are reasonable for humans. Serial comms
3220 * protocols shouldn't expect anything better since modem
3221 * latencies are larger.
3223 com->fifo_image = t->c_ospeed <= 4800
3224 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3227 * The Hayes ESP card needs the fifo DMA mode bit set
3228 * in compatibility mode. If not, it will interrupt
3229 * for each character received.
3232 com->fifo_image |= FIFO_DMA_MODE;
3235 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3237 outb(iobase + com_fifo, com->fifo_image);
3245 * This returns with interrupts disabled so that we can complete
3246 * the speed change atomically. Keeping interrupts disabled is
3247 * especially important while com_data is hidden.
3249 (void) siosetwater(com, t->c_ispeed);
3252 if (IS_8251(com->pc98_if_type))
3253 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3258 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3260 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3263 * Only set the divisor registers if they would change,
3264 * since on some 16550 incompatibles (UMC8669F), setting
3265 * them while input is arriving them loses sync until
3266 * data stops arriving.
3268 dlbl = divisor & 0xFF;
3270 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3271 outb(iobase + (com_dlbl << port_shift), dlbl);
3272 dlbh = (u_int) divisor >> 8;
3273 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3274 outb(iobase + (com_dlbh << port_shift), dlbh);
3276 if (inb(iobase + com_dlbl) != dlbl)
3277 outb(iobase + com_dlbl, dlbl);
3278 dlbh = (u_int) divisor >> 8;
3279 if (inb(iobase + com_dlbh) != dlbh)
3280 outb(iobase + com_dlbh, dlbh);
3287 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3289 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3292 if (!(tp->t_state & TS_TTSTOP))
3293 com->state |= CS_TTGO;
3295 if (cflag & CRTS_IFLOW) {
3296 if (com->st16650a) {
3297 outb(iobase + com_cfcr, 0xbf);
3298 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3300 com->state |= CS_RTS_IFLOW;
3302 * If CS_RTS_IFLOW just changed from off to on, the change
3303 * needs to be propagated to MCR_RTS. This isn't urgent,
3304 * so do it later by calling comstart() instead of repeating
3305 * a lot of code from comstart() here.
3307 } else if (com->state & CS_RTS_IFLOW) {
3308 com->state &= ~CS_RTS_IFLOW;
3310 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3311 * on here, since comstart() won't do it later.
3314 if (IS_8251(com->pc98_if_type))
3315 com_tiocm_bis(com, TIOCM_RTS);
3318 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3319 if (com->st16650a) {
3320 outb(iobase + com_cfcr, 0xbf);
3321 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3327 * Set up state to handle output flow control.
3328 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3329 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3331 com->state |= CS_ODEVREADY;
3332 com->state &= ~CS_CTS_OFLOW;
3334 if (com->pc98_if_type == COM_IF_RSA98III) {
3335 param = inb(com->rsabase + rsa_msr);
3336 outb(com->rsabase + rsa_msr, param & 0x14);
3339 if (cflag & CCTS_OFLOW) {
3340 com->state |= CS_CTS_OFLOW;
3342 if (IS_8251(com->pc98_if_type)) {
3343 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3344 com->state &= ~CS_ODEVREADY;
3348 if (com->pc98_if_type == COM_IF_RSA98III) {
3349 /* Set automatic flow control mode */
3350 outb(com->rsabase + rsa_msr, param | 0x08);
3353 if (!(com->last_modem_status & MSR_CTS))
3354 com->state &= ~CS_ODEVREADY;
3355 if (com->st16650a) {
3356 outb(iobase + com_cfcr, 0xbf);
3357 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3363 if (com->st16650a) {
3364 outb(iobase + com_cfcr, 0xbf);
3365 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3371 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3373 outb(iobase + com_cfcr, com->cfcr_image);
3377 /* XXX shouldn't call functions while intrs are disabled. */
3378 disc_optim(tp, t, com);
3380 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3381 * unconditionally, but that defeated the careful discarding of
3382 * stale input in sioopen().
3384 if (com->state >= (CS_BUSY | CS_TTGO))
3390 if (com->ibufold != NULL) {
3391 free(com->ibufold, M_DEVBUF);
3392 com->ibufold = NULL;
3398 siosetwater(com, speed)
3408 * Make the buffer size large enough to handle a softtty interrupt
3409 * latency of about 2 ticks without loss of throughput or data
3410 * (about 3 ticks if input flow control is not used or not honoured,
3411 * but a bit less for CS5-CS7 modes).
3413 cp4ticks = speed / 10 / hz * 4;
3414 for (ibufsize = 128; ibufsize < cp4ticks;)
3417 if (com->pc98_if_type == COM_IF_RSA98III)
3420 if (ibufsize == com->ibufsize) {
3426 * Allocate input buffer. The extra factor of 2 in the size is
3427 * to allow for an error byte for each input byte.
3429 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3435 /* Initialize non-critical variables. */
3436 com->ibufold = com->ibuf;
3437 com->ibufsize = ibufsize;
3440 tp->t_ififosize = 2 * ibufsize;
3441 tp->t_ispeedwat = (speed_t)-1;
3442 tp->t_ospeedwat = (speed_t)-1;
3446 * Read current input buffer, if any. Continue with interrupts
3450 if (com->iptr != com->ibuf)
3454 * Initialize critical variables, including input buffer watermarks.
3455 * The external device is asked to stop sending when the buffer
3456 * exactly reaches high water, or when the high level requests it.
3457 * The high level is notified immediately (rather than at a later
3458 * clock tick) when this watermark is reached.
3459 * The buffer size is chosen so the watermark should almost never
3461 * The low watermark is invisibly 0 since the buffer is always
3462 * emptied all at once.
3464 com->iptr = com->ibuf = ibuf;
3465 com->ibufend = ibuf + ibufsize;
3466 com->ierroff = ibufsize;
3467 com->ihighwater = ibuf + 3 * ibufsize / 4;
3482 unit = DEV_TO_UNIT(tp->t_dev);
3483 com = com_addr(unit);
3486 if (tp->t_state & TS_TTSTOP)
3487 com->state &= ~CS_TTGO;
3489 com->state |= CS_TTGO;
3490 if (tp->t_state & TS_TBLOCK) {
3492 if (IS_8251(com->pc98_if_type))
3493 tmp = com_tiocm_get(com) & TIOCM_RTS;
3495 tmp = com->mcr_image & MCR_RTS;
3496 if (tmp && (com->state & CS_RTS_IFLOW))
3498 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3501 if (IS_8251(com->pc98_if_type))
3502 com_tiocm_bic(com, TIOCM_RTS);
3505 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3508 if (IS_8251(com->pc98_if_type))
3509 tmp = com_tiocm_get(com) & TIOCM_RTS;
3511 tmp = com->mcr_image & MCR_RTS;
3512 if (!(tmp) && com->iptr < com->ihighwater
3513 && com->state & CS_RTS_IFLOW)
3515 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3516 && com->state & CS_RTS_IFLOW)
3519 if (IS_8251(com->pc98_if_type))
3520 com_tiocm_bis(com, TIOCM_RTS);
3523 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3526 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3529 /* if(IS_8251(com->pc98_if_type))
3530 com_int_Tx_enable(com); */
3535 if (tp->t_outq.c_cc != 0) {
3539 if (!com->obufs[0].l_queued) {
3540 com->obufs[0].l_tail
3541 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3547 com->obufs[0].l_next = NULL;
3548 com->obufs[0].l_queued = TRUE;
3550 if (com->state & CS_BUSY) {
3551 qp = com->obufq.l_next;
3552 while ((next = qp->l_next) != NULL)
3554 qp->l_next = &com->obufs[0];
3556 com->obufq.l_head = com->obufs[0].l_head;
3557 com->obufq.l_tail = com->obufs[0].l_tail;
3558 com->obufq.l_next = &com->obufs[0];
3559 com->state |= CS_BUSY;
3563 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3564 com->obufs[1].l_tail
3565 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3571 com->obufs[1].l_next = NULL;
3572 com->obufs[1].l_queued = TRUE;
3574 if (com->state & CS_BUSY) {
3575 qp = com->obufq.l_next;
3576 while ((next = qp->l_next) != NULL)
3578 qp->l_next = &com->obufs[1];
3580 com->obufq.l_head = com->obufs[1].l_head;
3581 com->obufq.l_tail = com->obufs[1].l_tail;
3582 com->obufq.l_next = &com->obufs[1];
3583 com->state |= CS_BUSY;
3587 tp->t_state |= TS_BUSY;
3590 if (com->state >= (CS_BUSY | CS_TTGO))
3591 siointr1(com); /* fake interrupt to start output */
3594 /* if(IS_8251(com->pc98_if_type))
3595 com_int_Tx_enable(com); */
3612 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3616 if (!IS_8251(com->pc98_if_type))
3617 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3623 /* XXX avoid h/w bug. */
3627 outb(com->iobase + (com_fifo << port_shift),
3628 FIFO_XMT_RST | com->fifo_image);
3629 if (com->pc98_if_type == COM_IF_RSA98III)
3630 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3631 outb(com->iobase + (com_fifo << port_shift),
3632 FIFO_XMT_RST | com->fifo_image);
3634 outb(com->iobase + com_fifo,
3635 FIFO_XMT_RST | com->fifo_image);
3637 com->obufs[0].l_queued = FALSE;
3638 com->obufs[1].l_queued = FALSE;
3639 if (com->state & CS_ODONE)
3640 com_events -= LOTS_OF_EVENTS;
3641 com->state &= ~(CS_ODONE | CS_BUSY);
3642 com->tp->t_state &= ~TS_BUSY;
3647 /* XXX avoid h/w bug. */
3651 if (com->pc98_if_type == COM_IF_RSA98III) {
3652 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3653 inb(com->data_port);
3655 outb(com->iobase + (com_fifo << port_shift),
3656 FIFO_RCV_RST | com->fifo_image);
3658 outb(com->iobase + com_fifo,
3659 FIFO_RCV_RST | com->fifo_image);
3661 com_events -= (com->iptr - com->ibuf);
3662 com->iptr = com->ibuf;
3676 if (mynor & CONTROL_MASK)
3678 unit = MINOR_TO_UNIT(mynor);
3679 if ((u_int) unit >= NSIOTOT)
3681 return (&sio_tty[unit]);
3685 commctl(com, bits, how)
3694 bits = TIOCM_LE; /* XXX - always enabled while open */
3695 mcr = com->mcr_image;
3700 msr = com->prev_modem_status;
3708 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3709 * more volatile by reading the modem status a lot. Perhaps
3710 * we should latch both bits until the status is read here.
3712 if (msr & (MSR_RI | MSR_TERI))
3717 if (bits & TIOCM_DTR)
3719 if (bits & TIOCM_RTS)
3726 outb(com->modem_ctl_port,
3727 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3730 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3733 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3748 * Set our timeout period to 1 second if no polled devices are open.
3749 * Otherwise set it to max(1/200, 1/hz).
3750 * Enable timeouts iff some device is open.
3752 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3755 for (unit = 0; unit < NSIOTOT; ++unit) {
3756 com = com_addr(unit);
3757 if (com != NULL && com->tp != NULL
3758 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3760 if (com->poll || com->poll_output) {
3761 sio_timeout = hz > 200 ? hz / 200 : 1;
3767 sio_timeouts_until_log = hz / sio_timeout;
3768 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3771 /* Flush error messages, if any. */
3772 sio_timeouts_until_log = 1;
3773 comwakeup((void *)NULL);
3774 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3785 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3788 * Recover from lost output interrupts.
3789 * Poll any lines that don't use interrupts.
3791 for (unit = 0; unit < NSIOTOT; ++unit) {
3792 com = com_addr(unit);
3793 if (com != NULL && !com->gone
3794 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3802 * Check for and log errors, but not too often.
3804 if (--sio_timeouts_until_log > 0)
3806 sio_timeouts_until_log = hz / sio_timeout;
3807 for (unit = 0; unit < NSIOTOT; ++unit) {
3810 com = com_addr(unit);
3815 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3820 delta = com->delta_error_counts[errnum];
3821 com->delta_error_counts[errnum] = 0;
3825 total = com->error_counts[errnum] += delta;
3826 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3827 unit, delta, error_desc[errnum],
3828 delta == 1 ? "" : "s", total);
3834 /* commint is called when modem control line changes */
3838 register struct tty *tp;
3844 unit = MINOR_TO_UNIT(mynor);
3845 com = com_addr(unit);
3848 stat = com_tiocm_get(com);
3849 delta = com_tiocm_get_delta(com);
3851 if (com->state & CS_CTS_OFLOW) {
3852 if (stat & TIOCM_CTS)
3853 com->state |= CS_ODEVREADY;
3855 com->state &= ~CS_ODEVREADY;
3857 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3858 if (stat & TIOCM_CAR )
3859 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
3860 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
3861 /* negate DTR, RTS */
3862 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3863 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3864 /* disable IENABLE */
3865 com_int_TxRx_disable( com );
3872 disc_optim(tp, t, com)
3877 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
3878 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
3879 && (!(t->c_iflag & PARMRK)
3880 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
3881 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
3882 && linesw[tp->t_line].l_rint == ttyinput)
3883 tp->t_state |= TS_CAN_BYPASS_L_RINT;
3885 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
3886 com->hotchar = linesw[tp->t_line].l_hotchar;
3890 * Following are all routines needed for SIO to act as console
3892 #include <sys/cons.h>
3902 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3903 static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
3904 static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
3905 static void siocntxwait __P((Port_t iobase));
3908 static cn_probe_t siocnprobe;
3909 static cn_init_t siocninit;
3910 static cn_checkc_t siocncheckc;
3911 static cn_getc_t siocngetc;
3912 static cn_putc_t siocnputc;
3914 CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, siocnputc);
3916 /* To get the GDB related variables */
3918 #include <ddb/ddb.h>
3929 * Wait for any pending transmission to finish. Required to avoid
3930 * the UART lockup bug when the speed is changed, and for normal
3934 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3935 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3940 * Read the serial port specified and try to figure out what speed
3941 * it's currently running at. We're assuming the serial port has
3942 * been initialized and is basicly idle. This routine is only intended
3943 * to be run at system startup.
3945 * If the value read from the serial port doesn't make sense, return 0.
3949 siocngetspeed(iobase, table)
3951 struct speedtab *table;
3958 cfcr = inb(iobase + com_cfcr);
3959 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3961 dlbl = inb(iobase + com_dlbl);
3962 dlbh = inb(iobase + com_dlbh);
3964 outb(iobase + com_cfcr, cfcr);
3966 code = dlbh << 8 | dlbl;
3968 for ( ; table->sp_speed != -1; table++)
3969 if (table->sp_code == code)
3970 return (table->sp_speed);
3972 return 0; /* didn't match anything sane */
3976 siocnopen(sp, iobase, speed)
3977 struct siocnstate *sp;
3986 * Save all the device control registers except the fifo register
3987 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3988 * We can't save the fifo register since it is read-only.
3990 sp->ier = inb(iobase + com_ier);
3991 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3992 siocntxwait(iobase);
3993 sp->cfcr = inb(iobase + com_cfcr);
3994 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3995 sp->dlbl = inb(iobase + com_dlbl);
3996 sp->dlbh = inb(iobase + com_dlbh);
3998 * Only set the divisor registers if they would change, since on
3999 * some 16550 incompatibles (Startech), setting them clears the
4000 * data input register. This also reduces the effects of the
4003 divisor = ttspeedtab(speed, comspeedtab);
4004 dlbl = divisor & 0xFF;
4005 if (sp->dlbl != dlbl)
4006 outb(iobase + com_dlbl, dlbl);
4007 dlbh = (u_int) divisor >> 8;
4008 if (sp->dlbh != dlbh)
4009 outb(iobase + com_dlbh, dlbh);
4010 outb(iobase + com_cfcr, CFCR_8BITS);
4011 sp->mcr = inb(iobase + com_mcr);
4013 * We don't want interrupts, but must be careful not to "disable"
4014 * them by clearing the MCR_IENABLE bit, since that might cause
4015 * an interrupt by floating the IRQ line.
4017 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4021 siocnclose(sp, iobase)
4022 struct siocnstate *sp;
4026 * Restore the device control registers.
4028 siocntxwait(iobase);
4029 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4030 if (sp->dlbl != inb(iobase + com_dlbl))
4031 outb(iobase + com_dlbl, sp->dlbl);
4032 if (sp->dlbh != inb(iobase + com_dlbh))
4033 outb(iobase + com_dlbh, sp->dlbh);
4034 outb(iobase + com_cfcr, sp->cfcr);
4036 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4038 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4039 outb(iobase + com_ier, sp->ier);
4052 struct siocnstate sp;
4055 * Find our first enabled console, if any. If it is a high-level
4056 * console device, then initialize it and return successfully.
4057 * If it is a low-level console device, then initialize it and
4058 * return unsuccessfully. It must be initialized in both cases
4059 * for early use by console drivers and debuggers. Initializing
4060 * the hardware is not necessary in all cases, since the i/o
4061 * routines initialize it on the fly, but it is necessary if
4062 * input might arrive while the hardware is switched back to an
4063 * uninitialized state. We can't handle multiple console devices
4064 * yet because our low-level routines don't take a device arg.
4065 * We trust the user to set the console flags properly so that we
4066 * don't need to probe.
4068 cp->cn_pri = CN_DEAD;
4070 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4072 if (resource_int_value("sio", unit, "flags", &flags))
4074 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4078 if (resource_int_value("sio", unit, "port", &port))
4082 if (boothowto & RB_SERIAL) {
4083 boot_speed = siocngetspeed(iobase, comspeedtab);
4085 comdefaultrate = boot_speed;
4089 * Initialize the divisor latch. We can't rely on
4090 * siocnopen() to do this the first time, since it
4091 * avoids writing to the latch if the latch appears
4092 * to have the correct value. Also, if we didn't
4093 * just read the speed from the hardware, then we
4094 * need to set the speed in hardware so that
4095 * switching it later is null.
4097 cfcr = inb(iobase + com_cfcr);
4098 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4099 outb(iobase + com_dlbl,
4100 COMBRD(comdefaultrate) & 0xff);
4101 outb(iobase + com_dlbh,
4102 (u_int) COMBRD(comdefaultrate) >> 8);
4103 outb(iobase + com_cfcr, cfcr);
4105 siocnopen(&sp, iobase, comdefaultrate);
4108 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4109 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4110 cp->cn_pri = COM_FORCECONSOLE(flags)
4111 || boothowto & RB_SERIAL
4112 ? CN_REMOTE : CN_NORMAL;
4113 printf("sio%d: system console\n", unit);
4114 siocniobase = iobase;
4117 if (COM_DEBUGGER(flags) && !COM_LLCONSOLE(flags)) {
4118 printf("sio%d: gdb debugging port\n", unit);
4119 siogdbiobase = iobase;
4123 gdbdev = makedev(CDEV_MAJOR, unit);
4124 gdb_getc = siocngetc;
4125 gdb_putc = siocnputc;
4134 * XXX Ugly Compatability.
4135 * If no gdb port has been specified, set it to be the console
4136 * as some configuration files don't specify the gdb port.
4138 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
4139 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
4141 printf("Set flag 0x80 on desired GDB port in your\n");
4142 printf("configuration file (currently sio only).\n");
4143 siogdbiobase = siocniobase;
4144 siogdbunit = siocnunit;
4145 gdbdev = makedev(CDEV_MAJOR, siocnunit);
4146 gdb_getc = siocngetc;
4147 gdb_putc = siocnputc;
4155 struct consdev siocons = {
4156 NULL, NULL, siocngetc, siocncheckc, siocnputc,
4160 extern struct consdev *cn_tab;
4163 siocnattach(port, speed)
4169 struct siocnstate sp;
4172 comdefaultrate = speed;
4177 * Initialize the divisor latch. We can't rely on
4178 * siocnopen() to do this the first time, since it
4179 * avoids writing to the latch if the latch appears
4180 * to have the correct value. Also, if we didn't
4181 * just read the speed from the hardware, then we
4182 * need to set the speed in hardware so that
4183 * switching it later is null.
4185 cfcr = inb(siocniobase + com_cfcr);
4186 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4187 outb(siocniobase + com_dlbl,
4188 COMBRD(comdefaultrate) & 0xff);
4189 outb(siocniobase + com_dlbh,
4190 (u_int) COMBRD(comdefaultrate) >> 8);
4191 outb(siocniobase + com_cfcr, cfcr);
4193 siocnopen(&sp, siocniobase, comdefaultrate);
4196 siocons.cn_dev = makedev(CDEV_MAJOR, 0);
4202 siogdbattach(port, speed)
4208 struct siocnstate sp;
4210 siogdbiobase = port;
4211 gdbdefaultrate = speed;
4216 * Initialize the divisor latch. We can't rely on
4217 * siocnopen() to do this the first time, since it
4218 * avoids writing to the latch if the latch appears
4219 * to have the correct value. Also, if we didn't
4220 * just read the speed from the hardware, then we
4221 * need to set the speed in hardware so that
4222 * switching it later is null.
4224 cfcr = inb(siogdbiobase + com_cfcr);
4225 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4226 outb(siogdbiobase + com_dlbl,
4227 COMBRD(gdbdefaultrate) & 0xff);
4228 outb(siogdbiobase + com_dlbh,
4229 (u_int) COMBRD(gdbdefaultrate) >> 8);
4230 outb(siogdbiobase + com_cfcr, cfcr);
4232 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4247 comconsole = DEV_TO_UNIT(cp->cn_dev);
4260 struct siocnstate sp;
4262 if (minor(dev) == siogdbunit)
4263 iobase = siogdbiobase;
4265 iobase = siocniobase;
4267 siocnopen(&sp, iobase, comdefaultrate);
4268 if (inb(iobase + com_lsr) & LSR_RXRDY)
4269 c = inb(iobase + com_data);
4272 siocnclose(&sp, iobase);
4285 struct siocnstate sp;
4287 if (minor(dev) == siogdbunit)
4288 iobase = siogdbiobase;
4290 iobase = siocniobase;
4292 siocnopen(&sp, iobase, comdefaultrate);
4293 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4295 c = inb(iobase + com_data);
4296 siocnclose(&sp, iobase);
4307 struct siocnstate sp;
4310 if (minor(dev) == siogdbunit)
4311 iobase = siogdbiobase;
4313 iobase = siocniobase;
4315 siocnopen(&sp, iobase, comdefaultrate);
4316 siocntxwait(iobase);
4317 outb(iobase + com_data, c);
4318 siocnclose(&sp, iobase);
4329 struct siocnstate sp;
4331 iobase = siogdbiobase;
4333 siocnopen(&sp, iobase, gdbdefaultrate);
4334 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4336 c = inb(iobase + com_data);
4337 siocnclose(&sp, iobase);
4347 struct siocnstate sp;
4350 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4351 siocntxwait(siogdbiobase);
4352 outb(siogdbiobase + com_data, c);
4353 siocnclose(&sp, siogdbiobase);
4360 * support PnP cards if we are using 'em
4365 static pnpid_t siopnp_ids[] = {
4366 { 0x5015f435, "MOT1550"},
4367 { 0x8113b04e, "Supra1381"},
4368 { 0x9012b04e, "Supra1290"},
4369 { 0x7121b04e, "SupraExpress 56i Sp"},
4370 { 0x11007256, "USR0011"},
4371 { 0x30207256, "USR2030"},
4372 { 0x31307256, "USR3031"},
4373 { 0x90307256, "USR3090"},
4374 { 0x0100440e, "Cardinal MVP288IV"},
4378 static char *siopnp_probe(u_long csn, u_long vend_id);
4379 static void siopnp_attach(u_long csn, u_long vend_id, char *name,
4380 struct isa_device *dev);
4381 static u_long nsiopnp = NSIO;
4383 static struct pnp_device siopnp = {
4390 DATA_SET (pnpdevice_set, siopnp);
4393 siopnp_probe(u_long csn, u_long vend_id)
4398 for(id = siopnp_ids; id->vend_id != 0; id++) {
4399 if (vend_id == id->vend_id) {
4407 read_pnp_parms(&d, 0);
4408 if (d.enable == 0 || d.flags & 1) {
4409 printf("CSN %lu is disabled.\n", csn);
4419 siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4423 if (dev->id_unit >= NSIOTOT)
4426 if (read_pnp_parms(&d, 0) == 0) {
4427 printf("failed to read pnp parms\n");
4431 write_pnp_parms(&d, 0);
4435 dev->id_iobase = d.port[0];
4436 dev->id_irq = (1 << d.irq[0]);
4437 dev->id_ointr = siointr;
4438 dev->id_ri_flags = RI_FAST;
4441 if (dev->id_driver == NULL) {
4442 dev->id_driver = &siodriver;
4443 dev->id_id = isa_compat_nextid();
4446 if ((dev->id_alive = sioprobe(dev)) != 0)
4449 printf("sio%d: probe failed\n", dev->id_unit);
4453 DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass, sio_cdevsw, 0, 0);
4457 * pc98 local function
4461 com_tiocm_set(struct com_s *com, int msr)
4465 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4468 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4469 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4470 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4471 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4472 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4473 pc98_i8251_clear_or_cmd( com, mask, tmp );
4478 com_tiocm_bis(struct com_s *com, int msr)
4484 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4485 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4486 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4487 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4489 pc98_i8251_or_cmd( com, tmp );
4494 com_tiocm_bic(struct com_s *com, int msr)
4500 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4501 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4502 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4504 pc98_i8251_clear_cmd( com, tmp );
4509 com_tiocm_get(struct com_s *com)
4511 return( com->pc98_prev_modem_status );
4515 com_tiocm_get_delta(struct com_s *com)
4519 tmp = com->pc98_modem_delta;
4520 com->pc98_modem_delta = 0;
4524 /* convert to TIOCM_?? ( ioctl.h ) */
4526 pc98_get_modem_status(struct com_s *com)
4531 stat = inb(com->sts_port);
4532 stat2 = inb(com->in_modem_port);
4533 msr = com->pc98_prev_modem_status
4534 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4535 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4536 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4537 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4538 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4539 #if COM_CARRIER_DETECT_EMULATE
4540 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4548 pc98_check_msr(void* chan)
4552 register struct tty *tp;
4560 unit = MINOR_TO_UNIT(mynor);
4561 com = com_addr(unit);
4565 msr = pc98_get_modem_status(com);
4566 /* make change flag */
4567 delta = msr ^ com->pc98_prev_modem_status;
4568 if ( delta & TIOCM_CAR ) {
4569 if ( com->modem_car_chg_timer ) {
4570 if ( -- com->modem_car_chg_timer )
4573 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4574 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4578 com->modem_car_chg_timer = 0;
4579 delta = ( msr ^ com->pc98_prev_modem_status ) &
4580 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4581 com->pc98_prev_modem_status = msr;
4582 delta = ( com->pc98_modem_delta |= delta );
4584 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4588 timeout(pc98_check_msr, (caddr_t)dev,
4589 PC98_CHECK_MODEM_INTERVAL);
4591 com->modem_checking = 0;
4596 pc98_msrint_start(dev_t dev)
4604 unit = MINOR_TO_UNIT(mynor);
4605 com = com_addr(unit);
4606 /* modem control line check routine envoke interval is 1/10 sec */
4607 if ( com->modem_checking == 0 ) {
4608 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4609 com->pc98_modem_delta = 0;
4610 timeout(pc98_check_msr, (caddr_t)dev,
4611 PC98_CHECK_MODEM_INTERVAL);
4612 com->modem_checking = 1;
4618 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4620 /* disable interrupt */
4623 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4625 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4626 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4631 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4636 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4637 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4642 pc98_check_i8251_interrupt(struct com_s *com)
4644 return ( com->intr_enable & 0x07 );
4648 pc98_i8251_clear_cmd(struct com_s *com, int x)
4653 tmp = com->pc98_prev_siocmd & ~(x);
4654 outb(com->cmd_port, tmp);
4655 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4660 pc98_i8251_or_cmd(struct com_s *com, int x)
4665 tmp = com->pc98_prev_siocmd | (x);
4666 outb(com->cmd_port, tmp);
4667 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4672 pc98_i8251_set_cmd(struct com_s *com, int x)
4678 outb(com->cmd_port, tmp);
4679 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4684 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4688 tmp = com->pc98_prev_siocmd & ~(clr);
4690 outb(com->cmd_port, tmp);
4691 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4696 pc98_i8251_get_cmd(struct com_s *com)
4698 return com->pc98_prev_siocmd;
4702 pc98_i8251_get_mod(struct com_s *com)
4704 return com->pc98_prev_siomod;
4708 pc98_i8251_reset(struct com_s *com, int mode, int command)
4710 outb(com->cmd_port, 0); /* dummy */
4712 outb(com->cmd_port, 0); /* dummy */
4714 outb(com->cmd_port, 0); /* dummy */
4716 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4718 outb(com->cmd_port, mode ); /* mode register */
4719 com->pc98_prev_siomod = mode;
4721 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4725 pc98_check_sysclock(void)
4727 /* get system clock from port */
4728 if ( pc98_machine_type & M_8M ) {
4729 /* 8 MHz system & H98 */
4738 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4743 count = pc98_ttspeedtab( com, speed );
4744 if ( count < 0 ) return;
4746 previnterrupt = pc98_check_i8251_interrupt(com);
4747 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4749 switch ( cflag&CSIZE ) {
4751 cfcr = MOD8251_5BITS; break;
4753 cfcr = MOD8251_6BITS; break;
4755 cfcr = MOD8251_7BITS; break;
4757 cfcr = MOD8251_8BITS; break;
4759 if ( cflag&PARENB ) {
4761 cfcr |= MOD8251_PODD;
4763 cfcr |= MOD8251_PEVEN;
4765 cfcr |= MOD8251_PDISAB;
4768 cfcr |= MOD8251_STOP2;
4770 cfcr |= MOD8251_STOP1;
4772 if ( count & 0x10000 )
4773 cfcr |= MOD8251_CLKX1;
4775 cfcr |= MOD8251_CLKX16;
4777 if (epson_machine_id != 0x20) { /* XXX */
4779 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4782 /* set baud rate from ospeed */
4783 pc98_set_baud_rate( com, count );
4785 if ( cfcr != pc98_i8251_get_mod(com) )
4786 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4788 pc98_enable_i8251_interrupt( com, previnterrupt );
4792 pc98_ttspeedtab(struct com_s *com, int speed)
4794 int if_type, effect_sp, count = -1, mod;
4796 if_type = com->pc98_if_type & 0x0f;
4798 switch (com->pc98_if_type) {
4799 case COM_IF_INTERNAL:
4800 if (PC98SIO_baud_rate_port(if_type) != -1) {
4801 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4803 count |= COM1_EXT_CLOCK;
4808 /* for *1CLK asynchronous! mode, TEFUTEFU */
4809 mod = (sysclock == 5) ? 2457600 : 1996800;
4810 effect_sp = ttspeedtab( speed, pc98speedtab );
4811 if ( effect_sp < 0 ) /* XXX */
4812 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4813 if ( effect_sp <= 0 )
4815 if ( effect_sp == speed )
4817 if ( mod % effect_sp )
4819 count = mod / effect_sp;
4820 if ( count > 65535 )
4822 if ( effect_sp != speed )
4825 case COM_IF_PC9861K_1:
4826 case COM_IF_PC9861K_2:
4829 case COM_IF_IND_SS_1:
4830 case COM_IF_IND_SS_2:
4831 case COM_IF_PIO9032B_1:
4832 case COM_IF_PIO9032B_2:
4833 if ( speed == 0 ) return 0;
4834 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4836 case COM_IF_B98_01_1:
4837 case COM_IF_B98_01_2:
4838 if ( speed == 0 ) return 0;
4839 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4841 if (count == 0 || count == 1) {
4843 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4853 pc98_set_baud_rate( struct com_s *com, int count )
4857 if_type = com->pc98_if_type & 0x0f;
4858 io = com->iobase & 0xff00;
4860 switch (com->pc98_if_type) {
4861 case COM_IF_INTERNAL:
4862 if (PC98SIO_baud_rate_port(if_type) != -1) {
4863 if (count & COM1_EXT_CLOCK) {
4864 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4867 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4872 printf( "[ Illegal count : %d ]", count );
4874 } else if ( count == 0 )
4883 outb( 0x75, count & 0xff );
4885 outb( 0x75, (count >> 8) & 0xff );
4888 case COM_IF_IND_SS_1:
4889 case COM_IF_IND_SS_2:
4890 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4891 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4892 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4893 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4894 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4896 case COM_IF_PIO9032B_1:
4897 case COM_IF_PIO9032B_2:
4898 outb(io | PC98SIO_baud_rate_port(if_type), count);
4900 case COM_IF_B98_01_1:
4901 case COM_IF_B98_01_2:
4902 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4905 * Some old B98_01 board should be controlled
4906 * in different way, but this hasn't been tested yet.
4908 outb(io | PC98SIO_func_port(if_type),
4909 (count & 0x20000) ? 0xf0 : 0xf2);
4915 pc98_check_if_type(device_t dev, struct siodev *iod)
4917 int irr, io, if_type, tmp;
4918 static short irq_tab[2][8] = {
4919 { 3, 5, 6, 9, 10, 12, 13, -1},
4920 { 3, 10, 12, 13, 5, 6, 9, -1}
4923 iod->if_type = if_type = (isa_get_flags(dev) >> 24) & 0xff;
4924 if ((if_type < 0 || if_type > COM_IF_END1) &&
4925 (if_type < 0x10 || if_type > COM_IF_END2))
4929 io = isa_get_port(dev) & 0xff00;
4931 if (IS_8251(iod->if_type)) {
4932 if (PC98SIO_func_port(if_type) != -1) {
4933 outb(io | PC98SIO_func_port(if_type), 0xf2);
4934 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4935 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4936 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4939 iod->cmd = io | PC98SIO_cmd_port(if_type);
4940 iod->sts = io | PC98SIO_sts_port(if_type);
4941 iod->mod = io | PC98SIO_in_modem_port(if_type);
4942 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4944 if (iod->if_type == COM_IF_INTERNAL) {
4947 /* XXX check new internal port. */
4950 for (tmp = 0; tmp < 100; tmp++) {
4951 if ((inb(0x13a) & 0x80) == 0) {
4952 PC98SIO_baud_rate_port(if_type) = 0x13a;
4953 if_8251_type[if_type].name = " (internal fast)";
4954 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4960 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4961 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4962 iod->irq = irq_tab[0][tmp];
4964 iod->irq = irq_tab[1][tmp];
4967 irr = if_16550a_type[if_type].irr_read;
4968 #ifdef COM_MULTIPORT
4969 if (!COM_ISMULTIPORT(isa_get_flags(dev)) ||
4970 device_get_unit(dev) == COM_MPMASTER(isa_get_flags(dev)))
4973 tmp = inb(io | irr);
4974 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4975 iod->irq = irq_tab[1][tmp >> 3];
4977 iod->irq = irq_tab[0][tmp & 0x07];
4980 if ( iod->irq == -1 ) return -1;
4985 pc98_set_ioport( struct com_s *com, int id_flags )
4989 if_type = (id_flags >> 24) & 0xff;
4990 if (IS_8251(if_type)) {
4991 pc98_check_sysclock();
4992 io = com->iobase & 0xff00;
4993 com->pc98_if_type = if_type;
4995 com->data_port = io | PC98SIO_data_port(if_type);
4996 com->cmd_port = io | PC98SIO_cmd_port(if_type);
4997 com->sts_port = io | PC98SIO_sts_port(if_type);
4998 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
4999 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5005 #endif /* PC98 defined */